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I have two OPI3 LTS in service that were locking up approx every 24 hours. I disabled CEC (under peripherals) and its been several weeks without a lockup now.

Glad its working for you now! Hopefully the CEC issue will get fixed eventually.

Can any of you with CEC issues try if devmem 0x3001b10 32 0x80000000 helps? There is basically no HW connection between CEC and video decoding except one clock, but that shouldn't matter since clock rate isn't changed by CEC driver.

I re-enabled CEC on one of my OP3LTS and executed that devmem command. I will post updates on what happens.

On the topic of CEC, for my own curiosity as a tinkerer, where can i find more information and/or block diagrams on how CEC is implemented on these Allwinner beasts?

What confuses me is that when enabling CEC i get the message about connecting to the "pulse-eight CEC adapter". But google seems to indicate that a "pulse-eight CEC adapter" is a small external physical black box. Is the same decoding chip inside that black box embedded on the OPI's circuit board? Or does the CEC pin from the HDMI connector wired directly to a pin on the allwinner SOC? Does the SOC have some sort of hardware CEC decoder, or is it all done in software as a driver/KO/addon?

I asked a question about this on the http://github.com/Pulse-Eight/libcec forum once, and they claimed their driver only supports the PulseEight branded hardware, and the Broadcom SOCs used in Rpi, but not allwinner. I'm confused...

As always, thank you to the developers for your work and education!

Well, documentation is scattered around. You need board schematic, which can be found on orangepi.org. Then you will probably want to see Allwinner H6 user manual, which can be found on linux-sunxi.org. Last but not least, you'll want to see CEC registers description. Unfortunately, you have to get creative here and find leaked DW HDMI documentation.

In any case, none of that will tell you anything about Pulse Eight adapter. You have to approach that one from Kodi perspective. Pulse Eight libcec library was first attempt at trying to make standard CEC library which can be used by applications. At that time, there were absolutely no standard kernel interface for CEC, so every device and SoC manufacturer did something hackish and incompatible with other solutions, even if same underlying HW was used. As you can imagine, Kodi used that to have any hope of supporting CEC on multiple devices. Later on, when Linux kernel finally got common CEC interface, Pulse Eight libcec library was extended to support this interface. Since Allwinner SoCs expose CEC functionality over this common kernel CEC interface, Pulse Eight library naturally also supports Allwinner SoCs (when using mainline kernel).

There is idea to get rid of Pulse Eight libcec dependency and use Linux CEC interface directly, but it's a lot of work that currently nobody wants to do.

tysm for this explanation!

i re-enabled CEC, rebooted, then executed the devmem command via SSH.

Its been running for over 24hrs with no lockups. That's not long enough to be conclusive yet, but its a very good sign!

If this ends up being the solution, will I need to put that devmem command into a startup script?

Thanks again,

But does CEC work? Please test that. There is a reason why that register is set differently. In any case, devmem command could only be workaround, but not a solution. It needs to be solved on kernel level. However, I always had troubles even with original OrangePi 3, so there might be connection, HW wise. It's interesting that I never had any troubles with Tanix TX6. Unfortunately there is no schematic nor kernel source to compare what they done differently.

Quote from jernej

But does CEC work?

yes, I was able to get CEC to work even after the devmem command.

just to clarify though, does changing that timing register with devmem take effect immediately? Or do i need to disable/re-enable the CEC option or something?

for what its worth, the Opi3LTS that i executed the command on has been running over 48hrs without freezing (and with CEC enabled). So it seems to have definitely helped.

Quote from gadget_guy

just to clarify though, does changing that timing register with devmem take effect immediately? Or do i need to disable/re-enable the CEC option or something?

Yes, it directly writes to HW clock register. It switches CEC clock source from periph0(2x) clock to external 32.768 kHz crystal, but sadly not all boards have it. Still, there is no logic why it would help. In any case, I have also other ideas, for which I will make test images.

Please test update from http://jernej.libreelec.tv/test/h6-cedrus/

Note that this is development version of LE12, so there might be other bugs. If it doesn't work, I can still build LE11 update.

There is just one clock/reset fix, so Cedrus driver actually follow proper order now. It might or might not be the issue experienced here.

Quote from jernej

Please test update from http://jernej.libreelec.tv/test/h6-cedrus/

ok, done. will keep you posted