Speaking of the GPU, I noticed that the OPP tables (sun50i-h6-gpu-opp.dtsi) are not included for any device other than Beelink GS1.
Yeah, GS1 was first, but then nobody actually updated and tested other boards.
I also assume the Tanix TX6 does dynamic frequency scaling (just with a fixed voltage?).
Correct (for CPU). GPU scaling should just work, if table is included.
I started looking at the clock code, and like everything it is a lot of indirection, macros, etc that takes years to fully understand -- and even then, there are things probably still not understood.
My research of bugs often lead me to clocks. So yeah, it's complex mechanism and, at least in the past, source of many issues.
I guess I am thinking that's why this isn't the root cause, the other factor is the scaling up/down of the frequency probably has an inherent delay and I would expect for the CPU clock to be adjusted the CPU is actually halted and the CCU has an inherent delay to wait for the clock to lock before releasing the CPU halt and perhaps that timing is greater than the regulator stabilization time (which worst case is 44us).
That's entirely possible.
I found something. H6 user manual has description how to properly adjust CPUX PLL. I'm sure that at least delay at the end is missing. However, I also noticed that many other SoCs, like A64 and H3, reparent CPU clock to something stable, like 24 MHz, switch CPUX PLL and then reparent back. I suppose that this is also valid option, at least until we can figure out more direct process.
But I assumed silence is good in this case.
