Enable PWM pin on Rock 4 SE?

odecif · March 25, 2025 at 10:08 AM

Hi! First time posting, some time lurking.

First off, I am new to GPIO, PWM and working in /sys (new as in have read a bunch but very little practise) so please be patient in my noobiness.

I have a couple of Radxa Rock 4 SE's with some options for which I've designed and printed a chassis/case for, and since the units are now encapsulated I decided on adding a small Noctua 40mm 5V PWM-fan to help with air flow and cooling connected to pins 2=5V, 9=GND and 11=PWM0 (pinout table). The fan is currently running, albeit a bit loud, which makes me think that it is currently not being controlled.

I have found the following thread on the Radxa forum in which a user had submitted a script on GitHub that supposedly helps with this, but in order to use it he says that the PWM-pin need to be enabled in the OS (hence why I am here). Is this done already in LibreELEC or what would I need to do? I have found previous threads from 6 years ago in which it is stated that I would need to compile the kernel (kernel 4 was relevant back then) with some patches applied but I am not certain if that is necessary today.

I do see some stuff present regarding pwm in the sys folder

Code

# find /sys -name pwm*
/sys/kernel/debug/pwm
/sys/class/pwm
/sys/class/pwm/pwmchip0
/sys/devices/platform/ff420020.pwm/pwm
/sys/devices/platform/ff420020.pwm/pwm/pwmchip0
/sys/bus/platform/drivers/pwm-clock
/sys/bus/platform/drivers/pwm-regulator
/sys/bus/platform/drivers/pwm-backlight
/sys/firmware/devicetree/base/pwm@ff420020
/sys/firmware/devicetree/base/pwm@ff420010
/sys/firmware/devicetree/base/pwm@ff420000
/sys/firmware/devicetree/base/pinctrl/pwm1
/sys/firmware/devicetree/base/pinctrl/pwm1/pwm1-pin
/sys/firmware/devicetree/base/pinctrl/pwm1/pwm1-pin-pull-down
/sys/firmware/devicetree/base/pinctrl/pwm3a
/sys/firmware/devicetree/base/pinctrl/pwm3a/pwm3a-pin
/sys/firmware/devicetree/base/pinctrl/pwm2
/sys/firmware/devicetree/base/pinctrl/pwm2/pwm2-pin
/sys/firmware/devicetree/base/pinctrl/pwm2/pwm2-pin-pull-down
/sys/firmware/devicetree/base/pinctrl/pwm0
/sys/firmware/devicetree/base/pinctrl/pwm0/pwm0-pin-pull-down
/sys/firmware/devicetree/base/pinctrl/pwm0/pwm0-pin
/sys/firmware/devicetree/base/pinctrl/pwm3b
/sys/firmware/devicetree/base/pinctrl/pwm3b/pwm3b-pin
/sys/firmware/devicetree/base/vdd-log/pwms
/sys/firmware/devicetree/base/vdd-log/pwm-supply
/sys/firmware/devicetree/base/__symbols__/pwm3a_pin
/sys/firmware/devicetree/base/__symbols__/pwm0_pin
/sys/firmware/devicetree/base/__symbols__/pwm3
/sys/firmware/devicetree/base/__symbols__/pwm3b_pin
/sys/firmware/devicetree/base/__symbols__/pwm1
/sys/firmware/devicetree/base/__symbols__/pwm1_pin
/sys/firmware/devicetree/base/__symbols__/pwm1_pin_pull_down
/sys/firmware/devicetree/base/__symbols__/pwm2_pin
/sys/firmware/devicetree/base/__symbols__/pwm2
/sys/firmware/devicetree/base/__symbols__/pwm2_pin_pull_down
/sys/firmware/devicetree/base/__symbols__/pwm0
/sys/firmware/devicetree/base/__symbols__/pwm0_pin_pull_down
/sys/firmware/devicetree/base/pwm@ff420030

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Code

# ls -lRt /sys/devices/platform/ff420020.pwm/
/sys/devices/platform/ff420020.pwm/:
total 0
lrwxrwxrwx    1 root     root             0 Mar 25 08:29 consumer:platform:vdd-log -> ../../virtual/devlink/platform:ff420020.pwm--platform:vdd-log
lrwxrwxrwx    1 root     root             0 Mar 25 08:29 driver -> ../../../bus/platform/drivers/rockchip-pwm
-rw-r--r--    1 root     root          4096 Mar 25 08:29 driver_override
-r--r--r--    1 root     root          4096 Mar 25 08:29 modalias
lrwxrwxrwx    1 root     root             0 Mar 25 08:29 of_node -> ../../../firmware/devicetree/base/pwm@ff420020
drwxr-xr-x    2 root     root             0 Mar 25 08:29 power
lrwxrwxrwx    1 root     root             0 Mar 25 08:29 supplier:platform:pinctrl -> ../../virtual/devlink/platform:pinctrl--platform:ff420020.pwm
drwxr-xr-x    3 root     root             0 Feb 27  2024 pwm
lrwxrwxrwx    1 root     root             0 Feb 27  2024 subsystem -> ../../../bus/platform
-rw-r--r--    1 root     root          4096 Feb 27  2024 uevent

/sys/devices/platform/ff420020.pwm/power:
total 0
-rw-r--r--    1 root     root          4096 Mar 25 08:29 autosuspend_delay_ms
-rw-r--r--    1 root     root          4096 Mar 25 08:29 control
-r--r--r--    1 root     root          4096 Mar 25 08:29 runtime_active_time
-r--r--r--    1 root     root          4096 Mar 25 08:29 runtime_status
-r--r--r--    1 root     root          4096 Mar 25 08:29 runtime_suspended_time

/sys/devices/platform/ff420020.pwm/pwm:
total 0
drwxr-xr-x    3 root     root             0 Feb 27  2024 pwmchip0

/sys/devices/platform/ff420020.pwm/pwm/pwmchip0:
total 0
--w-------    1 root     root          4096 Mar 25 09:59 export
lrwxrwxrwx    1 root     root             0 Mar 25 08:29 device -> ../../../ff420020.pwm
-r--r--r--    1 root     root          4096 Mar 25 08:29 npwm
drwxr-xr-x    2 root     root             0 Mar 25 08:29 power
--w-------    1 root     root          4096 Mar 25 08:29 unexport
lrwxrwxrwx    1 root     root             0 Feb 27  2024 subsystem -> ../../../../../class/pwm
-rw-r--r--    1 root     root          4096 Feb 27  2024 uevent

/sys/devices/platform/ff420020.pwm/pwm/pwmchip0/power:
total 0
-rw-r--r--    1 root     root          4096 Mar 25 08:29 autosuspend_delay_ms
-rw-r--r--    1 root     root          4096 Mar 25 08:29 control
-r--r--r--    1 root     root          4096 Mar 25 08:29 runtime_active_time
-r--r--r--    1 root     root          4096 Mar 25 08:29 runtime_status
-r--r--r--    1 root     root          4096 Mar 25 08:29 runtime_suspended_time

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Code

# ls -lRt /sys/class/pwm/pwmchip0/
/sys/class/pwm/pwmchip0/:
total 0
--w-------    1 root     root          4096 Mar 25 09:59 export
lrwxrwxrwx    1 root     root             0 Mar 25 08:29 device -> ../../../ff420020.pwm
-r--r--r--    1 root     root          4096 Mar 25 08:29 npwm
drwxr-xr-x    2 root     root             0 Mar 25 08:29 power
--w-------    1 root     root          4096 Mar 25 08:29 unexport
lrwxrwxrwx    1 root     root             0 Feb 27  2024 subsystem -> ../../../../../class/pwm
-rw-r--r--    1 root     root          4096 Feb 27  2024 uevent

/sys/class/pwm/pwmchip0/power:
total 0
-rw-r--r--    1 root     root          4096 Mar 25 08:29 autosuspend_delay_ms
-rw-r--r--    1 root     root          4096 Mar 25 08:29 control
-r--r--r--    1 root     root          4096 Mar 25 08:29 runtime_active_time
-r--r--r--    1 root     root          4096 Mar 25 08:29 runtime_status
-r--r--r--    1 root     root          4096 Mar 25 08:29 runtime_suspended_time

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I can see in the script linked above that it wants to access /sys/class/pwm/pwmchip0/pwm0 but I seem to be missing that path. Does LibreELEC handle PWM differently or should I have that path?

I cannot find anything regarding PWM in dmesg.

Thanks in advance.

**chewitt** · March 25, 2025 at 11:42 AM

The script was probably written against an older downstream vendor kernel not the modern mainline kernels that LE uses. I had a quick look at the rk3399-rock-4se.dts and rk3399-rock-pi-4.dtsi device-tree files for Linux 6.14 and while some PWM things do exist in them I don't see anything specific for fan control and no thermal properties are defined for the SoC. It's probably best to post in the Radxa forum to ask for a current method on Linux 6.12 and see what they say.

odecif · March 25, 2025 at 8:04 PM

Huh would you look at that, and here I thought I was a missing a step or configured something wrong... Thank you a lot for the help, I'll try posting on Radxa forum and see if maybe there is a solution to this. I'll post in this thread if I hear anything

odecif · March 26, 2025 at 11:05 PM

I just browsed through the device-tree file rk-3399-base.dtsi which is included in rk-3399-t.dtsi, which is included in rk-3399-rock-4se.dts on master in which I saw some stuff about 4 PWM ports/interfaces/pins(?):

Code

	pwm0: pwm@ff420000 {
		compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
		reg = <0x0 0xff420000 0x0 0x10>;
		#pwm-cells = <3>;
		pinctrl-names = "default";
		pinctrl-0 = <&pwm0_pin>;
		clocks = <&pmucru PCLK_RKPWM_PMU>;
		status = "disabled";
	};

	pwm1: pwm@ff420010 {
		compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
		reg = <0x0 0xff420010 0x0 0x10>;
		#pwm-cells = <3>;
		pinctrl-names = "default";
		pinctrl-0 = <&pwm1_pin>;
		clocks = <&pmucru PCLK_RKPWM_PMU>;
		status = "disabled";
	};

	pwm2: pwm@ff420020 {
		compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
		reg = <0x0 0xff420020 0x0 0x10>;
		#pwm-cells = <3>;
		pinctrl-names = "default";
		pinctrl-0 = <&pwm2_pin>;
		clocks = <&pmucru PCLK_RKPWM_PMU>;
		status = "disabled";
	};

	pwm3: pwm@ff420030 {
		compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
		reg = <0x0 0xff420030 0x0 0x10>;
		#pwm-cells = <3>;
		pinctrl-names = "default";
		pinctrl-0 = <&pwm3a_pin>;
		clocks = <&pmucru PCLK_RKPWM_PMU>;
		status = "disabled";
	};

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Might any one of these be possible to make use of somehow or do they need to be more defined than that in one of the other dts/dtsi-files?

Enable PWM pin on Rock 4 SE?

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