Posts by f1gogata

    f1gogata It looks like the edge2 u-boot defconfig set options designed for Android and this is the cause. I've defined an override in the Rockchip u-boot config that should fix that and the image in my test share is updated. Please download and retest.

    Now the boot is OK. But there is no video, and USB are not recognized. Log file https://paste.libreelec.tv/snaggy-buffy.log

    And boot UART:
    DDR ff1a08bde6 typ 25/03/13-15:39:39,fwver: v1.19
    ch0 ttot10
    ch1 ttot10
    ch2 ttot10
    ch3 ttot10
    ch0 ttot16
    LPDDR4X, 2112MHz
    channel[0] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB
    ch1 ttot16
    channel[1] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB
    ch2 ttot16
    channel[2] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB
    ch3 ttot16
    channel[3] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB
    Manufacturer ID:0x6
    DQS rds:l0,h1
    CH0 RX Vref:29.7%, TX Vref:23.8%,22.8%
    DQ rds:h5 h1 h3 h1 h1 l0 h2 l0, h2 h4 h2 h1 h2 h1 h1 h3

    DQS rds:h3,l0
    CH1 RX Vref:28.5%, TX Vref:21.8%,21.8%
    DQ rds:h4 h3 h1 h3 h2 l0 l0 h1, l0 h1 l2 h3 h2 h2 h3 l0

    DQS rds:l0,l5
    CH2 RX Vref:25.8%, TX Vref:22.8%,22.8%
    DQ rds:l0 l0 h1 l1 h3 h1 h1 h1, l0 h1 h2 l0 l0 l0 l1 h6

    DQS rds:h4,l0
    CH3 RX Vref:30.1%, TX Vref:22.8%,21.8%
    DQ rds:h2 h2 h5 h4 h3 h3 h5 h3, l0 h1 h1 l0 l0 h1 l0 h5

    stride=0x2, ddr_config=0x4
    hash ch_mask0-1 0x20 0x40, bank_mask0-3 0xa00 0x1400 0x2800 0x0, rank_mask0 0x401000
    change to F1: 528MHz
    ch0 ttot10
    ch1 ttot10
    ch2 ttot10
    ch3 ttot10
    change to F2: 1068MHz
    ch0 ttot12
    ch1 ttot12
    ch2 ttot12
    ch3 ttot12
    change to F3: 1560MHz
    ch0 ttot14
    ch1 ttot14
    ch2 ttot14
    ch3 ttot14
    change to F0: 2112MHz
    ch0 ttot16
    ch1 ttot16
    ch2 ttot16
    ch3 ttot16
    out

    U-Boot SPL 2026.10 (Oct 26 2026 - 12:06:58 +0000)
    Trying to boot from MMC1
    ## Checking hash(es) for config config-1 ... OK
    ## Checking hash(es) for Image atf-1 ... sha256+ OK
    ## Checking hash(es) for Image u-boot ... sha256+ OK
    ## Checking hash(es) for Image fdt-1 ... sha256+ OK
    ## Checking hash(es) for Image atf-2 ... sha256+ OK
    ## Checking hash(es) for Image atf-3 ... sha256+ OK
    NOTICE: BL31: v2.15.0(release):12.0.0-10135-gbe2fe77ac4-dirty
    NOTICE: BL31: Built : 17:04:29, Oct 20 2026


    U-Boot 2026.10 (Oct 26 2026 - 12:06:58 +0000)

    Model: Khadas Edge2
    SoC: RK3588S
    DRAM: 16 GiB
    DDR ff1a08bde6 typ 25/03/13-15:39:39,fwver: v1.19
    ch0 ttot10
    ch1 ttot10
    ch2 ttot10
    ch3 ttot10
    ch0 ttot16
    LPDDR4X, 2112MHz
    channel[0] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB
    ch1 ttot16
    channel[1] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB
    ch2 ttot16
    channel[2] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB
    ch3 ttot16
    channel[3] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB
    Manufacturer ID:0x6
    DQS rds:l0,h1
    CH0 RX Vref:29.3%, TX Vref:23.8%,23.8%
    DQ rds:h4 l0 h2 l0 h1 l0 h1 l1, h1 h3 h2 h1 h1 h1 h1 h3

    DQS rds:h3,l0
    CH1 RX Vref:28.5%, TX Vref:21.8%,21.8%
    DQ rds:h4 h3 h1 h2 h1 h1 l0 h1, l0 h1 l2 h4 h2 h2 h2 l0

    DQS rds:l0,l5
    CH2 RX Vref:25.8%, TX Vref:22.8%,23.8%
    DQ rds:l0 l0 h2 l1 h4 h1 h2 h1, l0 h1 h2 l0 l0 l0 l1 h6

    DQS rds:h4,l0
    CH3 RX Vref:30.1%, TX Vref:22.8%,20.8%
    DQ rds:h2 h2 h5 h3 h3 h2 h5 h3, l0 h1 h1 l0 l0 h1 l0 h5

    stride=0x2, ddr_config=0x4
    hash ch_mask0-1 0x20 0x40, bank_mask0-3 0xa00 0x1400 0x2800 0x0, rank_mask0 0x401000
    change to F1: 528MHz
    ch0 ttot10
    ch1 ttot10
    ch2 ttot10
    ch3 ttot10
    change to F2: 1068MHz
    ch0 ttot12
    ch1 ttot12
    ch2 ttot12
    ch3 ttot12
    change to F3: 1560MHz
    ch0 ttot14
    ch1 ttot14
    ch2 ttot14
    ch3 ttot14
    change to F0: 2112MHz
    ch0 ttot16
    ch1 ttot16
    ch2 ttot16
    ch3 ttot16
    out

    U-Boot SPL 2026.10 (Oct 26 2026 - 12:06:58 +0000)
    Trying to boot from MMC1
    ## Checking hash(es) for config config-1 ... OK
    ## Checking hash(es) for Image atf-1 ... sha256+ OK
    ## Checking hash(es) for Image u-boot ... sha256+ OK
    ## Checking hash(es) for Image fdt-1 ... sha256+ OK
    ## Checking hash(es) for Image atf-2 ... sha256+ OK
    ## Checking hash(es) for Image atf-3 ... sha256+ OK
    NOTICE: BL31: v2.15.0(release):12.0.0-10135-gbe2fe77ac4-dirty
    NOTICE: BL31: Built : 17:04:29, Oct 20 2026


    U-Boot 2026.10 (Oct 26 2026 - 12:06:58 +0000)

    Model: Khadas Edge2
    SoC: RK3588S
    DRAM: 16 GiB
    Core: 728 devices, 30 uclasses, devicetree: separate
    MMC: mmc@fe2c0000: 1, mmc@fe2e0000: 0
    Loading Environment from nowhere... OK
    In: serial@feb50000
    Out: serial@feb50000
    Err: serial@feb50000
    Model: Khadas Edge2
    SoC: RK3588S
    Net: No ethernet found.
    Hit SPACE in 1 seconds to stop autoboot
    Scanning for bootflows in all bootdevs
    Seq Method State Uclass Part Name Filename
    --- ----------- ------ -------- ---- ------------------------ ----------------
    Scanning bootdev '[email protected]':
    Card did not respond to voltage select! : -110
    Card did not respond to voltage select! : -110
    Card did not respond to voltage select! : -110
    Scanning bootdev '[email protected]':
    0 extlinux ready mmc 1 [email protected] /extlinux/extlinux.conf
    ** Booting bootflow '[email protected]_1' with extlinux
    1: LibreELEC
    Retrieving file: /KERNEL
    append: boot=UUID=2610-0537 disk=UUID=a9d0585d-9d88-414e-bafe-6200973e78c5 quiet earlycon console=uart8250,mmio32,0xfeb50000 console=tty0 coherent_pool=2M systemd.debug_shell=ttyS2
    Retrieving file: /rockchip/rk3588s-khadas-edge2.dtb
    ## Flattened Device Tree blob at 12000000
    Booting using the fdt blob at 0x12000000
    Working FDT set to 12000000
    Loading Device Tree to 00000000eceaa000, end 00000000eced67ba ... OK
    Working FDT set to eceaa000

    Starting kernel ...

    [ 0.326630] sdhci-dwcmshc fe2e0000.mmc: Can't reduce the clock below 52MHz in HS200/HS400 mode
    [ 0.539269] rockchip-pm-domain fd8d8000.power-management:power-controller: Failed to create device link (0x180) with supplier spi2.0 for /power-management@fd8d8000/power-controller/power-domain@12
    +q6E616D65LibreELEC:/ #

    The full log of UART with - LibreELEC-RK3588.aarch64-12.95.1-khadas-edge2.img
    Is this one:

    This is new log:

    this is log with U-Boot 2024.07 dd to - LibreELEC-RK3588.aarch64-12.95.1-khadas-edge2.img

    This is new log:

    So far, I have not been able to boot correctly new builds from chewitt github on internal eMMC
    I use Khadas Edge2 RK3588s, the SPI flash erase but stuck here:

    If i use u-boot-rockchip.bin from https://github.com/khadas/u-boot/tree/khadas-u-boot-v2024.07 and
    dd if=u-boot-rockchip.bin of=LibreELEC.khadas-edge2.img seek=64 conv=notrunc,fsync
    Boot process is correct an Libreeelc is working

    Is there any other way to use the current U-Boot version?

    I've picked the same changes to the next images I push to my test share (might be a few days as investigating a boot issue with Linux 7.0-rc1 at the moment). If you share a boot log showing which firmware files are being used these can also be added.

    Thank you for your response.

    Here is boot log from terminal -

    External Content pastebin.com
    Content embedded from external sources will not be displayed without your consent.
    Through the activation of external content, you agree that personal data may be transferred to third party platforms. We have provided more information on this in our privacy policy.

    So far, I have not been able to boot correctly new builds from chewitt github on internal eMMC of the Khadas Edge2.

    The only working option so far is to first install latest version from hеre https://yadi.sk/d/8vNYuuxynz1L0w

    on the eMMC, and then manually replace the SYSTEM, KERNEL, and DTB files.

    It seems that the official versions of U-Boot currently do not support installation from eMMC for this model.

    Is there any other solution for this, or do we simply need to wait for it to be developed in the future?

    Hello ,I tested the new build own (21/02/2026) for Khadas Edge2 from chewitt github and audio passthrough works fine.

    The built-in Wi-Fi module AP6275P was not being recognized before I made the following changes to the file.

    LibreELEC.tv/projects/Rockchip/linux/linux.aarch64.conf at rockchip · chewitt/LibreELEC.tv
    Just enough OS for KODI. Contribute to chewitt/LibreELEC.tv development by creating an account on GitHub.
    github.com

    + CONFIG_PCIEASPM_DEFAULT=y

    + CONFIG_BRCMFMAC_PROTO_MSGBUF=y

    +CONFIG_BRCMFMAC_PCIE=y

    and then copy firmware.tar.gz from this post RE: Unofficial LE for RK356x RK3328\RK3399 RK3588(s) RK3576

    Can you confirm if this is the correct way to do it, or should I use another method.

    @chewitt

    I just try to build Rockchip khadas-edge2 from this github - https://github.com/chewitt/LibreELEC.tv/tree/rockchip

    And I got this error:

    FAILED: [code=1] build/cores/VideoPlayer/codecs/video/CMakeFiles/dvdvideocodecs.dir/DVDVideoCodecDRMPRIME.cpp.o

    Link for the log file:

    External Content pastebin.com
    Content embedded from external sources will not be displayed without your consent.
    Through the activation of external content, you agree that personal data may be transferred to third party platforms. We have provided more information on this in our privacy policy.

    Can you help to resolve this issue?