From: Shigeaki Asai Date: Fri, 25 Sep 2026 13:00:00 +0900 Subject: [PATCH] arm64: dts: allwinner: h618: orangepi-zero3: Add CPU regulator ramp delay With cpufreq enabled, the Orange Pi Zero3 is unstable shortly after boot: either an RCU stall with CPU3 not responding even to NMIs and the PMIC I2C bus locked up, or an oops with obviously corrupted register values. Booting with cpufreq.off=1 is stable, and so is pinning the CPU at its top OPP, so the problem is frequency switching rather than the OPP voltages. The AXP313A regulator ops have no set_ramp_delay and the driver declares no ramp delay for DCDC2, so the regulator core assumes a new CPU voltage is reached instantly and raises the clock right away. Declare a ramp delay so the core waits for the voltage to settle before the frequency goes up. 2500 uV/us is the value the H6 boards use for their CPU rail. Tested on Orange Pi Zero3 (H618, 4 GiB) with the schedutil governor: 37664 frequency transitions without a hang or oops. Signed-off-by: Shigeaki Asai --- --- a/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts @@ -97,6 +97,7 @@ regulator-min-microvolt = <810000>; regulator-max-microvolt = <1100000>; regulator-name = "vdd-cpu"; + regulator-ramp-delay = <2500>; }; reg_dcdc3: dcdc3 {