diff --git a/config/graphic b/config/graphic
index 4b2e18af25..1500071bf2 100644
--- a/config/graphic
+++ b/config/graphic
@@ -78,6 +78,10 @@ get_graphicdrivers() {
     V4L2_SUPPORT="yes"
   fi
 
+  if listcontains "${GRAPHIC_DRIVERS}" "mali"; then
+    V4L2_SUPPORT="yes"
+  fi
+
   if listcontains "${GRAPHIC_DRIVERS}" "nvidia"; then
     XORG_DRIVERS+=" nvidia"
     VULKAN_DRIVERS_CONFIG+=" nvidia"
diff --git a/packages/addons/service/hyperhdr/package.mk b/packages/addons/service/hyperhdr/package.mk
index 9bc2c0a5ba..c7f69fbc06 100644
--- a/packages/addons/service/hyperhdr/package.mk
+++ b/packages/addons/service/hyperhdr/package.mk
@@ -4,7 +4,7 @@
 PKG_NAME="hyperhdr"
 PKG_VERSION="21.0.0.0"
 PKG_SHA256="fde381b8ae701c93b57b23cfa95c56dcbbecee7e5e7b2cce5d8b5f97ed86a676"
-PKG_REV="0"
+PKG_REV="1"
 PKG_LICENSE="MIT"
 PKG_SITE="https://github.com/awawa-dev/HyperHDR"
 PKG_URL="https://github.com/awawa-dev/HyperHDR/archive/v${PKG_VERSION}.tar.gz"
diff --git a/packages/addons/service/jellyfin/package.mk b/packages/addons/service/jellyfin/package.mk
index c77fa3dd6c..4fd875e932 100644
--- a/packages/addons/service/jellyfin/package.mk
+++ b/packages/addons/service/jellyfin/package.mk
@@ -4,7 +4,7 @@
 PKG_NAME="jellyfin"
 PKG_VERSION="1.0"
 PKG_VERSION_NUMBER="10.10.7"
-PKG_REV="0"
+PKG_REV="6"
 PKG_ARCH="any"
 PKG_LICENSE="GPLv2"
 PKG_SITE="https://jellyfin.org/"
diff --git a/packages/linux-firmware/kernel-firmware/firmwares/any.dat b/packages/linux-firmware/kernel-firmware/firmwares/any.dat
index 4c18cbdfce..822abb671f 100644
--- a/packages/linux-firmware/kernel-firmware/firmwares/any.dat
+++ b/packages/linux-firmware/kernel-firmware/firmwares/any.dat
@@ -23,3 +23,4 @@ rtl_bt/*
 rtlwifi/*
 rtw88/*
 rtw89/*
+rtl_nic/*
diff --git a/packages/linux/patches/raspberrypi/linux-001-backport-pr6741-rpi5-sand-fixes.patch b/packages/linux/patches/raspberrypi/linux-001-backport-pr6741-rpi5-sand-fixes.patch
new file mode 100644
index 0000000000..6ab84cc353
--- /dev/null
+++ b/packages/linux/patches/raspberrypi/linux-001-backport-pr6741-rpi5-sand-fixes.patch
@@ -0,0 +1,129 @@
+From 7ac0b48fa963cbc7e8b1f3702a4ae8d1947e65a2 Mon Sep 17 00:00:00 2001
+From: Dave Stevenson <dave.stevenson@raspberrypi.com>
+Date: Tue, 25 Mar 2025 16:02:24 +0000
+Subject: [PATCH 1/2] drm/vc4: plane: Correct SAND30 word sizing for cropping
+ on BCM2712
+
+BCM2712/vc6 uses 256bit words when reading in P030/SAND128,
+increased from 128bit on BCM2711/vc5.
+
+Update the code for cropping the read area to handle the correct
+word length.
+
+Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
+---
+ drivers/gpu/drm/vc4/vc4_plane.c | 16 ++++++++--------
+ 1 file changed, 8 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/gpu/drm/vc4/vc4_plane.c b/drivers/gpu/drm/vc4/vc4_plane.c
+index fdd6ba310324..f1333d89cd92 100644
+--- a/drivers/gpu/drm/vc4/vc4_plane.c
++++ b/drivers/gpu/drm/vc4/vc4_plane.c
+@@ -1934,18 +1934,18 @@ static int vc6_plane_mode_set(struct drm_plane *plane,
+
+			if (fb->format->format == DRM_FORMAT_P030) {
+				/*
+-				 * Spec says: bits [31:4] of the given address
+-				 * should point to the 128-bit word containing
+-				 * the desired starting pixel, and bits[3:0]
+-				 * should be between 0 and 11, indicating which
+-				 * of the 12-pixels in that 128-bit word is the
++				 * Spec says: bits [31:5] of the given address
++				 * should point to the 256-bit word containing
++				 * the desired starting pixel, and bits[4:0]
++				 * should be between 0 and 23, indicating which
++				 * of the 24-pixels in that 256-bit word is the
+				 * first pixel to be used
+				 */
+				u32 remaining_pixels = src_x % 96;
+-				u32 aligned = remaining_pixels / 12;
+-				u32 last_bits = remaining_pixels % 12;
++				u32 aligned = remaining_pixels / 24;
++				u32 last_bits = remaining_pixels % 24;
+
+-				x_off = aligned * 16 + last_bits;
++				x_off = aligned * 32 + last_bits;
+				tile_w = 128;
+				pix_per_tile = 96;
+			} else {
+--
+2.39.5
+
+
+From 3064adb25c5af41920f62d80dabf47a252b233a0 Mon Sep 17 00:00:00 2001
+From: Dave Stevenson <dave.stevenson@raspberrypi.com>
+Date: Mon, 31 Mar 2025 17:03:40 +0100
+Subject: [PATCH 2/2] drm/vc4: plane: Ensure fetch_count is sufficient for hw
+ in SAND mode
+
+The number of words to fetch for SAND formats on vc6 needs to account
+for all pixels requested by width.
+
+If cropping fractional pixels, then the width was being increased, but
+fetch_count had already been computed. That led to insufficient words
+being fetched, and the HVS locked up solid.
+
+Apply the fixup for fractional pixel source cropping before computing
+fetch_count.
+
+Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
+---
+ drivers/gpu/drm/vc4/vc4_plane.c | 36 ++++++++++++++++-----------------
+ 1 file changed, 18 insertions(+), 18 deletions(-)
+
+diff --git a/drivers/gpu/drm/vc4/vc4_plane.c b/drivers/gpu/drm/vc4/vc4_plane.c
+index f1333d89cd92..7a203a702c22 100644
+--- a/drivers/gpu/drm/vc4/vc4_plane.c
++++ b/drivers/gpu/drm/vc4/vc4_plane.c
+@@ -1874,6 +1874,24 @@ static int vc6_plane_mode_set(struct drm_plane *plane,
+
+	src_x = vc4_state->src_x >> 16;
+
++	/* fetch an extra pixel if we don't actually line up with the left edge. */
++	if ((vc4_state->src_x & 0xffff) && vc4_state->src_x < (state->fb->width << 16))
++		width++;
++
++	/* same for the right side */
++	if (((vc4_state->src_x + vc4_state->src_w[0]) & 0xffff) &&
++	    vc4_state->src_x + vc4_state->src_w[0] < (state->fb->width << 16))
++		width++;
++
++	/* now for the top */
++	if ((vc4_state->src_y & 0xffff) && vc4_state->src_y < (state->fb->height << 16))
++		height++;
++
++	/* and the bottom */
++	if (((vc4_state->src_y + vc4_state->src_h[0]) & 0xffff) &&
++	    vc4_state->src_y + vc4_state->src_h[0] < (state->fb->height << 16))
++		height++;
++
+	switch (base_format_mod) {
+	case DRM_FORMAT_MOD_LINEAR:
+		tiling = SCALER6_CTL0_ADDR_MODE_LINEAR;
+@@ -1988,24 +2006,6 @@ static int vc6_plane_mode_set(struct drm_plane *plane,
+		return -EINVAL;
+	}
+
+-	/* fetch an extra pixel if we don't actually line up with the left edge. */
+-	if ((vc4_state->src_x & 0xffff) && vc4_state->src_x < (state->fb->width << 16))
+-		width++;
+-
+-	/* same for the right side */
+-	if (((vc4_state->src_x + vc4_state->src_w[0]) & 0xffff) &&
+-	    vc4_state->src_x + vc4_state->src_w[0] < (state->fb->width << 16))
+-		width++;
+-
+-	/* now for the top */
+-	if ((vc4_state->src_y & 0xffff) && vc4_state->src_y < (state->fb->height << 16))
+-		height++;
+-
+-	/* and the bottom */
+-	if (((vc4_state->src_y + vc4_state->src_h[0]) & 0xffff) &&
+-	    vc4_state->src_y + vc4_state->src_h[0] < (state->fb->height << 16))
+-		height++;
+-
+	/* for YUV444 hardware wants double the width, otherwise it doesn't
+	 * fetch full width of chroma
+	 */
+--
+2.39.5
diff --git a/packages/sysutils/v4l-utils/keymaps/rockchip_remote.toml b/packages/sysutils/v4l-utils/keymaps/rockchip_remote.toml
new file mode 100644
index 0000000000..0a196df151
--- /dev/null
+++ b/packages/sysutils/v4l-utils/keymaps/rockchip_remote.toml
@@ -0,0 +1,167 @@
+[[protocols]]
+name = "conf1"
+protocol = "nec"
+variant = "nec"
+[protocols.scancodes]
+0x140 = "KEY_POWER"
+0x118 = "KEY_VOLUMEUP"
+0x110 = "KEY_VOLUMEDOWN"
+0x141 = "KEY_MUTE"
+0x100 = "KEY_MENU"
+0x119 = "KEY_BACK"
+0x116 = "KEY_UP"
+0x151 = "KEY_LEFT"
+0x150 = "KEY_RIGHT"
+0x11a = "KEY_DOWN"
+0x113 = "KEY_OK"
+0x111 = "KEY_HOME"
+0x14b = "KEY_PREVIOUS"
+0x14c = "KEY_INFO"
+0x14f = "KEY_NEXT"
+0x159 = "KEY_PREVIOUS"
+0x15a = "KEY_PLAYPAUSE"
+0x158 = "KEY_NEXT"
+0x147 = "KEY_MENU"
+0x101 = "KEY_NUMERIC_0"
+0x142 = "KEY_BACKSPACE"
+0x14e = "KEY_NUMERIC_1"
+0x10d = "KEY_NUMERIC_2"
+0x10c = "KEY_NUMERIC_3"
+0x14a = "KEY_NUMERIC_4"
+0x109 = "KEY_NUMERIC_5"
+0x108 = "KEY_NUMERIC_6"
+0x146 = "KEY_NUMERIC_7"
+0x105 = "KEY_NUMERIC_8"
+0x104 = "KEY_NUMERIC_9"
+
+[[protocols]]
+name = "conf2"
+protocol = "nec"
+variant = "necx"
+[protocols.scancodes]
+0x40404d = "KEY_POWER"
+0x404043 = "KEY_MUTE"
+0x404017 = "KEY_VOLUMEDOWN"
+0x404018 = "KEY_VOLUMEUP"
+0x40400b = "KEY_UP"
+0x404010 = "KEY_LEFT"
+0x404011 = "KEY_RIGHT"
+0x40400e = "KEY_DOWN"
+0x40400d = "KEY_OK"
+0x40401a = "KEY_HOME"
+0x404045 = "KEY_INFO"
+0x404042 = "KEY_BACK"
+0x404001 = "KEY_1"
+0x404002 = "KEY_2"
+0x404003 = "KEY_3"
+0x404004 = "KEY_4"
+0x404005 = "KEY_5"
+0x404006 = "KEY_6"
+0x404007 = "KEY_7"
+0x404008 = "KEY_8"
+0x404009 = "KEY_9"
+0x404047 = "KEY_SUBTITLE"
+0x404000 = "KEY_0"
+0x40400c = "KEY_BACKSPACE"
+
+[[protocols]]
+name = "conf3"
+protocol = "nec"
+variant = "necx"
+[protocols.scancodes]
+0xcc1d11 = "KEY_OK"
+0xcc1d0f = "KEY_BACK"
+0xcc1d07 = "KEY_UP"
+0xcc1d44 = "KEY_DOWN"
+0xcc1d10 = "KEY_LEFT"
+0xcc1d12 = "KEY_RIGHT"
+0xcc1d0e = "KEY_VOLUMEUP"
+0xcc1d02 = "KEY_VOLUMEDOWN"
+0xcc1d00 = "KEY_POWER"
+0xcc1d0c = "KEY_MUTE"
+0xcc1d40 = "KEY_C"
+0xcc1d41 = "KEY_1"
+0xcc1d45 = "KEY_2"
+0xcc1d4d = "KEY_3"
+0xcc1d42 = "KEY_4"
+0xcc1d46 = "KEY_5"
+0xcc1d4e = "KEY_6"
+0xcc1d43 = "KEY_7"
+0xcc1d47 = "KEY_8"
+0xcc1d4f = "KEY_9"
+0xcc1d49 = "KEY_0"
+0xcc1d4a = "KEY_BACKSPACE"
+0xcc1d01 = "KEY_M"
+0xcc1d05 = "KEY_T"
+0xcc1d09 = "KEY_E"
+0xcc1d0d = "KEY_A"
+0xcc1d06 = "KEY_PAGEDOWN"
+0xcc1d0a = "KEY_PAGEUP"
+0xcc1d03 = "KEY_HOME"
+0xcc1d4c = "KEY_INFO"
+0xcc1d48 = "KEY_O"
+
+[[protocols]]
+name = "onetv_lite"
+protocol = "NEC"
+[protocols.scancodes]
+0x19 = "KEY_MUTE"
+0x18 = "KEY_MEDIA"
+0x13 = "KEY_VOLUMEUP"
+0x17 = "KEY_VOLUMEDOWN"
+0x0d = "KEY_HOME"
+0x05 = "KEY_BACK"
+0x06 = "KEY_UP"
+0x5a = "KEY_LEFT"
+0x1a = "KEY_OK"
+0x1b = "KEY_RIGHT"
+0x16 = "KEY_DOWN"
+0x45 = "KEY_MENU"
+0x12 = "KEY_INFO"
+0x0f = "KEY_NUMERIC_0"
+0x52 = "KEY_NUMERIC_1"
+0x50 = "KEY_NUMERIC_2"
+0x10 = "KEY_NUMERIC_3"
+0x56 = "KEY_NUMERIC_4"
+0x54 = "KEY_NUMERIC_5"
+0x14 = "KEY_NUMERIC_6"
+0x4e = "KEY_NUMERIC_7"
+0x4c = "KEY_NUMERIC_8"
+0x0c = "KEY_NUMERIC_9"
+0x21 = "KEY_NUMERIC_STAR"
+0x51 = "KEY_BACKSPACE"
+0x59 = "KEY_POWER"
+
+[[protocols]]
+name = "greenet"
+protocol = "nec"
+variant = "nec"
+[protocols.scancodes]
+0xdf1c = "KEY_POWER"
+0xdf4b = "KEY_REWIND"
+0xdf4f = "KEY_FORWARD"
+0xdf01 = "KEY_PLAYPAUSE"
+0xdf5f = "KEY_MENU"
+0xdf5d = "KEY_VOLUMEUP"
+0xdf5c = "KEY_VOLUMEDOWN"
+0xdf42 = "KEY_HOME"
+0xdf0a = "KEY_BACK"
+0xdf1a = "KEY_UP"
+0xdf48 = "KEY_DOWN"
+0xdf07 = "KEY_RIGHT"
+0xdf47 = "KEY_LEFT"
+0xdf06 = "KEY_OK"
+0xdf03 = "KEY_ANGLE"
+0xdf18 = "KEY_CONTEXT_MENU"
+0xdf54 = "KEY_1"
+0xdf16 = "KEY_2"
+0xdf15 = "KEY_3"
+0xdf50 = "KEY_4"
+0xdf12 = "KEY_5"
+0xdf11 = "KEY_6"
+0xdf4c = "KEY_7"
+0xdf0e = "KEY_8"
+0xdf0d = "KEY_9"
+0xdf41 = "KEY_MUTE"
+0xdf0c = "KEY_0"
+0xdf10 = "KEY_BACKSPACE"
diff --git a/packages/sysutils/v4l-utils/package.mk b/packages/sysutils/v4l-utils/package.mk
index 40d959cc6e..ac7b5fc619 100644
--- a/packages/sysutils/v4l-utils/package.mk
+++ b/packages/sysutils/v4l-utils/package.mk
@@ -82,6 +82,7 @@ post_makeinstall_target() {
 *		rc-rc6-mce	libreelec_multi.toml
 # multi-table for amlogic devices
 meson-ir	rc-empty	libreelec_multi.toml
+rockchip_ir             rc-empty        libreelec_multi.toml
 EOF
 
   fi
diff --git a/packages/tools/optee-os/package.mk b/packages/tools/optee-os/package.mk
new file mode 100644
index 0000000000..750f052078
--- /dev/null
+++ b/packages/tools/optee-os/package.mk
@@ -0,0 +1,24 @@
+# SPDX-License-Identifier: GPL-2.0
+# Copyright (C) 2018-present Team LibreELEC
+
+PKG_NAME="optee-os"
+PKG_VERSION="4.2.0"
+PKG_SHA256="ce70f0d177001bf4855cd6cd6396f515af6126e4bba9b12c716a437a5cb40c7b"
+PKG_ARCH="arm"
+PKG_LICENSE="BSD-3c"
+PKG_SITE="https://github.com/OP-TEE/optee_os"
+PKG_URL="https://github.com/OP-TEE/optee_os/archive/refs/tags/${PKG_VERSION}.tar.gz"
+PKG_DEPENDS_TARGET="toolchain"
+PKG_LONGDESC="ARM Trusted Firmware is a reference implementation of secure world software, including a Secure Monitor executing at Exception Level 3 and various Arm interface standards."
+PKG_TOOLCHAIN="manual"
+
+[ -n "${KERNEL_TOOLCHAIN}" ] && PKG_DEPENDS_TARGET+=" gcc-${KERNEL_TOOLCHAIN}:host"
+
+make_target() {
+  CROSS_COMPILE="${TARGET_KERNEL_PREFIX}" LDFLAGS="" CFLAGS="" make CFG_CRYPTO=n CFG_REE_FS=n CFG_BUILD_IN_TREE_TA=y CFG_WITH_USER_TA=n PLATFORM=${OPTEE_PLATFORM}
+}
+
+makeinstall_target() {
+  mkdir -p ${INSTALL}/usr/share/bootloader
+  cp -a out/*/core/${ATF_BL31_BINARY:-tee-raw.bin} ${INSTALL}/usr/share/bootloader
+}
diff --git a/projects/Rockchip/devices/RK322X/README.md b/projects/Rockchip/devices/RK322X/README.md
new file mode 100644
index 0000000000..2d0f5974b9
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/README.md
@@ -0,0 +1 @@
+BUILDER_NAME=ilmich BUILD_PERIODIC=nightly PROJECT=Rockchip DEVICE=RK322X ARCH=arm UBOOT_SYSTEM=rk322x make image
diff --git a/projects/Rockchip/devices/RK322X/bootloader/canupdate.sh b/projects/Rockchip/devices/RK322X/bootloader/canupdate.sh
new file mode 100644
index 0000000000..77a2efc4fc
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/bootloader/canupdate.sh
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0
+# Copyright (C) 2017-present Team LibreELEC (https://libreelec.tv)
+
+# devices have been renamed after LE9.2
+if [ "${1}" = "TinkerBoard.arm" -o "${1}" = "MiQi.arm" ]; then
+  if [ "${2}" = "RK3288.arm" ]; then
+    exit 0
+  fi
+fi
+
+# Allow upgrades between arm and aarch64
+if [ "${1}" = "@PROJECT@.arm" -o "${1}" = "@PROJECT@.aarch64" ]; then
+  exit 0
+else
+  exit 1
+fi
diff --git a/projects/Rockchip/devices/RK322X/bootloader/config b/projects/Rockchip/devices/RK322X/bootloader/config
new file mode 100644
index 0000000000..42be4f4f35
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/bootloader/config
@@ -0,0 +1,2 @@
+# CONFIG_BOOTDELAY is not set
+# CONFIG_EFI_LOADER is not set
diff --git a/projects/Rockchip/devices/RK322X/bootloader/install b/projects/Rockchip/devices/RK322X/bootloader/install
new file mode 100644
index 0000000000..04969c5905
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/bootloader/install
@@ -0,0 +1,80 @@
+# SPDX-License-Identifier: GPL-2.0
+# Copyright (C) 2017-present Team LibreELEC (https://libreelec.tv)
+
+PKG_RKBIN="$(get_build_dir rkbin)"
+PKG_SOC="${DEVICE/RK/rk}"
+PKG_SOC="rk322x"
+
+case "${PKG_SOC}" in
+  rk3036)
+    PKG_DATAFILE="spl/u-boot-spl-nodtb.bin"
+    PKG_LOADER="u-boot-dtb.bin"
+    ;;
+  rk322x)
+   PKG_LOADER="${PKG_RKBIN}/rk32/rk322x_miniloader_v2.56.bin"
+   PKG_DATAFILE="${PKG_RKBIN}/rk32/rk322x_ddr_330MHz_v1.11.bin"
+   PKG_TOSTA="${PKG_RKBIN}/rk32/rk3228_tee_ta-51.1.0-333-gc9d95d1.bin"
+   PKG_LOAD_ADDR="0x60200000"
+   PKG_TOSXX_LOAD_ADDR="0x68400000"
+   ;;
+  rk3288)
+    PKG_DATAFILE="${PKG_RKBIN}/rk32/rk3288_ddr_400MHz_v1.08.bin"
+    PKG_LOADER="${PKG_RKBIN}/rk32/rk3288_miniloader_v2.58.bin"
+    PKG_LOAD_ADDR="0x0"
+    ;;
+  rk3328)
+    PKG_DATAFILE="${PKG_RKBIN}/rk33/rk3328_ddr_786MHz_v1.16.bin"
+    PKG_LOADER="${PKG_RKBIN}/rk33/rk3328_miniloader_v2.50.bin"
+    PKG_BL31="${PKG_RKBIN}/rk33/rk3328_bl31_v1.42.elf"
+    PKG_BL31_ADDR="0x10000"
+    PKG_LOAD_ADDR="0x200000"
+    ;;
+  rk3399)
+    PKG_DATAFILE="${PKG_RKBIN}/rk33/rk3399_ddr_800MHz_v1.24.bin"
+    PKG_LOADER="${PKG_RKBIN}/rk33/rk3399_miniloader_v1.24.bin"
+    PKG_BL31="${PKG_RKBIN}/rk33/rk3399_bl31_v1.31.elf"
+    PKG_BL31_ADDR="0x40000"
+    PKG_LOAD_ADDR="0x200000"
+    ;;
+  *)
+    PKG_DATAFILE="spl/u-boot-spl-dtb.bin"
+    PKG_LOADER="u-boot-dtb.bin"
+    ;;
+esac
+
+if [ -n "${PKG_DATAFILE}" -a -n "${PKG_LOADER}" ]; then
+  tools/mkimage -n ${PKG_SOC} -T rksd -d "${PKG_DATAFILE}" idbloader.img
+  cat "${PKG_LOADER}" >> idbloader.img
+  cp -av idbloader.img ${INSTALL}/usr/share/bootloader
+fi
+
+if [ -n "${PKG_LOAD_ADDR}" ]; then
+  ${PKG_RKBIN}/tools/loaderimage --pack --uboot u-boot-dtb.bin uboot.img ${PKG_LOAD_ADDR}
+  cp -av uboot.img ${INSTALL}/usr/share/bootloader
+fi
+
+if [ -n "${PKG_BL31}" ]; then
+  cat >trust.ini <<EOF
+[BL30_OPTION]
+SEC=0
+[BL31_OPTION]
+SEC=1
+PATH=${PKG_BL31}
+ADDR=${PKG_BL31_ADDR}
+[BL32_OPTION]
+SEC=0
+[BL33_OPTION]
+SEC=0
+[OUTPUT]
+PATH=trust.img
+EOF
+  ${PKG_RKBIN}/tools/trust_merger --verbose trust.ini
+elif [ -n "$PKG_TOSTA" -a -n "$PKG_TOSXX_LOAD_ADDR" ]; then
+  $PKG_RKBIN/tools/loaderimage --pack --trustos $PKG_TOSTA trust.img $PKG_TOSXX_LOAD_ADDR
+elif [ -n "$PKG_TOS" -a -n "$PKG_TOSXX_LOAD_ADDR" ]; then
+  $PKG_RKBIN/tools/loaderimage --pack --trustos $PKG_TOS trust.img $PKG_TOSXX_LOAD_ADDR
+fi
+
+if [ -f trust.img ]; then
+  cp -av trust.img ${INSTALL}/usr/share/bootloader
+fi
diff --git a/projects/Rockchip/devices/RK322X/bootloader/mkimage b/projects/Rockchip/devices/RK322X/bootloader/mkimage
new file mode 100644
index 0000000000..98fb9c7ed0
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/bootloader/mkimage
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0
+# Copyright (C) 2017-present Team LibreELEC (https://libreelec.tv)
+
+if [ -f "${RELEASE_DIR}/3rdparty/bootloader/idbloader.img" ]; then
+  echo "image: burn idbloader.img to image..."
+  dd if="${RELEASE_DIR}/3rdparty/bootloader/idbloader.img" of="${DISK}" bs=32k seek=1 conv=fsync,notrunc >"${SAVE_ERROR}" 2>&1 || show_error
+fi
+if [ -f "${RELEASE_DIR}/3rdparty/bootloader/uboot.img" ]; then
+  echo "image: burn uboot.img to image..."
+  dd if="${RELEASE_DIR}/3rdparty/bootloader/uboot.img" of="${DISK}" bs=64k seek=128 conv=fsync,notrunc >"${SAVE_ERROR}" 2>&1 || show_error
+fi
+if [ -f "${RELEASE_DIR}/3rdparty/bootloader/trust.img" ]; then
+  echo "image: burn trust.img to image..."
+  dd if="${RELEASE_DIR}/3rdparty/bootloader/trust.img" of="${DISK}" bs=64k seek=192 conv=fsync,notrunc >"${SAVE_ERROR}" 2>&1 || show_error
+fi
+
+# copy all dtb
+mcopy -o ${RELEASE_DIR}/3rdparty/bootloader/rk* ::
diff --git a/projects/Rockchip/devices/RK322X/bootloader/release b/projects/Rockchip/devices/RK322X/bootloader/release
new file mode 100644
index 0000000000..e2e9486143
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/bootloader/release
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: GPL-2.0
+# Copyright (C) 2017-present Team LibreELEC (https://libreelec.tv)
+
+SRCDIR="${BUILD}/image/system/usr/share/bootloader"
+DSTDIR="${RELEASE_DIR}/3rdparty/bootloader"
+
+mkdir -p "${DSTDIR}"
+  if [ -n "${UBOOT_SYSTEM}" ]; then
+    if [ -f "${SRCDIR}/idbloader.img" ]; then
+      cp -a "${SRCDIR}/idbloader.img" "${DSTDIR}"
+    fi
+    if [ -f "${SRCDIR}/uboot.img" ]; then
+      cp -a "${SRCDIR}/uboot.img" "${DSTDIR}"
+    fi
+    if [ -f "${SRCDIR}/trust.img" ]; then
+      cp -a "${SRCDIR}/trust.img" "${DSTDIR}"
+    fi
+  fi
+
+  cp -a "${SRCDIR}"/rk322*.dtb "${DSTDIR}"
diff --git a/projects/Rockchip/devices/RK322X/bootloader/update.sh b/projects/Rockchip/devices/RK322X/bootloader/update.sh
new file mode 100644
index 0000000000..a58b174c94
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/bootloader/update.sh
@@ -0,0 +1,89 @@
+# SPDX-License-Identifier: GPL-2.0
+# Copyright (C) 2017-present Team LibreELEC (https://libreelec.tv)
+
+[ -z "${SYSTEM_ROOT}" ] && SYSTEM_ROOT=""
+[ -z "${BOOT_ROOT}" ] && BOOT_ROOT="/flash"
+[ -z "${BOOT_PART}" ] && BOOT_PART=$(df "${BOOT_ROOT}" | tail -1 | awk {' print $1 '})
+if [ -z "${BOOT_DISK}" ]; then
+  case ${BOOT_PART} in
+    /dev/sd[a-z][0-9]*)
+      BOOT_DISK=$(echo ${BOOT_PART} | sed -e "s,[0-9]*,,g")
+      ;;
+    /dev/mmcblk*)
+      BOOT_DISK=$(echo ${BOOT_PART} | sed -e "s,p[0-9]*,,g")
+      ;;
+    /dev/rknand*)
+      BOOT_DISK=$(echo ${BOOT_PART} | sed -e "s,p[0-9]*,,g")
+      ;;
+  esac
+fi
+
+# mount ${BOOT_ROOT} r/w
+  mount -o remount,rw ${BOOT_ROOT}
+
+# update device tree
+  for all_dtb in ${BOOT_ROOT}/*.dtb; do
+    dtb=$(basename ${all_dtb})
+
+    # device tree mappings for update from vendor to mainline kernel
+    case "${dtb}" in
+      rk3288-miniarm.dtb)
+        new_dtb=rk3288-tinker-s.dtb
+        ;;
+      rk3328-box.dtb|rk3328-box-trn9.dtb|rk3328-box-z28.dtb|rk3328-rockbox.dtb)
+        new_dtb=rk3328-a1.dtb
+        ;;
+      rk3399-rock-pi-4.dtb)
+        new_dtb=rk3399-rock-pi-4b.dtb
+        ;;
+      *)
+        new_dtb="${dtb}"
+        ;;
+    esac
+
+    if [ "${dtb}" != "${new_dtb}" -a -f ${SYSTEM_ROOT}/usr/share/bootloader/${new_dtb} ]; then
+      echo -n "Replacing ${dtb} with ${new_dtb} ... "
+      cp -p ${SYSTEM_ROOT}/usr/share/bootloader/${new_dtb} ${BOOT_ROOT} && \
+      sed -e "s/FDT \/${dtb}/FDT \/${new_dtb}/g" \
+          -i ${BOOT_ROOT}/extlinux/extlinux.conf && \
+      rm -f ${BOOT_ROOT}/${dtb}
+      echo "done"
+    else
+      if [ -f ${SYSTEM_ROOT}/usr/share/bootloader/${dtb} ]; then
+        echo -n "Updating ${dtb}... "
+        cp -p ${SYSTEM_ROOT}/usr/share/bootloader/${dtb} ${BOOT_ROOT}
+        echo "done"
+      elif [ "$(grep -c "FDT /${dtb}" ${BOOT_ROOT}/extlinux/extlinux.conf)" -ne 0 ]; then
+	 non_existend_dtb="${dtb}"
+      fi
+    fi
+  done
+
+# update bootloader
+  if [ -f ${SYSTEM_ROOT}/usr/share/bootloader/idbloader.img ]; then
+    echo -n "Updating idbloader.img... "
+    dd if=${SYSTEM_ROOT}/usr/share/bootloader/idbloader.img of=${BOOT_DISK} bs=32k seek=1 conv=fsync &>/dev/null
+    echo "done"
+  fi
+  if [ -f ${SYSTEM_ROOT}/usr/share/bootloader/uboot.img ]; then
+    echo -n "Updating uboot.img... "
+    dd if=${SYSTEM_ROOT}/usr/share/bootloader/uboot.img of=${BOOT_DISK} bs=64k seek=128 conv=fsync &>/dev/null
+    echo "done"
+  fi
+  if [ -f ${SYSTEM_ROOT}/usr/share/bootloader/trust.img ]; then
+    echo -n "Updating trust.img... "
+    dd if=${SYSTEM_ROOT}/usr/share/bootloader/trust.img of=${BOOT_DISK} bs=64k seek=192 conv=fsync &>/dev/null
+    echo "done"
+  fi
+
+# mount ${BOOT_ROOT} r/o
+  sync
+  mount -o remount,ro ${BOOT_ROOT}
+
+# warning if device tree was not updated
+  if [ -n "${non_existend_dtb}" ]; then
+    echo "The device tree ${non_existend_dtb} your installation uses does not exist in this update package."
+    echo "The updated system will continue to use the device tree from the previous system and your installation might be broken."
+    echo "Please check documentation to find out which boards are supported by this package."
+    sleep 10
+  fi
diff --git a/projects/Rockchip/devices/RK322X/filesystem/etc/ssl/openssl.cnf b/projects/Rockchip/devices/RK322X/filesystem/etc/ssl/openssl.cnf
new file mode 100644
index 0000000000..27209ec964
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/filesystem/etc/ssl/openssl.cnf
@@ -0,0 +1,11 @@
+openssl_conf=openssl_conf
+
+[openssl_conf]
+engines=engines
+
+[engines]
+afalg=afalg
+
+[afalg]
+# Leave this alone and configure algorithms with CIPERS/DIGESTS below
+default_algorithms=ALL
diff --git a/projects/Rockchip/devices/RK322X/filesystem/usr/bin/rk322x-dtb-switch.sh b/projects/Rockchip/devices/RK322X/filesystem/usr/bin/rk322x-dtb-switch.sh
new file mode 100755
index 0000000000..d938047e53
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/filesystem/usr/bin/rk322x-dtb-switch.sh
@@ -0,0 +1,71 @@
+#!/bin/sh
+
+usage() {
+	echo "usage: $0 [list|switch|help]"
+	echo ""
+	echo "      show			show current device tree"
+	echo "      list			show available device trees"
+	echo "      switch [device tree]	switch to a device tree"
+	echo "      help			show this help"
+}
+
+show() {
+	DTB=`grep FDT /flash/extlinux/extlinux.conf | cut -d '/' -f 2`
+	echo "Current device tree is $DTB"
+}
+
+list()  {
+	for i in `ls -1 /usr/share/bootloader/*.dtb`;
+	do
+		echo `basename $i .dtb`
+	done
+}
+
+switch() {
+	if [ ! -e /usr/share/bootloader/$1.dtb ]; then
+		echo "Unable to find $1 device tree"
+		return 1
+	fi
+	echo "Device tree $1 founded"
+	read -p "Are you sure(y/n)?" yn
+	case $yn in
+		[Yy])
+			echo "Mounting flash rw"
+			mount -o remount,rw /flash/
+			echo "Switching dtb"
+			cp  -f /usr/share/bootloader/$1.dtb /flash/$1.dtb
+			sed -i "s/FDT.*/FDT \/$1.dtb/" /flash/extlinux/extlinux.conf
+			echo "Mounting flash ro"
+			mount -o remount,ro /flash/
+			echo "Switching is ok, now you need to reboot!!"
+			return 0
+			;;
+		[Nn])
+			return 1
+			;;
+	esac
+	return 1
+}
+
+case $1 in
+	show)
+		show
+		exit 0
+		;;
+	list)
+		list
+		exit 0
+		;;
+	switch)
+		switch $2
+		exit $?
+		;;
+	help)
+		usage
+		exit 1
+		;;
+	*)
+		usage
+		exit 1
+		;;
+esac
diff --git a/projects/Rockchip/devices/RK322X/kodi/advancedsettings.xml b/projects/Rockchip/devices/RK322X/kodi/advancedsettings.xml
new file mode 100644
index 0000000000..2e559bf2db
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/kodi/advancedsettings.xml
@@ -0,0 +1,10 @@
+<advancedsettings version="1.0">
+ <gui>
+    <fronttobackrendering>false</fronttobackrendering>
+    <!-- algorithmdirtyregions>1</algorithmdirtyregions -->
+    <!-- hardwaredirtyregions>true</hardwaredirtyregions -->
+  </gui>
+<imageres>540</imageres>
+<fanartres>540</fanartres>
+<imagescalingalgorithm>bicubic</imagescalingalgorithm>
+</advancedsettings>
diff --git a/projects/Rockchip/devices/RK322X/kodi/appliance.xml b/projects/Rockchip/devices/RK322X/kodi/appliance.xml
new file mode 100644
index 0000000000..94034252e6
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/kodi/appliance.xml
@@ -0,0 +1,27 @@
+<?xml version="1.0" encoding="utf-8"?>
+<settings version="1">
+  <section id="system">
+    <category id="display">
+      <group id="1">
+        <setting id="videoscreen.limitguisize">
+          <default>1</default>
+          <visible>false</visible>
+        </setting>
+      </group>
+      <group id="3">
+        <setting id="videoscreen.whitelist">
+          <default>0384002160060.00000pstd,0384002160050.00000pstd,0384002160030.00000pstd,0384002160025.00000pstd,0384002160024.00000pstd,0192001080060.00000pstd,0192001080050.00000pstd,0192001080030.00000pstd,0192001080024.00000pstd,0128000720060.00000pstd,0128000720050.00000pstd</default>
+        </setting>
+      </group>
+    </category>
+    <category id="audio">
+      <group id="3">
+        <visible>true</visible>
+        <setting id="audiooutput.passthrough">
+          <visible>true</visible>
+          <default>true</default>
+        </setting>
+      </group>
+    </category>
+  </section>
+</settings>
diff --git a/projects/Rockchip/devices/RK322X/linux/linux.arm.conf b/projects/Rockchip/devices/RK322X/linux/linux.arm.conf
new file mode 100644
index 0000000000..ce9a8069a7
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/linux/linux.arm.conf
@@ -0,0 +1,6409 @@
+#
+# General setup
+#
+CONFIG_INIT_ENV_ARG_LIMIT=32
+# CONFIG_COMPILE_TEST is not set
+# CONFIG_WERROR is not set
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_BUILD_SALT=""
+CONFIG_HAVE_KERNEL_GZIP=y
+CONFIG_HAVE_KERNEL_LZMA=y
+CONFIG_HAVE_KERNEL_XZ=y
+CONFIG_HAVE_KERNEL_LZO=y
+CONFIG_HAVE_KERNEL_LZ4=y
+# CONFIG_KERNEL_GZIP is not set
+# CONFIG_KERNEL_LZMA is not set
+# CONFIG_KERNEL_XZ is not set
+CONFIG_KERNEL_LZO=y
+# CONFIG_KERNEL_LZ4 is not set
+CONFIG_DEFAULT_INIT=""
+CONFIG_DEFAULT_HOSTNAME="@DISTRONAME@"
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
+# CONFIG_WATCH_QUEUE is not set
+CONFIG_CROSS_MEMORY_ATTACH=y
+# CONFIG_USELIB is not set
+# CONFIG_AUDIT is not set
+CONFIG_HAVE_ARCH_AUDITSYSCALL=y
+
+#
+# IRQ subsystem
+#
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_MIGRATION=y
+CONFIG_GENERIC_IRQ_INJECTION=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_GENERIC_IRQ_IPI=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_GENERIC_IRQ_DEBUGFS=y
+# end of IRQ subsystem
+
+CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_ARCH_HAS_TICK_BROADCAST=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_CONTEXT_TRACKING=y
+CONFIG_CONTEXT_TRACKING_IDLE=y
+
+#
+# Timers subsystem
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ_COMMON=y
+# CONFIG_HZ_PERIODIC is not set
+CONFIG_NO_HZ_IDLE=y
+# CONFIG_NO_HZ_FULL is not set
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+# end of Timers subsystem
+
+CONFIG_BPF=y
+CONFIG_HAVE_EBPF_JIT=y
+
+#
+# BPF subsystem
+#
+CONFIG_BPF_SYSCALL=y
+# CONFIG_BPF_JIT is not set
+# CONFIG_BPF_UNPRIV_DEFAULT_OFF is not set
+# CONFIG_BPF_PRELOAD is not set
+# end of BPF subsystem
+
+CONFIG_PREEMPT_VOLUNTARY_BUILD=y
+# CONFIG_PREEMPT_NONE is not set
+CONFIG_PREEMPT_VOLUNTARY=y
+# CONFIG_PREEMPT is not set
+
+#
+# CPU/Task time and stats accounting
+#
+CONFIG_TICK_CPU_ACCOUNTING=y
+# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set
+# CONFIG_IRQ_TIME_ACCOUNTING is not set
+CONFIG_SCHED_THERMAL_PRESSURE=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_TASKSTATS=y
+CONFIG_TASK_DELAY_ACCT=y
+CONFIG_TASK_XACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
+# CONFIG_PSI is not set
+# end of CPU/Task time and stats accounting
+
+CONFIG_CPU_ISOLATION=y
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_RCU_EXPERT is not set
+CONFIG_TREE_SRCU=y
+CONFIG_NEED_SRCU_NMI_SAFE=y
+CONFIG_TASKS_RCU_GENERIC=y
+CONFIG_TASKS_TRACE_RCU=y
+CONFIG_RCU_STALL_COMMON=y
+CONFIG_RCU_NEED_SEGCBLIST=y
+# end of RCU Subsystem
+
+CONFIG_IKCONFIG=m
+CONFIG_IKCONFIG_PROC=y
+# CONFIG_IKHEADERS is not set
+CONFIG_LOG_BUF_SHIFT=17
+CONFIG_LOG_CPU_MAX_BUF_SHIFT=12
+# CONFIG_PRINTK_INDEX is not set
+CONFIG_GENERIC_SCHED_CLOCK=y
+
+#
+# Scheduler features
+#
+# CONFIG_UCLAMP_TASK is not set
+# end of Scheduler features
+
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_GCC10_NO_ARRAY_BOUNDS=y
+CONFIG_CC_NO_ARRAY_BOUNDS=y
+CONFIG_CGROUPS=y
+CONFIG_PAGE_COUNTER=y
+# CONFIG_CGROUP_FAVOR_DYNMODS is not set
+CONFIG_MEMCG=y
+CONFIG_MEMCG_KMEM=y
+CONFIG_BLK_CGROUP=y
+CONFIG_CGROUP_WRITEBACK=y
+CONFIG_CGROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+CONFIG_CFS_BANDWIDTH=y
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_SCHED_MM_CID=y
+CONFIG_CGROUP_PIDS=y
+# CONFIG_CGROUP_RDMA is not set
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CPUSETS=y
+CONFIG_PROC_PID_CPUSET=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_CGROUP_PERF=y
+CONFIG_CGROUP_BPF=y
+# CONFIG_CGROUP_MISC is not set
+# CONFIG_CGROUP_DEBUG is not set
+CONFIG_SOCK_CGROUP_DATA=y
+CONFIG_NAMESPACES=y
+CONFIG_UTS_NS=y
+CONFIG_IPC_NS=y
+CONFIG_USER_NS=y
+CONFIG_PID_NS=y
+CONFIG_NET_NS=y
+# CONFIG_CHECKPOINT_RESTORE is not set
+CONFIG_SCHED_AUTOGROUP=y
+# CONFIG_RELAY is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE="@INITRAMFS_SOURCE@"
+CONFIG_INITRAMFS_ROOT_UID=0
+CONFIG_INITRAMFS_ROOT_GID=0
+CONFIG_RD_GZIP=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_LZMA=y
+CONFIG_RD_XZ=y
+CONFIG_RD_LZO=y
+CONFIG_RD_LZ4=y
+CONFIG_RD_ZSTD=y
+# CONFIG_INITRAMFS_COMPRESSION_GZIP is not set
+# CONFIG_INITRAMFS_COMPRESSION_BZIP2 is not set
+# CONFIG_INITRAMFS_COMPRESSION_LZMA is not set
+# CONFIG_INITRAMFS_COMPRESSION_XZ is not set
+CONFIG_INITRAMFS_COMPRESSION_LZO=y
+# CONFIG_INITRAMFS_COMPRESSION_LZ4 is not set
+# CONFIG_INITRAMFS_COMPRESSION_ZSTD is not set
+# CONFIG_INITRAMFS_COMPRESSION_NONE is not set
+# CONFIG_BOOT_CONFIG is not set
+CONFIG_INITRAMFS_PRESERVE_MTIME=y
+CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_LD_ORPHAN_WARN=y
+CONFIG_LD_ORPHAN_WARN_LEVEL="warn"
+CONFIG_SYSCTL=y
+CONFIG_HAVE_UID16=y
+# CONFIG_EXPERT is not set
+CONFIG_UID16=y
+CONFIG_MULTIUSER=y
+CONFIG_SYSFS_SYSCALL=y
+CONFIG_FHANDLE=y
+CONFIG_POSIX_TIMERS=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_FUTEX_PI=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_IO_URING=y
+CONFIG_ADVISE_SYSCALLS=y
+CONFIG_MEMBARRIER=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_SELFTEST is not set
+# CONFIG_KALLSYMS_ALL is not set
+CONFIG_KALLSYMS_BASE_RELATIVE=y
+CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y
+CONFIG_KCMP=y
+CONFIG_RSEQ=y
+CONFIG_CACHESTAT_SYSCALL=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_PERF_USE_VMALLOC=y
+
+#
+# Kernel Performance Events And Counters
+#
+CONFIG_PERF_EVENTS=y
+# CONFIG_DEBUG_PERF_USE_VMALLOC is not set
+# end of Kernel Performance Events And Counters
+
+CONFIG_SYSTEM_DATA_VERIFICATION=y
+# CONFIG_PROFILING is not set
+
+#
+# Kexec and crash features
+#
+# CONFIG_KEXEC is not set
+# CONFIG_CRASH_DUMP is not set
+# end of Kexec and crash features
+# end of General setup
+
+CONFIG_ARM=y
+CONFIG_ARM_HAS_GROUP_RELOCS=y
+CONFIG_ARM_DMA_USE_IOMMU=y
+CONFIG_ARM_DMA_IOMMU_ALIGNMENT=8
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_HAVE_PROC_CPU=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ARCH_SUPPORTS_UPROBES=y
+CONFIG_ARM_PATCH_PHYS_VIRT=y
+CONFIG_GENERIC_BUG=y
+CONFIG_PGTABLE_LEVELS=2
+
+#
+# System Type
+#
+CONFIG_MMU=y
+CONFIG_ARCH_MMAP_RND_BITS_MIN=8
+CONFIG_ARCH_MMAP_RND_BITS_MAX=16
+CONFIG_ARCH_MULTIPLATFORM=y
+
+#
+# Platform selection
+#
+
+#
+# CPU Core family selection
+#
+# CONFIG_ARCH_MULTI_V6 is not set
+CONFIG_ARCH_MULTI_V7=y
+CONFIG_ARCH_MULTI_V6_V7=y
+# end of Platform selection
+
+# CONFIG_ARCH_VIRT is not set
+# CONFIG_ARCH_AIROHA is not set
+# CONFIG_ARCH_ACTIONS is not set
+# CONFIG_ARCH_ALPINE is not set
+# CONFIG_ARCH_ARTPEC is not set
+# CONFIG_ARCH_ASPEED is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_BCM is not set
+# CONFIG_ARCH_BERLIN is not set
+# CONFIG_ARCH_DIGICOLOR is not set
+# CONFIG_ARCH_DOVE is not set
+# CONFIG_ARCH_EXYNOS is not set
+# CONFIG_ARCH_HIGHBANK is not set
+# CONFIG_ARCH_HISI is not set
+# CONFIG_ARCH_HPE is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_KEYSTONE is not set
+# CONFIG_ARCH_MEDIATEK is not set
+# CONFIG_ARCH_MESON is not set
+# CONFIG_ARCH_MILBEAUT is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_MSTARV7 is not set
+# CONFIG_ARCH_MVEBU is not set
+# CONFIG_ARCH_NPCM is not set
+
+#
+# TI OMAP/AM/DM/DRA Family
+#
+# CONFIG_ARCH_OMAP3 is not set
+# CONFIG_ARCH_OMAP4 is not set
+# CONFIG_SOC_OMAP5 is not set
+# CONFIG_SOC_AM33XX is not set
+# CONFIG_SOC_AM43XX is not set
+# CONFIG_SOC_DRA7XX is not set
+# end of TI OMAP/AM/DM/DRA Family
+
+# CONFIG_ARCH_QCOM is not set
+# CONFIG_ARCH_RDA is not set
+# CONFIG_ARCH_REALTEK is not set
+CONFIG_ARCH_ROCKCHIP=y
+# CONFIG_ARCH_S5PV210 is not set
+# CONFIG_ARCH_RENESAS is not set
+# CONFIG_ARCH_INTEL_SOCFPGA is not set
+# CONFIG_PLAT_SPEAR is not set
+# CONFIG_ARCH_STI is not set
+# CONFIG_ARCH_STM32 is not set
+# CONFIG_ARCH_SUNPLUS is not set
+# CONFIG_ARCH_SUNXI is not set
+# CONFIG_ARCH_TEGRA is not set
+# CONFIG_ARCH_UNIPHIER is not set
+# CONFIG_ARCH_U8500 is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VEXPRESS is not set
+# CONFIG_ARCH_WM8850 is not set
+# CONFIG_ARCH_ZYNQ is not set
+
+#
+# Processor Type
+#
+CONFIG_CPU_V7=y
+CONFIG_CPU_THUMB_CAPABLE=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+CONFIG_CPU_PABRT_V7=y
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+# CONFIG_ARM_LPAE is not set
+CONFIG_ARM_THUMB=y
+CONFIG_ARM_THUMBEE=y
+CONFIG_ARM_VIRT_EXT=y
+CONFIG_SWP_EMULATE=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+# CONFIG_CPU_BIG_ENDIAN is not set
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_ICACHE_MISMATCH_WORKAROUND is not set
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+CONFIG_CPU_SPECTRE=y
+CONFIG_HARDEN_BRANCH_PREDICTOR=y
+CONFIG_HARDEN_BRANCH_HISTORY=y
+CONFIG_KUSER_HELPERS=y
+CONFIG_VDSO=y
+CONFIG_OUTER_CACHE=y
+CONFIG_OUTER_CACHE_SYNC=y
+CONFIG_MIGHT_HAVE_CACHE_L2X0=y
+CONFIG_CACHE_L2X0=y
+# CONFIG_CACHE_L2X0_PMU is not set
+# CONFIG_PL310_ERRATA_588369 is not set
+# CONFIG_PL310_ERRATA_727915 is not set
+# CONFIG_PL310_ERRATA_753970 is not set
+# CONFIG_PL310_ERRATA_769419 is not set
+CONFIG_ARM_L1_CACHE_SHIFT_6=y
+CONFIG_ARM_L1_CACHE_SHIFT=6
+CONFIG_ARM_DMA_MEM_BUFFERABLE=y
+CONFIG_ARM_HEAVY_MB=y
+CONFIG_DEBUG_ALIGN_RODATA=y
+# CONFIG_ARM_ERRATA_430973 is not set
+# CONFIG_ARM_ERRATA_643719 is not set
+# CONFIG_ARM_ERRATA_720789 is not set
+# CONFIG_ARM_ERRATA_754322 is not set
+# CONFIG_ARM_ERRATA_754327 is not set
+# CONFIG_ARM_ERRATA_764369 is not set
+# CONFIG_ARM_ERRATA_764319 is not set
+# CONFIG_ARM_ERRATA_775420 is not set
+# CONFIG_ARM_ERRATA_798181 is not set
+# CONFIG_ARM_ERRATA_773022 is not set
+# CONFIG_ARM_ERRATA_818325_852422 is not set
+# CONFIG_ARM_ERRATA_821420 is not set
+# CONFIG_ARM_ERRATA_825619 is not set
+# CONFIG_ARM_ERRATA_857271 is not set
+# CONFIG_ARM_ERRATA_852421 is not set
+# CONFIG_ARM_ERRATA_852423 is not set
+# CONFIG_ARM_ERRATA_857272 is not set
+# end of System Type
+
+#
+# Bus support
+#
+# CONFIG_ARM_ERRATA_814220 is not set
+# end of Bus support
+
+#
+# Kernel Features
+#
+CONFIG_HAVE_SMP=y
+CONFIG_SMP=y
+CONFIG_SMP_ON_UP=y
+CONFIG_CURRENT_POINTER_IN_TPIDRURO=y
+CONFIG_IRQSTACKS=y
+CONFIG_ARM_CPU_TOPOLOGY=y
+CONFIG_SCHED_MC=y
+# CONFIG_SCHED_SMT is not set
+CONFIG_HAVE_ARM_SCU=y
+CONFIG_HAVE_ARM_ARCH_TIMER=y
+CONFIG_HAVE_ARM_TWD=y
+# CONFIG_MCPM is not set
+# CONFIG_BIG_LITTLE is not set
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_3G_OPT is not set
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_NR_CPUS=4
+CONFIG_HOTPLUG_CPU=y
+CONFIG_ARM_PSCI=y
+CONFIG_HZ_FIXED=0
+# CONFIG_HZ_100 is not set
+# CONFIG_HZ_200 is not set
+# CONFIG_HZ_250 is not set
+CONFIG_HZ_300=y
+# CONFIG_HZ_500 is not set
+# CONFIG_HZ_1000 is not set
+CONFIG_HZ=300
+CONFIG_SCHED_HRTICK=y
+# CONFIG_THUMB2_KERNEL is not set
+CONFIG_ARM_PATCH_IDIV=y
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_HIGHMEM=y
+CONFIG_HIGHPTE=y
+CONFIG_CPU_SW_DOMAIN_PAN=y
+CONFIG_HW_PERF_EVENTS=y
+# CONFIG_ARM_MODULE_PLTS is not set
+CONFIG_ARCH_FORCE_MAX_ORDER=11
+CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_UACCESS_WITH_MEMCPY is not set
+# CONFIG_PARAVIRT is not set
+# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set
+# CONFIG_XEN is not set
+# end of Kernel Features
+
+#
+# Boot options
+#
+CONFIG_USE_OF=y
+CONFIG_ARCH_WANT_FLAT_DTB_INSTALL=y
+CONFIG_ATAGS=y
+# CONFIG_DEPRECATED_PARAM_STRUCT is not set
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_ARM_ATAG_DTB_COMPAT=y
+CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y
+# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set
+CONFIG_CMDLINE=""
+CONFIG_ARCH_SUPPORTS_KEXEC=y
+CONFIG_ARCH_SUPPORTS_CRASH_DUMP=y
+CONFIG_AUTO_ZRELADDR=y
+# CONFIG_EFI is not set
+# end of Boot options
+
+#
+# CPU Power Management
+#
+
+#
+# CPU Frequency scaling
+#
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_GOV_ATTR_SET=y
+CONFIG_CPU_FREQ_GOV_COMMON=y
+CONFIG_CPU_FREQ_STAT=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
+
+#
+# CPU frequency scaling drivers
+#
+CONFIG_CPUFREQ_DT=y
+CONFIG_CPUFREQ_DT_PLATDEV=y
+# CONFIG_ARM_SCPI_CPUFREQ is not set
+# CONFIG_ARM_SCMI_CPUFREQ is not set
+# end of CPU Frequency scaling
+
+#
+# CPU Idle
+#
+# CONFIG_CPU_IDLE is not set
+# end of CPU Idle
+# end of CPU Power Management
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_VFP=y
+CONFIG_VFPv3=y
+CONFIG_NEON=y
+CONFIG_KERNEL_MODE_NEON=y
+# end of Floating point emulation
+
+#
+# Power management options
+#
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+# CONFIG_HIBERNATION is not set
+CONFIG_PM_SLEEP=y
+CONFIG_PM_SLEEP_SMP=y
+# CONFIG_PM_AUTOSLEEP is not set
+# CONFIG_PM_USERSPACE_AUTOSLEEP is not set
+CONFIG_PM_WAKELOCKS=y
+CONFIG_PM_WAKELOCKS_LIMIT=100
+CONFIG_PM_WAKELOCKS_GC=y
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+# CONFIG_APM_EMULATION is not set
+CONFIG_PM_CLK=y
+CONFIG_PM_GENERIC_DOMAINS=y
+# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
+CONFIG_PM_GENERIC_DOMAINS_SLEEP=y
+CONFIG_PM_GENERIC_DOMAINS_OF=y
+CONFIG_CPU_PM=y
+# CONFIG_ENERGY_MODEL is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARM_CPU_SUSPEND=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+# end of Power management options
+
+CONFIG_CPU_MITIGATIONS=y
+
+#
+# General architecture-dependent options
+#
+CONFIG_HOTPLUG_CORE_SYNC=y
+CONFIG_HOTPLUG_CORE_SYNC_DEAD=y
+# CONFIG_KPROBES is not set
+CONFIG_JUMP_LABEL=y
+# CONFIG_STATIC_KEYS_SELFTEST is not set
+CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
+CONFIG_ARCH_USE_BUILTIN_BSWAP=y
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_OPTPROBES=y
+CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y
+CONFIG_HAVE_NMI=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HAVE_ARCH_TRACEHOOK=y
+CONFIG_HAVE_DMA_CONTIGUOUS=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_ARCH_HAS_FORTIFY_SOURCE=y
+CONFIG_ARCH_HAS_KEEPINITRD=y
+CONFIG_ARCH_HAS_SET_MEMORY=y
+CONFIG_ARCH_HAS_CPU_FINALIZE_INIT=y
+CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y
+CONFIG_ARCH_32BIT_OFF_T=y
+CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
+CONFIG_HAVE_RSEQ=y
+CONFIG_HAVE_HW_BREAKPOINT=y
+CONFIG_HAVE_PERF_REGS=y
+CONFIG_HAVE_PERF_USER_STACK_DUMP=y
+CONFIG_HAVE_ARCH_JUMP_LABEL=y
+CONFIG_MMU_LAZY_TLB_REFCOUNT=y
+CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y
+CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
+CONFIG_HAVE_ARCH_SECCOMP=y
+CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
+CONFIG_SECCOMP=y
+CONFIG_SECCOMP_FILTER=y
+# CONFIG_SECCOMP_CACHE_DEBUG is not set
+CONFIG_HAVE_STACKPROTECTOR=y
+CONFIG_STACKPROTECTOR=y
+CONFIG_STACKPROTECTOR_STRONG=y
+CONFIG_LTO_NONE=y
+CONFIG_HAVE_CONTEXT_TRACKING_USER=y
+CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
+CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
+CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y
+CONFIG_HAVE_SOFTIRQ_ON_OWN_STACK=y
+CONFIG_SOFTIRQ_ON_OWN_STACK=y
+CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
+CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
+CONFIG_HAVE_EXIT_THREAD=y
+CONFIG_ARCH_MMAP_RND_BITS=8
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_OLD_SIGSUSPEND3=y
+CONFIG_OLD_SIGACTION=y
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_HAVE_ARCH_VMAP_STACK=y
+# CONFIG_VMAP_STACK is not set
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
+CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
+CONFIG_STRICT_KERNEL_RWX=y
+CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
+CONFIG_STRICT_MODULE_RWX=y
+# CONFIG_LOCK_EVENT_COUNTS is not set
+CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y
+CONFIG_HAVE_ARCH_PFN_VALID=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_GCOV_KERNEL is not set
+CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
+# end of GCOV-based kernel profiling
+
+CONFIG_HAVE_GCC_PLUGINS=y
+# CONFIG_GCC_PLUGINS is not set
+CONFIG_FUNCTION_ALIGNMENT=0
+# end of General architecture-dependent options
+
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_DEBUG is not set
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODULE_UNLOAD_TAINT_TRACKING is not set
+CONFIG_MODVERSIONS=y
+CONFIG_MODULE_SRCVERSION_ALL=y
+# CONFIG_MODULE_SIG is not set
+CONFIG_MODULE_COMPRESS_NONE=y
+# CONFIG_MODULE_COMPRESS_GZIP is not set
+# CONFIG_MODULE_COMPRESS_XZ is not set
+# CONFIG_MODULE_COMPRESS_ZSTD is not set
+# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set
+CONFIG_MODPROBE_PATH="/sbin/modprobe"
+CONFIG_MODULES_TREE_LOOKUP=y
+CONFIG_BLOCK=y
+CONFIG_BLOCK_LEGACY_AUTOLOAD=y
+CONFIG_BLK_CGROUP_RWSTAT=y
+CONFIG_BLK_CGROUP_PUNT_BIO=y
+CONFIG_BLK_DEV_BSG_COMMON=y
+# CONFIG_BLK_DEV_BSGLIB is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+# CONFIG_BLK_DEV_ZONED is not set
+CONFIG_BLK_DEV_THROTTLING=y
+# CONFIG_BLK_DEV_THROTTLING_LOW is not set
+# CONFIG_BLK_WBT is not set
+# CONFIG_BLK_CGROUP_IOLATENCY is not set
+# CONFIG_BLK_CGROUP_IOCOST is not set
+# CONFIG_BLK_CGROUP_IOPRIO is not set
+# CONFIG_BLK_DEBUG_FS is not set
+# CONFIG_BLK_SED_OPAL is not set
+# CONFIG_BLK_INLINE_ENCRYPTION is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_AIX_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+CONFIG_MAC_PARTITION=y
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+CONFIG_EFI_PARTITION=y
+# CONFIG_SYSV68_PARTITION is not set
+# CONFIG_CMDLINE_PARTITION is not set
+# end of Partition Types
+
+CONFIG_BLK_MQ_VIRTIO=y
+CONFIG_BLK_PM=y
+
+#
+# IO Schedulers
+#
+CONFIG_MQ_IOSCHED_DEADLINE=y
+CONFIG_MQ_IOSCHED_KYBER=y
+# CONFIG_IOSCHED_BFQ is not set
+# end of IO Schedulers
+
+CONFIG_PADATA=y
+CONFIG_ASN1=y
+CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
+CONFIG_INLINE_READ_UNLOCK=y
+CONFIG_INLINE_READ_UNLOCK_IRQ=y
+CONFIG_INLINE_WRITE_UNLOCK=y
+CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
+CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y
+CONFIG_FREEZER=y
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_ELF_FDPIC is not set
+CONFIG_ELFCORE=y
+CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
+CONFIG_BINFMT_SCRIPT=y
+CONFIG_ARCH_HAS_BINFMT_FLAT=y
+# CONFIG_BINFMT_FLAT is not set
+CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
+CONFIG_BINFMT_MISC=m
+CONFIG_COREDUMP=y
+# end of Executable file formats
+
+#
+# Memory Management options
+#
+CONFIG_SWAP=y
+# CONFIG_ZSWAP is not set
+CONFIG_ZSMALLOC=y
+# CONFIG_ZSMALLOC_STAT is not set
+CONFIG_ZSMALLOC_CHAIN_SIZE=8
+
+#
+# SLAB allocator options
+#
+# CONFIG_SLAB_DEPRECATED is not set
+CONFIG_SLUB=y
+CONFIG_SLAB_MERGE_DEFAULT=y
+# CONFIG_SLAB_FREELIST_RANDOM is not set
+# CONFIG_SLAB_FREELIST_HARDENED is not set
+# CONFIG_SLUB_STATS is not set
+CONFIG_SLUB_CPU_PARTIAL=y
+# CONFIG_RANDOM_KMALLOC_CACHES is not set
+# end of SLAB allocator options
+
+# CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set
+# CONFIG_COMPAT_BRK is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_MEMORY_ISOLATION=y
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+CONFIG_MEMORY_BALLOON=y
+CONFIG_BALLOON_COMPACTION=y
+CONFIG_COMPACTION=y
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+CONFIG_PAGE_REPORTING=y
+CONFIG_MIGRATION=y
+CONFIG_CONTIG_ALLOC=y
+CONFIG_PCP_BATCH_SCALE_MAX=5
+CONFIG_BOUNCE=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
+CONFIG_CMA=y
+# CONFIG_CMA_DEBUG is not set
+# CONFIG_CMA_DEBUGFS is not set
+CONFIG_CMA_SYSFS=y
+CONFIG_CMA_AREAS=7
+CONFIG_GENERIC_EARLY_IOREMAP=y
+# CONFIG_IDLE_PAGE_TRACKING is not set
+CONFIG_ARCH_HAS_CURRENT_STACK_POINTER=y
+CONFIG_VM_EVENT_COUNTERS=y
+# CONFIG_PERCPU_STATS is not set
+# CONFIG_GUP_TEST is not set
+# CONFIG_DMAPOOL_TEST is not set
+CONFIG_KMAP_LOCAL=y
+CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y
+CONFIG_MEMFD_CREATE=y
+# CONFIG_ANON_VMA_NAME is not set
+# CONFIG_USERFAULTFD is not set
+CONFIG_LRU_GEN=y
+CONFIG_LRU_GEN_ENABLED=y
+# CONFIG_LRU_GEN_STATS is not set
+CONFIG_LOCK_MM_AND_FIND_VMA=y
+
+#
+# Data Access Monitoring
+#
+# CONFIG_DAMON is not set
+# end of Data Access Monitoring
+# end of Memory Management options
+
+CONFIG_NET=y
+CONFIG_NET_INGRESS=y
+CONFIG_NET_EGRESS=y
+CONFIG_NET_XGRESS=y
+CONFIG_SKB_EXTENSIONS=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_DIAG is not set
+CONFIG_UNIX=y
+CONFIG_UNIX_SCM=y
+CONFIG_AF_UNIX_OOB=y
+# CONFIG_UNIX_DIAG is not set
+# CONFIG_TLS is not set
+CONFIG_XFRM=y
+CONFIG_XFRM_ALGO=y
+CONFIG_XFRM_USER=y
+# CONFIG_XFRM_INTERFACE is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+CONFIG_XFRM_AH=m
+CONFIG_XFRM_ESP=y
+CONFIG_XFRM_IPCOMP=m
+# CONFIG_NET_KEY is not set
+# CONFIG_XDP_SOCKETS is not set
+CONFIG_NET_HANDSHAKE=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+# CONFIG_IP_FIB_TRIE_STATS is not set
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+CONFIG_IP_ROUTE_VERBOSE=y
+CONFIG_IP_ROUTE_CLASSID=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+CONFIG_NET_IPIP=m
+CONFIG_NET_IPGRE_DEMUX=m
+CONFIG_NET_IP_TUNNEL=m
+CONFIG_NET_IPGRE=m
+# CONFIG_NET_IPGRE_BROADCAST is not set
+CONFIG_IP_MROUTE_COMMON=y
+CONFIG_IP_MROUTE=y
+CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
+CONFIG_IP_PIMSM_V1=y
+CONFIG_IP_PIMSM_V2=y
+CONFIG_SYN_COOKIES=y
+CONFIG_NET_IPVTI=m
+CONFIG_NET_UDP_TUNNEL=m
+# CONFIG_NET_FOU is not set
+# CONFIG_NET_FOU_IP_TUNNELS is not set
+CONFIG_INET_AH=m
+CONFIG_INET_ESP=y
+# CONFIG_INET_ESP_OFFLOAD is not set
+# CONFIG_INET_ESPINTCP is not set
+CONFIG_INET_IPCOMP=m
+CONFIG_INET_TABLE_PERTURB_ORDER=16
+CONFIG_INET_XFRM_TUNNEL=m
+CONFIG_INET_TUNNEL=m
+CONFIG_INET_DIAG=m
+CONFIG_INET_TCP_DIAG=m
+# CONFIG_INET_UDP_DIAG is not set
+# CONFIG_INET_RAW_DIAG is not set
+# CONFIG_INET_DIAG_DESTROY is not set
+CONFIG_TCP_CONG_ADVANCED=y
+CONFIG_TCP_CONG_BIC=m
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_TCP_CONG_WESTWOOD=m
+CONFIG_TCP_CONG_HTCP=m
+# CONFIG_TCP_CONG_HSTCP is not set
+# CONFIG_TCP_CONG_HYBLA is not set
+# CONFIG_TCP_CONG_VEGAS is not set
+# CONFIG_TCP_CONG_NV is not set
+# CONFIG_TCP_CONG_SCALABLE is not set
+# CONFIG_TCP_CONG_LP is not set
+# CONFIG_TCP_CONG_VENO is not set
+# CONFIG_TCP_CONG_YEAH is not set
+# CONFIG_TCP_CONG_ILLINOIS is not set
+# CONFIG_TCP_CONG_DCTCP is not set
+# CONFIG_TCP_CONG_CDG is not set
+CONFIG_TCP_CONG_BBR=m
+CONFIG_DEFAULT_CUBIC=y
+# CONFIG_DEFAULT_RENO is not set
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+CONFIG_IPV6=y
+CONFIG_IPV6_ROUTER_PREF=y
+# CONFIG_IPV6_ROUTE_INFO is not set
+CONFIG_IPV6_OPTIMISTIC_DAD=y
+CONFIG_INET6_AH=m
+CONFIG_INET6_ESP=m
+# CONFIG_INET6_ESP_OFFLOAD is not set
+# CONFIG_INET6_ESPINTCP is not set
+CONFIG_INET6_IPCOMP=m
+CONFIG_IPV6_MIP6=m
+# CONFIG_IPV6_ILA is not set
+CONFIG_INET6_XFRM_TUNNEL=m
+CONFIG_INET6_TUNNEL=m
+# CONFIG_IPV6_VTI is not set
+CONFIG_IPV6_SIT=m
+# CONFIG_IPV6_SIT_6RD is not set
+CONFIG_IPV6_NDISC_NODETYPE=y
+CONFIG_IPV6_TUNNEL=m
+# CONFIG_IPV6_GRE is not set
+CONFIG_IPV6_MULTIPLE_TABLES=y
+CONFIG_IPV6_SUBTREES=y
+CONFIG_IPV6_MROUTE=y
+CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y
+CONFIG_IPV6_PIMSM_V2=y
+# CONFIG_IPV6_SEG6_LWTUNNEL is not set
+# CONFIG_IPV6_SEG6_HMAC is not set
+# CONFIG_IPV6_RPL_LWTUNNEL is not set
+# CONFIG_IPV6_IOAM6_LWTUNNEL is not set
+# CONFIG_MPTCP is not set
+# CONFIG_NETWORK_SECMARK is not set
+CONFIG_NET_PTP_CLASSIFY=y
+# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
+CONFIG_NETFILTER=y
+CONFIG_NETFILTER_ADVANCED=y
+CONFIG_BRIDGE_NETFILTER=m
+
+#
+# Core Netfilter Configuration
+#
+CONFIG_NETFILTER_INGRESS=y
+CONFIG_NETFILTER_EGRESS=y
+CONFIG_NETFILTER_SKIP_EGRESS=y
+CONFIG_NETFILTER_NETLINK=m
+CONFIG_NETFILTER_FAMILY_BRIDGE=y
+CONFIG_NETFILTER_FAMILY_ARP=y
+CONFIG_NETFILTER_BPF_LINK=y
+CONFIG_NETFILTER_NETLINK_HOOK=m
+CONFIG_NETFILTER_NETLINK_ACCT=m
+CONFIG_NETFILTER_NETLINK_QUEUE=m
+CONFIG_NETFILTER_NETLINK_LOG=m
+CONFIG_NETFILTER_NETLINK_OSF=m
+CONFIG_NF_CONNTRACK=m
+CONFIG_NF_LOG_SYSLOG=m
+CONFIG_NETFILTER_CONNCOUNT=m
+CONFIG_NF_CONNTRACK_MARK=y
+CONFIG_NF_CONNTRACK_ZONES=y
+CONFIG_NF_CONNTRACK_PROCFS=y
+CONFIG_NF_CONNTRACK_EVENTS=y
+# CONFIG_NF_CONNTRACK_TIMEOUT is not set
+CONFIG_NF_CONNTRACK_TIMESTAMP=y
+CONFIG_NF_CONNTRACK_LABELS=y
+CONFIG_NF_CONNTRACK_OVS=y
+CONFIG_NF_CT_PROTO_DCCP=y
+CONFIG_NF_CT_PROTO_GRE=y
+CONFIG_NF_CT_PROTO_SCTP=y
+CONFIG_NF_CT_PROTO_UDPLITE=y
+CONFIG_NF_CONNTRACK_AMANDA=m
+CONFIG_NF_CONNTRACK_FTP=m
+CONFIG_NF_CONNTRACK_H323=m
+CONFIG_NF_CONNTRACK_IRC=m
+CONFIG_NF_CONNTRACK_BROADCAST=m
+CONFIG_NF_CONNTRACK_NETBIOS_NS=m
+CONFIG_NF_CONNTRACK_SNMP=m
+CONFIG_NF_CONNTRACK_PPTP=m
+CONFIG_NF_CONNTRACK_SANE=m
+CONFIG_NF_CONNTRACK_SIP=m
+CONFIG_NF_CONNTRACK_TFTP=m
+CONFIG_NF_CT_NETLINK=m
+# CONFIG_NETFILTER_NETLINK_GLUE_CT is not set
+CONFIG_NF_NAT=m
+CONFIG_NF_NAT_AMANDA=m
+CONFIG_NF_NAT_FTP=m
+CONFIG_NF_NAT_IRC=m
+CONFIG_NF_NAT_SIP=m
+CONFIG_NF_NAT_TFTP=m
+CONFIG_NF_NAT_REDIRECT=y
+CONFIG_NF_NAT_MASQUERADE=y
+CONFIG_NF_NAT_OVS=y
+CONFIG_NF_TABLES=m
+CONFIG_NF_TABLES_INET=y
+CONFIG_NF_TABLES_NETDEV=y
+CONFIG_NFT_NUMGEN=m
+CONFIG_NFT_CT=m
+CONFIG_NFT_FLOW_OFFLOAD=m
+CONFIG_NFT_CONNLIMIT=m
+CONFIG_NFT_LOG=m
+CONFIG_NFT_LIMIT=m
+CONFIG_NFT_MASQ=m
+CONFIG_NFT_REDIR=m
+CONFIG_NFT_NAT=m
+CONFIG_NFT_TUNNEL=m
+CONFIG_NFT_QUEUE=m
+CONFIG_NFT_QUOTA=m
+CONFIG_NFT_REJECT=m
+CONFIG_NFT_REJECT_INET=m
+CONFIG_NFT_COMPAT=m
+CONFIG_NFT_HASH=m
+CONFIG_NFT_FIB=m
+CONFIG_NFT_FIB_INET=m
+# CONFIG_NFT_XFRM is not set
+CONFIG_NFT_SOCKET=m
+CONFIG_NFT_OSF=m
+CONFIG_NFT_TPROXY=m
+# CONFIG_NFT_SYNPROXY is not set
+CONFIG_NF_DUP_NETDEV=m
+CONFIG_NFT_DUP_NETDEV=m
+CONFIG_NFT_FWD_NETDEV=m
+CONFIG_NFT_FIB_NETDEV=m
+CONFIG_NFT_REJECT_NETDEV=m
+CONFIG_NF_FLOW_TABLE_INET=m
+CONFIG_NF_FLOW_TABLE=m
+CONFIG_NF_FLOW_TABLE_PROCFS=y
+CONFIG_NETFILTER_XTABLES=m
+
+#
+# Xtables combined modules
+#
+CONFIG_NETFILTER_XT_MARK=m
+CONFIG_NETFILTER_XT_CONNMARK=m
+CONFIG_NETFILTER_XT_SET=m
+
+#
+# Xtables targets
+#
+CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
+CONFIG_NETFILTER_XT_TARGET_CT=m
+CONFIG_NETFILTER_XT_TARGET_DSCP=m
+CONFIG_NETFILTER_XT_TARGET_HL=m
+CONFIG_NETFILTER_XT_TARGET_HMARK=m
+CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m
+CONFIG_NETFILTER_XT_TARGET_LED=m
+CONFIG_NETFILTER_XT_TARGET_LOG=m
+CONFIG_NETFILTER_XT_TARGET_MARK=m
+CONFIG_NETFILTER_XT_NAT=m
+CONFIG_NETFILTER_XT_TARGET_NETMAP=m
+CONFIG_NETFILTER_XT_TARGET_NFLOG=m
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
+CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
+CONFIG_NETFILTER_XT_TARGET_RATEEST=m
+CONFIG_NETFILTER_XT_TARGET_REDIRECT=m
+CONFIG_NETFILTER_XT_TARGET_MASQUERADE=m
+CONFIG_NETFILTER_XT_TARGET_TEE=m
+CONFIG_NETFILTER_XT_TARGET_TPROXY=m
+CONFIG_NETFILTER_XT_TARGET_TRACE=m
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
+CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
+
+#
+# Xtables matches
+#
+CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
+CONFIG_NETFILTER_XT_MATCH_BPF=m
+# CONFIG_NETFILTER_XT_MATCH_CGROUP is not set
+CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
+CONFIG_NETFILTER_XT_MATCH_COMMENT=m
+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
+CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m
+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
+CONFIG_NETFILTER_XT_MATCH_CPU=m
+CONFIG_NETFILTER_XT_MATCH_DCCP=m
+CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m
+CONFIG_NETFILTER_XT_MATCH_DSCP=m
+CONFIG_NETFILTER_XT_MATCH_ECN=m
+CONFIG_NETFILTER_XT_MATCH_ESP=m
+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
+CONFIG_NETFILTER_XT_MATCH_HELPER=m
+CONFIG_NETFILTER_XT_MATCH_HL=m
+# CONFIG_NETFILTER_XT_MATCH_IPCOMP is not set
+CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
+CONFIG_NETFILTER_XT_MATCH_IPVS=m
+CONFIG_NETFILTER_XT_MATCH_L2TP=m
+CONFIG_NETFILTER_XT_MATCH_LENGTH=m
+CONFIG_NETFILTER_XT_MATCH_LIMIT=m
+CONFIG_NETFILTER_XT_MATCH_MAC=m
+CONFIG_NETFILTER_XT_MATCH_MARK=m
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
+CONFIG_NETFILTER_XT_MATCH_NFACCT=m
+CONFIG_NETFILTER_XT_MATCH_OSF=m
+CONFIG_NETFILTER_XT_MATCH_OWNER=m
+CONFIG_NETFILTER_XT_MATCH_POLICY=m
+CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
+CONFIG_NETFILTER_XT_MATCH_QUOTA=m
+CONFIG_NETFILTER_XT_MATCH_RATEEST=m
+CONFIG_NETFILTER_XT_MATCH_REALM=m
+CONFIG_NETFILTER_XT_MATCH_RECENT=m
+# CONFIG_NETFILTER_XT_MATCH_SCTP is not set
+CONFIG_NETFILTER_XT_MATCH_SOCKET=m
+CONFIG_NETFILTER_XT_MATCH_STATE=m
+CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
+CONFIG_NETFILTER_XT_MATCH_STRING=m
+CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
+CONFIG_NETFILTER_XT_MATCH_TIME=m
+CONFIG_NETFILTER_XT_MATCH_U32=m
+# end of Core Netfilter Configuration
+
+CONFIG_IP_SET=m
+CONFIG_IP_SET_MAX=256
+CONFIG_IP_SET_BITMAP_IP=m
+CONFIG_IP_SET_BITMAP_IPMAC=m
+CONFIG_IP_SET_BITMAP_PORT=m
+CONFIG_IP_SET_HASH_IP=m
+# CONFIG_IP_SET_HASH_IPMARK is not set
+CONFIG_IP_SET_HASH_IPPORT=m
+CONFIG_IP_SET_HASH_IPPORTIP=m
+CONFIG_IP_SET_HASH_IPPORTNET=m
+# CONFIG_IP_SET_HASH_IPMAC is not set
+# CONFIG_IP_SET_HASH_MAC is not set
+# CONFIG_IP_SET_HASH_NETPORTNET is not set
+CONFIG_IP_SET_HASH_NET=m
+# CONFIG_IP_SET_HASH_NETNET is not set
+CONFIG_IP_SET_HASH_NETPORT=m
+CONFIG_IP_SET_HASH_NETIFACE=m
+CONFIG_IP_SET_LIST_SET=m
+CONFIG_IP_VS=m
+# CONFIG_IP_VS_IPV6 is not set
+# CONFIG_IP_VS_DEBUG is not set
+CONFIG_IP_VS_TAB_BITS=12
+
+#
+# IPVS transport protocol load balancing support
+#
+CONFIG_IP_VS_PROTO_TCP=y
+CONFIG_IP_VS_PROTO_UDP=y
+CONFIG_IP_VS_PROTO_AH_ESP=y
+CONFIG_IP_VS_PROTO_ESP=y
+CONFIG_IP_VS_PROTO_AH=y
+CONFIG_IP_VS_PROTO_SCTP=y
+
+#
+# IPVS scheduler
+#
+CONFIG_IP_VS_RR=m
+CONFIG_IP_VS_WRR=m
+CONFIG_IP_VS_LC=m
+CONFIG_IP_VS_WLC=m
+# CONFIG_IP_VS_FO is not set
+# CONFIG_IP_VS_OVF is not set
+CONFIG_IP_VS_LBLC=m
+CONFIG_IP_VS_LBLCR=m
+CONFIG_IP_VS_DH=m
+CONFIG_IP_VS_SH=m
+# CONFIG_IP_VS_MH is not set
+CONFIG_IP_VS_SED=m
+CONFIG_IP_VS_NQ=m
+# CONFIG_IP_VS_TWOS is not set
+
+#
+# IPVS SH scheduler
+#
+CONFIG_IP_VS_SH_TAB_BITS=8
+
+#
+# IPVS MH scheduler
+#
+CONFIG_IP_VS_MH_TAB_INDEX=12
+
+#
+# IPVS application helper
+#
+CONFIG_IP_VS_FTP=m
+CONFIG_IP_VS_NFCT=y
+CONFIG_IP_VS_PE_SIP=m
+
+#
+# IP: Netfilter Configuration
+#
+CONFIG_NF_DEFRAG_IPV4=m
+CONFIG_NF_SOCKET_IPV4=m
+CONFIG_NF_TPROXY_IPV4=m
+CONFIG_NF_TABLES_IPV4=y
+CONFIG_NFT_REJECT_IPV4=m
+CONFIG_NFT_DUP_IPV4=m
+CONFIG_NFT_FIB_IPV4=m
+CONFIG_NF_TABLES_ARP=y
+CONFIG_NF_DUP_IPV4=m
+# CONFIG_NF_LOG_ARP is not set
+CONFIG_NF_LOG_IPV4=m
+CONFIG_NF_REJECT_IPV4=m
+CONFIG_NF_NAT_SNMP_BASIC=m
+CONFIG_NF_NAT_PPTP=m
+CONFIG_NF_NAT_H323=m
+CONFIG_IP_NF_IPTABLES=m
+CONFIG_IP_NF_MATCH_AH=m
+CONFIG_IP_NF_MATCH_ECN=m
+CONFIG_IP_NF_MATCH_RPFILTER=m
+CONFIG_IP_NF_MATCH_TTL=m
+CONFIG_IP_NF_FILTER=m
+CONFIG_IP_NF_TARGET_REJECT=m
+# CONFIG_IP_NF_TARGET_SYNPROXY is not set
+CONFIG_IP_NF_NAT=m
+CONFIG_IP_NF_TARGET_MASQUERADE=m
+CONFIG_IP_NF_TARGET_NETMAP=m
+CONFIG_IP_NF_TARGET_REDIRECT=m
+CONFIG_IP_NF_MANGLE=m
+CONFIG_IP_NF_TARGET_ECN=m
+CONFIG_IP_NF_TARGET_TTL=m
+CONFIG_IP_NF_RAW=m
+CONFIG_IP_NF_ARPTABLES=m
+CONFIG_IP_NF_ARPFILTER=m
+CONFIG_IP_NF_ARP_MANGLE=m
+# end of IP: Netfilter Configuration
+
+#
+# IPv6: Netfilter Configuration
+#
+CONFIG_NF_SOCKET_IPV6=m
+CONFIG_NF_TPROXY_IPV6=m
+CONFIG_NF_TABLES_IPV6=y
+CONFIG_NFT_REJECT_IPV6=m
+CONFIG_NFT_DUP_IPV6=m
+CONFIG_NFT_FIB_IPV6=m
+CONFIG_NF_DUP_IPV6=m
+CONFIG_NF_REJECT_IPV6=m
+CONFIG_NF_LOG_IPV6=m
+CONFIG_IP6_NF_IPTABLES=m
+CONFIG_IP6_NF_MATCH_AH=m
+CONFIG_IP6_NF_MATCH_EUI64=m
+CONFIG_IP6_NF_MATCH_FRAG=m
+CONFIG_IP6_NF_MATCH_OPTS=m
+CONFIG_IP6_NF_MATCH_HL=m
+CONFIG_IP6_NF_MATCH_IPV6HEADER=m
+CONFIG_IP6_NF_MATCH_MH=m
+CONFIG_IP6_NF_MATCH_RPFILTER=m
+CONFIG_IP6_NF_MATCH_RT=m
+# CONFIG_IP6_NF_MATCH_SRH is not set
+CONFIG_IP6_NF_TARGET_HL=m
+CONFIG_IP6_NF_FILTER=m
+CONFIG_IP6_NF_TARGET_REJECT=m
+# CONFIG_IP6_NF_TARGET_SYNPROXY is not set
+CONFIG_IP6_NF_MANGLE=m
+CONFIG_IP6_NF_RAW=m
+CONFIG_IP6_NF_NAT=m
+CONFIG_IP6_NF_TARGET_MASQUERADE=m
+CONFIG_IP6_NF_TARGET_NPT=m
+# end of IPv6: Netfilter Configuration
+
+CONFIG_NF_DEFRAG_IPV6=m
+CONFIG_NF_TABLES_BRIDGE=m
+# CONFIG_NFT_BRIDGE_META is not set
+CONFIG_NFT_BRIDGE_REJECT=m
+# CONFIG_NF_CONNTRACK_BRIDGE is not set
+CONFIG_BRIDGE_NF_EBTABLES=m
+CONFIG_BRIDGE_EBT_BROUTE=m
+CONFIG_BRIDGE_EBT_T_FILTER=m
+CONFIG_BRIDGE_EBT_T_NAT=m
+CONFIG_BRIDGE_EBT_802_3=m
+CONFIG_BRIDGE_EBT_AMONG=m
+CONFIG_BRIDGE_EBT_ARP=m
+CONFIG_BRIDGE_EBT_IP=m
+CONFIG_BRIDGE_EBT_IP6=m
+CONFIG_BRIDGE_EBT_LIMIT=m
+CONFIG_BRIDGE_EBT_MARK=m
+CONFIG_BRIDGE_EBT_PKTTYPE=m
+CONFIG_BRIDGE_EBT_STP=m
+CONFIG_BRIDGE_EBT_VLAN=m
+CONFIG_BRIDGE_EBT_ARPREPLY=m
+CONFIG_BRIDGE_EBT_DNAT=m
+CONFIG_BRIDGE_EBT_MARK_T=m
+CONFIG_BRIDGE_EBT_REDIRECT=m
+CONFIG_BRIDGE_EBT_SNAT=m
+CONFIG_BRIDGE_EBT_LOG=m
+CONFIG_BRIDGE_EBT_NFLOG=m
+# CONFIG_BPFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_RDS is not set
+# CONFIG_TIPC is not set
+CONFIG_ATM=m
+# CONFIG_ATM_CLIP is not set
+# CONFIG_ATM_LANE is not set
+# CONFIG_ATM_BR2684 is not set
+CONFIG_L2TP=m
+# CONFIG_L2TP_DEBUGFS is not set
+CONFIG_L2TP_V3=y
+CONFIG_L2TP_IP=m
+CONFIG_L2TP_ETH=m
+CONFIG_STP=m
+CONFIG_GARP=m
+CONFIG_BRIDGE=m
+CONFIG_BRIDGE_IGMP_SNOOPING=y
+CONFIG_BRIDGE_VLAN_FILTERING=y
+# CONFIG_BRIDGE_MRP is not set
+# CONFIG_BRIDGE_CFM is not set
+CONFIG_NET_DSA=m
+# CONFIG_NET_DSA_TAG_NONE is not set
+# CONFIG_NET_DSA_TAG_AR9331 is not set
+CONFIG_NET_DSA_TAG_BRCM_COMMON=m
+CONFIG_NET_DSA_TAG_BRCM=m
+CONFIG_NET_DSA_TAG_BRCM_LEGACY=m
+CONFIG_NET_DSA_TAG_BRCM_PREPEND=m
+CONFIG_NET_DSA_TAG_HELLCREEK=m
+# CONFIG_NET_DSA_TAG_GSWIP is not set
+# CONFIG_NET_DSA_TAG_DSA is not set
+# CONFIG_NET_DSA_TAG_EDSA is not set
+# CONFIG_NET_DSA_TAG_MTK is not set
+CONFIG_NET_DSA_TAG_KSZ=m
+# CONFIG_NET_DSA_TAG_OCELOT is not set
+# CONFIG_NET_DSA_TAG_OCELOT_8021Q is not set
+# CONFIG_NET_DSA_TAG_QCA is not set
+# CONFIG_NET_DSA_TAG_RTL4_A is not set
+# CONFIG_NET_DSA_TAG_RTL8_4 is not set
+# CONFIG_NET_DSA_TAG_RZN1_A5PSW is not set
+# CONFIG_NET_DSA_TAG_LAN9303 is not set
+# CONFIG_NET_DSA_TAG_SJA1105 is not set
+# CONFIG_NET_DSA_TAG_TRAILER is not set
+# CONFIG_NET_DSA_TAG_XRS700X is not set
+CONFIG_VLAN_8021Q=m
+CONFIG_VLAN_8021Q_GVRP=y
+# CONFIG_VLAN_8021Q_MVRP is not set
+CONFIG_LLC=m
+# CONFIG_LLC2 is not set
+CONFIG_ATALK=m
+# CONFIG_DEV_APPLETALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_PHONET is not set
+CONFIG_6LOWPAN=m
+# CONFIG_6LOWPAN_DEBUGFS is not set
+CONFIG_6LOWPAN_NHC=m
+CONFIG_6LOWPAN_NHC_DEST=m
+CONFIG_6LOWPAN_NHC_FRAGMENT=m
+CONFIG_6LOWPAN_NHC_HOP=m
+CONFIG_6LOWPAN_NHC_IPV6=m
+CONFIG_6LOWPAN_NHC_MOBILITY=m
+CONFIG_6LOWPAN_NHC_ROUTING=m
+CONFIG_6LOWPAN_NHC_UDP=m
+# CONFIG_6LOWPAN_GHC_EXT_HDR_HOP is not set
+# CONFIG_6LOWPAN_GHC_UDP is not set
+# CONFIG_6LOWPAN_GHC_ICMPV6 is not set
+# CONFIG_6LOWPAN_GHC_EXT_HDR_DEST is not set
+# CONFIG_6LOWPAN_GHC_EXT_HDR_FRAG is not set
+# CONFIG_6LOWPAN_GHC_EXT_HDR_ROUTE is not set
+CONFIG_IEEE802154=m
+# CONFIG_IEEE802154_NL802154_EXPERIMENTAL is not set
+CONFIG_IEEE802154_SOCKET=m
+CONFIG_IEEE802154_6LOWPAN=m
+CONFIG_MAC802154=m
+CONFIG_NET_SCHED=y
+
+#
+# Queueing/Scheduling
+#
+CONFIG_NET_SCH_HTB=m
+CONFIG_NET_SCH_HFSC=m
+CONFIG_NET_SCH_PRIO=m
+CONFIG_NET_SCH_MULTIQ=m
+CONFIG_NET_SCH_RED=m
+CONFIG_NET_SCH_SFB=m
+CONFIG_NET_SCH_SFQ=m
+CONFIG_NET_SCH_TEQL=m
+CONFIG_NET_SCH_TBF=m
+# CONFIG_NET_SCH_CBS is not set
+# CONFIG_NET_SCH_ETF is not set
+CONFIG_NET_SCH_MQPRIO_LIB=m
+# CONFIG_NET_SCH_TAPRIO is not set
+CONFIG_NET_SCH_GRED=m
+CONFIG_NET_SCH_NETEM=m
+CONFIG_NET_SCH_DRR=m
+CONFIG_NET_SCH_MQPRIO=m
+# CONFIG_NET_SCH_SKBPRIO is not set
+CONFIG_NET_SCH_CHOKE=m
+CONFIG_NET_SCH_QFQ=m
+CONFIG_NET_SCH_CODEL=m
+CONFIG_NET_SCH_FQ_CODEL=m
+CONFIG_NET_SCH_CAKE=m
+CONFIG_NET_SCH_FQ=m
+CONFIG_NET_SCH_HHF=m
+CONFIG_NET_SCH_PIE=m
+# CONFIG_NET_SCH_FQ_PIE is not set
+CONFIG_NET_SCH_INGRESS=m
+CONFIG_NET_SCH_PLUG=m
+# CONFIG_NET_SCH_ETS is not set
+# CONFIG_NET_SCH_DEFAULT is not set
+
+#
+# Classification
+#
+CONFIG_NET_CLS=y
+CONFIG_NET_CLS_BASIC=m
+CONFIG_NET_CLS_ROUTE4=m
+CONFIG_NET_CLS_FW=m
+CONFIG_NET_CLS_U32=m
+# CONFIG_CLS_U32_PERF is not set
+CONFIG_CLS_U32_MARK=y
+CONFIG_NET_CLS_FLOW=m
+CONFIG_NET_CLS_CGROUP=m
+# CONFIG_NET_CLS_BPF is not set
+# CONFIG_NET_CLS_FLOWER is not set
+# CONFIG_NET_CLS_MATCHALL is not set
+CONFIG_NET_EMATCH=y
+CONFIG_NET_EMATCH_STACK=32
+CONFIG_NET_EMATCH_CMP=m
+CONFIG_NET_EMATCH_NBYTE=m
+CONFIG_NET_EMATCH_U32=m
+CONFIG_NET_EMATCH_META=m
+CONFIG_NET_EMATCH_TEXT=m
+CONFIG_NET_EMATCH_IPSET=m
+# CONFIG_NET_EMATCH_IPT is not set
+CONFIG_NET_CLS_ACT=y
+CONFIG_NET_ACT_POLICE=m
+CONFIG_NET_ACT_GACT=m
+CONFIG_GACT_PROB=y
+CONFIG_NET_ACT_MIRRED=m
+# CONFIG_NET_ACT_SAMPLE is not set
+CONFIG_NET_ACT_IPT=m
+CONFIG_NET_ACT_NAT=m
+CONFIG_NET_ACT_PEDIT=m
+CONFIG_NET_ACT_SIMP=m
+CONFIG_NET_ACT_SKBEDIT=m
+CONFIG_NET_ACT_CSUM=m
+# CONFIG_NET_ACT_MPLS is not set
+# CONFIG_NET_ACT_VLAN is not set
+# CONFIG_NET_ACT_BPF is not set
+# CONFIG_NET_ACT_CONNMARK is not set
+# CONFIG_NET_ACT_CTINFO is not set
+# CONFIG_NET_ACT_SKBMOD is not set
+# CONFIG_NET_ACT_IFE is not set
+# CONFIG_NET_ACT_TUNNEL_KEY is not set
+# CONFIG_NET_ACT_CT is not set
+# CONFIG_NET_ACT_GATE is not set
+# CONFIG_NET_TC_SKB_EXT is not set
+CONFIG_NET_SCH_FIFO=y
+# CONFIG_DCB is not set
+CONFIG_DNS_RESOLVER=y
+CONFIG_BATMAN_ADV=m
+CONFIG_BATMAN_ADV_BATMAN_V=y
+CONFIG_BATMAN_ADV_BLA=y
+CONFIG_BATMAN_ADV_DAT=y
+# CONFIG_BATMAN_ADV_NC is not set
+CONFIG_BATMAN_ADV_MCAST=y
+# CONFIG_BATMAN_ADV_DEBUG is not set
+CONFIG_OPENVSWITCH=m
+CONFIG_OPENVSWITCH_GRE=m
+CONFIG_OPENVSWITCH_VXLAN=m
+# CONFIG_VSOCKETS is not set
+# CONFIG_NETLINK_DIAG is not set
+CONFIG_MPLS=y
+CONFIG_NET_MPLS_GSO=m
+# CONFIG_MPLS_ROUTING is not set
+CONFIG_NET_NSH=m
+# CONFIG_HSR is not set
+CONFIG_NET_SWITCHDEV=y
+CONFIG_NET_L3_MASTER_DEV=y
+# CONFIG_QRTR is not set
+# CONFIG_NET_NCSI is not set
+CONFIG_PCPU_DEV_REFCNT=y
+CONFIG_MAX_SKB_FRAGS=17
+CONFIG_RPS=y
+CONFIG_RFS_ACCEL=y
+CONFIG_SOCK_RX_QUEUE_MAPPING=y
+CONFIG_XPS=y
+CONFIG_CGROUP_NET_PRIO=y
+CONFIG_CGROUP_NET_CLASSID=y
+CONFIG_NET_RX_BUSY_POLL=y
+CONFIG_BQL=y
+# CONFIG_BPF_STREAM_PARSER is not set
+CONFIG_NET_FLOW_LIMIT=y
+
+#
+# Network testing
+#
+CONFIG_NET_PKTGEN=m
+# end of Network testing
+# end of Networking options
+
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+CONFIG_BT=y
+CONFIG_BT_BREDR=y
+CONFIG_BT_RFCOMM=y
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=y
+CONFIG_BT_BNEP_MC_FILTER=y
+CONFIG_BT_BNEP_PROTO_FILTER=y
+CONFIG_BT_HIDP=y
+CONFIG_BT_HS=y
+CONFIG_BT_LE=y
+CONFIG_BT_LE_L2CAP_ECRED=y
+# CONFIG_BT_6LOWPAN is not set
+# CONFIG_BT_LEDS is not set
+CONFIG_BT_MSFTEXT=y
+# CONFIG_BT_AOSPEXT is not set
+CONFIG_BT_DEBUGFS=y
+# CONFIG_BT_SELFTEST is not set
+
+#
+# Bluetooth device drivers
+#
+CONFIG_BT_INTEL=m
+CONFIG_BT_BCM=m
+CONFIG_BT_RTL=m
+CONFIG_BT_QCA=m
+CONFIG_BT_MTK=m
+CONFIG_BT_HCIBTUSB=m
+# CONFIG_BT_HCIBTUSB_AUTOSUSPEND is not set
+CONFIG_BT_HCIBTUSB_POLL_SYNC=y
+CONFIG_BT_HCIBTUSB_BCM=y
+CONFIG_BT_HCIBTUSB_MTK=y
+CONFIG_BT_HCIBTUSB_RTL=y
+CONFIG_BT_HCIBTSDIO=m
+CONFIG_BT_HCIUART=m
+CONFIG_BT_HCIUART_SERDEV=y
+CONFIG_BT_HCIUART_H4=y
+CONFIG_BT_HCIUART_NOKIA=m
+CONFIG_BT_HCIUART_BCSP=y
+CONFIG_BT_HCIUART_ATH3K=y
+CONFIG_BT_HCIUART_LL=y
+CONFIG_BT_HCIUART_3WIRE=y
+CONFIG_BT_HCIUART_INTEL=y
+CONFIG_BT_HCIUART_BCM=y
+CONFIG_BT_HCIUART_RTL=y
+CONFIG_BT_HCIUART_QCA=y
+CONFIG_BT_HCIUART_AG6XX=y
+CONFIG_BT_HCIUART_MRVL=y
+CONFIG_BT_HCIBCM203X=m
+CONFIG_BT_HCIBPA10X=m
+CONFIG_BT_HCIBFUSB=m
+CONFIG_BT_HCIVHCI=m
+CONFIG_BT_MRVL=m
+CONFIG_BT_MRVL_SDIO=m
+CONFIG_BT_ATH3K=m
+CONFIG_BT_MTKSDIO=m
+CONFIG_BT_MTKUART=m
+CONFIG_BT_HCIRSI=m
+CONFIG_BT_VIRTIO=m
+CONFIG_BT_NXPUART=m
+# end of Bluetooth device drivers
+
+CONFIG_AF_RXRPC=m
+# CONFIG_AF_RXRPC_IPV6 is not set
+# CONFIG_AF_RXRPC_INJECT_LOSS is not set
+# CONFIG_AF_RXRPC_INJECT_RX_DELAY is not set
+# CONFIG_AF_RXRPC_DEBUG is not set
+# CONFIG_RXKAD is not set
+# CONFIG_RXPERF is not set
+# CONFIG_AF_KCM is not set
+# CONFIG_MCTP is not set
+CONFIG_FIB_RULES=y
+CONFIG_WIRELESS=y
+CONFIG_WIRELESS_EXT=y
+CONFIG_WEXT_CORE=y
+CONFIG_WEXT_PROC=y
+CONFIG_WEXT_PRIV=y
+CONFIG_CFG80211=m
+# CONFIG_NL80211_TESTMODE is not set
+# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
+CONFIG_CFG80211_REQUIRE_SIGNED_REGDB=y
+CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y
+CONFIG_CFG80211_DEFAULT_PS=y
+# CONFIG_CFG80211_DEBUGFS is not set
+CONFIG_CFG80211_CRDA_SUPPORT=y
+CONFIG_CFG80211_WEXT=y
+CONFIG_LIB80211=m
+# CONFIG_LIB80211_DEBUG is not set
+CONFIG_MAC80211=m
+CONFIG_MAC80211_HAS_RC=y
+CONFIG_MAC80211_RC_MINSTREL=y
+CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
+CONFIG_MAC80211_RC_DEFAULT="minstrel_ht"
+# CONFIG_MAC80211_MESH is not set
+CONFIG_MAC80211_LEDS=y
+# CONFIG_MAC80211_DEBUGFS is not set
+# CONFIG_MAC80211_MESSAGE_TRACING is not set
+# CONFIG_MAC80211_DEBUG_MENU is not set
+CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
+CONFIG_RFKILL=y
+CONFIG_RFKILL_LEDS=y
+CONFIG_RFKILL_INPUT=y
+CONFIG_RFKILL_GPIO=m
+# CONFIG_NET_9P is not set
+# CONFIG_CAIF is not set
+# CONFIG_CEPH_LIB is not set
+# CONFIG_NFC is not set
+# CONFIG_PSAMPLE is not set
+# CONFIG_NET_IFE is not set
+# CONFIG_LWTUNNEL is not set
+CONFIG_DST_CACHE=y
+CONFIG_GRO_CELLS=y
+CONFIG_NET_SELFTESTS=y
+CONFIG_NET_SOCK_MSG=y
+CONFIG_NET_DEVLINK=y
+CONFIG_PAGE_POOL=y
+# CONFIG_PAGE_POOL_STATS is not set
+CONFIG_FAILOVER=y
+CONFIG_ETHTOOL_NETLINK=y
+
+#
+# Device Drivers
+#
+CONFIG_ARM_AMBA=y
+CONFIG_HAVE_PCI=y
+# CONFIG_PCI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Generic Driver Options
+#
+# CONFIG_UEVENT_HELPER is not set
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_DEVTMPFS_SAFE is not set
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+
+#
+# Firmware loader
+#
+CONFIG_FW_LOADER=y
+CONFIG_FW_LOADER_DEBUG=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_FW_LOADER_USER_HELPER is not set
+# CONFIG_FW_LOADER_COMPRESS is not set
+CONFIG_FW_CACHE=y
+# CONFIG_FW_UPLOAD is not set
+# end of Firmware loader
+
+CONFIG_WANT_DEV_COREDUMP=y
+CONFIG_ALLOW_DEV_COREDUMP=y
+CONFIG_DEV_COREDUMP=y
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set
+# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_CPU_VULNERABILITIES=y
+CONFIG_SOC_BUS=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_I2C=y
+CONFIG_REGMAP_SPI=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_REGMAP_IRQ=y
+CONFIG_DMA_SHARED_BUFFER=y
+# CONFIG_DMA_FENCE_TRACE is not set
+CONFIG_GENERIC_ARCH_TOPOLOGY=y
+# CONFIG_FW_DEVLINK_SYNC_STATE_TIMEOUT is not set
+# end of Generic Driver Options
+
+#
+# Bus devices
+#
+# CONFIG_BRCMSTB_GISB_ARB is not set
+# CONFIG_MOXTET is not set
+# CONFIG_VEXPRESS_CONFIG is not set
+# CONFIG_MHI_BUS is not set
+# CONFIG_MHI_BUS_EP is not set
+# end of Bus devices
+
+#
+# Cache Drivers
+#
+# end of Cache Drivers
+
+# CONFIG_CONNECTOR is not set
+
+#
+# Firmware Drivers
+#
+
+#
+# ARM System Control and Management Interface Protocol
+#
+CONFIG_ARM_SCMI_PROTOCOL=y
+# CONFIG_ARM_SCMI_RAW_MODE_SUPPORT is not set
+CONFIG_ARM_SCMI_HAVE_TRANSPORT=y
+CONFIG_ARM_SCMI_HAVE_SHMEM=y
+CONFIG_ARM_SCMI_HAVE_MSG=y
+# CONFIG_ARM_SCMI_TRANSPORT_MAILBOX is not set
+CONFIG_ARM_SCMI_TRANSPORT_OPTEE=y
+CONFIG_ARM_SCMI_TRANSPORT_SMC=y
+# CONFIG_ARM_SCMI_TRANSPORT_SMC_ATOMIC_ENABLE is not set
+# CONFIG_ARM_SCMI_TRANSPORT_VIRTIO is not set
+CONFIG_ARM_SCMI_POWER_DOMAIN=y
+CONFIG_ARM_SCMI_POWER_CONTROL=y
+# end of ARM System Control and Management Interface Protocol
+
+CONFIG_ARM_SCPI_PROTOCOL=m
+CONFIG_ARM_SCPI_POWER_DOMAIN=m
+# CONFIG_FW_CFG_SYSFS is not set
+# CONFIG_TRUSTED_FOUNDATIONS is not set
+# CONFIG_GOOGLE_FIRMWARE is not set
+CONFIG_ARM_PSCI_FW=y
+CONFIG_HAVE_ARM_SMCCC=y
+CONFIG_HAVE_ARM_SMCCC_DISCOVERY=y
+CONFIG_ARM_SMCCC_SOC_ID=y
+
+#
+# Tegra firmware driver
+#
+# end of Tegra firmware driver
+# end of Firmware Drivers
+
+# CONFIG_GNSS is not set
+# CONFIG_MTD is not set
+CONFIG_DTC=y
+CONFIG_OF=y
+# CONFIG_OF_UNITTEST is not set
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_DYNAMIC=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_RESERVED_MEM=y
+CONFIG_OF_RESOLVE=y
+CONFIG_OF_OVERLAY=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_NULL_BLK is not set
+CONFIG_CDROM=m
+CONFIG_ZRAM=y
+# CONFIG_ZRAM_DEF_COMP_LZORLE is not set
+# CONFIG_ZRAM_DEF_COMP_ZSTD is not set
+CONFIG_ZRAM_DEF_COMP_LZ4=y
+# CONFIG_ZRAM_DEF_COMP_LZO is not set
+CONFIG_ZRAM_DEF_COMP="lz4"
+# CONFIG_ZRAM_WRITEBACK is not set
+# CONFIG_ZRAM_MEMORY_TRACKING is not set
+CONFIG_ZRAM_MULTI_COMP=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_LOOP_MIN_COUNT=8
+# CONFIG_BLK_DEV_DRBD is not set
+CONFIG_BLK_DEV_NBD=m
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+CONFIG_VIRTIO_BLK=y
+# CONFIG_BLK_DEV_RBD is not set
+# CONFIG_BLK_DEV_UBLK is not set
+
+#
+# NVME Support
+#
+# CONFIG_NVME_FC is not set
+# CONFIG_NVME_TCP is not set
+# CONFIG_NVME_TARGET is not set
+# end of NVME Support
+
+#
+# Misc devices
+#
+# CONFIG_AD525X_DPOT is not set
+# CONFIG_DUMMY_IRQ is not set
+# CONFIG_ICS932S401 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_HI6421V600_IRQ is not set
+# CONFIG_APDS9802ALS is not set
+# CONFIG_ISL29003 is not set
+# CONFIG_ISL29020 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_SENSORS_BH1770 is not set
+# CONFIG_SENSORS_APDS990X is not set
+# CONFIG_HMC6352 is not set
+# CONFIG_DS1682 is not set
+# CONFIG_LATTICE_ECP3_CONFIG is not set
+CONFIG_SRAM=y
+CONFIG_SRAM_EXEC=y
+# CONFIG_XILINX_SDFEC is not set
+CONFIG_MISC_RTSX=m
+# CONFIG_HISI_HIKEY_USB is not set
+# CONFIG_OPEN_DICE is not set
+# CONFIG_VCPU_STALL_DETECTOR is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_AT24 is not set
+CONFIG_EEPROM_AT25=m
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_MAX6875 is not set
+CONFIG_EEPROM_93CX6=m
+# CONFIG_EEPROM_93XX46 is not set
+# CONFIG_EEPROM_IDT_89HPESX is not set
+# CONFIG_EEPROM_EE1004 is not set
+# end of EEPROM support
+
+#
+# Texas Instruments shared transport line discipline
+#
+# CONFIG_TI_ST is not set
+# end of Texas Instruments shared transport line discipline
+
+# CONFIG_SENSORS_LIS3_SPI is not set
+# CONFIG_SENSORS_LIS3_I2C is not set
+# CONFIG_ALTERA_STAPL is not set
+# CONFIG_ECHO is not set
+CONFIG_MISC_RTSX_USB=m
+# CONFIG_UACCE is not set
+# CONFIG_PVPANIC is not set
+# end of Misc devices
+
+#
+# SCSI device support
+#
+CONFIG_SCSI_MOD=y
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI_COMMON=y
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_PROC_FS is not set
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=m
+# CONFIG_CHR_DEV_ST is not set
+CONFIG_BLK_DEV_SR=m
+CONFIG_CHR_DEV_SG=m
+CONFIG_BLK_DEV_BSG=y
+# CONFIG_CHR_DEV_SCH is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+# end of SCSI Transports
+
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_DH is not set
+# end of SCSI device support
+
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+# CONFIG_TARGET_CORE is not set
+CONFIG_NETDEVICES=y
+CONFIG_MII=y
+CONFIG_NET_CORE=y
+# CONFIG_BONDING is not set
+CONFIG_DUMMY=m
+CONFIG_WIREGUARD=m
+# CONFIG_WIREGUARD_DEBUG is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_IFB is not set
+# CONFIG_NET_TEAM is not set
+CONFIG_MACVLAN=m
+CONFIG_MACVTAP=m
+CONFIG_IPVLAN_L3S=y
+CONFIG_IPVLAN=m
+CONFIG_IPVTAP=m
+CONFIG_VXLAN=m
+# CONFIG_GENEVE is not set
+# CONFIG_BAREUDP is not set
+# CONFIG_GTP is not set
+CONFIG_AMT=m
+# CONFIG_MACSEC is not set
+# CONFIG_NETCONSOLE is not set
+CONFIG_TUN=m
+CONFIG_TAP=m
+# CONFIG_TUN_VNET_CROSS_LE is not set
+CONFIG_VETH=m
+CONFIG_VIRTIO_NET=y
+CONFIG_NLMON=m
+CONFIG_NET_VRF=m
+# CONFIG_ATM_DRIVERS is not set
+
+#
+# Distributed Switch Architecture drivers
+#
+# CONFIG_B53 is not set
+# CONFIG_NET_DSA_BCM_SF2 is not set
+# CONFIG_NET_DSA_LOOP is not set
+# CONFIG_NET_DSA_LANTIQ_GSWIP is not set
+# CONFIG_NET_DSA_MT7530 is not set
+# CONFIG_NET_DSA_MV88E6060 is not set
+# CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON is not set
+# CONFIG_NET_DSA_MV88E6XXX is not set
+# CONFIG_NET_DSA_AR9331 is not set
+# CONFIG_NET_DSA_QCA8K is not set
+# CONFIG_NET_DSA_SJA1105 is not set
+# CONFIG_NET_DSA_XRS700X_I2C is not set
+# CONFIG_NET_DSA_XRS700X_MDIO is not set
+# CONFIG_NET_DSA_REALTEK is not set
+# CONFIG_NET_DSA_SMSC_LAN9303_I2C is not set
+# CONFIG_NET_DSA_SMSC_LAN9303_MDIO is not set
+# CONFIG_NET_DSA_VITESSE_VSC73XX_SPI is not set
+# CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM is not set
+# end of Distributed Switch Architecture drivers
+
+CONFIG_ETHERNET=y
+# CONFIG_NET_VENDOR_ALACRITECH is not set
+# CONFIG_ALTERA_TSE is not set
+# CONFIG_NET_VENDOR_AMAZON is not set
+# CONFIG_NET_VENDOR_AQUANTIA is not set
+# CONFIG_NET_VENDOR_ARC is not set
+# CONFIG_NET_VENDOR_ASIX is not set
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CADENCE is not set
+# CONFIG_NET_VENDOR_CAVIUM is not set
+# CONFIG_NET_VENDOR_CIRRUS is not set
+# CONFIG_NET_VENDOR_CORTINA is not set
+# CONFIG_NET_VENDOR_DAVICOM is not set
+# CONFIG_DNET is not set
+# CONFIG_NET_VENDOR_ENGLEDER is not set
+# CONFIG_NET_VENDOR_EZCHIP is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_FUNGIBLE is not set
+# CONFIG_NET_VENDOR_GOOGLE is not set
+# CONFIG_NET_VENDOR_HISILICON is not set
+# CONFIG_NET_VENDOR_HUAWEI is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_ADI is not set
+# CONFIG_NET_VENDOR_LITEX is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MELLANOX is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_MICROCHIP is not set
+# CONFIG_NET_VENDOR_MICROSEMI is not set
+# CONFIG_NET_VENDOR_MICROSOFT is not set
+# CONFIG_NET_VENDOR_NI is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_NETRONOME is not set
+# CONFIG_ETHOC is not set
+# CONFIG_NET_VENDOR_PENSANDO is not set
+# CONFIG_NET_VENDOR_QUALCOMM is not set
+# CONFIG_NET_VENDOR_RENESAS is not set
+# CONFIG_NET_VENDOR_ROCKER is not set
+# CONFIG_NET_VENDOR_SAMSUNG is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SOLARFLARE is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_SOCIONEXT is not set
+CONFIG_NET_VENDOR_STMICRO=y
+CONFIG_STMMAC_ETH=y
+# CONFIG_STMMAC_SELFTESTS is not set
+CONFIG_STMMAC_PLATFORM=y
+CONFIG_DWMAC_DWC_QOS_ETH=y
+CONFIG_DWMAC_GENERIC=y
+CONFIG_DWMAC_ROCKCHIP=y
+# CONFIG_DWMAC_INTEL_PLAT is not set
+# CONFIG_NET_VENDOR_SYNOPSYS is not set
+# CONFIG_NET_VENDOR_VERTEXCOM is not set
+# CONFIG_NET_VENDOR_VIA is not set
+# CONFIG_NET_VENDOR_WANGXUN is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
+# CONFIG_NET_VENDOR_XILINX is not set
+CONFIG_PHYLINK=y
+CONFIG_PHYLIB=y
+CONFIG_SWPHY=y
+# CONFIG_LED_TRIGGER_PHY is not set
+CONFIG_PHYLIB_LEDS=y
+CONFIG_FIXED_PHY=y
+# CONFIG_SFP is not set
+
+#
+# MII PHY device drivers
+#
+# CONFIG_AMD_PHY is not set
+# CONFIG_ADIN_PHY is not set
+# CONFIG_ADIN1100_PHY is not set
+# CONFIG_AQUANTIA_PHY is not set
+CONFIG_AX88796B_PHY=m
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_BCM54140_PHY is not set
+# CONFIG_BCM7XXX_PHY is not set
+# CONFIG_BCM84881_PHY is not set
+# CONFIG_BCM87XX_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_CORTINA_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_INTEL_XWAY_PHY is not set
+# CONFIG_LSI_ET1011C_PHY is not set
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_MARVELL_10G_PHY is not set
+# CONFIG_MARVELL_88Q2XXX_PHY is not set
+# CONFIG_MARVELL_88X2222_PHY is not set
+# CONFIG_MAXLINEAR_GPHY is not set
+# CONFIG_MEDIATEK_GE_PHY is not set
+# CONFIG_MICREL_PHY is not set
+# CONFIG_MICROCHIP_T1S_PHY is not set
+CONFIG_MICROCHIP_PHY=m
+# CONFIG_MICROCHIP_T1_PHY is not set
+# CONFIG_MICROSEMI_PHY is not set
+# CONFIG_MOTORCOMM_PHY is not set
+# CONFIG_NATIONAL_PHY is not set
+# CONFIG_NXP_CBTX_PHY is not set
+# CONFIG_NXP_C45_TJA11XX_PHY is not set
+# CONFIG_NXP_TJA11XX_PHY is not set
+# CONFIG_NCN26000_PHY is not set
+# CONFIG_AT803X_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+CONFIG_REALTEK_PHY=y
+# CONFIG_RENESAS_PHY is not set
+CONFIG_ROCKCHIP_PHY=y
+CONFIG_SMSC_PHY=m
+# CONFIG_STE10XP is not set
+# CONFIG_TERANETICS_PHY is not set
+# CONFIG_DP83822_PHY is not set
+# CONFIG_DP83TC811_PHY is not set
+# CONFIG_DP83848_PHY is not set
+# CONFIG_DP83867_PHY is not set
+# CONFIG_DP83869_PHY is not set
+# CONFIG_DP83TD510_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_XILINX_GMII2RGMII is not set
+# CONFIG_MICREL_KS8995MA is not set
+# CONFIG_PSE_CONTROLLER is not set
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_BUS=y
+CONFIG_FWNODE_MDIO=y
+CONFIG_OF_MDIO=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MDIO_BITBANG=y
+# CONFIG_MDIO_BCM_UNIMAC is not set
+CONFIG_MDIO_GPIO=y
+# CONFIG_MDIO_HISI_FEMAC is not set
+# CONFIG_MDIO_MVUSB is not set
+# CONFIG_MDIO_MSCC_MIIM is not set
+# CONFIG_MDIO_IPQ4019 is not set
+# CONFIG_MDIO_IPQ8064 is not set
+
+#
+# MDIO Multiplexers
+#
+CONFIG_MDIO_BUS_MUX=y
+CONFIG_MDIO_BUS_MUX_GPIO=y
+CONFIG_MDIO_BUS_MUX_MULTIPLEXER=y
+CONFIG_MDIO_BUS_MUX_MMIOREG=y
+
+#
+# PCS device drivers
+#
+CONFIG_PCS_XPCS=y
+# end of PCS device drivers
+
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+CONFIG_USB_NET_DRIVERS=y
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+CONFIG_USB_PEGASUS=m
+CONFIG_USB_RTL8150=m
+CONFIG_USB_RTL8152=m
+CONFIG_USB_LAN78XX=m
+CONFIG_USB_USBNET=m
+CONFIG_USB_NET_AX8817X=m
+CONFIG_USB_NET_AX88179_178A=m
+CONFIG_USB_NET_CDCETHER=m
+# CONFIG_USB_NET_CDC_EEM is not set
+CONFIG_USB_NET_CDC_NCM=m
+# CONFIG_USB_NET_HUAWEI_CDC_NCM is not set
+# CONFIG_USB_NET_CDC_MBIM is not set
+CONFIG_USB_NET_DM9601=m
+# CONFIG_USB_NET_SR9700 is not set
+CONFIG_USB_NET_SR9800=m
+CONFIG_USB_NET_SMSC75XX=m
+CONFIG_USB_NET_SMSC95XX=m
+# CONFIG_USB_NET_GL620A is not set
+CONFIG_USB_NET_NET1080=m
+CONFIG_USB_NET_PLUSB=m
+CONFIG_USB_NET_MCS7830=m
+CONFIG_USB_NET_RNDIS_HOST=m
+CONFIG_USB_NET_CDC_SUBSET_ENABLE=m
+CONFIG_USB_NET_CDC_SUBSET=m
+# CONFIG_USB_ALI_M5632 is not set
+# CONFIG_USB_AN2720 is not set
+CONFIG_USB_BELKIN=y
+CONFIG_USB_ARMLINUX=y
+# CONFIG_USB_EPSON2888 is not set
+# CONFIG_USB_KC2190 is not set
+CONFIG_USB_NET_ZAURUS=m
+# CONFIG_USB_NET_CX82310_ETH is not set
+# CONFIG_USB_NET_KALMIA is not set
+# CONFIG_USB_NET_QMI_WWAN is not set
+# CONFIG_USB_HSO is not set
+# CONFIG_USB_NET_INT51X1 is not set
+# CONFIG_USB_IPHETH is not set
+# CONFIG_USB_SIERRA_NET is not set
+# CONFIG_USB_VL600 is not set
+# CONFIG_USB_NET_CH9200 is not set
+# CONFIG_USB_NET_AQC111 is not set
+CONFIG_USB_RTL8153_ECM=m
+CONFIG_WLAN=y
+CONFIG_WLAN_VENDOR_ADMTEK=y
+CONFIG_ATH_COMMON=m
+CONFIG_WLAN_VENDOR_ATH=y
+# CONFIG_ATH_DEBUG is not set
+CONFIG_ATH9K_HW=m
+CONFIG_ATH9K_COMMON=m
+CONFIG_ATH9K_BTCOEX_SUPPORT=y
+# CONFIG_ATH9K is not set
+CONFIG_ATH9K_HTC=m
+# CONFIG_ATH9K_HTC_DEBUGFS is not set
+CONFIG_CARL9170=m
+CONFIG_CARL9170_LEDS=y
+CONFIG_CARL9170_WPC=y
+CONFIG_CARL9170_HWRNG=y
+CONFIG_ATH6KL=m
+# CONFIG_ATH6KL_SDIO is not set
+CONFIG_ATH6KL_USB=m
+# CONFIG_ATH6KL_DEBUG is not set
+CONFIG_AR5523=m
+# CONFIG_ATH10K is not set
+CONFIG_WCN36XX=m
+# CONFIG_WCN36XX_DEBUGFS is not set
+CONFIG_ATH11K=m
+# CONFIG_ATH11K_DEBUG is not set
+CONFIG_WLAN_VENDOR_ATMEL=y
+CONFIG_AT76C50X_USB=m
+CONFIG_WLAN_VENDOR_BROADCOM=y
+CONFIG_B43=m
+CONFIG_B43_BCMA=y
+CONFIG_B43_SSB=y
+CONFIG_B43_BUSES_BCMA_AND_SSB=y
+# CONFIG_B43_BUSES_BCMA is not set
+# CONFIG_B43_BUSES_SSB is not set
+CONFIG_B43_SDIO=y
+CONFIG_B43_BCMA_PIO=y
+CONFIG_B43_PIO=y
+CONFIG_B43_PHY_G=y
+CONFIG_B43_PHY_N=y
+CONFIG_B43_PHY_LP=y
+CONFIG_B43_PHY_HT=y
+CONFIG_B43_LEDS=y
+CONFIG_B43_HWRNG=y
+# CONFIG_B43_DEBUG is not set
+CONFIG_B43LEGACY=m
+CONFIG_B43LEGACY_LEDS=y
+CONFIG_B43LEGACY_HWRNG=y
+CONFIG_B43LEGACY_DEBUG=y
+CONFIG_B43LEGACY_DMA=y
+CONFIG_B43LEGACY_PIO=y
+CONFIG_B43LEGACY_DMA_AND_PIO_MODE=y
+# CONFIG_B43LEGACY_DMA_MODE is not set
+# CONFIG_B43LEGACY_PIO_MODE is not set
+CONFIG_BRCMUTIL=m
+# CONFIG_BRCMSMAC is not set
+CONFIG_BRCMFMAC=m
+CONFIG_BRCMFMAC_PROTO_BCDC=y
+CONFIG_BRCMFMAC_SDIO=y
+CONFIG_BRCMFMAC_USB=y
+# CONFIG_BRCM_TRACING is not set
+# CONFIG_BRCMDBG is not set
+CONFIG_WLAN_VENDOR_CISCO=y
+CONFIG_WLAN_VENDOR_INTEL=y
+CONFIG_WLAN_VENDOR_INTERSIL=y
+# CONFIG_HOSTAP is not set
+CONFIG_P54_COMMON=m
+CONFIG_P54_USB=m
+# CONFIG_P54_SPI is not set
+CONFIG_P54_LEDS=y
+CONFIG_WLAN_VENDOR_MARVELL=y
+CONFIG_LIBERTAS=m
+CONFIG_LIBERTAS_USB=m
+# CONFIG_LIBERTAS_SDIO is not set
+# CONFIG_LIBERTAS_SPI is not set
+# CONFIG_LIBERTAS_DEBUG is not set
+CONFIG_LIBERTAS_MESH=y
+CONFIG_LIBERTAS_THINFIRM=m
+# CONFIG_LIBERTAS_THINFIRM_DEBUG is not set
+CONFIG_LIBERTAS_THINFIRM_USB=m
+CONFIG_MWIFIEX=m
+# CONFIG_MWIFIEX_SDIO is not set
+CONFIG_MWIFIEX_USB=m
+CONFIG_WLAN_VENDOR_MEDIATEK=y
+CONFIG_MT7601U=m
+CONFIG_MT76_CORE=m
+CONFIG_MT76_LEDS=y
+CONFIG_MT76_USB=m
+CONFIG_MT76x02_LIB=m
+CONFIG_MT76x02_USB=m
+CONFIG_MT76_CONNAC_LIB=m
+CONFIG_MT792x_LIB=m
+CONFIG_MT792x_USB=m
+CONFIG_MT76x0_COMMON=m
+CONFIG_MT76x0U=m
+CONFIG_MT76x2_COMMON=m
+CONFIG_MT76x2U=m
+CONFIG_MT7615_COMMON=m
+CONFIG_MT7663_USB_SDIO_COMMON=m
+CONFIG_MT7663U=m
+# CONFIG_MT7663S is not set
+CONFIG_MT7921_COMMON=m
+# CONFIG_MT7921S is not set
+CONFIG_MT7921U=m
+CONFIG_WLAN_VENDOR_MICROCHIP=y
+# CONFIG_WILC1000_SDIO is not set
+# CONFIG_WILC1000_SPI is not set
+CONFIG_WLAN_VENDOR_PURELIFI=y
+CONFIG_PLFXLC=m
+CONFIG_WLAN_VENDOR_RALINK=y
+CONFIG_RT2X00=m
+CONFIG_RT2500USB=m
+CONFIG_RT73USB=m
+CONFIG_RT2800USB=m
+CONFIG_RT2800USB_RT33XX=y
+CONFIG_RT2800USB_RT35XX=y
+CONFIG_RT2800USB_RT3573=y
+CONFIG_RT2800USB_RT53XX=y
+CONFIG_RT2800USB_RT55XX=y
+CONFIG_RT2800USB_UNKNOWN=y
+CONFIG_RT2800_LIB=m
+CONFIG_RT2X00_LIB_USB=m
+CONFIG_RT2X00_LIB=m
+CONFIG_RT2X00_LIB_FIRMWARE=y
+CONFIG_RT2X00_LIB_CRYPTO=y
+CONFIG_RT2X00_LIB_LEDS=y
+# CONFIG_RT2X00_DEBUG is not set
+CONFIG_WLAN_VENDOR_REALTEK=y
+CONFIG_RTL8187=m
+CONFIG_RTL8187_LEDS=y
+CONFIG_RTL_CARDS=m
+CONFIG_RTL8192CU=m
+CONFIG_RTLWIFI=m
+CONFIG_RTLWIFI_USB=m
+CONFIG_RTLWIFI_DEBUG=y
+CONFIG_RTL8192C_COMMON=m
+CONFIG_RTL8XXXU=m
+# CONFIG_RTL8XXXU_UNTESTED is not set
+CONFIG_RTW88=m
+CONFIG_RTW88_CORE=m
+CONFIG_RTW88_SDIO=m
+CONFIG_RTW88_USB=m
+CONFIG_RTW88_8822B=m
+CONFIG_RTW88_8822C=m
+CONFIG_RTW88_8723D=m
+CONFIG_RTW88_8821C=m
+CONFIG_RTW88_8822BS=m
+CONFIG_RTW88_8822BU=m
+CONFIG_RTW88_8822CS=m
+CONFIG_RTW88_8822CU=m
+CONFIG_RTW88_8723CS=m
+CONFIG_RTW88_8723DS=m
+CONFIG_RTW88_8723DU=m
+CONFIG_RTW88_8821CS=m
+CONFIG_RTW88_8821CU=m
+# CONFIG_RTW88_DEBUG is not set
+# CONFIG_RTW88_DEBUGFS is not set
+CONFIG_RTW89=m
+CONFIG_WLAN_VENDOR_RSI=y
+CONFIG_RSI_91X=m
+# CONFIG_RSI_DEBUGFS is not set
+# CONFIG_RSI_SDIO is not set
+CONFIG_RSI_USB=m
+CONFIG_RSI_COEX=y
+CONFIG_WLAN_VENDOR_SILABS=y
+# CONFIG_WFX is not set
+CONFIG_WLAN_VENDOR_ST=y
+# CONFIG_CW1200 is not set
+CONFIG_WLAN_VENDOR_TI=y
+# CONFIG_WL1251 is not set
+CONFIG_WL12XX=m
+CONFIG_WL18XX=m
+CONFIG_WLCORE=m
+# CONFIG_WLCORE_SPI is not set
+# CONFIG_WLCORE_SDIO is not set
+CONFIG_WLAN_VENDOR_ZYDAS=y
+CONFIG_USB_ZD1201=m
+CONFIG_ZD1211RW=m
+# CONFIG_ZD1211RW_DEBUG is not set
+CONFIG_WLAN_VENDOR_QUANTENNA=y
+# CONFIG_ESP8089 is not set
+# CONFIG_ESP8089_DEBUG_FS is not set
+CONFIG_USB_NET_RNDIS_WLAN=m
+# CONFIG_MAC80211_HWSIM is not set
+# CONFIG_VIRT_WIFI is not set
+# CONFIG_WAN is not set
+# CONFIG_IEEE802154_DRIVERS is not set
+
+#
+# Wireless WAN
+#
+# CONFIG_WWAN is not set
+# end of Wireless WAN
+
+# CONFIG_NETDEVSIM is not set
+CONFIG_NET_FAILOVER=y
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+CONFIG_INPUT_LEDS=y
+CONFIG_INPUT_FF_MEMLESS=y
+# CONFIG_INPUT_SPARSEKMAP is not set
+CONFIG_INPUT_MATRIXKMAP=y
+CONFIG_INPUT_VIVALDIFMAP=m
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+CONFIG_INPUT_JOYDEV=m
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ADP5588 is not set
+# CONFIG_KEYBOARD_ADP5589 is not set
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_QT1050 is not set
+# CONFIG_KEYBOARD_QT1070 is not set
+# CONFIG_KEYBOARD_QT2160 is not set
+# CONFIG_KEYBOARD_DLINK_DIR685 is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+CONFIG_KEYBOARD_GPIO=y
+# CONFIG_KEYBOARD_GPIO_POLLED is not set
+# CONFIG_KEYBOARD_TCA6416 is not set
+# CONFIG_KEYBOARD_TCA8418 is not set
+# CONFIG_KEYBOARD_MATRIX is not set
+# CONFIG_KEYBOARD_LM8323 is not set
+# CONFIG_KEYBOARD_LM8333 is not set
+# CONFIG_KEYBOARD_MAX7359 is not set
+# CONFIG_KEYBOARD_MCS is not set
+# CONFIG_KEYBOARD_MPR121 is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_OPENCORES is not set
+CONFIG_KEYBOARD_PINEPHONE=m
+# CONFIG_KEYBOARD_PMIC8XXX is not set
+# CONFIG_KEYBOARD_SAMSUNG is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_OMAP4 is not set
+# CONFIG_KEYBOARD_TM2_TOUCHKEY is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_CAP11XX is not set
+# CONFIG_KEYBOARD_BCM is not set
+CONFIG_KEYBOARD_CYPRESS_SF=m
+CONFIG_INPUT_MOUSE=y
+# CONFIG_MOUSE_PS2 is not set
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_APPLETOUCH is not set
+# CONFIG_MOUSE_BCM5974 is not set
+# CONFIG_MOUSE_CYAPA is not set
+# CONFIG_MOUSE_ELAN_I2C is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_MOUSE_GPIO is not set
+# CONFIG_MOUSE_SYNAPTICS_I2C is not set
+# CONFIG_MOUSE_SYNAPTICS_USB is not set
+CONFIG_INPUT_JOYSTICK=y
+CONFIG_JOYSTICK_ANALOG=m
+CONFIG_JOYSTICK_A3D=m
+CONFIG_JOYSTICK_ADI=m
+CONFIG_JOYSTICK_COBRA=m
+CONFIG_JOYSTICK_GF2K=m
+CONFIG_JOYSTICK_GRIP=m
+CONFIG_JOYSTICK_GRIP_MP=m
+CONFIG_JOYSTICK_GUILLEMOT=m
+CONFIG_JOYSTICK_INTERACT=m
+CONFIG_JOYSTICK_SIDEWINDER=m
+CONFIG_JOYSTICK_TMDC=m
+CONFIG_JOYSTICK_IFORCE=m
+CONFIG_JOYSTICK_IFORCE_USB=m
+CONFIG_JOYSTICK_IFORCE_232=m
+CONFIG_JOYSTICK_WARRIOR=m
+CONFIG_JOYSTICK_MAGELLAN=m
+CONFIG_JOYSTICK_SPACEORB=m
+CONFIG_JOYSTICK_SPACEBALL=m
+CONFIG_JOYSTICK_STINGER=m
+CONFIG_JOYSTICK_TWIDJOY=m
+CONFIG_JOYSTICK_ZHENHUA=m
+CONFIG_JOYSTICK_AS5011=m
+CONFIG_JOYSTICK_JOYDUMP=m
+CONFIG_JOYSTICK_XPAD=m
+CONFIG_JOYSTICK_XPAD_FF=y
+CONFIG_JOYSTICK_XPAD_LEDS=y
+CONFIG_JOYSTICK_PSXPAD_SPI=m
+CONFIG_JOYSTICK_PSXPAD_SPI_FF=y
+CONFIG_JOYSTICK_PXRC=m
+CONFIG_JOYSTICK_QWIIC=m
+CONFIG_JOYSTICK_FSIA6B=m
+CONFIG_JOYSTICK_SENSEHAT=m
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+CONFIG_INPUT_MISC=y
+# CONFIG_INPUT_AD714X is not set
+# CONFIG_INPUT_ATMEL_CAPTOUCH is not set
+# CONFIG_INPUT_BMA150 is not set
+# CONFIG_INPUT_E3X0_BUTTON is not set
+# CONFIG_INPUT_PM8XXX_VIBRATOR is not set
+# CONFIG_INPUT_PMIC8XXX_PWRKEY is not set
+# CONFIG_INPUT_MMA8450 is not set
+# CONFIG_INPUT_GPIO_BEEPER is not set
+# CONFIG_INPUT_GPIO_DECODER is not set
+# CONFIG_INPUT_GPIO_VIBRA is not set
+# CONFIG_INPUT_ATI_REMOTE2 is not set
+# CONFIG_INPUT_KEYSPAN_REMOTE is not set
+# CONFIG_INPUT_KXTJ9 is not set
+# CONFIG_INPUT_POWERMATE is not set
+# CONFIG_INPUT_YEALINK is not set
+# CONFIG_INPUT_CM109 is not set
+# CONFIG_INPUT_REGULATOR_HAPTIC is not set
+CONFIG_INPUT_UINPUT=y
+# CONFIG_INPUT_PCF8574 is not set
+# CONFIG_INPUT_PWM_BEEPER is not set
+# CONFIG_INPUT_PWM_VIBRA is not set
+# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
+CONFIG_INPUT_DA7280_HAPTICS=m
+# CONFIG_INPUT_DA9063_ONKEY is not set
+# CONFIG_INPUT_ADXL34X is not set
+# CONFIG_INPUT_IMS_PCU is not set
+# CONFIG_INPUT_IQS269A is not set
+CONFIG_INPUT_IQS626A=m
+CONFIG_INPUT_IQS7222=m
+# CONFIG_INPUT_CMA3000 is not set
+# CONFIG_INPUT_DRV260X_HAPTICS is not set
+# CONFIG_INPUT_DRV2665_HAPTICS is not set
+# CONFIG_INPUT_DRV2667_HAPTICS is not set
+CONFIG_RMI4_CORE=m
+# CONFIG_RMI4_I2C is not set
+# CONFIG_RMI4_SPI is not set
+# CONFIG_RMI4_SMB is not set
+CONFIG_RMI4_F03=y
+CONFIG_RMI4_F03_SERIO=m
+CONFIG_RMI4_2D_SENSOR=y
+CONFIG_RMI4_F11=y
+CONFIG_RMI4_F12=y
+CONFIG_RMI4_F30=y
+CONFIG_RMI4_F34=y
+CONFIG_RMI4_F3A=y
+CONFIG_RMI4_F54=y
+CONFIG_RMI4_F55=y
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=y
+CONFIG_SERIO_AMBAKMI=y
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_SERIO_ALTERA_PS2 is not set
+# CONFIG_SERIO_PS2MULT is not set
+# CONFIG_SERIO_ARC_PS2 is not set
+# CONFIG_SERIO_APBPS2 is not set
+# CONFIG_SERIO_GPIO_PS2 is not set
+# CONFIG_USERIO is not set
+CONFIG_GAMEPORT=m
+# end of Hardware I/O ports
+# end of Input device support
+
+#
+# Character devices
+#
+CONFIG_TTY=y
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_VT_CONSOLE_SLEEP=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_LEGACY_TIOCSTI=y
+CONFIG_LDISC_AUTOLOAD=y
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_EARLYCON=y
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
+# CONFIG_SERIAL_8250_16550A_VARIANTS is not set
+# CONFIG_SERIAL_8250_FINTEK is not set
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_DMA=y
+CONFIG_SERIAL_8250_NR_UARTS=5
+CONFIG_SERIAL_8250_RUNTIME_UARTS=5
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_MANY_PORTS=y
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+# CONFIG_SERIAL_8250_DETECT_IRQ is not set
+# CONFIG_SERIAL_8250_RSA is not set
+CONFIG_SERIAL_8250_DWLIB=y
+CONFIG_SERIAL_8250_FSL=y
+CONFIG_SERIAL_8250_DW=y
+# CONFIG_SERIAL_8250_RT288X is not set
+CONFIG_SERIAL_OF_PLATFORM=y
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_AMBA_PL010 is not set
+# CONFIG_SERIAL_AMBA_PL011 is not set
+# CONFIG_SERIAL_EARLYCON_SEMIHOST is not set
+# CONFIG_SERIAL_MAX3100 is not set
+# CONFIG_SERIAL_MAX310X is not set
+# CONFIG_SERIAL_UARTLITE is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_SIFIVE is not set
+# CONFIG_SERIAL_SCCNXP is not set
+# CONFIG_SERIAL_SC16IS7XX is not set
+# CONFIG_SERIAL_ALTERA_JTAGUART is not set
+# CONFIG_SERIAL_ALTERA_UART is not set
+CONFIG_SERIAL_XILINX_PS_UART=y
+CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y
+# CONFIG_SERIAL_ARC is not set
+# CONFIG_SERIAL_FSL_LPUART is not set
+# CONFIG_SERIAL_FSL_LINFLEXUART is not set
+# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set
+CONFIG_SERIAL_ST_ASC=m
+# CONFIG_SERIAL_SPRD is not set
+# end of Serial drivers
+
+CONFIG_SERIAL_MCTRL_GPIO=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_N_GSM is not set
+# CONFIG_NULL_TTY is not set
+CONFIG_HVC_DRIVER=y
+# CONFIG_HVC_DCC is not set
+CONFIG_SERIAL_DEV_BUS=y
+CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
+CONFIG_VIRTIO_CONSOLE=y
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_HW_RANDOM_TIMERIOMEM is not set
+# CONFIG_HW_RANDOM_BA431 is not set
+# CONFIG_HW_RANDOM_VIRTIO is not set
+CONFIG_HW_RANDOM_OPTEE=m
+# CONFIG_HW_RANDOM_CCTRNG is not set
+# CONFIG_HW_RANDOM_XIPHERA is not set
+CONFIG_HW_RANDOM_ARM_SMCCC_TRNG=y
+CONFIG_DEVMEM=y
+CONFIG_DEVPORT=y
+# CONFIG_TCG_TPM is not set
+# CONFIG_XILLYBUS is not set
+# CONFIG_XILLYUSB is not set
+# end of Character devices
+
+#
+# I2C support
+#
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_COMPAT=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_MUX=y
+
+#
+# Multiplexer I2C Chip support
+#
+CONFIG_I2C_ARB_GPIO_CHALLENGE=m
+# CONFIG_I2C_MUX_GPIO is not set
+# CONFIG_I2C_MUX_GPMUX is not set
+# CONFIG_I2C_MUX_LTC4306 is not set
+# CONFIG_I2C_MUX_PCA9541 is not set
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_I2C_MUX_PINCTRL=y
+# CONFIG_I2C_MUX_REG is not set
+CONFIG_I2C_DEMUX_PINCTRL=y
+# CONFIG_I2C_MUX_MLXCPLD is not set
+# end of Multiplexer I2C Chip support
+
+CONFIG_I2C_HELPER_AUTO=y
+CONFIG_I2C_ALGOBIT=m
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_CBUS_GPIO is not set
+CONFIG_I2C_DESIGNWARE_CORE=y
+# CONFIG_I2C_DESIGNWARE_SLAVE is not set
+CONFIG_I2C_DESIGNWARE_PLATFORM=y
+# CONFIG_I2C_EMEV2 is not set
+CONFIG_I2C_GPIO=m
+# CONFIG_I2C_GPIO_FAULT_INJECTOR is not set
+# CONFIG_I2C_NOMADIK is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_PCA_PLATFORM is not set
+CONFIG_I2C_RK3X=y
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_XILINX is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_DIOLAN_U2C is not set
+# CONFIG_I2C_CP2615 is not set
+# CONFIG_I2C_ROBOTFUZZ_OSIF is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_VIRTIO is not set
+# end of I2C Hardware Bus support
+
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_SLAVE is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# end of I2C support
+
+# CONFIG_I3C is not set
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+
+#
+# SPI Master Controller Drivers
+#
+# CONFIG_SPI_ALTERA is not set
+# CONFIG_SPI_AXI_SPI_ENGINE is not set
+CONFIG_SPI_BITBANG=m
+# CONFIG_SPI_CADENCE is not set
+# CONFIG_SPI_CADENCE_QUADSPI is not set
+# CONFIG_SPI_CADENCE_XSPI is not set
+# CONFIG_SPI_DESIGNWARE is not set
+CONFIG_SPI_GPIO=m
+# CONFIG_SPI_FSL_SPI is not set
+# CONFIG_SPI_MICROCHIP_CORE is not set
+# CONFIG_SPI_MICROCHIP_CORE_QSPI is not set
+# CONFIG_SPI_OC_TINY is not set
+CONFIG_SPI_PL022=y
+CONFIG_SPI_ROCKCHIP=m
+CONFIG_SPI_ROCKCHIP_SFC=m
+# CONFIG_SPI_SC18IS602 is not set
+# CONFIG_SPI_SIFIVE is not set
+# CONFIG_SPI_SN_F_OSPI is not set
+# CONFIG_SPI_MXIC is not set
+# CONFIG_SPI_XCOMM is not set
+# CONFIG_SPI_XILINX is not set
+# CONFIG_SPI_ZYNQMP_GQSPI is not set
+# CONFIG_SPI_AMD is not set
+
+#
+# SPI Multiplexer support
+#
+# CONFIG_SPI_MUX is not set
+
+#
+# SPI Protocol Masters
+#
+CONFIG_SPI_SPIDEV=m
+# CONFIG_SPI_LOOPBACK_TEST is not set
+# CONFIG_SPI_TLE62X0 is not set
+# CONFIG_SPI_SLAVE is not set
+CONFIG_SPI_DYNAMIC=y
+CONFIG_SPMI=y
+# CONFIG_SPMI_HISI3670 is not set
+# CONFIG_HSI is not set
+CONFIG_PPS=y
+# CONFIG_PPS_DEBUG is not set
+
+#
+# PPS clients support
+#
+# CONFIG_PPS_CLIENT_KTIMER is not set
+# CONFIG_PPS_CLIENT_LDISC is not set
+# CONFIG_PPS_CLIENT_GPIO is not set
+
+#
+# PPS generators support
+#
+
+#
+# PTP clock support
+#
+CONFIG_PTP_1588_CLOCK=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+
+#
+# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks.
+#
+# CONFIG_PTP_1588_CLOCK_KVM is not set
+# CONFIG_PTP_1588_CLOCK_IDT82P33 is not set
+# CONFIG_PTP_1588_CLOCK_IDTCM is not set
+# CONFIG_PTP_1588_CLOCK_MOCK is not set
+# end of PTP clock support
+
+CONFIG_PINCTRL=y
+CONFIG_PINMUX=y
+CONFIG_PINCONF=y
+CONFIG_GENERIC_PINCONF=y
+# CONFIG_DEBUG_PINCTRL is not set
+# CONFIG_PINCTRL_CY8C95X0 is not set
+CONFIG_PINCTRL_MAX77620=y
+# CONFIG_PINCTRL_MCP23S08 is not set
+# CONFIG_PINCTRL_MICROCHIP_SGPIO is not set
+# CONFIG_PINCTRL_OCELOT is not set
+CONFIG_PINCTRL_ROCKCHIP=y
+# CONFIG_PINCTRL_SINGLE is not set
+# CONFIG_PINCTRL_STMFX is not set
+# CONFIG_PINCTRL_SX150X is not set
+
+#
+# Renesas pinctrl drivers
+#
+# end of Renesas pinctrl drivers
+
+CONFIG_GPIOLIB=y
+CONFIG_GPIOLIB_FASTPATH_LIMIT=512
+CONFIG_OF_GPIO=y
+CONFIG_GPIOLIB_IRQCHIP=y
+# CONFIG_DEBUG_GPIO is not set
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_CDEV_V1=y
+CONFIG_GPIO_GENERIC=y
+
+#
+# Memory mapped GPIO drivers
+#
+# CONFIG_GPIO_74XX_MMIO is not set
+# CONFIG_GPIO_ALTERA is not set
+# CONFIG_GPIO_CADENCE is not set
+CONFIG_GPIO_DWAPB=y
+# CONFIG_GPIO_FTGPIO010 is not set
+# CONFIG_GPIO_GENERIC_PLATFORM is not set
+# CONFIG_GPIO_GRGPIO is not set
+# CONFIG_GPIO_HLWD is not set
+# CONFIG_GPIO_LOGICVC is not set
+# CONFIG_GPIO_MB86S7X is not set
+# CONFIG_GPIO_MPC8XXX is not set
+CONFIG_GPIO_PL061=y
+CONFIG_GPIO_ROCKCHIP=y
+# CONFIG_GPIO_SIFIVE is not set
+CONFIG_GPIO_SYSCON=y
+# CONFIG_GPIO_XILINX is not set
+# CONFIG_GPIO_ZEVIO is not set
+# CONFIG_GPIO_AMD_FCH is not set
+# end of Memory mapped GPIO drivers
+
+#
+# I2C GPIO expanders
+#
+# CONFIG_GPIO_ADNP is not set
+# CONFIG_GPIO_FXL6408 is not set
+# CONFIG_GPIO_DS4520 is not set
+# CONFIG_GPIO_GW_PLD is not set
+# CONFIG_GPIO_MAX7300 is not set
+# CONFIG_GPIO_MAX732X is not set
+CONFIG_GPIO_PCA953X=y
+CONFIG_GPIO_PCA953X_IRQ=y
+# CONFIG_GPIO_PCA9570 is not set
+# CONFIG_GPIO_PCF857X is not set
+# CONFIG_GPIO_TPIC2810 is not set
+# end of I2C GPIO expanders
+
+#
+# MFD GPIO expanders
+#
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_GPIO_MAX77620 is not set
+# end of MFD GPIO expanders
+
+#
+# SPI GPIO expanders
+#
+# CONFIG_GPIO_74X164 is not set
+# CONFIG_GPIO_MAX3191X is not set
+# CONFIG_GPIO_MAX7301 is not set
+# CONFIG_GPIO_MC33880 is not set
+# CONFIG_GPIO_PISOSR is not set
+# CONFIG_GPIO_XRA1403 is not set
+# end of SPI GPIO expanders
+
+#
+# USB GPIO expanders
+#
+# end of USB GPIO expanders
+
+#
+# Virtual GPIO drivers
+#
+# CONFIG_GPIO_AGGREGATOR is not set
+# CONFIG_GPIO_LATCH is not set
+# CONFIG_GPIO_MOCKUP is not set
+# CONFIG_GPIO_VIRTIO is not set
+# CONFIG_GPIO_SIM is not set
+# end of Virtual GPIO drivers
+
+# CONFIG_W1 is not set
+CONFIG_POWER_RESET=y
+# CONFIG_POWER_RESET_BRCMKONA is not set
+# CONFIG_POWER_RESET_BRCMSTB is not set
+# CONFIG_POWER_RESET_GPIO is not set
+# CONFIG_POWER_RESET_GPIO_RESTART is not set
+# CONFIG_POWER_RESET_LTC2952 is not set
+# CONFIG_POWER_RESET_REGULATOR is not set
+# CONFIG_POWER_RESET_RESTART is not set
+# CONFIG_POWER_RESET_VERSATILE is not set
+CONFIG_POWER_RESET_SYSCON=y
+# CONFIG_POWER_RESET_SYSCON_POWEROFF is not set
+CONFIG_REBOOT_MODE=y
+CONFIG_SYSCON_REBOOT_MODE=y
+# CONFIG_NVMEM_REBOOT_MODE is not set
+CONFIG_POWER_SUPPLY=y
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+CONFIG_POWER_SUPPLY_HWMON=y
+# CONFIG_IP5XXX_POWER is not set
+# CONFIG_TEST_POWER is not set
+# CONFIG_CHARGER_ADP5061 is not set
+# CONFIG_BATTERY_CW2015 is not set
+# CONFIG_BATTERY_DS2780 is not set
+# CONFIG_BATTERY_DS2781 is not set
+# CONFIG_BATTERY_DS2782 is not set
+# CONFIG_BATTERY_SAMSUNG_SDI is not set
+# CONFIG_BATTERY_SBS is not set
+# CONFIG_CHARGER_SBS is not set
+# CONFIG_MANAGER_SBS is not set
+# CONFIG_BATTERY_BQ27XXX is not set
+# CONFIG_BATTERY_MAX17040 is not set
+# CONFIG_BATTERY_MAX17042 is not set
+# CONFIG_CHARGER_ISP1704 is not set
+# CONFIG_CHARGER_MAX8903 is not set
+# CONFIG_CHARGER_LP8727 is not set
+# CONFIG_CHARGER_GPIO is not set
+# CONFIG_CHARGER_MANAGER is not set
+# CONFIG_CHARGER_LT3651 is not set
+# CONFIG_CHARGER_LTC4162L is not set
+# CONFIG_CHARGER_DETECTOR_MAX14656 is not set
+# CONFIG_CHARGER_MAX77976 is not set
+# CONFIG_CHARGER_BQ2415X is not set
+# CONFIG_CHARGER_BQ24190 is not set
+# CONFIG_CHARGER_BQ24257 is not set
+# CONFIG_CHARGER_BQ24735 is not set
+# CONFIG_CHARGER_BQ2515X is not set
+# CONFIG_CHARGER_BQ25890 is not set
+# CONFIG_CHARGER_BQ25980 is not set
+# CONFIG_CHARGER_BQ256XX is not set
+# CONFIG_CHARGER_SMB347 is not set
+# CONFIG_BATTERY_GAUGE_LTC2941 is not set
+# CONFIG_BATTERY_GOLDFISH is not set
+# CONFIG_BATTERY_RT5033 is not set
+# CONFIG_CHARGER_RT9455 is not set
+# CONFIG_CHARGER_RT9467 is not set
+# CONFIG_CHARGER_RT9471 is not set
+# CONFIG_CHARGER_UCS1002 is not set
+# CONFIG_CHARGER_BD99954 is not set
+# CONFIG_BATTERY_UG3105 is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_DEBUG_CHIP is not set
+
+#
+# Native drivers
+#
+# CONFIG_SENSORS_AD7314 is not set
+# CONFIG_SENSORS_AD7414 is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM1177 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ADT7310 is not set
+# CONFIG_SENSORS_ADT7410 is not set
+# CONFIG_SENSORS_ADT7411 is not set
+# CONFIG_SENSORS_ADT7462 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7475 is not set
+# CONFIG_SENSORS_AHT10 is not set
+# CONFIG_SENSORS_AQUACOMPUTER_D5NEXT is not set
+# CONFIG_SENSORS_AS370 is not set
+# CONFIG_SENSORS_ASC7621 is not set
+# CONFIG_SENSORS_AXI_FAN_CONTROL is not set
+# CONFIG_SENSORS_ARM_SCMI is not set
+CONFIG_SENSORS_ARM_SCPI=m
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_CORSAIR_CPRO is not set
+# CONFIG_SENSORS_CORSAIR_PSU is not set
+# CONFIG_SENSORS_DS620 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
+# CONFIG_SENSORS_FTSTEUTATES is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_G760A is not set
+# CONFIG_SENSORS_G762 is not set
+# CONFIG_SENSORS_GPIO_FAN is not set
+# CONFIG_SENSORS_HIH6130 is not set
+# CONFIG_SENSORS_HS3001 is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_JC42 is not set
+# CONFIG_SENSORS_POWR1220 is not set
+# CONFIG_SENSORS_LINEAGE is not set
+# CONFIG_SENSORS_LTC2945 is not set
+# CONFIG_SENSORS_LTC2947_I2C is not set
+# CONFIG_SENSORS_LTC2947_SPI is not set
+# CONFIG_SENSORS_LTC2990 is not set
+# CONFIG_SENSORS_LTC2992 is not set
+# CONFIG_SENSORS_LTC4151 is not set
+# CONFIG_SENSORS_LTC4215 is not set
+# CONFIG_SENSORS_LTC4222 is not set
+# CONFIG_SENSORS_LTC4245 is not set
+# CONFIG_SENSORS_LTC4260 is not set
+# CONFIG_SENSORS_LTC4261 is not set
+# CONFIG_SENSORS_MAX1111 is not set
+# CONFIG_SENSORS_MAX127 is not set
+# CONFIG_SENSORS_MAX16065 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX1668 is not set
+# CONFIG_SENSORS_MAX197 is not set
+# CONFIG_SENSORS_MAX31722 is not set
+# CONFIG_SENSORS_MAX31730 is not set
+# CONFIG_SENSORS_MAX31760 is not set
+# CONFIG_MAX31827 is not set
+# CONFIG_SENSORS_MAX6620 is not set
+# CONFIG_SENSORS_MAX6621 is not set
+# CONFIG_SENSORS_MAX6639 is not set
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_MAX6697 is not set
+# CONFIG_SENSORS_MAX31790 is not set
+# CONFIG_SENSORS_MC34VR500 is not set
+# CONFIG_SENSORS_MCP3021 is not set
+# CONFIG_SENSORS_TC654 is not set
+# CONFIG_SENSORS_TPS23861 is not set
+# CONFIG_SENSORS_MR75203 is not set
+# CONFIG_SENSORS_ADCXX is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM70 is not set
+# CONFIG_SENSORS_LM73 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+CONFIG_SENSORS_LM90=m
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_LM95234 is not set
+# CONFIG_SENSORS_LM95241 is not set
+# CONFIG_SENSORS_LM95245 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_NCT6683 is not set
+# CONFIG_SENSORS_NCT6775_I2C is not set
+# CONFIG_SENSORS_NCT7802 is not set
+# CONFIG_SENSORS_NCT7904 is not set
+# CONFIG_SENSORS_NPCM7XX is not set
+# CONFIG_SENSORS_NZXT_KRAKEN2 is not set
+# CONFIG_SENSORS_NZXT_SMART2 is not set
+# CONFIG_SENSORS_OCC_P8_I2C is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_PMBUS is not set
+CONFIG_SENSORS_PWM_FAN=m
+# CONFIG_SENSORS_SBTSI is not set
+# CONFIG_SENSORS_SBRMI is not set
+# CONFIG_SENSORS_SHT15 is not set
+# CONFIG_SENSORS_SHT21 is not set
+# CONFIG_SENSORS_SHT3x is not set
+# CONFIG_SENSORS_SHT4x is not set
+# CONFIG_SENSORS_SHTC1 is not set
+# CONFIG_SENSORS_DME1737 is not set
+# CONFIG_SENSORS_EMC1403 is not set
+# CONFIG_SENSORS_EMC2103 is not set
+# CONFIG_SENSORS_EMC2305 is not set
+# CONFIG_SENSORS_EMC6W201 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_SCH5627 is not set
+# CONFIG_SENSORS_SCH5636 is not set
+# CONFIG_SENSORS_STTS751 is not set
+# CONFIG_SENSORS_ADC128D818 is not set
+# CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_ADS7871 is not set
+# CONFIG_SENSORS_AMC6821 is not set
+# CONFIG_SENSORS_INA209 is not set
+CONFIG_SENSORS_INA2XX=m
+# CONFIG_SENSORS_INA238 is not set
+# CONFIG_SENSORS_INA3221 is not set
+# CONFIG_SENSORS_TC74 is not set
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_TMP102 is not set
+# CONFIG_SENSORS_TMP103 is not set
+# CONFIG_SENSORS_TMP108 is not set
+# CONFIG_SENSORS_TMP401 is not set
+# CONFIG_SENSORS_TMP421 is not set
+# CONFIG_SENSORS_TMP464 is not set
+# CONFIG_SENSORS_TMP513 is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_W83773G is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83795 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+CONFIG_THERMAL=y
+CONFIG_THERMAL_NETLINK=y
+# CONFIG_THERMAL_STATISTICS is not set
+CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
+CONFIG_THERMAL_HWMON=y
+CONFIG_THERMAL_OF=y
+# CONFIG_THERMAL_WRITABLE_TRIPS is not set
+CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
+# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set
+# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set
+# CONFIG_THERMAL_GOV_FAIR_SHARE is not set
+CONFIG_THERMAL_GOV_STEP_WISE=y
+# CONFIG_THERMAL_GOV_BANG_BANG is not set
+# CONFIG_THERMAL_GOV_USER_SPACE is not set
+CONFIG_CPU_THERMAL=y
+CONFIG_CPU_FREQ_THERMAL=y
+CONFIG_DEVFREQ_THERMAL=y
+CONFIG_THERMAL_EMULATION=y
+# CONFIG_THERMAL_MMIO is not set
+# CONFIG_MAX77620_THERMAL is not set
+CONFIG_ROCKCHIP_THERMAL=y
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_CORE=y
+# CONFIG_WATCHDOG_NOWAYOUT is not set
+CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y
+CONFIG_WATCHDOG_OPEN_TIMEOUT=0
+# CONFIG_WATCHDOG_SYSFS is not set
+# CONFIG_WATCHDOG_HRTIMER_PRETIMEOUT is not set
+
+#
+# Watchdog Pretimeout Governors
+#
+# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_DA9063_WATCHDOG=m
+# CONFIG_GPIO_WATCHDOG is not set
+# CONFIG_XILINX_WATCHDOG is not set
+# CONFIG_ZIIRAVE_WATCHDOG is not set
+# CONFIG_ARM_SP805_WATCHDOG is not set
+# CONFIG_CADENCE_WATCHDOG is not set
+# CONFIG_FTWDT010_WATCHDOG is not set
+CONFIG_DW_WATCHDOG=y
+# CONFIG_MAX63XX_WATCHDOG is not set
+# CONFIG_MAX77620_WATCHDOG is not set
+CONFIG_ARM_SMC_WATCHDOG=m
+# CONFIG_MEN_A21_WDT is not set
+
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+CONFIG_SSB=m
+CONFIG_SSB_BLOCKIO=y
+CONFIG_SSB_SDIOHOST_POSSIBLE=y
+CONFIG_SSB_SDIOHOST=y
+# CONFIG_SSB_DRIVER_GPIO is not set
+CONFIG_BCMA_POSSIBLE=y
+CONFIG_BCMA=m
+CONFIG_BCMA_BLOCKIO=y
+# CONFIG_BCMA_HOST_SOC is not set
+# CONFIG_BCMA_DRIVER_GMAC_CMN is not set
+# CONFIG_BCMA_DRIVER_GPIO is not set
+# CONFIG_BCMA_DEBUG is not set
+
+#
+# Multifunction device drivers
+#
+CONFIG_MFD_CORE=y
+# CONFIG_MFD_ACT8945A is not set
+# CONFIG_MFD_AS3711 is not set
+# CONFIG_MFD_SMPRO is not set
+# CONFIG_MFD_AS3722 is not set
+# CONFIG_PMIC_ADP5520 is not set
+# CONFIG_MFD_AAT2870_CORE is not set
+# CONFIG_MFD_ATMEL_FLEXCOM is not set
+# CONFIG_MFD_ATMEL_HLCDC is not set
+# CONFIG_MFD_BCM590XX is not set
+# CONFIG_MFD_BD9571MWV is not set
+# CONFIG_MFD_AXP20X_I2C is not set
+# CONFIG_MFD_CS42L43_I2C is not set
+# CONFIG_MFD_MADERA is not set
+# CONFIG_MFD_MAX5970 is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_DA9052_SPI is not set
+# CONFIG_MFD_DA9052_I2C is not set
+# CONFIG_MFD_DA9055 is not set
+# CONFIG_MFD_DA9062 is not set
+CONFIG_MFD_DA9063=m
+# CONFIG_MFD_DA9150 is not set
+# CONFIG_MFD_DLN2 is not set
+# CONFIG_MFD_GATEWORKS_GSC is not set
+# CONFIG_MFD_MC13XXX_SPI is not set
+# CONFIG_MFD_MC13XXX_I2C is not set
+# CONFIG_MFD_MP2629 is not set
+# CONFIG_MFD_HI6421_PMIC is not set
+# CONFIG_MFD_HI6421_SPMI is not set
+# CONFIG_MFD_IQS62X is not set
+# CONFIG_MFD_KEMPLD is not set
+# CONFIG_MFD_88PM800 is not set
+# CONFIG_MFD_88PM805 is not set
+# CONFIG_MFD_88PM860X is not set
+# CONFIG_MFD_MAX14577 is not set
+# CONFIG_MFD_MAX77541 is not set
+CONFIG_MFD_MAX77620=y
+# CONFIG_MFD_MAX77650 is not set
+# CONFIG_MFD_MAX77686 is not set
+# CONFIG_MFD_MAX77693 is not set
+# CONFIG_MFD_MAX77714 is not set
+# CONFIG_MFD_MAX77843 is not set
+# CONFIG_MFD_MAX8907 is not set
+# CONFIG_MFD_MAX8925 is not set
+# CONFIG_MFD_MAX8997 is not set
+# CONFIG_MFD_MAX8998 is not set
+# CONFIG_MFD_MT6360 is not set
+# CONFIG_MFD_MT6370 is not set
+# CONFIG_MFD_MT6397 is not set
+# CONFIG_MFD_MENF21BMC is not set
+# CONFIG_MFD_OCELOT is not set
+# CONFIG_EZX_PCAP is not set
+# CONFIG_MFD_CPCAP is not set
+# CONFIG_MFD_VIPERBOARD is not set
+# CONFIG_MFD_NTXEC is not set
+# CONFIG_MFD_RETU is not set
+# CONFIG_MFD_PCF50633 is not set
+CONFIG_MFD_PM8XXX=y
+# CONFIG_MFD_SY7636A is not set
+# CONFIG_MFD_RT4831 is not set
+# CONFIG_MFD_RT5033 is not set
+# CONFIG_MFD_RT5120 is not set
+# CONFIG_MFD_RC5T583 is not set
+# CONFIG_MFD_RK8XX_I2C is not set
+# CONFIG_MFD_RK8XX_SPI is not set
+# CONFIG_MFD_RN5T618 is not set
+CONFIG_MFD_SEC_CORE=y
+# CONFIG_MFD_SI476X_CORE is not set
+CONFIG_MFD_SIMPLE_MFD_I2C=m
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_SKY81452 is not set
+# CONFIG_MFD_STMPE is not set
+CONFIG_MFD_SYSCON=y
+# CONFIG_MFD_LP3943 is not set
+# CONFIG_MFD_LP8788 is not set
+# CONFIG_MFD_TI_LMU is not set
+# CONFIG_MFD_PALMAS is not set
+# CONFIG_TPS6105X is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_TPS6507X is not set
+# CONFIG_MFD_TPS65086 is not set
+# CONFIG_MFD_TPS65090 is not set
+# CONFIG_MFD_TPS65217 is not set
+# CONFIG_MFD_TI_LP873X is not set
+# CONFIG_MFD_TI_LP87565 is not set
+# CONFIG_MFD_TPS65218 is not set
+# CONFIG_MFD_TPS65219 is not set
+# CONFIG_MFD_TPS6586X is not set
+# CONFIG_MFD_TPS65910 is not set
+# CONFIG_MFD_TPS65912_I2C is not set
+# CONFIG_MFD_TPS65912_SPI is not set
+# CONFIG_MFD_TPS6594_I2C is not set
+# CONFIG_MFD_TPS6594_SPI is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_TWL6040_CORE is not set
+# CONFIG_MFD_WL1273_CORE is not set
+# CONFIG_MFD_LM3533 is not set
+# CONFIG_MFD_TC3589X is not set
+# CONFIG_MFD_TQMX86 is not set
+# CONFIG_MFD_LOCHNAGAR is not set
+# CONFIG_MFD_ARIZONA_I2C is not set
+# CONFIG_MFD_ARIZONA_SPI is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X_I2C is not set
+# CONFIG_MFD_WM831X_SPI is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_WM8994 is not set
+# CONFIG_MFD_ROHM_BD718XX is not set
+# CONFIG_MFD_ROHM_BD71828 is not set
+# CONFIG_MFD_ROHM_BD957XMUF is not set
+# CONFIG_MFD_STPMIC1 is not set
+# CONFIG_MFD_STMFX is not set
+# CONFIG_MFD_ATC260X_I2C is not set
+# CONFIG_MFD_KHADAS_MCU is not set
+# CONFIG_MFD_QCOM_PM8008 is not set
+# CONFIG_RAVE_SP_CORE is not set
+# CONFIG_MFD_INTEL_M10_BMC_SPI is not set
+# CONFIG_MFD_RSMU_I2C is not set
+# CONFIG_MFD_RSMU_SPI is not set
+# end of Multifunction device drivers
+
+CONFIG_REGULATOR=y
+# CONFIG_REGULATOR_DEBUG is not set
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
+# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
+# CONFIG_REGULATOR_88PG86X is not set
+# CONFIG_REGULATOR_ACT8865 is not set
+# CONFIG_REGULATOR_AD5398 is not set
+# CONFIG_REGULATOR_ARM_SCMI is not set
+# CONFIG_REGULATOR_AW37503 is not set
+# CONFIG_REGULATOR_DA9063 is not set
+# CONFIG_REGULATOR_DA9121 is not set
+# CONFIG_REGULATOR_DA9210 is not set
+# CONFIG_REGULATOR_DA9211 is not set
+# CONFIG_REGULATOR_FAN53555 is not set
+# CONFIG_REGULATOR_FAN53880 is not set
+CONFIG_REGULATOR_GPIO=y
+# CONFIG_REGULATOR_ISL9305 is not set
+# CONFIG_REGULATOR_ISL6271A is not set
+# CONFIG_REGULATOR_LP3971 is not set
+# CONFIG_REGULATOR_LP3972 is not set
+# CONFIG_REGULATOR_LP872X is not set
+# CONFIG_REGULATOR_LP8755 is not set
+# CONFIG_REGULATOR_LTC3589 is not set
+# CONFIG_REGULATOR_LTC3676 is not set
+# CONFIG_REGULATOR_MAX1586 is not set
+# CONFIG_REGULATOR_MAX77620 is not set
+# CONFIG_REGULATOR_MAX77857 is not set
+# CONFIG_REGULATOR_MAX8649 is not set
+# CONFIG_REGULATOR_MAX8660 is not set
+# CONFIG_REGULATOR_MAX8893 is not set
+# CONFIG_REGULATOR_MAX8952 is not set
+# CONFIG_REGULATOR_MAX8973 is not set
+# CONFIG_REGULATOR_MAX20086 is not set
+# CONFIG_REGULATOR_MAX20411 is not set
+# CONFIG_REGULATOR_MAX77826 is not set
+# CONFIG_REGULATOR_MCP16502 is not set
+# CONFIG_REGULATOR_MP5416 is not set
+# CONFIG_REGULATOR_MP8859 is not set
+# CONFIG_REGULATOR_MP886X is not set
+# CONFIG_REGULATOR_MPQ7920 is not set
+# CONFIG_REGULATOR_MT6311 is not set
+# CONFIG_REGULATOR_MT6315 is not set
+# CONFIG_REGULATOR_PCA9450 is not set
+# CONFIG_REGULATOR_PF8X00 is not set
+# CONFIG_REGULATOR_PFUZE100 is not set
+# CONFIG_REGULATOR_PV88060 is not set
+# CONFIG_REGULATOR_PV88080 is not set
+# CONFIG_REGULATOR_PV88090 is not set
+CONFIG_REGULATOR_PWM=y
+# CONFIG_REGULATOR_QCOM_SPMI is not set
+# CONFIG_REGULATOR_QCOM_USB_VBUS is not set
+# CONFIG_REGULATOR_RAA215300 is not set
+# CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY is not set
+# CONFIG_REGULATOR_RT4801 is not set
+# CONFIG_REGULATOR_RT4803 is not set
+# CONFIG_REGULATOR_RT5190A is not set
+# CONFIG_REGULATOR_RT5739 is not set
+# CONFIG_REGULATOR_RT5759 is not set
+# CONFIG_REGULATOR_RT6160 is not set
+# CONFIG_REGULATOR_RT6190 is not set
+# CONFIG_REGULATOR_RT6245 is not set
+# CONFIG_REGULATOR_RTQ2134 is not set
+# CONFIG_REGULATOR_RTMV20 is not set
+# CONFIG_REGULATOR_RTQ6752 is not set
+# CONFIG_REGULATOR_RTQ2208 is not set
+# CONFIG_REGULATOR_S2MPA01 is not set
+# CONFIG_REGULATOR_S2MPS11 is not set
+# CONFIG_REGULATOR_S5M8767 is not set
+# CONFIG_REGULATOR_SLG51000 is not set
+# CONFIG_REGULATOR_SY8106A is not set
+# CONFIG_REGULATOR_SY8824X is not set
+# CONFIG_REGULATOR_SY8827N is not set
+# CONFIG_REGULATOR_TPS51632 is not set
+# CONFIG_REGULATOR_TPS62360 is not set
+# CONFIG_REGULATOR_TPS6286X is not set
+# CONFIG_REGULATOR_TPS6287X is not set
+# CONFIG_REGULATOR_TPS65023 is not set
+# CONFIG_REGULATOR_TPS6507X is not set
+# CONFIG_REGULATOR_TPS65132 is not set
+# CONFIG_REGULATOR_TPS6524X is not set
+# CONFIG_REGULATOR_VCTRL is not set
+# CONFIG_REGULATOR_QCOM_LABIBB is not set
+CONFIG_RC_CORE=y
+# CONFIG_LIRC is not set
+CONFIG_RC_MAP=m
+CONFIG_RC_DECODERS=y
+CONFIG_IR_IMON_DECODER=m
+CONFIG_IR_JVC_DECODER=m
+CONFIG_IR_MCE_KBD_DECODER=m
+CONFIG_IR_NEC_DECODER=m
+CONFIG_IR_RC5_DECODER=m
+CONFIG_IR_RC6_DECODER=m
+CONFIG_IR_RCMM_DECODER=m
+CONFIG_IR_SANYO_DECODER=m
+CONFIG_IR_SHARP_DECODER=m
+CONFIG_IR_SONY_DECODER=m
+CONFIG_IR_XMP_DECODER=m
+CONFIG_RC_DEVICES=y
+# CONFIG_IR_GPIO_CIR is not set
+# CONFIG_IR_HIX5HD2 is not set
+# CONFIG_IR_IGORPLUGUSB is not set
+# CONFIG_IR_IGUANA is not set
+# CONFIG_IR_IMON is not set
+# CONFIG_IR_IMON_RAW is not set
+# CONFIG_IR_MCEUSB is not set
+# CONFIG_IR_REDRAT3 is not set
+CONFIG_IR_ROCKCHIP_CIR=m
+# CONFIG_IR_SERIAL is not set
+# CONFIG_IR_STREAMZAP is not set
+# CONFIG_IR_TOY is not set
+# CONFIG_IR_TTUSBIR is not set
+# CONFIG_RC_ATI_REMOTE is not set
+# CONFIG_RC_LOOPBACK is not set
+# CONFIG_RC_XBOX_DVD is not set
+CONFIG_CEC_CORE=y
+CONFIG_CEC_NOTIFIER=y
+
+#
+# CEC support
+#
+# CONFIG_MEDIA_CEC_RC is not set
+CONFIG_MEDIA_CEC_SUPPORT=y
+CONFIG_CEC_CH7322=y
+CONFIG_USB_PULSE8_CEC=m
+CONFIG_USB_RAINSHADOW_CEC=m
+# end of CEC support
+
+CONFIG_MEDIA_SUPPORT=y
+CONFIG_MEDIA_SUPPORT_FILTER=y
+CONFIG_MEDIA_SUBDRV_AUTOSELECT=y
+
+#
+# Media device types
+#
+CONFIG_MEDIA_CAMERA_SUPPORT=y
+# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set
+CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
+# CONFIG_MEDIA_RADIO_SUPPORT is not set
+# CONFIG_MEDIA_SDR_SUPPORT is not set
+CONFIG_MEDIA_PLATFORM_SUPPORT=y
+# CONFIG_MEDIA_TEST_SUPPORT is not set
+# end of Media device types
+
+CONFIG_VIDEO_DEV=y
+CONFIG_MEDIA_CONTROLLER=y
+CONFIG_DVB_CORE=y
+
+#
+# Video4Linux options
+#
+CONFIG_VIDEO_V4L2_I2C=y
+CONFIG_VIDEO_V4L2_SUBDEV_API=y
+# CONFIG_VIDEO_ADV_DEBUG is not set
+# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
+CONFIG_VIDEO_TUNER=m
+CONFIG_V4L2_H264=y
+CONFIG_V4L2_VP9=y
+CONFIG_V4L2_MEM2MEM_DEV=y
+CONFIG_V4L2_FLASH_LED_CLASS=m
+CONFIG_V4L2_FWNODE=m
+CONFIG_V4L2_ASYNC=m
+# end of Video4Linux options
+
+#
+# Media controller options
+#
+CONFIG_MEDIA_CONTROLLER_DVB=y
+CONFIG_MEDIA_CONTROLLER_REQUEST_API=y
+# end of Media controller options
+
+#
+# Digital TV options
+#
+# CONFIG_DVB_MMAP is not set
+# CONFIG_DVB_NET is not set
+CONFIG_DVB_MAX_ADAPTERS=16
+# CONFIG_DVB_DYNAMIC_MINORS is not set
+# CONFIG_DVB_DEMUX_SECTION_LOSS_LOG is not set
+# CONFIG_DVB_ULE_DEBUG is not set
+# end of Digital TV options
+
+#
+# Media drivers
+#
+
+#
+# Drivers filtered as selected at 'Filter media drivers'
+#
+
+#
+# Media drivers
+#
+CONFIG_MEDIA_USB_SUPPORT=y
+
+#
+# Webcam devices
+#
+CONFIG_USB_GSPCA=m
+CONFIG_USB_GSPCA_BENQ=m
+CONFIG_USB_GSPCA_CONEX=m
+CONFIG_USB_GSPCA_CPIA1=m
+CONFIG_USB_GSPCA_DTCS033=m
+CONFIG_USB_GSPCA_ETOMS=m
+CONFIG_USB_GSPCA_FINEPIX=m
+CONFIG_USB_GSPCA_JEILINJ=m
+CONFIG_USB_GSPCA_JL2005BCD=m
+CONFIG_USB_GSPCA_KINECT=m
+CONFIG_USB_GSPCA_KONICA=m
+CONFIG_USB_GSPCA_MARS=m
+CONFIG_USB_GSPCA_MR97310A=m
+CONFIG_USB_GSPCA_NW80X=m
+CONFIG_USB_GSPCA_OV519=m
+CONFIG_USB_GSPCA_OV534=m
+CONFIG_USB_GSPCA_OV534_9=m
+CONFIG_USB_GSPCA_PAC207=m
+CONFIG_USB_GSPCA_PAC7302=m
+CONFIG_USB_GSPCA_PAC7311=m
+CONFIG_USB_GSPCA_SE401=m
+CONFIG_USB_GSPCA_SN9C2028=m
+CONFIG_USB_GSPCA_SN9C20X=m
+CONFIG_USB_GSPCA_SONIXB=m
+CONFIG_USB_GSPCA_SONIXJ=m
+CONFIG_USB_GSPCA_SPCA1528=m
+CONFIG_USB_GSPCA_SPCA500=m
+CONFIG_USB_GSPCA_SPCA501=m
+CONFIG_USB_GSPCA_SPCA505=m
+CONFIG_USB_GSPCA_SPCA506=m
+CONFIG_USB_GSPCA_SPCA508=m
+CONFIG_USB_GSPCA_SPCA561=m
+CONFIG_USB_GSPCA_SQ905=m
+CONFIG_USB_GSPCA_SQ905C=m
+CONFIG_USB_GSPCA_SQ930X=m
+CONFIG_USB_GSPCA_STK014=m
+CONFIG_USB_GSPCA_STK1135=m
+CONFIG_USB_GSPCA_STV0680=m
+CONFIG_USB_GSPCA_SUNPLUS=m
+CONFIG_USB_GSPCA_T613=m
+CONFIG_USB_GSPCA_TOPRO=m
+CONFIG_USB_GSPCA_TOUPTEK=m
+CONFIG_USB_GSPCA_TV8532=m
+CONFIG_USB_GSPCA_VC032X=m
+CONFIG_USB_GSPCA_VICAM=m
+CONFIG_USB_GSPCA_XIRLINK_CIT=m
+CONFIG_USB_GSPCA_ZC3XX=m
+CONFIG_USB_GL860=m
+CONFIG_USB_M5602=m
+CONFIG_USB_STV06XX=m
+CONFIG_USB_PWC=m
+# CONFIG_USB_PWC_DEBUG is not set
+CONFIG_USB_PWC_INPUT_EVDEV=y
+CONFIG_USB_S2255=m
+CONFIG_VIDEO_USBTV=m
+CONFIG_USB_VIDEO_CLASS=m
+CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
+
+#
+# Analog/digital TV USB devices
+#
+CONFIG_VIDEO_AU0828=m
+CONFIG_VIDEO_AU0828_V4L2=y
+CONFIG_VIDEO_AU0828_RC=y
+CONFIG_VIDEO_CX231XX=m
+CONFIG_VIDEO_CX231XX_RC=y
+CONFIG_VIDEO_CX231XX_ALSA=m
+CONFIG_VIDEO_CX231XX_DVB=m
+
+#
+# Digital TV USB devices
+#
+CONFIG_DVB_AS102=m
+CONFIG_DVB_B2C2_FLEXCOP_USB=m
+CONFIG_DVB_B2C2_FLEXCOP_USB_DEBUG=y
+CONFIG_DVB_USB_V2=m
+CONFIG_DVB_USB_AF9015=m
+CONFIG_DVB_USB_AF9035=m
+CONFIG_DVB_USB_ANYSEE=m
+CONFIG_DVB_USB_AU6610=m
+CONFIG_DVB_USB_AZ6007=m
+CONFIG_DVB_USB_CE6230=m
+CONFIG_DVB_USB_DVBSKY=m
+CONFIG_DVB_USB_EC168=m
+CONFIG_DVB_USB_GL861=m
+CONFIG_DVB_USB_LME2510=m
+CONFIG_DVB_USB_MXL111SF=m
+CONFIG_DVB_USB_RTL28XXU=m
+CONFIG_DVB_USB_ZD1301=m
+CONFIG_DVB_USB=m
+# CONFIG_DVB_USB_DEBUG is not set
+CONFIG_DVB_USB_A800=m
+CONFIG_DVB_USB_AF9005=m
+CONFIG_DVB_USB_AF9005_REMOTE=m
+CONFIG_DVB_USB_AZ6027=m
+CONFIG_DVB_USB_CINERGY_T2=m
+CONFIG_DVB_USB_CXUSB=m
+CONFIG_DVB_USB_CXUSB_ANALOG=y
+CONFIG_DVB_USB_DIB0700=m
+CONFIG_DVB_USB_DIB3000MC=m
+CONFIG_DVB_USB_DIBUSB_MB=m
+CONFIG_DVB_USB_DIBUSB_MB_FAULTY=y
+CONFIG_DVB_USB_DIBUSB_MC=m
+CONFIG_DVB_USB_DIGITV=m
+CONFIG_DVB_USB_DTT200U=m
+CONFIG_DVB_USB_DTV5100=m
+CONFIG_DVB_USB_DW2102=m
+CONFIG_DVB_USB_GP8PSK=m
+CONFIG_DVB_USB_M920X=m
+CONFIG_DVB_USB_NOVA_T_USB2=m
+CONFIG_DVB_USB_OPERA1=m
+CONFIG_DVB_USB_PCTV452E=m
+CONFIG_DVB_USB_TECHNISAT_USB2=m
+CONFIG_DVB_USB_TTUSB2=m
+CONFIG_DVB_USB_UMT_010=m
+CONFIG_DVB_USB_VP702X=m
+CONFIG_DVB_USB_VP7045=m
+CONFIG_SMS_USB_DRV=m
+
+#
+# Webcam, TV (analog/digital) USB devices
+#
+CONFIG_VIDEO_EM28XX=m
+CONFIG_VIDEO_EM28XX_V4L2=m
+CONFIG_VIDEO_EM28XX_ALSA=m
+CONFIG_VIDEO_EM28XX_DVB=m
+CONFIG_VIDEO_EM28XX_RC=m
+CONFIG_MEDIA_PLATFORM_DRIVERS=y
+# CONFIG_V4L_PLATFORM_DRIVERS is not set
+# CONFIG_DVB_PLATFORM_DRIVERS is not set
+CONFIG_V4L_MEM2MEM_DRIVERS=y
+# CONFIG_VIDEO_MEM2MEM_DEINTERLACE is not set
+
+#
+# Allegro DVT media platform drivers
+#
+
+#
+# Amlogic media platform drivers
+#
+
+#
+# Amphion drivers
+#
+
+#
+# Aspeed media platform drivers
+#
+
+#
+# Atmel media platform drivers
+#
+
+#
+# Cadence media platform drivers
+#
+# CONFIG_VIDEO_CADENCE_CSI2RX is not set
+# CONFIG_VIDEO_CADENCE_CSI2TX is not set
+
+#
+# Chips&Media media platform drivers
+#
+
+#
+# Intel media platform drivers
+#
+
+#
+# Marvell media platform drivers
+#
+
+#
+# Mediatek media platform drivers
+#
+
+#
+# Microchip Technology, Inc. media platform drivers
+#
+
+#
+# NVidia media platform drivers
+#
+
+#
+# NXP media platform drivers
+#
+
+#
+# Qualcomm media platform drivers
+#
+
+#
+# Renesas media platform drivers
+#
+
+#
+# Rockchip media platform drivers
+#
+CONFIG_VIDEO_ROCKCHIP_IEP=y
+CONFIG_VIDEO_ROCKCHIP_RGA=y
+
+#
+# Samsung media platform drivers
+#
+
+#
+# STMicroelectronics media platform drivers
+#
+
+#
+# Sunxi media platform drivers
+#
+
+#
+# Texas Instruments drivers
+#
+
+#
+# Verisilicon media platform drivers
+#
+CONFIG_VIDEO_HANTRO=y
+CONFIG_VIDEO_HANTRO_ROCKCHIP=y
+
+#
+# VIA media platform drivers
+#
+
+#
+# Xilinx media platform drivers
+#
+
+#
+# MMC/SDIO DVB adapters
+#
+# CONFIG_SMS_SDIO_DRV is not set
+CONFIG_MEDIA_COMMON_OPTIONS=y
+
+#
+# common driver options
+#
+CONFIG_CYPRESS_FIRMWARE=m
+CONFIG_TTPCI_EEPROM=m
+CONFIG_UVC_COMMON=m
+CONFIG_VIDEO_CX2341X=m
+CONFIG_VIDEO_TVEEPROM=m
+CONFIG_DVB_B2C2_FLEXCOP=m
+CONFIG_DVB_B2C2_FLEXCOP_DEBUG=y
+CONFIG_SMS_SIANO_MDTV=m
+CONFIG_SMS_SIANO_RC=y
+CONFIG_VIDEOBUF2_CORE=y
+CONFIG_VIDEOBUF2_V4L2=y
+CONFIG_VIDEOBUF2_MEMOPS=y
+CONFIG_VIDEOBUF2_DMA_CONTIG=y
+CONFIG_VIDEOBUF2_VMALLOC=y
+CONFIG_VIDEOBUF2_DMA_SG=y
+# end of Media drivers
+
+CONFIG_MEDIA_HIDE_ANCILLARY_SUBDRV=y
+
+#
+# Media ancillary drivers
+#
+CONFIG_MEDIA_ATTACH=y
+
+#
+# IR I2C driver auto-selected by 'Autoselect ancillary drivers'
+#
+CONFIG_VIDEO_IR_I2C=y
+# CONFIG_VIDEO_CAMERA_SENSOR is not set
+
+#
+# Lens drivers
+#
+# CONFIG_VIDEO_AD5820 is not set
+# CONFIG_VIDEO_AK7375 is not set
+# CONFIG_VIDEO_DW9714 is not set
+# CONFIG_VIDEO_DW9719 is not set
+# CONFIG_VIDEO_DW9768 is not set
+# CONFIG_VIDEO_DW9807_VCM is not set
+# end of Lens drivers
+
+#
+# Flash devices
+#
+# CONFIG_VIDEO_ADP1653 is not set
+# CONFIG_VIDEO_LM3560 is not set
+# CONFIG_VIDEO_LM3646 is not set
+# end of Flash devices
+
+#
+# audio, video and radio I2C drivers auto-selected by 'Autoselect ancillary drivers'
+#
+CONFIG_VIDEO_MSP3400=m
+CONFIG_VIDEO_SAA711X=m
+CONFIG_VIDEO_TVP5150=m
+
+#
+# Video and audio decoders
+#
+CONFIG_VIDEO_CX25840=m
+
+#
+# Video serializers and deserializers
+#
+# CONFIG_VIDEO_DS90UB913 is not set
+# CONFIG_VIDEO_DS90UB953 is not set
+# CONFIG_VIDEO_DS90UB960 is not set
+# end of Video serializers and deserializers
+
+#
+# SPI I2C drivers auto-selected by 'Autoselect ancillary drivers'
+#
+
+#
+# Media SPI Adapters
+#
+# CONFIG_CXD2880_SPI_DRV is not set
+# CONFIG_VIDEO_GS1662 is not set
+# end of Media SPI Adapters
+
+CONFIG_MEDIA_TUNER=y
+
+#
+# Tuner drivers auto-selected by 'Autoselect ancillary drivers'
+#
+CONFIG_MEDIA_TUNER_E4000=m
+CONFIG_MEDIA_TUNER_FC0011=m
+CONFIG_MEDIA_TUNER_FC0012=m
+CONFIG_MEDIA_TUNER_FC0013=m
+CONFIG_MEDIA_TUNER_FC2580=m
+CONFIG_MEDIA_TUNER_IT913X=m
+CONFIG_MEDIA_TUNER_MAX2165=m
+CONFIG_MEDIA_TUNER_MC44S803=y
+CONFIG_MEDIA_TUNER_MT2060=m
+CONFIG_MEDIA_TUNER_MT2063=m
+CONFIG_MEDIA_TUNER_MT20XX=y
+CONFIG_MEDIA_TUNER_MT2266=m
+CONFIG_MEDIA_TUNER_MXL5005S=m
+CONFIG_MEDIA_TUNER_MXL5007T=m
+CONFIG_MEDIA_TUNER_QM1D1C0042=m
+CONFIG_MEDIA_TUNER_QT1010=m
+CONFIG_MEDIA_TUNER_R820T=m
+CONFIG_MEDIA_TUNER_SI2157=m
+CONFIG_MEDIA_TUNER_SIMPLE=y
+CONFIG_MEDIA_TUNER_TDA18212=m
+CONFIG_MEDIA_TUNER_TDA18218=m
+CONFIG_MEDIA_TUNER_TDA18250=m
+CONFIG_MEDIA_TUNER_TDA18271=y
+CONFIG_MEDIA_TUNER_TDA827X=y
+CONFIG_MEDIA_TUNER_TDA8290=y
+CONFIG_MEDIA_TUNER_TDA9887=y
+CONFIG_MEDIA_TUNER_TUA9001=m
+CONFIG_MEDIA_TUNER_XC2028=y
+CONFIG_MEDIA_TUNER_XC4000=y
+CONFIG_MEDIA_TUNER_XC5000=y
+
+#
+# DVB Frontend drivers auto-selected by 'Autoselect ancillary drivers'
+#
+
+#
+# Multistandard (satellite) frontends
+#
+CONFIG_DVB_M88DS3103=m
+CONFIG_DVB_STB0899=m
+CONFIG_DVB_STB6100=m
+CONFIG_DVB_STV090x=m
+CONFIG_DVB_STV6110x=m
+
+#
+# Multistandard (cable + terrestrial) frontends
+#
+CONFIG_DVB_DRXK=m
+CONFIG_DVB_MN88472=m
+CONFIG_DVB_MN88473=m
+CONFIG_DVB_SI2165=m
+CONFIG_DVB_TDA18271C2DD=m
+
+#
+# DVB-S (satellite) frontends
+#
+CONFIG_DVB_CX24116=m
+CONFIG_DVB_CX24120=m
+CONFIG_DVB_CX24123=m
+CONFIG_DVB_DS3000=m
+CONFIG_DVB_MT312=m
+CONFIG_DVB_S5H1420=m
+CONFIG_DVB_SI21XX=m
+CONFIG_DVB_STB6000=m
+CONFIG_DVB_STV0288=m
+CONFIG_DVB_STV0299=m
+CONFIG_DVB_STV0900=m
+CONFIG_DVB_STV6110=m
+CONFIG_DVB_TDA10071=m
+CONFIG_DVB_TDA10086=m
+CONFIG_DVB_TDA826X=m
+CONFIG_DVB_TS2020=m
+CONFIG_DVB_TUNER_CX24113=m
+CONFIG_DVB_TUNER_ITD1000=m
+CONFIG_DVB_ZL10039=m
+
+#
+# DVB-T (terrestrial) frontends
+#
+CONFIG_DVB_AF9013=m
+CONFIG_DVB_AS102_FE=m
+CONFIG_DVB_CX22702=m
+CONFIG_DVB_CXD2820R=m
+CONFIG_DVB_CXD2841ER=m
+CONFIG_DVB_DIB3000MB=m
+CONFIG_DVB_DIB3000MC=m
+CONFIG_DVB_DIB7000M=m
+CONFIG_DVB_DIB7000P=m
+CONFIG_DVB_DRXD=m
+CONFIG_DVB_EC100=m
+CONFIG_DVB_GP8PSK_FE=m
+CONFIG_DVB_MT352=m
+CONFIG_DVB_NXT6000=m
+CONFIG_DVB_RTL2830=m
+CONFIG_DVB_RTL2832=m
+CONFIG_DVB_SI2168=m
+CONFIG_DVB_TDA10048=m
+CONFIG_DVB_TDA1004X=m
+CONFIG_DVB_ZD1301_DEMOD=m
+CONFIG_DVB_ZL10353=m
+
+#
+# DVB-C (cable) frontends
+#
+CONFIG_DVB_STV0297=m
+CONFIG_DVB_TDA10023=m
+
+#
+# ATSC (North American/Korean Terrestrial/Cable DTV) frontends
+#
+CONFIG_DVB_AU8522=m
+CONFIG_DVB_AU8522_DTV=m
+CONFIG_DVB_AU8522_V4L=m
+CONFIG_DVB_BCM3510=m
+CONFIG_DVB_LG2160=m
+CONFIG_DVB_LGDT3305=m
+CONFIG_DVB_LGDT3306A=m
+CONFIG_DVB_LGDT330X=m
+CONFIG_DVB_MXL692=m
+CONFIG_DVB_NXT200X=m
+CONFIG_DVB_S5H1409=m
+CONFIG_DVB_S5H1411=m
+
+#
+# ISDB-T (terrestrial) frontends
+#
+CONFIG_DVB_DIB8000=m
+CONFIG_DVB_MB86A20S=m
+CONFIG_DVB_S921=m
+
+#
+# ISDB-S (satellite) & ISDB-T (terrestrial) frontends
+#
+CONFIG_DVB_TC90522=m
+
+#
+# Digital terrestrial only tuners/PLL
+#
+CONFIG_DVB_PLL=m
+CONFIG_DVB_TUNER_DIB0070=m
+CONFIG_DVB_TUNER_DIB0090=m
+
+#
+# SEC control devices for DVB-S
+#
+CONFIG_DVB_A8293=m
+CONFIG_DVB_AF9033=m
+CONFIG_DVB_ATBM8830=m
+CONFIG_DVB_ISL6421=m
+CONFIG_DVB_ISL6423=m
+CONFIG_DVB_IX2505V=m
+CONFIG_DVB_LGS8GXX=m
+CONFIG_DVB_LNBP21=m
+CONFIG_DVB_LNBP22=m
+CONFIG_DVB_M88RS2000=m
+CONFIG_DVB_DRX39XYJ=m
+
+#
+# Common Interface (EN50221) controller drivers
+#
+CONFIG_DVB_SP2=m
+# end of Media ancillary drivers
+
+#
+# Graphics support
+#
+CONFIG_VIDEO_CMDLINE=y
+CONFIG_VIDEO_NOMODESET=y
+# CONFIG_AUXDISPLAY is not set
+CONFIG_DRM=y
+# CONFIG_DRM_DEBUG_MM is not set
+CONFIG_DRM_KMS_HELPER=y
+CONFIG_DRM_FBDEV_EMULATION=y
+CONFIG_DRM_FBDEV_OVERALLOC=300
+CONFIG_DRM_LOAD_EDID_FIRMWARE=y
+CONFIG_DRM_DISPLAY_HELPER=y
+CONFIG_DRM_DISPLAY_HDMI_HELPER=y
+# CONFIG_DRM_DP_AUX_CHARDEV is not set
+# CONFIG_DRM_DP_CEC is not set
+CONFIG_DRM_GEM_DMA_HELPER=y
+CONFIG_DRM_GEM_SHMEM_HELPER=y
+CONFIG_DRM_SCHED=y
+
+#
+# I2C encoder or helper chips
+#
+# CONFIG_DRM_I2C_CH7006 is not set
+# CONFIG_DRM_I2C_SIL164 is not set
+# CONFIG_DRM_I2C_NXP_TDA998X is not set
+# CONFIG_DRM_I2C_NXP_TDA9950 is not set
+# end of I2C encoder or helper chips
+
+#
+# ARM devices
+#
+# CONFIG_DRM_HDLCD is not set
+# CONFIG_DRM_MALI_DISPLAY is not set
+# CONFIG_DRM_KOMEDA is not set
+# end of ARM devices
+
+CONFIG_DRM_VGEM=y
+# CONFIG_DRM_VKMS is not set
+CONFIG_DRM_ROCKCHIP=y
+CONFIG_ROCKCHIP_VOP=y
+# CONFIG_ROCKCHIP_VOP2 is not set
+# CONFIG_ROCKCHIP_ANALOGIX_DP is not set
+# CONFIG_ROCKCHIP_CDN_DP is not set
+CONFIG_ROCKCHIP_DW_HDMI=y
+# CONFIG_ROCKCHIP_DW_MIPI_DSI is not set
+# CONFIG_ROCKCHIP_INNO_HDMI is not set
+# CONFIG_ROCKCHIP_LVDS is not set
+CONFIG_ROCKCHIP_RGB=y
+# CONFIG_ROCKCHIP_RK3066_HDMI is not set
+# CONFIG_DRM_UDL is not set
+# CONFIG_DRM_ARMADA is not set
+# CONFIG_DRM_TILCDC is not set
+# CONFIG_DRM_VIRTIO_GPU is not set
+# CONFIG_DRM_FSL_DCU is not set
+CONFIG_DRM_PANEL=y
+
+#
+# Display Panels
+#
+# CONFIG_DRM_PANEL_ABT_Y030XX067A is not set
+# CONFIG_DRM_PANEL_ARM_VERSATILE is not set
+# CONFIG_DRM_PANEL_AUO_A030JTN01 is not set
+# CONFIG_DRM_PANEL_LVDS is not set
+# CONFIG_DRM_PANEL_SIMPLE is not set
+# CONFIG_DRM_PANEL_EDP is not set
+# CONFIG_DRM_PANEL_ILITEK_IL9322 is not set
+# CONFIG_DRM_PANEL_ILITEK_ILI9341 is not set
+# CONFIG_DRM_PANEL_INNOLUX_EJ030NA is not set
+# CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set
+# CONFIG_DRM_PANEL_LG_LB035Q02 is not set
+# CONFIG_DRM_PANEL_LG_LG4573 is not set
+# CONFIG_DRM_PANEL_NEC_NL8048HL11 is not set
+# CONFIG_DRM_PANEL_NEWVISION_NV3052C is not set
+# CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set
+# CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set
+# CONFIG_DRM_PANEL_ORISETECH_OTA5601A is not set
+# CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20 is not set
+# CONFIG_DRM_PANEL_SAMSUNG_DB7430 is not set
+# CONFIG_DRM_PANEL_SAMSUNG_S6D27A1 is not set
+# CONFIG_DRM_PANEL_SAMSUNG_S6D7AA0 is not set
+# CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set
+# CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 is not set
+# CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set
+# CONFIG_DRM_PANEL_SEIKO_43WVF1G is not set
+# CONFIG_DRM_PANEL_SHARP_LS037V7DW01 is not set
+# CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set
+# CONFIG_DRM_PANEL_SONY_ACX565AKM is not set
+# CONFIG_DRM_PANEL_TPO_TD028TTEC1 is not set
+# CONFIG_DRM_PANEL_TPO_TD043MTEA1 is not set
+# CONFIG_DRM_PANEL_TPO_TPG110 is not set
+# CONFIG_DRM_PANEL_WIDECHIPS_WS2401 is not set
+# end of Display Panels
+
+CONFIG_DRM_BRIDGE=y
+CONFIG_DRM_PANEL_BRIDGE=y
+
+#
+# Display Interface Bridges
+#
+# CONFIG_DRM_CHIPONE_ICN6211 is not set
+# CONFIG_DRM_CHRONTEL_CH7033 is not set
+# CONFIG_DRM_DISPLAY_CONNECTOR is not set
+# CONFIG_DRM_ITE_IT6505 is not set
+# CONFIG_DRM_LONTIUM_LT8912B is not set
+# CONFIG_DRM_LONTIUM_LT9211 is not set
+# CONFIG_DRM_LONTIUM_LT9611 is not set
+# CONFIG_DRM_LONTIUM_LT9611UXC is not set
+# CONFIG_DRM_ITE_IT66121 is not set
+# CONFIG_DRM_LVDS_CODEC is not set
+# CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set
+# CONFIG_DRM_NWL_MIPI_DSI is not set
+# CONFIG_DRM_NXP_PTN3460 is not set
+# CONFIG_DRM_PARADE_PS8622 is not set
+# CONFIG_DRM_PARADE_PS8640 is not set
+# CONFIG_DRM_SAMSUNG_DSIM is not set
+# CONFIG_DRM_SIL_SII8620 is not set
+# CONFIG_DRM_SII902X is not set
+# CONFIG_DRM_SII9234 is not set
+# CONFIG_DRM_SIMPLE_BRIDGE is not set
+# CONFIG_DRM_THINE_THC63LVD1024 is not set
+# CONFIG_DRM_TOSHIBA_TC358762 is not set
+# CONFIG_DRM_TOSHIBA_TC358764 is not set
+# CONFIG_DRM_TOSHIBA_TC358767 is not set
+# CONFIG_DRM_TOSHIBA_TC358768 is not set
+# CONFIG_DRM_TOSHIBA_TC358775 is not set
+# CONFIG_DRM_TI_DLPC3433 is not set
+# CONFIG_DRM_TI_TFP410 is not set
+# CONFIG_DRM_TI_SN65DSI83 is not set
+# CONFIG_DRM_TI_SN65DSI86 is not set
+# CONFIG_DRM_TI_TPD12S015 is not set
+# CONFIG_DRM_ANALOGIX_ANX6345 is not set
+# CONFIG_DRM_ANALOGIX_ANX78XX is not set
+# CONFIG_DRM_ANALOGIX_ANX7625 is not set
+# CONFIG_DRM_I2C_ADV7511 is not set
+# CONFIG_DRM_CDNS_DSI is not set
+# CONFIG_DRM_CDNS_MHDP8546 is not set
+CONFIG_DRM_DW_HDMI=y
+# CONFIG_DRM_DW_HDMI_AHB_AUDIO is not set
+CONFIG_DRM_DW_HDMI_I2S_AUDIO=m
+# CONFIG_DRM_DW_HDMI_GP_AUDIO is not set
+CONFIG_DRM_DW_HDMI_CEC=y
+# end of Display Interface Bridges
+
+# CONFIG_DRM_ETNAVIV is not set
+# CONFIG_DRM_LOGICVC is not set
+# CONFIG_DRM_ARCPGU is not set
+# CONFIG_DRM_GM12U320 is not set
+# CONFIG_DRM_PANEL_MIPI_DBI is not set
+# CONFIG_DRM_SIMPLEDRM is not set
+# CONFIG_TINYDRM_HX8357D is not set
+# CONFIG_TINYDRM_ILI9163 is not set
+# CONFIG_TINYDRM_ILI9225 is not set
+# CONFIG_TINYDRM_ILI9341 is not set
+# CONFIG_TINYDRM_ILI9486 is not set
+# CONFIG_TINYDRM_MI0283QT is not set
+# CONFIG_TINYDRM_REPAPER is not set
+# CONFIG_TINYDRM_ST7586 is not set
+# CONFIG_TINYDRM_ST7735R is not set
+# CONFIG_DRM_PL111 is not set
+# CONFIG_DRM_TVE200 is not set
+CONFIG_DRM_LIMA=y
+# CONFIG_DRM_PANFROST is not set
+# CONFIG_DRM_MCDE is not set
+# CONFIG_DRM_TIDSS is not set
+# CONFIG_DRM_GUD is not set
+# CONFIG_DRM_SSD130X is not set
+# CONFIG_DRM_LEGACY is not set
+CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
+
+#
+# Frame buffer Devices
+#
+CONFIG_FB=y
+# CONFIG_FB_ARMCLCD is not set
+# CONFIG_FB_OPENCORES is not set
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_SMSCUFX is not set
+# CONFIG_FB_UDL is not set
+# CONFIG_FB_IBM_GXT4500 is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_SIMPLE is not set
+# CONFIG_FB_SSD1307 is not set
+CONFIG_FB_CORE=y
+CONFIG_FB_NOTIFY=y
+CONFIG_FIRMWARE_EDID=y
+CONFIG_FB_DEVICE=y
+CONFIG_FB_SYS_FILLRECT=y
+CONFIG_FB_SYS_COPYAREA=y
+CONFIG_FB_SYS_IMAGEBLIT=y
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+CONFIG_FB_SYS_FOPS=y
+CONFIG_FB_DEFERRED_IO=y
+CONFIG_FB_DMAMEM_HELPERS=y
+CONFIG_FB_IOMEM_FOPS=y
+CONFIG_FB_SYSMEM_HELPERS=y
+CONFIG_FB_SYSMEM_HELPERS_DEFERRED=y
+CONFIG_FB_MODE_HELPERS=y
+# CONFIG_FB_TILEBLITTING is not set
+# end of Frame buffer Devices
+
+#
+# Backlight & LCD device support
+#
+# CONFIG_LCD_CLASS_DEVICE is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+# CONFIG_BACKLIGHT_KTD253 is not set
+# CONFIG_BACKLIGHT_KTZ8866 is not set
+# CONFIG_BACKLIGHT_PWM is not set
+# CONFIG_BACKLIGHT_QCOM_WLED is not set
+# CONFIG_BACKLIGHT_ADP8860 is not set
+# CONFIG_BACKLIGHT_ADP8870 is not set
+# CONFIG_BACKLIGHT_LM3630A is not set
+# CONFIG_BACKLIGHT_LM3639 is not set
+# CONFIG_BACKLIGHT_LP855X is not set
+# CONFIG_BACKLIGHT_GPIO is not set
+# CONFIG_BACKLIGHT_LV5207LP is not set
+# CONFIG_BACKLIGHT_BD6107 is not set
+# CONFIG_BACKLIGHT_ARCXCNN is not set
+# CONFIG_BACKLIGHT_LED is not set
+# end of Backlight & LCD device support
+
+CONFIG_VIDEOMODE_HELPERS=y
+CONFIG_HDMI=y
+
+#
+# Console display driver support
+#
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE_LEGACY_ACCELERATION=y
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER is not set
+# end of Console display driver support
+
+# CONFIG_LOGO is not set
+# end of Graphics support
+
+# CONFIG_DRM_ACCEL is not set
+CONFIG_SOUND=y
+CONFIG_SOUND_OSS_CORE=y
+CONFIG_SOUND_OSS_CORE_PRECLAIM=y
+CONFIG_SND=m
+CONFIG_SND_TIMER=m
+CONFIG_SND_PCM=m
+CONFIG_SND_PCM_ELD=y
+CONFIG_SND_PCM_IEC958=y
+CONFIG_SND_DMAENGINE_PCM=m
+CONFIG_SND_SEQ_DEVICE=m
+CONFIG_SND_RAWMIDI=m
+CONFIG_SND_JACK=y
+CONFIG_SND_JACK_INPUT_DEV=y
+CONFIG_SND_OSSEMUL=y
+# CONFIG_SND_MIXER_OSS is not set
+CONFIG_SND_PCM_OSS=m
+CONFIG_SND_PCM_OSS_PLUGINS=y
+CONFIG_SND_PCM_TIMER=y
+CONFIG_SND_HRTIMER=m
+# CONFIG_SND_DYNAMIC_MINORS is not set
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_PROC_FS=y
+CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_VERBOSE_PRINTK is not set
+CONFIG_SND_CTL_FAST_LOOKUP=y
+# CONFIG_SND_DEBUG is not set
+# CONFIG_SND_CTL_INPUT_VALIDATION is not set
+CONFIG_SND_SEQUENCER=m
+CONFIG_SND_SEQ_DUMMY=m
+# CONFIG_SND_SEQUENCER_OSS is not set
+CONFIG_SND_SEQ_HRTIMER_DEFAULT=y
+CONFIG_SND_SEQ_MIDI_EVENT=m
+CONFIG_SND_SEQ_MIDI=m
+CONFIG_SND_SEQ_VIRMIDI=m
+CONFIG_SND_SEQ_UMP=y
+CONFIG_SND_MPU401_UART=m
+CONFIG_SND_DRIVERS=y
+CONFIG_SND_DUMMY=m
+CONFIG_SND_ALOOP=m
+# CONFIG_SND_PCMTEST is not set
+CONFIG_SND_VIRMIDI=m
+CONFIG_SND_MTPAV=m
+CONFIG_SND_SERIAL_U16550=m
+# CONFIG_SND_SERIAL_GENERIC is not set
+CONFIG_SND_MPU401=m
+
+#
+# HD-Audio
+#
+# end of HD-Audio
+
+CONFIG_SND_HDA_PREALLOC_SIZE=64
+# CONFIG_SND_ARM is not set
+CONFIG_SND_SPI=y
+# CONFIG_SND_USB is not set
+CONFIG_SND_SOC=m
+CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y
+# CONFIG_SND_SOC_ADI is not set
+# CONFIG_SND_SOC_AMD_ACP is not set
+# CONFIG_SND_AMD_ACP_CONFIG is not set
+# CONFIG_SND_ATMEL_SOC is not set
+# CONFIG_SND_BCM63XX_I2S_WHISTLER is not set
+# CONFIG_SND_DESIGNWARE_I2S is not set
+
+#
+# SoC Audio for Freescale CPUs
+#
+
+#
+# Common SoC Audio options for Freescale CPUs:
+#
+# CONFIG_SND_SOC_FSL_ASRC is not set
+# CONFIG_SND_SOC_FSL_SAI is not set
+# CONFIG_SND_SOC_FSL_AUDMIX is not set
+# CONFIG_SND_SOC_FSL_SSI is not set
+# CONFIG_SND_SOC_FSL_SPDIF is not set
+# CONFIG_SND_SOC_FSL_ESAI is not set
+# CONFIG_SND_SOC_FSL_MICFIL is not set
+# CONFIG_SND_SOC_FSL_XCVR is not set
+# CONFIG_SND_SOC_IMX_AUDMUX is not set
+# end of SoC Audio for Freescale CPUs
+
+# CONFIG_SND_SOC_CHV3_I2S is not set
+# CONFIG_SND_I2S_HI6210_I2S is not set
+# CONFIG_SND_SOC_IMG is not set
+# CONFIG_SND_SOC_MTK_BTCVSD is not set
+CONFIG_SND_SOC_ROCKCHIP=m
+CONFIG_SND_SOC_ROCKCHIP_I2S=m
+CONFIG_SND_SOC_ROCKCHIP_I2S_TDM=m
+CONFIG_SND_SOC_ROCKCHIP_PDM=m
+CONFIG_SND_SOC_ROCKCHIP_SPDIF=m
+CONFIG_SND_SOC_ROCKCHIP_MAX98090=m
+CONFIG_SND_SOC_ROCKCHIP_RT5645=m
+# CONFIG_SND_SOC_RK3288_HDMI_ANALOG is not set
+# CONFIG_SND_SOC_RK3399_GRU_SOUND is not set
+# CONFIG_SND_SOC_SOF_TOPLEVEL is not set
+
+#
+# STMicroelectronics STM32 SOC audio support
+#
+# end of STMicroelectronics STM32 SOC audio support
+
+# CONFIG_SND_SOC_XILINX_I2S is not set
+# CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER is not set
+# CONFIG_SND_SOC_XILINX_SPDIF is not set
+# CONFIG_SND_SOC_XTFPGA_I2S is not set
+CONFIG_SND_SOC_I2C_AND_SPI=m
+
+#
+# CODEC drivers
+#
+# CONFIG_SND_SOC_AC97_CODEC is not set
+# CONFIG_SND_SOC_ADAU1372_I2C is not set
+# CONFIG_SND_SOC_ADAU1372_SPI is not set
+# CONFIG_SND_SOC_ADAU1701 is not set
+# CONFIG_SND_SOC_ADAU1761_I2C is not set
+# CONFIG_SND_SOC_ADAU1761_SPI is not set
+# CONFIG_SND_SOC_ADAU7002 is not set
+# CONFIG_SND_SOC_ADAU7118_HW is not set
+# CONFIG_SND_SOC_ADAU7118_I2C is not set
+# CONFIG_SND_SOC_AK4104 is not set
+# CONFIG_SND_SOC_AK4118 is not set
+# CONFIG_SND_SOC_AK4375 is not set
+# CONFIG_SND_SOC_AK4458 is not set
+# CONFIG_SND_SOC_AK4554 is not set
+# CONFIG_SND_SOC_AK4613 is not set
+# CONFIG_SND_SOC_AK4642 is not set
+# CONFIG_SND_SOC_AK5386 is not set
+# CONFIG_SND_SOC_AK5558 is not set
+# CONFIG_SND_SOC_ALC5623 is not set
+# CONFIG_SND_SOC_AW8738 is not set
+# CONFIG_SND_SOC_AW88395 is not set
+# CONFIG_SND_SOC_AW88261 is not set
+# CONFIG_SND_SOC_BD28623 is not set
+# CONFIG_SND_SOC_BT_SCO is not set
+# CONFIG_SND_SOC_CHV3_CODEC is not set
+# CONFIG_SND_SOC_CS35L32 is not set
+# CONFIG_SND_SOC_CS35L33 is not set
+# CONFIG_SND_SOC_CS35L34 is not set
+# CONFIG_SND_SOC_CS35L35 is not set
+# CONFIG_SND_SOC_CS35L36 is not set
+# CONFIG_SND_SOC_CS35L41_SPI is not set
+# CONFIG_SND_SOC_CS35L41_I2C is not set
+# CONFIG_SND_SOC_CS35L45_SPI is not set
+# CONFIG_SND_SOC_CS35L45_I2C is not set
+# CONFIG_SND_SOC_CS35L56_I2C is not set
+# CONFIG_SND_SOC_CS35L56_SPI is not set
+# CONFIG_SND_SOC_CS42L42 is not set
+# CONFIG_SND_SOC_CS42L51_I2C is not set
+# CONFIG_SND_SOC_CS42L52 is not set
+# CONFIG_SND_SOC_CS42L56 is not set
+# CONFIG_SND_SOC_CS42L73 is not set
+# CONFIG_SND_SOC_CS42L83 is not set
+# CONFIG_SND_SOC_CS4234 is not set
+# CONFIG_SND_SOC_CS4265 is not set
+# CONFIG_SND_SOC_CS4270 is not set
+# CONFIG_SND_SOC_CS4271_I2C is not set
+# CONFIG_SND_SOC_CS4271_SPI is not set
+# CONFIG_SND_SOC_CS42XX8_I2C is not set
+# CONFIG_SND_SOC_CS43130 is not set
+# CONFIG_SND_SOC_CS4341 is not set
+# CONFIG_SND_SOC_CS4349 is not set
+# CONFIG_SND_SOC_CS53L30 is not set
+# CONFIG_SND_SOC_CX2072X is not set
+# CONFIG_SND_SOC_DA7213 is not set
+# CONFIG_SND_SOC_DMIC is not set
+CONFIG_SND_SOC_HDMI_CODEC=m
+# CONFIG_SND_SOC_ES7134 is not set
+# CONFIG_SND_SOC_ES7241 is not set
+# CONFIG_SND_SOC_ES8316 is not set
+# CONFIG_SND_SOC_ES8326 is not set
+# CONFIG_SND_SOC_ES8328_I2C is not set
+# CONFIG_SND_SOC_ES8328_SPI is not set
+# CONFIG_SND_SOC_GTM601 is not set
+# CONFIG_SND_SOC_HDA is not set
+# CONFIG_SND_SOC_ICS43432 is not set
+# CONFIG_SND_SOC_IDT821034 is not set
+# CONFIG_SND_SOC_INNO_RK3036 is not set
+# CONFIG_SND_SOC_MAX98088 is not set
+CONFIG_SND_SOC_MAX98090=m
+# CONFIG_SND_SOC_MAX98357A is not set
+# CONFIG_SND_SOC_MAX98504 is not set
+# CONFIG_SND_SOC_MAX9867 is not set
+# CONFIG_SND_SOC_MAX98927 is not set
+# CONFIG_SND_SOC_MAX98520 is not set
+# CONFIG_SND_SOC_MAX98373_I2C is not set
+# CONFIG_SND_SOC_MAX98388 is not set
+# CONFIG_SND_SOC_MAX98390 is not set
+# CONFIG_SND_SOC_MAX98396 is not set
+# CONFIG_SND_SOC_MAX9860 is not set
+# CONFIG_SND_SOC_MSM8916_WCD_ANALOG is not set
+# CONFIG_SND_SOC_MSM8916_WCD_DIGITAL is not set
+# CONFIG_SND_SOC_PCM1681 is not set
+# CONFIG_SND_SOC_PCM1789_I2C is not set
+# CONFIG_SND_SOC_PCM179X_I2C is not set
+# CONFIG_SND_SOC_PCM179X_SPI is not set
+# CONFIG_SND_SOC_PCM186X_I2C is not set
+# CONFIG_SND_SOC_PCM186X_SPI is not set
+# CONFIG_SND_SOC_PCM3060_I2C is not set
+# CONFIG_SND_SOC_PCM3060_SPI is not set
+# CONFIG_SND_SOC_PCM3168A_I2C is not set
+# CONFIG_SND_SOC_PCM3168A_SPI is not set
+# CONFIG_SND_SOC_PCM5102A is not set
+# CONFIG_SND_SOC_PCM512x_I2C is not set
+# CONFIG_SND_SOC_PCM512x_SPI is not set
+# CONFIG_SND_SOC_PEB2466 is not set
+CONFIG_SND_SOC_RK3228=m
+# CONFIG_SND_SOC_RK3328 is not set
+CONFIG_SND_SOC_RL6231=m
+# CONFIG_SND_SOC_RT5616 is not set
+# CONFIG_SND_SOC_RT5631 is not set
+# CONFIG_SND_SOC_RT5640 is not set
+CONFIG_SND_SOC_RT5645=m
+# CONFIG_SND_SOC_RT5659 is not set
+# CONFIG_SND_SOC_RT9120 is not set
+# CONFIG_SND_SOC_SGTL5000 is not set
+# CONFIG_SND_SOC_SIMPLE_AMPLIFIER is not set
+# CONFIG_SND_SOC_SIMPLE_MUX is not set
+# CONFIG_SND_SOC_SMA1303 is not set
+CONFIG_SND_SOC_SPDIF=m
+# CONFIG_SND_SOC_SRC4XXX_I2C is not set
+# CONFIG_SND_SOC_SSM2305 is not set
+# CONFIG_SND_SOC_SSM2518 is not set
+# CONFIG_SND_SOC_SSM2602_SPI is not set
+# CONFIG_SND_SOC_SSM2602_I2C is not set
+# CONFIG_SND_SOC_SSM3515 is not set
+# CONFIG_SND_SOC_SSM4567 is not set
+# CONFIG_SND_SOC_STA32X is not set
+# CONFIG_SND_SOC_STA350 is not set
+# CONFIG_SND_SOC_STI_SAS is not set
+# CONFIG_SND_SOC_TAS2552 is not set
+# CONFIG_SND_SOC_TAS2562 is not set
+# CONFIG_SND_SOC_TAS2764 is not set
+# CONFIG_SND_SOC_TAS2770 is not set
+# CONFIG_SND_SOC_TAS2780 is not set
+# CONFIG_SND_SOC_TAS2781_I2C is not set
+# CONFIG_SND_SOC_TAS5086 is not set
+# CONFIG_SND_SOC_TAS571X is not set
+# CONFIG_SND_SOC_TAS5720 is not set
+# CONFIG_SND_SOC_TAS5805M is not set
+# CONFIG_SND_SOC_TAS6424 is not set
+# CONFIG_SND_SOC_TDA7419 is not set
+# CONFIG_SND_SOC_TFA9879 is not set
+# CONFIG_SND_SOC_TFA989X is not set
+# CONFIG_SND_SOC_TLV320ADC3XXX is not set
+# CONFIG_SND_SOC_TLV320AIC23_I2C is not set
+# CONFIG_SND_SOC_TLV320AIC23_SPI is not set
+# CONFIG_SND_SOC_TLV320AIC31XX is not set
+# CONFIG_SND_SOC_TLV320AIC32X4_I2C is not set
+# CONFIG_SND_SOC_TLV320AIC32X4_SPI is not set
+# CONFIG_SND_SOC_TLV320AIC3X_I2C is not set
+# CONFIG_SND_SOC_TLV320AIC3X_SPI is not set
+# CONFIG_SND_SOC_TLV320ADCX140 is not set
+CONFIG_SND_SOC_TS3A227E=m
+# CONFIG_SND_SOC_TSCS42XX is not set
+# CONFIG_SND_SOC_TSCS454 is not set
+# CONFIG_SND_SOC_UDA1334 is not set
+# CONFIG_SND_SOC_WM8510 is not set
+# CONFIG_SND_SOC_WM8523 is not set
+# CONFIG_SND_SOC_WM8524 is not set
+# CONFIG_SND_SOC_WM8580 is not set
+# CONFIG_SND_SOC_WM8711 is not set
+# CONFIG_SND_SOC_WM8728 is not set
+# CONFIG_SND_SOC_WM8731_I2C is not set
+# CONFIG_SND_SOC_WM8731_SPI is not set
+# CONFIG_SND_SOC_WM8737 is not set
+# CONFIG_SND_SOC_WM8741 is not set
+# CONFIG_SND_SOC_WM8750 is not set
+# CONFIG_SND_SOC_WM8753 is not set
+# CONFIG_SND_SOC_WM8770 is not set
+# CONFIG_SND_SOC_WM8776 is not set
+# CONFIG_SND_SOC_WM8782 is not set
+# CONFIG_SND_SOC_WM8804_I2C is not set
+# CONFIG_SND_SOC_WM8804_SPI is not set
+# CONFIG_SND_SOC_WM8903 is not set
+# CONFIG_SND_SOC_WM8904 is not set
+# CONFIG_SND_SOC_WM8940 is not set
+# CONFIG_SND_SOC_WM8960 is not set
+# CONFIG_SND_SOC_WM8961 is not set
+# CONFIG_SND_SOC_WM8962 is not set
+# CONFIG_SND_SOC_WM8974 is not set
+# CONFIG_SND_SOC_WM8978 is not set
+# CONFIG_SND_SOC_WM8985 is not set
+# CONFIG_SND_SOC_ZL38060 is not set
+# CONFIG_SND_SOC_MAX9759 is not set
+# CONFIG_SND_SOC_MT6351 is not set
+# CONFIG_SND_SOC_MT6358 is not set
+# CONFIG_SND_SOC_MT6660 is not set
+# CONFIG_SND_SOC_NAU8315 is not set
+# CONFIG_SND_SOC_NAU8540 is not set
+# CONFIG_SND_SOC_NAU8810 is not set
+# CONFIG_SND_SOC_NAU8821 is not set
+# CONFIG_SND_SOC_NAU8822 is not set
+# CONFIG_SND_SOC_NAU8824 is not set
+# CONFIG_SND_SOC_TPA6130A2 is not set
+# CONFIG_SND_SOC_LPASS_WSA_MACRO is not set
+# CONFIG_SND_SOC_LPASS_VA_MACRO is not set
+# CONFIG_SND_SOC_LPASS_RX_MACRO is not set
+# CONFIG_SND_SOC_LPASS_TX_MACRO is not set
+# end of CODEC drivers
+
+CONFIG_SND_SIMPLE_CARD_UTILS=m
+CONFIG_SND_SIMPLE_CARD=m
+CONFIG_SND_AUDIO_GRAPH_CARD=m
+# CONFIG_SND_AUDIO_GRAPH_CARD2 is not set
+# CONFIG_SND_TEST_COMPONENT is not set
+# CONFIG_SND_VIRTIO is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HID_BATTERY_STRENGTH is not set
+# CONFIG_HIDRAW is not set
+# CONFIG_UHID is not set
+CONFIG_HID_GENERIC=y
+
+#
+# Special HID drivers
+#
+CONFIG_HID_A4TECH=m
+CONFIG_HID_ACCUTOUCH=m
+CONFIG_HID_ACRUX=m
+CONFIG_HID_ACRUX_FF=y
+CONFIG_HID_APPLE=m
+CONFIG_HID_APPLEIR=m
+CONFIG_HID_ASUS=m
+CONFIG_HID_AUREAL=m
+CONFIG_HID_BELKIN=m
+CONFIG_HID_BETOP_FF=m
+CONFIG_HID_BIGBEN_FF=m
+CONFIG_HID_CHERRY=m
+CONFIG_HID_CHICONY=m
+CONFIG_HID_CORSAIR=m
+CONFIG_HID_COUGAR=m
+CONFIG_HID_MACALLY=m
+CONFIG_HID_PRODIKEYS=m
+CONFIG_HID_CMEDIA=m
+CONFIG_HID_CREATIVE_SB0540=m
+CONFIG_HID_CYPRESS=m
+CONFIG_HID_DRAGONRISE=m
+CONFIG_DRAGONRISE_FF=y
+CONFIG_HID_EMS_FF=m
+CONFIG_HID_ELAN=m
+CONFIG_HID_ELECOM=m
+CONFIG_HID_ELO=m
+CONFIG_HID_EVISION=m
+CONFIG_HID_EZKEY=m
+CONFIG_HID_GEMBIRD=m
+CONFIG_HID_GFRM=m
+CONFIG_HID_GLORIOUS=m
+CONFIG_HID_HOLTEK=m
+CONFIG_HOLTEK_FF=y
+CONFIG_HID_VIVALDI_COMMON=m
+CONFIG_HID_GOOGLE_STADIA_FF=m
+CONFIG_HID_VIVALDI=m
+CONFIG_HID_GT683R=m
+CONFIG_HID_KEYTOUCH=m
+CONFIG_HID_KYE=m
+CONFIG_HID_UCLOGIC=m
+CONFIG_HID_WALTOP=m
+CONFIG_HID_VIEWSONIC=m
+CONFIG_HID_VRC2=m
+CONFIG_HID_XIAOMI=m
+CONFIG_HID_GYRATION=m
+CONFIG_HID_ICADE=m
+CONFIG_HID_ITE=m
+CONFIG_HID_JABRA=m
+CONFIG_HID_TWINHAN=m
+CONFIG_HID_KENSINGTON=m
+CONFIG_HID_LCPOWER=m
+CONFIG_HID_LED=m
+CONFIG_HID_LENOVO=m
+CONFIG_HID_LETSKETCH=m
+CONFIG_HID_LOGITECH=m
+CONFIG_HID_LOGITECH_HIDPP=m
+CONFIG_LOGITECH_FF=y
+CONFIG_LOGIRUMBLEPAD2_FF=y
+CONFIG_LOGIG940_FF=y
+CONFIG_LOGIWHEELS_FF=y
+CONFIG_HID_MAGICMOUSE=m
+CONFIG_HID_MALTRON=m
+CONFIG_HID_MAYFLASH=m
+CONFIG_HID_MEGAWORLD_FF=m
+CONFIG_HID_REDRAGON=m
+CONFIG_HID_MICROSOFT=m
+CONFIG_HID_MONTEREY=m
+CONFIG_HID_MULTITOUCH=m
+CONFIG_HID_NINTENDO=m
+CONFIG_NINTENDO_FF=y
+CONFIG_HID_NTI=m
+CONFIG_HID_NTRIG=m
+CONFIG_HID_NVIDIA_SHIELD=m
+# CONFIG_NVIDIA_SHIELD_FF is not set
+CONFIG_HID_ORTEK=m
+CONFIG_HID_OUYA=m
+CONFIG_HID_PANTHERLORD=m
+CONFIG_PANTHERLORD_FF=y
+CONFIG_HID_PENMOUNT=m
+CONFIG_HID_PETALYNX=m
+CONFIG_HID_PICOLCD=m
+CONFIG_HID_PICOLCD_FB=y
+CONFIG_HID_PICOLCD_BACKLIGHT=y
+CONFIG_HID_PICOLCD_LEDS=y
+CONFIG_HID_PICOLCD_CIR=y
+CONFIG_HID_PLANTRONICS=m
+CONFIG_HID_PXRC=m
+CONFIG_HID_RAZER=m
+CONFIG_HID_PRIMAX=m
+CONFIG_HID_RETRODE=m
+CONFIG_HID_ROCCAT=m
+CONFIG_HID_SAITEK=m
+CONFIG_HID_SAMSUNG=m
+CONFIG_HID_SEMITEK=m
+CONFIG_HID_SIGMAMICRO=m
+CONFIG_HID_SONY=m
+CONFIG_SONY_FF=y
+CONFIG_HID_SPEEDLINK=m
+CONFIG_HID_STEAM=m
+# CONFIG_STEAM_FF is not set
+CONFIG_HID_STEELSERIES=m
+CONFIG_HID_SUNPLUS=m
+CONFIG_HID_RMI=m
+CONFIG_HID_GREENASIA=m
+CONFIG_GREENASIA_FF=y
+CONFIG_HID_SMARTJOYPLUS=m
+CONFIG_SMARTJOYPLUS_FF=y
+CONFIG_HID_TIVO=m
+CONFIG_HID_TOPSEED=m
+CONFIG_HID_TOPRE=m
+CONFIG_HID_THINGM=m
+CONFIG_HID_THRUSTMASTER=m
+CONFIG_THRUSTMASTER_FF=y
+CONFIG_HID_UDRAW_PS3=m
+CONFIG_HID_U2FZERO=m
+CONFIG_HID_WACOM=m
+CONFIG_HID_WIIMOTE=m
+CONFIG_HID_XINMO=m
+CONFIG_HID_ZEROPLUS=m
+CONFIG_ZEROPLUS_FF=y
+CONFIG_HID_ZYDACRON=m
+CONFIG_HID_SENSOR_HUB=m
+CONFIG_HID_SENSOR_CUSTOM_SENSOR=m
+CONFIG_HID_ALPS=m
+CONFIG_HID_MCP2221=m
+# end of Special HID drivers
+
+#
+# HID-BPF support
+#
+# end of HID-BPF support
+
+#
+# USB HID support
+#
+CONFIG_USB_HID=y
+# CONFIG_HID_PID is not set
+# CONFIG_USB_HIDDEV is not set
+# end of USB HID support
+
+CONFIG_I2C_HID=y
+# CONFIG_I2C_HID_OF is not set
+# CONFIG_I2C_HID_OF_ELAN is not set
+# CONFIG_I2C_HID_OF_GOODIX is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_COMMON=y
+# CONFIG_USB_LED_TRIG is not set
+CONFIG_USB_ULPI_BUS=y
+# CONFIG_USB_CONN_GPIO is not set
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEFAULT_PERSIST=y
+# CONFIG_USB_FEW_INIT_RETRIES is not set
+# CONFIG_USB_DYNAMIC_MINORS is not set
+CONFIG_USB_OTG=y
+# CONFIG_USB_OTG_PRODUCTLIST is not set
+# CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set
+# CONFIG_USB_OTG_FSM is not set
+# CONFIG_USB_LEDS_TRIGGER_USBPORT is not set
+CONFIG_USB_AUTOSUSPEND_DELAY=2
+# CONFIG_USB_MON is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+CONFIG_USB_XHCI_HCD=y
+# CONFIG_USB_XHCI_DBGCAP is not set
+# CONFIG_USB_XHCI_PCI_RENESAS is not set
+CONFIG_USB_XHCI_PLATFORM=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+CONFIG_USB_EHCI_TT_NEWSCHED=y
+# CONFIG_USB_EHCI_FSL is not set
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_MAX3421_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_PLATFORM=y
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HCD_BCMA is not set
+# CONFIG_USB_HCD_SSB is not set
+# CONFIG_USB_HCD_TEST_MODE is not set
+
+#
+# USB Device Class drivers
+#
+CONFIG_USB_ACM=y
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_REALTEK is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_STORAGE_ENE_UB6250 is not set
+CONFIG_USB_UAS=y
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USBIP_CORE is not set
+
+#
+# USB dual-mode controller drivers
+#
+# CONFIG_USB_CDNS_SUPPORT is not set
+# CONFIG_USB_MUSB_HDRC is not set
+# CONFIG_USB_DWC3 is not set
+CONFIG_USB_DWC2=y
+CONFIG_USB_DWC2_HOST=y
+
+#
+# Gadget/Dual-role mode requires USB Gadget support to be enabled
+#
+# CONFIG_USB_DWC2_DEBUG is not set
+# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set
+# CONFIG_USB_CHIPIDEA is not set
+# CONFIG_USB_ISP1760 is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_APPLE_MFI_FASTCHARGE is not set
+# CONFIG_USB_SISUSBVGA is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_EHSET_TEST_FIXTURE is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_YUREX is not set
+# CONFIG_USB_EZUSB_FX2 is not set
+# CONFIG_USB_HUB_USB251XB is not set
+# CONFIG_USB_HSIC_USB3503 is not set
+# CONFIG_USB_HSIC_USB4604 is not set
+# CONFIG_USB_LINK_LAYER_TEST is not set
+# CONFIG_USB_CHAOSKEY is not set
+# CONFIG_USB_ONBOARD_HUB is not set
+# CONFIG_USB_ATM is not set
+
+#
+# USB Physical Layer drivers
+#
+CONFIG_USB_PHY=y
+CONFIG_NOP_USB_XCEIV=y
+# CONFIG_AM335X_PHY_USB is not set
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_USB_ISP1301 is not set
+CONFIG_USB_ULPI=y
+CONFIG_USB_ULPI_VIEWPORT=y
+# end of USB Physical Layer drivers
+
+# CONFIG_USB_GADGET is not set
+# CONFIG_TYPEC is not set
+CONFIG_USB_ROLE_SWITCH=y
+CONFIG_MMC=y
+CONFIG_PWRSEQ_EMMC=y
+# CONFIG_PWRSEQ_SD8787 is not set
+CONFIG_PWRSEQ_SIMPLE=y
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_MINORS=32
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+# CONFIG_MMC_DEBUG is not set
+CONFIG_MMC_ARMMMCI=y
+CONFIG_MMC_STM32_SDMMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_OF_ARASAN=y
+# CONFIG_MMC_SDHCI_OF_AT91 is not set
+# CONFIG_MMC_SDHCI_OF_DWCMSHC is not set
+# CONFIG_MMC_SDHCI_CADENCE is not set
+# CONFIG_MMC_SDHCI_F_SDH30 is not set
+# CONFIG_MMC_SDHCI_MILBEAUT is not set
+CONFIG_MMC_SPI=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_PLTFM=y
+# CONFIG_MMC_DW_BLUEFIELD is not set
+# CONFIG_MMC_DW_EXYNOS is not set
+# CONFIG_MMC_DW_HI3798CV200 is not set
+CONFIG_MMC_DW_K3=y
+CONFIG_MMC_DW_ROCKCHIP=y
+# CONFIG_MMC_VUB300 is not set
+# CONFIG_MMC_USHC is not set
+# CONFIG_MMC_USDHI6ROL0 is not set
+# CONFIG_MMC_REALTEK_USB is not set
+CONFIG_MMC_CQHCI=y
+# CONFIG_MMC_HSQ is not set
+# CONFIG_MMC_MTK is not set
+# CONFIG_MMC_SDHCI_XENON is not set
+# CONFIG_SCSI_UFSHCD is not set
+# CONFIG_MEMSTICK is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_CLASS_FLASH=m
+# CONFIG_LEDS_CLASS_MULTICOLOR is not set
+# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set
+
+#
+# LED drivers
+#
+# CONFIG_LEDS_AN30259A is not set
+# CONFIG_LEDS_AW200XX is not set
+# CONFIG_LEDS_AW2013 is not set
+# CONFIG_LEDS_BCM6328 is not set
+# CONFIG_LEDS_BCM6358 is not set
+# CONFIG_LEDS_CR0014114 is not set
+# CONFIG_LEDS_EL15203000 is not set
+# CONFIG_LEDS_LM3530 is not set
+# CONFIG_LEDS_LM3532 is not set
+# CONFIG_LEDS_LM3642 is not set
+# CONFIG_LEDS_LM3692X is not set
+# CONFIG_LEDS_PCA9532 is not set
+CONFIG_LEDS_GPIO=y
+# CONFIG_LEDS_LP3944 is not set
+# CONFIG_LEDS_LP3952 is not set
+# CONFIG_LEDS_LP50XX is not set
+# CONFIG_LEDS_LP55XX_COMMON is not set
+# CONFIG_LEDS_LP8860 is not set
+# CONFIG_LEDS_PCA955X is not set
+# CONFIG_LEDS_PCA963X is not set
+# CONFIG_LEDS_PCA995X is not set
+# CONFIG_LEDS_DAC124S085 is not set
+CONFIG_LEDS_PWM=y
+# CONFIG_LEDS_REGULATOR is not set
+# CONFIG_LEDS_BD2606MVV is not set
+# CONFIG_LEDS_BD2802 is not set
+# CONFIG_LEDS_LT3593 is not set
+# CONFIG_LEDS_TCA6507 is not set
+# CONFIG_LEDS_TLC591XX is not set
+# CONFIG_LEDS_LM355x is not set
+# CONFIG_LEDS_IS31FL319X is not set
+# CONFIG_LEDS_IS31FL32XX is not set
+
+#
+# LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM)
+#
+# CONFIG_LEDS_BLINKM is not set
+CONFIG_LEDS_SYSCON=y
+# CONFIG_LEDS_PM8058 is not set
+# CONFIG_LEDS_MLXREG is not set
+# CONFIG_LEDS_USER is not set
+# CONFIG_LEDS_SPI_BYTE is not set
+# CONFIG_LEDS_LM3697 is not set
+
+#
+# Flash and Torch LED drivers
+#
+# CONFIG_LEDS_AAT1290 is not set
+# CONFIG_LEDS_AS3645A is not set
+# CONFIG_LEDS_KTD2692 is not set
+# CONFIG_LEDS_LM3601X is not set
+# CONFIG_LEDS_RT4505 is not set
+# CONFIG_LEDS_RT8515 is not set
+# CONFIG_LEDS_SGM3140 is not set
+
+#
+# RGB LED drivers
+#
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_ONESHOT=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
+CONFIG_LEDS_TRIGGER_CPU=y
+CONFIG_LEDS_TRIGGER_ACTIVITY=y
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
+
+#
+# iptables trigger is under Netfilter config (LED target)
+#
+# CONFIG_LEDS_TRIGGER_TRANSIENT is not set
+# CONFIG_LEDS_TRIGGER_CAMERA is not set
+CONFIG_LEDS_TRIGGER_PANIC=y
+# CONFIG_LEDS_TRIGGER_NETDEV is not set
+# CONFIG_LEDS_TRIGGER_PATTERN is not set
+# CONFIG_LEDS_TRIGGER_AUDIO is not set
+# CONFIG_LEDS_TRIGGER_TTY is not set
+
+#
+# Simple LED drivers
+#
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_INFINIBAND is not set
+CONFIG_EDAC_ATOMIC_SCRUB=y
+CONFIG_EDAC_SUPPORT=y
+CONFIG_EDAC=y
+CONFIG_EDAC_LEGACY_SYSFS=y
+# CONFIG_EDAC_DEBUG is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+CONFIG_RTC_SYSTOHC=y
+CONFIG_RTC_SYSTOHC_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+CONFIG_RTC_NVMEM=y
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_ABB5ZES3 is not set
+# CONFIG_RTC_DRV_ABEOZ9 is not set
+# CONFIG_RTC_DRV_ABX80X is not set
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_HYM8563 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+CONFIG_RTC_DRV_MAX77686=y
+# CONFIG_RTC_DRV_NCT3018Y is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_ISL12022 is not set
+# CONFIG_RTC_DRV_ISL12026 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8523 is not set
+# CONFIG_RTC_DRV_PCF85063 is not set
+# CONFIG_RTC_DRV_PCF85363 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_BQ32K is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8010 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
+# CONFIG_RTC_DRV_EM3027 is not set
+# CONFIG_RTC_DRV_RV3028 is not set
+# CONFIG_RTC_DRV_RV3032 is not set
+# CONFIG_RTC_DRV_RV8803 is not set
+CONFIG_RTC_DRV_S5M=y
+# CONFIG_RTC_DRV_SD3078 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_M41T93 is not set
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1302 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1343 is not set
+# CONFIG_RTC_DRV_DS1347 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
+# CONFIG_RTC_DRV_MAX6916 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RX4581 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_PCF2123 is not set
+# CONFIG_RTC_DRV_MCP795 is not set
+CONFIG_RTC_I2C_AND_SPI=y
+
+#
+# SPI and I2C RTC drivers
+#
+CONFIG_RTC_DRV_DS3232=y
+CONFIG_RTC_DRV_DS3232_HWMON=y
+# CONFIG_RTC_DRV_PCF2127 is not set
+# CONFIG_RTC_DRV_RV3029C2 is not set
+# CONFIG_RTC_DRV_RX6110 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1685_FAMILY is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_DS2404 is not set
+CONFIG_RTC_DRV_DA9063=m
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_MSM6242 is not set
+# CONFIG_RTC_DRV_RP5C01 is not set
+# CONFIG_RTC_DRV_OPTEE is not set
+# CONFIG_RTC_DRV_ZYNQMP is not set
+
+#
+# on-CPU RTC drivers
+#
+# CONFIG_RTC_DRV_PL030 is not set
+CONFIG_RTC_DRV_PL031=y
+# CONFIG_RTC_DRV_CADENCE is not set
+# CONFIG_RTC_DRV_FTRTC010 is not set
+# CONFIG_RTC_DRV_PM8XXX is not set
+# CONFIG_RTC_DRV_R7301 is not set
+
+#
+# HID Sensor RTC drivers
+#
+# CONFIG_RTC_DRV_GOLDFISH is not set
+CONFIG_DMADEVICES=y
+# CONFIG_DMADEVICES_DEBUG is not set
+
+#
+# DMA Devices
+#
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_OF=y
+# CONFIG_ALTERA_MSGDMA is not set
+# CONFIG_AMBA_PL08X is not set
+# CONFIG_DW_AXI_DMAC is not set
+# CONFIG_FSL_EDMA is not set
+# CONFIG_FSL_QDMA is not set
+# CONFIG_INTEL_IDMA64 is not set
+# CONFIG_NBPFAXI_DMA is not set
+CONFIG_PL330_DMA=y
+# CONFIG_XILINX_DMA is not set
+# CONFIG_XILINX_XDMA is not set
+# CONFIG_XILINX_ZYNQMP_DPDMA is not set
+# CONFIG_QCOM_HIDMA_MGMT is not set
+# CONFIG_QCOM_HIDMA is not set
+# CONFIG_DW_DMAC is not set
+# CONFIG_SF_PDMA is not set
+
+#
+# DMA Clients
+#
+# CONFIG_ASYNC_TX_DMA is not set
+# CONFIG_DMATEST is not set
+
+#
+# DMABUF options
+#
+CONFIG_SYNC_FILE=y
+# CONFIG_SW_SYNC is not set
+# CONFIG_UDMABUF is not set
+# CONFIG_DMABUF_MOVE_NOTIFY is not set
+# CONFIG_DMABUF_DEBUG is not set
+# CONFIG_DMABUF_SELFTESTS is not set
+CONFIG_DMABUF_HEAPS=y
+# CONFIG_DMABUF_SYSFS_STATS is not set
+CONFIG_DMABUF_HEAPS_SYSTEM=y
+CONFIG_DMABUF_HEAPS_CMA=y
+# end of DMABUF options
+
+# CONFIG_UIO is not set
+CONFIG_VFIO=y
+CONFIG_VFIO_GROUP=y
+CONFIG_VFIO_CONTAINER=y
+CONFIG_VFIO_IOMMU_TYPE1=y
+# CONFIG_VFIO_NOIOMMU is not set
+
+#
+# VFIO support for platform devices
+#
+# CONFIG_VFIO_PLATFORM is not set
+# CONFIG_VFIO_AMBA is not set
+# end of VFIO support for platform devices
+
+# CONFIG_VIRT_DRIVERS is not set
+CONFIG_VIRTIO_ANCHOR=y
+CONFIG_VIRTIO=y
+CONFIG_VIRTIO_MENU=y
+CONFIG_VIRTIO_BALLOON=y
+# CONFIG_VIRTIO_INPUT is not set
+CONFIG_VIRTIO_MMIO=y
+# CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES is not set
+# CONFIG_VDPA is not set
+# CONFIG_VHOST_MENU is not set
+
+#
+# Microsoft Hyper-V guest support
+#
+# end of Microsoft Hyper-V guest support
+
+# CONFIG_GREYBUS is not set
+# CONFIG_COMEDI is not set
+CONFIG_STAGING=y
+# CONFIG_PRISM2_USB is not set
+# CONFIG_RTLLIB is not set
+CONFIG_RTL8723BS=m
+CONFIG_R8712U=m
+# CONFIG_VT6656 is not set
+CONFIG_STAGING_MEDIA=y
+# CONFIG_VIDEO_MAX96712 is not set
+CONFIG_VIDEO_ROCKCHIP_VDEC=y
+# CONFIG_STAGING_MEDIA_DEPRECATED is not set
+# CONFIG_STAGING_BOARD is not set
+# CONFIG_LTE_GDM724X is not set
+# CONFIG_FB_TFT is not set
+# CONFIG_KS7010 is not set
+# CONFIG_PI433 is not set
+# CONFIG_XIL_AXIS_FIFO is not set
+# CONFIG_FIELDBUS_DEV is not set
+# CONFIG_GOLDFISH is not set
+# CONFIG_CHROME_PLATFORMS is not set
+# CONFIG_MELLANOX_PLATFORM is not set
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_CLK_PREPARE=y
+CONFIG_COMMON_CLK=y
+
+#
+# Clock driver for ARM Reference designs
+#
+# CONFIG_CLK_ICST is not set
+# CONFIG_CLK_SP810 is not set
+# end of Clock driver for ARM Reference designs
+
+# CONFIG_LMK04832 is not set
+# CONFIG_COMMON_CLK_MAX77686 is not set
+# CONFIG_COMMON_CLK_MAX9485 is not set
+# CONFIG_COMMON_CLK_SCMI is not set
+CONFIG_COMMON_CLK_SCPI=m
+# CONFIG_COMMON_CLK_SI5341 is not set
+# CONFIG_COMMON_CLK_SI5351 is not set
+# CONFIG_COMMON_CLK_SI514 is not set
+# CONFIG_COMMON_CLK_SI544 is not set
+# CONFIG_COMMON_CLK_SI570 is not set
+# CONFIG_COMMON_CLK_CDCE706 is not set
+# CONFIG_COMMON_CLK_CDCE925 is not set
+CONFIG_COMMON_CLK_CS2000_CP=y
+CONFIG_COMMON_CLK_S2MPS11=y
+# CONFIG_COMMON_CLK_AXI_CLKGEN is not set
+CONFIG_COMMON_CLK_PWM=y
+# CONFIG_COMMON_CLK_RS9_PCIE is not set
+# CONFIG_COMMON_CLK_SI521XX is not set
+# CONFIG_COMMON_CLK_VC3 is not set
+# CONFIG_COMMON_CLK_VC5 is not set
+# CONFIG_COMMON_CLK_VC7 is not set
+# CONFIG_COMMON_CLK_FIXED_MMIO is not set
+CONFIG_COMMON_CLK_ROCKCHIP=y
+CONFIG_CLK_RV110X=y
+# CONFIG_CLK_RV1126 is not set
+CONFIG_CLK_RK3036=y
+CONFIG_CLK_RK312X=y
+CONFIG_CLK_RK3188=y
+CONFIG_CLK_RK322X=y
+CONFIG_CLK_RK3288=y
+# CONFIG_XILINX_VCU is not set
+# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set
+CONFIG_HWSPINLOCK=y
+
+#
+# Clock Source drivers
+#
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_CLKSRC_MMIO=y
+CONFIG_DW_APB_TIMER=y
+CONFIG_DW_APB_TIMER_OF=y
+CONFIG_ROCKCHIP_TIMER=y
+CONFIG_ARM_ARCH_TIMER=y
+CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
+CONFIG_ARM_GLOBAL_TIMER=y
+CONFIG_ARM_GT_INITIAL_PRESCALER_VAL=1
+CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK=y
+# CONFIG_MICROCHIP_PIT64B is not set
+# end of Clock Source drivers
+
+CONFIG_MAILBOX=y
+CONFIG_ARM_MHU=y
+# CONFIG_ARM_MHU_V2 is not set
+CONFIG_PLATFORM_MHU=y
+# CONFIG_PL320_MBOX is not set
+CONFIG_ROCKCHIP_MBOX=y
+# CONFIG_ALTERA_MBOX is not set
+# CONFIG_MAILBOX_TEST is not set
+CONFIG_IOMMU_API=y
+CONFIG_IOMMU_SUPPORT=y
+
+#
+# Generic IOMMU Pagetable Support
+#
+CONFIG_IOMMU_IO_PGTABLE=y
+CONFIG_IOMMU_IO_PGTABLE_LPAE=y
+# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set
+# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
+# end of Generic IOMMU Pagetable Support
+
+# CONFIG_IOMMU_DEBUGFS is not set
+# CONFIG_IOMMU_DEFAULT_DMA_STRICT is not set
+# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set
+CONFIG_IOMMU_DEFAULT_PASSTHROUGH=y
+CONFIG_OF_IOMMU=y
+# CONFIG_IOMMUFD is not set
+CONFIG_ROCKCHIP_IOMMU=y
+# CONFIG_ARM_SMMU is not set
+
+#
+# Remoteproc drivers
+#
+# CONFIG_REMOTEPROC is not set
+# end of Remoteproc drivers
+
+#
+# Rpmsg drivers
+#
+# CONFIG_RPMSG_QCOM_GLINK_RPM is not set
+# CONFIG_RPMSG_VIRTIO is not set
+# end of Rpmsg drivers
+
+# CONFIG_SOUNDWIRE is not set
+
+#
+# SOC (System On Chip) specific Drivers
+#
+
+#
+# Amlogic SoC drivers
+#
+# end of Amlogic SoC drivers
+
+#
+# Broadcom SoC drivers
+#
+# CONFIG_SOC_BRCMSTB is not set
+# end of Broadcom SoC drivers
+
+#
+# NXP/Freescale QorIQ SoC drivers
+#
+# CONFIG_QUICC_ENGINE is not set
+# CONFIG_FSL_RCPM is not set
+# end of NXP/Freescale QorIQ SoC drivers
+
+#
+# fujitsu SoC drivers
+#
+# end of fujitsu SoC drivers
+
+#
+# i.MX SoC drivers
+#
+# end of i.MX SoC drivers
+
+#
+# Enable LiteX SoC Builder specific drivers
+#
+# CONFIG_LITEX_SOC_CONTROLLER is not set
+# end of Enable LiteX SoC Builder specific drivers
+
+# CONFIG_WPCM450_SOC is not set
+
+#
+# Qualcomm SoC drivers
+#
+CONFIG_QCOM_QMI_HELPERS=m
+# end of Qualcomm SoC drivers
+
+CONFIG_ROCKCHIP_GRF=y
+CONFIG_ROCKCHIP_IODOMAIN=y
+CONFIG_ROCKCHIP_PM_DOMAINS=y
+# CONFIG_SOC_TI is not set
+
+#
+# Xilinx SoC drivers
+#
+# end of Xilinx SoC drivers
+# end of SOC (System On Chip) specific Drivers
+
+CONFIG_PM_DEVFREQ=y
+
+#
+# DEVFREQ Governors
+#
+CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
+CONFIG_DEVFREQ_GOV_PERFORMANCE=y
+CONFIG_DEVFREQ_GOV_POWERSAVE=y
+CONFIG_DEVFREQ_GOV_USERSPACE=y
+CONFIG_DEVFREQ_GOV_PASSIVE=y
+
+#
+# DEVFREQ Drivers
+#
+CONFIG_ARM_RK3228_DMC_DEVFREQ=y
+# CONFIG_ARM_RK3399_DMC_DEVFREQ is not set
+CONFIG_PM_DEVFREQ_EVENT=y
+CONFIG_DEVFREQ_EVENT_ROCKCHIP_DFI=y
+CONFIG_EXTCON=y
+
+#
+# Extcon Device Drivers
+#
+# CONFIG_EXTCON_FSA9480 is not set
+# CONFIG_EXTCON_GPIO is not set
+# CONFIG_EXTCON_MAX3355 is not set
+# CONFIG_EXTCON_PTN5150 is not set
+# CONFIG_EXTCON_RT8973A is not set
+# CONFIG_EXTCON_SM5502 is not set
+CONFIG_EXTCON_USB_GPIO=y
+# CONFIG_MEMORY is not set
+# CONFIG_IIO is not set
+CONFIG_PWM=y
+CONFIG_PWM_SYSFS=y
+# CONFIG_PWM_DEBUG is not set
+# CONFIG_PWM_ATMEL_TCB is not set
+# CONFIG_PWM_CLK is not set
+# CONFIG_PWM_FSL_FTM is not set
+# CONFIG_PWM_PCA9685 is not set
+CONFIG_PWM_ROCKCHIP=y
+# CONFIG_PWM_XILINX is not set
+
+#
+# IRQ chip support
+#
+CONFIG_IRQCHIP=y
+CONFIG_ARM_GIC=y
+CONFIG_ARM_GIC_MAX_NR=1
+# CONFIG_AL_FIC is not set
+# CONFIG_XILINX_INTC is not set
+# end of IRQ chip support
+
+# CONFIG_IPACK_BUS is not set
+CONFIG_ARCH_HAS_RESET_CONTROLLER=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RESET_SCMI=y
+# CONFIG_RESET_TI_SYSCON is not set
+# CONFIG_RESET_TI_TPS380X is not set
+
+#
+# PHY Subsystem
+#
+CONFIG_GENERIC_PHY=y
+# CONFIG_PHY_CAN_TRANSCEIVER is not set
+
+#
+# PHY drivers for Broadcom platforms
+#
+# CONFIG_BCM_KONA_USB2_PHY is not set
+# end of PHY drivers for Broadcom platforms
+
+# CONFIG_PHY_CADENCE_TORRENT is not set
+# CONFIG_PHY_CADENCE_DPHY is not set
+# CONFIG_PHY_CADENCE_DPHY_RX is not set
+# CONFIG_PHY_CADENCE_SIERRA is not set
+# CONFIG_PHY_CADENCE_SALVO is not set
+# CONFIG_PHY_PXA_28NM_HSIC is not set
+# CONFIG_PHY_PXA_28NM_USB2 is not set
+# CONFIG_PHY_LAN966X_SERDES is not set
+# CONFIG_PHY_MAPPHONE_MDM6600 is not set
+# CONFIG_PHY_OCELOT_SERDES is not set
+# CONFIG_PHY_QCOM_USB_HS is not set
+# CONFIG_PHY_QCOM_USB_HSIC is not set
+# CONFIG_PHY_ROCKCHIP_DP is not set
+# CONFIG_PHY_ROCKCHIP_DPHY_RX0 is not set
+CONFIG_PHY_ROCKCHIP_EMMC=y
+CONFIG_PHY_ROCKCHIP_INNO_HDMI=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+# CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY is not set
+# CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY is not set
+# CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY is not set
+# CONFIG_PHY_ROCKCHIP_PCIE is not set
+# CONFIG_PHY_ROCKCHIP_SNPS_PCIE3 is not set
+# CONFIG_PHY_ROCKCHIP_TYPEC is not set
+CONFIG_PHY_ROCKCHIP_USB=y
+# CONFIG_PHY_SAMSUNG_USB2 is not set
+# CONFIG_PHY_TUSB1210 is not set
+# end of PHY Subsystem
+
+# CONFIG_POWERCAP is not set
+# CONFIG_MCB is not set
+
+#
+# Performance monitor support
+#
+# CONFIG_ARM_CCI_PMU is not set
+# CONFIG_ARM_CCN is not set
+CONFIG_ARM_PMU=y
+# CONFIG_ARM_PMUV3 is not set
+# end of Performance monitor support
+
+CONFIG_RAS=y
+
+#
+# Android
+#
+# CONFIG_ANDROID_BINDER_IPC is not set
+# end of Android
+
+# CONFIG_DAX is not set
+CONFIG_NVMEM=y
+CONFIG_NVMEM_SYSFS=y
+
+#
+# Layout Types
+#
+# CONFIG_NVMEM_LAYOUT_SL28_VPD is not set
+# CONFIG_NVMEM_LAYOUT_ONIE_TLV is not set
+# end of Layout Types
+
+# CONFIG_NVMEM_RMEM is not set
+CONFIG_NVMEM_ROCKCHIP_EFUSE=y
+# CONFIG_NVMEM_ROCKCHIP_OTP is not set
+# CONFIG_NVMEM_SPMI_SDAM is not set
+
+#
+# HW tracing support
+#
+# CONFIG_STM is not set
+# CONFIG_INTEL_TH is not set
+# end of HW tracing support
+
+# CONFIG_FPGA is not set
+# CONFIG_FSI is not set
+CONFIG_TEE=y
+CONFIG_OPTEE=y
+CONFIG_MULTIPLEXER=y
+
+#
+# Multiplexer drivers
+#
+# CONFIG_MUX_ADG792A is not set
+# CONFIG_MUX_ADGS1408 is not set
+# CONFIG_MUX_GPIO is not set
+# CONFIG_MUX_MMIO is not set
+# end of Multiplexer drivers
+
+CONFIG_PM_OPP=y
+# CONFIG_SIOX is not set
+# CONFIG_SLIMBUS is not set
+# CONFIG_INTERCONNECT is not set
+# CONFIG_COUNTER is not set
+# CONFIG_MOST is not set
+# CONFIG_PECI is not set
+# CONFIG_HTE is not set
+# end of Device Drivers
+
+#
+# File systems
+#
+CONFIG_DCACHE_WORD_ACCESS=y
+CONFIG_VALIDATE_FS_PARSER=y
+CONFIG_FS_IOMAP=y
+CONFIG_BUFFER_HEAD=y
+CONFIG_LEGACY_DIRECT_IO=y
+# CONFIG_EXT2_FS is not set
+# CONFIG_EXT3_FS is not set
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_USE_FOR_EXT2=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_EXT4_FS_SECURITY=y
+# CONFIG_EXT4_DEBUG is not set
+CONFIG_JBD2=y
+# CONFIG_JBD2_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+CONFIG_JFS_FS=m
+CONFIG_JFS_POSIX_ACL=y
+CONFIG_JFS_SECURITY=y
+# CONFIG_JFS_DEBUG is not set
+# CONFIG_JFS_STATISTICS is not set
+CONFIG_XFS_FS=m
+CONFIG_XFS_SUPPORT_V4=y
+CONFIG_XFS_SUPPORT_ASCII_CI=y
+CONFIG_XFS_QUOTA=y
+CONFIG_XFS_POSIX_ACL=y
+CONFIG_XFS_RT=y
+CONFIG_XFS_DRAIN_INTENTS=y
+CONFIG_XFS_ONLINE_SCRUB=y
+CONFIG_XFS_ONLINE_SCRUB_STATS=y
+CONFIG_XFS_ONLINE_REPAIR=y
+CONFIG_XFS_DEBUG=y
+CONFIG_XFS_ASSERT_FATAL=y
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+CONFIG_BTRFS_FS=m
+CONFIG_BTRFS_FS_POSIX_ACL=y
+# CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set
+# CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set
+# CONFIG_BTRFS_DEBUG is not set
+# CONFIG_BTRFS_ASSERT is not set
+# CONFIG_BTRFS_FS_REF_VERIFY is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_F2FS_FS=m
+CONFIG_F2FS_STAT_FS=y
+CONFIG_F2FS_FS_XATTR=y
+CONFIG_F2FS_FS_POSIX_ACL=y
+CONFIG_F2FS_FS_SECURITY=y
+CONFIG_F2FS_CHECK_FS=y
+CONFIG_F2FS_FAULT_INJECTION=y
+CONFIG_F2FS_FS_COMPRESSION=y
+CONFIG_F2FS_FS_LZO=y
+CONFIG_F2FS_FS_LZORLE=y
+CONFIG_F2FS_FS_LZ4=y
+CONFIG_F2FS_FS_LZ4HC=y
+CONFIG_F2FS_FS_ZSTD=y
+CONFIG_F2FS_IOSTAT=y
+# CONFIG_F2FS_UNFAIR_RWSEM is not set
+CONFIG_FS_POSIX_ACL=y
+CONFIG_EXPORTFS=y
+# CONFIG_EXPORTFS_BLOCK_OPS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FS_ENCRYPTION=y
+CONFIG_FS_ENCRYPTION_ALGS=y
+# CONFIG_FS_VERITY is not set
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY_USER=y
+CONFIG_FANOTIFY=y
+CONFIG_QUOTA=y
+# CONFIG_QUOTA_NETLINK_INTERFACE is not set
+# CONFIG_QUOTA_DEBUG is not set
+# CONFIG_QFMT_V1 is not set
+# CONFIG_QFMT_V2 is not set
+CONFIG_QUOTACTL=y
+CONFIG_AUTOFS_FS=y
+CONFIG_FUSE_FS=m
+CONFIG_CUSE=m
+# CONFIG_VIRTIO_FS is not set
+CONFIG_OVERLAY_FS=m
+# CONFIG_OVERLAY_FS_REDIRECT_DIR is not set
+CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y
+# CONFIG_OVERLAY_FS_INDEX is not set
+# CONFIG_OVERLAY_FS_METACOPY is not set
+# CONFIG_OVERLAY_FS_DEBUG is not set
+
+#
+# Caches
+#
+CONFIG_NETFS_SUPPORT=m
+CONFIG_NETFS_STATS=y
+# CONFIG_FSCACHE is not set
+# end of Caches
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=m
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=m
+# end of CD-ROM/DVD Filesystems
+
+#
+# DOS/FAT/EXFAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+# CONFIG_MSDOS_FS is not set
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+CONFIG_FAT_DEFAULT_UTF8=y
+CONFIG_EXFAT_FS=m
+CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8"
+CONFIG_NTFS_FS=m
+# CONFIG_NTFS_DEBUG is not set
+CONFIG_NTFS_RW=y
+CONFIG_NTFS3_FS=m
+CONFIG_NTFS3_LZX_XPRESS=y
+CONFIG_NTFS3_FS_POSIX_ACL=y
+# end of DOS/FAT/EXFAT/NT Filesystems
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+# CONFIG_PROC_CHILDREN is not set
+CONFIG_KERNFS=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_TMPFS_XATTR=y
+# CONFIG_TMPFS_QUOTA is not set
+CONFIG_CONFIGFS_FS=y
+# end of Pseudo filesystems
+
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ORANGEFS_FS is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+CONFIG_ECRYPT_FS=m
+CONFIG_ECRYPT_FS_MESSAGING=y
+CONFIG_HFS_FS=m
+CONFIG_HFSPLUS_FS=m
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_CRAMFS is not set
+CONFIG_SQUASHFS=y
+CONFIG_SQUASHFS_FILE_CACHE=y
+# CONFIG_SQUASHFS_FILE_DIRECT is not set
+CONFIG_SQUASHFS_DECOMP_SINGLE=y
+# CONFIG_SQUASHFS_CHOICE_DECOMP_BY_MOUNT is not set
+CONFIG_SQUASHFS_COMPILE_DECOMP_SINGLE=y
+# CONFIG_SQUASHFS_COMPILE_DECOMP_MULTI is not set
+# CONFIG_SQUASHFS_COMPILE_DECOMP_MULTI_PERCPU is not set
+# CONFIG_SQUASHFS_XATTR is not set
+CONFIG_SQUASHFS_ZLIB=y
+CONFIG_SQUASHFS_LZ4=y
+CONFIG_SQUASHFS_LZO=y
+CONFIG_SQUASHFS_XZ=y
+CONFIG_SQUASHFS_ZSTD=y
+# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set
+# CONFIG_SQUASHFS_EMBEDDED is not set
+CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX6FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_PSTORE=y
+CONFIG_PSTORE_DEFAULT_KMSG_BYTES=10240
+CONFIG_PSTORE_COMPRESS=y
+CONFIG_PSTORE_CONSOLE=y
+CONFIG_PSTORE_PMSG=y
+CONFIG_PSTORE_RAM=y
+CONFIG_PSTORE_ZONE=y
+CONFIG_PSTORE_BLK=y
+CONFIG_PSTORE_BLK_BLKDEV=""
+CONFIG_PSTORE_BLK_KMSG_SIZE=64
+CONFIG_PSTORE_BLK_MAX_REASON=2
+CONFIG_PSTORE_BLK_PMSG_SIZE=64
+CONFIG_PSTORE_BLK_CONSOLE_SIZE=64
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_EROFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=m
+CONFIG_NFS_V2=m
+CONFIG_NFS_V3=m
+# CONFIG_NFS_V3_ACL is not set
+CONFIG_NFS_V4=m
+# CONFIG_NFS_SWAP is not set
+CONFIG_NFS_V4_1=y
+CONFIG_NFS_V4_2=y
+CONFIG_PNFS_FILE_LAYOUT=m
+CONFIG_PNFS_FLEXFILE_LAYOUT=m
+CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org"
+# CONFIG_NFS_V4_1_MIGRATION is not set
+# CONFIG_NFS_USE_LEGACY_DNS is not set
+CONFIG_NFS_USE_KERNEL_DNS=y
+CONFIG_NFS_DISABLE_UDP_SUPPORT=y
+# CONFIG_NFS_V4_2_READ_PLUS is not set
+# CONFIG_NFSD is not set
+CONFIG_GRACE_PERIOD=m
+CONFIG_LOCKD=m
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_NFS_V4_2_SSC_HELPER=y
+CONFIG_SUNRPC=m
+CONFIG_SUNRPC_GSS=m
+CONFIG_SUNRPC_BACKCHANNEL=y
+CONFIG_RPCSEC_GSS_KRB5=m
+# CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_AES_SHA1 is not set
+# CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_CAMELLIA is not set
+# CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_AES_SHA2 is not set
+# CONFIG_SUNRPC_DEBUG is not set
+# CONFIG_CEPH_FS is not set
+CONFIG_CIFS=m
+CONFIG_CIFS_STATS2=y
+CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y
+CONFIG_CIFS_UPCALL=y
+CONFIG_CIFS_XATTR=y
+CONFIG_CIFS_POSIX=y
+CONFIG_CIFS_DEBUG=y
+# CONFIG_CIFS_DEBUG2 is not set
+# CONFIG_CIFS_DEBUG_DUMP_KEYS is not set
+# CONFIG_CIFS_DFS_UPCALL is not set
+# CONFIG_CIFS_SWN_UPCALL is not set
+# CONFIG_SMB_SERVER is not set
+CONFIG_SMBFS=m
+CONFIG_CODA_FS=m
+CONFIG_AFS_FS=m
+# CONFIG_AFS_DEBUG is not set
+# CONFIG_AFS_DEBUG_CURSOR is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="utf8"
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_737=m
+CONFIG_NLS_CODEPAGE_775=m
+CONFIG_NLS_CODEPAGE_850=m
+CONFIG_NLS_CODEPAGE_852=m
+CONFIG_NLS_CODEPAGE_855=m
+CONFIG_NLS_CODEPAGE_857=m
+CONFIG_NLS_CODEPAGE_860=m
+CONFIG_NLS_CODEPAGE_861=m
+CONFIG_NLS_CODEPAGE_862=m
+CONFIG_NLS_CODEPAGE_863=m
+CONFIG_NLS_CODEPAGE_864=m
+CONFIG_NLS_CODEPAGE_865=m
+CONFIG_NLS_CODEPAGE_866=m
+CONFIG_NLS_CODEPAGE_869=m
+CONFIG_NLS_CODEPAGE_936=m
+CONFIG_NLS_CODEPAGE_950=m
+CONFIG_NLS_CODEPAGE_932=m
+CONFIG_NLS_CODEPAGE_949=m
+CONFIG_NLS_CODEPAGE_874=m
+CONFIG_NLS_ISO8859_8=m
+CONFIG_NLS_CODEPAGE_1250=m
+CONFIG_NLS_CODEPAGE_1251=m
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_2=m
+CONFIG_NLS_ISO8859_3=m
+CONFIG_NLS_ISO8859_4=m
+CONFIG_NLS_ISO8859_5=m
+CONFIG_NLS_ISO8859_6=m
+CONFIG_NLS_ISO8859_7=m
+CONFIG_NLS_ISO8859_9=m
+CONFIG_NLS_ISO8859_13=m
+CONFIG_NLS_ISO8859_14=m
+CONFIG_NLS_ISO8859_15=m
+CONFIG_NLS_KOI8_R=m
+CONFIG_NLS_KOI8_U=m
+# CONFIG_NLS_MAC_ROMAN is not set
+# CONFIG_NLS_MAC_CELTIC is not set
+# CONFIG_NLS_MAC_CENTEURO is not set
+# CONFIG_NLS_MAC_CROATIAN is not set
+# CONFIG_NLS_MAC_CYRILLIC is not set
+# CONFIG_NLS_MAC_GAELIC is not set
+# CONFIG_NLS_MAC_GREEK is not set
+# CONFIG_NLS_MAC_ICELAND is not set
+# CONFIG_NLS_MAC_INUIT is not set
+# CONFIG_NLS_MAC_ROMANIAN is not set
+# CONFIG_NLS_MAC_TURKISH is not set
+CONFIG_NLS_UTF8=y
+CONFIG_NLS_UCS2_UTILS=m
+# CONFIG_DLM is not set
+# CONFIG_UNICODE is not set
+CONFIG_IO_WQ=y
+# end of File systems
+
+#
+# Security options
+#
+CONFIG_KEYS=y
+# CONFIG_KEYS_REQUEST_CACHE is not set
+# CONFIG_PERSISTENT_KEYRINGS is not set
+# CONFIG_TRUSTED_KEYS is not set
+# CONFIG_ENCRYPTED_KEYS is not set
+CONFIG_KEY_DH_OPERATIONS=y
+# CONFIG_SECURITY_DMESG_RESTRICT is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_HARDENED_USERCOPY is not set
+# CONFIG_FORTIFY_SOURCE is not set
+# CONFIG_STATIC_USERMODEHELPER is not set
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_LSM="yama,loadpin,safesetid,integrity"
+
+#
+# Kernel hardening options
+#
+
+#
+# Memory initialization
+#
+CONFIG_INIT_STACK_NONE=y
+# CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set
+# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set
+CONFIG_CC_HAS_ZERO_CALL_USED_REGS=y
+# CONFIG_ZERO_CALL_USED_REGS is not set
+# end of Memory initialization
+
+#
+# Hardening of kernel data structures
+#
+# CONFIG_LIST_HARDENED is not set
+# CONFIG_BUG_ON_DATA_CORRUPTION is not set
+# end of Hardening of kernel data structures
+
+CONFIG_RANDSTRUCT_NONE=y
+# end of Kernel hardening options
+# end of Security options
+
+CONFIG_XOR_BLOCKS=m
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_SIG=y
+CONFIG_CRYPTO_SIG2=y
+CONFIG_CRYPTO_SKCIPHER=y
+CONFIG_CRYPTO_SKCIPHER2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_RNG_DEFAULT=y
+CONFIG_CRYPTO_AKCIPHER2=y
+CONFIG_CRYPTO_AKCIPHER=y
+CONFIG_CRYPTO_KPP2=y
+CONFIG_CRYPTO_KPP=y
+CONFIG_CRYPTO_ACOMP2=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+CONFIG_CRYPTO_USER=y
+CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
+CONFIG_CRYPTO_NULL=y
+CONFIG_CRYPTO_NULL2=y
+CONFIG_CRYPTO_PCRYPT=y
+CONFIG_CRYPTO_CRYPTD=y
+CONFIG_CRYPTO_AUTHENC=y
+# CONFIG_CRYPTO_TEST is not set
+CONFIG_CRYPTO_SIMD=m
+CONFIG_CRYPTO_ENGINE=y
+# end of Crypto core or helper
+
+#
+# Public-key cryptography
+#
+CONFIG_CRYPTO_RSA=y
+CONFIG_CRYPTO_DH=y
+# CONFIG_CRYPTO_DH_RFC7919_GROUPS is not set
+CONFIG_CRYPTO_ECC=y
+CONFIG_CRYPTO_ECDH=y
+CONFIG_CRYPTO_ECDSA=m
+CONFIG_CRYPTO_ECRDSA=m
+CONFIG_CRYPTO_SM2=m
+CONFIG_CRYPTO_CURVE25519=m
+# end of Public-key cryptography
+
+#
+# Block ciphers
+#
+CONFIG_CRYPTO_AES=y
+# CONFIG_CRYPTO_AES_TI is not set
+CONFIG_CRYPTO_ANUBIS=m
+CONFIG_CRYPTO_ARIA=m
+CONFIG_CRYPTO_BLOWFISH=m
+CONFIG_CRYPTO_BLOWFISH_COMMON=m
+CONFIG_CRYPTO_CAMELLIA=m
+CONFIG_CRYPTO_CAST_COMMON=m
+CONFIG_CRYPTO_CAST5=m
+CONFIG_CRYPTO_CAST6=m
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_FCRYPT=m
+CONFIG_CRYPTO_KHAZAD=m
+CONFIG_CRYPTO_SEED=m
+CONFIG_CRYPTO_SERPENT=m
+CONFIG_CRYPTO_SM4=m
+CONFIG_CRYPTO_SM4_GENERIC=m
+CONFIG_CRYPTO_TEA=m
+CONFIG_CRYPTO_TWOFISH=m
+CONFIG_CRYPTO_TWOFISH_COMMON=m
+# end of Block ciphers
+
+#
+# Length-preserving ciphers and modes
+#
+# CONFIG_CRYPTO_ADIANTUM is not set
+CONFIG_CRYPTO_ARC4=m
+CONFIG_CRYPTO_CHACHA20=y
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CFB is not set
+CONFIG_CRYPTO_CTR=y
+CONFIG_CRYPTO_CTS=y
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_HCTR2=m
+# CONFIG_CRYPTO_KEYWRAP is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_OFB is not set
+# CONFIG_CRYPTO_PCBC is not set
+CONFIG_CRYPTO_XCTR=m
+CONFIG_CRYPTO_XTS=y
+CONFIG_CRYPTO_NHPOLY1305=m
+# end of Length-preserving ciphers and modes
+
+#
+# AEAD (authenticated encryption with associated data) ciphers
+#
+# CONFIG_CRYPTO_AEGIS128 is not set
+# CONFIG_CRYPTO_CHACHA20POLY1305 is not set
+CONFIG_CRYPTO_CCM=m
+CONFIG_CRYPTO_GCM=y
+CONFIG_CRYPTO_GENIV=y
+CONFIG_CRYPTO_SEQIV=y
+CONFIG_CRYPTO_ECHAINIV=y
+# CONFIG_CRYPTO_ESSIV is not set
+# end of AEAD (authenticated encryption with associated data) ciphers
+
+#
+# Hashes, digests, and MACs
+#
+CONFIG_CRYPTO_BLAKE2B=y
+CONFIG_CRYPTO_CMAC=y
+CONFIG_CRYPTO_GHASH=y
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_MD4=m
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_MICHAEL_MIC=m
+CONFIG_CRYPTO_POLYVAL=m
+CONFIG_CRYPTO_POLY1305=m
+# CONFIG_CRYPTO_RMD160 is not set
+CONFIG_CRYPTO_SHA1=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_SHA512=y
+CONFIG_CRYPTO_SHA3=y
+CONFIG_CRYPTO_SM3=m
+CONFIG_CRYPTO_SM3_GENERIC=m
+CONFIG_CRYPTO_STREEBOG=m
+# CONFIG_CRYPTO_VMAC is not set
+# CONFIG_CRYPTO_WP512 is not set
+# CONFIG_CRYPTO_XCBC is not set
+CONFIG_CRYPTO_XXHASH=m
+# end of Hashes, digests, and MACs
+
+#
+# CRCs (cyclic redundancy checks)
+#
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_CRC32=m
+# CONFIG_CRYPTO_CRCT10DIF is not set
+# end of CRCs (cyclic redundancy checks)
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_LZO=y
+# CONFIG_CRYPTO_842 is not set
+CONFIG_CRYPTO_LZ4=y
+# CONFIG_CRYPTO_LZ4HC is not set
+CONFIG_CRYPTO_ZSTD=y
+# end of Compression
+
+#
+# Random number generation
+#
+CONFIG_CRYPTO_ANSI_CPRNG=y
+CONFIG_CRYPTO_DRBG_MENU=y
+CONFIG_CRYPTO_DRBG_HMAC=y
+# CONFIG_CRYPTO_DRBG_HASH is not set
+# CONFIG_CRYPTO_DRBG_CTR is not set
+CONFIG_CRYPTO_DRBG=y
+CONFIG_CRYPTO_JITTERENTROPY=y
+# CONFIG_CRYPTO_JITTERENTROPY_TESTINTERFACE is not set
+CONFIG_CRYPTO_KDF800108_CTR=y
+# end of Random number generation
+
+#
+# Userspace interface
+#
+CONFIG_CRYPTO_USER_API=y
+CONFIG_CRYPTO_USER_API_HASH=y
+CONFIG_CRYPTO_USER_API_SKCIPHER=y
+# CONFIG_CRYPTO_USER_API_RNG is not set
+# CONFIG_CRYPTO_USER_API_AEAD is not set
+CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y
+CONFIG_CRYPTO_STATS=y
+# end of Userspace interface
+
+CONFIG_CRYPTO_HASH_INFO=y
+
+#
+# Accelerated Cryptographic Algorithms for CPU (arm)
+#
+CONFIG_CRYPTO_CURVE25519_NEON=m
+CONFIG_CRYPTO_GHASH_ARM_CE=m
+CONFIG_CRYPTO_NHPOLY1305_NEON=m
+CONFIG_CRYPTO_POLY1305_ARM=m
+CONFIG_CRYPTO_BLAKE2S_ARM=y
+CONFIG_CRYPTO_BLAKE2B_NEON=m
+CONFIG_CRYPTO_SHA1_ARM=m
+CONFIG_CRYPTO_SHA1_ARM_NEON=m
+CONFIG_CRYPTO_SHA1_ARM_CE=m
+CONFIG_CRYPTO_SHA2_ARM_CE=m
+CONFIG_CRYPTO_SHA256_ARM=m
+CONFIG_CRYPTO_SHA512_ARM=m
+CONFIG_CRYPTO_AES_ARM=m
+CONFIG_CRYPTO_AES_ARM_BS=m
+CONFIG_CRYPTO_AES_ARM_CE=m
+CONFIG_CRYPTO_CHACHA20_NEON=m
+CONFIG_CRYPTO_CRC32_ARM_CE=y
+# end of Accelerated Cryptographic Algorithms for CPU (arm)
+
+CONFIG_CRYPTO_HW=y
+# CONFIG_CRYPTO_DEV_ATMEL_ECC is not set
+# CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set
+CONFIG_CRYPTO_DEV_ROCKCHIP=y
+CONFIG_CRYPTO_DEV_ROCKCHIP_DEBUG=y
+# CONFIG_CRYPTO_DEV_VIRTIO is not set
+# CONFIG_CRYPTO_DEV_SAFEXCEL is not set
+# CONFIG_CRYPTO_DEV_CCREE is not set
+# CONFIG_CRYPTO_DEV_AMLOGIC_GXL is not set
+CONFIG_ASYMMETRIC_KEY_TYPE=y
+CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y
+CONFIG_X509_CERTIFICATE_PARSER=y
+CONFIG_PKCS8_PRIVATE_KEY_PARSER=m
+CONFIG_PKCS7_MESSAGE_PARSER=y
+# CONFIG_PKCS7_TEST_KEY is not set
+# CONFIG_SIGNED_PE_FILE_VERIFICATION is not set
+# CONFIG_FIPS_SIGNATURE_SELFTEST is not set
+
+#
+# Certificates for signature checking
+#
+CONFIG_SYSTEM_TRUSTED_KEYRING=y
+CONFIG_SYSTEM_TRUSTED_KEYS=""
+# CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set
+# CONFIG_SECONDARY_TRUSTED_KEYRING is not set
+# CONFIG_SYSTEM_BLACKLIST_KEYRING is not set
+# end of Certificates for signature checking
+
+CONFIG_BINARY_PRINTF=y
+
+#
+# Library routines
+#
+CONFIG_RAID6_PQ=m
+CONFIG_RAID6_PQ_BENCHMARK=y
+CONFIG_LINEAR_RANGES=y
+# CONFIG_PACKING is not set
+CONFIG_BITREVERSE=y
+CONFIG_HAVE_ARCH_BITREVERSE=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_NET_UTILS=y
+CONFIG_CORDIC=m
+# CONFIG_PRIME_NUMBERS is not set
+CONFIG_RATIONAL=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
+
+#
+# Crypto library routines
+#
+CONFIG_CRYPTO_LIB_UTILS=y
+CONFIG_CRYPTO_LIB_AES=y
+CONFIG_CRYPTO_LIB_ARC4=m
+CONFIG_CRYPTO_LIB_GF128MUL=y
+CONFIG_CRYPTO_ARCH_HAVE_LIB_BLAKE2S=y
+CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=m
+CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y
+CONFIG_CRYPTO_LIB_CHACHA=m
+CONFIG_CRYPTO_ARCH_HAVE_LIB_CURVE25519=m
+CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=m
+CONFIG_CRYPTO_LIB_CURVE25519=m
+CONFIG_CRYPTO_LIB_DES=y
+CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9
+CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=m
+CONFIG_CRYPTO_LIB_POLY1305_GENERIC=m
+CONFIG_CRYPTO_LIB_POLY1305=m
+CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_SHA256=y
+# end of Crypto library routines
+
+CONFIG_CRC_CCITT=m
+CONFIG_CRC16=y
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC64_ROCKSOFT is not set
+CONFIG_CRC_ITU_T=y
+CONFIG_CRC32=y
+# CONFIG_CRC32_SELFTEST is not set
+CONFIG_CRC32_SLICEBY8=y
+# CONFIG_CRC32_SLICEBY4 is not set
+# CONFIG_CRC32_SARWATE is not set
+# CONFIG_CRC32_BIT is not set
+# CONFIG_CRC64 is not set
+# CONFIG_CRC4 is not set
+CONFIG_CRC7=y
+CONFIG_LIBCRC32C=m
+CONFIG_CRC8=m
+CONFIG_XXHASH=y
+# CONFIG_RANDOM32_SELFTEST is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_LZ4_COMPRESS=y
+CONFIG_LZ4HC_COMPRESS=m
+CONFIG_LZ4_DECOMPRESS=y
+CONFIG_ZSTD_COMMON=y
+CONFIG_ZSTD_COMPRESS=y
+CONFIG_ZSTD_DECOMPRESS=y
+CONFIG_XZ_DEC=y
+CONFIG_XZ_DEC_X86=y
+CONFIG_XZ_DEC_POWERPC=y
+CONFIG_XZ_DEC_IA64=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_ARMTHUMB=y
+CONFIG_XZ_DEC_SPARC=y
+CONFIG_XZ_DEC_MICROLZMA=y
+CONFIG_XZ_DEC_BCJ=y
+# CONFIG_XZ_DEC_TEST is not set
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_DECOMPRESS_BZIP2=y
+CONFIG_DECOMPRESS_LZMA=y
+CONFIG_DECOMPRESS_XZ=y
+CONFIG_DECOMPRESS_LZO=y
+CONFIG_DECOMPRESS_LZ4=y
+CONFIG_DECOMPRESS_ZSTD=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_REED_SOLOMON=y
+CONFIG_REED_SOLOMON_ENC8=y
+CONFIG_REED_SOLOMON_DEC8=y
+CONFIG_TEXTSEARCH=y
+CONFIG_TEXTSEARCH_KMP=m
+CONFIG_TEXTSEARCH_BM=m
+CONFIG_TEXTSEARCH_FSM=m
+CONFIG_INTERVAL_TREE=y
+CONFIG_XARRAY_MULTI=y
+CONFIG_ASSOCIATIVE_ARRAY=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HAS_DMA=y
+CONFIG_DMA_OPS=y
+CONFIG_NEED_SG_DMA_LENGTH=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_DMA_DECLARE_COHERENT=y
+CONFIG_ARCH_HAS_SETUP_DMA_OPS=y
+CONFIG_ARCH_HAS_TEARDOWN_DMA_OPS=y
+CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y
+CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y
+CONFIG_DMA_NONCOHERENT_MMAP=y
+CONFIG_DMA_CMA=y
+
+#
+# Default contiguous memory area size:
+#
+CONFIG_CMA_SIZE_MBYTES=128
+CONFIG_CMA_SIZE_SEL_MBYTES=y
+# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
+# CONFIG_CMA_SIZE_SEL_MIN is not set
+# CONFIG_CMA_SIZE_SEL_MAX is not set
+CONFIG_CMA_ALIGNMENT=8
+# CONFIG_DMA_API_DEBUG is not set
+# CONFIG_DMA_MAP_BENCHMARK is not set
+CONFIG_SGL_ALLOC=y
+CONFIG_CPU_RMAP=y
+CONFIG_DQL=y
+CONFIG_GLOB=y
+# CONFIG_GLOB_SELFTEST is not set
+CONFIG_NLATTR=y
+CONFIG_CLZ_TAB=y
+# CONFIG_IRQ_POLL is not set
+CONFIG_MPILIB=y
+CONFIG_LIBFDT=y
+CONFIG_OID_REGISTRY=y
+CONFIG_HAVE_GENERIC_VDSO=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_VDSO_32=y
+CONFIG_FONT_SUPPORT=y
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+CONFIG_SG_POOL=y
+CONFIG_ARCH_STACKWALK=y
+CONFIG_STACKDEPOT=y
+CONFIG_SBITMAP=y
+# end of Library routines
+
+CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
+
+#
+# Kernel hacking
+#
+
+#
+# printk and dmesg options
+#
+CONFIG_PRINTK_TIME=y
+# CONFIG_PRINTK_CALLER is not set
+# CONFIG_STACKTRACE_BUILD_ID is not set
+CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7
+CONFIG_CONSOLE_LOGLEVEL_QUIET=4
+CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
+# CONFIG_BOOT_PRINTK_DELAY is not set
+CONFIG_DYNAMIC_DEBUG=y
+CONFIG_DYNAMIC_DEBUG_CORE=y
+CONFIG_SYMBOLIC_ERRNAME=y
+CONFIG_DEBUG_BUGVERBOSE=y
+# end of printk and dmesg options
+
+CONFIG_DEBUG_KERNEL=y
+CONFIG_DEBUG_MISC=y
+
+#
+# Compile-time checks and compiler options
+#
+CONFIG_AS_HAS_NON_CONST_LEB128=y
+CONFIG_DEBUG_INFO_NONE=y
+# CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT is not set
+# CONFIG_DEBUG_INFO_DWARF4 is not set
+# CONFIG_DEBUG_INFO_DWARF5 is not set
+CONFIG_FRAME_WARN=2048
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_READABLE_ASM is not set
+# CONFIG_HEADERS_INSTALL is not set
+# CONFIG_DEBUG_SECTION_MISMATCH is not set
+CONFIG_SECTION_MISMATCH_WARN_ONLY=y
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# end of Compile-time checks and compiler options
+
+#
+# Generic Kernel Debugging Instruments
+#
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1
+CONFIG_MAGIC_SYSRQ_SERIAL=y
+CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE=""
+CONFIG_DEBUG_FS=y
+CONFIG_DEBUG_FS_ALLOW_ALL=y
+# CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set
+# CONFIG_DEBUG_FS_ALLOW_NONE is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y
+# CONFIG_UBSAN is not set
+CONFIG_HAVE_KCSAN_COMPILER=y
+# end of Generic Kernel Debugging Instruments
+
+#
+# Networking Debugging
+#
+# CONFIG_NET_DEV_REFCNT_TRACKER is not set
+# CONFIG_NET_NS_REFCNT_TRACKER is not set
+# CONFIG_DEBUG_NET is not set
+# end of Networking Debugging
+
+#
+# Memory Debugging
+#
+# CONFIG_PAGE_EXTENSION is not set
+# CONFIG_DEBUG_PAGEALLOC is not set
+CONFIG_SLUB_DEBUG=y
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_PAGE_OWNER is not set
+# CONFIG_PAGE_POISONING is not set
+# CONFIG_DEBUG_RODATA_TEST is not set
+# CONFIG_DEBUG_WX is not set
+CONFIG_HAVE_DEBUG_KMEMLEAK=y
+# CONFIG_DEBUG_KMEMLEAK is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_SHRINKER_DEBUG is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_SCHED_STACK_END_CHECK is not set
+# CONFIG_DEBUG_VM is not set
+CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y
+# CONFIG_DEBUG_VIRTUAL is not set
+CONFIG_DEBUG_MEMORY_INIT=y
+# CONFIG_DEBUG_PER_CPU_MAPS is not set
+# CONFIG_DEBUG_KMAP_LOCAL is not set
+# CONFIG_DEBUG_HIGHMEM is not set
+CONFIG_HAVE_ARCH_KASAN=y
+CONFIG_HAVE_ARCH_KASAN_VMALLOC=y
+CONFIG_CC_HAS_KASAN_GENERIC=y
+CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y
+# CONFIG_KASAN is not set
+CONFIG_HAVE_ARCH_KFENCE=y
+# CONFIG_KFENCE is not set
+# end of Memory Debugging
+
+# CONFIG_DEBUG_SHIRQ is not set
+
+#
+# Debug Oops, Lockups and Hangs
+#
+# CONFIG_PANIC_ON_OOPS is not set
+CONFIG_PANIC_ON_OOPS_VALUE=0
+CONFIG_PANIC_TIMEOUT=0
+# CONFIG_SOFTLOCKUP_DETECTOR is not set
+CONFIG_HAVE_HARDLOCKUP_DETECTOR_BUDDY=y
+# CONFIG_HARDLOCKUP_DETECTOR is not set
+# CONFIG_DETECT_HUNG_TASK is not set
+# CONFIG_WQ_WATCHDOG is not set
+# CONFIG_WQ_CPU_INTENSIVE_REPORT is not set
+# CONFIG_TEST_LOCKUP is not set
+# end of Debug Oops, Lockups and Hangs
+
+#
+# Scheduler Debugging
+#
+# CONFIG_SCHED_DEBUG is not set
+CONFIG_SCHED_INFO=y
+# CONFIG_SCHEDSTATS is not set
+# end of Scheduler Debugging
+
+# CONFIG_DEBUG_TIMEKEEPING is not set
+
+#
+# Lock Debugging (spinlocks, mutexes, etc...)
+#
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set
+# CONFIG_DEBUG_RWSEMS is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_DEBUG_ATOMIC_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_LOCK_TORTURE_TEST is not set
+# CONFIG_WW_MUTEX_SELFTEST is not set
+# CONFIG_SCF_TORTURE_TEST is not set
+# end of Lock Debugging (spinlocks, mutexes, etc...)
+
+# CONFIG_DEBUG_IRQFLAGS is not set
+CONFIG_STACKTRACE=y
+# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set
+# CONFIG_DEBUG_KOBJECT is not set
+
+#
+# Debug kernel data structures
+#
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_PLIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_MAPLE_TREE is not set
+# end of Debug kernel data structures
+
+#
+# RCU Debugging
+#
+# CONFIG_RCU_SCALE_TEST is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_REF_SCALE_TEST is not set
+CONFIG_RCU_CPU_STALL_TIMEOUT=21
+CONFIG_RCU_EXP_CPU_STALL_TIMEOUT=0
+# CONFIG_RCU_CPU_STALL_CPUTIME is not set
+# CONFIG_RCU_TRACE is not set
+# CONFIG_RCU_EQS_DEBUG is not set
+# end of RCU Debugging
+
+# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set
+# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set
+# CONFIG_LATENCYTOP is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_HAVE_BUILDTIME_MCOUNT_SORT=y
+CONFIG_TRACING_SUPPORT=y
+# CONFIG_FTRACE is not set
+# CONFIG_SAMPLES is not set
+CONFIG_STRICT_DEVMEM=y
+# CONFIG_IO_STRICT_DEVMEM is not set
+
+#
+# arm Debugging
+#
+# CONFIG_ARM_PTDUMP_DEBUGFS is not set
+# CONFIG_UNWINDER_FRAME_POINTER is not set
+CONFIG_UNWINDER_ARM=y
+CONFIG_ARM_UNWIND=y
+# CONFIG_DEBUG_USER is not set
+# CONFIG_DEBUG_LL is not set
+CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
+CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
+# CONFIG_PID_IN_CONTEXTIDR is not set
+# CONFIG_CORESIGHT is not set
+# end of arm Debugging
+
+#
+# Kernel Testing and Coverage
+#
+# CONFIG_KUNIT is not set
+# CONFIG_NOTIFIER_ERROR_INJECTION is not set
+# CONFIG_FAULT_INJECTION is not set
+CONFIG_ARCH_HAS_KCOV=y
+CONFIG_CC_HAS_SANCOV_TRACE_PC=y
+# CONFIG_KCOV is not set
+# CONFIG_RUNTIME_TESTING_MENU is not set
+CONFIG_ARCH_USE_MEMTEST=y
+CONFIG_MEMTEST=y
+# end of Kernel Testing and Coverage
+
+#
+# Rust hacking
+#
+# end of Rust hacking
+# end of Kernel hacking
diff --git a/projects/Rockchip/devices/RK322X/options b/projects/Rockchip/devices/RK322X/options
new file mode 100644
index 0000000000..99f6e73095
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/options
@@ -0,0 +1,52 @@
+################################################################################
+# setup device defaults
+################################################################################
+
+  # The TARGET_CPU variable controls which processor should be targeted for
+  # generated code.
+    case $TARGET_ARCH in
+      arm)
+        TARGET_FLOAT="hard"
+        TARGET_CPU="cortex-a7"
+        TARGET_FPU="neon-vfpv4"
+        TARGET_FEATURES="32bit"
+        ;;
+    esac
+
+  # Kernel target
+    KERNEL_TARGET="zImage"
+
+  # SquashFS compression method (gzip / lzo / xz / zstd)
+    SQUASHFS_COMPRESSION="lzo"
+
+  # UBOOT_FIRMWARE+=" optee-os"
+  # OPTEE_PLATFORM="rockchip-rk322x"
+
+  # Additional kernel make parameters (for example to specify the u-boot loadaddress)
+  # KERNEL_MAKE_EXTRACMD=" rockchip/rk3229-xms6.dtb"
+    KERNEL_MAKE_EXTRACMD=" rockchip/rk322x-box.dtb \
+	rockchip/rk322x-box-t95d.dtb \
+	rockchip/rk322x-box-onetv-lite.dtb \
+	rockchip/rk322x-box-mxq4k.dtb \
+	rockchip/rk322x-box-mxq4k_r29.dtb \
+	rockchip/rk322x-box-mxq4kpro.dtb \
+	rockchip/rk322x-box-mxq4kpro_r329q.dtb \
+	rockchip/rk322x-box-v884k.dtb \
+	rockchip/rk322x-box-v88mars.dtb \
+	rockchip/rk322x-box-a95xr1.dtb"
+
+  # Mali GPU family
+    MALI_FAMILY="400"
+    GRAPHIC_DRIVERS="lima"
+
+  # kernel serial console
+    EXTRA_CMDLINE="console=uart8250,mmio32,0x11030000 console=tty0"
+
+  # set the addon project
+    ADDON_PROJECT="ARMv7"
+
+    ADDITIONAL_PACKAGES="$ADDITIONAL_PACKAGES rockchip-firmware irq-balancer openvfd-driver "
+
+    IR_REMOTE_KEYMAPS=" rockchip_remote "
+
+    WIRELESS_DAEMON="wpa_supplicant"
diff --git a/projects/Rockchip/devices/RK322X/packages/cmake/package.mk b/projects/Rockchip/devices/RK322X/packages/cmake/package.mk
new file mode 100644
index 0000000000..10b038279b
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/packages/cmake/package.mk
@@ -0,0 +1,25 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Copyright (C) 2009-2016 Stephan Raue (stephan@openelec.tv)
+# Copyright (C) 2016-present Team LibreELEC (https://libreelec.tv)
+
+PKG_NAME="cmake"
+PKG_VERSION="3.31.6"
+PKG_SHA256="653427f0f5014750aafff22727fb2aa60c6c732ca91808cfb78ce22ddd9e55f0"
+PKG_LICENSE="BSD"
+PKG_SITE="https://cmake.org/"
+PKG_URL="https://cmake.org/files/v$(get_pkg_version_maj_min)/cmake-${PKG_VERSION}.tar.gz"
+PKG_DEPENDS_HOST="pkg-config:host"
+PKG_LONGDESC="A cross-platform, open-source make system."
+PKG_TOOLCHAIN="configure"
+PKG_BUILD_FLAGS="+local-cc"
+
+configure_host() {
+  ../configure --prefix=${TOOLCHAIN} \
+               --no-qt-gui --no-system-libs \
+               -- \
+               -DCMAKE_C_FLAGS="-O2 -Wall -pipe -Wno-format-security" \
+               -DCMAKE_CXX_FLAGS="-O2 -Wall -pipe -Wno-format-security" \
+               -DCMAKE_EXE_LINKER_FLAGS="${HOST_LDFLAGS}" \
+               -DCMAKE_USE_OPENSSL=OFF \
+               -DBUILD_CursesDialog=0
+}
diff --git a/projects/Rockchip/devices/RK322X/packages/cmake/patches/cmake-001-disable-free-comp-methods.patch b/projects/Rockchip/devices/RK322X/packages/cmake/patches/cmake-001-disable-free-comp-methods.patch
new file mode 100644
index 0000000000..901379517d
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/packages/cmake/patches/cmake-001-disable-free-comp-methods.patch
@@ -0,0 +1,14 @@
+--- a/Utilities/cmcurl/lib/vtls/openssl.c.orig	2016-10-19 19:17:49.615923691 +0200
++++ b/Utilities/cmcurl/lib/vtls/openssl.c	2016-10-19 19:22:50.849565684 +0200
+@@ -134,6 +134,11 @@
+ #define HAVE_SSL_COMP_FREE_COMPRESSION_METHODS 1
+ #endif
+
++#if !defined(OPENSSL_NO_COMP) || \
++  OPENSSL_VERSION_NUMBER >= 0x10100000L /* 1.1.0+ has no free compression methods */
++#undef HAVE_SSL_COMP_FREE_COMPRESSION_METHODS /* undef */
++#endif
++
+ #if (OPENSSL_VERSION_NUMBER < 0x0090808fL)
+ /* not present in older OpenSSL */
+ #define OPENSSL_load_builtin_modules(x)
diff --git a/projects/Rockchip/devices/RK322X/packages/connman/config/settings b/projects/Rockchip/devices/RK322X/packages/connman/config/settings
new file mode 100644
index 0000000000..632a97b7a0
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/packages/connman/config/settings
@@ -0,0 +1,8 @@
+[global]
+OfflineMode=false
+
+[Wired]
+Enable=true
+
+[WiFi]
+Enable=true
diff --git a/projects/Rockchip/devices/RK322X/packages/connman/debug.d/connman.conf b/projects/Rockchip/devices/RK322X/packages/connman/debug.d/connman.conf
new file mode 100644
index 0000000000..86502aa3ea
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/packages/connman/debug.d/connman.conf
@@ -0,0 +1,2 @@
+CONNMAN_DEBUG="--debug"
+CONNMANVPN_DEBUG="--debug"
diff --git a/projects/Rockchip/devices/RK322X/packages/connman/package.mk b/projects/Rockchip/devices/RK322X/packages/connman/package.mk
new file mode 100644
index 0000000000..b0d6cbabe2
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/packages/connman/package.mk
@@ -0,0 +1,111 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Copyright (C) 2009-2016 Stephan Raue (stephan@openelec.tv)
+# Copyright (C) 2019-present Team LibreELEC (https://libreelec.tv)
+
+PKG_NAME="connman"
+PKG_VERSION="1.44"
+PKG_SHA256="d751da9858a6e3dfe70d6c98e71ea4f5896e1c92c5e1b17f10d055eaeae0e452"
+PKG_LICENSE="GPL"
+PKG_SITE="http://www.connman.net"
+PKG_URL="https://git.kernel.org/pub/scm/network/connman/connman.git/snapshot/connman-${PKG_VERSION}.tar.gz"
+PKG_DEPENDS_TARGET="toolchain dbus glib iptables readline"
+PKG_LONGDESC="A modular network connection manager."
+PKG_TOOLCHAIN="autotools"
+
+PKG_CONFIGURE_OPTS_TARGET="--srcdir=.. \
+                           --disable-debug \
+                           --disable-hh2serial-gps \
+                           --disable-openconnect \
+                           --disable-openvpn \
+                           --disable-vpnc \
+                           --disable-l2tp \
+                           --disable-pptp \
+                           --disable-iospm \
+                           --disable-tist \
+                           --disable-session-policy-local \
+                           --disable-test \
+                           --disable-nmcompat \
+                           --disable-polkit \
+                           --disable-selinux \
+                           --enable-loopback \
+                           --enable-ethernet \
+                           --disable-gadget \
+                           --disable-bluetooth \
+                           --disable-ofono \
+                           --disable-dundee \
+                           --disable-pacrunner \
+                           --disable-neard \
+                           --disable-wispr \
+                           --disable-tools \
+                           --disable-stats \
+                           --enable-client \
+                           --enable-datafiles \
+                           --with-dbusconfdir=/usr/share \
+                           --with-systemdunitdir=/usr/lib/systemd/system \
+                           --disable-silent-rules"
+
+case "${WIRELESS_DAEMON}" in
+  wpa_supplicant)
+    PKG_DEPENDS_TARGET+=" wpa_supplicant"
+    PKG_CONFIGURE_OPTS_TARGET+=" WPASUPPLICANT=/usr/bin/wpa_supplicant \
+                                 --enable-wifi \
+                                 --disable-iwd"
+    ;;
+  iwd)
+    PKG_DEPENDS_TARGET+=" iwd"
+    PKG_CONFIGURE_OPTS_TARGET+=" --disable-wifi \
+                                 --enable-iwd"
+    ;;
+esac
+
+
+if [ "${WIREGUARD_SUPPORT}" = "yes" ]; then
+  PKG_CONFIGURE_OPTS_TARGET+=" --enable-wireguard=builtin"
+else
+  PKG_CONFIGURE_OPTS_TARGET+=" --disable-wireguard"
+fi
+
+PKG_MAKE_OPTS_TARGET="storagedir=/storage/.cache/connman \
+                      vpn_storagedir=/storage/.config/wireguard \
+                      statedir=/run/connman"
+
+post_configure_target() {
+  libtool_remove_rpath libtool
+}
+
+post_makeinstall_target() {
+  rm -rf ${INSTALL}/usr/lib/systemd
+  rm -rf ${INSTALL}/usr/lib/tmpfiles.d/connman_resolvconf.conf
+
+  mkdir -p ${INSTALL}/usr/bin
+    cp -P client/connmanctl ${INSTALL}/usr/bin
+
+  mkdir -p ${INSTALL}/usr/lib/connman
+    cp -P ${PKG_DIR}/scripts/connman-setup ${INSTALL}/usr/lib/connman
+
+  mkdir -p ${INSTALL}/etc/connman
+    cp ../src/main.conf ${INSTALL}/etc/connman
+    sed -i ${INSTALL}/etc/connman/main.conf \
+        -e "s|^# BackgroundScanning.*|BackgroundScanning = true|g" \
+        -e "s|^# UseGatewaysAsTimeservers.*|UseGatewaysAsTimeservers = false|g" \
+        -e "s|^# FallbackNameservers.*|FallbackNameservers = 8.8.8.8,8.8.4.4|g" \
+        -e "s|^# FallbackTimeservers.*|FallbackTimeservers = 0.pool.ntp.org,1.pool.ntp.org,2.pool.ntp.org,3.pool.ntp.org|g" \
+        -e "s|^# PreferredTechnologies.*|PreferredTechnologies = ethernet,wifi,cellular|g" \
+        -e "s|^# TetheringTechnologies.*|TetheringTechnologies = ethernet,wifi|g" \
+        -e "s|^# AllowHostnameUpdates.*|AllowHostnameUpdates = false|g" \
+        -e "s|^# PersistentTetheringMode.*|PersistentTetheringMode = true|g" \
+        -e "s|^# NetworkInterfaceBlacklist = vmnet,vboxnet,virbr,ifb|NetworkInterfaceBlacklist = vmnet,vboxnet,virbr,ifb,docker,veth,zt|g"
+
+  mkdir -p ${INSTALL}/usr/share/connman/
+    cp ${PKG_DIR}/config/settings ${INSTALL}/usr/share/connman/
+}
+
+post_install() {
+  add_user system x 430 430 "service" "/var/run/connman" "/bin/sh"
+  add_group system 430
+
+  enable_service connman.service
+  if [ "${WIREGUARD_SUPPORT}" = "yes" ]; then
+    enable_service connman-vpn.service
+  fi
+}
diff --git a/projects/Rockchip/devices/RK322X/packages/connman/patches/connman-01-do-not-cleanup-routes.patch b/projects/Rockchip/devices/RK322X/packages/connman/patches/connman-01-do-not-cleanup-routes.patch
new file mode 100644
index 0000000000..5e7a1002a3
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/packages/connman/patches/connman-01-do-not-cleanup-routes.patch
@@ -0,0 +1,12 @@
+diff --git a/src/device.c b/src/device.c
+index 0fda950..eb09e53 100644
+--- a/src/device.c
++++ b/src/device.c
+@@ -1490,8 +1490,6 @@ int __connman_device_init(const char *device, const char *nodevice)
+	if (nodevice)
+		nodevice_filter = g_strsplit(nodevice, ",", -1);
+
+-	cleanup_devices();
+-
+	return 0;
+ }
diff --git a/projects/Rockchip/devices/RK322X/packages/connman/patches/connman-04-ipv6-disabled-by-default.patch b/projects/Rockchip/devices/RK322X/packages/connman/patches/connman-04-ipv6-disabled-by-default.patch
new file mode 100644
index 0000000000..556bc4f8a3
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/packages/connman/patches/connman-04-ipv6-disabled-by-default.patch
@@ -0,0 +1,22 @@
+commit 707a0d73d7231b1821072712a7771c7aef140e21
+Author: Stefan Saraev <stefan@saraev.ca>
+Date:   Tue Jul 23 11:28:10 2013 +0300
+
+    ipv6 disabled by default
+
+diff --git a/src/ipconfig.c b/src/ipconfig.c
+index fbeff8f..3eb61c4 100644
+--- a/src/ipconfig.c
++++ b/src/ipconfig.c
+@@ -1243,10 +1243,7 @@ static struct connman_ipconfig *create_ipv6config(int index)
+	ipv6config->index = index;
+	ipv6config->type = CONNMAN_IPCONFIG_TYPE_IPV6;
+
+-	if (!is_ipv6_supported)
+-		ipv6config->method = CONNMAN_IPCONFIG_METHOD_OFF;
+-	else
+-		ipv6config->method = CONNMAN_IPCONFIG_METHOD_AUTO;
++	ipv6config->method = CONNMAN_IPCONFIG_METHOD_OFF;
+
+	ipdevice = g_hash_table_lookup(ipdevice_hash, GINT_TO_POINTER(index));
+	if (ipdevice)
diff --git a/projects/Rockchip/devices/RK322X/packages/connman/patches/connman-05_link-against-ncurses.patch b/projects/Rockchip/devices/RK322X/packages/connman/patches/connman-05_link-against-ncurses.patch
new file mode 100644
index 0000000000..311c285df8
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/packages/connman/patches/connman-05_link-against-ncurses.patch
@@ -0,0 +1,24 @@
+From 59bd0267cc8a581ff6f3388756a5524159a75b3b Mon Sep 17 00:00:00 2001
+From: Stefan Saraev <stefan@saraev.ca>
+Date: Sat, 13 Dec 2014 14:36:57 +0200
+Subject: [PATCH 5/5] link against ncurses
+
+---
+ Makefile.am |    2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/Makefile.am b/Makefile.am
+index 41efc1f..d1d3ddc 100644
+--- a/Makefile.am
++++ b/Makefile.am
+@@ -312,7 +312,7 @@ client_connmanctl_SOURCES = client/dbus_helpers.h client/dbus_helpers.c \
+			client/main.c
+
+ client_connmanctl_LDADD = gdbus/libgdbus-internal.la @DBUS_LIBS@ @GLIB_LIBS@ \
+-				-lreadline -ldl
++				-lreadline -lncurses -ldl
+ endif
+
+ noinst_PROGRAMS += unit/test-ippool
+--
+1.7.10.4
diff --git a/projects/Rockchip/devices/RK322X/packages/connman/scripts/connman-setup b/projects/Rockchip/devices/RK322X/packages/connman/scripts/connman-setup
new file mode 100755
index 0000000000..16bc279ad2
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/packages/connman/scripts/connman-setup
@@ -0,0 +1,25 @@
+#!/bin/sh
+
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Copyright (C) 2009-2014 Stephan Raue (stephan@openelec.tv)
+
+# creating initial settings file
+  if [ ! -f /storage/.cache/connman/settings ]; then
+    mkdir -p /storage/.cache/connman
+      cp /usr/share/connman/settings /storage/.cache/connman
+  fi
+
+# set variable for connman main.conf location
+  if [ -f /storage/.config/connman_main.conf ]; then
+    export CONNMAN_MAIN="--config=/storage/.config/connman_main.conf"
+  else
+    export CONNMAN_MAIN="--config=/etc/connman/main.conf"
+  fi
+
+# switch resolv.conf management to connman and use current contents
+# as a fallback
+if [ -f /run/libreelec/resolv.conf ]; then
+  cat /run/libreelec/resolv.conf > /run/connman/resolv.conf
+fi
+rm -f /run/libreelec/resolv.conf
+ln -s /run/connman/resolv.conf /run/libreelec/resolv.conf
diff --git a/projects/Rockchip/devices/RK322X/packages/connman/system.d/connman-vpn.service b/projects/Rockchip/devices/RK322X/packages/connman/system.d/connman-vpn.service
new file mode 100644
index 0000000000..6711bd4b68
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/packages/connman/system.d/connman-vpn.service
@@ -0,0 +1,14 @@
+[Unit]
+Description=ConnMan VPN service
+
+[Service]
+Type=dbus
+BusName=net.connman.vpn
+ExecStart=/usr/sbin/connman-vpnd -n
+StandardOutput=null
+CapabilityBoundingSet=CAP_KILL CAP_NET_ADMIN CAP_NET_BIND_SERVICE CAP_NET_RAW CAP_SETGID CAP_SETUID
+ProtectHome=read-only
+ProtectSystem=full
+
+[Install]
+WantedBy=multi-user.target
diff --git a/projects/Rockchip/devices/RK322X/packages/connman/system.d/connman.service b/projects/Rockchip/devices/RK322X/packages/connman/system.d/connman.service
new file mode 100644
index 0000000000..7ae77172e8
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/packages/connman/system.d/connman.service
@@ -0,0 +1,21 @@
+[Unit]
+Description=Connection service
+DefaultDependencies=false
+Conflicts=shutdown.target
+Before=network.target multi-user.target shutdown.target
+After=dbus.service network-base.service
+Wants=network.target
+ConditionPathExists=!/dev/.kernel_ipconfig
+
+[Service]
+Type=dbus
+BusName=net.connman
+Restart=on-failure
+EnvironmentFile=-/run/libreelec/debug/connman.conf
+ExecStart=/bin/sh -c ". /usr/lib/connman/connman-setup; exec /usr/sbin/connmand -nr $CONNMAN_MAIN $CONNMAN_DEBUG"
+StandardOutput=null
+RestartSec=2
+StartLimitInterval=0
+
+[Install]
+WantedBy=multi-user.target
diff --git a/projects/Rockchip/devices/RK322X/packages/connman/system.d/network-online.service b/projects/Rockchip/devices/RK322X/packages/connman/system.d/network-online.service
new file mode 100644
index 0000000000..935f638938
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/packages/connman/system.d/network-online.service
@@ -0,0 +1,17 @@
+[Unit]
+Description=Wait for network to be configured by ConnMan
+After=connman.service
+Before=network-online.target
+DefaultDependencies=no
+Conflicts=shutdown.target
+ConditionPathExists=!/dev/.kernel_ipconfig
+
+[Service]
+Type=oneshot
+ExecStartPre=/bin/sh -c 'echo "waiting on Network to come online ..."'
+ExecStart=/usr/sbin/connmand-wait-online --timeout=30
+StandardOutput=tty
+RemainAfterExit=yes
+
+[Install]
+WantedBy=network-online.target
diff --git a/projects/Rockchip/devices/RK322X/packages/connman/tmpfiles.d/z_03_connman.conf b/projects/Rockchip/devices/RK322X/packages/connman/tmpfiles.d/z_03_connman.conf
new file mode 100644
index 0000000000..ebadc7ae17
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/packages/connman/tmpfiles.d/z_03_connman.conf
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Copyright (C) 2009-2014 Stephan Raue (stephan@openelec.tv)
+
+d    /run/connman                0755 root root - -
+d    /storage/.cache/connman     0755 root root - -
diff --git a/projects/Rockchip/devices/RK322X/packages/e2fsprogs/package.mk b/projects/Rockchip/devices/RK322X/packages/e2fsprogs/package.mk
new file mode 100644
index 0000000000..4763bb5cb0
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/packages/e2fsprogs/package.mk
@@ -0,0 +1,118 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Copyright (C) 2009-2016 Stephan Raue (stephan@openelec.tv)
+# Copyright (C) 2018-present Team LibreELEC (https://libreelec.tv)
+
+PKG_NAME="e2fsprogs"
+PKG_VERSION="1.47.2"
+PKG_SHA256="08242e64ca0e8194d9c1caad49762b19209a06318199b63ce74ae4ef2d74e63c"
+PKG_LICENSE="GPL"
+PKG_SITE="http://e2fsprogs.sourceforge.net/"
+PKG_URL="https://www.kernel.org/pub/linux/kernel/people/tytso/${PKG_NAME}/v${PKG_VERSION}/${PKG_NAME}-${PKG_VERSION}.tar.xz"
+PKG_DEPENDS_HOST="autotools:host"
+PKG_DEPENDS_TARGET="autotools:host gcc:host"
+PKG_DEPENDS_INIT="autotools:host gcc:host"
+PKG_LONGDESC="The filesystem utilities for the EXT2 filesystem, including e2fsck, mke2fs, dumpe2fs, fsck, and others."
+PKG_BUILD_FLAGS="-parallel -cfg-libs -cfg-libs:host -cfg-libs:init"
+
+PKG_CONFIGURE_OPTS_HOST="--prefix=${TOOLCHAIN}/ \
+                         --bindir=${TOOLCHAIN}/bin \
+                         --sbindir=${TOOLCHAIN}/sbin \
+                         --disable-debugfs \
+                         --disable-defrag \
+                         --disable-e2initrd-helper \
+                         --disable-fsck \
+                         --disable-fuse2fs \
+                         --disable-imager \
+                         --disable-nls \
+                         --disable-resizer \
+                         --disable-rpath \
+                         --disable-subset \
+                         --disable-symlink-build \
+                         --disable-symlink-install \
+                         --enable-tls \
+                         --disable-uuidd \
+                         --enable-verbose-makecmds \
+                         --with-crond-dir=no \
+                         --with-gnu-ld \
+                         --without-pthread \
+                         --with-systemd-unit-dir=no \
+                         --with-udev-rules-dir=no"
+
+post_unpack() {
+  # Increase minimal inode size to avoid:
+  # "ext4 filesystem being mounted at xxx supports timestamps until 2038 (0x7fffffff)"
+  sed -i 's/inode_size = 128/inode_size = 256/g' ${PKG_BUILD}/misc/mke2fs.conf.in
+}
+
+pre_configure() {
+  PKG_CONFIGURE_OPTS_INIT="BUILD_CC=${HOST_CC} \
+                           --disable-blkid-debug \
+                           --disable-bsd-shlibs \
+                           --disable-debugfs \
+                           --disable-e2initrd-helper \
+                           --disable-elf-shlibs \
+                           --enable-fsck \
+                           --disable-fuse2fs \
+                           --disable-imager \
+                           --disable-jbd-debug \
+                           --enable-libblkid \
+                           --enable-libuuid \
+                           --disable-nls \
+                           --disable-profile \
+                           --enable-resizer \
+                           --disable-rpath \
+                           --disable-subset \
+                           --enable-symlink-build \
+                           --enable-symlink-install \
+                           --disable-testio-debug \
+                           --enable-tls \
+                           --disable-uuidd \
+                           --enable-verbose-makecmds \
+                           --with-crond-dir=no \
+                           --with-gnu-ld \
+                           --without-pthread \
+                           --with-systemd-unit-dir=no \
+                           --with-udev-rules-dir=no"
+
+  PKG_CONFIGURE_OPTS_TARGET="${PKG_CONFIGURE_OPTS_INIT}"
+}
+
+post_makeinstall_target() {
+  make -C lib/et LIBMODE=644 DESTDIR=${SYSROOT_PREFIX} install
+
+  rm -rf ${INSTALL}/usr/sbin/badblocks
+  rm -rf ${INSTALL}/usr/sbin/blkid
+  rm -rf ${INSTALL}/usr/sbin/dumpe2fs
+  rm -rf ${INSTALL}/usr/sbin/e2freefrag
+  rm -rf ${INSTALL}/usr/sbin/e2mmpstatus
+  rm -rf ${INSTALL}/usr/sbin/e2undo
+  rm -rf ${INSTALL}/usr/sbin/e4defrag
+  rm -rf ${INSTALL}/usr/sbin/filefrag
+  rm -rf ${INSTALL}/usr/sbin/fsck
+  rm -rf ${INSTALL}/usr/sbin/logsave
+  rm -rf ${INSTALL}/usr/sbin/mklost+found
+}
+
+makeinstall_init() {
+  mkdir -p ${INSTALL}/usr/sbin
+    cp e2fsck/e2fsck ${INSTALL}/usr/sbin
+    ln -sf e2fsck ${INSTALL}/usr/sbin/fsck.ext2
+    ln -sf e2fsck ${INSTALL}/usr/sbin/fsck.ext3
+    ln -sf e2fsck ${INSTALL}/usr/sbin/fsck.ext4
+
+  if [ ${INITRAMFS_PARTED_SUPPORT} = "yes" ]; then
+    cp misc/mke2fs ${INSTALL}/usr/sbin
+    ln -sf mke2fs ${INSTALL}/usr/sbin/mkfs.ext2
+    ln -sf mke2fs ${INSTALL}/usr/sbin/mkfs.ext3
+    ln -sf mke2fs ${INSTALL}/usr/sbin/mkfs.ext4
+  fi
+}
+
+makeinstall_host() {
+  make -C lib/et LIBMODE=644 install
+  make -C lib/ext2fs LIBMODE=644 install
+  mkdir -p ${TOOLCHAIN}/sbin
+  cp e2fsck/e2fsck ${TOOLCHAIN}/sbin
+  cp misc/mke2fs ${TOOLCHAIN}/sbin
+  cp misc/tune2fs ${TOOLCHAIN}/sbin
+}
diff --git a/projects/Rockchip/devices/RK322X/packages/elfutils/package.mk b/projects/Rockchip/devices/RK322X/packages/elfutils/package.mk
new file mode 100644
index 0000000000..006150323e
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/packages/elfutils/package.mk
@@ -0,0 +1,56 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Copyright (C) 2009-2016 Stephan Raue (stephan@openelec.tv)
+# Copyright (C) 2018-present Team LibreELEC (https://libreelec.tv)
+
+PKG_NAME="elfutils"
+PKG_VERSION="0.193"
+PKG_SHA256="7857f44b624f4d8d421df851aaae7b1402cfe6bcdd2d8049f15fc07d3dde7635"
+PKG_LICENSE="GPL"
+PKG_SITE="https://sourceware.org/elfutils/"
+PKG_URL="https://sourceware.org/elfutils/ftp/${PKG_VERSION}/${PKG_NAME}-${PKG_VERSION}.tar.bz2"
+PKG_DEPENDS_HOST="autoconf:host automake:host m4:host make:host zlib:host"
+PKG_DEPENDS_TARGET="toolchain zlib elfutils:host libarchive"
+PKG_LONGDESC="A collection of utilities to handle ELF objects."
+PKG_TOOLCHAIN="autotools"
+PKG_BUILD_FLAGS="+pic -cfg-libs -cfg-libs:host"
+
+if [ "${DISTRO_VERSION}" = "devel" ]; then
+  PKG_PROGRAMS="--enable-programs --program-prefix="
+  PKG_PROGRAMS_LIST="readelf"
+else
+  PKG_PROGRAMS="--disable-programs"
+  PKG_PROGRAMS_LIST=
+fi
+
+PKG_CONFIGURE_OPTS_HOST="utrace_cv_cc_biarch=false \
+                         --disable-programs \
+                         --disable-nls \
+                         --disable-debuginfod \
+                         --disable-libdebuginfod \
+                         --with-zlib \
+                         --without-bzlib \
+                         --without-lzma"
+
+PKG_CONFIGURE_OPTS_TARGET="utrace_cv_cc_biarch=false \
+                           ${PKG_PROGRAMS} \
+                           --disable-nls \
+                           --disable-debuginfod \
+                           --disable-libdebuginfod \
+                           --with-zlib \
+                           --without-bzlib \
+                           --without-lzma"
+
+pre_configure_target() {
+  export PKG_CONFIG="${PKG_CONFIG} --static"
+}
+
+post_makeinstall_target() {
+  # don't install progs into sysroot
+  rm -fr ${SYSROOT_PREFIX}/usr/bin
+
+  if [ -n "${PKG_PROGRAMS_LIST}" ]; then
+    for PKG_TEMP in $(find ${INSTALL}/usr/bin -type f); do
+      listcontains "${PKG_PROGRAMS_LIST}" ${PKG_TEMP#${INSTALL}/usr/bin/} || rm ${PKG_TEMP}
+    done
+  fi
+}
diff --git a/projects/Rockchip/devices/RK322X/packages/elfutils/patches/elfutils-001-make-executables-optional.patch b/projects/Rockchip/devices/RK322X/packages/elfutils/patches/elfutils-001-make-executables-optional.patch
new file mode 100644
index 0000000000..a8af6565df
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/packages/elfutils/patches/elfutils-001-make-executables-optional.patch
@@ -0,0 +1,45 @@
+From be854357189b6a3bd7e846b4e7914877f0deaf9f Mon Sep 17 00:00:00 2001
+From: MilhouseVH <milhouseVH.github@nmacleod.com>
+Date: Sat, 25 Jan 2020 21:28:52 +0000
+Subject: [PATCH] make executables optional
+
+---
+ Makefile.am  | 6 +++++-
+ configure.ac | 5 +++++
+ 2 files changed, 10 insertions(+), 1 deletion(-)
+
+diff --git a/Makefile.am b/Makefile.am
+index bd8926b..1733937 100644
+--- a/Makefile.am
++++ b/Makefile.am
+@@ -29,7 +29,11 @@
+ pkginclude_HEADERS = version.h
+
+ SUBDIRS = config lib libelf libcpu backends libebl libdwelf libdwfl \
+-	  libdwfl_stacktrace libdw libasm debuginfod src po doc tests
++	  libdwfl_stacktrace libdw libasm debuginfod po doc tests
++
++if BUILD_PROGRAMS
++  SUBDIRS += src
++endif
+
+ EXTRA_DIST = elfutils.spec GPG-KEY NOTES CONTRIBUTING SECURITY \
+	     COPYING COPYING-GPLV2 COPYING-LGPLV3 CONDUCT
+diff --git a/configure.ac b/configure.ac
+index 5a2dc37..a1e856a 100644
+--- a/configure.ac
++++ b/configure.ac
+@@ -82,6 +82,11 @@
+
+ AH_TEMPLATE([USE_LOCKS], [Defined if libraries should be thread-safe.])
+
++AC_ARG_ENABLE([programs],
++AS_HELP_STRING([--enable-programs], [Build and install programs when enabled (default: disabled)]),
++               [build_programs=$enableval], [build_programs=no])
++AM_CONDITIONAL(BUILD_PROGRAMS, test "$build_programs" = yes)
++
+ # Provided by gnulib's m4/std-gnu11.m4 for autoconf pre 2.70
+ AC_PROG_CC
+ AS_IF([test "x$ac_cv_prog_cc_c11" = "xno"],
+--
+2.7.4
diff --git a/projects/Rockchip/devices/RK322X/packages/elfutils/patches/elfutils-002-libelf--Add-libeu-objects-to-libelf.a-static-archive.patch b/projects/Rockchip/devices/RK322X/packages/elfutils/patches/elfutils-002-libelf--Add-libeu-objects-to-libelf.a-static-archive.patch
new file mode 100644
index 0000000000..4267e21f7b
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/packages/elfutils/patches/elfutils-002-libelf--Add-libeu-objects-to-libelf.a-static-archive.patch
@@ -0,0 +1,35 @@
+From f5d6e088f84dd05278c4698a21cbf1ff4569978d Mon Sep 17 00:00:00 2001
+From: Mark Wielaard <mark@klomp.org>
+Date: Tue, 22 Oct 2024 15:03:42 +0200
+Subject: [PATCH] libelf: Add libeu objects to libelf.a static archive
+
+libelf might use some symbols from libeu.a, specifically the eu-search
+wrappers. But we don't ship libeu.a separately. So include the libeu
+objects in the libelf.a archive to facilitate static linking.
+
+	* libelf/Makefile.am (libeu_objects): New variable.
+	(libelf_a_LIBADD): New, add libeu_objects.
+
+https://sourceware.org/bugzilla/show_bug.cgi?id=32293
+
+Signed-off-by: Mark Wielaard <mark@klomp.org>
+---
+ libelf/Makefile.am | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/libelf/Makefile.am b/libelf/Makefile.am
+index 3402863ef..2d3dbdf22 100644
+--- a/libelf/Makefile.am
++++ b/libelf/Makefile.am
+@@ -122,6 +122,9 @@ libelf.so: $(srcdir)/libelf.map $(libelf_so_LIBS) $(libelf_so_DEPS)
+	@$(textrel_check)
+	$(AM_V_at)ln -fs $@ $@.$(VERSION)
+
++libeu_objects = $(shell $(AR) t ../lib/libeu.a)
++libelf_a_LIBADD = $(addprefix ../lib/,$(libeu_objects))
++
+ install: install-am libelf.so
+	$(mkinstalldirs) $(DESTDIR)$(libdir)
+	$(INSTALL_PROGRAM) libelf.so $(DESTDIR)$(libdir)/libelf-$(PACKAGE_VERSION).so
+--
+2.43.5
diff --git a/projects/Rockchip/devices/RK322X/packages/irq-balancer/package.mk b/projects/Rockchip/devices/RK322X/packages/irq-balancer/package.mk
new file mode 100644
index 0000000000..32bb09afdf
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/packages/irq-balancer/package.mk
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0
+# Copyright (C) 2018-present Team LibreELEC (https://libreelec.tv)
+
+PKG_NAME="irq-balancer"
+PKG_VERSION="1.0"
+PKG_LICENSE="GPLv2"
+PKG_LONGDESC="irq-balancer: script that config irqs"
+PKG_TOOLCHAIN="manual"
+
+makeinstall_target() {
+  mkdir -p ${INSTALL}/usr/bin
+    cp ${PKG_DIR}/scripts/irq-balancer ${INSTALL}/usr/bin
+}
+
+post_install() {
+  enable_service irq-balancer.service
+}
diff --git a/projects/Rockchip/devices/RK322X/packages/irq-balancer/scripts/irq-balancer b/projects/Rockchip/devices/RK322X/packages/irq-balancer/scripts/irq-balancer
new file mode 100755
index 0000000000..153ac0bd33
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/packages/irq-balancer/scripts/irq-balancer
@@ -0,0 +1,19 @@
+#!/bin/sh
+
+# graphics and multimedia stack
+# echo 2 > /proc/irq/$(awk -F":" "/20030000.video-codec/ {print \$1}" < /proc/interrupts | sed 's/\ //g')/smp_affinity
+# echo 2 > /proc/irq/$(awk -F":" "/pp0/ {print \$1}" < /proc/interrupts | sed 's/\ //g')/smp_affinity
+# echo 2 > /proc/irq/$(awk -F":" "/gp$/ {print \$1}" < /proc/interrupts | sed 's/\ //g')/smp_affinity
+# echo 2 > /proc/irq/$(awk -F":" "/20050000.vop$/ {print \$1}" < /proc/interrupts | sed 's/\ //g')/smp_affinity
+# echo 2 > /proc/irq/$(awk -F":" "/20070000.iep$/ {print \$1}" < /proc/interrupts | sed 's/\ //g')/smp_affinity
+# usb stack
+echo 4 > /proc/irq/$(awk -F":" "/:usb1/ {print \$1}" < /proc/interrupts | sed 's/\ //g')/smp_affinity
+echo 4 > /proc/irq/$(awk -F":" "/:usb2/ {print \$1}" < /proc/interrupts | sed 's/\ //g')/smp_affinity
+echo 4 > /proc/irq/$(awk -F":" "/:usb3/ {print \$1}" < /proc/interrupts | sed 's/\ //g')/smp_affinity
+echo 4 > /proc/irq/$(awk -F":" "/:usb4/ {print \$1}" < /proc/interrupts | sed 's/\ //g')/smp_affinity
+echo 4 > /proc/irq/$(awk -F":" "/:usb5/ {print \$1}" < /proc/interrupts | sed 's/\ //g')/smp_affinity
+echo 4 > /proc/irq/$(awk -F":" "/:usb6/ {print \$1}" < /proc/interrupts | sed 's/\ //g')/smp_affinity
+echo 4 > /proc/irq/$(awk -F":" "/:usb7/ {print \$1}" < /proc/interrupts | sed 's/\ //g')/smp_affinity
+# network stack
+# echo 8 > /proc/irq/$(awk -F":" "/30010000.mmc$/ {print \$1}" < /proc/interrupts | sed 's/\ //g')/smp_affinity
+# echo 8 > /proc/irq/$(awk -F":" "/eth0/ {print \$1}" < /proc/interrupts | sed 's/\ //g' | head -n1)/smp_affinity
diff --git a/projects/Rockchip/devices/RK322X/packages/irq-balancer/system.d/irq-balancer.service b/projects/Rockchip/devices/RK322X/packages/irq-balancer/system.d/irq-balancer.service
new file mode 100644
index 0000000000..285823725f
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/packages/irq-balancer/system.d/irq-balancer.service
@@ -0,0 +1,12 @@
+[Unit]
+Description=Configure irq
+Before=kodi.service
+After=network-online.target graphical.target
+
+[Service]
+Type=oneshot
+RemainAfterExit=yes
+ExecStart=/usr/bin/irq-balancer
+
+[Install]
+WantedBy=kodi.target
diff --git a/projects/Rockchip/devices/RK322X/packages/m4/package.mk b/projects/Rockchip/devices/RK322X/packages/m4/package.mk
new file mode 100644
index 0000000000..0d88dd4a7e
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/packages/m4/package.mk
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Copyright (C) 2009-2016 Stephan Raue (stephan@openelec.tv)
+
+PKG_NAME="m4"
+PKG_VERSION="1.4.20"
+PKG_SHA256="ac6989ee5d2aed81739780630cc2ce097e2a6546feb96a4a54db37d46a1452e4"
+PKG_LICENSE="GPL"
+PKG_SITE="http://www.gnu.org/software/m4/"
+PKG_URL="http://ftpmirror.gnu.org/m4/${PKG_NAME}-${PKG_VERSION}.tar.bz2"
+PKG_DEPENDS_HOST="ccache:host"
+PKG_LONGDESC="The m4 macro processor."
+
+PKG_CONFIGURE_OPTS_HOST="gl_cv_func_gettimeofday_clobber=no --target=${TARGET_NAME}"
+
+post_makeinstall_host() {
+  make prefix=${SYSROOT_PREFIX}/usr install
+}
diff --git a/projects/Rockchip/devices/RK322X/packages/mesa/package.mk b/projects/Rockchip/devices/RK322X/packages/mesa/package.mk
new file mode 100644
index 0000000000..3374240a50
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/packages/mesa/package.mk
@@ -0,0 +1,99 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Copyright (C) 2009-2016 Stephan Raue (stephan@openelec.tv)
+# Copyright (C) 2018-present Team LibreELEC (https://libreelec.tv)
+
+PKG_NAME="mesa"
+PKG_VERSION="25.1.4"
+PKG_SHA256="164872a5e792408aa72fecd52b7be6409724c4ad81700798675a7d801d976704"
+PKG_LICENSE="OSS"
+PKG_SITE="http://www.mesa3d.org/"
+PKG_URL="https://mesa.freedesktop.org/archive/mesa-${PKG_VERSION}.tar.xz"
+PKG_DEPENDS_TARGET="toolchain expat libdrm Mako:host pyyaml:host"
+PKG_LONGDESC="Mesa is a 3-D graphics library with an API."
+
+get_graphicdrivers
+
+if [ "${DEVICE}" = "Dragonboard" ]; then
+  PKG_DEPENDS_TARGET+=" libarchive libxml2 lua54"
+fi
+
+PKG_MESON_OPTS_TARGET="-Dgallium-drivers=${GALLIUM_DRIVERS// /,} \
+                       -Dgallium-extra-hud=false \
+                       -Dgallium-nine=false \
+                       -Dgallium-opencl=disabled \
+                       -Dshader-cache=enabled \
+                       -Dshared-glapi=enabled \
+                       -Dopengl=true \
+                       -Dgbm=enabled \
+                       -Degl=enabled \
+                       -Dvalgrind=disabled \
+                       -Dlibunwind=disabled \
+                       -Dlmsensors=disabled \
+                       -Dbuild-tests=false \
+                       -Ddraw-use-llvm=false \
+                       -Dselinux=false \
+                       -Dosmesa=false"
+
+if [ "${DISPLAYSERVER}" = "x11" ]; then
+  PKG_DEPENDS_TARGET+=" xorgproto libXext libXdamage libXfixes libXxf86vm libxcb libX11 libxshmfence libXrandr"
+  export X11_INCLUDES=
+  PKG_MESON_OPTS_TARGET+=" -Dplatforms=x11 \
+                           -Ddri3=enabled \
+                           -Dglx=dri"
+elif [ "${DISPLAYSERVER}" = "wl" ]; then
+  PKG_DEPENDS_TARGET+=" wayland wayland-protocols"
+  PKG_MESON_OPTS_TARGET+=" -Dplatforms=wayland \
+                           -Ddri3=disabled \
+                           -Dglx=disabled"
+else
+  PKG_MESON_OPTS_TARGET+=" -Dplatforms="" \
+                           -Dglx=disabled"
+fi
+
+if listcontains "${GRAPHIC_DRIVERS}" "(nvidia|nvidia-ng)"; then
+  PKG_DEPENDS_TARGET+=" libglvnd"
+  PKG_MESON_OPTS_TARGET+=" -Dglvnd=true"
+else
+  PKG_MESON_OPTS_TARGET+=" -Dglvnd=false"
+fi
+
+if [ "${LLVM_SUPPORT}" = "yes" ]; then
+  PKG_DEPENDS_TARGET+=" elfutils llvm"
+  PKG_MESON_OPTS_TARGET+=" -Dllvm=enabled"
+else
+  PKG_MESON_OPTS_TARGET+=" -Dllvm=disabled"
+fi
+
+if [ "${VDPAU_SUPPORT}" = "yes" -a "${DISPLAYSERVER}" = "x11" ]; then
+  PKG_DEPENDS_TARGET+=" libvdpau"
+  PKG_MESON_OPTS_TARGET+=" -Dgallium-vdpau=enabled"
+else
+  PKG_MESON_OPTS_TARGET+=" -Dgallium-vdpau=disabled"
+fi
+
+if [ "${VAAPI_SUPPORT}" = "yes" ] && listcontains "${GRAPHIC_DRIVERS}" "(r600|radeonsi)"; then
+  PKG_DEPENDS_TARGET+=" libva"
+  PKG_MESON_OPTS_TARGET+=" -Dgallium-va=enabled \
+                           -Dvideo-codecs=vc1dec,h264dec,h264enc,h265dec,h265enc"
+else
+  PKG_MESON_OPTS_TARGET+=" -Dgallium-va=disabled"
+fi
+
+if listcontains "${GRAPHIC_DRIVERS}" "vmware"; then
+  PKG_MESON_OPTS_TARGET+=" -Dgallium-xa=enabled"
+else
+  PKG_MESON_OPTS_TARGET+=" -Dgallium-xa=disabled"
+fi
+
+if [ "${OPENGLES_SUPPORT}" = "yes" ]; then
+  PKG_MESON_OPTS_TARGET+=" -Dgles1=disabled -Dgles2=enabled"
+else
+  PKG_MESON_OPTS_TARGET+=" -Dgles1=disabled -Dgles2=disabled"
+fi
+
+if [ "${VULKAN_SUPPORT}" = "yes" ]; then
+  PKG_DEPENDS_TARGET+=" ${VULKAN} vulkan-tools"
+  PKG_MESON_OPTS_TARGET+=" -Dvulkan-drivers=${VULKAN_DRIVERS_MESA// /,}"
+else
+  PKG_MESON_OPTS_TARGET+=" -Dvulkan-drivers="
+fi
diff --git a/projects/Rockchip/devices/RK322X/packages/mesa/patches/0001-lima-use-hardware-y-coord-flipping.patch b/projects/Rockchip/devices/RK322X/packages/mesa/patches/0001-lima-use-hardware-y-coord-flipping.patch
new file mode 100644
index 0000000000..95cd403a5b
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/packages/mesa/patches/0001-lima-use-hardware-y-coord-flipping.patch
@@ -0,0 +1,175 @@
+diff -ruPN mesa-25.1.3/src/gallium/auxiliary/util/u_framebuffer.c mesa-new/src/gallium/auxiliary/util/u_framebuffer.c
+--- mesa-25.1.3/src/gallium/auxiliary/util/u_framebuffer.c	2025-06-07 15:47:15.000000000 +0200
++++ mesa-new/src/gallium/auxiliary/util/u_framebuffer.c	2025-06-22 09:23:07.304890312 +0200
+@@ -109,6 +109,8 @@
+
+       dst->nr_cbufs = src->nr_cbufs;
+
++      dst->flip_y = src->flip_y;
++
+       dst->viewmask = src->viewmask;
+       pipe_surface_reference(&dst->zsbuf, src->zsbuf);
+       pipe_resource_reference(&dst->resolve, src->resolve);
+@@ -124,6 +126,8 @@
+
+       dst->nr_cbufs = 0;
+
++      dst->flip_y = 0;
++
+       dst->viewmask = 0;
+
+       pipe_surface_reference(&dst->zsbuf, NULL);
+diff -ruPN mesa-25.1.3/src/gallium/auxiliary/util/u_screen.c mesa-new/src/gallium/auxiliary/util/u_screen.c
+--- mesa-25.1.3/src/gallium/auxiliary/util/u_screen.c	2025-06-07 15:47:15.000000000 +0200
++++ mesa-new/src/gallium/auxiliary/util/u_screen.c	2025-06-22 09:26:43.510881219 +0200
+@@ -184,6 +184,8 @@
+    caps->performance_monitor =
+       pscreen->get_driver_query_info && pscreen->get_driver_query_group_info &&
+       pscreen->get_driver_query_group_info(pscreen, 0, NULL) != 0;
++
++   caps->y_flip = true;
+ }
+
+ uint64_t u_default_get_timestamp(UNUSED struct pipe_screen *screen)
+diff -ruPN mesa-25.1.3/src/gallium/drivers/lima/ir/pp/lower.c mesa-new/src/gallium/drivers/lima/ir/pp/lower.c
+--- mesa-25.1.3/src/gallium/drivers/lima/ir/pp/lower.c	2025-06-07 15:47:15.000000000 +0200
++++ mesa-new/src/gallium/drivers/lima/ir/pp/lower.c	2025-06-22 09:10:11.806922924 +0200
+@@ -147,13 +147,10 @@
+    assert(node->type == ppir_node_type_alu);
+    ppir_alu_node *alu = ppir_node_to_alu(node);
+
++   /* Follow the binary driver behavior which adds the negated
++    * argument as a second src to ddx/ddy */
+    alu->src[1] = alu->src[0];
+-   if (node->op == ppir_op_ddx)
+-      alu->src[1].negate = !alu->src[1].negate;
+-   else if (node->op == ppir_op_ddy)
+-      alu->src[0].negate = !alu->src[0].negate;
+-   else
+-      assert(0);
++   alu->src[1].negate = !alu->src[1].negate;
+
+    alu->num_src = 2;
+
+diff -ruPN mesa-25.1.3/src/gallium/drivers/lima/lima_job.c mesa-new/src/gallium/drivers/lima/lima_job.c
+--- mesa-25.1.3/src/gallium/drivers/lima/lima_job.c	2025-06-07 15:47:15.000000000 +0200
++++ mesa-new/src/gallium/drivers/lima/lima_job.c	2025-06-22 09:18:20.331902380 +0200
+@@ -63,14 +63,15 @@
+    if (!surf) {
+       /* We don't have neither cbuf nor zsbuf, use dimensions from ctx */
+       fb->width = ctx->framebuffer.base.width;
+-      fb->height =  ctx->framebuffer.base.height;
++      fb->height =  ctx->framebuffer.base.height;
+    } else {
+       uint16_t width, height;
+       pipe_surface_size(&surf->base, &width, &height);
+       fb->width = width;
+       fb->height = height;
+    }
+-
++
++   fb->flip_y = ctx->framebuffer.base.flip_y;
+    int width = align(fb->width, 16) >> 4;
+    int height = align(fb->height, 16) >> 4;
+
+@@ -839,11 +840,26 @@
+    frame->fragment_stack_size = job->pp_max_stack_size << 16 | job->pp_max_stack_size;
+
+    /* related with MSAA and different value when r4p0/r7p0 */
+-   frame->supersampled_height = fb->height * 2 - 1;
+-   frame->scale = 0xE0C;
++   if (fb->flip_y)
++      frame->supersampled_height = fb->height * 2 - 1;
++   else
++      frame->supersampled_height = 1;
++
++   frame->scale = 0x00C;
++   if (fb->flip_y) {
++      /* 11: flip derivative y
++       * 10: flip fragcoord y
++       *  9: flip dithering */
++      frame->scale |= (1<<11) | (1<<10) | (1<<9);
++   }
+
+    frame->dubya = 0x77;
+-   frame->onscreen = 1;
++
++   if (fb->flip_y)
++      frame->onscreen = 1;
++   else
++      frame->onscreen = 0;
++
+    frame->blocking = (fb->shift_min << 28) | (fb->shift_h << 16) | fb->shift_w;
+
+    /* Set default layout to 8888 */
+diff -ruPN mesa-25.1.3/src/gallium/drivers/lima/lima_job.h mesa-new/src/gallium/drivers/lima/lima_job.h
+--- mesa-25.1.3/src/gallium/drivers/lima/lima_job.h	2025-06-07 15:47:15.000000000 +0200
++++ mesa-new/src/gallium/drivers/lima/lima_job.h	2025-06-22 09:15:11.116910337 +0200
+@@ -57,6 +57,7 @@
+    int shift_w, shift_h;
+    int block_w, block_h;
+    int shift_min;
++   int flip_y;
+ };
+
+ struct lima_job {
+diff -ruPN mesa-25.1.3/src/gallium/drivers/lima/lima_screen.c mesa-new/src/gallium/drivers/lima/lima_screen.c
+--- mesa-25.1.3/src/gallium/drivers/lima/lima_screen.c	2025-06-07 15:47:15.000000000 +0200
++++ mesa-new/src/gallium/drivers/lima/lima_screen.c	2025-06-22 09:26:49.823880954 +0200
+@@ -212,6 +212,7 @@
+    caps->max_texture_anisotropy = 16.0f;
+
+    caps->max_texture_lod_bias = 15.0f;
++   caps->y_flip = false;
+ }
+
+ static bool
+diff -ruPN mesa-25.1.3/src/gallium/include/pipe/p_defines.h mesa-new/src/gallium/include/pipe/p_defines.h
+--- mesa-25.1.3/src/gallium/include/pipe/p_defines.h	2025-06-07 15:47:15.000000000 +0200
++++ mesa-new/src/gallium/include/pipe/p_defines.h	2025-06-22 09:26:34.999881577 +0200
+@@ -1112,6 +1112,7 @@
+    float min_conservative_raster_dilate;
+    float max_conservative_raster_dilate;
+    float conservative_raster_dilate_granularity;
++   bool y_flip;
+ };
+
+ /**
+diff -ruPN mesa-25.1.3/src/gallium/include/pipe/p_state.h mesa-new/src/gallium/include/pipe/p_state.h
+--- mesa-25.1.3/src/gallium/include/pipe/p_state.h	2025-06-07 15:47:15.000000000 +0200
++++ mesa-new/src/gallium/include/pipe/p_state.h	2025-06-22 09:20:24.527897157 +0200
+@@ -418,7 +418,7 @@
+    struct pipe_surface *cbufs[PIPE_MAX_COLOR_BUFS];
+
+    struct pipe_surface *zsbuf;      /**< Z/stencil buffer */
+-
++   bool flip_y; /**< Flip Y coordinates (fragcoord, derivatives, etc) */
+    struct pipe_resource *resolve;
+ };
+
+diff -ruPN mesa-25.1.3/src/mesa/state_tracker/st_atom_framebuffer.c mesa-new/src/mesa/state_tracker/st_atom_framebuffer.c
+--- mesa-25.1.3/src/mesa/state_tracker/st_atom_framebuffer.c	2025-06-07 15:47:15.000000000 +0200
++++ mesa-new/src/mesa/state_tracker/st_atom_framebuffer.c	2025-06-22 09:21:43.270893845 +0200
+@@ -225,6 +225,8 @@
+    if (framebuffer.height == USHRT_MAX)
+       framebuffer.height = 0;
+
++   framebuffer.flip_y = fb->FlipY;
++
+    cso_set_framebuffer(st->cso_context, &framebuffer);
+
+    st->state.fb_width = framebuffer.width;
+diff -ruPN mesa-25.1.3/src/mesa/state_tracker/st_program.c mesa-new/src/mesa/state_tracker/st_program.c
+--- mesa-25.1.3/src/mesa/state_tracker/st_program.c	2025-06-07 15:47:15.000000000 +0200
++++ mesa-new/src/mesa/state_tracker/st_program.c	2025-06-22 09:29:23.604874487 +0200
+@@ -355,7 +355,9 @@
+    NIR_PASS(_, nir, nir_lower_reg_intrinsics_to_ssa);
+    nir_validate_shader(nir, "after st/ptn lower_reg_intrinsics_to_ssa");
+
+-   NIR_PASS(_, nir, st_nir_lower_wpos_ytransform, prog, screen);
++   if (screen->caps.y_flip) {
++	NIR_PASS(_, nir, st_nir_lower_wpos_ytransform, prog, screen);
++   }
+    NIR_PASS(_, nir, nir_lower_system_values);
+
+    struct nir_lower_compute_system_values_options cs_options = {
diff --git a/projects/Rockchip/devices/RK322X/packages/mesa/patches/0002-lima-encodeconstant-lod-bias-in-the-texture-instruction.patch b/projects/Rockchip/devices/RK322X/packages/mesa/patches/0002-lima-encodeconstant-lod-bias-in-the-texture-instruction.patch
new file mode 100644
index 0000000000..9b313fb397
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/packages/mesa/patches/0002-lima-encodeconstant-lod-bias-in-the-texture-instruction.patch
@@ -0,0 +1,168 @@
+From e6af6844af22f0807add87c89b36713857c7f596 Mon Sep 17 00:00:00 2001
+From: sarbes <sarbes@kodi.tv>
+Date: Thu, 17 Apr 2025 15:13:59 +0200
+Subject: [PATCH] lima: encode constant lod/bias in the texture instruction
+
+Encoding the constant in the texture instruction avoids loading the constant, and potentially saves one cycle.
+---
+ src/gallium/drivers/lima/ir/pp/codegen.c | 18 +++--------------
+ src/gallium/drivers/lima/ir/pp/codegen.h | 25 ++++++++++--------------
+ src/gallium/drivers/lima/ir/pp/disasm.c  | 15 +++-----------
+ src/gallium/drivers/lima/ir/pp/nir.c     | 23 +++++++++++++++-------
+ src/gallium/drivers/lima/ir/pp/ppir.h    |  3 ++-
+ 5 files changed, 34 insertions(+), 50 deletions(-)
+
+diff --git a/src/gallium/drivers/lima/ir/pp/codegen.c b/src/gallium/drivers/lima/ir/pp/codegen.c
+index 3d6db737915ba..047d8cafce586 100644
+--- a/src/gallium/drivers/lima/ir/pp/codegen.c
++++ b/src/gallium/drivers/lima/ir/pp/codegen.c
+@@ -149,24 +149,12 @@ static void ppir_codegen_encode_texld(ppir_node *node, void *code)
+
+    f->index = ldtex->sampler;
+
+-   f->lod_bias_en = ldtex->lod_bias_en;
++   f->lod_bias_register = ldtex->lod_bias_register;
+    f->explicit_lod = ldtex->explicit_lod;
+-   if (ldtex->lod_bias_en)
++   if (ldtex->lod_bias_register)
+       f->lod_bias = ppir_target_get_src_reg_index(&ldtex->src[1]);
+
+-   switch (ldtex->sampler_dim) {
+-   case GLSL_SAMPLER_DIM_2D:
+-   case GLSL_SAMPLER_DIM_3D:
+-   case GLSL_SAMPLER_DIM_RECT:
+-   case GLSL_SAMPLER_DIM_EXTERNAL:
+-      f->type = ppir_codegen_sampler_type_generic;
+-      break;
+-   case GLSL_SAMPLER_DIM_CUBE:
+-      f->type = ppir_codegen_sampler_type_cube;
+-      break;
+-   default:
+-      break;
+-   }
++   f->constant_lod_bias = ldtex->constant_lod_bias * 16.f;
+
+    f->offset_en = 0;
+    f->unknown_2 = 0x39001;
+diff --git a/src/gallium/drivers/lima/ir/pp/codegen.h b/src/gallium/drivers/lima/ir/pp/codegen.h
+index 055e952f5fc06..b4eece779d7e8 100644
+--- a/src/gallium/drivers/lima/ir/pp/codegen.h
++++ b/src/gallium/drivers/lima/ir/pp/codegen.h
+@@ -103,22 +103,17 @@ typedef union __attribute__((__packed__)) {
+    } reg;
+ } ppir_codegen_field_varying;
+
+-typedef enum {
+-   ppir_codegen_sampler_type_generic = 0x00,
+-   ppir_codegen_sampler_type_cube    = 0x1F,
+-} ppir_codegen_sampler_type;
+-
+ typedef struct __attribute__((__packed__)) {
+-   unsigned                  lod_bias     :  6;
+-   unsigned                  index_offset :  6;
+-   unsigned                  unknown_0    :  5; /* = 00000 */
+-   bool                      explicit_lod :  1;
+-   bool                      lod_bias_en  :  1;
+-   unsigned                  unknown_1    :  5; /* = 00000 */
+-   ppir_codegen_sampler_type type         :  5;
+-   bool                      offset_en    :  1;
+-   unsigned                  index        : 12;
+-   unsigned                  unknown_2    : 20; /* = 0011 1001 0000 0000 0001 */
++   unsigned lod_bias          :  6;
++   unsigned index_offset      :  6;
++   unsigned unknown_0         :  5; /* = 00000 */
++   bool     explicit_lod      :  1;
++   bool     lod_bias_register :  1;
++   unsigned unknown_1         :  1; /* = 0 */
++   signed   constant_lod_bias :  9;
++   bool     offset_en         :  1;
++   unsigned index             : 12;
++   unsigned unknown_2         : 20; /* = 0011 1001 0000 0000 0001 */
+ } ppir_codegen_field_sampler;
+
+ typedef enum {
+diff --git a/src/gallium/drivers/lima/ir/pp/disasm.c b/src/gallium/drivers/lima/ir/pp/disasm.c
+index 7bf62384c1595..f84acc311b095 100644
+--- a/src/gallium/drivers/lima/ir/pp/disasm.c
++++ b/src/gallium/drivers/lima/ir/pp/disasm.c
+@@ -281,19 +281,10 @@ print_sampler(void *code, unsigned offset, FILE *fp)
+    ppir_codegen_field_sampler *sampler = code;
+
+    fprintf(fp, "texld");
+-   if (sampler->lod_bias_en)
++   if (sampler->lod_bias_register)
+       fprintf(fp, ".b");
+
+-   switch (sampler->type) {
+-   case ppir_codegen_sampler_type_generic:
+-      break;
+-   case ppir_codegen_sampler_type_cube:
+-      fprintf(fp, ".cube");
+-      break;
+-   default:
+-      fprintf(fp, "_t%u", sampler->type);
+-      break;
+-   }
++   fprintf(fp, " bias%03x", sampler->constant_lod_bias & 0x1ff);
+
+    fprintf(fp, " %u", sampler->index);
+
+@@ -303,7 +294,7 @@ print_sampler(void *code, unsigned offset, FILE *fp)
+       print_source_scalar(sampler->index_offset, NULL, false, false, fp);
+    }
+
+-   if (sampler->lod_bias_en)
++   if (sampler->lod_bias_register)
+    {
+       fprintf(fp, " ");
+       print_source_scalar(sampler->lod_bias, NULL, false, false, fp);
+diff --git a/src/gallium/drivers/lima/ir/pp/nir.c b/src/gallium/drivers/lima/ir/pp/nir.c
+index edebab28167c6..f7c75193384eb 100644
+--- a/src/gallium/drivers/lima/ir/pp/nir.c
++++ b/src/gallium/drivers/lima/ir/pp/nir.c
+@@ -614,13 +614,22 @@ static bool ppir_emit_tex(ppir_block *block, nir_instr *ni)
+          node->num_src++;
+          break;
+       }
+-      case nir_tex_src_bias:
+-      case nir_tex_src_lod:
+-         node->lod_bias_en = true;
+-         node->explicit_lod = (instr->src[i].src_type == nir_tex_src_lod);
+-         ppir_node_add_src(block->comp, &node->node, &node->src[1], &instr->src[i].src, 1);
+-         node->num_src++;
+-         break;
++         case nir_tex_src_lod:
++            node->explicit_lod = true;
++            FALLTHROUGH;
++         case nir_tex_src_bias:
++            // the hardware seems to be able to do "texture2D(sampler, uv, 1.23 + bias)" as well
++            if (nir_src_is_const(instr->src[i].src) && instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE)
++               node->constant_lod_bias = nir_src_as_float(instr->src[i].src);
++            else {
++               node->lod_bias_register = true;
++               ppir_node_add_src(block->comp, &node->node, &node->src[1], &instr->src[i].src, 1);
++               node->num_src++;
++               // for whatever reason, the blob biases cubemaps
++               if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && instr->src[i].src_type == nir_tex_src_bias)
++                  node->constant_lod_bias = -1.0f;
++            }
++            break;
+       default:
+          ppir_error("unsupported texture source type\n");
+          return false;
+diff --git a/src/gallium/drivers/lima/ir/pp/ppir.h b/src/gallium/drivers/lima/ir/pp/ppir.h
+index ee4e49ae77c23..d91befc7d00bb 100644
+--- a/src/gallium/drivers/lima/ir/pp/ppir.h
++++ b/src/gallium/drivers/lima/ir/pp/ppir.h
+@@ -346,7 +346,8 @@ typedef struct {
+    int num_src;
+    int sampler;
+    int sampler_dim;
+-   bool lod_bias_en;
++   float constant_lod_bias;
++   bool lod_bias_register;
+    bool explicit_lod;
+ } ppir_load_texture_node;
+
+--
+GitLab
diff --git a/projects/Rockchip/devices/RK322X/packages/mesa/patches/0003-lima-encode-constant-scalar-multiplier-in-the-mul-add.patch b/projects/Rockchip/devices/RK322X/packages/mesa/patches/0003-lima-encode-constant-scalar-multiplier-in-the-mul-add.patch
new file mode 100644
index 0000000000..63cee5f04d
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/packages/mesa/patches/0003-lima-encode-constant-scalar-multiplier-in-the-mul-add.patch
@@ -0,0 +1,206 @@
+From 657bd9b8f9c747b61dff9b9be84e19c1f684210f Mon Sep 17 00:00:00 2001
+From: sarbes <sarbes@kodi.tv>
+Date: Sun, 27 Apr 2025 22:57:15 +0200
+Subject: [PATCH] lima: encode constant scalar multiplier in the mul/add
+ instruction
+
+Utgard GPUs can encode a few selected scalar multipliers in the mul/add instruction. When applicable, it saves a mul and a load.
+
+v2:
+- fix mistake with the vec4 adder
+v3:
+- removed x16 modifier
+v4:
+- move shift to ppir_dest
+- prevent emmision of combine alu if shift is present
+---
+ src/gallium/drivers/lima/ir/pp/codegen.c | 10 +--
+ src/gallium/drivers/lima/ir/pp/instr.c   |  4 +-
+ src/gallium/drivers/lima/ir/pp/lower.c   | 80 ++++++++++++++++++++++++
+ src/gallium/drivers/lima/ir/pp/ppir.h    |  2 +-
+ 4 files changed, 88 insertions(+), 8 deletions(-)
+
+diff --git a/src/gallium/drivers/lima/ir/pp/codegen.c b/src/gallium/drivers/lima/ir/pp/codegen.c
+index 3d6db737915ba..3e266a4db0060 100644
+--- a/src/gallium/drivers/lima/ir/pp/codegen.c
++++ b/src/gallium/drivers/lima/ir/pp/codegen.c
+@@ -217,7 +217,7 @@ static ppir_codegen_outmod ppir_codegen_get_outmod(ppir_outmod outmod)
+ static unsigned shift_to_op(int shift)
+ {
+    assert(shift >= -3 && shift <= 3);
+-   return shift < 0 ? shift + 8 : shift;
++   return shift & 0x7;
+ }
+
+ static void ppir_codegen_encode_vec_mul(ppir_node *node, void *code)
+@@ -240,7 +240,7 @@ static void ppir_codegen_encode_vec_mul(ppir_node *node, void *code)
+
+    switch (node->op) {
+    case ppir_op_mul:
+-      f->op = shift_to_op(alu->shift);
++      f->op = shift_to_op(dest->shift);
+       break;
+    case ppir_op_mov:
+       f->op = ppir_codegen_vec4_mul_op_mov;
+@@ -316,7 +316,7 @@ static void ppir_codegen_encode_scl_mul(ppir_node *node, void *code)
+
+    switch (node->op) {
+    case ppir_op_mul:
+-      f->op = shift_to_op(alu->shift);
++      f->op = shift_to_op(dest->shift);
+       break;
+    case ppir_op_mov:
+       f->op = ppir_codegen_float_mul_op_mov;
+@@ -383,7 +383,7 @@ static void ppir_codegen_encode_vec_add(ppir_node *node, void *code)
+
+    switch (node->op) {
+    case ppir_op_add:
+-      f->op = ppir_codegen_vec4_acc_op_add;
++      f->op = shift_to_op(dest->shift);
+       break;
+    case ppir_op_mov:
+       f->op = ppir_codegen_vec4_acc_op_mov;
+@@ -473,7 +473,7 @@ static void ppir_codegen_encode_scl_add(ppir_node *node, void *code)
+
+    switch (node->op) {
+    case ppir_op_add:
+-      f->op = shift_to_op(alu->shift);
++      f->op = shift_to_op(dest->shift);
+       break;
+    case ppir_op_mov:
+       f->op = ppir_codegen_float_acc_op_mov;
+diff --git a/src/gallium/drivers/lima/ir/pp/instr.c b/src/gallium/drivers/lima/ir/pp/instr.c
+index 0befd2cd21af1..72ffc3a9a99ab 100644
+--- a/src/gallium/drivers/lima/ir/pp/instr.c
++++ b/src/gallium/drivers/lima/ir/pp/instr.c
+@@ -349,8 +349,8 @@ bool ppir_instr_insert_node(ppir_instr *instr, ppir_node *node)
+             if (dest->type == ppir_target_pipeline)
+                continue;
+
+-            /* No modifiers on vector output */
+-            if (node->op == ppir_op_mul && dest->modifier != ppir_outmod_none)
++            /* No modifiers/shift on vector output */
++            if (node->op == ppir_op_mul && (dest->modifier != ppir_outmod_none || dest->shift != 0))
+                continue;
+
+             /* No modifiers on vector source on combiner */
+diff --git a/src/gallium/drivers/lima/ir/pp/lower.c b/src/gallium/drivers/lima/ir/pp/lower.c
+index 8315b934795fc..c02c7a47de7bf 100644
+--- a/src/gallium/drivers/lima/ir/pp/lower.c
++++ b/src/gallium/drivers/lima/ir/pp/lower.c
+@@ -663,6 +663,85 @@ static bool ppir_lower_accum(ppir_block *block, ppir_node *node)
+    return true;
+ }
+
++static bool ppir_lower_fold_const_scalar_mul(ppir_block *block, ppir_node *node)
++{
++   /* add and mul instructions can encode a limited selection of scalar
++    * constants and multiply them in situe. E.g. (src[0] + src[1]) * 2. */
++   ppir_alu_node* alu_node = NULL;
++   ppir_const_node* const_node = NULL;
++
++   ppir_node_foreach_pred_safe(node, dep) {
++      ppir_node *p = dep->pred;
++      if (p->type == ppir_node_type_const)
++         const_node = ppir_node_to_const(p);
++      else if (p->type == ppir_node_type_alu)
++         alu_node = ppir_node_to_alu(p);
++   }
++
++   if (!alu_node || !const_node)
++      return false;
++
++   if (alu_node->node.op != ppir_op_add && alu_node->node.op != ppir_op_mul)
++      return false;
++
++   if (!ppir_node_has_single_succ(&alu_node->node))
++      return false;
++
++   // ppir_outmod_clamp_positive should be fine: max(x*n,0) == max(x,0)*n; for n >= 0
++   if (alu_node->dest.modifier == ppir_outmod_clamp_fraction || alu_node->dest.modifier == ppir_outmod_round)
++      return false;
++
++   if (const_node->constant.num != 1)
++      return false;
++
++   float scalar = const_node->constant.value[0].f;
++
++   if (scalar == 2.0f)
++      alu_node->dest.shift = 1;
++   else if (scalar == 4.0f)
++      alu_node->dest.shift = 2;
++   else if (scalar == 8.0f)
++      alu_node->dest.shift = 3;
++   else if (scalar == 1.0f/2.0f)
++      alu_node->dest.shift = -1;
++   else if (scalar == 1.0f/4.0f)
++      alu_node->dest.shift = -2;
++   else if (scalar == 1.0f/8.0f)
++      alu_node->dest.shift = -3;
++   else {
++      alu_node->dest.shift = 0;
++      return false;
++   }
++
++   alu_node->node.is_out |= node->is_out;
++
++   ppir_dest dest = ppir_node_to_alu(node)->dest;
++   if (!(alu_node->node.op == ppir_op_add && dest.type == ppir_target_pipeline))
++      alu_node->dest = dest;
++
++   ppir_node_replace_all_succ(&alu_node->node, node);
++
++   /* for all nodes after the scalar mul node */
++   ppir_node_foreach_succ_safe(node, dep) {
++      /* replace the scalar mul node with the pred alu */
++      ppir_node *p = dep->succ;
++      ppir_node_remove_dep(dep);
++      ppir_node_add_dep(p, &alu_node->node, ppir_dep_src);
++   }
++
++   ppir_node_delete(node);
++   ppir_node_delete(&const_node->node);
++
++   return true;
++}
++
++static bool ppir_lower_mul(ppir_block *block, ppir_node *node)
++{
++   /* check if we can fold a constant scalar */
++   ppir_lower_fold_const_scalar_mul(block, node);
++   return true;
++}
++
+ static bool (*ppir_lower_funcs[ppir_op_num])(ppir_block *, ppir_node *) = {
+    [ppir_op_abs] = ppir_lower_abs,
+    [ppir_op_neg] = ppir_lower_neg,
+@@ -684,6 +763,7 @@ static bool (*ppir_lower_funcs[ppir_op_num])(ppir_block *, ppir_node *) = {
+    [ppir_op_min] = ppir_lower_accum,
+    [ppir_op_eq] = ppir_lower_accum,
+    [ppir_op_ne] = ppir_lower_accum,
++   [ppir_op_mul] = ppir_lower_mul,
+ };
+
+ bool ppir_lower_prog(ppir_compiler *comp)
+diff --git a/src/gallium/drivers/lima/ir/pp/ppir.h b/src/gallium/drivers/lima/ir/pp/ppir.h
+index ee4e49ae77c23..083f9a148e69f 100644
+--- a/src/gallium/drivers/lima/ir/pp/ppir.h
++++ b/src/gallium/drivers/lima/ir/pp/ppir.h
+@@ -294,6 +294,7 @@ typedef struct ppir_dest {
+
+    ppir_outmod modifier;
+    unsigned write_mask : 4;
++   int shift;
+ } ppir_dest;
+
+ typedef struct {
+@@ -301,7 +302,6 @@ typedef struct {
+    ppir_dest dest;
+    ppir_src src[3];
+    int num_src;
+-   int shift : 3; /* Only used for ppir_op_mul */
+ } ppir_alu_node;
+
+ typedef struct ppir_const {
+--
+GitLab
diff --git a/projects/Rockchip/devices/RK322X/packages/ncurses/package.mk b/projects/Rockchip/devices/RK322X/packages/ncurses/package.mk
new file mode 100644
index 0000000000..0317d62d1c
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/packages/ncurses/package.mk
@@ -0,0 +1,92 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Copyright (C) 2009-2016 Stephan Raue (stephan@openelec.tv)
+# Copyright (C) 2017-present Team LibreELEC (https://libreelec.tv)
+
+PKG_NAME="ncurses"
+PKG_VERSION="6.5-20250517"
+PKG_SHA256="13e78548b31adef93e3b9735bf728fac5a84969873333c7833614db61891353e"
+PKG_LICENSE="MIT"
+PKG_SITE="http://www.gnu.org/software/ncurses/"
+PKG_URL="http://invisible-mirror.net/archives/ncurses/current/ncurses-${PKG_VERSION}.tgz"
+PKG_DEPENDS_HOST="ccache:host"
+PKG_DEPENDS_TARGET="autotools:host gcc:host zlib ncurses:host"
+PKG_LONGDESC="A library is a free software emulation of curses in System V Release 4.0, and more."
+PKG_BUILD_FLAGS="+pic"
+
+PKG_CONFIGURE_OPTS_TARGET="--without-ada \
+                           --without-cxx \
+                           --without-cxx-binding \
+                           --disable-db-install \
+                           --without-manpages \
+                           --without-progs \
+                           --without-tests \
+                           --without-shared \
+                           --with-normal \
+                           --without-debug \
+                           --without-profile \
+                           --without-termlib \
+                           --without-ticlib \
+                           --without-gpm \
+                           --without-dbmalloc \
+                           --without-dmalloc \
+                           --disable-rpath \
+                           --disable-database \
+                           --with-fallbacks=linux,screen,xterm,xterm-color,dumb,st-256color \
+                           --with-termpath=/storage/.config/termcap \
+                           --disable-big-core \
+                           --enable-termcap \
+                           --enable-getcap \
+                           --disable-getcap-cache \
+                           --enable-symlinks \
+                           --disable-bsdpad \
+                           --without-rcs-ids \
+                           --enable-ext-funcs \
+                           --disable-const \
+                           --enable-no-padding \
+                           --disable-sigwinch \
+                           --enable-pc-files \
+                           --with-pkg-config-libdir=/usr/lib/pkgconfig \
+                           --disable-tcap-names \
+                           --without-develop \
+                           --disable-hard-tabs \
+                           --disable-xmc-glitch \
+                           --enable-hashmap \
+                           --disable-safe-sprintf \
+                           --disable-scroll-hints \
+                           --enable-widec \
+                           --disable-echo \
+                           --disable-warnings \
+                           --disable-home-terminfo \
+                           --disable-assertions \
+                           --enable-leaks \
+                           --enable-sigwinch \
+                           --cache-file=config.cache"
+
+PKG_CONFIGURE_OPTS_HOST="--enable-termcap \
+                         --with-termlib \
+                         --with-shared \
+                         --enable-pc-files \
+                         --without-manpages"
+
+pre_configure_target() {
+  cat >config.cache <<EOF
+cf_cv_builtin_bool=yes
+cf_cv_header_stdbool_h=yes
+EOF
+}
+
+post_makeinstall_target() {
+  local f
+  cp misc/ncurses-config ${TOOLCHAIN}/bin
+  chmod +x ${TOOLCHAIN}/bin/ncurses-config
+  sed -e "s:\(['=\" ]\)/usr:\\1${PKG_ORIG_SYSROOT_PREFIX}/usr:g" -i ${TOOLCHAIN}/bin/ncurses-config
+  rm -f ${TOOLCHAIN}/bin/ncurses6-config
+  rm -rf ${INSTALL}/usr/bin
+  # create links to be compatible with any ncurses include path and lib names
+  ln -sf . ${SYSROOT_PREFIX}/usr/include/ncursesw
+  ln -sf . ${SYSROOT_PREFIX}/usr/include/ncurses
+  for f in form menu ncurses panel; do
+    ln -sf lib${f}w.a ${SYSROOT_PREFIX}/usr/lib/lib${f}.a
+    ln -sf ${f}w.pc ${SYSROOT_PREFIX}/usr/lib/pkgconfig/${f}.pc
+  done
+}
diff --git a/projects/Rockchip/devices/RK322X/packages/ncurses/patches/ncurses-001-terminfo-xterm.patch b/projects/Rockchip/devices/RK322X/packages/ncurses/patches/ncurses-001-terminfo-xterm.patch
new file mode 100644
index 0000000000..9a648a2ea0
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/packages/ncurses/patches/ncurses-001-terminfo-xterm.patch
@@ -0,0 +1,18 @@
+
+Remove recent xterm terminfo features to be compatible with other emulations
+
+--- a/misc/terminfo.src	2021-03-20 22:45:39.000000000 +0100
++++ b/misc/terminfo.src	2021-06-01 23:53:10.335516419 +0200
+@@ -4946,9 +4946,9 @@ xterm-xfree86|xterm terminal emulator (X
+
+ xterm+nofkeys|building block for xterm fkey-variants,
+	npc,
+-	kcbt=\E[Z, nel=\EE, use=ecma+index, use=ansi+rep,
+-	use=ecma+strikeout, use=vt420+lrmm, use=xterm+focus,
+-	use=xterm+sm+1006, use=xterm+tmux, use=ecma+italics,
++	kcbt=\E[Z, nel=\EE, use=ecma+index,
++	use=ecma+strikeout, use=vt420+lrmm,
++	use=xterm+sm+1005, use=xterm+tmux, use=ecma+italics,
+	use=xterm+keypad, use=xterm-basic,
+
+ xterm-p370|xterm patch #370,
diff --git a/projects/Rockchip/devices/RK322X/packages/ncurses/patches/ncurses-002-alloc-fallbacks.patch b/projects/Rockchip/devices/RK322X/packages/ncurses/patches/ncurses-002-alloc-fallbacks.patch
new file mode 100644
index 0000000000..e764bf5b66
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/packages/ncurses/patches/ncurses-002-alloc-fallbacks.patch
@@ -0,0 +1,13 @@
+Fix freeing not allocated fallback entries by allocating a copy.
+
+--- a/ncurses/tinfo/tinfo_driver.c	2018-11-24 23:17:03.000000000 +0100
++++ b/ncurses/tinfo/tinfo_driver.c	2018-12-29 10:27:19.000000000 +0100
+@@ -180,6 +180,8 @@ drv_CanHandle(TERMINAL_CONTROL_BLOCK * T
+     if (status != TGETENT_YES) {
+	const TERMTYPE2 *fallback = _nc_fallback2(tname);
+
++	if (fallback)
++            fallback = _nc_copy_entry(fallback);
+	if (fallback) {
+	    T(("found fallback entry"));
+	    TerminalType(termp) = *fallback;
diff --git a/projects/Rockchip/devices/RK322X/packages/ncurses/patches/ncurses-004-fix_configure_pkgconfig.patch b/projects/Rockchip/devices/RK322X/packages/ncurses/patches/ncurses-004-fix_configure_pkgconfig.patch
new file mode 100644
index 0000000000..2edaefec1c
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/packages/ncurses/patches/ncurses-004-fix_configure_pkgconfig.patch
@@ -0,0 +1,13 @@
+Fix configure option --with-pkg-config-libdir is broken for cross compilation
+
+--- a/configure	2021-10-17 17:12:23.000000000 +0200
++++ b/configure	2021-11-26 00:27:00.224815736 +0100
+@@ -4255,7 +4255,7 @@ echo $ECHO_N "checking for first directo
+	cf_pkg_config_path=none
+	for cf_config in $cf_search_path
+	do
+-		if test -d "$cf_config"
++		if test -n "$cf_config"
+		then
+			cf_pkg_config_path=$cf_config
+			break
diff --git a/projects/Rockchip/devices/RK322X/packages/openvfd-driver/openvfd.conf.d/hc4.conf b/projects/Rockchip/devices/RK322X/packages/openvfd-driver/openvfd.conf.d/hc4.conf
new file mode 100644
index 0000000000..b7d3e14f89
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/packages/openvfd-driver/openvfd.conf.d/hc4.conf
@@ -0,0 +1,7 @@
+vfd_gpio_clk='0,0,0xFF'
+vfd_gpio_dat='0,0,0xFF'
+vfd_gpio_stb='0,0,0xFF'
+vfd_gpio_protocol='1,2'
+vfd_chars='0,1,2,3,4'
+vfd_dot_bits='0,1,2,3,4,5,6'
+vfd_display_type='0x3F,0x3C,0x20,0xFD'
diff --git a/projects/Rockchip/devices/RK322X/packages/openvfd-driver/openvfd.conf.d/t95d.conf b/projects/Rockchip/devices/RK322X/packages/openvfd-driver/openvfd.conf.d/t95d.conf
new file mode 100644
index 0000000000..39d931dbcd
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/packages/openvfd-driver/openvfd.conf.d/t95d.conf
@@ -0,0 +1,34 @@
+# This file must be renamed to vfd.conf and placed in the /storage/.config/ folder.
+#
+# Mini One configuration
+#--------------------
+#gpio_xxx:
+# [0] 2 = &gpio0, 3 = &gpio1, 4 = &gpio2, 5 = &gpio3.
+# [1] pin number.
+# [2] Reserved - must be 0.
+
+vfd_gpio_clk='2,2,0'
+vfd_gpio_dat='2,1,0'
+vfd_gpio_stb='2,0,0'
+
+#chars:
+# < DHHMM > Order of display chars (D=dots, represented by a single char)
+vfd_chars='0,1,2,3,4'
+
+#dot_bits:
+# Order of dot bits. Typical configurations:
+# Display Type 0, 1 usually has Alarm, USB, Play, Pause, Col, Ethernet, Wifi dots
+# Alarm = 0, USB = 1, Play = 2, Pause = 3, Col = 4, Eth = 5, Wifi = 6
+# Display Type 2 usually has APPS, USB, SETUP, CARD, Col, HDMI, CVBS dots
+# APPS = 0, USB = 1, SETUP = 2, CARD = 3, Col = 4, HDMI = 5, CVBS = 6
+# Display Type 3 Power, LAN, Col, Low Wifi, High Wifi
+# N/A = 0, N/A = 1, Power = 2, LAN = 3, Col = 4, Low Wifi = 5, High Wifi = 6
+# Display Type 5 - Col = 2
+vfd_dot_bits='0,1,2,3,4,5,6'
+
+#display_type:
+# [0] - Display type.
+# [1] - Reserved - must be 0.
+# [2] - Flags. (bit 0 = '1' - Common Anode display, bits [1-7] - Reserved.)
+# [3] - Controller.
+vfd_display_type='0x01,0x00,0x00,0x02'
diff --git a/projects/Rockchip/devices/RK322X/packages/openvfd-driver/package.mk b/projects/Rockchip/devices/RK322X/packages/openvfd-driver/package.mk
new file mode 100644
index 0000000000..9877b61b68
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/packages/openvfd-driver/package.mk
@@ -0,0 +1,45 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Copyright (C) 2018-present Arthur Liberman (arthur_liberman@hotmail.com)
+
+PKG_NAME="openvfd-driver"
+PKG_VERSION="f150d14ffb3b0e47f939b9bc081f398fb852b0eb"
+PKG_SHA256="6cf681feedb764bdd6796e3d8c8cb700e73a0444815b96ea529ef6922f1707e7"
+PKG_LICENSE="GPLv2"
+PKG_SITE="https://github.com/LibreELEC/linux_openvfd"
+PKG_URL="https://github.com/LibreELEC/linux_openvfd/archive/$PKG_VERSION.tar.gz"
+PKG_SOURCE_DIR="linux_openvfd-$PKG_VERSION*"
+PKG_DEPENDS_TARGET="toolchain linux"
+PKG_NEED_UNPACK="$LINUX_DEPENDS"
+PKG_LONGDESC="openvfd-driver: an open source Linux driver for VFD displays"
+PKG_TOOLCHAIN="manual"
+PKG_IS_KERNEL_PKG="yes"
+
+pre_make_target() {
+  unset LDFLAGS
+}
+
+make_target() {
+  make ARCH=$TARGET_KERNEL_ARCH \
+       CROSS_COMPILE=$TARGET_KERNEL_PREFIX \
+       -C "$(kernel_path)" M="$PKG_BUILD/driver"
+
+  make OpenVFDService
+}
+
+makeinstall_target() {
+  mkdir -p $INSTALL/$(get_full_module_dir)/$PKG_NAME
+    find $PKG_BUILD/ -name \*.ko -not -path '*/\.*' -exec cp {} $INSTALL/$(get_full_module_dir)/$PKG_NAME \;
+
+  mkdir -p $INSTALL/usr/sbin
+    cp -P OpenVFDService $INSTALL/usr/sbin
+
+  mkdir -p $INSTALL/usr/libexec/
+    cp $PKG_DIR/scripts/* $INSTALL/usr/libexec/
+
+  mkdir -p $INSTALL/etc/openvfd.conf.d/
+    cp $PKG_DIR/openvfd.conf.d/* $INSTALL/etc/openvfd.conf.d/
+}
+
+post_install() {
+  enable_service openvfd.service
+}
diff --git a/projects/Rockchip/devices/RK322X/packages/openvfd-driver/patches/0001-remove-pin-flags-in-kernel.patch b/projects/Rockchip/devices/RK322X/packages/openvfd-driver/patches/0001-remove-pin-flags-in-kernel.patch
new file mode 100644
index 0000000000..64212c55ab
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/packages/openvfd-driver/patches/0001-remove-pin-flags-in-kernel.patch
@@ -0,0 +1,26 @@
+From 9264588ba27a964a1e56346202901dd17f9e133d Mon Sep 17 00:00:00 2001
+From: Arthur Liberman <arthur_liberman@hotmail.com>
+Date: Fri, 6 Sep 2024 17:51:36 +0300
+Subject: [PATCH] Remove pin flags in kernel 6.3 Fixes #17
+
+---
+ driver/openvfd_drv.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/driver/openvfd_drv.c b/driver/openvfd_drv.c
+index 48f2b97..fe57d8f 100644
+--- a/driver/openvfd_drv.c
++++ b/driver/openvfd_drv.c
+@@ -709,7 +709,12 @@ static int verify_module_params(struct vfd_dev *dev)
+ void get_pin_from_dt(const char *name, const struct platform_device *pdev, struct vfd_pin *pin)
+ {
+	if (of_find_property(pdev->dev.of_node, name, NULL)) {
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6,3,0))
++		pin->flags.value = 0;
++		pin->pin = of_get_named_gpio(pdev->dev.of_node, name, 0);
++#else
+		pin->pin = of_get_named_gpio_flags(pdev->dev.of_node, name, 0, &pin->flags.value);
++#endif
+		pr_dbg2("%s: pin = %d, flags = 0x%02X\n", name, pin->pin, pin->flags.value);
+	} else {
+		pin->pin = -2;
diff --git a/projects/Rockchip/devices/RK322X/packages/openvfd-driver/patches/0002-fix-compile-6.x-kernels.patch b/projects/Rockchip/devices/RK322X/packages/openvfd-driver/patches/0002-fix-compile-6.x-kernels.patch
new file mode 100644
index 0000000000..e99a5fe9de
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/packages/openvfd-driver/patches/0002-fix-compile-6.x-kernels.patch
@@ -0,0 +1,113 @@
+diff --git a/driver/openvfd_drv.c b/driver/openvfd_drv.c
+index ce9eb7659a..7d000511b6 100644
+--- a/driver/openvfd_drv.c
++++ b/driver/openvfd_drv.c
+@@ -597,6 +597,15 @@ static void print_param_debug(const char *label, int argc, unsigned char param[]
+	pr_dbg2("%s\n", buffer);
+ }
+
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(6,9,0)
++static int is_right_chip(struct gpio_chip *chip, const void *data)
++{
++	pr_dbg("is_right_chip %s | %s | %d\n", chip->label, (const char*)data, strcmp(data, chip->label));
++	if (strcmp((const char *)data, chip->label) == 0)
++		return 1;
++	return 0;
++}
++#else
+ static int is_right_chip(struct gpio_chip *chip, void *data)
+ {
+	pr_dbg("is_right_chip %s | %s | %d\n", chip->label, (char*)data, strcmp(data, chip->label));
+@@ -604,6 +613,41 @@ static int is_right_chip(struct gpio_chip *chip, void *data)
+		return 1;
+	return 0;
+ }
++#endif
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(6,9,0)
++static struct gpio_chip *gpiochip_find(void *data,
++				int (*match)(struct gpio_chip *gc,
++							 const void *data))
++{
++	struct gpio_device *gdev;
++	struct gpio_chip *gc = NULL;
++
++	gdev = gpio_device_find(data, match);
++	if (gdev) {
++		gc = gpio_device_get_chip(gdev);
++		gpio_device_put(gdev);
++	}
++
++	return gc;
++}
++#elif LINUX_VERSION_CODE >= KERNEL_VERSION(6,7,0)
++static struct gpio_chip *gpiochip_find(void *data,
++                int (*match)(struct gpio_chip *gc,
++					         void *data))
++{
++    struct gpio_device *gdev;
++    struct gpio_chip *gc = NULL;
++
++    gdev = gpio_device_find(data, match);
++    if (gdev) {
++        gc = gpio_device_get_chip(gdev);
++        gpio_device_put(gdev);
++    }
++
++    return gc;
++}
++#endif
+
+ static int get_chip_pin_number(const unsigned char gpio[])
+ {
+@@ -646,6 +690,20 @@ int evaluate_pin(const char *name, const unsigned char *vfd_arg, struct vfd_pin
+
+ char gpio_chip_names[1024] = { 0 };
+
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(6,9,0)
++static int enum_gpio_chips(struct gpio_chip *chip, const void *data)
++{
++	static unsigned char first_iteration = 1;
++	const char *sep = ", ";
++	size_t str_len = strlen(gpio_chip_names);
++	if (first_iteration)
++		sep = "";
++	(void)data;
++	scnprintf(gpio_chip_names + str_len, sizeof(gpio_chip_names) - str_len, "%s%s", sep, chip->label);
++	first_iteration = 0;
++	return 0;
++}
++#else
+ static int enum_gpio_chips(struct gpio_chip *chip, void *data)
+ {
+	static unsigned char first_iteration = 1;
+@@ -657,6 +715,7 @@ static int enum_gpio_chips(struct gpio_chip *chip, void *data)
+	first_iteration = 0;
+	return 0;
+ }
++#endif
+
+ static int verify_module_params(struct vfd_dev *dev)
+ {
+@@ -986,7 +986,11 @@ static int openvfd_driver_probe(struct platform_device *pdev)
+	return state;
+ }
+
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(6,11,0)
++static void openvfd_driver_remove(struct platform_device *pdev)
++#else
+ static int openvfd_driver_remove(struct platform_device *pdev)
++#endif
+ {
+	set_power(0);
+ #ifdef CONFIG_HAS_EARLYSUSPEND
+@@ -1013,7 +1017,9 @@ static int openvfd_driver_remove(struct platform_device *pdev)
+	kfree(pdata);
+	pdata = NULL;
+ #endif
++#if LINUX_VERSION_CODE < KERNEL_VERSION(6,10,0)
+	return 0;
++#endif
+ }
+
+ static void openvfd_driver_shutdown(struct platform_device *dev)
diff --git a/projects/Rockchip/devices/RK322X/packages/openvfd-driver/scripts/openvfd-start b/projects/Rockchip/devices/RK322X/packages/openvfd-driver/scripts/openvfd-start
new file mode 100755
index 0000000000..6b45edffc1
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/packages/openvfd-driver/scripts/openvfd-start
@@ -0,0 +1,35 @@
+#!/bin/sh
+
+OSRELEASEFILE="/etc/os-release"
+USRCONFFILE="/storage/.config/vfd.conf"
+SYSCONFDIR="/etc/openvfd.conf.d"
+PROC_DT="/proc/device-tree"
+DT_ID=$(dtname)
+
+case $DT_ID in
+  *t95d*)
+    SYSCONFFILE="$SYSCONFDIR/t95d.conf"
+    ;;
+esac
+
+if [ "$(tr -d '\0' < $PROC_DT/openvfd/compatible)" = "open,vfd" ]; then
+  if [ -f "$USRCONFFILE" ]; then
+    source "$USRCONFFILE"
+  elif [ -f "$SYSCONFFILE" ]; then
+    source "$SYSCONFFILE"
+  else
+    exit 0
+  fi
+
+  /sbin/modprobe openvfd vfd_gpio_clk=${vfd_gpio_clk} \
+                         vfd_gpio_dat=${vfd_gpio_dat} \
+                         vfd_gpio_stb=${vfd_gpio_stb:-0,0,0xFF} \
+                         vfd_gpio0=${vfd_gpio0:-0,0,0xFF} \
+                         vfd_gpio1=${vfd_gpio1:-0,0,0xFF} \
+                         vfd_gpio2=${vfd_gpio2:-0,0,0xFF} \
+                         vfd_gpio3=${vfd_gpio3:-0,0,0xFF} \
+                         vfd_gpio_protocol=${vfd_gpio_protocol:-0,0} \
+                         vfd_chars=${vfd_chars} vfd_dot_bits=${vfd_dot_bits} \
+                         vfd_display_type=${vfd_display_type}
+  /usr/sbin/OpenVFDService ${clock_12h_format:+-12h}
+fi
diff --git a/projects/Rockchip/devices/RK322X/packages/openvfd-driver/system.d/openvfd.service b/projects/Rockchip/devices/RK322X/packages/openvfd-driver/system.d/openvfd.service
new file mode 100644
index 0000000000..9db453f828
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/packages/openvfd-driver/system.d/openvfd.service
@@ -0,0 +1,13 @@
+[Unit]
+Description=OpenVFD Service
+ConditionPathExists=/proc/device-tree/openvfd/
+After=local-fs.target
+
+[Service]
+ExecStart=/usr/libexec/openvfd-start
+ExecStop=/bin/kill -TERM $MAINPID
+ExecStopPost=-/usr/sbin/rmmod openvfd
+RemainAfterExit=yes
+
+[Install]
+WantedBy=basic.target
diff --git a/projects/Rockchip/devices/RK322X/packages/pyyaml/package.mk b/projects/Rockchip/devices/RK322X/packages/pyyaml/package.mk
new file mode 100644
index 0000000000..f4f98be040
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/packages/pyyaml/package.mk
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0-only
+# Copyright (C) 2024-present Team LibreELEC (https://libreelec.tv)
+
+PKG_NAME="pyyaml"
+PKG_VERSION="6.0.2"
+PKG_SHA256="d584d9ec91ad65861cc08d42e834324ef890a082e591037abe114850ff7bbc3e"
+PKG_LICENSE="MIT"
+PKG_SITE="https://pypi.org/project/PyYAML/"
+PKG_URL="https://files.pythonhosted.org/packages/source/${PKG_NAME:0:1}/${PKG_NAME}/${PKG_NAME}-${PKG_VERSION}.tar.gz"
+PKG_DEPENDS_HOST="Python3:host setuptools:host"
+PKG_LONGDESC="YAML parser and emitter for Python"
+PKG_TOOLCHAIN="manual"
+
+makeinstall_host() {
+
+  export DONT_BUILD_LEGACY_PYC=1
+  exec_thread_safe python3 setup.py install --prefix="${TOOLCHAIN}"
+
+}
\ No newline at end of file
diff --git a/projects/Rockchip/devices/RK322X/packages/rkbin/package.mk b/projects/Rockchip/devices/RK322X/packages/rkbin/package.mk
new file mode 100644
index 0000000000..53623e5448
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/packages/rkbin/package.mk
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.
+# Copyright (C) 2017-present Team LibreELEC (https://libreelec.tv)
+
+PKG_NAME="rkbin"
+
+# Version is: knaerzche/tag:libreelec-991d0e4
+PKG_VERSION="84f2356cf510319665874daf29df9ad8a94ac7e4"
+PKG_SHA256="08fe5759ecdb1ee9c51c848c39f3e603f0e4e0b791b79f5c554e4b50c9ddb0a3"
+PKG_ARCH="arm aarch64"
+PKG_LICENSE="nonfree"
+PKG_SITE="https://github.com/rockchip-linux/rkbin"
+PKG_URL="https://github.com/ilmich/rkbin/archive/$PKG_VERSION.tar.gz"
+PKG_LONGDESC="rkbin: Rockchip Firmware and Tool Binaries"
+PKG_TOOLCHAIN="manual"
diff --git a/projects/Rockchip/devices/RK322X/packages/rockchip-firmware/package.mk b/projects/Rockchip/devices/RK322X/packages/rockchip-firmware/package.mk
new file mode 100644
index 0000000000..31e0e0dc94
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/packages/rockchip-firmware/package.mk
@@ -0,0 +1,26 @@
+# SPDX-License-Identifier: GPL-2.0
+# Copyright (C) 2017-present Team LibreELEC (https://libreelec.tv)
+
+PKG_NAME="rockchip-firmware"
+PKG_VERSION="firmware"
+PKG_ARCH="arm aarch64"
+PKG_LICENSE="nonfree"
+PKG_SITE="https://github.com/rockchip-linux"
+PKG_URL=""
+PKG_DEPENDS_TARGET="rkbin"
+PKG_LONGDESC="rockchip firmware"
+PKG_TOOLCHAIN="manual"
+
+makeinstall_target() {
+    mkdir -p $INSTALL/$(get_full_firmware_dir)/{ssv6051,rtl_bt,brcm}
+
+    cp -v $(get_build_dir rkbin)/firmware/wifi/ssv6051-sw.bin $INSTALL/$(get_full_firmware_dir)/
+    cp -v $(get_build_dir rkbin)/firmware/wifi/ssv6051-wifi.cfg $INSTALL/$(get_full_firmware_dir)/
+    cp -v $(get_build_dir rkbin)/firmware/bluetooth/rtl8723cs_xx_config.bin $INSTALL/$(get_full_firmware_dir)/rtl_bt
+    cp -v $(get_build_dir rkbin)/firmware/bluetooth/rtl8723cs_xx_fw.bin $INSTALL/$(get_full_firmware_dir)/rtl_bt
+    cp -v $(get_build_dir rkbin)/firmware/wifi/eagle_fw_ate_config_v19.bin $INSTALL/$(get_full_firmware_dir)/
+    cp -v $(get_build_dir rkbin)/firmware/wifi/eagle_fw_first_init_v19.bin $INSTALL/$(get_full_firmware_dir)/
+    cp -v $(get_build_dir rkbin)/firmware/wifi/eagle_fw_second_init_v19.bin $INSTALL/$(get_full_firmware_dir)/
+    cp -v $(get_build_dir rkbin)/firmware/wifi/brcmfmac43342-sdio.bin $INSTALL/$(get_full_firmware_dir)/brcm/brcmfmac43342-sdio.bin
+    cp -v $(get_build_dir rkbin)/firmware/wifi/brcmfmac43342-sdio.txt $INSTALL/$(get_full_firmware_dir)/brcm/brcmfmac43342-sdio.txt
+}
diff --git a/projects/Rockchip/devices/RK322X/packages/rsync/package.mk b/projects/Rockchip/devices/RK322X/packages/rsync/package.mk
new file mode 100644
index 0000000000..f833174649
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/packages/rsync/package.mk
@@ -0,0 +1,44 @@
+# SPDX-License-Identifier: GPL-2.0
+# Copyright (C) 2016-present Team LibreELEC (https://libreelec.tv)
+
+PKG_NAME="rsync"
+PKG_VERSION="3.4.1"
+PKG_SHA256="2924bcb3a1ed8b551fc101f740b9f0fe0a202b115027647cf69850d65fd88c52"
+PKG_LICENSE="GPLv3"
+PKG_SITE="https://rsync.samba.org"
+PKG_URL="https://download.samba.org/pub/rsync/src/${PKG_NAME}-${PKG_VERSION}.tar.gz"
+PKG_DEPENDS_HOST="autotools:host zlib:host"
+PKG_DEPENDS_TARGET="toolchain zlib openssl"
+PKG_LONGDESC="A very fast method for bringing remote files into sync."
+PKG_BUILD_FLAGS="-sysroot -cfg-libs -cfg-libs:host"
+
+PKG_CONFIGURE_OPTS_HOST="--disable-md2man \
+                         --disable-ipv6 \
+                         --disable-openssl \
+                         --disable-xxhash \
+                         --disable-zstd \
+                         --disable-lz4 \
+                         --disable-iconv \
+                         --with-included-popt \
+                         --without-included-zlib"
+
+PKG_CONFIGURE_OPTS_TARGET="--disable-acl-support \
+                           --disable-md5-asm \
+                           --enable-openssl \
+                           --disable-lz4 \
+                           --disable-md2man \
+                           --disable-roll-simd \
+                           --disable-xattr-support \
+                           --disable-xxhash \
+                           --disable-zstd \
+                           --with-included-popt \
+                           --without-included-zlib"
+
+pre_make_host() {
+  # do not detect LE git version
+  echo "#define RSYNC_GITVER \"${PKG_VERSION}\"" >git-version.h
+}
+
+pre_make_target() {
+  pre_make_host
+}
diff --git a/projects/Rockchip/devices/RK322X/packages/systemd/scripts/cpufreq b/projects/Rockchip/devices/RK322X/packages/systemd/scripts/cpufreq
new file mode 100755
index 0000000000..d898392d10
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/packages/systemd/scripts/cpufreq
@@ -0,0 +1,24 @@
+#!/bin/sh
+
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Copyright (C) 2009-2015 Stephan Raue (stephan@openelec.tv)
+# Copyright (C) 2019-present Team LibreELEC (https://libreelec.tv)
+
+SYS_CPUFREQ_GOV=$(cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_governor)
+
+if [ "${SYS_CPUFREQ_GOV}" = "ondemands" ]; then
+  for io_is_busy in $(find /sys/devices/system/cpu -name io_is_busy); do
+    echo 1 > "${io_is_busy}"
+  done
+  for up_threshold in $(find /sys/devices/system/cpu -name up_threshold); do
+    echo 75 > "${up_threshold}"
+  done
+  for sampling_rate in $(find /sys/devices/system/cpu -name sampling_rate); do
+    echo 100000 > "${sampling_rate}"
+  done
+  for sampling_down_factor in $(find /sys/devices/system/cpu -name sampling_down_factor); do
+    echo 5 > "${sampling_down_factor}"
+  done
+else
+  echo "cpufreq: settings not found for current cpu governor." | systemd-cat -p info
+fi
diff --git a/projects/Rockchip/devices/RK322X/packages/u-boot/package.mk b/projects/Rockchip/devices/RK322X/packages/u-boot/package.mk
new file mode 100644
index 0000000000..42c95477de
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/packages/u-boot/package.mk
@@ -0,0 +1,84 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Copyright (C) 2009-2016 Stephan Raue (stephan@openelec.tv)
+# Copyright (C) 2017-present Team LibreELEC (https://libreelec.tv)
+
+PKG_NAME="u-boot"
+PKG_ARCH="arm aarch64"
+PKG_LICENSE="GPL"
+PKG_SITE="https://www.denx.de/wiki/U-Boot"
+PKG_DEPENDS_TARGET="toolchain Python3:host swig:host"
+PKG_LONGDESC="Das U-Boot is a cross-platform bootloader for embedded systems."
+
+PKG_STAMP="${UBOOT_SYSTEM} ${UBOOT_TARGET}"
+
+[ -n "${KERNEL_TOOLCHAIN}" ] && PKG_DEPENDS_TARGET+=" gcc-arm-${KERNEL_TOOLCHAIN}:host"
+
+if [ -n "${UBOOT_FIRMWARE}" ]; then
+  PKG_DEPENDS_TARGET+=" ${UBOOT_FIRMWARE}"
+  PKG_DEPENDS_UNPACK+=" ${UBOOT_FIRMWARE}"
+fi
+
+PKG_NEED_UNPACK="${PROJECT_DIR}/${PROJECT}/bootloader"
+[ -n "${DEVICE}" ] && PKG_NEED_UNPACK+=" ${PROJECT_DIR}/${PROJECT}/devices/${DEVICE}/bootloader"
+
+case "${PROJECT}" in
+  Amlogic)
+    PKG_VERSION="807482107a6d426dbcd6457d9ccf8b3ce6ca887b" # 2021.04-rc2 custodians/u-boot-amlogic-test
+    PKG_SHA256="a10430d2c1a1d9e83e66bed342433ddfe4f3d6f16d9fa8b4d4c034b600baffd3"
+    PKG_URL="https://github.com/chewitt/u-boot/archive/${PKG_VERSION}.tar.gz"
+    PKG_PATCH_DIRS="amlogic"
+    ;;
+  Rockchip)
+    PKG_VERSION="479fbf72ee0660f74652da35a9f837b0e0ee06e8"
+    PKG_SHA256="1e5840d098d23b9f9e4fcaa5eaba8eb9dcee5cf59f311bfc9e4cad8c28359c40"
+    PKG_URL="https://github.com/rockchip-linux/u-boot/archive/${PKG_VERSION}.tar.gz"
+    PKG_PATCH_DIRS="rockchip"
+    ;;
+  *)
+    PKG_VERSION="2021.01"
+    PKG_SHA256="b407e1510a74e863b8b5cb42a24625344f0e0c2fc7582d8c866bd899367d0454"
+    PKG_URL="http://ftp.denx.de/pub/u-boot/${PKG_NAME}-${PKG_VERSION}.tar.bz2"
+    PKG_PATCH_DIRS="default"
+    ;;
+esac
+
+post_patch() {
+  if [ -n "${UBOOT_SYSTEM}" ] && find_file_path bootloader/config; then
+    PKG_CONFIG_FILE="${PKG_BUILD}/configs/$(${ROOT}/${SCRIPTS}/uboot_helper ${PROJECT} ${DEVICE} ${UBOOT_SYSTEM} config)"
+    if [ -f "${PKG_CONFIG_FILE}" ]; then
+      cat ${FOUND_PATH} >> "${PKG_CONFIG_FILE}"
+    fi
+  fi
+}
+
+make_target() {
+  if [ -z "${UBOOT_SYSTEM}" ]; then
+    echo "UBOOT_SYSTEM must be set to build an image"
+    echo "see './scripts/uboot_helper' for more information"
+  else
+    [ "${BUILD_WITH_DEBUG}" = "yes" ] && PKG_DEBUG=1 || PKG_DEBUG=0
+    DEBUG=${PKG_DEBUG} CROSS_COMPILE="${TARGET_KERNEL_PREFIX}" LDFLAGS="" ARCH=arm make mrproper
+    [ -n "${UBOOT_FIRMWARE}" ] && find_file_path bootloader/firmware && . ${FOUND_PATH}
+    DEBUG=${PKG_DEBUG} CROSS_COMPILE="${TARGET_KERNEL_PREFIX}" LDFLAGS="" ARCH=arm make $(${ROOT}/${SCRIPTS}/uboot_helper ${PROJECT} ${DEVICE} ${UBOOT_SYSTEM} config)
+    DEBUG=${PKG_DEBUG} CROSS_COMPILE="${TARGET_KERNEL_PREFIX}" LDFLAGS="" ARCH=arm _python_sysroot="${TOOLCHAIN}" _python_prefix=/ _python_exec_prefix=/ make ${UBOOT_TARGET} HOSTCC="${HOST_CC}" HOSTLDFLAGS="-L${TOOLCHAIN}/lib" HOSTSTRIP="true" CONFIG_MKIMAGE_DTC_PATH="scripts/dtc/dtc"
+  fi
+}
+
+makeinstall_target() {
+  mkdir -p ${INSTALL}/usr/share/bootloader
+
+    # Only install u-boot.img et al when building a board specific image
+    if [ -n "${UBOOT_SYSTEM}" ]; then
+      find_file_path bootloader/install && . ${FOUND_PATH}
+    fi
+
+    # Always install the update script
+    find_file_path bootloader/update.sh && cp -av ${FOUND_PATH} ${INSTALL}/usr/share/bootloader
+
+    # Always install the canupdate script
+    if find_file_path bootloader/canupdate.sh; then
+      cp -av ${FOUND_PATH} ${INSTALL}/usr/share/bootloader
+      sed -e "s/@PROJECT@/${DEVICE:-${PROJECT}}/g" \
+          -i ${INSTALL}/usr/share/bootloader/canupdate.sh
+    fi
+}
diff --git a/projects/Rockchip/devices/RK322X/packages/u-boot/patches/rockchip/u-boot-0002-rockchip-board-use-efuse-cpuid-to-set-ethaddr.patch b/projects/Rockchip/devices/RK322X/packages/u-boot/patches/rockchip/u-boot-0002-rockchip-board-use-efuse-cpuid-to-set-ethaddr.patch
new file mode 100644
index 0000000000..9574958182
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/packages/u-boot/patches/rockchip/u-boot-0002-rockchip-board-use-efuse-cpuid-to-set-ethaddr.patch
@@ -0,0 +1,97 @@
+From 61b0555d3b8e962f3cac5cf17ab149f4fb318ca3 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Mon, 20 Aug 2018 22:55:34 +0200
+Subject: [PATCH] rockchip: board: use efuse cpuid to set ethaddr
+
+---
+ arch/arm/mach-rockchip/board.c | 51 ++++++++++++++++++++++++++++++++++
+ 1 file changed, 51 insertions(+)
+
+diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c
+index b56edebf13..155871f5bf 100644
+--- a/arch/arm/mach-rockchip/board.c
++++ b/arch/arm/mach-rockchip/board.c
+@@ -13,6 +13,8 @@
+ #include <cli.h>
+ #include <clk.h>
+ #include <console.h>
++#include <hash.h>
++#include <u-boot/sha256.h>
+ #include <debug_uart.h>
+ #include <dm.h>
+ #include <dvfs.h>
+@@ -90,6 +92,40 @@ static int rockchip_set_ethaddr(void)
+		sprintf(buf, "%pM", ethaddr);
+		env_set("ethaddr", buf);
+	}
++#elif CONFIG_IS_ENABLED(CMD_NET)
++	int ret;
++	const char *cpuid = env_get("cpuid#");
++	u8 hash[SHA256_SUM_LEN];
++	int size = sizeof(hash);
++	u8 mac_addr[6];
++
++	/* Only generate a MAC address, if none is set in the environment */
++	if (env_get("ethaddr"))
++		return 0;
++
++	if (!cpuid) {
++		debug("%s: could not retrieve 'cpuid#'\n", __func__);
++		return -EINVAL;
++	}
++
++	ret = hash_block("sha256", (void *)cpuid, strlen(cpuid), hash, &size);
++	if (ret) {
++		debug("%s: failed to calculate SHA256\n", __func__);
++		return -EINVAL;
++	}
++
++	/* Copy 6 bytes of the hash to base the MAC address on */
++	memcpy(mac_addr, hash, 6);
++
++	/* Make this a valid MAC address and set it */
++	mac_addr[0] &= 0xfe;  /* clear multicast bit */
++	mac_addr[0] |= 0x02;  /* set local assignment bit (IEEE802) */
++	eth_env_set_enetaddr("ethaddr", mac_addr);
++
++	/* Make a valid MAC address for eth1 */
++	mac_addr[5] += 0x20;
++	mac_addr[5] &= 0xff;
++	eth_env_set_enetaddr("eth1addr", mac_addr);
+ #endif
+	return 0;
+ }
+@@ -99,6 +135,9 @@ static int rockchip_set_serialno(void)
+	u8 low[CPUID_LEN / 2], high[CPUID_LEN / 2];
+	u8 cpuid[CPUID_LEN] = {0};
+	char serialno_str[VENDOR_SN_MAX];
++#ifdef CONFIG_ROCKCHIP_EFUSE
++	char cpuid_str[CPUID_LEN * 2 + 1];
++#endif
+	int ret = 0, i;
+	u64 serialno;
+
+@@ -130,6 +169,13 @@ static int rockchip_set_serialno(void)
+			       __func__, ret);
+			return ret;
+		}
++
++		memset(cpuid_str, 0, sizeof(cpuid_str));
++		for (i = 0; i < CPUID_LEN; i++) {
++			sprintf(&cpuid_str[i * 2], "%02x", cpuid[i]);
++		}
++
++		env_set("cpuid#", cpuid_str);
+ #else
+				/* generate random cpuid */
+				for (i = 0; i < CPUID_LEN; i++)
+@@ -260,8 +306,8 @@ static void cmdline_handle(void)
+
+ int board_late_init(void)
+ {
+-	rockchip_set_ethaddr();
+	rockchip_set_serialno();
++	rockchip_set_ethaddr();
+	setup_download_mode();
+ #if (CONFIG_ROCKCHIP_BOOT_MODE_REG > 0)
+	setup_boot_mode();
diff --git a/projects/Rockchip/devices/RK322X/packages/u-boot/patches/rockchip/u-boot-0008-rockchip-disable-android-boot-and-config.patch b/projects/Rockchip/devices/RK322X/packages/u-boot/patches/rockchip/u-boot-0008-rockchip-disable-android-boot-and-config.patch
new file mode 100644
index 0000000000..e29ede4522
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/packages/u-boot/patches/rockchip/u-boot-0008-rockchip-disable-android-boot-and-config.patch
@@ -0,0 +1,114 @@
+From d0c3abbbecfe69a73b157451857ca061870ec49b Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Sat, 18 Aug 2018 17:27:32 +0200
+Subject: [PATCH] rockchip: disable android boot and config
+
+---
+ configs/evb-rk3399_defconfig       | 17 +----------------
+ configs/miqi-rk3288_defconfig      | 12 +-----------
+ configs/tinker-rk3288_defconfig    |  3 ---
+ include/configs/rockchip-common.h  |  2 --
+ 5 files changed, 4 insertions(+), 35 deletions(-)
+
+diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig
+index 305f0a405d..96aa34b2c0 100644
+--- a/configs/evb-rk3399_defconfig
++++ b/configs/evb-rk3399_defconfig
+@@ -7,16 +7,15 @@
+ CONFIG_SPL_LIBCOMMON_SUPPORT=y
+ CONFIG_SPL_LIBGENERIC_SUPPORT=y
+ CONFIG_SYS_MALLOC_F_LEN=0x4000
+ CONFIG_ROCKCHIP_RK3399=y
+-CONFIG_RKIMG_BOOTLOADER=y
+-# CONFIG_USING_KERNEL_DTB is not set
++CONFIG_SPL_STACK_R_ADDR=0x80000
+ CONFIG_DEFAULT_DEVICE_TREE="rk3399-evb"
++# CONFIG_ANDROID_BOOT_IMAGE is not set
+ CONFIG_DEBUG_UART=y
+ CONFIG_FIT=y
+ CONFIG_SPL_LOAD_FIT=y
+ CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py"
+ # CONFIG_DISPLAY_CPUINFO is not set
+-CONFIG_ANDROID_BOOTLOADER=y
+ CONFIG_SPL_STACK_R=y
+ CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
+ CONFIG_SPL_ATF=y
+diff --git a/configs/miqi-rk3288_defconfig b/configs/miqi-rk3288_defconfig
+index ffbe701cfd..0aa4c903e4 100644
+--- a/configs/miqi-rk3288_defconfig
++++ b/configs/miqi-rk3288_defconfig
+@@ -3,12 +3,11 @@ CONFIG_ARCH_ROCKCHIP=y
+ CONFIG_SYS_MALLOC_F_LEN=0x2000
+ CONFIG_ROCKCHIP_RK3288=y
+ CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
+-CONFIG_RKIMG_BOOTLOADER=y
+ CONFIG_TARGET_MIQI_RK3288=y
+ CONFIG_SPL_STACK_R_ADDR=0x80000
+ CONFIG_DEFAULT_DEVICE_TREE="rk3288-miqi"
+ CONFIG_DEBUG_UART=y
+-# CONFIG_SILENT_CONSOLE is not set
++# CONFIG_ANDROID_BOOT_IMAGE is not set
+ # CONFIG_DISPLAY_CPUINFO is not set
+ CONFIG_SPL_STACK_R=y
+ CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
+@@ -16,10 +15,6 @@ CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
+ CONFIG_CMD_GPIO=y
+ CONFIG_CMD_GPT=y
+ CONFIG_CMD_I2C=y
+-CONFIG_ANDROID_BOOT_IMAGE=y
+-CONFIG_ANDROID_BOOTLOADER=y
+-CONFIG_CMD_BOOT_ANDROID=y
+-CONFIG_CMD_BOOT_ROCKCHIP=y
+ CONFIG_CMD_MMC=y
+ CONFIG_CMD_SF=y
+ CONFIG_CMD_SPI=y
+@@ -80,11 +75,6 @@ CONFIG_G_DNL_PRODUCT_NUM=0x320a
+ CONFIG_USB_HOST_ETHER=y
+ CONFIG_USB_ETHER_ASIX=y
+ CONFIG_USB_ETHER_SMSC95XX=y
+-CONFIG_DM_VIDEO=y
+-CONFIG_DISPLAY=y
+-CONFIG_VIDEO_ROCKCHIP=y
+-CONFIG_DISPLAY_ROCKCHIP_HDMI=y
+-CONFIG_CONSOLE_SCROLL_LINES=10
+ CONFIG_USE_TINY_PRINTF=y
+ CONFIG_CMD_DHRYSTONE=y
+ CONFIG_ERRNO_STR=y
+diff --git a/configs/tinker-rk3288_defconfig b/configs/tinker-rk3288_defconfig
+index 0afc0a35e1..a6f8c0cb51 100644
+--- a/configs/tinker-rk3288_defconfig
++++ b/configs/tinker-rk3288_defconfig
+@@ -3,13 +3,11 @@ CONFIG_ARCH_ROCKCHIP=y
+ CONFIG_SYS_MALLOC_F_LEN=0x2000
+ CONFIG_ROCKCHIP_RK3288=y
+ CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
+-CONFIG_RKIMG_BOOTLOADER=y
+ CONFIG_TARGET_TINKER_RK3288=y
+ CONFIG_SPL_STACK_R_ADDR=0x80000
+ CONFIG_DEFAULT_DEVICE_TREE="rk3288-tinker"
+ CONFIG_DEBUG_UART=y
+ # CONFIG_ANDROID_BOOT_IMAGE is not set
+-# CONFIG_SILENT_CONSOLE is not set
+ CONFIG_CONSOLE_MUX=y
+ # CONFIG_DISPLAY_CPUINFO is not set
+ CONFIG_SPL_STACK_R=y
+@@ -19,7 +17,6 @@ CONFIG_SPL_I2C_SUPPORT=y
+ CONFIG_CMD_GPIO=y
+ CONFIG_CMD_GPT=y
+ CONFIG_CMD_I2C=y
+-CONFIG_CMD_BOOT_ROCKCHIP=y
+ CONFIG_CMD_MMC=y
+ CONFIG_CMD_SF=y
+ CONFIG_CMD_SPI=y
+diff --git a/include/configs/rockchip-common.h b/include/configs/rockchip-common.h
+index f159cbddf3..75a0963953 100644
+--- a/include/configs/rockchip-common.h
++++ b/include/configs/rockchip-common.h
+@@ -105,8 +105,6 @@
+	"boot_android ${devtype} ${devnum};"
+ #else
+ #define RKIMG_BOOTCOMMAND			\
+-	"boot_android ${devtype} ${devnum};"	\
+-	"bootrkp;"				\
+	"run distro_bootcmd;"
+ #endif
diff --git a/projects/Rockchip/devices/RK322X/packages/u-boot/patches/rockchip/u-boot-0012-Makefile-compat.patch b/projects/Rockchip/devices/RK322X/packages/u-boot/patches/rockchip/u-boot-0012-Makefile-compat.patch
new file mode 100644
index 0000000000..fef03057ae
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/packages/u-boot/patches/rockchip/u-boot-0012-Makefile-compat.patch
@@ -0,0 +1,12 @@
+diff --git a/Makefile b/Makefile
+index 28e3e70..c398ba6 100644
+--- a/Makefile
++++ b/Makefile
+@@ -359,6 +359,7 @@ KBUILD_CPPFLAGS := -D__KERNEL__ -D__UBOOT__
+
+ KBUILD_CFLAGS   := -Wall -Wstrict-prototypes \
+		   -Wno-format-security \
++		   -Wno-error=tautological-compare \
+		   -fno-builtin -ffreestanding
+ KBUILD_CFLAGS	+= -fshort-wchar -Werror
+ KBUILD_AFLAGS   := -D__ASSEMBLY__
diff --git a/projects/Rockchip/devices/RK322X/packages/u-boot/patches/rockchip/u-boot-0012-Revert-Makefile-enable-Werror-option.patch b/projects/Rockchip/devices/RK322X/packages/u-boot/patches/rockchip/u-boot-0012-Revert-Makefile-enable-Werror-option.patch
new file mode 100644
index 0000000000..4ea0eb75cb
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/packages/u-boot/patches/rockchip/u-boot-0012-Revert-Makefile-enable-Werror-option.patch
@@ -0,0 +1,23 @@
+From 45be7edd81e458ca90985a0c687e769aa9ebaf5b Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Mon, 9 Sep 2019 05:59:12 +0000
+Subject: [PATCH] Revert "Makefile: enable -Werror option"
+
+This reverts commit 76ba1d8a713bc964fc8e0a639f90344c4c60f026.
+---
+ Makefile | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/Makefile b/Makefile
+index f81ac1f9f9..fe2a57fa58 100644
+--- a/Makefile
++++ b/Makefile
+@@ -360,7 +360,7 @@ KBUILD_CPPFLAGS := -D__KERNEL__ -D__UBOOT__
+ KBUILD_CFLAGS   := -Wall -Wstrict-prototypes \
+		   -Wno-format-security \
+		   -fno-builtin -ffreestanding
+-KBUILD_CFLAGS	+= -fshort-wchar -Werror
++KBUILD_CFLAGS	+= -fshort-wchar
+ KBUILD_AFLAGS   := -D__ASSEMBLY__
+
+ # Read UBOOTRELEASE from include/config/uboot.release (if it exists)
diff --git a/projects/Rockchip/devices/RK322X/packages/u-boot/patches/rockchip/u-boot-1000-rk322x-defconfig-dts.patch b/projects/Rockchip/devices/RK322X/packages/u-boot/patches/rockchip/u-boot-1000-rk322x-defconfig-dts.patch
new file mode 100644
index 0000000000..5edc31f296
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/packages/u-boot/patches/rockchip/u-boot-1000-rk322x-defconfig-dts.patch
@@ -0,0 +1,308 @@
+diff -ruPN u-boot-e311da245800596d57b7b7d91ebd4a730747a9ec/arch/arm/dts/rk322x-box.dts u-boot-new/arch/arm/dts/rk322x-box.dts
+--- u-boot-e311da245800596d57b7b7d91ebd4a730747a9ec/arch/arm/dts/rk322x-box.dts	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-new/arch/arm/dts/rk322x-box.dts	2022-01-26 10:11:24.960209651 +0100
+@@ -0,0 +1,36 @@
++/*
++ * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
++ *
++ * SPDX-License-Identifier:     GPL-2.0+ X11
++ */
++
++/dts-v1/;
++
++#include "rk322x-box.dtsi"
++#include "rk322x-u-boot.dtsi"
++#include <dt-bindings/input/input.h>
++
++/ {
++	model = "Rockchip RK322x SoC (eMMC)";
++
++	aliases {
++		mmc1 = &emmc;
++		mmc2 = &nandc;
++	};
++
++	chosen {
++		u-boot,spl-boot-order = &sdmmc, &emmc, &nandc;
++	};
++
++};
++
++&emmc {
++	/* /delete-property/ pinctrl-names;
++	/delete-property/ pinctrl-0; */
++	/delete-property/ default-sample-phase;
++	status = "okay";
++};
++
++&nandc {
++	status = "okay";
++};
+diff -ruPN u-boot-e311da245800596d57b7b7d91ebd4a730747a9ec/arch/arm/dts/rk322x-box.dtsi u-boot-new/arch/arm/dts/rk322x-box.dtsi
+--- u-boot-e311da245800596d57b7b7d91ebd4a730747a9ec/arch/arm/dts/rk322x-box.dtsi	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-new/arch/arm/dts/rk322x-box.dtsi	2022-01-26 09:58:53.845178207 +0100
+@@ -0,0 +1,140 @@
++/*
++ * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
++ *
++ * SPDX-License-Identifier:     GPL-2.0+ X11
++ */
++
++/dts-v1/;
++
++#include "rk322x.dtsi"
++#include "rk322x-u-boot.dtsi"
++#include <dt-bindings/input/input.h>
++
++/ {
++	model = "Rockchip RK322x SoC";
++	compatible = "rockchip,rk3229-evb", "rockchip,rk3229";
++
++	aliases {
++               serial0 = &uart0;
++               serial1 = &uart1;
++               serial2 = &uart2;
++               mmc0 = &sdmmc;
++        };
++
++	ext_gmac: ext_gmac {
++		compatible = "fixed-clock";
++		clock-frequency = <125000000>;
++		clock-output-names = "ext_gmac";
++		#clock-cells = <0>;
++	};
++
++	vcc_phy: vcc-phy-regulator {
++		compatible = "regulator-fixed";
++		enable-active-high;
++		regulator-name = "vcc_phy";
++		regulator-min-microvolt = <1800000>;
++		regulator-max-microvolt = <1800000>;
++		regulator-always-on;
++		regulator-boot-on;
++	};
++
++	vcc_otg_vbus: otg-vbus-regulator {
++		compatible = "regulator-fixed";
++		gpio = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&otg_vbus_drv>;
++		regulator-name = "vcc_otg_vbus";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		enable-active-high;
++	};
++
++	gpio-keys {
++		u-boot,dm-pre-reloc;
++		compatible = "gpio-keys";
++		status = "okay";
++
++		volume-up {
++			u-boot,dm-pre-reloc;
++			linux,code = <KEY_VOLUMEUP>;
++			label = "Volume Up";
++			gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
++		};
++	};
++
++};
++
++/*&dmc {
++	rockchip,pctl-timing = <0x96 0xC8 0x1F3 0xF 0x8000004D 0x4 0x4E 0x6 0x3
++		0x0 0x6 0x5 0xC 0x10 0x6 0x4 0x4
++		0x5 0x4 0x200 0x3 0xA 0x40 0x0 0x1
++		0x5 0x5 0x3 0xC 0x1E 0x100 0x0 0x4
++		0x0 0x924>;
++	rockchip,phy-timing = <0x220 0x1 0x0 0x0 0x0 0x4 0x60>;
++	rockchip,sdram-params = <0x428B188 0x0 0x21 0x472 0x15
++		0 300 3 0 120>;
++};*/
++
++&gmac {
++	assigned-clocks = <&cru SCLK_MAC_EXTCLK>, <&cru SCLK_MAC>;
++	assigned-clock-parents = <&ext_gmac>, <&cru SCLK_MAC_EXTCLK>;
++	clock_in_out = "input";
++	phy-supply = <&vcc_phy>;
++	phy-mode = "rgmii";
++	pinctrl-names = "default";
++	pinctrl-0 = <&rgmii_pins>;
++	snps,reset-gpio = <&gpio2 RK_PD0 GPIO_ACTIVE_LOW>;
++	snps,reset-active-low;
++	snps,reset-delays-us = <0 10000 1000000>;
++	tx_delay = <0x30>;
++	rx_delay = <0x10>;
++	status = "okay";
++};
++
++&sdmmc {
++	bus-width = <4>;
++	cap-mmc-highspeed;
++	cap-sd-highspeed;
++	card-detect-delay = <200>;
++	disable-wp;
++	num-slots = <1>;
++	supports-sd;
++	status = "okay";
++};
++
++&uart2 {
++	status = "okay";
++};
++
++&u2phy0 {
++	status = "okay";
++
++	u2phy0_otg: otg-port {
++		status = "okay";
++	};
++
++	u2phy0_host: host-port {
++		status = "okay";
++	};
++};
++
++&usb20_otg {
++       status = "okay";
++};
++
++
++&pinctrl {
++
++	gpio {
++		gpio_leds: gpio-leds {
++			rockchip,pins = <3 21 RK_FUNC_GPIO &pcfg_pull_down>;
++		};
++	};
++
++	usb {
++		otg_vbus_drv: otg-vbus-drv {
++			rockchip,pins = <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++};
+diff -ruPN u-boot-e311da245800596d57b7b7d91ebd4a730747a9ec/configs/rk322x-linux-miniloader_defconfig u-boot-new/configs/rk322x-linux-miniloader_defconfig
+--- u-boot-e311da245800596d57b7b7d91ebd4a730747a9ec/configs/rk322x-linux-miniloader_defconfig	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-new/configs/rk322x-box_defconfig	2022-01-26 10:13:25.228214686 +0100
+@@ -0,0 +1,120 @@
++CONFIG_ARM=y
++CONFIG_ARCH_ROCKCHIP=y
++CONFIG_SPL_LIBCOMMON_SUPPORT=y
++CONFIG_SPL_LIBGENERIC_SUPPORT=y
++CONFIG_SYS_MALLOC_F_LEN=0x1000
++CONFIG_ROCKCHIP_RK322X=y
++CONFIG_TPL_LDSCRIPT="arch/arm/mach-rockchip/u-boot-tpl.lds"
++CONFIG_TPL_TEXT_BASE=0x10081000
++CONFIG_TPL_MAX_SIZE=28672
++CONFIG_TPL_STACK=0x10088000
++CONFIG_TPL_ROCKCHIP_BACK_TO_BROM=y
++CONFIG_TPL_TINY_MEMSET=y
++CONFIG_USE_TINY_PRINTF=y
++CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0
++CONFIG_RKIMG_BOOTLOADER=y
++CONFIG_TARGET_EVB_RK3229=y
++CONFIG_SPL_STACK_R_ADDR=0x60600000
++CONFIG_DEFAULT_DEVICE_TREE="rk322x-box"
++CONFIG_BOOTDELAY=1
++CONFIG_DEBUG_UART=y
++CONFIG_FIT=y
++CONFIG_FIT_VERBOSE=y
++CONFIG_SPL_LOAD_FIT=y
++CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_optee.sh"
++# CONFIG_DISPLAY_CPUINFO is not set
++# CONFIG_ANDROID_BOOTLOADER is not set
++# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
++# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
++CONFIG_SPL_STACK_R=y
++CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
++CONFIG_SPL_OPTEE=y
++# CONFIG_CMD_IMLS is not set
++CONFIG_CMD_GPT=y
++CONFIG_CMD_MMC=y
++CONFIG_CMD_USB=y
++CONFIG_CMD_NET=y
++CONFIG_CMD_USB_MASS_STORAGE=y
++# CONFIG_CMD_SETEXPR is not set
++CONFIG_CMD_TIME=y
++CONFIG_SPL_OF_CONTROL=y
++CONFIG_TPL_OF_CONTROL=y
++CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
++# CONFIG_ENV_IS_IN_MMC is not set
++CONFIG_TPL_DM=y
++CONFIG_REGMAP=y
++CONFIG_SPL_REGMAP=y
++CONFIG_TPL_REGMAP=y
++CONFIG_SYSCON=y
++CONFIG_SPL_SYSCON=y
++CONFIG_TPL_SYSCON=y
++CONFIG_CLK=y
++CONFIG_SPL_CLK=y
++CONFIG_TPL_CLK=y
++CONFIG_ROCKCHIP_GPIO=y
++CONFIG_SYS_I2C_ROCKCHIP=y
++CONFIG_MISC=y
++CONFIG_ROCKCHIP_EFUSE=y
++CONFIG_MMC_DW=y
++CONFIG_MMC_DW_ROCKCHIP=y
++CONFIG_DM_ETH=y
++CONFIG_ETH_DESIGNWARE=y
++CONFIG_GMAC_ROCKCHIP=y
++CONFIG_PHY=y
++CONFIG_PHY_ROCKCHIP_INNO_USB2=y
++CONFIG_PINCTRL=y
++CONFIG_RAM=y
++CONFIG_SPL_RAM=y
++CONFIG_TPL_RAM=y
++CONFIG_BAUDRATE=115200
++CONFIG_DEBUG_UART_BASE=0x11030000
++CONFIG_DEBUG_UART_CLOCK=24000000
++CONFIG_DEBUG_UART_SHIFT=2
++CONFIG_SYS_NS16550=y
++CONFIG_SYSRESET=y
++CONFIG_USB=y
++CONFIG_USB_DWC2=y
++CONFIG_USB_GADGET=y
++CONFIG_USB_GADGET_DWC2_OTG=y
++CONFIG_USB_GADGET_DOWNLOAD=y
++CONFIG_G_DNL_MANUFACTURER="Rockchip"
++CONFIG_G_DNL_VENDOR_NUM=0x18d1
++CONFIG_G_DNL_PRODUCT_NUM=0xd00d
++CONFIG_SHA1=y
++CONFIG_SHA256=y
++CONFIG_ERRNO_STR=y
++CONFIG_OPTEE_CLIENT=y
++CONFIG_OPTEE_V2=y
++CONFIG_DM_RESET=y
++CONFIG_RESET_ROCKCHIP=y
++CONFIG_ROCKCHIP_SFC=y
++CONFIG_RKNAND=y
++CONFIG_LZ4=y
++CONFIG_LZO=y
++CONFIG_LZMA=y
++CONFIG_DM_KEY=y
++CONFIG_USB_STORAGE=y
++CONFIG_ROCKCHIP_USB_BOOT=y
++CONFIG_INPUT=y
++CONFIG_DM_KEY=y
++CONFIG_ADC_KEY=y
++CONFIG_GPIO_KEY=y
++CONFIG_RK_KEY=y
++CONFIG_PWRKEY_DNL_TRIGGER_NUM=0
++CONFIG_LED=y
++CONFIG_LED_GPIO=y
++CONFIG_DM_VIDEO=y
++CONFIG_BACKLIGHT_PWM=y
++CONFIG_VIDEO_BPP8=y
++CONFIG_VIDEO_BPP16=y
++CONFIG_VIDEO_BPP32=y
++CONFIG_CONSOLE_NORMAL=y
++CONFIG_I2C_EDID=y
++CONFIG_VIDEO_ROCKCHIP=y
++CONFIG_VIDEO_ROCKCHIP_MAX_XRES=1920
++CONFIG_VIDEO_ROCKCHIP_MAX_YRES=1080
++CONFIG_DISPLAY_ROCKCHIP_HDMI=y
++CONFIG_CONSOLE_SCROLL_LINES=1
++CONFIG_VIDEO_DW_HDMI=y
++CONFIG_DISPLAY=y
++# CONFIG_MMC_USE_PRE_CONFIG is not set
diff --git a/projects/Rockchip/devices/RK322X/packages/u-boot/patches/rockchip/u-boot-1002-fixgcc10.patch b/projects/Rockchip/devices/RK322X/packages/u-boot/patches/rockchip/u-boot-1002-fixgcc10.patch
new file mode 100644
index 0000000000..1ff2da3d9c
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/packages/u-boot/patches/rockchip/u-boot-1002-fixgcc10.patch
@@ -0,0 +1,22 @@
+diff -rupN u-boot/scripts/dtc/dtc-lexer.l u-boot-new/scripts/dtc/dtc-lexer.l
+--- u-boot/scripts/dtc/dtc-lexer.l	2020-03-30 11:32:14.000000000 +0200
++++ u-boot-new/scripts/dtc/dtc-lexer.l	2021-12-01 11:40:21.021358521 +0100
+@@ -38,7 +38,6 @@ LINECOMMENT	"//".*\n
+ #include "srcpos.h"
+ #include "dtc-parser.tab.h"
+
+-YYLTYPE yylloc;
+ extern bool treesource_error;
+
+ /* CAUTION: this will stop working if we ever use yyless() or yyunput() */
+diff -rupN u-boot/scripts/dtc/dtc-lexer.lex.c_shipped u-boot-new/scripts/dtc/dtc-lexer.lex.c_shipped
+--- u-boot/scripts/dtc/dtc-lexer.lex.c_shipped	2020-03-30 11:32:14.000000000 +0200
++++ u-boot-new/scripts/dtc/dtc-lexer.lex.c_shipped	2021-12-01 11:40:35.695359135 +0100
+@@ -631,7 +631,6 @@ char *yytext;
+ #include "srcpos.h"
+ #include "dtc-parser.tab.h"
+
+-YYLTYPE yylloc;
+ extern bool treesource_error;
+
+ /* CAUTION: this will stop working if we ever use yyless() or yyunput() */
diff --git a/projects/Rockchip/devices/RK322X/packages/u-boot/patches/rockchip/u-boot-1004-disable-broken-rockchip-dts.patch b/projects/Rockchip/devices/RK322X/packages/u-boot/patches/rockchip/u-boot-1004-disable-broken-rockchip-dts.patch
new file mode 100644
index 0000000000..a5204f5708
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/packages/u-boot/patches/rockchip/u-boot-1004-disable-broken-rockchip-dts.patch
@@ -0,0 +1,38 @@
+diff -rupN u-boot-505eebf24e153630f5a3e0ec232ffda67bf48e9e/arch/arm/dts/Makefile u-boot-patched/arch/arm/dts/Makefile
+--- u-boot-505eebf24e153630f5a3e0ec232ffda67bf48e9e/arch/arm/dts/Makefile	2020-03-30 11:32:14.000000000 +0200
++++ u-boot-patched/arch/arm/dts/Makefile	2021-08-04 11:30:57.303969160 +0200
+@@ -28,34 +28,6 @@ dtb-$(CONFIG_EXYNOS5) += exynos5250-arnd
+	exynos5422-odroidxu3.dtb
+ dtb-$(CONFIG_EXYNOS7420) += exynos7420-espresso7420.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
+-	rk3036-sdk.dtb \
+-	rk3066a-mk808.dtb \
+-	rk3126-evb.dtb \
+-	rk3128-evb.dtb \
+-	rk3188-radxarock.dtb \
+-	rk3288-evb.dtb \
+-	rk3288-fennec.dtb \
+-	rk3288-firefly.dtb \
+-	rk3288-miqi.dtb \
+-	rk3288-phycore-rdk.dtb \
+-	rk3288-popmetal.dtb \
+-	rk3288-rock2-square.dtb \
+-	rk3288-tinker.dtb \
+-	rk3288-veyron-jerry.dtb \
+-	rk3288-veyron-mickey.dtb \
+-	rk3288-veyron-minnie.dtb \
+-	rk3288-vyasa.dtb \
+-	rk3308-evb.dtb \
+-	rk3328-evb.dtb \
+-	rk3368-lion.dtb \
+-	rk3368-sheep.dtb \
+-	rk3368-geekbox.dtb \
+-	rk3368-px5-evb.dtb \
+-	rk3399-evb.dtb \
+-	rk3399-firefly.dtb \
+-	rk3399-puma-ddr1333.dtb \
+-	rk3399-puma-ddr1600.dtb \
+-	rk3399-puma-ddr1866.dtb \
+	rv1108-evb.dtb
+ dtb-$(CONFIG_ARCH_MESON) += \
+	meson-gxbb-odroidc2.dtb
diff --git a/projects/Rockchip/devices/RK322X/packages/u-boot/patches/rockchip/u-boot-1005-fix-rknand-image-generation.patch.disabled b/projects/Rockchip/devices/RK322X/packages/u-boot/patches/rockchip/u-boot-1005-fix-rknand-image-generation.patch.disabled
new file mode 100644
index 0000000000..682595f744
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/packages/u-boot/patches/rockchip/u-boot-1005-fix-rknand-image-generation.patch.disabled
@@ -0,0 +1,71 @@
+diff -ruPN u-boot-68c4faa3f8204593f60dadfb560abe58b1899556/tools/rkcommon.c u-boot-new/tools/rkcommon.c
+--- u-boot-68c4faa3f8204593f60dadfb560abe58b1899556/tools/rkcommon.c	2020-03-30 08:52:08.000000000 +0200
++++ u-boot-new/tools/rkcommon.c	2022-11-30 09:21:32.405491864 +0100
+@@ -36,10 +36,20 @@
+	uint8_t reserved[4];
+	uint32_t disable_rc4;
+	uint16_t init_offset;
+-	uint8_t reserved1[492];
++	uint16_t init2_offset;
++	uint8_t reserved1[490];
+	uint16_t init_size;
+	uint16_t init_boot_size;
+-	uint8_t reserved2[2];
++	uint16_t crc;
++};
++
++struct header0_info1 {
++  uint16_t reservedBlock;
++  uint16_t disk0Size;
++  uint16_t disk1Size;
++  uint16_t disk2Size;
++  uint16_t disk3Size;
++  uint32_t chipTag;
+ };
+
+ /**
+@@ -228,7 +238,7 @@
+	memset(buf, '\0', RK_INIT_OFFSET * RK_BLK_SIZE);
+	hdr->signature = RK_SIGNATURE;
+	hdr->disable_rc4 = !rkcommon_need_rc4_spl(params);
+-	hdr->init_offset = RK_INIT_OFFSET;
++	hdr->init_offset = hdr->init2_offset = RK_INIT_OFFSET;
+	hdr->init_size = spl_params.init_size / RK_BLK_SIZE;
+
+	/*
+@@ -249,12 +259,23 @@
+	rc4_encode(buf, RK_BLK_SIZE, rc4_key);
+ }
+
++static void rkcommon_set_header0_1(void *buf, struct image_tool_params *params)
++{
++	struct header0_info1 *hdr = buf + 512;
++
++	//memset(buf + 512, '\0', RK_INIT_OFFSET * RK_BLK_SIZE);
++	hdr->reservedBlock = 0x0c;
++	hdr->disk0Size = 0xffff;
++	hdr->chipTag = 0x38324b52;
++}
++
+ void rkcommon_set_header(void *buf,  struct stat *sbuf,  int ifd,
+			 struct image_tool_params *params)
+ {
+	struct header1_info *hdr = buf + RK_SPL_HDR_START;
+
+	rkcommon_set_header0(buf, params);
++	rkcommon_set_header0_1(buf, params);
+
+	/* Set up the SPL name (i.e. copy spl_hdr over) */
+	if (memcmp(&hdr->magic, "RSAK", 4))
+diff -ruPN u-boot-68c4faa3f8204593f60dadfb560abe58b1899556/tools/rknand.c u-boot-new/tools/rknand.c
+--- u-boot-68c4faa3f8204593f60dadfb560abe58b1899556/tools/rknand.c	2020-03-30 08:52:08.000000000 +0200
++++ u-boot-new/tools/rknand.c	2022-11-28 15:12:23.480682164 +0100
+@@ -104,7 +104,7 @@
+	rkcommon_check_params,
+	/* TODO: Support rknand in there helpers */
+	NULL, //rkcommon_verify_header,
+-	NULL, //rkcommon_print_header,
++	rkcommon_print_header,
+	rknand_set_header,
+	NULL,
+	rknand_check_image_type,
diff --git a/projects/Rockchip/devices/RK322X/packages/u-boot/patches/rockchip/u-boot-2004-rk322x-box-add-nand-env-boot.patch b/projects/Rockchip/devices/RK322X/packages/u-boot/patches/rockchip/u-boot-2004-rk322x-box-add-nand-env-boot.patch
new file mode 100644
index 0000000000..070f225391
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/packages/u-boot/patches/rockchip/u-boot-2004-rk322x-box-add-nand-env-boot.patch
@@ -0,0 +1,14 @@
+diff --git a/include/configs/rk322x_common.h b/include/configs/rk322x_common.h
+index d9935dd..06a33f7 100644
+--- a/include/configs/rk322x_common.h
++++ b/include/configs/rk322x_common.h
+@@ -58,7 +58,8 @@
+	ENV_MEM_LAYOUT_SETTINGS \
+	ROCKCHIP_DEVICE_SETTINGS \
+	RKIMG_DET_BOOTDEV \
+-	BOOTENV
++	BOOTENV \
++	"rknand_boot=if rknand dev ${devnum}; then setenv devtype rknand; run scan_dev_for_boot_part; fi"
+ #endif
+
+ #define CONFIG_PREBOOT
diff --git a/projects/Rockchip/devices/RK322X/packages/wpa_supplicant/config/makefile.config b/projects/Rockchip/devices/RK322X/packages/wpa_supplicant/config/makefile.config
new file mode 100644
index 0000000000..5c98433969
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/packages/wpa_supplicant/config/makefile.config
@@ -0,0 +1,35 @@
+CONFIG_CTRL_IFACE=y
+CONFIG_CTRL_IFACE_DBUS=y
+CONFIG_CTRL_IFACE_DBUS_NEW=y
+CONFIG_CTRL_IFACE_DBUS_INTRO=y
+CONFIG_DRIVER_WEXT=y
+CONFIG_LIBNL32=y
+CONFIG_DRIVER_NL80211=y
+CONFIG_DRIVER_WIRED=y
+CONFIG_IEEE8021X_EAPOL=y
+CONFIG_EAP_MD5=y
+CONFIG_EAP_MSCHAPV2=y
+CONFIG_EAP_TLS=y
+CONFIG_EAP_PEAP=y
+CONFIG_EAP_TTLS=y
+CONFIG_EAP_PSK=y
+CONFIG_EAP_FAST=y
+CONFIG_EAP_GTC=y
+CONFIG_EAP_OTP=y
+CONFIG_EAP_AKA=y
+CONFIG_EAP_PAX=y
+CONFIG_EAP_LEAP=y
+CONFIG_EAP_SAKE=y
+CONFIG_EAP_GPSK=y
+CONFIG_EAP_GPSK_SHA256=y
+CONFIG_EAP_TNC=y
+CONFIG_WPS=y
+CONFIG_EAP_IKEV2=y
+CONFIG_PKCS12=y
+CONFIG_SMARTCARD=y
+CONFIG_DEBUG_FILE=y
+CONFIG_BACKEND=file
+CONFIG_PEERKEY=y
+CONFIG_BGSCAN_SIMPLE=y
+CONFIG_AP=y
+#CONFIG_FIPS=y
\ No newline at end of file
diff --git a/projects/Rockchip/devices/RK322X/packages/wpa_supplicant/package.mk b/projects/Rockchip/devices/RK322X/packages/wpa_supplicant/package.mk
new file mode 100644
index 0000000000..907e63a251
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/packages/wpa_supplicant/package.mk
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Copyright (C) 2009-2016 Stephan Raue (stephan@openelec.tv)
+# Copyright (C) 2019-present Team LibreELEC (https://libreelec.tv)
+
+PKG_NAME="wpa_supplicant"
+PKG_VERSION="2.11"
+PKG_SHA256="912ea06f74e30a8e36fbb68064d6cdff218d8d591db0fc5d75dee6c81ac7fc0a"
+PKG_LICENSE="GPL"
+PKG_SITE="https://w1.fi/wpa_supplicant/"
+PKG_URL="https://w1.fi/releases/${PKG_NAME}-${PKG_VERSION}.tar.gz"
+PKG_DEPENDS_TARGET="toolchain dbus libnl openssl"
+PKG_LONGDESC="A free software implementation of an IEEE 802.11i supplicant."
+PKG_TOOLCHAIN="make"
+PKG_BUILD_FLAGS="+lto-parallel"
+
+PKG_MAKE_OPTS_TARGET="-C wpa_supplicant V=1 LIBDIR=/usr/lib BINDIR=/usr/bin"
+PKG_MAKEINSTALL_OPTS_TARGET="-C wpa_supplicant V=1 LIBDIR=/usr/lib BINDIR=/usr/bin"
+
+configure_target() {
+  LDFLAGS+=" -lpthread -lm"
+
+  cp ${PKG_DIR}/config/makefile.config wpa_supplicant/.config
+}
+
+post_makeinstall_target() {
+  rm -r ${INSTALL}/usr/bin/wpa_cli
+
+  mkdir -p ${INSTALL}/etc/dbus-1/system.d
+    cp wpa_supplicant/dbus/dbus-wpa_supplicant.conf ${INSTALL}/etc/dbus-1/system.d
+
+  mkdir -p ${INSTALL}/usr/lib/systemd/system
+    cp wpa_supplicant/systemd/wpa_supplicant.service ${INSTALL}/usr/lib/systemd/system
+
+  mkdir -p ${INSTALL}/usr/share/dbus-1/system-services
+    cp wpa_supplicant/dbus/fi.w1.wpa_supplicant1.service ${INSTALL}/usr/share/dbus-1/system-services
+}
diff --git a/projects/Rockchip/devices/RK322X/packages/wpa_supplicant/patches/wpa_supplicant-2.4-libnl3-includes.patch b/projects/Rockchip/devices/RK322X/packages/wpa_supplicant/patches/wpa_supplicant-2.4-libnl3-includes.patch
new file mode 100644
index 0000000000..56c09ffaee
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/packages/wpa_supplicant/patches/wpa_supplicant-2.4-libnl3-includes.patch
@@ -0,0 +1,12 @@
+diff -Naur wpa_supplicant-2.4/src/drivers/drivers.mk wpa_supplicant-2.4.patch/src/drivers/drivers.mk
+--- wpa_supplicant-2.4/src/drivers/drivers.mk	2015-03-15 18:30:39.000000000 +0100
++++ wpa_supplicant-2.4.patch/src/drivers/drivers.mk	2015-03-17 13:16:01.390789977 +0100
+@@ -35,7 +35,7 @@
+ ifdef CONFIG_LIBNL32
+   DRV_LIBS += -lnl-3
+   DRV_LIBS += -lnl-genl-3
+-  DRV_CFLAGS += -I/usr/include/libnl3
++  DRV_CFLAGS += `pkg-config --cflags libnl-3.0`
+ ifdef CONFIG_LIBNL3_ROUTE
+   DRV_LIBS += -lnl-route-3
+   DRV_CFLAGS += -DCONFIG_LIBNL3_ROUTE
diff --git a/projects/Rockchip/devices/RK322X/patches/alsa-lib/IEC958-to-DW-HDMI-format-hack.patch b/projects/Rockchip/devices/RK322X/patches/alsa-lib/IEC958-to-DW-HDMI-format-hack.patch
new file mode 100644
index 0000000000..2a5393ed21
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/patches/alsa-lib/IEC958-to-DW-HDMI-format-hack.patch
@@ -0,0 +1,100 @@
+From 51d80714a7654ada9c15f03760b2bbe9d3c37823 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@siol.net>
+Date: Tue, 14 Jul 2020 21:16:00 +0200
+Subject: [PATCH] IEC958 to DW-HDMI format hack
+
+---
+ src/pcm/pcm_iec958.c | 42 +++++++++++++++++-------------------------
+ 1 file changed, 17 insertions(+), 25 deletions(-)
+
+diff --git a/src/pcm/pcm_iec958.c b/src/pcm/pcm_iec958.c
+index dd64aac65d8f..dc280d7ed48b 100644
+--- a/src/pcm/pcm_iec958.c
++++ b/src/pcm/pcm_iec958.c
+@@ -71,8 +71,8 @@ enum { PREAMBLE_Z, PREAMBLE_X, PREAMBLE_Y };
+ #endif /* DOC_HIDDEN */
+
+ /*
+- * Determine parity for time slots 4 upto 30
+- * to be sure that bit 4 upt 31 will carry
++ * Determine parity for time slots 11 upto 29
++ * to be sure that bit 11 upto 30 will carry
+  * an even number of ones and zeros.
+  */
+ static unsigned int iec958_parity(unsigned int data)
+@@ -80,9 +80,8 @@ static unsigned int iec958_parity(unsigned int data)
+	unsigned int parity;
+	int bit;
+
+-	data >>= 4;     /* start from bit 4 */
+	parity = 0;
+-	for (bit = 4; bit <= 30; bit++) {
++	for (bit = 11; bit <= 29; bit++) {
+		if (data & 1)
+			parity++;
+		data >>= 1;
+@@ -94,13 +93,13 @@ static unsigned int iec958_parity(unsigned int data)
+  * Compose 32bit IEC958 subframe, two sub frames
+  * build one frame with two channels.
+  *
+- * bit 0-3  = preamble
+- *     4-7  = AUX (=0)
+- *     8-27 = data (12-27 for 16bit, 8-27 for 20bit, and 24bit without AUX)
+- *     28   = validity (0 for valid data, else 'in error')
+- *     29   = user data (0)
+- *     30   = channel status (24 bytes for 192 frames)
+- *     31   = parity
++ * bit 0-10  = padding
++ *     11-26 = data
++ *     27    = validity (0 for valid data, else 'in error')
++ *     28    = user data (0)
++ *     29    = channel status (24 bytes for 192 frames)
++ *     30    = parity
++ *     31    = frame start
+  */
+
+ static inline uint32_t iec958_subframe(snd_pcm_iec958_t *iec, uint32_t data, int channel)
+@@ -108,25 +107,19 @@ static inline uint32_t iec958_subframe(snd_pcm_iec958_t *iec, uint32_t data, int
+	unsigned int byte = iec->counter >> 3;
+	unsigned int mask = 1 << (iec->counter - (byte << 3));
+
+-	/* bit 4-27 */
+-	data >>= 4;
+-	data &= ~0xf;
++	data = (data & 0xffff0000) >> 5;
+
+	/* set IEC status bits (up to 192 bits) */
+	if (iec->status[byte] & mask)
++		data |= 0x20000000;
++
++	if (iec958_parity(data))
+		data |= 0x40000000;
+
+-	if (iec958_parity(data))	/* parity bit 4-30 */
++	/* block start */
++	if (!iec->counter)
+		data |= 0x80000000;
+
+-	/* Preamble */
+-	if (channel)
+-		data |= iec->preamble[PREAMBLE_Y];	/* odd sub frame, 'Y' */
+-	else if (! iec->counter)
+-		data |= iec->preamble[PREAMBLE_Z];	/* Block start, 'Z' */
+-	else
+-		data |= iec->preamble[PREAMBLE_X];	/* even sub frame, 'X' */
+-
+	if (iec->byteswap)
+		data = bswap_32(data);
+
+@@ -137,8 +130,7 @@ static inline int32_t iec958_to_s32(snd_pcm_iec958_t *iec, uint32_t data)
+ {
+	if (iec->byteswap)
+		data = bswap_32(data);
+-	data &= ~0xf;
+-	data <<= 4;
++	data <<= 5;
+	return (int32_t)data;
+ }
+
+--
+2.27.0
diff --git a/projects/Rockchip/devices/RK322X/patches/gmp/0001-acinclude.m4-fix-std-c23-build-failure.patch b/projects/Rockchip/devices/RK322X/patches/gmp/0001-acinclude.m4-fix-std-c23-build-failure.patch
new file mode 100644
index 0000000000..9e30509cc2
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/patches/gmp/0001-acinclude.m4-fix-std-c23-build-failure.patch
@@ -0,0 +1,72 @@
+From 396d0ca56134936a8b89cba07518bcf8c4c14dc6 Mon Sep 17 00:00:00 2001
+From: Rudi Heitbaum <rudi@heitbaum.com>
+Date: Tue, 21 Jan 2025 10:18:09 +0000
+Subject: [PATCH V2] acinclude.m4: fix -std=c23 build failure
+
+Add prototype to configure test function as c23 removes unprototyped
+functions.
+
+gcc-15 switched to -std=c23 by default:
+
+    https://gcc.gnu.org/git/?p=gcc.git;a=commitdiff;h=55e3bd376b2214e200fa76d12b67ff259b06c212
+
+As a result `configure` fails with:
+    conftest.c: In function 'f':
+    conftest.c:12:48: error: too many arguments to function 'g'; expected 0, have 6
+       12 | for(i=0;i<1;i++){if(e(got,got,9,d[i].n)==0)h();g(i,d[i].src,d[i].n,got,d[i].want,9);if(d[i].n)h();}}
+          |                                                ^ ~
+    conftest.c:7:6: note: declared here
+        7 | void g(){}
+          |      ^
+
+Upstream: hg log --patch --rev 18477:8e7bb4ae7a18
+Link: https://gmplib.org/list-archives/gmp-bugs/2024-November/005550.html
+Link: https://gmplib.org/list-archives/gmp-devel/2025-January/006281.html
+Signed-off-by: Rudi Heitbaum <rudi@heitbaum.com>
+---
+v2:
+- update prototype to allow type checking
+---
+ acinclude.m4 | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/acinclude.m4 b/acinclude.m4
+index fddb5fb07a..2d41de6328 100644
+--- a/acinclude.m4
++++ b/acinclude.m4
+@@ -609,7 +609,7 @@ GMP_PROG_CC_WORKS_PART([$1], [long long reliability test 1],
+
+ #if defined (__GNUC__) && ! defined (__cplusplus)
+ typedef unsigned long long t1;typedef t1*t2;
+-void g(){}
++void g(int,const t1 *,t1,t1 *,const t1 *,int){}
+ void h(){}
+ static __inline__ t1 e(t2 rp,t2 up,int n,t1 v0)
+ {t1 c,x,r;int i;if(v0){c=1;for(i=1;i<n;i++){x=up[i];r=x+1;rp[i]=r;}}return c;}
+--
+2.43.0
+
+From c32b367226696744ee3a5e5eb4f372f4931c78f1 Mon Sep 17 00:00:00 2001
+From: Rudi Heitbaum <rudi@heitbaum.com>
+Date: Fri, 31 Jan 2025 04:24:59 +0000
+Subject: [PATCH] configure: fix -std=c23 build failure
+
+---
+ configure | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/configure b/configure
+index 7910aa0970..bd4342d124 100755
+--- a/configure
++++ b/configure
+@@ -6568,7 +6568,7 @@ if test "$gmp_prog_cc_works" = yes; then
+
+ #if defined (__GNUC__) && ! defined (__cplusplus)
+ typedef unsigned long long t1;typedef t1*t2;
+-void g(){}
++void g(int i,const t1 *src,t1 n,t1 *got,const t1 *want,int j){}
+ void h(){}
+ static __inline__ t1 e(t2 rp,t2 up,int n,t1 v0)
+ {t1 c,x,r;int i;if(v0){c=1;for(i=1;i<n;i++){x=up[i];r=x+1;rp[i]=r;}}return c;}
+--
+2.43.0
diff --git a/projects/Rockchip/devices/RK322X/patches/kodi-broken/01-24605.patch b/projects/Rockchip/devices/RK322X/patches/kodi-broken/01-24605.patch
new file mode 100644
index 0000000000..00a8e98b18
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/patches/kodi-broken/01-24605.patch
@@ -0,0 +1,817 @@
+From a7283ef2b5e02b29c2fbe7f4d286fb4f8e9a18fc Mon Sep 17 00:00:00 2001
+From: sarbes <sarbes@kodi.tv>
+Date: Wed, 10 Apr 2024 10:26:27 +0200
+Subject: [PATCH] GL: improve text rendering
+
+---
+ .../shaders/GL/1.2/gl_shader_vert_clip.glsl   |  39 ++++++
+ .../shaders/GL/1.2/gl_shader_vert_simple.glsl |  26 ++++
+ .../shaders/GL/1.5/gl_shader_vert_clip.glsl   |  39 ++++++
+ .../shaders/GL/1.5/gl_shader_vert_simple.glsl |  26 ++++
+ .../VideoRenderers/OverlayRendererGL.cpp      |   5 +
+ xbmc/guilib/GUIFont.cpp                       |  16 +--
+ xbmc/guilib/GUIFontTTF.cpp                    |  95 +++++++++++++-
+ xbmc/guilib/GUIFontTTF.h                      |  12 +-
+ xbmc/guilib/GUIFontTTFGL.cpp                  | 118 ++++++++++--------
+ xbmc/guilib/GUIFontTTFGL.h                    |   4 +-
+ xbmc/rendering/gl/GLShader.cpp                |   6 +-
+ xbmc/rendering/gl/GLShader.h                  |   8 +-
+ xbmc/rendering/gl/RenderSystemGL.cpp          |  47 ++++++-
+ xbmc/rendering/gl/RenderSystemGL.h            |   7 +-
+ 14 files changed, 376 insertions(+), 72 deletions(-)
+ create mode 100644 system/shaders/GL/1.2/gl_shader_vert_clip.glsl
+ create mode 100644 system/shaders/GL/1.2/gl_shader_vert_simple.glsl
+ create mode 100644 system/shaders/GL/1.5/gl_shader_vert_clip.glsl
+ create mode 100644 system/shaders/GL/1.5/gl_shader_vert_simple.glsl
+
+diff --git a/system/shaders/GL/1.2/gl_shader_vert_clip.glsl b/system/shaders/GL/1.2/gl_shader_vert_clip.glsl
+new file mode 100644
+index 0000000000000..37d67946f5949
+--- /dev/null
++++ b/system/shaders/GL/1.2/gl_shader_vert_clip.glsl
+@@ -0,0 +1,39 @@
++/*
++ *  Copyright (C) 2024 Team Kodi
++ *  This file is part of Kodi - https://kodi.tv
++ *
++ *  SPDX-License-Identifier: GPL-2.0-or-later
++ *  See LICENSES/README.md for more information.
++ */
++
++#version 120
++
++attribute vec4 m_attrpos;
++attribute vec4 m_attrcol;
++attribute vec4 m_attrcord0;
++attribute vec4 m_attrcord1;
++varying vec4 m_cord0;
++varying vec4 m_cord1;
++varying vec4 m_colour;
++uniform mat4 m_matrix;
++uniform vec4 m_shaderClip;
++uniform vec4 m_cordStep;
++
++// this shader can be used in cases where clipping via glScissor() is not
++// possible (e.g. when rotating). it can't discard triangles, but it may
++// degenerate them.
++
++void main ()
++{
++  // limit the vertices to the clipping area
++  vec4 position = m_attrpos;
++  position.xy = clamp(position.xy, m_shaderClip.xy, m_shaderClip.zw);
++  gl_Position = m_matrix * position;
++
++  // correct texture coordinates for clipped vertices
++  vec2 clipDist = m_attrpos.xy - position.xy;
++  m_cord0.xy = m_attrcord0.xy - clipDist * m_cordStep.xy;
++  m_cord1.xy = m_attrcord1.xy - clipDist * m_cordStep.zw;
++
++  m_colour = m_attrcol;
++}
+diff --git a/system/shaders/GL/1.2/gl_shader_vert_simple.glsl b/system/shaders/GL/1.2/gl_shader_vert_simple.glsl
+new file mode 100644
+index 0000000000000..f06893a0850ed
+--- /dev/null
++++ b/system/shaders/GL/1.2/gl_shader_vert_simple.glsl
+@@ -0,0 +1,26 @@
++/*
++ *  Copyright (C) 2024 Team Kodi
++ *  This file is part of Kodi - https://kodi.tv
++ *
++ *  SPDX-License-Identifier: GPL-2.0-or-later
++ *  See LICENSES/README.md for more information.
++ */
++
++#version 120
++
++attribute vec4 m_attrpos;
++attribute vec4 m_attrcol;
++attribute vec4 m_attrcord0;
++attribute vec4 m_attrcord1;
++varying vec4 m_cord0;
++varying vec4 m_cord1;
++varying vec4 m_colour;
++uniform mat4 m_matrix;
++
++void main ()
++{
++  gl_Position = m_matrix * m_attrpos;
++  m_colour    = m_attrcol;
++  m_cord0     = m_attrcord0;
++  m_cord1     = m_attrcord1;
++}
+diff --git a/system/shaders/GL/1.5/gl_shader_vert_clip.glsl b/system/shaders/GL/1.5/gl_shader_vert_clip.glsl
+new file mode 100644
+index 0000000000000..2fa1c63da13d7
+--- /dev/null
++++ b/system/shaders/GL/1.5/gl_shader_vert_clip.glsl
+@@ -0,0 +1,39 @@
++/*
++ *  Copyright (C) 2024 Team Kodi
++ *  This file is part of Kodi - https://kodi.tv
++ *
++ *  SPDX-License-Identifier: GPL-2.0-or-later
++ *  See LICENSES/README.md for more information.
++ */
++
++#version 150
++
++in vec4 m_attrpos;
++in vec4 m_attrcol;
++in vec4 m_attrcord0;
++in vec4 m_attrcord1;
++out vec4 m_cord0;
++out vec4 m_cord1;
++out vec4 m_colour;
++uniform mat4 m_matrix;
++uniform vec4 m_shaderClip;
++uniform vec4 m_cordStep;
++
++// this shader can be used in cases where clipping via glScissor() is not
++// possible (e.g. when rotating). it can't discard triangles, but it may
++// degenerate them.
++
++void main ()
++{
++  // limit the vertices to the clipping area
++  vec4 position = m_attrpos;
++  position.xy = clamp(position.xy, m_shaderClip.xy, m_shaderClip.zw);
++  gl_Position = m_matrix * position;
++
++  // correct texture coordinates for clipped vertices
++  vec2 clipDist = m_attrpos.xy - position.xy;
++  m_cord0.xy = m_attrcord0.xy - clipDist * m_cordStep.xy;
++  m_cord1.xy = m_attrcord1.xy - clipDist * m_cordStep.zw;
++
++  m_colour = m_attrcol;
++}
+diff --git a/system/shaders/GL/1.5/gl_shader_vert_simple.glsl b/system/shaders/GL/1.5/gl_shader_vert_simple.glsl
+new file mode 100644
+index 0000000000000..9c1552d7a4af9
+--- /dev/null
++++ b/system/shaders/GL/1.5/gl_shader_vert_simple.glsl
+@@ -0,0 +1,26 @@
++/*
++ *  Copyright (C) 2024 Team Kodi
++ *  This file is part of Kodi - https://kodi.tv
++ *
++ *  SPDX-License-Identifier: GPL-2.0-or-later
++ *  See LICENSES/README.md for more information.
++ */
++
++#version 150
++
++in vec4 m_attrpos;
++in vec4 m_attrcol;
++in vec4 m_attrcord0;
++in vec4 m_attrcord1;
++out vec4 m_cord0;
++out vec4 m_cord1;
++out vec4 m_colour;
++uniform mat4 m_matrix;
++
++void main ()
++{
++  gl_Position = m_matrix * m_attrpos;
++  m_colour    = m_attrcol;
++  m_cord0     = m_attrcord0;
++  m_cord1     = m_attrcord1;
++}
+diff --git a/xbmc/cores/VideoPlayer/VideoRenderers/OverlayRendererGL.cpp b/xbmc/cores/VideoPlayer/VideoRenderers/OverlayRendererGL.cpp
+index 3caa28e4bf2a7..8559d22eae223 100644
+--- a/xbmc/cores/VideoPlayer/VideoRenderers/OverlayRendererGL.cpp
++++ b/xbmc/cores/VideoPlayer/VideoRenderers/OverlayRendererGL.cpp
+@@ -293,6 +293,11 @@ void COverlayGlyphGL::Render(SRenderState& state)
+   GLint posLoc  = renderSystem->ShaderGetPos();
+   GLint colLoc  = renderSystem->ShaderGetCol();
+   GLint tex0Loc = renderSystem->ShaderGetCoord0();
++  GLint matrixUniformLoc = renderSystem->ShaderGetMatrix();
++
++  CMatrixGL matrix = glMatrixProject.Get();
++  matrix.MultMatrixf(glMatrixModview.Get());
++  glUniformMatrix4fv(matrixUniformLoc, 1, GL_FALSE, matrix);
+
+   std::vector<VERTEX> vecVertices(6 * m_vertex.size() / 4);
+   VERTEX* vertices = vecVertices.data();
+diff --git a/xbmc/guilib/GUIFont.cpp b/xbmc/guilib/GUIFont.cpp
+index 784dd75971319..bf0c014a0aac4 100644
+--- a/xbmc/guilib/GUIFont.cpp
++++ b/xbmc/guilib/GUIFont.cpp
+@@ -234,18 +234,18 @@ void CGUIFont::DrawScrollingText(float x,
+       shadowColors.emplace_back((renderColor & 0xff000000) != 0 ? shadowColor : 0);
+     for (float dx = -offset; dx < maxWidth; dx += scrollInfo.m_totalWidth)
+     {
+-      m_font->DrawTextInternal(context, x + dx + 1, y + 1, shadowColors, text, alignment,
+-                               textPixelWidth, scroll);
+-      m_font->DrawTextInternal(context, x + dx + scrollInfo.m_textWidth + 1, y + 1, shadowColors,
+-                               scrollInfo.m_suffix, alignment, suffixPixelWidth, scroll);
++      m_font->DrawTextInternal(context, x + 1, y + 1, shadowColors, text, alignment, textPixelWidth,
++                               scroll, dx);
++      m_font->DrawTextInternal(context, x + scrollInfo.m_textWidth + 1, y + 1, shadowColors,
++                               scrollInfo.m_suffix, alignment, suffixPixelWidth, scroll, dx);
+     }
+   }
+   for (float dx = -offset; dx < maxWidth; dx += scrollInfo.m_totalWidth)
+   {
+-    m_font->DrawTextInternal(context, x + dx, y, renderColors, text, alignment, textPixelWidth,
+-                             scroll);
+-    m_font->DrawTextInternal(context, x + dx + scrollInfo.m_textWidth, y, renderColors,
+-                             scrollInfo.m_suffix, alignment, suffixPixelWidth, scroll);
++    m_font->DrawTextInternal(context, x, y, renderColors, text, alignment, textPixelWidth, scroll,
++                             dx);
++    m_font->DrawTextInternal(context, x + scrollInfo.m_textWidth, y, renderColors,
++                             scrollInfo.m_suffix, alignment, suffixPixelWidth, scroll, dx);
+   }
+
+   context.RestoreClipRegion();
+diff --git a/xbmc/guilib/GUIFontTTF.cpp b/xbmc/guilib/GUIFontTTF.cpp
+index 10041f7d61ec8..780f168a30065 100644
+--- a/xbmc/guilib/GUIFontTTF.cpp
++++ b/xbmc/guilib/GUIFontTTF.cpp
+@@ -1,5 +1,5 @@
+ /*
+- *  Copyright (C) 2005-2018 Team Kodi
++ *  Copyright (C) 2005-2024 Team Kodi
+  *  This file is part of Kodi - https://kodi.tv
+  *
+  *  SPDX-License-Identifier: GPL-2.0-or-later
+@@ -339,7 +339,9 @@ void CGUIFontTTF::DrawTextInternal(CGraphicContext& context,
+                                    const vecText& text,
+                                    uint32_t alignment,
+                                    float maxPixelWidth,
+-                                   bool scrolling)
++                                   bool scrolling,
++                                   float dx,
++                                   float dy)
+ {
+   if (text.empty())
+   {
+@@ -349,15 +351,40 @@ void CGUIFontTTF::DrawTextInternal(CGraphicContext& context,
+   Begin();
+   uint32_t rawAlignment = alignment;
+   bool dirtyCache(false);
++
++#if defined(HAS_GL)
++  // round coordinates to the pixel grid. otherwise, we might sample at the wrong positions.
++  if (!scrolling)
++    x = std::round(x);
++  y = std::round(y);
++#else
++  x += dx;
++  y += dy;
++#endif
++
++#if defined(HAS_GL)
++  // GL can scissor and shader clip
++  const bool hardwareClipping = true;
++#else
++  // FIXME: remove static (CPU based) clipping for GLES/DX
+   const bool hardwareClipping = m_renderSystem->ScissorsCanEffectClipping();
++#endif
++
++  // FIXME: remove positional stuff once GLES/DX are brought up to date
+   CGUIFontCacheStaticPosition staticPos(x, y);
+   CGUIFontCacheDynamicPosition dynamicPos;
++
++#if defined(HAS_GL)
++  // dummy positions for the time being
++  dynamicPos = CGUIFontCacheDynamicPosition(0.0f, 0.0f, 0.0f);
++#else
+   if (hardwareClipping)
+   {
+     dynamicPos =
+         CGUIFontCacheDynamicPosition(context.ScaleFinalXCoord(x, y), context.ScaleFinalYCoord(x, y),
+                                      context.ScaleFinalZCoord(x, y));
+   }
++#endif
+
+   CVertexBuffer unusedVertexBuffer;
+   CVertexBuffer& vertexBuffer =
+@@ -388,8 +415,14 @@ void CGUIFontTTF::DrawTextInternal(CGraphicContext& context,
+   {
+     const std::vector<Glyph> glyphs = GetHarfBuzzShapedGlyphs(text);
+     // save the origin, which is scaled separately
++#if defined(HAS_GL)
++    // the origin is now at [0,0], and not at "random" locations anymore. positioning is done in the vertex shader.
++    m_originX = 0;
++    m_originY = 0;
++#else
+     m_originX = x;
+     m_originY = y;
++#endif
+
+     // cache the ellipses width
+     if (!m_ellipseCached)
+@@ -623,7 +656,11 @@ void CGUIFontTTF::DrawTextInternal(CGraphicContext& context,
+                                 scrolling, std::chrono::steady_clock::now(), dirtyCache);
+       CVertexBuffer newVertexBuffer = CreateVertexBuffer(*tempVertices);
+       vertexBuffer = newVertexBuffer;
++#if defined(HAS_GL)
++      m_vertexTrans.emplace_back(x, y, 0.0f, &vertexBuffer, context.GetClipRegion(), dx, dy);
++#else
+       m_vertexTrans.emplace_back(.0f, .0f, .0f, &vertexBuffer, context.GetClipRegion());
++#endif
+     }
+     else
+     {
+@@ -637,8 +674,12 @@ void CGUIFontTTF::DrawTextInternal(CGraphicContext& context,
+   else
+   {
+     if (hardwareClipping)
++#if defined(HAS_GL)
++      m_vertexTrans.emplace_back(x, y, 0.0f, &vertexBuffer, context.GetClipRegion(), dx, dy);
++#else
+       m_vertexTrans.emplace_back(dynamicPos.m_x, dynamicPos.m_y, dynamicPos.m_z, &vertexBuffer,
+                                  context.GetClipRegion());
++#endif
+     else
+       /* Append the vertices from the cache to the set collected since the first Begin() call */
+       m_vertex.insert(m_vertex.end(), vertices->begin(), vertices->end());
+@@ -1044,12 +1085,19 @@ void CGUIFontTTF::RenderCharacter(CGraphicContext& context,
+
+   // posX and posY are relative to our origin, and the textcell is offset
+   // from our (posX, posY).  Plus, these are unscaled quantities compared to the underlying GUI resolution
++#if defined(HAS_GL)
++  CRect vertex((posX + ch->m_offsetX), (posY + ch->m_offsetY), (posX + ch->m_offsetX + width),
++               (posY + ch->m_offsetY + height));
++#else
+   CRect vertex((posX + ch->m_offsetX) * context.GetGUIScaleX(),
+                (posY + ch->m_offsetY) * context.GetGUIScaleY(),
+                (posX + ch->m_offsetX + width) * context.GetGUIScaleX(),
+                (posY + ch->m_offsetY + height) * context.GetGUIScaleY());
+   vertex += CPoint(m_originX, m_originY);
++#endif
+   CRect texture(ch->m_left, ch->m_top, ch->m_right, ch->m_bottom);
++
++#if !defined(HAS_GL)
+   if (!m_renderSystem->ScissorsCanEffectClipping())
+     context.ClipRect(vertex, texture);
+
+@@ -1109,6 +1157,14 @@ void CGUIFontTTF::RenderCharacter(CGraphicContext& context,
+   const float tr = texture.x2 * m_textureScaleX;
+   const float tt = texture.y1 * m_textureScaleY;
+   const float tb = texture.y2 * m_textureScaleY;
++#else
++  // when scaling by shader, we have to grow the vertex and texture coords
++  // by .5 or we would ommit pixels when animating.
++  const float tl = (texture.x1 - .5f) * m_textureScaleX;
++  const float tr = (texture.x2 + .5f) * m_textureScaleX;
++  const float tt = (texture.y1 - .5f) * m_textureScaleY;
++  const float tb = (texture.y2 + .5f) * m_textureScaleY;
++#endif
+
+   vertices.resize(vertices.size() + VERTEX_PER_GLYPH);
+   SVertex* v = &vertices[vertices.size() - VERTEX_PER_GLYPH];
+@@ -1152,8 +1208,41 @@ void CGUIFontTTF::RenderCharacter(CGraphicContext& context,
+
+   v[3].u = tl;
+   v[3].v = tb;
+-#else
++#elif defined(HAS_GL)
+   // GL / GLES uses triangle strips, not quads, so have to rearrange the vertex order
++  // GL uses vertex shaders to manipulate text rotation/translation/scaling/clipping.
++
++  // nudge position to align with raster grid. messes up kerning, but also avoids
++  // linear filtering (when not scaled/rotated).
++  float xOffset = 0.0f;
++  if (roundX)
++    xOffset = (vertex.x1 - std::floor(vertex.x1));
++  float yOffset = (vertex.y1 - std::floor(vertex.y1));
++
++  v[0].u = tl;
++  v[0].v = tt;
++  v[0].x = vertex.x1 - xOffset - 0.5f;
++  v[0].y = vertex.y1 - yOffset - 0.5f;
++  v[0].z = 0;
++
++  v[1].u = tl;
++  v[1].v = tb;
++  v[1].x = vertex.x1 - xOffset - 0.5f;
++  v[1].y = vertex.y2 - yOffset + 0.5f;
++  v[1].z = 0;
++
++  v[2].u = tr;
++  v[2].v = tt;
++  v[2].x = vertex.x2 - xOffset + 0.5f;
++  v[2].y = vertex.y1 - yOffset - 0.5f;
++  v[2].z = 0;
++
++  v[3].u = tr;
++  v[3].v = tb;
++  v[3].x = vertex.x2 - xOffset + 0.5f;
++  v[3].y = vertex.y2 - yOffset + 0.5f;
++  v[3].z = 0;
++#else
+   v[0].u = tl;
+   v[0].v = tt;
+   v[0].x = x[0];
+diff --git a/xbmc/guilib/GUIFontTTF.h b/xbmc/guilib/GUIFontTTF.h
+index 2ed270343d471..02a0ac16df2f6 100644
+--- a/xbmc/guilib/GUIFontTTF.h
++++ b/xbmc/guilib/GUIFontTTF.h
+@@ -164,7 +164,9 @@ class CGUIFontTTF
+                         const vecText& text,
+                         uint32_t alignment,
+                         float maxPixelWidth,
+-                        bool scrolling);
++                        bool scrolling,
++                        float dx = 0.0f,
++                        float dy = 0.0f);
+
+   float m_height{0.0f};
+
+@@ -238,16 +240,22 @@ class CGUIFontTTF
+     float m_translateX;
+     float m_translateY;
+     float m_translateZ;
++    float m_offsetX; // skews the "raw" mesh before applying UI matrix (useful for scrolling)
++    float m_offsetY;
+     const CVertexBuffer* m_vertexBuffer;
+     CRect m_clip;
+     CTranslatedVertices(float translateX,
+                         float translateY,
+                         float translateZ,
+                         const CVertexBuffer* vertexBuffer,
+-                        const CRect& clip)
++                        const CRect& clip,
++                        float offsetX = 0.0f,
++                        float offsetY = 0.0f)
+       : m_translateX(translateX),
+         m_translateY(translateY),
+         m_translateZ(translateZ),
++        m_offsetX(offsetX),
++        m_offsetY(offsetY),
+         m_vertexBuffer(vertexBuffer),
+         m_clip(clip)
+     {
+diff --git a/xbmc/guilib/GUIFontTTFGL.cpp b/xbmc/guilib/GUIFontTTFGL.cpp
+index 12889c9b1dad1..96d230eb15290 100644
+--- a/xbmc/guilib/GUIFontTTFGL.cpp
++++ b/xbmc/guilib/GUIFontTTFGL.cpp
+@@ -1,5 +1,5 @@
+ /*
+- *  Copyright (C) 2005-2018 Team Kodi
++ *  Copyright (C) 2005-2024 Team Kodi
+  *  This file is part of Kodi - https://kodi.tv
+  *
+  *  SPDX-License-Identifier: GPL-2.0-or-later
+@@ -63,7 +63,18 @@ bool CGUIFontTTFGL::FirstBegin()
+     internalFormat = GL_R8;
+   else
+     internalFormat = GL_LUMINANCE;
++
+   renderSystem->EnableShader(ShaderMethodGL::SM_FONTS);
++  if (renderSystem->ScissorsCanEffectClipping())
++  {
++    m_scissorClip = true;
++  }
++  else
++  {
++    m_scissorClip = false;
++    renderSystem->ResetScissors();
++    renderSystem->EnableShader(ShaderMethodGL::SM_FONTS_SHADER_CLIP);
++  }
+
+   if (m_textureStatus == TEXTURE_REALLOCATED)
+   {
+@@ -117,6 +128,9 @@ bool CGUIFontTTFGL::FirstBegin()
+
+ void CGUIFontTTFGL::LastEnd()
+ {
++  // static vertex arrays are not supported anymore
++  assert(m_vertex.empty());
++
+   CWinSystemBase* const winSystem = CServiceBroker::GetWinSystem();
+   if (!winSystem)
+     return;
+@@ -126,7 +140,9 @@ void CGUIFontTTFGL::LastEnd()
+   GLint posLoc = renderSystem->ShaderGetPos();
+   GLint colLoc = renderSystem->ShaderGetCol();
+   GLint tex0Loc = renderSystem->ShaderGetCoord0();
+-  GLint modelLoc = renderSystem->ShaderGetModel();
++  GLint clipUniformLoc = renderSystem->ShaderGetClip();
++  GLint coordStepUniformLoc = renderSystem->ShaderGetCoordStep();
++  GLint matrixUniformLoc = renderSystem->ShaderGetMatrix();
+
+   CreateStaticVertexBuffers();
+
+@@ -135,44 +151,6 @@ void CGUIFontTTFGL::LastEnd()
+   glEnableVertexAttribArray(colLoc);
+   glEnableVertexAttribArray(tex0Loc);
+
+-  if (!m_vertex.empty())
+-  {
+-
+-    // Deal with vertices that had to use software clipping
+-    std::vector<SVertex> vecVertices(6 * (m_vertex.size() / 4));
+-    SVertex* vertices = &vecVertices[0];
+-    for (size_t i = 0; i < m_vertex.size(); i += 4)
+-    {
+-      *vertices++ = m_vertex[i];
+-      *vertices++ = m_vertex[i + 1];
+-      *vertices++ = m_vertex[i + 2];
+-
+-      *vertices++ = m_vertex[i + 1];
+-      *vertices++ = m_vertex[i + 3];
+-      *vertices++ = m_vertex[i + 2];
+-    }
+-    vertices = &vecVertices[0];
+-
+-    GLuint VertexVBO;
+-
+-    glGenBuffers(1, &VertexVBO);
+-    glBindBuffer(GL_ARRAY_BUFFER, VertexVBO);
+-    glBufferData(GL_ARRAY_BUFFER, sizeof(SVertex) * vecVertices.size(), &vecVertices[0],
+-                 GL_STATIC_DRAW);
+-
+-    glVertexAttribPointer(posLoc, 3, GL_FLOAT, GL_FALSE, sizeof(SVertex),
+-                          reinterpret_cast<const GLvoid*>(offsetof(SVertex, x)));
+-    glVertexAttribPointer(colLoc, 4, GL_UNSIGNED_BYTE, GL_TRUE, sizeof(SVertex),
+-                          reinterpret_cast<const GLvoid*>(offsetof(SVertex, r)));
+-    glVertexAttribPointer(tex0Loc, 2, GL_FLOAT, GL_FALSE, sizeof(SVertex),
+-                          reinterpret_cast<const GLvoid*>(offsetof(SVertex, u)));
+-
+-    glDrawArrays(GL_TRIANGLES, 0, vecVertices.size());
+-
+-    glBindBuffer(GL_ARRAY_BUFFER, 0);
+-    glDeleteBuffers(1, &VertexVBO);
+-  }
+-
+   if (!m_vertexTrans.empty())
+   {
+     // Deal with the vertices that can be hardware clipped and therefore translated
+@@ -199,14 +177,55 @@ void CGUIFontTTFGL::LastEnd()
+         // skip empty clip
+         if (clip.IsEmpty())
+           continue;
++      }
++
++      if (m_scissorClip)
++      {
++        // clip using scissors
+         renderSystem->SetScissors(clip);
+       }
++      else
++      {
++        // clip using vertex shader
++        renderSystem->ResetScissors();
++
++        float x1 =
++            m_vertexTrans[i].m_clip.x1 - m_vertexTrans[i].m_translateX - m_vertexTrans[i].m_offsetX;
++        float y1 =
++            m_vertexTrans[i].m_clip.y1 - m_vertexTrans[i].m_translateY - m_vertexTrans[i].m_offsetY;
++        float x2 =
++            m_vertexTrans[i].m_clip.x2 - m_vertexTrans[i].m_translateX - m_vertexTrans[i].m_offsetX;
++        float y2 =
++            m_vertexTrans[i].m_clip.y2 - m_vertexTrans[i].m_translateY - m_vertexTrans[i].m_offsetY;
++
++        glUniform4f(clipUniformLoc, x1, y1, x2, y2);
++
++        // setup texture step
++        float stepX = context.GetGUIScaleX() / (static_cast<float>(m_textureWidth));
++        float stepY = context.GetGUIScaleY() / (static_cast<float>(m_textureHeight));
++        glUniform4f(coordStepUniformLoc, stepX, stepY, 1.0f, 1.0f);
++      }
+
+-      // Apply the translation to the currently active (top-of-stack) model view matrix
+-      glMatrixModview.Push();
+-      glMatrixModview.Get().Translatef(m_vertexTrans[i].m_translateX, m_vertexTrans[i].m_translateY,
+-                                       m_vertexTrans[i].m_translateZ);
+-      glUniformMatrix4fv(modelLoc, 1, GL_FALSE, glMatrixModview.Get());
++      // calculate the fractional offset to the ideal position
++      float fractX =
++          context.ScaleFinalXCoord(m_vertexTrans[i].m_translateX, m_vertexTrans[i].m_translateY);
++      float fractY =
++          context.ScaleFinalYCoord(m_vertexTrans[i].m_translateX, m_vertexTrans[i].m_translateY);
++      fractX = -fractX + std::round(fractX);
++      fractY = -fractY + std::round(fractY);
++
++      // proj * model * gui * scroll * translation * scaling * correction factor
++      CMatrixGL matrix = glMatrixProject.Get();
++      matrix.MultMatrixf(glMatrixModview.Get());
++      matrix.MultMatrixf(CMatrixGL(context.GetGUIMatrix()));
++      matrix.Translatef(m_vertexTrans[i].m_offsetX, m_vertexTrans[i].m_offsetY, 0.0f);
++      matrix.Translatef(m_vertexTrans[i].m_translateX, m_vertexTrans[i].m_translateY, 0.0f);
++      // the gui matrix messes with the scale. correct it here for now.
++      matrix.Scalef(context.GetGUIScaleX(), context.GetGUIScaleY(), 1.0f);
++      // the gui matrix doesn't align to exact pixel coords atm. correct it here for now.
++      matrix.Translatef(fractX, fractY, 0.0f);
++
++      glUniformMatrix4fv(matrixUniformLoc, 1, GL_FALSE, matrix);
+
+       // Bind the buffer to the OpenGL context's GL_ARRAY_BUFFER binding point
+       glBindBuffer(GL_ARRAY_BUFFER, m_vertexTrans[i].m_vertexBuffer->bufferHandle);
+@@ -233,13 +252,12 @@ void CGUIFontTTFGL::LastEnd()
+
+         glDrawElements(GL_TRIANGLES, 6 * count, GL_UNSIGNED_SHORT, 0);
+       }
+-
+-      glMatrixModview.Pop();
+     }
++
+     // Restore the original scissor rectangle
+-    renderSystem->SetScissors(scissor);
+-    // Restore the original model view matrix
+-    glUniformMatrix4fv(modelLoc, 1, GL_FALSE, glMatrixModview.Get());
++    if (m_scissorClip)
++      renderSystem->SetScissors(scissor);
++
+     // Unbind GL_ARRAY_BUFFER and GL_ELEMENT_ARRAY_BUFFER
+     glBindBuffer(GL_ARRAY_BUFFER, 0);
+     glBindBuffer(GL_ELEMENT_ARRAY_BUFFER, 0);
+diff --git a/xbmc/guilib/GUIFontTTFGL.h b/xbmc/guilib/GUIFontTTFGL.h
+index 22fbe6419b81c..e59a54a23c066 100644
+--- a/xbmc/guilib/GUIFontTTFGL.h
++++ b/xbmc/guilib/GUIFontTTFGL.h
+@@ -1,5 +1,5 @@
+ /*
+- *  Copyright (C) 2005-2018 Team Kodi
++ *  Copyright (C) 2005-2024 Team Kodi
+  *  This file is part of Kodi - https://kodi.tv
+  *
+  *  SPDX-License-Identifier: GPL-2.0-or-later
+@@ -55,4 +55,6 @@ class CGUIFontTTFGL : public CGUIFontTTF
+   TextureStatus m_textureStatus{TEXTURE_VOID};
+
+   static bool m_staticVertexBufferCreated;
++
++  bool m_scissorClip{false};
+ };
+diff --git a/xbmc/rendering/gl/GLShader.cpp b/xbmc/rendering/gl/GLShader.cpp
+index e91af97b562c4..77dd6e4ed259e 100644
+--- a/xbmc/rendering/gl/GLShader.cpp
++++ b/xbmc/rendering/gl/GLShader.cpp
+@@ -1,12 +1,11 @@
+ /*
+- *  Copyright (C) 2005-2018 Team Kodi
++ *  Copyright (C) 2005-2024 Team Kodi
+  *  This file is part of Kodi - https://kodi.tv
+  *
+  *  SPDX-License-Identifier: GPL-2.0-or-later
+  *  See LICENSES/README.md for more information.
+  */
+
+-
+ #include "GLShader.h"
+
+ #include "ServiceBroker.h"
+@@ -49,6 +48,9 @@ void CGLShader::OnCompiledAndLinked()
+   // Variables passed directly to the Vertex shader
+   m_hProj = glGetUniformLocation(ProgramHandle(), "m_proj");
+   m_hModel = glGetUniformLocation(ProgramHandle(), "m_model");
++  m_hMatrix = glGetUniformLocation(ProgramHandle(), "m_matrix");
++  m_hShaderClip = glGetUniformLocation(ProgramHandle(), "m_shaderClip");
++  m_hCoordStep = glGetUniformLocation(ProgramHandle(), "m_cordStep");
+
+   // Vertex attributes
+   m_hPos = glGetAttribLocation(ProgramHandle(),  "m_attrpos");
+diff --git a/xbmc/rendering/gl/GLShader.h b/xbmc/rendering/gl/GLShader.h
+index d5b82f3a075b7..791c44926bd7e 100644
+--- a/xbmc/rendering/gl/GLShader.h
++++ b/xbmc/rendering/gl/GLShader.h
+@@ -1,5 +1,5 @@
+ /*
+- *  Copyright (C) 2005-2018 Team Kodi
++ *  Copyright (C) 2005-2024 Team Kodi
+  *  This file is part of Kodi - https://kodi.tv
+  *
+  *  SPDX-License-Identifier: GPL-2.0-or-later
+@@ -27,6 +27,9 @@ class CGLShader : public Shaders::CGLSLShaderProgram
+   GLint GetCord1Loc() {return m_hCord1;}
+   GLint GetUniColLoc() {return m_hUniCol;}
+   GLint GetModelLoc() {return m_hModel; }
++  GLint GetMatrixLoc() { return m_hMatrix; }
++  GLint GetShaderClipLoc() { return m_hShaderClip; }
++  GLint GetShaderCoordStepLoc() { return m_hCoordStep; }
+   bool HardwareClipIsPossible() {return m_clipPossible; }
+   GLfloat GetClipXFactor() {return m_clipXFactor; }
+   GLfloat GetClipXOffset() {return m_clipXOffset; }
+@@ -39,6 +42,9 @@ class CGLShader : public Shaders::CGLSLShaderProgram
+   GLint m_hUniCol = 0;
+   GLint m_hProj = 0;
+   GLint m_hModel = 0;
++  GLint m_hMatrix{0}; // m_hProj * m_hModel
++  GLint m_hShaderClip{0}; // clipping rect vec4(x1,y1,x2,y2)
++  GLint m_hCoordStep{0}; // step (1/resolution) for the two textures vec4(t1.x,t1.y,t2.x,t2.y)
+   GLint m_hPos = 0;
+   GLint m_hCol = 0;
+   GLint m_hCord0 = 0;
+diff --git a/xbmc/rendering/gl/RenderSystemGL.cpp b/xbmc/rendering/gl/RenderSystemGL.cpp
+index 4b80014d41386..516027ef49134 100644
+--- a/xbmc/rendering/gl/RenderSystemGL.cpp
++++ b/xbmc/rendering/gl/RenderSystemGL.cpp
+@@ -1,5 +1,5 @@
+ /*
+- *  Copyright (C) 2005-2018 Team Kodi
++ *  Copyright (C) 2005-2024 Team Kodi
+  *  This file is part of Kodi - https://kodi.tv
+  *
+  *  SPDX-License-Identifier: GPL-2.0-or-later
+@@ -682,13 +682,24 @@ void CRenderSystemGL::InitialiseShaders()
+     CLog::Log(LOGERROR, "GUI Shader gl_shader_frag_multi.glsl - compile and link failed");
+   }
+
+-  m_pShader[ShaderMethodGL::SM_FONTS] =
+-      std::make_unique<CGLShader>("gl_shader_frag_fonts.glsl", defines);
++  m_pShader[ShaderMethodGL::SM_FONTS] = std::make_unique<CGLShader>(
++      "gl_shader_vert_simple.glsl", "gl_shader_frag_fonts.glsl", defines);
+   if (!m_pShader[ShaderMethodGL::SM_FONTS]->CompileAndLink())
+   {
+     m_pShader[ShaderMethodGL::SM_FONTS]->Free();
+     m_pShader[ShaderMethodGL::SM_FONTS].reset();
+-    CLog::Log(LOGERROR, "GUI Shader gl_shader_frag_fonts.glsl - compile and link failed");
++    CLog::Log(LOGERROR, "GUI Shader gl_shader_vert_simple.glsl + gl_shader_frag_fonts.glsl - "
++                        "compile and link failed");
++  }
++
++  m_pShader[ShaderMethodGL::SM_FONTS_SHADER_CLIP] =
++      std::make_unique<CGLShader>("gl_shader_vert_clip.glsl", "gl_shader_frag_fonts.glsl", defines);
++  if (!m_pShader[ShaderMethodGL::SM_FONTS_SHADER_CLIP]->CompileAndLink())
++  {
++    m_pShader[ShaderMethodGL::SM_FONTS_SHADER_CLIP]->Free();
++    m_pShader[ShaderMethodGL::SM_FONTS_SHADER_CLIP].reset();
++    CLog::Log(LOGERROR, "GUI Shader gl_shader_vert_clip.glsl + gl_shader_frag_fonts.glsl - compile "
++                        "and link failed");
+   }
+
+   m_pShader[ShaderMethodGL::SM_TEXTURE_NOBLEND] =
+@@ -732,6 +743,10 @@ void CRenderSystemGL::ReleaseShaders()
+     m_pShader[ShaderMethodGL::SM_FONTS]->Free();
+   m_pShader[ShaderMethodGL::SM_FONTS].reset();
+
++  if (m_pShader[ShaderMethodGL::SM_FONTS_SHADER_CLIP])
++    m_pShader[ShaderMethodGL::SM_FONTS_SHADER_CLIP]->Free();
++  m_pShader[ShaderMethodGL::SM_FONTS_SHADER_CLIP].reset();
++
+   if (m_pShader[ShaderMethodGL::SM_TEXTURE_NOBLEND])
+     m_pShader[ShaderMethodGL::SM_TEXTURE_NOBLEND]->Free();
+   m_pShader[ShaderMethodGL::SM_TEXTURE_NOBLEND].reset();
+@@ -811,6 +826,30 @@ GLint CRenderSystemGL::ShaderGetModel()
+   return -1;
+ }
+
++GLint CRenderSystemGL::ShaderGetMatrix()
++{
++  if (m_pShader[m_method])
++    return m_pShader[m_method]->GetMatrixLoc();
++
++  return -1;
++}
++
++GLint CRenderSystemGL::ShaderGetClip()
++{
++  if (m_pShader[m_method])
++    return m_pShader[m_method]->GetShaderClipLoc();
++
++  return -1;
++}
++
++GLint CRenderSystemGL::ShaderGetCoordStep()
++{
++  if (m_pShader[m_method])
++    return m_pShader[m_method]->GetShaderCoordStepLoc();
++
++  return -1;
++}
++
+ std::string CRenderSystemGL::GetShaderPath(const std::string &filename)
+ {
+   std::string path = "GL/1.2/";
+diff --git a/xbmc/rendering/gl/RenderSystemGL.h b/xbmc/rendering/gl/RenderSystemGL.h
+index 191c97ff961fc..520c552e45ab5 100644
+--- a/xbmc/rendering/gl/RenderSystemGL.h
++++ b/xbmc/rendering/gl/RenderSystemGL.h
+@@ -1,5 +1,5 @@
+ /*
+- *  Copyright (C) 2005-2018 Team Kodi
++ *  Copyright (C) 2005-2024 Team Kodi
+  *  This file is part of Kodi - https://kodi.tv
+  *
+  *  SPDX-License-Identifier: GPL-2.0-or-later
+@@ -27,6 +27,7 @@ enum class ShaderMethodGL
+   SM_TEXTURE_LIM,
+   SM_MULTI,
+   SM_FONTS,
++  SM_FONTS_SHADER_CLIP,
+   SM_TEXTURE_NOBLEND,
+   SM_MULTI_BLENDCOLOR,
+   SM_MAX
+@@ -52,6 +53,7 @@ struct fmt::formatter<ShaderMethodGL> : fmt::formatter<std::string_view>
+       {ShaderMethodGL::SM_TEXTURE_LIM, "texture limited"},
+       {ShaderMethodGL::SM_MULTI, "multi"},
+       {ShaderMethodGL::SM_FONTS, "fonts"},
++      {ShaderMethodGL::SM_FONTS_SHADER_CLIP, "fonts with vertex shader based clipping"},
+       {ShaderMethodGL::SM_TEXTURE_NOBLEND, "texture no blending"},
+       {ShaderMethodGL::SM_MULTI_BLENDCOLOR, "multi blend colour"},
+   });
+@@ -114,6 +116,9 @@ class CRenderSystemGL : public CRenderSystemBase
+   GLint ShaderGetCoord1();
+   GLint ShaderGetUniCol();
+   GLint ShaderGetModel();
++  GLint ShaderGetMatrix();
++  GLint ShaderGetClip();
++  GLint ShaderGetCoordStep();
+
+ protected:
+   virtual void SetVSyncImpl(bool enable) = 0;
diff --git a/projects/Rockchip/devices/RK322X/patches/kodi-broken/01-25033.patch b/projects/Rockchip/devices/RK322X/patches/kodi-broken/01-25033.patch
new file mode 100644
index 0000000000..294c73a8ed
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/patches/kodi-broken/01-25033.patch
@@ -0,0 +1,527 @@
+From 5b73d31eadd3f38b24d045e2a10b47b0052b3620 Mon Sep 17 00:00:00 2001
+From: sarbes <sarbes@kodi.tv>
+Date: Sun, 21 Apr 2024 01:50:36 +0200
+Subject: [PATCH] GLES: Add font shader clipping
+
+---
+ system/shaders/GLES/2.0/gles_shader_clip.vert |  39 +++++++
+ .../shaders/GLES/2.0/gles_shader_simple.vert  |  26 +++++
+ .../VideoRenderers/OverlayRendererGLES.cpp    |   5 +
+ xbmc/guilib/GUIFontTTF.cpp                    |  42 ++------
+ xbmc/guilib/GUIFontTTFGLES.cpp                | 102 +++++++++++-------
+ xbmc/guilib/GUIFontTTFGLES.h                  |   1 +
+ xbmc/rendering/gles/GLESShader.cpp            |   3 +
+ xbmc/rendering/gles/GLESShader.h              |   6 ++
+ xbmc/rendering/gles/RenderSystemGLES.cpp      |  40 ++++++-
+ xbmc/rendering/gles/RenderSystemGLES.h        |   5 +
+ 10 files changed, 197 insertions(+), 72 deletions(-)
+ create mode 100644 system/shaders/GLES/2.0/gles_shader_clip.vert
+ create mode 100644 system/shaders/GLES/2.0/gles_shader_simple.vert
+
+diff --git a/system/shaders/GLES/2.0/gles_shader_clip.vert b/system/shaders/GLES/2.0/gles_shader_clip.vert
+new file mode 100644
+index 0000000000000..513a24456c7df
+--- /dev/null
++++ b/system/shaders/GLES/2.0/gles_shader_clip.vert
+@@ -0,0 +1,39 @@
++/*
++ *  Copyright (C) 2024 Team Kodi
++ *  This file is part of Kodi - https://kodi.tv
++ *
++ *  SPDX-License-Identifier: GPL-2.0-or-later
++ *  See LICENSES/README.md for more information.
++ */
++
++#version 100
++
++attribute vec4 m_attrpos;
++attribute vec4 m_attrcol;
++attribute vec4 m_attrcord0;
++attribute vec4 m_attrcord1;
++varying vec4 m_cord0;
++varying vec4 m_cord1;
++varying vec4 m_colour;
++uniform mat4 m_matrix;
++uniform vec4 m_shaderClip;
++uniform vec4 m_cordStep;
++
++// this shader can be used in cases where clipping via glScissor() is not
++// possible (e.g. when rotating). it can't discard triangles, but it may
++// degenerate them.
++
++void main()
++{
++  // limit the vertices to the clipping area
++  vec4 position = m_attrpos;
++  position.xy = clamp(position.xy, m_shaderClip.xy, m_shaderClip.zw);
++  gl_Position = m_matrix * position;
++
++  // correct texture coordinates for clipped vertices
++  vec2 clipDist = m_attrpos.xy - position.xy;
++  m_cord0.xy = m_attrcord0.xy - clipDist * m_cordStep.xy;
++  m_cord1.xy = m_attrcord1.xy - clipDist * m_cordStep.zw;
++
++  m_colour = m_attrcol;
++}
+diff --git a/system/shaders/GLES/2.0/gles_shader_simple.vert b/system/shaders/GLES/2.0/gles_shader_simple.vert
+new file mode 100644
+index 0000000000000..6d49788b65f87
+--- /dev/null
++++ b/system/shaders/GLES/2.0/gles_shader_simple.vert
+@@ -0,0 +1,26 @@
++/*
++ *  Copyright (C) 2024 Team Kodi
++ *  This file is part of Kodi - https://kodi.tv
++ *
++ *  SPDX-License-Identifier: GPL-2.0-or-later
++ *  See LICENSES/README.md for more information.
++ */
++
++#version 100
++
++attribute vec4 m_attrpos;
++attribute vec4 m_attrcol;
++attribute vec4 m_attrcord0;
++attribute vec4 m_attrcord1;
++varying vec4 m_cord0;
++varying vec4 m_cord1;
++varying vec4 m_colour;
++uniform mat4 m_matrix;
++
++void main()
++{
++  gl_Position = m_matrix * m_attrpos;
++  m_colour    = m_attrcol;
++  m_cord0     = m_attrcord0;
++  m_cord1     = m_attrcord1;
++}
+diff --git a/xbmc/cores/VideoPlayer/VideoRenderers/OverlayRendererGLES.cpp b/xbmc/cores/VideoPlayer/VideoRenderers/OverlayRendererGLES.cpp
+index cf3b31324add0..237afacc42c3a 100644
+--- a/xbmc/cores/VideoPlayer/VideoRenderers/OverlayRendererGLES.cpp
++++ b/xbmc/cores/VideoPlayer/VideoRenderers/OverlayRendererGLES.cpp
+@@ -352,6 +352,11 @@ void COverlayGlyphGLES::Render(SRenderState& state)
+   GLint posLoc = renderSystem->GUIShaderGetPos();
+   GLint colLoc = renderSystem->GUIShaderGetCol();
+   GLint tex0Loc = renderSystem->GUIShaderGetCoord0();
++  GLint matrixUniformLoc = renderSystem->GUIShaderGetMatrix();
++
++  CMatrixGL matrix = glMatrixProject.Get();
++  matrix.MultMatrixf(glMatrixModview.Get());
++  glUniformMatrix4fv(matrixUniformLoc, 1, GL_FALSE, matrix);
+
+   // stack object until VBOs will be used
+   std::vector<VERTEX> vecVertices(6 * m_vertex.size() / 4);
+diff --git a/xbmc/guilib/GUIFontTTF.cpp b/xbmc/guilib/GUIFontTTF.cpp
+index d19c1f0a3ffb3..ff11db14f899c 100644
+--- a/xbmc/guilib/GUIFontTTF.cpp
++++ b/xbmc/guilib/GUIFontTTF.cpp
+@@ -382,7 +382,7 @@ void CGUIFontTTF::DrawTextInternal(CGraphicContext& context,
+   uint32_t rawAlignment = alignment;
+   bool dirtyCache(false);
+
+-#if defined(HAS_GL)
++#if not defined(HAS_DX)
+   // round coordinates to the pixel grid. otherwise, we might sample at the wrong positions.
+   if (!scrolling)
+     x = std::round(x);
+@@ -392,7 +392,7 @@ void CGUIFontTTF::DrawTextInternal(CGraphicContext& context,
+   y += dy;
+ #endif
+
+-#if defined(HAS_GL)
++#if not defined(HAS_DX)
+   // GL can scissor and shader clip
+   const bool hardwareClipping = true;
+ #else
+@@ -404,7 +404,7 @@ void CGUIFontTTF::DrawTextInternal(CGraphicContext& context,
+   CGUIFontCacheStaticPosition staticPos(x, y);
+   CGUIFontCacheDynamicPosition dynamicPos;
+
+-#if defined(HAS_GL)
++#if not defined(HAS_DX)
+   // dummy positions for the time being
+   dynamicPos = CGUIFontCacheDynamicPosition(0.0f, 0.0f, 0.0f);
+ #else
+@@ -452,7 +452,7 @@ void CGUIFontTTF::DrawTextInternal(CGraphicContext& context,
+
+     const std::vector<Glyph> glyphs = GetHarfBuzzShapedGlyphs(text);
+     // save the origin, which is scaled separately
+-#if defined(HAS_GL)
++#if not defined(HAS_DX)
+     // the origin is now at [0,0], and not at "random" locations anymore. positioning is done in the vertex shader.
+     m_originX = 0;
+     m_originY = 0;
+@@ -710,7 +710,7 @@ void CGUIFontTTF::DrawTextInternal(CGraphicContext& context,
+                                 scrolling, std::chrono::steady_clock::now(), dirtyCache);
+       CVertexBuffer newVertexBuffer = CreateVertexBuffer(*tempVertices);
+       vertexBuffer = newVertexBuffer;
+-#if defined(HAS_GL)
++#if not defined(HAS_DX)
+       m_vertexTrans.emplace_back(x, y, 0.0f, &vertexBuffer, context.GetClipRegion(), dx, dy);
+ #else
+       m_vertexTrans.emplace_back(.0f, .0f, .0f, &vertexBuffer, context.GetClipRegion());
+@@ -728,7 +728,7 @@ void CGUIFontTTF::DrawTextInternal(CGraphicContext& context,
+   else
+   {
+     if (hardwareClipping)
+-#if defined(HAS_GL)
++#if not defined(HAS_DX)
+       m_vertexTrans.emplace_back(x, y, 0.0f, &vertexBuffer, context.GetClipRegion(), dx, dy);
+ #else
+       m_vertexTrans.emplace_back(dynamicPos.m_x, dynamicPos.m_y, dynamicPos.m_z, &vertexBuffer,
+@@ -1139,7 +1139,7 @@ void CGUIFontTTF::RenderCharacter(CGraphicContext& context,
+
+   // posX and posY are relative to our origin, and the textcell is offset
+   // from our (posX, posY).  Plus, these are unscaled quantities compared to the underlying GUI resolution
+-#if defined(HAS_GL)
++#if not defined(HAS_DX)
+   CRect vertex((posX + ch->m_offsetX), (posY + ch->m_offsetY), (posX + ch->m_offsetX + width),
+                (posY + ch->m_offsetY + height));
+ #else
+@@ -1151,7 +1151,7 @@ void CGUIFontTTF::RenderCharacter(CGraphicContext& context,
+ #endif
+   CRect texture(ch->m_left, ch->m_top, ch->m_right, ch->m_bottom);
+
+-#if !defined(HAS_GL)
++#if defined(HAS_DX)
+   if (!m_renderSystem->ScissorsCanEffectClipping())
+     context.ClipRect(vertex, texture);
+
+@@ -1262,7 +1262,7 @@ void CGUIFontTTF::RenderCharacter(CGraphicContext& context,
+
+   v[3].u = tl;
+   v[3].v = tb;
+-#elif defined(HAS_GL)
++#else
+   // GL / GLES uses triangle strips, not quads, so have to rearrange the vertex order
+   // GL uses vertex shaders to manipulate text rotation/translation/scaling/clipping.
+
+@@ -1296,30 +1296,6 @@ void CGUIFontTTF::RenderCharacter(CGraphicContext& context,
+   v[3].x = vertex.x2 - xOffset + 0.5f;
+   v[3].y = vertex.y2 - yOffset + 0.5f;
+   v[3].z = 0;
+-#else
+-  v[0].u = tl;
+-  v[0].v = tt;
+-  v[0].x = x[0];
+-  v[0].y = y[0];
+-  v[0].z = z[0];
+-
+-  v[1].u = tl;
+-  v[1].v = tb;
+-  v[1].x = x[3];
+-  v[1].y = y[3];
+-  v[1].z = z[3];
+-
+-  v[2].u = tr;
+-  v[2].v = tt;
+-  v[2].x = x[1];
+-  v[2].y = y[1];
+-  v[2].z = z[1];
+-
+-  v[3].u = tr;
+-  v[3].v = tb;
+-  v[3].x = x[2];
+-  v[3].y = y[2];
+-  v[3].z = z[2];
+ #endif
+ }
+
+diff --git a/xbmc/guilib/GUIFontTTFGLES.cpp b/xbmc/guilib/GUIFontTTFGLES.cpp
+index c00a6013192d3..67cceae441c62 100644
+--- a/xbmc/guilib/GUIFontTTFGLES.cpp
++++ b/xbmc/guilib/GUIFontTTFGLES.cpp
+@@ -62,6 +62,17 @@ bool CGUIFontTTFGLES::FirstBegin()
+   GLenum pixformat = GL_ALPHA; // deprecated
+   GLenum internalFormat = GL_ALPHA;
+
++  if (renderSystem->ScissorsCanEffectClipping())
++  {
++    m_scissorClip = true;
++  }
++  else
++  {
++    m_scissorClip = false;
++    renderSystem->ResetScissors();
++    renderSystem->EnableGUIShader(ShaderMethodGLES::SM_FONTS_SHADER_CLIP);
++  }
++
+   if (m_textureStatus == TEXTURE_REALLOCATED)
+   {
+     if (glIsTexture(m_nTexture))
+@@ -124,6 +135,9 @@ bool CGUIFontTTFGLES::FirstBegin()
+
+ void CGUIFontTTFGLES::LastEnd()
+ {
++  // static vertex arrays are not supported anymore
++  assert(m_vertex.empty());
++
+   CWinSystemBase* const winSystem = CServiceBroker::GetWinSystem();
+   if (!winSystem)
+     return;
+@@ -134,7 +148,9 @@ void CGUIFontTTFGLES::LastEnd()
+   GLint posLoc = renderSystem->GUIShaderGetPos();
+   GLint colLoc = renderSystem->GUIShaderGetCol();
+   GLint tex0Loc = renderSystem->GUIShaderGetCoord0();
+-  GLint modelLoc = renderSystem->GUIShaderGetModel();
++  GLint clipUniformLoc = renderSystem->GUIShaderGetClip();
++  GLint coordStepUniformLoc = renderSystem->GUIShaderGetCoordStep();
++  GLint matrixUniformLoc = renderSystem->GUIShaderGetMatrix();
+
+   CreateStaticVertexBuffers();
+
+@@ -143,35 +159,6 @@ void CGUIFontTTFGLES::LastEnd()
+   glEnableVertexAttribArray(colLoc);
+   glEnableVertexAttribArray(tex0Loc);
+
+-  if (!m_vertex.empty())
+-  {
+-    // Deal with vertices that had to use software clipping
+-    std::vector<SVertex> vecVertices(6 * (m_vertex.size() / 4));
+-    SVertex* vertices = &vecVertices[0];
+-
+-    for (size_t i = 0; i < m_vertex.size(); i += 4)
+-    {
+-      *vertices++ = m_vertex[i];
+-      *vertices++ = m_vertex[i + 1];
+-      *vertices++ = m_vertex[i + 2];
+-
+-      *vertices++ = m_vertex[i + 1];
+-      *vertices++ = m_vertex[i + 3];
+-      *vertices++ = m_vertex[i + 2];
+-    }
+-
+-    vertices = &vecVertices[0];
+-
+-    glVertexAttribPointer(posLoc, 3, GL_FLOAT, GL_FALSE, sizeof(SVertex),
+-                          reinterpret_cast<char*>(vertices) + offsetof(SVertex, x));
+-    glVertexAttribPointer(colLoc, 4, GL_UNSIGNED_BYTE, GL_TRUE, sizeof(SVertex),
+-                          reinterpret_cast<char*>(vertices) + offsetof(SVertex, r));
+-    glVertexAttribPointer(tex0Loc, 2, GL_FLOAT, GL_FALSE, sizeof(SVertex),
+-                          reinterpret_cast<char*>(vertices) + offsetof(SVertex, u));
+-
+-    glDrawArrays(GL_TRIANGLES, 0, vecVertices.size());
+-  }
+-
+   if (!m_vertexTrans.empty())
+   {
+     // Deal with the vertices that can be hardware clipped and therefore translated
+@@ -198,14 +185,54 @@ void CGUIFontTTFGLES::LastEnd()
+         // skip empty clip
+         if (clip.IsEmpty())
+           continue;
++      }
++      if (m_scissorClip)
++      {
++        // clip using scissors
+         renderSystem->SetScissors(clip);
+       }
++      else
++      {
++        // clip using vertex shader
++        renderSystem->ResetScissors();
++
++        float x1 =
++            m_vertexTrans[i].m_clip.x1 - m_vertexTrans[i].m_translateX - m_vertexTrans[i].m_offsetX;
++        float y1 =
++            m_vertexTrans[i].m_clip.y1 - m_vertexTrans[i].m_translateY - m_vertexTrans[i].m_offsetY;
++        float x2 =
++            m_vertexTrans[i].m_clip.x2 - m_vertexTrans[i].m_translateX - m_vertexTrans[i].m_offsetX;
++        float y2 =
++            m_vertexTrans[i].m_clip.y2 - m_vertexTrans[i].m_translateY - m_vertexTrans[i].m_offsetY;
++
++        glUniform4f(clipUniformLoc, x1, y1, x2, y2);
++
++        // setup texture step
++        float stepX = context.GetGUIScaleX() / (static_cast<float>(m_textureWidth));
++        float stepY = context.GetGUIScaleY() / (static_cast<float>(m_textureHeight));
++        glUniform4f(coordStepUniformLoc, stepX, stepY, 1.0f, 1.0f);
++      }
+
+-      // Apply the translation to the currently active (top-of-stack) model view matrix
+-      glMatrixModview.Push();
+-      glMatrixModview.Get().Translatef(m_vertexTrans[i].m_translateX, m_vertexTrans[i].m_translateY,
+-                                       m_vertexTrans[i].m_translateZ);
+-      glUniformMatrix4fv(modelLoc, 1, GL_FALSE, glMatrixModview.Get());
++      // calculate the fractional offset to the ideal position
++      float fractX =
++          context.ScaleFinalXCoord(m_vertexTrans[i].m_translateX, m_vertexTrans[i].m_translateY);
++      float fractY =
++          context.ScaleFinalYCoord(m_vertexTrans[i].m_translateX, m_vertexTrans[i].m_translateY);
++      fractX = -fractX + std::round(fractX);
++      fractY = -fractY + std::round(fractY);
++
++      // proj * model * gui * scroll * translation * scaling * correction factor
++      CMatrixGL matrix = glMatrixProject.Get();
++      matrix.MultMatrixf(glMatrixModview.Get());
++      matrix.MultMatrixf(CMatrixGL(context.GetGUIMatrix()));
++      matrix.Translatef(m_vertexTrans[i].m_offsetX, m_vertexTrans[i].m_offsetY, 0.0f);
++      matrix.Translatef(m_vertexTrans[i].m_translateX, m_vertexTrans[i].m_translateY, 0.0f);
++      // the gui matrix messes with the scale. correct it here for now.
++      matrix.Scalef(context.GetGUIScaleX(), context.GetGUIScaleY(), 1.0f);
++      // the gui matrix doesn't align to exact pixel coords atm. correct it here for now.
++      matrix.Translatef(fractX, fractY, 0.0f);
++
++      glUniformMatrix4fv(matrixUniformLoc, 1, GL_FALSE, matrix);
+
+       // Bind the buffer to the OpenGL context's GL_ARRAY_BUFFER binding point
+       glBindBuffer(GL_ARRAY_BUFFER, m_vertexTrans[i].m_vertexBuffer->bufferHandle);
+@@ -236,9 +263,8 @@ void CGUIFontTTFGLES::LastEnd()
+       glMatrixModview.Pop();
+     }
+     // Restore the original scissor rectangle
+-    renderSystem->SetScissors(scissor);
+-    // Restore the original model view matrix
+-    glUniformMatrix4fv(modelLoc, 1, GL_FALSE, glMatrixModview.Get());
++    if (m_scissorClip)
++      renderSystem->SetScissors(scissor);
+     // Unbind GL_ARRAY_BUFFER and GL_ELEMENT_ARRAY_BUFFER
+     glBindBuffer(GL_ARRAY_BUFFER, 0);
+     glBindBuffer(GL_ELEMENT_ARRAY_BUFFER, 0);
+diff --git a/xbmc/guilib/GUIFontTTFGLES.h b/xbmc/guilib/GUIFontTTFGLES.h
+index ae03da74e6aa6..264d1a7611fa7 100644
+--- a/xbmc/guilib/GUIFontTTFGLES.h
++++ b/xbmc/guilib/GUIFontTTFGLES.h
+@@ -55,4 +55,5 @@ class CGUIFontTTFGLES : public CGUIFontTTF
+   TextureStatus m_textureStatus{TEXTURE_VOID};
+
+   static bool m_staticVertexBufferCreated;
++  bool m_scissorClip{false};
+ };
+diff --git a/xbmc/rendering/gles/GLESShader.cpp b/xbmc/rendering/gles/GLESShader.cpp
+index 961c3f79613d6..ba7b83175d57d 100644
+--- a/xbmc/rendering/gles/GLESShader.cpp
++++ b/xbmc/rendering/gles/GLESShader.cpp
+@@ -54,6 +54,9 @@ void CGLESShader::OnCompiledAndLinked()
+   m_hProj  = glGetUniformLocation(ProgramHandle(), "m_proj");
+   m_hModel = glGetUniformLocation(ProgramHandle(), "m_model");
+   m_hCoord0Matrix = glGetUniformLocation(ProgramHandle(), "m_coord0Matrix");
++  m_hMatrix = glGetUniformLocation(ProgramHandle(), "m_matrix");
++  m_hShaderClip = glGetUniformLocation(ProgramHandle(), "m_shaderClip");
++  m_hCoordStep = glGetUniformLocation(ProgramHandle(), "m_cordStep");
+
+   // Vertex attributes
+   m_hPos    = glGetAttribLocation(ProgramHandle(),  "m_attrpos");
+diff --git a/xbmc/rendering/gles/GLESShader.h b/xbmc/rendering/gles/GLESShader.h
+index 1f59895740872..ddc31202c531c 100644
+--- a/xbmc/rendering/gles/GLESShader.h
++++ b/xbmc/rendering/gles/GLESShader.h
+@@ -32,6 +32,9 @@ class CGLESShader : public Shaders::CGLSLShaderProgram
+   GLint GetContrastLoc() { return m_hContrast; }
+   GLint GetBrightnessLoc() { return m_hBrightness; }
+   GLint GetModelLoc() { return m_hModel; }
++  GLint GetMatrixLoc() { return m_hMatrix; }
++  GLint GetShaderClipLoc() { return m_hShaderClip; }
++  GLint GetShaderCoordStepLoc() { return m_hCoordStep; }
+   bool HardwareClipIsPossible() { return m_clipPossible; }
+   GLfloat GetClipXFactor() { return m_clipXFactor; }
+   GLfloat GetClipXOffset() { return m_clipXOffset; }
+@@ -44,6 +47,9 @@ class CGLESShader : public Shaders::CGLSLShaderProgram
+   GLint m_hUniCol = 0;
+   GLint m_hProj = 0;
+   GLint m_hModel = 0;
++  GLint m_hMatrix{0}; // m_hProj * m_hModel
++  GLint m_hShaderClip{0}; // clipping rect vec4(x1,y1,x2,y2)
++  GLint m_hCoordStep{0}; // step (1/resolution) for the two textures vec4(t1.x,t1.y,t2.x,t2.y)
+   GLint m_hPos = 0;
+   GLint m_hCol = 0;
+   GLint m_hCord0 = 0;
+diff --git a/xbmc/rendering/gles/RenderSystemGLES.cpp b/xbmc/rendering/gles/RenderSystemGLES.cpp
+index f25f783960191..a5c02803b0145 100644
+--- a/xbmc/rendering/gles/RenderSystemGLES.cpp
++++ b/xbmc/rendering/gles/RenderSystemGLES.cpp
+@@ -425,7 +425,7 @@ void CRenderSystemGLES::InitialiseShaders()
+   }
+
+   m_pShader[ShaderMethodGLES::SM_FONTS] =
+-      std::make_unique<CGLESShader>("gles_shader_fonts.frag", defines);
++      std::make_unique<CGLESShader>("gles_shader_simple.vert", "gles_shader_fonts.frag", defines);
+   if (!m_pShader[ShaderMethodGLES::SM_FONTS]->CompileAndLink())
+   {
+     m_pShader[ShaderMethodGLES::SM_FONTS]->Free();
+@@ -433,6 +433,16 @@ void CRenderSystemGLES::InitialiseShaders()
+     CLog::Log(LOGERROR, "GUI Shader gles_shader_fonts.frag - compile and link failed");
+   }
+
++  m_pShader[ShaderMethodGLES::SM_FONTS_SHADER_CLIP] =
++      std::make_unique<CGLESShader>("gles_shader_clip.vert", "gles_shader_fonts.frag", defines);
++  if (!m_pShader[ShaderMethodGLES::SM_FONTS_SHADER_CLIP]->CompileAndLink())
++  {
++    m_pShader[ShaderMethodGLES::SM_FONTS_SHADER_CLIP]->Free();
++    m_pShader[ShaderMethodGLES::SM_FONTS_SHADER_CLIP].reset();
++    CLog::Log(LOGERROR, "GUI Shader gles_shader_clip.vert + gles_shader_fonts.frag - compile "
++                        "and link failed");
++  }
++
+   m_pShader[ShaderMethodGLES::SM_TEXTURE_NOBLEND] =
+       std::make_unique<CGLESShader>("gles_shader_texture_noblend.frag", defines);
+   if (!m_pShader[ShaderMethodGLES::SM_TEXTURE_NOBLEND]->CompileAndLink())
+@@ -528,6 +538,10 @@ void CRenderSystemGLES::ReleaseShaders()
+     m_pShader[ShaderMethodGLES::SM_FONTS]->Free();
+   m_pShader[ShaderMethodGLES::SM_FONTS].reset();
+
++  if (m_pShader[ShaderMethodGLES::SM_FONTS_SHADER_CLIP])
++    m_pShader[ShaderMethodGLES::SM_FONTS_SHADER_CLIP]->Free();
++  m_pShader[ShaderMethodGLES::SM_FONTS_SHADER_CLIP].reset();
++
+   if (m_pShader[ShaderMethodGLES::SM_TEXTURE_NOBLEND])
+     m_pShader[ShaderMethodGLES::SM_TEXTURE_NOBLEND]->Free();
+   m_pShader[ShaderMethodGLES::SM_TEXTURE_NOBLEND].reset();
+@@ -675,3 +689,27 @@ GLint CRenderSystemGLES::GUIShaderGetModel()
+
+   return -1;
+ }
++
++GLint CRenderSystemGLES::GUIShaderGetMatrix()
++{
++  if (m_pShader[m_method])
++    return m_pShader[m_method]->GetMatrixLoc();
++
++  return -1;
++}
++
++GLint CRenderSystemGLES::GUIShaderGetClip()
++{
++  if (m_pShader[m_method])
++    return m_pShader[m_method]->GetShaderClipLoc();
++
++  return -1;
++}
++
++GLint CRenderSystemGLES::GUIShaderGetCoordStep()
++{
++  if (m_pShader[m_method])
++    return m_pShader[m_method]->GetShaderCoordStepLoc();
++
++  return -1;
++}
+diff --git a/xbmc/rendering/gles/RenderSystemGLES.h b/xbmc/rendering/gles/RenderSystemGLES.h
+index e0cd72b9c1937..7986f2c0a42cb 100644
+--- a/xbmc/rendering/gles/RenderSystemGLES.h
++++ b/xbmc/rendering/gles/RenderSystemGLES.h
+@@ -25,6 +25,7 @@ enum class ShaderMethodGLES
+   SM_TEXTURE,
+   SM_MULTI,
+   SM_FONTS,
++  SM_FONTS_SHADER_CLIP,
+   SM_TEXTURE_NOBLEND,
+   SM_MULTI_BLENDCOLOR,
+   SM_TEXTURE_RGBA,
+@@ -55,6 +56,7 @@ struct fmt::formatter<ShaderMethodGLES> : fmt::formatter<std::string_view>
+       {ShaderMethodGLES::SM_TEXTURE, "texture"},
+       {ShaderMethodGLES::SM_MULTI, "multi"},
+       {ShaderMethodGLES::SM_FONTS, "fonts"},
++      {ShaderMethodGLES::SM_FONTS_SHADER_CLIP, "fonts with vertex shader based clipping"},
+       {ShaderMethodGLES::SM_TEXTURE_NOBLEND, "texture no blending"},
+       {ShaderMethodGLES::SM_MULTI_BLENDCOLOR, "multi blend colour"},
+       {ShaderMethodGLES::SM_TEXTURE_RGBA, "texure rgba"},
+@@ -124,6 +126,9 @@ class CRenderSystemGLES : public CRenderSystemBase
+   GLint GUIShaderGetContrast();
+   GLint GUIShaderGetBrightness();
+   GLint GUIShaderGetModel();
++  GLint GUIShaderGetMatrix();
++  GLint GUIShaderGetClip();
++  GLint GUIShaderGetCoordStep();
+
+ protected:
+   virtual void SetVSyncImpl(bool enable) = 0;
diff --git a/projects/Rockchip/devices/RK322X/patches/kodi-broken/02-22919.patch b/projects/Rockchip/devices/RK322X/patches/kodi-broken/02-22919.patch
new file mode 100644
index 0000000000..5e235a9a3a
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/patches/kodi-broken/02-22919.patch
@@ -0,0 +1,3136 @@
+From 949db03482560ad3ca527f4ee16c4ffc7641ca19 Mon Sep 17 00:00:00 2001
+From: sarbes <sarbes@kodi.tv>
+Date: Thu, 25 Apr 2024 22:54:54 +0200
+Subject: [PATCH 1/4] Implement front to back rendering
+
+---
+ system/shaders/GL/1.2/gl_shader_vert.glsl     |   2 +
+ .../shaders/GL/1.2/gl_shader_vert_clip.glsl   |   4 +
+ .../GL/1.2/gl_shader_vert_default.glsl        |   1 +
+ .../shaders/GL/1.2/gl_shader_vert_simple.glsl |   2 +
+ system/shaders/GL/1.2/gl_yuv2rgb_vertex.glsl  |   1 +
+ system/shaders/GL/1.5/gl_shader_vert.glsl     |   2 +
+ .../shaders/GL/1.5/gl_shader_vert_clip.glsl   |   4 +
+ .../GL/1.5/gl_shader_vert_default.glsl        |   1 +
+ .../shaders/GL/1.5/gl_shader_vert_simple.glsl |   2 +
+ system/shaders/GL/1.5/gl_yuv2rgb_vertex.glsl  |   1 +
+ system/shaders/GLES/2.0/gles_shader.vert      |   2 +
+ system/shaders/GLES/2.0/gles_shader_clip.vert |   4 +
+ .../shaders/GLES/2.0/gles_shader_simple.vert  |   4 +
+ system/shaders/GLES/2.0/gles_yuv2rgb.vert     |   1 +
+ .../RetroPlayer/rendering/RenderContext.cpp   |  15 +++
+ .../RetroPlayer/rendering/RenderContext.h     |   1 +
+ .../VideoRenderers/RPRendererDMA.cpp          |   2 +
+ .../VideoRenderers/RPRendererGuiTexture.cpp   |   4 +
+ .../VideoRenderers/RPRendererOpenGL.cpp       |   2 +
+ .../VideoRenderers/RPRendererOpenGLES.cpp     |   4 +
+ .../VideoRenderers/DebugRenderer.cpp          |   2 +-
+ .../VideoRenderers/DebugRenderer.h            |   2 +-
+ .../HwDecRender/RendererDRMPRIMEGLES.cpp      |   5 +
+ .../HwDecRender/RendererMediaCodec.cpp        |   4 +-
+ .../VideoRenderers/LinuxRendererGL.cpp        |  57 ++++++++-
+ .../VideoRenderers/LinuxRendererGL.h          |   1 +
+ .../VideoRenderers/LinuxRendererGLES.cpp      |  82 ++++++++++--
+ .../VideoRenderers/LinuxRendererGLES.h        |   4 +-
+ .../VideoRenderers/OverlayRenderer.cpp        |   2 +-
+ .../VideoRenderers/OverlayRenderer.h          |   2 +-
+ .../VideoRenderers/OverlayRendererGL.cpp      |   6 +
+ .../VideoRenderers/OverlayRendererGLES.cpp    |   5 +
+ xbmc/guilib/GUIBaseContainer.cpp              |  57 ++++++++-
+ xbmc/guilib/GUIBaseContainer.h                |   9 ++
+ xbmc/guilib/GUIBorderedImage.cpp              |  12 +-
+ xbmc/guilib/GUIButtonControl.cpp              |  18 ++-
+ xbmc/guilib/GUIControl.cpp                    |   5 +
+ xbmc/guilib/GUIControl.h                      |   1 +
+ xbmc/guilib/GUIControlGroup.cpp               |  41 +++++-
+ xbmc/guilib/GUIControlGroup.h                 |   1 +
+ xbmc/guilib/GUIEditControl.cpp                |   3 +
+ xbmc/guilib/GUIFadeLabelControl.cpp           |  10 ++
+ xbmc/guilib/GUIFadeLabelControl.h             |   4 +
+ xbmc/guilib/GUIFontTTFGL.cpp                  |   5 +
+ xbmc/guilib/GUIFontTTFGLES.cpp                |   5 +
+ xbmc/guilib/GUILabelControl.cpp               |   3 +
+ xbmc/guilib/GUIListItemLayout.cpp             |   5 +
+ xbmc/guilib/GUIListItemLayout.h               |   1 +
+ xbmc/guilib/GUIListLabel.cpp                  |   3 +
+ xbmc/guilib/GUIPanelContainer.cpp             |  29 ++++-
+ xbmc/guilib/GUISettingsSliderControl.cpp      |   3 +
+ xbmc/guilib/GUISpinControl.cpp                |   3 +
+ xbmc/guilib/GUITextBox.cpp                    |  10 ++
+ xbmc/guilib/GUITextBox.h                      |   1 +
+ xbmc/guilib/GUITexture.cpp                    |  55 ++++++--
+ xbmc/guilib/GUITexture.h                      |  15 ++-
+ xbmc/guilib/GUITextureD3D.cpp                 |   4 +-
+ xbmc/guilib/GUITextureD3D.h                   |   4 +-
+ xbmc/guilib/GUITextureGL.cpp                  |  20 ++-
+ xbmc/guilib/GUITextureGL.h                    |   4 +-
+ xbmc/guilib/GUITextureGLES.cpp                |  20 ++-
+ xbmc/guilib/GUITextureGLES.h                  |   4 +-
+ xbmc/guilib/GUIVideoControl.cpp               |  14 +-
+ xbmc/guilib/GUIWindow.cpp                     |   2 +
+ xbmc/guilib/GUIWindowManager.cpp              |  56 ++++++++
+ xbmc/guilib/GUIWindowManager.h                |   6 +
+ xbmc/pictures/SlideShowPicture.cpp            |   3 +
+ xbmc/pictures/SlideShowPictureGL.cpp          |   2 +
+ xbmc/pictures/SlideShowPictureGLES.cpp        |   2 +
+ xbmc/pvr/guilib/GUIEPGGridContainer.cpp       | 120 ++++++++++++++++--
+ xbmc/pvr/guilib/GUIEPGGridContainer.h         |  25 +++-
+ xbmc/rendering/RenderSystem.h                 |  10 ++
+ xbmc/rendering/gl/GLShader.cpp                |   1 +
+ xbmc/rendering/gl/GLShader.h                  |   2 +
+ xbmc/rendering/gl/RenderSystemGL.cpp          |  64 +++++++++-
+ xbmc/rendering/gl/RenderSystemGL.h            |   4 +
+ xbmc/rendering/gles/GLESShader.cpp            |   1 +
+ xbmc/rendering/gles/GLESShader.h              |   2 +
+ xbmc/rendering/gles/RenderSystemGLES.cpp      |  57 ++++++++-
+ xbmc/rendering/gles/RenderSystemGLES.h        |   4 +
+ xbmc/settings/AdvancedSettings.cpp            |   2 +
+ xbmc/settings/AdvancedSettings.h              |   2 +
+ xbmc/utils/TransformMatrix.h                  |  12 ++
+ xbmc/video/dialogs/GUIDialogTeletext.cpp      |   5 +-
+ xbmc/video/windows/GUIWindowFullScreen.cpp    |  21 ++-
+ xbmc/windowing/GraphicContext.cpp             |  39 ++++++
+ xbmc/windowing/GraphicContext.h               |  46 ++++++-
+ xbmc/windowing/X11/GLContextEGL.cpp           |   2 +-
+ xbmc/windows/GUIWindowDebugInfo.cpp           |   6 +
+ 89 files changed, 1001 insertions(+), 95 deletions(-)
+
+diff --git a/system/shaders/GL/1.2/gl_shader_vert.glsl b/system/shaders/GL/1.2/gl_shader_vert.glsl
+index 7c10b5f1bfb4b..fef2d2d94e8e3 100644
+--- a/system/shaders/GL/1.2/gl_shader_vert.glsl
++++ b/system/shaders/GL/1.2/gl_shader_vert.glsl
+@@ -29,11 +29,13 @@ varying vec4 m_cord1;
+ varying vec4 m_colour;
+ uniform mat4 m_proj;
+ uniform mat4 m_model;
++uniform float m_depth;
+
+ void main ()
+ {
+   mat4 mvp    = m_proj * m_model;
+   gl_Position = mvp * m_attrpos;
++  gl_Position.z = m_depth * gl_Position.w;
+   m_colour    = m_attrcol;
+   m_cord0     = m_attrcord0;
+   m_cord1     = m_attrcord1;
+diff --git a/system/shaders/GL/1.2/gl_shader_vert_clip.glsl b/system/shaders/GL/1.2/gl_shader_vert_clip.glsl
+index 37d67946f5949..959f8ad46bec1 100644
+--- a/system/shaders/GL/1.2/gl_shader_vert_clip.glsl
++++ b/system/shaders/GL/1.2/gl_shader_vert_clip.glsl
+@@ -18,6 +18,7 @@ varying vec4 m_colour;
+ uniform mat4 m_matrix;
+ uniform vec4 m_shaderClip;
+ uniform vec4 m_cordStep;
++uniform float m_depth;
+
+ // this shader can be used in cases where clipping via glScissor() is not
+ // possible (e.g. when rotating). it can't discard triangles, but it may
+@@ -30,6 +31,9 @@ void main ()
+   position.xy = clamp(position.xy, m_shaderClip.xy, m_shaderClip.zw);
+   gl_Position = m_matrix * position;
+
++  // set rendering depth
++  gl_Position.z = m_depth * gl_Position.w;
++
+   // correct texture coordinates for clipped vertices
+   vec2 clipDist = m_attrpos.xy - position.xy;
+   m_cord0.xy = m_attrcord0.xy - clipDist * m_cordStep.xy;
+diff --git a/system/shaders/GL/1.2/gl_shader_vert_default.glsl b/system/shaders/GL/1.2/gl_shader_vert_default.glsl
+index 554e15c3fdb73..bbb06cb5fe494 100644
+--- a/system/shaders/GL/1.2/gl_shader_vert_default.glsl
++++ b/system/shaders/GL/1.2/gl_shader_vert_default.glsl
+@@ -28,4 +28,5 @@ void main ()
+ {
+   mat4 mvp    = m_proj * m_model;
+   gl_Position = mvp * m_attrpos;
++  gl_Position.z = -1. * gl_Position.w;
+ }
+diff --git a/system/shaders/GL/1.2/gl_shader_vert_simple.glsl b/system/shaders/GL/1.2/gl_shader_vert_simple.glsl
+index f06893a0850ed..91fbae0b755c7 100644
+--- a/system/shaders/GL/1.2/gl_shader_vert_simple.glsl
++++ b/system/shaders/GL/1.2/gl_shader_vert_simple.glsl
+@@ -16,10 +16,12 @@ varying vec4 m_cord0;
+ varying vec4 m_cord1;
+ varying vec4 m_colour;
+ uniform mat4 m_matrix;
++uniform float m_depth;
+
+ void main ()
+ {
+   gl_Position = m_matrix * m_attrpos;
++  gl_Position.z = m_depth * gl_Position.w;
+   m_colour    = m_attrcol;
+   m_cord0     = m_attrcord0;
+   m_cord1     = m_attrcord1;
+diff --git a/system/shaders/GL/1.2/gl_yuv2rgb_vertex.glsl b/system/shaders/GL/1.2/gl_yuv2rgb_vertex.glsl
+index cdf3c56a71463..8d7e0c35301ea 100644
+--- a/system/shaders/GL/1.2/gl_yuv2rgb_vertex.glsl
++++ b/system/shaders/GL/1.2/gl_yuv2rgb_vertex.glsl
+@@ -32,6 +32,7 @@ void main ()
+ {
+   mat4 mvp    = m_proj * m_model;
+   gl_Position = mvp * m_attrpos;
++  gl_Position.z = -1. * gl_Position.w;
+   m_cordY     = m_attrcordY;
+   m_cordU     = m_attrcordU;
+   m_cordV     = m_attrcordV;
+diff --git a/system/shaders/GL/1.5/gl_shader_vert.glsl b/system/shaders/GL/1.5/gl_shader_vert.glsl
+index a8568310c2b88..c66c8047887d3 100644
+--- a/system/shaders/GL/1.5/gl_shader_vert.glsl
++++ b/system/shaders/GL/1.5/gl_shader_vert.glsl
+@@ -9,11 +9,13 @@ out vec4 m_cord1;
+ out vec4 m_colour;
+ uniform mat4 m_proj;
+ uniform mat4 m_model;
++uniform float m_depth;
+
+ void main ()
+ {
+   mat4 mvp    = m_proj * m_model;
+   gl_Position = mvp * m_attrpos;
++  gl_Position.z = m_depth * gl_Position.w;
+   m_colour    = m_attrcol;
+   m_cord0     = m_attrcord0;
+   m_cord1     = m_attrcord1;
+diff --git a/system/shaders/GL/1.5/gl_shader_vert_clip.glsl b/system/shaders/GL/1.5/gl_shader_vert_clip.glsl
+index 2fa1c63da13d7..0cb2a8f1d8038 100644
+--- a/system/shaders/GL/1.5/gl_shader_vert_clip.glsl
++++ b/system/shaders/GL/1.5/gl_shader_vert_clip.glsl
+@@ -18,6 +18,7 @@ out vec4 m_colour;
+ uniform mat4 m_matrix;
+ uniform vec4 m_shaderClip;
+ uniform vec4 m_cordStep;
++uniform float m_depth;
+
+ // this shader can be used in cases where clipping via glScissor() is not
+ // possible (e.g. when rotating). it can't discard triangles, but it may
+@@ -30,6 +31,9 @@ void main ()
+   position.xy = clamp(position.xy, m_shaderClip.xy, m_shaderClip.zw);
+   gl_Position = m_matrix * position;
+
++  // set rendering depth
++  gl_Position.z = m_depth * gl_Position.w;
++
+   // correct texture coordinates for clipped vertices
+   vec2 clipDist = m_attrpos.xy - position.xy;
+   m_cord0.xy = m_attrcord0.xy - clipDist * m_cordStep.xy;
+diff --git a/system/shaders/GL/1.5/gl_shader_vert_default.glsl b/system/shaders/GL/1.5/gl_shader_vert_default.glsl
+index e4f2d7c9eeced..b68ef12925ba4 100644
+--- a/system/shaders/GL/1.5/gl_shader_vert_default.glsl
++++ b/system/shaders/GL/1.5/gl_shader_vert_default.glsl
+@@ -8,4 +8,5 @@ void main ()
+ {
+   mat4 mvp    = m_proj * m_model;
+   gl_Position = mvp * m_attrpos;
++  gl_Position.z = -1. * gl_Position.w;
+ }
+diff --git a/system/shaders/GL/1.5/gl_shader_vert_simple.glsl b/system/shaders/GL/1.5/gl_shader_vert_simple.glsl
+index 9c1552d7a4af9..953cdfcf8b5e4 100644
+--- a/system/shaders/GL/1.5/gl_shader_vert_simple.glsl
++++ b/system/shaders/GL/1.5/gl_shader_vert_simple.glsl
+@@ -16,10 +16,12 @@ out vec4 m_cord0;
+ out vec4 m_cord1;
+ out vec4 m_colour;
+ uniform mat4 m_matrix;
++uniform float m_depth;
+
+ void main ()
+ {
+   gl_Position = m_matrix * m_attrpos;
++  gl_Position.z = m_depth * gl_Position.w;
+   m_colour    = m_attrcol;
+   m_cord0     = m_attrcord0;
+   m_cord1     = m_attrcord1;
+diff --git a/system/shaders/GL/1.5/gl_yuv2rgb_vertex.glsl b/system/shaders/GL/1.5/gl_yuv2rgb_vertex.glsl
+index 4772bd4172989..257aacfcc2e88 100644
+--- a/system/shaders/GL/1.5/gl_yuv2rgb_vertex.glsl
++++ b/system/shaders/GL/1.5/gl_yuv2rgb_vertex.glsl
+@@ -14,6 +14,7 @@ void main ()
+ {
+   mat4 mvp = m_proj * m_model;
+   gl_Position = mvp * m_attrpos;
++  gl_Position.z = -1. * gl_Position.w;
+   m_cordY = m_attrcordY;
+   m_cordU = m_attrcordU;
+   m_cordV = m_attrcordV;
+diff --git a/system/shaders/GLES/2.0/gles_shader.vert b/system/shaders/GLES/2.0/gles_shader.vert
+index 890acbbb8190e..17b4ad7b48faf 100644
+--- a/system/shaders/GLES/2.0/gles_shader.vert
++++ b/system/shaders/GLES/2.0/gles_shader.vert
+@@ -30,11 +30,13 @@ varying lowp vec4 m_colour;
+ uniform mat4 m_proj;
+ uniform mat4 m_model;
+ uniform mat4 m_coord0Matrix;
++uniform float m_depth;
+
+ void main ()
+ {
+   mat4 mvp = m_proj * m_model;
+   gl_Position = mvp * m_attrpos;
++  gl_Position.z = m_depth * gl_Position.w;
+   m_colour = m_attrcol;
+   m_cord0 = m_coord0Matrix * m_attrcord0;
+   m_cord1 = m_attrcord1;
+diff --git a/system/shaders/GLES/2.0/gles_shader_clip.vert b/system/shaders/GLES/2.0/gles_shader_clip.vert
+index 513a24456c7df..1b1cf3f91e4e9 100644
+--- a/system/shaders/GLES/2.0/gles_shader_clip.vert
++++ b/system/shaders/GLES/2.0/gles_shader_clip.vert
+@@ -18,6 +18,7 @@ varying vec4 m_colour;
+ uniform mat4 m_matrix;
+ uniform vec4 m_shaderClip;
+ uniform vec4 m_cordStep;
++uniform float m_depth;
+
+ // this shader can be used in cases where clipping via glScissor() is not
+ // possible (e.g. when rotating). it can't discard triangles, but it may
+@@ -30,6 +31,9 @@ void main()
+   position.xy = clamp(position.xy, m_shaderClip.xy, m_shaderClip.zw);
+   gl_Position = m_matrix * position;
+
++  // set rendering depth
++  gl_Position.z = m_depth * gl_Position.w;
++
+   // correct texture coordinates for clipped vertices
+   vec2 clipDist = m_attrpos.xy - position.xy;
+   m_cord0.xy = m_attrcord0.xy - clipDist * m_cordStep.xy;
+diff --git a/system/shaders/GLES/2.0/gles_shader_simple.vert b/system/shaders/GLES/2.0/gles_shader_simple.vert
+index 6d49788b65f87..2f34f8bf28892 100644
+--- a/system/shaders/GLES/2.0/gles_shader_simple.vert
++++ b/system/shaders/GLES/2.0/gles_shader_simple.vert
+@@ -16,10 +16,14 @@ varying vec4 m_cord0;
+ varying vec4 m_cord1;
+ varying vec4 m_colour;
+ uniform mat4 m_matrix;
++uniform float m_depth;
+
+ void main()
+ {
+   gl_Position = m_matrix * m_attrpos;
++
++  // set rendering depth
++  gl_Position.z = m_depth * gl_Position.w;
+   m_colour    = m_attrcol;
+   m_cord0     = m_attrcord0;
+   m_cord1     = m_attrcord1;
+diff --git a/system/shaders/GLES/2.0/gles_yuv2rgb.vert b/system/shaders/GLES/2.0/gles_yuv2rgb.vert
+index bc437afdc3046..c96a6a958594c 100644
+--- a/system/shaders/GLES/2.0/gles_yuv2rgb.vert
++++ b/system/shaders/GLES/2.0/gles_yuv2rgb.vert
+@@ -34,6 +34,7 @@ void main ()
+ {
+   mat4 mvp = m_proj * m_model;
+   gl_Position = mvp * m_attrpos;
++  gl_Position.z = -1. * gl_Position.w;
+   m_cordY = m_attrcordY;
+   m_cordU = m_attrcordU;
+   m_cordV = m_attrcordV;
+diff --git a/xbmc/cores/RetroPlayer/rendering/RenderContext.cpp b/xbmc/cores/RetroPlayer/rendering/RenderContext.cpp
+index bc5d50fee6d53..db954e985e47b 100644
+--- a/xbmc/cores/RetroPlayer/rendering/RenderContext.cpp
++++ b/xbmc/cores/RetroPlayer/rendering/RenderContext.cpp
+@@ -184,6 +184,21 @@ int CRenderContext::GUIShaderGetUniCol()
+   return -1;
+ }
+
++int CRenderContext::GUIShaderGetDepth()
++{
++#if defined(HAS_GL)
++  CRenderSystemGL* renderingGL = dynamic_cast<CRenderSystemGL*>(m_rendering);
++  if (renderingGL != nullptr)
++    return static_cast<int>(renderingGL->ShaderGetDepth());
++#elif HAS_GLES >= 2
++  CRenderSystemGLES* renderingGLES = dynamic_cast<CRenderSystemGLES*>(m_rendering);
++  if (renderingGLES != nullptr)
++    return static_cast<int>(renderingGLES->GUIShaderGetDepth());
++#endif
++
++  return -1;
++}
++
+ CGUIShaderDX* CRenderContext::GetGUIShader()
+ {
+ #if defined(HAS_DX)
+diff --git a/xbmc/cores/RetroPlayer/rendering/RenderContext.h b/xbmc/cores/RetroPlayer/rendering/RenderContext.h
+index 3f0c4c7524c27..0058c70b12b13 100644
+--- a/xbmc/cores/RetroPlayer/rendering/RenderContext.h
++++ b/xbmc/cores/RetroPlayer/rendering/RenderContext.h
+@@ -69,6 +69,7 @@ class CRenderContext
+   int GUIShaderGetPos();
+   int GUIShaderGetCoord0();
+   int GUIShaderGetUniCol();
++  int GUIShaderGetDepth();
+
+   // DirectX rendering functions
+   CGUIShaderDX* GetGUIShader();
+diff --git a/xbmc/cores/RetroPlayer/rendering/VideoRenderers/RPRendererDMA.cpp b/xbmc/cores/RetroPlayer/rendering/VideoRenderers/RPRendererDMA.cpp
+index 97a9eaa462f08..8b9886b835844 100644
+--- a/xbmc/cores/RetroPlayer/rendering/VideoRenderers/RPRendererDMA.cpp
++++ b/xbmc/cores/RetroPlayer/rendering/VideoRenderers/RPRendererDMA.cpp
+@@ -85,6 +85,7 @@ void CRPRendererDMA::Render(uint8_t alpha)
+   GLint vertLoc = m_context.GUIShaderGetPos();
+   GLint loc = m_context.GUIShaderGetCoord0();
+   GLint uniColLoc = m_context.GUIShaderGetUniCol();
++  GLint depthLoc = m_context.GUIShaderGetDepth();
+
+   // Setup color values
+   colour[0] = UTILS::GL::GetChannelFromARGB(UTILS::GL::ColorChannel::R, color);
+@@ -122,6 +123,7 @@ void CRPRendererDMA::Render(uint8_t alpha)
+
+   glUniform4f(uniColLoc, (colour[0] / 255.0f), (colour[1] / 255.0f), (colour[2] / 255.0f),
+               (colour[3] / 255.0f));
++  glUniform1f(depthLoc, -1.0f);
+   glDrawElements(GL_TRIANGLE_STRIP, 4, GL_UNSIGNED_BYTE, 0);
+
+   glDisableVertexAttribArray(vertLoc);
+diff --git a/xbmc/cores/RetroPlayer/rendering/VideoRenderers/RPRendererGuiTexture.cpp b/xbmc/cores/RetroPlayer/rendering/VideoRenderers/RPRendererGuiTexture.cpp
+index f38e24006c3cf..7929140a8a518 100644
+--- a/xbmc/cores/RetroPlayer/rendering/VideoRenderers/RPRendererGuiTexture.cpp
++++ b/xbmc/cores/RetroPlayer/rendering/VideoRenderers/RPRendererGuiTexture.cpp
+@@ -184,6 +184,7 @@ void CRPRendererGuiTexture::RenderInternal(bool clear, uint8_t alpha)
+   GLint posLoc = m_context.GUIShaderGetPos();
+   GLint tex0Loc = m_context.GUIShaderGetCoord0();
+   GLint uniColLoc = m_context.GUIShaderGetUniCol();
++  GLint depthLoc = m_context.GUIShaderGetDepth();
+
+   glGenBuffers(1, &vertexVBO);
+   glBindBuffer(GL_ARRAY_BUFFER, vertexVBO);
+@@ -212,6 +213,7 @@ void CRPRendererGuiTexture::RenderInternal(bool clear, uint8_t alpha)
+
+   glUniform4f(uniColLoc, (colour[0] / 255.0f), (colour[1] / 255.0f), (colour[2] / 255.0f),
+               (colour[3] / 255.0f));
++  glUniform1f(depthLoc, -1.0f);
+
+   glGenBuffers(1, &indexVBO);
+   glBindBuffer(GL_ELEMENT_ARRAY_BUFFER, indexVBO);
+@@ -246,6 +248,7 @@ void CRPRendererGuiTexture::RenderInternal(bool clear, uint8_t alpha)
+   GLint posLoc = m_context.GUIShaderGetPos();
+   GLint tex0Loc = m_context.GUIShaderGetCoord0();
+   GLint uniColLoc = m_context.GUIShaderGetUniCol();
++  GLint depthLoc = m_context.GUIShaderGetDepth();
+
+   glVertexAttribPointer(posLoc, 3, GL_FLOAT, 0, 0, ver);
+   glVertexAttribPointer(tex0Loc, 2, GL_FLOAT, 0, 0, tex);
+@@ -275,6 +278,7 @@ void CRPRendererGuiTexture::RenderInternal(bool clear, uint8_t alpha)
+
+   glUniform4f(uniColLoc, (col[0] / 255.0f), (col[1] / 255.0f), (col[2] / 255.0f),
+               (col[3] / 255.0f));
++  glUniform1f(depthLoc, -1.0f);
+   glDrawElements(GL_TRIANGLE_STRIP, 4, GL_UNSIGNED_BYTE, idx);
+
+   glDisableVertexAttribArray(posLoc);
+diff --git a/xbmc/cores/RetroPlayer/rendering/VideoRenderers/RPRendererOpenGL.cpp b/xbmc/cores/RetroPlayer/rendering/VideoRenderers/RPRendererOpenGL.cpp
+index 49ff7f8ca87b1..c3ac4218dd318 100644
+--- a/xbmc/cores/RetroPlayer/rendering/VideoRenderers/RPRendererOpenGL.cpp
++++ b/xbmc/cores/RetroPlayer/rendering/VideoRenderers/RPRendererOpenGL.cpp
+@@ -295,6 +295,7 @@ void CRPRendererOpenGL::Render(uint8_t alpha)
+   PackedVertex vertex[4];
+
+   GLint uniColLoc = m_context.GUIShaderGetUniCol();
++  GLint depthLoc = m_context.GUIShaderGetDepth();
+
+   // Setup color values
+   colour[0] = UTILS::GL::GetChannelFromARGB(UTILS::GL::ColorChannel::R, color);
+@@ -326,6 +327,7 @@ void CRPRendererOpenGL::Render(uint8_t alpha)
+
+   glUniform4f(uniColLoc, (colour[0] / 255.0f), (colour[1] / 255.0f), (colour[2] / 255.0f),
+               (colour[3] / 255.0f));
++  glUniform1f(depthLoc, -1.0f);
+
+   glDrawElements(GL_TRIANGLE_STRIP, 4, GL_UNSIGNED_BYTE, 0);
+
+diff --git a/xbmc/cores/RetroPlayer/rendering/VideoRenderers/RPRendererOpenGLES.cpp b/xbmc/cores/RetroPlayer/rendering/VideoRenderers/RPRendererOpenGLES.cpp
+index b8e4259147d02..d120ff7862db5 100644
+--- a/xbmc/cores/RetroPlayer/rendering/VideoRenderers/RPRendererOpenGLES.cpp
++++ b/xbmc/cores/RetroPlayer/rendering/VideoRenderers/RPRendererOpenGLES.cpp
+@@ -128,8 +128,10 @@ void CRPRendererOpenGLES::DrawBlackBars()
+   m_context.EnableGUIShader(GL_SHADER_METHOD::DEFAULT);
+   GLint posLoc = m_context.GUIShaderGetPos();
+   GLint uniCol = m_context.GUIShaderGetUniCol();
++  GLint depthLoc = m_context.GUIShaderGetDepth();
+
+   glUniform4f(uniCol, m_clearColour / 255.0f, m_clearColour / 255.0f, m_clearColour / 255.0f, 1.0f);
++  glUniform1f(depthLoc, -1.0f);
+
+   // top quad
+   if (m_rotatedDestCoords[0].y > 0.0f)
+@@ -268,6 +270,7 @@ void CRPRendererOpenGLES::Render(uint8_t alpha)
+   GLint vertLoc = m_context.GUIShaderGetPos();
+   GLint loc = m_context.GUIShaderGetCoord0();
+   GLint uniColLoc = m_context.GUIShaderGetUniCol();
++  GLint depthLoc = m_context.GUIShaderGetDepth();
+
+   // Setup color values
+   colour[0] = UTILS::GL::GetChannelFromARGB(UTILS::GL::ColorChannel::R, color);
+@@ -305,6 +308,7 @@ void CRPRendererOpenGLES::Render(uint8_t alpha)
+
+   glUniform4f(uniColLoc, (colour[0] / 255.0f), (colour[1] / 255.0f), (colour[2] / 255.0f),
+               (colour[3] / 255.0f));
++  glUniform1f(depthLoc, -1.0f);
+   glDrawElements(GL_TRIANGLE_STRIP, 4, GL_UNSIGNED_BYTE, 0);
+
+   glDisableVertexAttribArray(vertLoc);
+diff --git a/xbmc/cores/VideoPlayer/VideoRenderers/DebugRenderer.cpp b/xbmc/cores/VideoPlayer/VideoRenderers/DebugRenderer.cpp
+index 9a8f496f96a79..2277962600c91 100644
+--- a/xbmc/cores/VideoPlayer/VideoRenderers/DebugRenderer.cpp
++++ b/xbmc/cores/VideoPlayer/VideoRenderers/DebugRenderer.cpp
+@@ -116,7 +116,7 @@ CDebugRenderer::CRenderer::CRenderer() : OVERLAY::CRenderer()
+ {
+ }
+
+-void CDebugRenderer::CRenderer::Render(int idx)
++void CDebugRenderer::CRenderer::Render(int idx, float depth)
+ {
+   std::vector<SElement>& list = m_buffers[idx];
+   for (std::vector<SElement>::iterator it = list.begin(); it != list.end(); ++it)
+diff --git a/xbmc/cores/VideoPlayer/VideoRenderers/DebugRenderer.h b/xbmc/cores/VideoPlayer/VideoRenderers/DebugRenderer.h
+index e5a08d306f14b..7a5c306150283 100644
+--- a/xbmc/cores/VideoPlayer/VideoRenderers/DebugRenderer.h
++++ b/xbmc/cores/VideoPlayer/VideoRenderers/DebugRenderer.h
+@@ -34,7 +34,7 @@ class CDebugRenderer
+   {
+   public:
+     CRenderer();
+-    void Render(int idx) override;
++    void Render(int idx, float depth = 1.0f) override;
+     void CreateSubtitlesStyle();
+
+   private:
+diff --git a/xbmc/cores/VideoPlayer/VideoRenderers/HwDecRender/RendererDRMPRIMEGLES.cpp b/xbmc/cores/VideoPlayer/VideoRenderers/HwDecRender/RendererDRMPRIMEGLES.cpp
+index ed6052864bbf2..e7adf42dced69 100644
+--- a/xbmc/cores/VideoPlayer/VideoRenderers/HwDecRender/RendererDRMPRIMEGLES.cpp
++++ b/xbmc/cores/VideoPlayer/VideoRenderers/HwDecRender/RendererDRMPRIMEGLES.cpp
+@@ -224,8 +224,10 @@ void CRendererDRMPRIMEGLES::DrawBlackBars()
+   renderSystem->EnableGUIShader(ShaderMethodGLES::SM_DEFAULT);
+   GLint posLoc = renderSystem->GUIShaderGetPos();
+   GLint uniCol = renderSystem->GUIShaderGetUniCol();
++  GLint depthLoc = renderSystem->GUIShaderGetDepth();
+
+   glUniform4f(uniCol, m_clearColour / 255.0f, m_clearColour / 255.0f, m_clearColour / 255.0f, 1.0f);
++  glUniform1f(depthLoc, -1.0f);
+
+   GLuint vertexVBO;
+   glGenBuffers(1, &vertexVBO);
+@@ -328,6 +330,7 @@ void CRendererDRMPRIMEGLES::Render(unsigned int flags, int index)
+
+   GLint vertLoc = renderSystem->GUIShaderGetPos();
+   GLint loc = renderSystem->GUIShaderGetCoord0();
++  GLint depthLoc = renderSystem->GUIShaderGetDepth();
+
+   // top left
+   vertex[0].x = m_rotatedDestCoords[0].x;
+@@ -374,6 +377,8 @@ void CRendererDRMPRIMEGLES::Render(unsigned int flags, int index)
+   glBindBuffer(GL_ELEMENT_ARRAY_BUFFER, indexVBO);
+   glBufferData(GL_ELEMENT_ARRAY_BUFFER, sizeof(GLubyte) * 4, idx, GL_STATIC_DRAW);
+
++  glUniform1f(depthLoc, -1.0f);
++
+   glDrawElements(GL_TRIANGLE_STRIP, 4, GL_UNSIGNED_BYTE, 0);
+
+   glDisableVertexAttribArray(vertLoc);
+diff --git a/xbmc/cores/VideoPlayer/VideoRenderers/HwDecRender/RendererMediaCodec.cpp b/xbmc/cores/VideoPlayer/VideoRenderers/HwDecRender/RendererMediaCodec.cpp
+index e06a81cf18d67..d37d61e08d8c1 100644
+--- a/xbmc/cores/VideoPlayer/VideoRenderers/HwDecRender/RendererMediaCodec.cpp
++++ b/xbmc/cores/VideoPlayer/VideoRenderers/HwDecRender/RendererMediaCodec.cpp
+@@ -112,8 +112,6 @@ bool CRendererMediaCodec::RenderHook(int index)
+   CYuvPlane &plane = m_buffers[index].fields[0][0];
+   CYuvPlane &planef = m_buffers[index].fields[m_currentField][0];
+
+-  glDisable(GL_DEPTH_TEST);
+-
+   glActiveTexture(GL_TEXTURE0);
+   glBindTexture(GL_TEXTURE_EXTERNAL_OES, plane.id);
+
+@@ -139,6 +137,8 @@ bool CRendererMediaCodec::RenderHook(int index)
+   glUniform1f(contrastLoc, m_videoSettings.m_Contrast * 0.02f);
+   GLint   brightnessLoc = renderSystem->GUIShaderGetBrightness();
+   glUniform1f(brightnessLoc, m_videoSettings.m_Brightness * 0.01f - 0.5f);
++  GLint depthLoc = renderSystem->GUIShaderGetDepth();
++  glUniform1f(depthLoc, -1.0f);
+
+   glUniformMatrix4fv(renderSystem->GUIShaderGetCoord0Matrix(), 1, GL_FALSE, m_textureMatrix);
+
+diff --git a/xbmc/cores/VideoPlayer/VideoRenderers/LinuxRendererGL.cpp b/xbmc/cores/VideoPlayer/VideoRenderers/LinuxRendererGL.cpp
+index d96c29a6b71c8..c2fa1e125d527 100644
+--- a/xbmc/cores/VideoPlayer/VideoRenderers/LinuxRendererGL.cpp
++++ b/xbmc/cores/VideoPlayer/VideoRenderers/LinuxRendererGL.cpp
+@@ -531,9 +531,56 @@ void CLinuxRendererGL::RenderUpdate(int index, int index2, bool clear, unsigned
+ void CLinuxRendererGL::ClearBackBuffer()
+ {
+   //set the entire backbuffer to black
+-  glClearColor(m_clearColour, m_clearColour, m_clearColour, 0);
+-  glClear(GL_COLOR_BUFFER_BIT);
+-  glClearColor(0,0,0,0);
++  //if we do a two pass render, we have to draw a quad. else we might occlude OSD elements.
++  if (CServiceBroker::GetWinSystem()->GetGfxContext().GetRenderOrder() ==
++      RENDER_ORDER_ALL_BACK_TO_FRONT)
++  {
++    CServiceBroker::GetWinSystem()->GetGfxContext().Clear(0xff000000);
++  }
++  else
++  {
++    ClearBackBufferQuad();
++  }
++}
++
++void CLinuxRendererGL::ClearBackBufferQuad()
++{
++  CRect windowRect(0, 0, CServiceBroker::GetWinSystem()->GetGfxContext().GetWidth(),
++                   CServiceBroker::GetWinSystem()->GetGfxContext().GetHeight());
++  struct Svertex
++  {
++    float x, y;
++  };
++
++  std::vector<Svertex> vertices{
++      {windowRect.x1, windowRect.y2 * 2},
++      {windowRect.x1, windowRect.y1},
++      {windowRect.x2 * 2, windowRect.y1},
++  };
++
++  glDisable(GL_BLEND);
++
++  m_renderSystem->EnableShader(ShaderMethodGL::SM_DEFAULT);
++  GLint posLoc = m_renderSystem->ShaderGetPos();
++  GLint uniCol = m_renderSystem->ShaderGetUniCol();
++
++  glUniform4f(uniCol, m_clearColour / 255.0f, m_clearColour / 255.0f, m_clearColour / 255.0f, 1.0f);
++
++  GLuint vertexVBO;
++  glGenBuffers(1, &vertexVBO);
++  glBindBuffer(GL_ARRAY_BUFFER, vertexVBO);
++  glBufferData(GL_ARRAY_BUFFER, sizeof(Svertex) * vertices.size(), vertices.data(), GL_STATIC_DRAW);
++
++  glVertexAttribPointer(posLoc, 2, GL_FLOAT, GL_FALSE, sizeof(Svertex), 0);
++  glEnableVertexAttribArray(posLoc);
++
++  glDrawArrays(GL_TRIANGLES, 0, vertices.size());
++
++  glDisableVertexAttribArray(posLoc);
++  glBindBuffer(GL_ARRAY_BUFFER, 0);
++  glDeleteBuffers(1, &vertexVBO);
++
++  m_renderSystem->DisableShader();
+ }
+
+ //draw black bars around the video quad, this is more efficient than glClear()
+@@ -1047,8 +1094,6 @@ void CLinuxRendererGL::RenderSinglePass(int index, int field)
+     LoadShaders(field);
+   }
+
+-  glDisable(GL_DEPTH_TEST);
+-
+   // Y
+   glActiveTexture(GL_TEXTURE0);
+   glBindTexture(m_textureTarget, planes[0].id);
+@@ -1219,8 +1264,6 @@ void CLinuxRendererGL::RenderToFBO(int index, int field, bool weave /*= false*/)
+     }
+   }
+
+-  glDisable(GL_DEPTH_TEST);
+-
+   // Y
+   glActiveTexture(GL_TEXTURE0);
+   glBindTexture(m_textureTarget, planes[0].id);
+diff --git a/xbmc/cores/VideoPlayer/VideoRenderers/LinuxRendererGL.h b/xbmc/cores/VideoPlayer/VideoRenderers/LinuxRendererGL.h
+index 31a3c273bfc7c..da1b4f628e862 100644
+--- a/xbmc/cores/VideoPlayer/VideoRenderers/LinuxRendererGL.h
++++ b/xbmc/cores/VideoPlayer/VideoRenderers/LinuxRendererGL.h
+@@ -87,6 +87,7 @@ class CLinuxRendererGL : public CBaseRenderer
+
+   bool Render(unsigned int flags, int renderBuffer);
+   void ClearBackBuffer();
++  void ClearBackBufferQuad();
+   void DrawBlackBars();
+
+   bool ValidateRenderer();
+diff --git a/xbmc/cores/VideoPlayer/VideoRenderers/LinuxRendererGLES.cpp b/xbmc/cores/VideoPlayer/VideoRenderers/LinuxRendererGLES.cpp
+index a0ed2c1ab4cb1..6ba930e7d2c98 100644
+--- a/xbmc/cores/VideoPlayer/VideoRenderers/LinuxRendererGLES.cpp
++++ b/xbmc/cores/VideoPlayer/VideoRenderers/LinuxRendererGLES.cpp
+@@ -357,6 +357,63 @@ void CLinuxRendererGLES::Update()
+   ValidateRenderTarget();
+ }
+
++void CLinuxRendererGLES::ClearBackBuffer()
++{
++  //set the entire backbuffer to black
++  //if we do a two pass render, we have to draw a quad. else we might occlude OSD elements.
++  if (CServiceBroker::GetWinSystem()->GetGfxContext().GetRenderOrder() ==
++      RENDER_ORDER_ALL_BACK_TO_FRONT)
++  {
++    CServiceBroker::GetWinSystem()->GetGfxContext().Clear(0xff000000);
++  }
++  else
++  {
++    ClearBackBufferQuad();
++  }
++}
++
++void CLinuxRendererGLES::ClearBackBufferQuad()
++{
++  CRect windowRect(0, 0, CServiceBroker::GetWinSystem()->GetGfxContext().GetWidth(),
++                   CServiceBroker::GetWinSystem()->GetGfxContext().GetHeight());
++  struct Svertex
++  {
++    float x, y;
++  };
++
++  std::vector<Svertex> vertices{
++      {windowRect.x1, windowRect.y2 * 2},
++      {windowRect.x1, windowRect.y1},
++      {windowRect.x2 * 2, windowRect.y1},
++  };
++
++  glDisable(GL_BLEND);
++
++  m_renderSystem->EnableGUIShader(ShaderMethodGLES::SM_DEFAULT);
++  GLint posLoc = m_renderSystem->GUIShaderGetPos();
++  GLint uniCol = m_renderSystem->GUIShaderGetUniCol();
++  GLint depthLoc = m_renderSystem->GUIShaderGetDepth();
++
++  glUniform4f(uniCol, m_clearColour / 255.0f, m_clearColour / 255.0f, m_clearColour / 255.0f, 1.0f);
++  glUniform1f(depthLoc, -1);
++
++  GLuint vertexVBO;
++  glGenBuffers(1, &vertexVBO);
++  glBindBuffer(GL_ARRAY_BUFFER, vertexVBO);
++  glBufferData(GL_ARRAY_BUFFER, sizeof(Svertex) * vertices.size(), vertices.data(), GL_STATIC_DRAW);
++
++  glVertexAttribPointer(posLoc, 2, GL_FLOAT, GL_FALSE, sizeof(Svertex), 0);
++  glEnableVertexAttribArray(posLoc);
++
++  glDrawArrays(GL_TRIANGLES, 0, vertices.size());
++
++  glDisableVertexAttribArray(posLoc);
++  glBindBuffer(GL_ARRAY_BUFFER, 0);
++  glDeleteBuffers(1, &vertexVBO);
++
++  m_renderSystem->DisableGUIShader();
++}
++
+ void CLinuxRendererGLES::DrawBlackBars()
+ {
+   CRect windowRect(0, 0, CServiceBroker::GetWinSystem()->GetGfxContext().GetWidth(),
+@@ -399,8 +456,10 @@ void CLinuxRendererGLES::DrawBlackBars()
+   renderSystem->EnableGUIShader(ShaderMethodGLES::SM_DEFAULT);
+   GLint posLoc = renderSystem->GUIShaderGetPos();
+   GLint uniCol = renderSystem->GUIShaderGetUniCol();
++  GLint depthLoc = m_renderSystem->GUIShaderGetDepth();
+
+   glUniform4f(uniCol, m_clearColour / 255.0f, m_clearColour / 255.0f, m_clearColour / 255.0f, 1.0f);
++  glUniform1f(depthLoc, -1);
+
+   GLuint vertexVBO;
+   glGenBuffers(1, &vertexVBO);
+@@ -431,6 +490,9 @@ void CLinuxRendererGLES::RenderUpdate(int index, int index2, bool clear, unsigne
+   // if its first pass, just init textures and return
+   if (ValidateRenderTarget())
+   {
++    if (clear) //if clear is set, we're expected to overwrite all backbuffer pixels, even if we have nothing to render
++      ClearBackBuffer();
++
+     return;
+   }
+
+@@ -455,9 +517,7 @@ void CLinuxRendererGLES::RenderUpdate(int index, int index2, bool clear, unsigne
+       DrawBlackBars();
+     else
+     {
+-      glClearColor(m_clearColour, m_clearColour, m_clearColour, 0);
+-      glClear(GL_COLOR_BUFFER_BIT);
+-      glClearColor(0, 0, 0, 0);
++      ClearBackBuffer();
+     }
+   }
+
+@@ -489,7 +549,8 @@ void CLinuxRendererGLES::RenderUpdate(int index, int index2, bool clear, unsigne
+     }
+   }
+
+-  Render(flags, index);
++  if (!Render(flags, index) && clear)
++    ClearBackBuffer();
+
+   VerifyGLState();
+   glEnable(GL_BLEND);
+@@ -783,7 +844,7 @@ bool CLinuxRendererGLES::UploadTexture(int index)
+   return ret;
+ }
+
+-void CLinuxRendererGLES::Render(unsigned int flags, int index)
++bool CLinuxRendererGLES::Render(unsigned int flags, int index)
+ {
+   // obtain current field, if interlaced
+   if( flags & RENDER_FLAG_TOP)
+@@ -802,7 +863,7 @@ void CLinuxRendererGLES::Render(unsigned int flags, int index)
+   // call texture load function
+   if (!UploadTexture(index))
+   {
+-    return;
++    return false;
+   }
+
+   if (RenderHook(index))
+@@ -832,8 +893,13 @@ void CLinuxRendererGLES::Render(unsigned int flags, int index)
+       break;
+     }
+   }
++  else
++  {
++    return false;
++  }
+
+   AfterRenderHook(index);
++  return true;
+ }
+
+ void CLinuxRendererGLES::RenderSinglePass(int index, int field)
+@@ -871,8 +937,6 @@ void CLinuxRendererGLES::RenderSinglePass(int index, int field)
+     LoadShaders(field);
+   }
+
+-  glDisable(GL_DEPTH_TEST);
+-
+   // Y
+   glActiveTexture(GL_TEXTURE0);
+   glBindTexture(m_textureTarget, planes[0].id);
+@@ -1021,8 +1085,6 @@ void CLinuxRendererGLES::RenderToFBO(int index, int field)
+     }
+   }
+
+-  glDisable(GL_DEPTH_TEST);
+-
+   // Y
+   glActiveTexture(GL_TEXTURE0);
+   glBindTexture(m_textureTarget, planes[0].id);
+diff --git a/xbmc/cores/VideoPlayer/VideoRenderers/LinuxRendererGLES.h b/xbmc/cores/VideoPlayer/VideoRenderers/LinuxRendererGLES.h
+index 31157fe6a5b06..5fb5118fbd4ba 100644
+--- a/xbmc/cores/VideoPlayer/VideoRenderers/LinuxRendererGLES.h
++++ b/xbmc/cores/VideoPlayer/VideoRenderers/LinuxRendererGLES.h
+@@ -91,7 +91,7 @@ class CLinuxRendererGLES : public CBaseRenderer
+   static const int FIELD_TOP{1};
+   static const int FIELD_BOT{2};
+
+-  virtual void Render(unsigned int flags, int index);
++  virtual bool Render(unsigned int flags, int index);
+   virtual void RenderUpdateVideo(bool clear, unsigned int flags = 0, unsigned int alpha = 255);
+
+   int NextYV12Texture();
+@@ -212,5 +212,7 @@ class CLinuxRendererGLES : public CBaseRenderer
+   CRect m_viewRect;
+
+ private:
++  void ClearBackBuffer();
++  void ClearBackBufferQuad();
+   void DrawBlackBars();
+ };
+diff --git a/xbmc/cores/VideoPlayer/VideoRenderers/OverlayRenderer.cpp b/xbmc/cores/VideoPlayer/VideoRenderers/OverlayRenderer.cpp
+index dfd4b3122778e..246128003a680 100644
+--- a/xbmc/cores/VideoPlayer/VideoRenderers/OverlayRenderer.cpp
++++ b/xbmc/cores/VideoPlayer/VideoRenderers/OverlayRenderer.cpp
+@@ -138,7 +138,7 @@ void CRenderer::ReleaseUnused()
+   }
+ }
+
+-void CRenderer::Render(int idx)
++void CRenderer::Render(int idx, float depth)
+ {
+   std::unique_lock<CCriticalSection> lock(m_section);
+
+diff --git a/xbmc/cores/VideoPlayer/VideoRenderers/OverlayRenderer.h b/xbmc/cores/VideoPlayer/VideoRenderers/OverlayRenderer.h
+index a6690004e6df6..a79f601af56fa 100644
+--- a/xbmc/cores/VideoPlayer/VideoRenderers/OverlayRenderer.h
++++ b/xbmc/cores/VideoPlayer/VideoRenderers/OverlayRenderer.h
+@@ -99,7 +99,7 @@ namespace OVERLAY {
+     void Notify(const Observable& obs, const ObservableMessage msg) override;
+
+     void AddOverlay(std::shared_ptr<CDVDOverlay> o, double pts, int index);
+-    virtual void Render(int idx);
++    virtual void Render(int idx, float depth = 0.0f);
+
+     /*!
+      * \brief Release resources
+diff --git a/xbmc/cores/VideoPlayer/VideoRenderers/OverlayRendererGL.cpp b/xbmc/cores/VideoPlayer/VideoRenderers/OverlayRendererGL.cpp
+index 8559d22eae223..7f2debce85b77 100644
+--- a/xbmc/cores/VideoPlayer/VideoRenderers/OverlayRendererGL.cpp
++++ b/xbmc/cores/VideoPlayer/VideoRenderers/OverlayRendererGL.cpp
+@@ -293,6 +293,7 @@ void COverlayGlyphGL::Render(SRenderState& state)
+   GLint posLoc  = renderSystem->ShaderGetPos();
+   GLint colLoc  = renderSystem->ShaderGetCol();
+   GLint tex0Loc = renderSystem->ShaderGetCoord0();
++  GLint depthLoc = renderSystem->ShaderGetDepth();
+   GLint matrixUniformLoc = renderSystem->ShaderGetMatrix();
+
+   CMatrixGL matrix = glMatrixProject.Get();
+@@ -330,6 +331,8 @@ void COverlayGlyphGL::Render(SRenderState& state)
+   glEnableVertexAttribArray(colLoc);
+   glEnableVertexAttribArray(tex0Loc);
+
++  glUniform1f(depthLoc, -1.0f);
++
+   glDrawArrays(GL_TRIANGLES, 0, vecVertices.size());
+
+   glDisableVertexAttribArray(posLoc);
+@@ -401,6 +404,7 @@ void COverlayTextureGL::Render(SRenderState& state)
+   GLint posLoc = renderSystem->ShaderGetPos();
+   GLint tex0Loc = renderSystem->ShaderGetCoord0();
+   GLint uniColLoc = renderSystem->ShaderGetUniCol();
++  GLint depthLoc = renderSystem->ShaderGetDepth();
+
+   GLfloat col[4] = {1.0f, 1.0f, 1.0f, 1.0f};
+
+@@ -456,6 +460,8 @@ void COverlayTextureGL::Render(SRenderState& state)
+   glBindBuffer(GL_ELEMENT_ARRAY_BUFFER, indexVBO);
+   glBufferData(GL_ELEMENT_ARRAY_BUFFER, sizeof(GLubyte)*4, idx, GL_STATIC_DRAW);
+
++  glUniform1f(depthLoc, -1.0f);
++
+   glDrawElements(GL_TRIANGLE_STRIP, 4, GL_UNSIGNED_BYTE, 0);
+
+   glDisableVertexAttribArray(posLoc);
+diff --git a/xbmc/cores/VideoPlayer/VideoRenderers/OverlayRendererGLES.cpp b/xbmc/cores/VideoPlayer/VideoRenderers/OverlayRendererGLES.cpp
+index 237afacc42c3a..4f4b39b038aac 100644
+--- a/xbmc/cores/VideoPlayer/VideoRenderers/OverlayRendererGLES.cpp
++++ b/xbmc/cores/VideoPlayer/VideoRenderers/OverlayRendererGLES.cpp
+@@ -352,6 +352,7 @@ void COverlayGlyphGLES::Render(SRenderState& state)
+   GLint posLoc = renderSystem->GUIShaderGetPos();
+   GLint colLoc = renderSystem->GUIShaderGetCol();
+   GLint tex0Loc = renderSystem->GUIShaderGetCoord0();
++  GLint depthLoc = renderSystem->GUIShaderGetDepth();
+   GLint matrixUniformLoc = renderSystem->GUIShaderGetMatrix();
+
+   CMatrixGL matrix = glMatrixProject.Get();
+@@ -386,6 +387,8 @@ void COverlayGlyphGLES::Render(SRenderState& state)
+   glEnableVertexAttribArray(colLoc);
+   glEnableVertexAttribArray(tex0Loc);
+
++  glUniform1f(depthLoc, -1.0f);
++
+   glDrawArrays(GL_TRIANGLES, 0, vecVertices.size());
+
+   glDisableVertexAttribArray(posLoc);
+@@ -448,6 +451,7 @@ void COverlayTextureGLES::Render(SRenderState& state)
+   GLint colLoc = renderSystem->GUIShaderGetCol();
+   GLint tex0Loc = renderSystem->GUIShaderGetCoord0();
+   GLint uniColLoc = renderSystem->GUIShaderGetUniCol();
++  GLint depthLoc = renderSystem->GUIShaderGetDepth();
+
+   GLfloat col[4] = {1.0f, 1.0f, 1.0f, 1.0f};
+   GLfloat ver[4][2];
+@@ -463,6 +467,7 @@ void COverlayTextureGLES::Render(SRenderState& state)
+   glEnableVertexAttribArray(tex0Loc);
+
+   glUniform4f(uniColLoc, (col[0]), (col[1]), (col[2]), (col[3]));
++  glUniform1f(depthLoc, 1.0f);
+   // Setup vertex position values
+   ver[0][0] = ver[3][0] = rd.x1;
+   ver[0][1] = ver[1][1] = rd.y1;
+diff --git a/xbmc/guilib/GUIBaseContainer.cpp b/xbmc/guilib/GUIBaseContainer.cpp
+index 65d604c18f2b8..70c7a1a2bd9ba 100644
+--- a/xbmc/guilib/GUIBaseContainer.cpp
++++ b/xbmc/guilib/GUIBaseContainer.cpp
+@@ -286,6 +286,8 @@ void CGUIBaseContainer::Render()
+     float focusedPos = 0;
+     std::shared_ptr<CGUIListItem> focusedItem;
+     int current = offset - cacheBefore;
++
++    std::vector<RENDERITEM> renderitems;
+     while (pos < end && m_items.size())
+     {
+       int itemNo = CorrectOffset(current, 0);
+@@ -304,9 +306,9 @@ void CGUIBaseContainer::Render()
+         else
+         {
+           if (m_orientation == VERTICAL)
+-            RenderItem(origin.x, pos, item.get(), false);
++            renderitems.emplace_back(RENDERITEM{origin.x, pos, item, false});
+           else
+-            RenderItem(pos, origin.y, item.get(), false);
++            renderitems.emplace_back(RENDERITEM{pos, origin.y, item, false});
+         }
+       }
+       // increment our position
+@@ -317,9 +319,25 @@ void CGUIBaseContainer::Render()
+     if (focusedItem)
+     {
+       if (m_orientation == VERTICAL)
+-        RenderItem(origin.x, focusedPos, focusedItem.get(), true);
++        renderitems.emplace_back(RENDERITEM{origin.x, focusedPos, focusedItem, true});
+       else
+-        RenderItem(focusedPos, origin.y, focusedItem.get(), true);
++        renderitems.emplace_back(RENDERITEM{focusedPos, origin.y, focusedItem, true});
++    }
++
++    if (CServiceBroker::GetWinSystem()->GetGfxContext().GetRenderOrder() ==
++        RENDER_ORDER_FRONT_TO_BACK)
++    {
++      for (auto it = std::crbegin(renderitems); it != std::crend(renderitems); it++)
++      {
++        RenderItem(it->posX, it->posY, it->item.get(), it->focused);
++      }
++    }
++    else
++    {
++      for (const auto& renderitem : renderitems)
++      {
++        RenderItem(renderitem.posX, renderitem.posY, renderitem.item.get(), renderitem.focused);
++      }
+     }
+
+     CServiceBroker::GetWinSystem()->GetGfxContext().RestoreClipRegion();
+@@ -1045,6 +1063,37 @@ void CGUIBaseContainer::UpdateVisibility(const CGUIListItem *item)
+   UpdateListProvider();
+ }
+
++void CGUIBaseContainer::AssignDepth()
++{
++  std::shared_ptr<CGUIListItem> focusedItem = nullptr;
++  int32_t current = 0;
++
++  for (const auto& item : m_items)
++  {
++    bool focused = (current == GetOffset() + GetCursor());
++    if (focused)
++    {
++      focusedItem = item;
++    }
++    else
++    {
++      if (item->GetFocusedLayout())
++        item->GetFocusedLayout()->AssignDepth();
++      if (item->GetLayout())
++        item->GetLayout()->AssignDepth();
++    }
++    current++;
++  }
++
++  if (focusedItem)
++  {
++    if (focusedItem->GetFocusedLayout())
++      focusedItem->GetFocusedLayout()->AssignDepth();
++    if (focusedItem->GetLayout())
++      focusedItem->GetLayout()->AssignDepth();
++  }
++}
++
+ void CGUIBaseContainer::UpdateListProvider(bool forceRefresh /* = false */)
+ {
+   if (m_listProvider)
+diff --git a/xbmc/guilib/GUIBaseContainer.h b/xbmc/guilib/GUIBaseContainer.h
+index 38e68cf51de7f..15f63048fa6c5 100644
+--- a/xbmc/guilib/GUIBaseContainer.h
++++ b/xbmc/guilib/GUIBaseContainer.h
+@@ -50,6 +50,7 @@ class CGUIBaseContainer : public IGUIContainer
+   void AllocResources() override;
+   void FreeResources(bool immediately = false) override;
+   void UpdateVisibility(const CGUIListItem *item = NULL) override;
++  void AssignDepth() override;
+
+   virtual unsigned int GetRows() const;
+
+@@ -213,6 +214,14 @@ class CGUIBaseContainer : public IGUIContainer
+
+   unsigned int m_lastRenderTime;
+
++  struct RENDERITEM
++  {
++    float posX;
++    float posY;
++    std::shared_ptr<CGUIListItem> item;
++    bool focused;
++  };
++
+ private:
+   bool OnContextMenu();
+
+diff --git a/xbmc/guilib/GUIBorderedImage.cpp b/xbmc/guilib/GUIBorderedImage.cpp
+index 7c48ddb9e1567..0ed3044a115f1 100644
+--- a/xbmc/guilib/GUIBorderedImage.cpp
++++ b/xbmc/guilib/GUIBorderedImage.cpp
+@@ -56,9 +56,17 @@ void CGUIBorderedImage::Process(unsigned int currentTime, CDirtyRegionList &dirt
+
+ void CGUIBorderedImage::Render()
+ {
++  bool renderFrontToBack = CServiceBroker::GetWinSystem()->GetGfxContext().GetRenderOrder() ==
++                           RENDER_ORDER_FRONT_TO_BACK;
++
++  if (renderFrontToBack)
++    CGUIImage::Render();
++
+   if (!m_borderImage->GetFileName().empty() && m_texture->ReadyToRender())
+-    m_borderImage->Render();
+-  CGUIImage::Render();
++    m_borderImage->Render(-1);
++
++  if (!renderFrontToBack)
++    CGUIImage::Render();
+ }
+
+ CRect CGUIBorderedImage::CalcRenderRegion() const
+diff --git a/xbmc/guilib/GUIButtonControl.cpp b/xbmc/guilib/GUIButtonControl.cpp
+index f509371689be9..22ded687b717d 100644
+--- a/xbmc/guilib/GUIButtonControl.cpp
++++ b/xbmc/guilib/GUIButtonControl.cpp
+@@ -110,15 +110,27 @@ void CGUIButtonControl::Process(unsigned int currentTime, CDirtyRegionList &dirt
+
+ void CGUIButtonControl::Render()
+ {
+-  m_imgFocus->Render();
+-  m_imgNoFocus->Render();
++  if (CServiceBroker::GetWinSystem()->GetGfxContext().GetRenderOrder() ==
++      RENDER_ORDER_FRONT_TO_BACK)
++  {
++    m_imgNoFocus->Render();
++    m_imgFocus->Render(-1);
++  }
++  else
++  {
++    m_imgFocus->Render(-1);
++    m_imgNoFocus->Render();
++    RenderText();
++  }
+
+-  RenderText();
+   CGUIControl::Render();
+ }
+
+ void CGUIButtonControl::RenderText()
+ {
++  if (CServiceBroker::GetWinSystem()->GetGfxContext().GetRenderOrder() ==
++      RENDER_ORDER_FRONT_TO_BACK)
++    return;
+   m_label.Render();
+   m_label2.Render();
+ }
+diff --git a/xbmc/guilib/GUIControl.cpp b/xbmc/guilib/GUIControl.cpp
+index 0c6a902ebb732..7ae97281202b5 100644
+--- a/xbmc/guilib/GUIControl.cpp
++++ b/xbmc/guilib/GUIControl.cpp
+@@ -488,6 +488,11 @@ float CGUIControl::GetHeight() const
+   return m_height;
+ }
+
++void CGUIControl::AssignDepth()
++{
++  m_cachedTransform.depth = CServiceBroker::GetWinSystem()->GetGfxContext().GetDepth();
++}
++
+ void CGUIControl::MarkDirtyRegion(const unsigned int dirtyState)
+ {
+   // if the control is culled, bail
+diff --git a/xbmc/guilib/GUIControl.h b/xbmc/guilib/GUIControl.h
+index a57f02243b398..93b5dcf199530 100644
+--- a/xbmc/guilib/GUIControl.h
++++ b/xbmc/guilib/GUIControl.h
+@@ -184,6 +184,7 @@ class CGUIControl
+   virtual float GetYPosition() const;
+   virtual float GetWidth() const;
+   virtual float GetHeight() const;
++  virtual void AssignDepth();
+
+   void MarkDirtyRegion(const unsigned int dirtyState = DIRTY_STATE_CONTROL);
+   bool IsControlDirty() const { return m_controlDirtyState != 0; }
+diff --git a/xbmc/guilib/GUIControlGroup.cpp b/xbmc/guilib/GUIControlGroup.cpp
+index 11af2ea89e36a..61142c7b5d93f 100644
+--- a/xbmc/guilib/GUIControlGroup.cpp
++++ b/xbmc/guilib/GUIControlGroup.cpp
+@@ -108,12 +108,26 @@ void CGUIControlGroup::Render()
+   CPoint pos(GetPosition());
+   CServiceBroker::GetWinSystem()->GetGfxContext().SetOrigin(pos.x, pos.y);
+   CGUIControl *focusedControl = NULL;
+-  for (auto *control : m_children)
++  if (CServiceBroker::GetWinSystem()->GetGfxContext().GetRenderOrder() ==
++      RENDER_ORDER_FRONT_TO_BACK)
++  {
++    for (auto it = m_children.rbegin(); it != m_children.rend(); ++it)
++    {
++      if (m_renderFocusedLast && (*it)->HasFocus())
++        focusedControl = (*it);
++      else
++        (*it)->DoRender();
++    }
++  }
++  else
+   {
+-    if (m_renderFocusedLast && control->HasFocus())
+-      focusedControl = control;
+-    else
+-      control->DoRender();
++    for (auto* control : m_children)
++    {
++      if (m_renderFocusedLast && control->HasFocus())
++        focusedControl = control;
++      else
++        control->DoRender();
++    }
+   }
+   if (focusedControl)
+     focusedControl->DoRender();
+@@ -286,6 +300,23 @@ bool CGUIControlGroup::CanFocus() const
+   return false;
+ }
+
++void CGUIControlGroup::AssignDepth()
++{
++  CGUIControl* focusedControl = nullptr;
++  if (m_children.size())
++  {
++    for (auto* control : m_children)
++    {
++      if (m_renderFocusedLast && control->HasFocus())
++        focusedControl = control;
++      else
++        control->AssignDepth();
++    }
++  }
++  if (focusedControl)
++    focusedControl->AssignDepth();
++}
++
+ void CGUIControlGroup::SetInitialVisibility()
+ {
+   CGUIControl::SetInitialVisibility();
+diff --git a/xbmc/guilib/GUIControlGroup.h b/xbmc/guilib/GUIControlGroup.h
+index 5c13466949deb..73529dda79c12 100644
+--- a/xbmc/guilib/GUIControlGroup.h
++++ b/xbmc/guilib/GUIControlGroup.h
+@@ -41,6 +41,7 @@ class CGUIControlGroup : public CGUIControlLookup
+   void FreeResources(bool immediately = false) override;
+   void DynamicResourceAlloc(bool bOnOff) override;
+   bool CanFocus() const override;
++  void AssignDepth() override;
+
+   EVENT_RESULT SendMouseEvent(const CPoint& point, const KODI::MOUSE::CMouseEvent& event) override;
+   void UnfocusFromPoint(const CPoint &point) override;
+diff --git a/xbmc/guilib/GUIEditControl.cpp b/xbmc/guilib/GUIEditControl.cpp
+index fe85f1ac77d16..adf88357472c0 100644
+--- a/xbmc/guilib/GUIEditControl.cpp
++++ b/xbmc/guilib/GUIEditControl.cpp
+@@ -548,6 +548,9 @@ void CGUIEditControl::ProcessText(unsigned int currentTime)
+
+ void CGUIEditControl::RenderText()
+ {
++  if (CServiceBroker::GetWinSystem()->GetGfxContext().GetRenderOrder() ==
++      RENDER_ORDER_FRONT_TO_BACK)
++    return;
+   m_label.Render();
+
+   if (CServiceBroker::GetWinSystem()->GetGfxContext().SetClipRegion(m_clipRect.x1, m_clipRect.y1, m_clipRect.Width(), m_clipRect.Height()))
+diff --git a/xbmc/guilib/GUIFadeLabelControl.cpp b/xbmc/guilib/GUIFadeLabelControl.cpp
+index 1827c3d0c2941..89f994b0f056e 100644
+--- a/xbmc/guilib/GUIFadeLabelControl.cpp
++++ b/xbmc/guilib/GUIFadeLabelControl.cpp
+@@ -128,6 +128,7 @@ void CGUIFadeLabelControl::Process(unsigned int currentTime, CDirtyRegionList &d
+     m_fadeAnim.Animate(currentTime, true);
+     m_fadeAnim.RenderAnimation(matrix);
+     m_fadeMatrix = CServiceBroker::GetWinSystem()->GetGfxContext().AddTransform(matrix);
++    m_fadeMatrix.depth = m_fadeDepth;
+
+     if (m_fadeAnim.GetState() == ANIM_STATE_APPLIED)
+       m_fadeAnim.ResetAnimation();
+@@ -170,6 +171,9 @@ bool CGUIFadeLabelControl::UpdateColors(const CGUIListItem* item)
+
+ void CGUIFadeLabelControl::Render()
+ {
++  if (CServiceBroker::GetWinSystem()->GetGfxContext().GetRenderOrder() ==
++      RENDER_ORDER_FRONT_TO_BACK)
++    return;
+   if (!m_label.font)
+   { // nothing to render
+     CGUIControl::Render();
+@@ -243,6 +247,12 @@ bool CGUIFadeLabelControl::OnMessage(CGUIMessage& message)
+   return CGUIControl::OnMessage(message);
+ }
+
++void CGUIFadeLabelControl::AssignDepth()
++{
++  CGUIControl::AssignDepth();
++  m_fadeDepth = m_cachedTransform.depth;
++}
++
+ std::string CGUIFadeLabelControl::GetDescription() const
+ {
+   return (m_currentLabel < m_infoLabels.size()) ?  m_infoLabels[m_currentLabel].GetLabel(m_parentID) : "";
+diff --git a/xbmc/guilib/GUIFadeLabelControl.h b/xbmc/guilib/GUIFadeLabelControl.h
+index 9f5f7abe4b499..098a7527d4495 100644
+--- a/xbmc/guilib/GUIFadeLabelControl.h
++++ b/xbmc/guilib/GUIFadeLabelControl.h
+@@ -17,6 +17,7 @@
+ #include "GUILabel.h"
+ #include "guilib/guiinfo/GUIInfoLabel.h"
+
++#include <cstdint>
+ #include <vector>
+
+ /*!
+@@ -35,6 +36,7 @@ class CGUIFadeLabelControl : public CGUIControl
+   void Render() override;
+   bool CanFocus() const override;
+   bool OnMessage(CGUIMessage& message) override;
++  void AssignDepth() override;
+
+   void SetInfo(const std::vector<KODI::GUILIB::GUIINFO::CGUIInfoLabel> &vecInfo);
+   void SetScrolling(bool scroll) { m_scroll = scroll; }
+@@ -74,5 +76,7 @@ class CGUIFadeLabelControl : public CGUIControl
+   bool m_resetOnLabelChange;
+   bool m_randomized;
+   bool m_allLabelsShown = true;
++
++  uint32_t m_fadeDepth{0};
+ };
+
+diff --git a/xbmc/guilib/GUIFontTTFGL.cpp b/xbmc/guilib/GUIFontTTFGL.cpp
+index 3706883911c8c..603d5086ac08a 100644
+--- a/xbmc/guilib/GUIFontTTFGL.cpp
++++ b/xbmc/guilib/GUIFontTTFGL.cpp
+@@ -155,6 +155,7 @@ void CGUIFontTTFGL::LastEnd()
+   GLint clipUniformLoc = renderSystem->ShaderGetClip();
+   GLint coordStepUniformLoc = renderSystem->ShaderGetCoordStep();
+   GLint matrixUniformLoc = renderSystem->ShaderGetMatrix();
++  GLint depthLoc = renderSystem->ShaderGetDepth();
+
+   CreateStaticVertexBuffers();
+
+@@ -239,6 +240,10 @@ void CGUIFontTTFGL::LastEnd()
+
+       glUniformMatrix4fv(matrixUniformLoc, 1, GL_FALSE, matrix);
+
++      // Apply the depth value of the layer
++      float depth = CServiceBroker::GetWinSystem()->GetGfxContext().GetTransformDepth();
++      glUniform1f(depthLoc, depth);
++
+       // Bind the buffer to the OpenGL context's GL_ARRAY_BUFFER binding point
+       glBindBuffer(GL_ARRAY_BUFFER, m_vertexTrans[i].m_vertexBuffer->bufferHandle);
+
+diff --git a/xbmc/guilib/GUIFontTTFGLES.cpp b/xbmc/guilib/GUIFontTTFGLES.cpp
+index 67cceae441c62..3a23a1d1f2496 100644
+--- a/xbmc/guilib/GUIFontTTFGLES.cpp
++++ b/xbmc/guilib/GUIFontTTFGLES.cpp
+@@ -151,6 +151,7 @@ void CGUIFontTTFGLES::LastEnd()
+   GLint clipUniformLoc = renderSystem->GUIShaderGetClip();
+   GLint coordStepUniformLoc = renderSystem->GUIShaderGetCoordStep();
+   GLint matrixUniformLoc = renderSystem->GUIShaderGetMatrix();
++  GLint depthLoc = renderSystem->GUIShaderGetDepth();
+
+   CreateStaticVertexBuffers();
+
+@@ -232,6 +233,10 @@ void CGUIFontTTFGLES::LastEnd()
+       // the gui matrix doesn't align to exact pixel coords atm. correct it here for now.
+       matrix.Translatef(fractX, fractY, 0.0f);
+
++      // Apply the depth value of the layer
++      float depth = CServiceBroker::GetWinSystem()->GetGfxContext().GetTransformDepth();
++      glUniform1f(depthLoc, depth);
++
+       glUniformMatrix4fv(matrixUniformLoc, 1, GL_FALSE, matrix);
+
+       // Bind the buffer to the OpenGL context's GL_ARRAY_BUFFER binding point
+diff --git a/xbmc/guilib/GUILabelControl.cpp b/xbmc/guilib/GUILabelControl.cpp
+index 9728639b1369d..5f57fbc3a64b4 100644
+--- a/xbmc/guilib/GUILabelControl.cpp
++++ b/xbmc/guilib/GUILabelControl.cpp
+@@ -139,6 +139,9 @@ CRect CGUILabelControl::CalcRenderRegion() const
+
+ void CGUILabelControl::Render()
+ {
++  if (CServiceBroker::GetWinSystem()->GetGfxContext().GetRenderOrder() ==
++      RENDER_ORDER_FRONT_TO_BACK)
++    return;
+   m_label.Render();
+   CGUIControl::Render();
+ }
+diff --git a/xbmc/guilib/GUIListItemLayout.cpp b/xbmc/guilib/GUIListItemLayout.cpp
+index 3b0f774d3d54b..35ff8ac4624ee 100644
+--- a/xbmc/guilib/GUIListItemLayout.cpp
++++ b/xbmc/guilib/GUIListItemLayout.cpp
+@@ -237,6 +237,11 @@ void CGUIListItemLayout::FreeResources(bool immediately)
+   m_group.FreeResources(immediately);
+ }
+
++void CGUIListItemLayout::AssignDepth()
++{
++  m_group.AssignDepth();
++}
++
+ #ifdef _DEBUG
+ void CGUIListItemLayout::DumpTextureUse()
+ {
+diff --git a/xbmc/guilib/GUIListItemLayout.h b/xbmc/guilib/GUIListItemLayout.h
+index 69d4c4fa6383b..7ba75794dd4b5 100644
+--- a/xbmc/guilib/GUIListItemLayout.h
++++ b/xbmc/guilib/GUIListItemLayout.h
+@@ -34,6 +34,7 @@ class CGUIListItemLayout final
+   void SetInvalid() { m_invalidated = true; }
+   void FreeResources(bool immediately = false);
+   void SetParentControl(CGUIControl* control) { m_group.SetParentControl(control); }
++  void AssignDepth();
+
+   //#ifdef GUILIB_PYTHON_COMPATIBILITY
+   void CreateListControlLayouts(float width, float height, bool focused, const CLabelInfo &labelInfo, const CLabelInfo &labelInfo2, const CTextureInfo &texture, const CTextureInfo &textureFocus, float texHeight, float iconWidth, float iconHeight, const std::string &nofocusCondition, const std::string &focusCondition);
+diff --git a/xbmc/guilib/GUIListLabel.cpp b/xbmc/guilib/GUIListLabel.cpp
+index b3138eb7aaacb..6797ba99dc963 100644
+--- a/xbmc/guilib/GUIListLabel.cpp
++++ b/xbmc/guilib/GUIListLabel.cpp
+@@ -67,6 +67,9 @@ void CGUIListLabel::Process(unsigned int currentTime, CDirtyRegionList &dirtyreg
+
+ void CGUIListLabel::Render()
+ {
++  if (CServiceBroker::GetWinSystem()->GetGfxContext().GetRenderOrder() ==
++      RENDER_ORDER_FRONT_TO_BACK)
++    return;
+   m_label.Render();
+   CGUIControl::Render();
+ }
+diff --git a/xbmc/guilib/GUIPanelContainer.cpp b/xbmc/guilib/GUIPanelContainer.cpp
+index 6d641104029f0..3c757dc157301 100644
+--- a/xbmc/guilib/GUIPanelContainer.cpp
++++ b/xbmc/guilib/GUIPanelContainer.cpp
+@@ -114,6 +114,7 @@ void CGUIPanelContainer::Render()
+     std::shared_ptr<CGUIListItem> focusedItem;
+     int current = (offset - cacheBefore) * m_itemsPerRow;
+     int col = 0;
++    std::vector<RENDERITEM> renderitems;
+     while (pos < end && m_items.size())
+     {
+       if (current >= (int)m_items.size())
+@@ -132,9 +133,11 @@ void CGUIPanelContainer::Render()
+         else
+         {
+           if (m_orientation == VERTICAL)
+-            RenderItem(origin.x + col * m_layout->Size(HORIZONTAL), pos, item.get(), false);
++            renderitems.emplace_back(
++                RENDERITEM{origin.x + col * m_layout->Size(HORIZONTAL), pos, item, false});
+           else
+-            RenderItem(pos, origin.y + col * m_layout->Size(VERTICAL), item.get(), false);
++            renderitems.emplace_back(
++                RENDERITEM{pos, origin.y + col * m_layout->Size(VERTICAL), item, false});
+         }
+       }
+       // increment our position
+@@ -151,9 +154,27 @@ void CGUIPanelContainer::Render()
+     if (focusedItem)
+     {
+       if (m_orientation == VERTICAL)
+-        RenderItem(origin.x + focusedCol * m_layout->Size(HORIZONTAL), focusedPos, focusedItem.get(), true);
++        renderitems.emplace_back(RENDERITEM{origin.x + focusedCol * m_layout->Size(HORIZONTAL),
++                                            focusedPos, focusedItem, true});
+       else
+-        RenderItem(focusedPos, origin.y + focusedCol * m_layout->Size(VERTICAL), focusedItem.get(), true);
++        renderitems.emplace_back(RENDERITEM{
++            focusedPos, origin.y + focusedCol * m_layout->Size(VERTICAL), focusedItem, true});
++    }
++
++    if (CServiceBroker::GetWinSystem()->GetGfxContext().GetRenderOrder() ==
++        RENDER_ORDER_FRONT_TO_BACK)
++    {
++      for (auto it = std::crbegin(renderitems); it != std::crend(renderitems); it++)
++      {
++        RenderItem(it->posX, it->posY, it->item.get(), it->focused);
++      }
++    }
++    else
++    {
++      for (const auto& renderitem : renderitems)
++      {
++        RenderItem(renderitem.posX, renderitem.posY, renderitem.item.get(), renderitem.focused);
++      }
+     }
+
+     CServiceBroker::GetWinSystem()->GetGfxContext().RestoreClipRegion();
+diff --git a/xbmc/guilib/GUISettingsSliderControl.cpp b/xbmc/guilib/GUISettingsSliderControl.cpp
+index 1eb0e0e93ede0..31fb9832f2050 100644
+--- a/xbmc/guilib/GUISettingsSliderControl.cpp
++++ b/xbmc/guilib/GUISettingsSliderControl.cpp
+@@ -81,6 +81,9 @@ void CGUISettingsSliderControl::Render()
+ {
+   m_buttonControl.Render();
+   CGUISliderControl::Render();
++  if (CServiceBroker::GetWinSystem()->GetGfxContext().GetRenderOrder() ==
++      RENDER_ORDER_FRONT_TO_BACK)
++    return;
+   m_label.Render();
+ }
+
+diff --git a/xbmc/guilib/GUISpinControl.cpp b/xbmc/guilib/GUISpinControl.cpp
+index 2545985a345da..62a8caaaad1ec 100644
+--- a/xbmc/guilib/GUISpinControl.cpp
++++ b/xbmc/guilib/GUISpinControl.cpp
+@@ -555,6 +555,9 @@ void CGUISpinControl::Render()
+
+ void CGUISpinControl::RenderText(float posX, float posY, float width, float height)
+ {
++  if (CServiceBroker::GetWinSystem()->GetGfxContext().GetRenderOrder() ==
++      RENDER_ORDER_FRONT_TO_BACK)
++    return;
+   m_label.SetMaxRect(posX, posY, width, height);
+   m_label.SetColor(GetTextColor());
+   m_label.Render();
+diff --git a/xbmc/guilib/GUITextBox.cpp b/xbmc/guilib/GUITextBox.cpp
+index 898b7bb49e6e5..045de2b3e065d 100644
+--- a/xbmc/guilib/GUITextBox.cpp
++++ b/xbmc/guilib/GUITextBox.cpp
+@@ -197,6 +197,10 @@ void CGUITextBox::Process(unsigned int currentTime, CDirtyRegionList &dirtyregio
+
+ void CGUITextBox::Render()
+ {
++  if (CServiceBroker::GetWinSystem()->GetGfxContext().GetRenderOrder() ==
++      RENDER_ORDER_FRONT_TO_BACK)
++    return;
++
+   // render the repeat anim as appropriate
+   if (m_autoScrollRepeatAnim)
+     CServiceBroker::GetWinSystem()->GetGfxContext().SetTransform(m_cachedTextMatrix);
+@@ -389,6 +393,12 @@ void CGUITextBox::ResetAutoScrolling()
+     m_autoScrollRepeatAnim->ResetAnimation();
+ }
+
++void CGUITextBox::AssignDepth()
++{
++  CGUIControl::AssignDepth();
++  m_cachedTextMatrix.depth = m_cachedTransform.depth;
++}
++
+ unsigned int CGUITextBox::GetRows() const
+ {
+   return m_lines.size();
+diff --git a/xbmc/guilib/GUITextBox.h b/xbmc/guilib/GUITextBox.h
+index 7027731c31df0..23c6fc11e3ffc 100644
+--- a/xbmc/guilib/GUITextBox.h
++++ b/xbmc/guilib/GUITextBox.h
+@@ -49,6 +49,7 @@ class CGUITextBox : public CGUIControl, public CGUITextLayout
+   void SetAutoScrolling(const TiXmlNode *node);
+   void SetAutoScrolling(int delay, int time, int repeatTime, const std::string &condition = "");
+   void ResetAutoScrolling();
++  void AssignDepth() override;
+
+   bool GetCondition(int condition, int data) const override;
+   virtual std::string GetLabel(int info) const;
+diff --git a/xbmc/guilib/GUITexture.cpp b/xbmc/guilib/GUITexture.cpp
+index 7f2f51dbbc694..7a3e004ad911b 100644
+--- a/xbmc/guilib/GUITexture.cpp
++++ b/xbmc/guilib/GUITexture.cpp
+@@ -9,6 +9,7 @@
+ #include "GUITexture.h"
+
+ #include "GUILargeTextureManager.h"
++#include "Texture.h"
+ #include "TextureManager.h"
+ #include "utils/MathUtils.h"
+ #include "utils/StringUtils.h"
+@@ -52,13 +53,20 @@ CGUITexture* CGUITexture::CreateTexture(
+ void CGUITexture::DrawQuad(const CRect& coords,
+                            UTILS::COLOR::Color color,
+                            CTexture* texture,
+-                           const CRect* texCoords)
++                           const CRect* texCoords,
++                           const float depth,
++                           const bool blending)
+ {
++  // bail for now if we render front to back
++  if (CServiceBroker::GetWinSystem()->GetGfxContext().GetRenderOrder() ==
++      RENDER_ORDER_FRONT_TO_BACK)
++    return;
++
+   if (!m_drawQuadFunc)
+     throw std::runtime_error(
+         "No GUITexture DrawQuad function available. Did you forget to register?");
+
+-  m_drawQuadFunc(coords, color, texture, texCoords);
++  m_drawQuadFunc(coords, color, texture, texCoords, depth, blending);
+ }
+
+ CGUITexture::CGUITexture(
+@@ -163,29 +171,54 @@ bool CGUITexture::Process(unsigned int currentTime)
+   return changed;
+ }
+
+-void CGUITexture::Render()
++void CGUITexture::Render(int32_t depthOffset, int32_t overrideDepth)
+ {
+   if (!m_visible || !m_texture.size())
+     return;
+
+-  // see if we need to clip the image
+-  if (m_vertex.Width() > m_width || m_vertex.Height() > m_height)
+-  {
+-    if (!CServiceBroker::GetWinSystem()->GetGfxContext().SetClipRegion(m_posX, m_posY, m_width, m_height))
+-      return;
+-  }
+-
+   // set our draw color
+   #define MIX_ALPHA(a,c) (((a * (c >> 24)) / 255) << 24) | (c & 0x00ffffff)
+
+   // diffuse color
+   UTILS::COLOR::Color color =
+       (m_info.diffuseColor) ? (UTILS::COLOR::Color)m_info.diffuseColor : m_diffuseColor;
++  // clang-format off
+   if (m_alpha != 0xFF)
+-	  color = MIX_ALPHA(m_alpha, color);
++    color = MIX_ALPHA(m_alpha, color);
++  // clang-format on
+
+   color = CServiceBroker::GetWinSystem()->GetGfxContext().MergeColor(color);
+
++  if (overrideDepth >= 0)
++  {
++    m_depth = CServiceBroker::GetWinSystem()->GetGfxContext().GetNormalizedDepth(overrideDepth +
++                                                                                 depthOffset);
++  }
++  else
++  {
++    m_depth = CServiceBroker::GetWinSystem()->GetGfxContext().GetTransformDepth(depthOffset);
++  }
++
++  bool hasAlpha =
++      (((color >> 24) & 0xFF) != 0xFF || m_texture.m_textures[m_currentFrame]->HasAlpha());
++  if (m_diffuse.size())
++    hasAlpha |= m_diffuse.m_textures[0]->HasAlpha();
++
++  // bail if it is not the appropriate render pass
++  RENDER_ORDER renderOrder = CServiceBroker::GetWinSystem()->GetGfxContext().GetRenderOrder();
++  if (hasAlpha && renderOrder == RENDER_ORDER_FRONT_TO_BACK)
++    return;
++  if (!hasAlpha && renderOrder == RENDER_ORDER_BACK_TO_FRONT)
++    return;
++
++  // see if we need to clip the image
++  if (m_vertex.Width() > m_width || m_vertex.Height() > m_height)
++  {
++    if (!CServiceBroker::GetWinSystem()->GetGfxContext().SetClipRegion(m_posX, m_posY, m_width,
++                                                                       m_height))
++      return;
++  }
++
+   // setup our renderer
+   Begin(color);
+
+diff --git a/xbmc/guilib/GUITexture.h b/xbmc/guilib/GUITexture.h
+index c34dedc259de5..bbedc3aa212e5 100644
+--- a/xbmc/guilib/GUITexture.h
++++ b/xbmc/guilib/GUITexture.h
+@@ -67,8 +67,12 @@ class CGUITexture;
+
+ using CreateGUITextureFunc = std::function<CGUITexture*(
+     float posX, float posY, float width, float height, const CTextureInfo& texture)>;
+-using DrawQuadFunc = std::function<void(
+-    const CRect& coords, UTILS::COLOR::Color color, CTexture* texture, const CRect* texCoords)>;
++using DrawQuadFunc = std::function<void(const CRect& coords,
++                                        UTILS::COLOR::Color color,
++                                        CTexture* texture,
++                                        const CRect* texCoords,
++                                        const float depth,
++                                        const bool blending)>;
+
+ class CGUITexture
+ {
+@@ -85,10 +89,12 @@ class CGUITexture
+   static void DrawQuad(const CRect& coords,
+                        UTILS::COLOR::Color color,
+                        CTexture* texture = nullptr,
+-                       const CRect* texCoords = nullptr);
++                       const CRect* texCoords = nullptr,
++                       const float depth = 1.0,
++                       const bool blending = true);
+
+   bool Process(unsigned int currentTime);
+-  void Render();
++  void Render(int32_t depthOffset = 0, int32_t overrideDepth = -1);
+
+   void DynamicResourceAlloc(bool bOnOff);
+   bool AllocResources();
+@@ -172,6 +178,7 @@ class CGUITexture
+   float m_posY;
+   float m_width;
+   float m_height;
++  float m_depth{0};
+
+   CRect m_vertex;       // vertex coords to render
+   bool m_invalid;       // if true, we need to recalculate
+diff --git a/xbmc/guilib/GUITextureD3D.cpp b/xbmc/guilib/GUITextureD3D.cpp
+index d031cac40af1e..68ce6f06f7906 100644
+--- a/xbmc/guilib/GUITextureD3D.cpp
++++ b/xbmc/guilib/GUITextureD3D.cpp
+@@ -140,7 +140,9 @@ void CGUITextureD3D::Draw(float *x, float *y, float *z, const CRect &texture, co
+ void CGUITextureD3D::DrawQuad(const CRect& rect,
+                               UTILS::COLOR::Color color,
+                               CTexture* texture,
+-                              const CRect* texCoords)
++                              const CRect* texCoords,
++                              const float depth,
++                              const bool blending)
+ {
+   unsigned numViews = 0;
+   ID3D11ShaderResourceView* views = nullptr;
+diff --git a/xbmc/guilib/GUITextureD3D.h b/xbmc/guilib/GUITextureD3D.h
+index a649f85ab1f22..87fd9a784865b 100644
+--- a/xbmc/guilib/GUITextureD3D.h
++++ b/xbmc/guilib/GUITextureD3D.h
+@@ -21,7 +21,9 @@ class CGUITextureD3D : public CGUITexture
+   static void DrawQuad(const CRect& coords,
+                        UTILS::COLOR::Color color,
+                        CTexture* texture = nullptr,
+-                       const CRect* texCoords = nullptr);
++                       const CRect* texCoords = nullptr,
++                       const float depth = 1.0,
++                       const bool blending = true);
+
+   CGUITextureD3D(float posX, float posY, float width, float height, const CTextureInfo& texture);
+   ~CGUITextureD3D() override = default;
+diff --git a/xbmc/guilib/GUITextureGL.cpp b/xbmc/guilib/GUITextureGL.cpp
+index 6e46aa700a4c9..c2f23ccdfb594 100644
+--- a/xbmc/guilib/GUITextureGL.cpp
++++ b/xbmc/guilib/GUITextureGL.cpp
+@@ -108,6 +108,7 @@ void CGUITextureGL::End()
+     GLint tex0Loc = m_renderSystem->ShaderGetCoord0();
+     GLint tex1Loc = m_renderSystem->ShaderGetCoord1();
+     GLint uniColLoc = m_renderSystem->ShaderGetUniCol();
++    GLint depthLoc = m_renderSystem->ShaderGetDepth();
+
+     GLuint VertexVBO;
+     GLuint IndexVBO;
+@@ -116,6 +117,8 @@ void CGUITextureGL::End()
+     glBindBuffer(GL_ARRAY_BUFFER, VertexVBO);
+     glBufferData(GL_ARRAY_BUFFER, sizeof(PackedVertex)*m_packedVertices.size(), &m_packedVertices[0], GL_STATIC_DRAW);
+
++    glUniform1f(depthLoc, m_depth);
++
+     if (uniColLoc >= 0)
+     {
+       glUniform4f(uniColLoc,(m_col[0] / 255.0f), (m_col[1] / 255.0f), (m_col[2] / 255.0f), (m_col[3] / 255.0f));
+@@ -255,7 +258,9 @@ void CGUITextureGL::Draw(float *x, float *y, float *z, const CRect &texture, con
+ void CGUITextureGL::DrawQuad(const CRect& rect,
+                              UTILS::COLOR::Color color,
+                              CTexture* texture,
+-                             const CRect* texCoords)
++                             const CRect* texCoords,
++                             const float depth,
++                             const bool blending)
+ {
+   CRenderSystemGL *renderSystem = dynamic_cast<CRenderSystemGL*>(CServiceBroker::GetRenderSystem());
+   if (texture)
+@@ -264,8 +269,15 @@ void CGUITextureGL::DrawQuad(const CRect& rect,
+     texture->BindToUnit(0);
+   }
+
+-  glBlendFunc(GL_SRC_ALPHA,GL_ONE_MINUS_SRC_ALPHA);
+-  glEnable(GL_BLEND);          // Turn Blending On
++  if (blending)
++  {
++    glBlendFunc(GL_SRC_ALPHA, GL_ONE_MINUS_SRC_ALPHA);
++    glEnable(GL_BLEND);
++  }
++  else
++  {
++    glDisable(GL_BLEND);
++  }
+
+   VerifyGLState();
+
+@@ -288,6 +300,7 @@ void CGUITextureGL::DrawQuad(const CRect& rect,
+   GLint posLoc = renderSystem->ShaderGetPos();
+   GLint tex0Loc = renderSystem->ShaderGetCoord0();
+   GLint uniColLoc = renderSystem->ShaderGetUniCol();
++  GLint depthLoc = renderSystem->ShaderGetDepth();
+
+   // Setup Colors
+   col[0] = KODI::UTILS::GL::GetChannelFromARGB(KODI::UTILS::GL::ColorChannel::R, color);
+@@ -296,6 +309,7 @@ void CGUITextureGL::DrawQuad(const CRect& rect,
+   col[3] = KODI::UTILS::GL::GetChannelFromARGB(KODI::UTILS::GL::ColorChannel::A, color);
+
+   glUniform4f(uniColLoc, col[0] / 255.0f, col[1] / 255.0f, col[2] / 255.0f, col[3] / 255.0f);
++  glUniform1f(depthLoc, depth);
+
+   // bottom left
+   vertex[0].x = rect.x1;
+diff --git a/xbmc/guilib/GUITextureGL.h b/xbmc/guilib/GUITextureGL.h
+index 4acba1eb6dedf..5850586a2222c 100644
+--- a/xbmc/guilib/GUITextureGL.h
++++ b/xbmc/guilib/GUITextureGL.h
+@@ -27,7 +27,9 @@ class CGUITextureGL : public CGUITexture
+   static void DrawQuad(const CRect& coords,
+                        UTILS::COLOR::Color color,
+                        CTexture* texture = nullptr,
+-                       const CRect* texCoords = nullptr);
++                       const CRect* texCoords = nullptr,
++                       const float depth = 1.0,
++                       const bool blending = true);
+
+   CGUITextureGL(float posX, float posY, float width, float height, const CTextureInfo& texture);
+   ~CGUITextureGL() override = default;
+diff --git a/xbmc/guilib/GUITextureGLES.cpp b/xbmc/guilib/GUITextureGLES.cpp
+index d92201ae7fcce..97fdb28679dfd 100644
+--- a/xbmc/guilib/GUITextureGLES.cpp
++++ b/xbmc/guilib/GUITextureGLES.cpp
+@@ -114,12 +114,15 @@ void CGUITextureGLES::End()
+     GLint tex0Loc = m_renderSystem->GUIShaderGetCoord0();
+     GLint tex1Loc = m_renderSystem->GUIShaderGetCoord1();
+     GLint uniColLoc = m_renderSystem->GUIShaderGetUniCol();
++    GLint depthLoc = m_renderSystem->GUIShaderGetDepth();
+
+     if(uniColLoc >= 0)
+     {
+       glUniform4f(uniColLoc,(m_col[0] / 255.0f), (m_col[1] / 255.0f), (m_col[2] / 255.0f), (m_col[3] / 255.0f));
+     }
+
++    glUniform1f(depthLoc, m_depth);
++
+     if(m_diffuse.size())
+     {
+       glVertexAttribPointer(tex1Loc, 2, GL_FLOAT, 0, sizeof(PackedVertex), (char*)&m_packedVertices[0] + offsetof(PackedVertex, u2));
+@@ -234,7 +237,9 @@ void CGUITextureGLES::Draw(float *x, float *y, float *z, const CRect &texture, c
+ void CGUITextureGLES::DrawQuad(const CRect& rect,
+                                UTILS::COLOR::Color color,
+                                CTexture* texture,
+-                               const CRect* texCoords)
++                               const CRect* texCoords,
++                               const float depth,
++                               const bool blending)
+ {
+   CRenderSystemGLES *renderSystem = dynamic_cast<CRenderSystemGLES*>(CServiceBroker::GetRenderSystem());
+   if (texture)
+@@ -243,8 +248,15 @@ void CGUITextureGLES::DrawQuad(const CRect& rect,
+     texture->BindToUnit(0);
+   }
+
+-  glBlendFunc(GL_SRC_ALPHA,GL_ONE_MINUS_SRC_ALPHA);
+-  glEnable(GL_BLEND);          // Turn Blending On
++  if (blending)
++  {
++    glBlendFunc(GL_SRC_ALPHA, GL_ONE_MINUS_SRC_ALPHA);
++    glEnable(GL_BLEND);
++  }
++  else
++  {
++    glDisable(GL_BLEND);
++  }
+
+   VerifyGLState();
+
+@@ -261,6 +273,7 @@ void CGUITextureGLES::DrawQuad(const CRect& rect,
+   GLint posLoc   = renderSystem->GUIShaderGetPos();
+   GLint tex0Loc  = renderSystem->GUIShaderGetCoord0();
+   GLint uniColLoc= renderSystem->GUIShaderGetUniCol();
++  GLint depthLoc = renderSystem->GUIShaderGetDepth();
+
+   glVertexAttribPointer(posLoc,  3, GL_FLOAT, 0, 0, ver);
+   if (texture)
+@@ -277,6 +290,7 @@ void CGUITextureGLES::DrawQuad(const CRect& rect,
+   col[3] = KODI::UTILS::GL::GetChannelFromARGB(KODI::UTILS::GL::ColorChannel::A, color);
+
+   glUniform4f(uniColLoc, col[0] / 255.0f, col[1] / 255.0f, col[2] / 255.0f, col[3] / 255.0f);
++  glUniform1f(depthLoc, depth);
+
+   ver[0][0] = ver[3][0] = rect.x1;
+   ver[0][1] = ver[1][1] = rect.y1;
+diff --git a/xbmc/guilib/GUITextureGLES.h b/xbmc/guilib/GUITextureGLES.h
+index a9b361031b1cd..ad563704e088d 100644
+--- a/xbmc/guilib/GUITextureGLES.h
++++ b/xbmc/guilib/GUITextureGLES.h
+@@ -36,7 +36,9 @@ class CGUITextureGLES : public CGUITexture
+   static void DrawQuad(const CRect& coords,
+                        UTILS::COLOR::Color color,
+                        CTexture* texture = nullptr,
+-                       const CRect* texCoords = nullptr);
++                       const CRect* texCoords = nullptr,
++                       const float depth = 1.0,
++                       const bool blending = true);
+
+   CGUITextureGLES(float posX, float posY, float width, float height, const CTextureInfo& texture);
+   ~CGUITextureGLES() override = default;
+diff --git a/xbmc/guilib/GUIVideoControl.cpp b/xbmc/guilib/GUIVideoControl.cpp
+index a24b20e3cfd21..ccb066a75477b 100644
+--- a/xbmc/guilib/GUIVideoControl.cpp
++++ b/xbmc/guilib/GUIVideoControl.cpp
+@@ -9,6 +9,7 @@
+ #include "GUIVideoControl.h"
+
+ #include "GUIComponent.h"
++#include "GUITexture.h"
+ #include "GUIWindowManager.h"
+ #include "ServiceBroker.h"
+ #include "application/ApplicationComponents.h"
+@@ -17,6 +18,7 @@
+ #include "input/actions/ActionIDs.h"
+ #include "input/mouse/MouseEvent.h"
+ #include "utils/ColorUtils.h"
++#include "windowing/GraphicContext.h"
+
+ using namespace KODI;
+
+@@ -41,6 +43,9 @@ void CGUIVideoControl::Process(unsigned int currentTime, CDirtyRegionList &dirty
+
+ void CGUIVideoControl::Render()
+ {
++  if (CServiceBroker::GetWinSystem()->GetGfxContext().GetRenderOrder() ==
++      RENDER_ORDER_FRONT_TO_BACK)
++    return;
+   auto& components = CServiceBroker::GetAppComponents();
+   const auto appPlayer = components.GetComponent<CApplicationPlayer>();
+   if (appPlayer->IsRenderingVideo())
+@@ -64,7 +69,14 @@ void CGUIVideoControl::Render()
+       CRect region = GetRenderRegion();
+       region.Intersect(old);
+       CServiceBroker::GetWinSystem()->GetGfxContext().SetScissors(region);
+-      CServiceBroker::GetWinSystem()->GetGfxContext().Clear(0);
++
++      // with dual pass rendering, we need to "clear" with a quad, as we need to conserve the already rendered layers
++      if (CServiceBroker::GetWinSystem()->GetGfxContext().GetRenderOrder() ==
++          RENDER_ORDER_BACK_TO_FRONT)
++        CGUITexture::DrawQuad(region, 0x00000000, nullptr, nullptr, -1.0f, false);
++      else if (CServiceBroker::GetWinSystem()->GetGfxContext().GetRenderOrder() ==
++               RENDER_ORDER_ALL_BACK_TO_FRONT)
++        CServiceBroker::GetWinSystem()->GetGfxContext().Clear(0);
+       CServiceBroker::GetWinSystem()->GetGfxContext().SetScissors(old);
+     }
+     else
+diff --git a/xbmc/guilib/GUIWindow.cpp b/xbmc/guilib/GUIWindow.cpp
+index ebb133d870fa3..36306ff90856b 100644
+--- a/xbmc/guilib/GUIWindow.cpp
++++ b/xbmc/guilib/GUIWindow.cpp
+@@ -1078,6 +1078,8 @@ void CGUIWindow::ClearBackground()
+   UTILS::COLOR::Color color = m_clearBackground;
+   if (color)
+     CServiceBroker::GetWinSystem()->GetGfxContext().Clear(color);
++  else
++    CServiceBroker::GetWinSystem()->GetGfxContext().Clear();
+ }
+
+ void CGUIWindow::SetID(int id)
+diff --git a/xbmc/guilib/GUIWindowManager.cpp b/xbmc/guilib/GUIWindowManager.cpp
+index abf7feae25846..993a34c7c91cc 100644
+--- a/xbmc/guilib/GUIWindowManager.cpp
++++ b/xbmc/guilib/GUIWindowManager.cpp
+@@ -1224,6 +1224,19 @@ void CGUIWindowManager::Process(unsigned int currentTime)
+       pWindow->DoProcess(currentTime, m_dirtyregions);
+   }
+
++  // assign depth values to all active controls
++  if (pWindow)
++    pWindow->AssignDepth();
++
++  std::vector<CGUIWindow*> activeDialogs = m_activeDialogs;
++  stable_sort(activeDialogs.begin(), activeDialogs.end(), RenderOrderSortFunction);
++
++  for (const auto& window : activeDialogs)
++  {
++    if (window->IsDialogRunning())
++      window->AssignDepth();
++  }
++
+   for (auto& itr : m_dirtyregions)
+     m_tracker.MarkDirtyRegion(itr);
+ }
+@@ -1249,6 +1262,14 @@ void CGUIWindowManager::MarkDirty(const CRect& rect)
+ }
+
+ void CGUIWindowManager::RenderPass() const
++{
++  if (CServiceBroker::GetSettingsComponent()->GetAdvancedSettings()->m_guiFrontToBackRendering)
++    RenderPassDual();
++  else
++    RenderPassSingle();
++}
++
++void CGUIWindowManager::RenderPassSingle() const
+ {
+   CGUIWindow* pWindow = GetWindow(GetActiveWindow());
+   if (pWindow)
+@@ -1268,6 +1289,40 @@ void CGUIWindowManager::RenderPass() const
+   }
+ }
+
++void CGUIWindowManager::RenderPassDual() const
++{
++  CGUIWindow* pWindow = GetWindow(GetActiveWindow());
++  if (pWindow)
++    pWindow->ClearBackground();
++
++  std::vector<CGUIWindow*> renderList = m_activeDialogs;
++  stable_sort(renderList.begin(), renderList.end(), RenderOrderSortFunction);
++
++  // first the opaque pass, rendering from front to back
++  CServiceBroker::GetWinSystem()->GetGfxContext().SetRenderOrder(RENDER_ORDER_FRONT_TO_BACK);
++  for (auto it = renderList.rbegin(); it != renderList.rend(); ++it)
++  {
++    if ((*it)->IsDialogRunning())
++      (*it)->DoRender();
++  }
++
++  if (pWindow)
++    pWindow->DoRender();
++
++  // now we render all elements with transparency back to front
++  CServiceBroker::GetWinSystem()->GetGfxContext().SetRenderOrder(RENDER_ORDER_BACK_TO_FRONT);
++  if (pWindow)
++  {
++    pWindow->DoRender();
++  }
++
++  for (const auto& window : renderList)
++  {
++    if (window->IsDialogRunning())
++      window->DoRender();
++  }
++}
++
+ void CGUIWindowManager::RenderEx() const
+ {
+   CGUIWindow* pWindow = GetWindow(GetActiveWindow());
+@@ -1337,6 +1392,7 @@ bool CGUIWindowManager::Render()
+
+ void CGUIWindowManager::AfterRender()
+ {
++  CServiceBroker::GetWinSystem()->GetGfxContext().ResetDepth();
+   m_tracker.CleanMarkedRegions();
+
+   CGUIWindow* pWindow = GetWindow(GetActiveWindow());
+diff --git a/xbmc/guilib/GUIWindowManager.h b/xbmc/guilib/GUIWindowManager.h
+index 9bbd281713f00..b7f2373d7724b 100644
+--- a/xbmc/guilib/GUIWindowManager.h
++++ b/xbmc/guilib/GUIWindowManager.h
+@@ -231,6 +231,12 @@ class CGUIWindowManager : public KODI::MESSAGING::IMessageTarget
+ #endif
+ private:
+   void RenderPass() const;
++  /*! \brief Render in one back to front pass.
++   */
++  void RenderPassSingle() const;
++  /*! \brief Render opaque elements front to back, and transparent ones back to front
++   */
++  void RenderPassDual() const;
+
+   void LoadNotOnDemandWindows();
+   void UnloadNotOnDemandWindows();
+diff --git a/xbmc/pictures/SlideShowPicture.cpp b/xbmc/pictures/SlideShowPicture.cpp
+index 005d7406542a6..fd0fd2cdd6125 100644
+--- a/xbmc/pictures/SlideShowPicture.cpp
++++ b/xbmc/pictures/SlideShowPicture.cpp
+@@ -727,6 +727,9 @@ void CSlideShowPic::Move(float fDeltaX, float fDeltaY)
+
+ void CSlideShowPic::Render()
+ {
++  if (CServiceBroker::GetWinSystem()->GetGfxContext().GetRenderOrder() ==
++      RENDER_ORDER_FRONT_TO_BACK)
++    return;
+   std::unique_lock<CCriticalSection> lock(m_textureAccess);
+
+   Render(m_ax, m_ay, m_pImage.get(), (m_alpha << 24) | 0xFFFFFF);
+diff --git a/xbmc/pictures/SlideShowPictureGL.cpp b/xbmc/pictures/SlideShowPictureGL.cpp
+index 5749bff2c1681..ee7ddb2a9f637 100644
+--- a/xbmc/pictures/SlideShowPictureGL.cpp
++++ b/xbmc/pictures/SlideShowPictureGL.cpp
+@@ -81,6 +81,7 @@ void CSlideShowPicGL::Render(float* x, float* y, CTexture* pTexture, UTILS::COLO
+   GLint posLoc = renderSystem->ShaderGetPos();
+   GLint tex0Loc = renderSystem->ShaderGetCoord0();
+   GLint uniColLoc = renderSystem->ShaderGetUniCol();
++  GLint depthLoc = renderSystem->ShaderGetDepth();
+
+   glGenBuffers(1, &vertexVBO);
+   glBindBuffer(GL_ARRAY_BUFFER, vertexVBO);
+@@ -102,6 +103,7 @@ void CSlideShowPicGL::Render(float* x, float* y, CTexture* pTexture, UTILS::COLO
+
+   glUniform4f(uniColLoc, (colour[0] / 255.0f), (colour[1] / 255.0f), (colour[2] / 255.0f),
+               (colour[3] / 255.0f));
++  glUniform1f(depthLoc, -1.0f);
+
+   glGenBuffers(1, &indexVBO);
+   glBindBuffer(GL_ELEMENT_ARRAY_BUFFER, indexVBO);
+diff --git a/xbmc/pictures/SlideShowPictureGLES.cpp b/xbmc/pictures/SlideShowPictureGLES.cpp
+index ce0200616df44..de41bbe77fb0c 100644
+--- a/xbmc/pictures/SlideShowPictureGLES.cpp
++++ b/xbmc/pictures/SlideShowPictureGLES.cpp
+@@ -53,6 +53,7 @@ void CSlideShowPicGLES::Render(float* x, float* y, CTexture* pTexture, UTILS::CO
+   GLint posLoc = renderSystem->GUIShaderGetPos();
+   GLint tex0Loc = renderSystem->GUIShaderGetCoord0();
+   GLint uniColLoc = renderSystem->GUIShaderGetUniCol();
++  GLint depthLoc = renderSystem->GUIShaderGetDepth();
+
+   glVertexAttribPointer(posLoc, 3, GL_FLOAT, 0, 0, ver);
+   glVertexAttribPointer(tex0Loc, 2, GL_FLOAT, 0, 0, tex);
+@@ -88,6 +89,7 @@ void CSlideShowPicGLES::Render(float* x, float* y, CTexture* pTexture, UTILS::CO
+
+   glUniform4f(uniColLoc, (col[0] / 255.0f), (col[1] / 255.0f), (col[2] / 255.0f),
+               (col[3] / 255.0f));
++  glUniform1f(depthLoc, -1.0f);
+   glDrawElements(GL_TRIANGLE_STRIP, 4, GL_UNSIGNED_BYTE, idx);
+
+   glDisableVertexAttribArray(posLoc);
+diff --git a/xbmc/pvr/guilib/GUIEPGGridContainer.cpp b/xbmc/pvr/guilib/GUIEPGGridContainer.cpp
+index d990f3f9db384..ffb9e4aa8b830 100644
+--- a/xbmc/pvr/guilib/GUIEPGGridContainer.cpp
++++ b/xbmc/pvr/guilib/GUIEPGGridContainer.cpp
+@@ -207,11 +207,23 @@ void CGUIEPGGridContainer::Process(unsigned int currentTime, CDirtyRegionList& d
+
+ void CGUIEPGGridContainer::Render()
+ {
+-  RenderChannels();
+-  RenderRulerDate();
+-  RenderRuler();
+-  RenderProgrammeGrid();
+-  RenderProgressIndicator();
++  if (CServiceBroker::GetWinSystem()->GetGfxContext().GetRenderOrder() ==
++      RENDER_ORDER_FRONT_TO_BACK)
++  {
++    RenderProgressIndicator();
++    RenderProgrammeGrid();
++    RenderRuler();
++    RenderRulerDate();
++    RenderChannels();
++  }
++  else
++  {
++    RenderChannels();
++    RenderRulerDate();
++    RenderRuler();
++    RenderProgrammeGrid();
++    RenderProgressIndicator();
++  }
+
+   CGUIControl::Render();
+ }
+@@ -316,7 +328,7 @@ void CGUIEPGGridContainer::RenderProgressIndicator()
+   if (CServiceBroker::GetWinSystem()->GetGfxContext().SetClipRegion(m_rulerPosX, m_rulerPosY, GetProgressIndicatorWidth(), GetProgressIndicatorHeight()))
+   {
+     m_guiProgressIndicatorTexture->SetDiffuseColor(m_diffuseColor);
+-    m_guiProgressIndicatorTexture->Render();
++    m_guiProgressIndicatorTexture->Render(0, m_guiProgressIndicatorTextureDepth);
+     CServiceBroker::GetWinSystem()->GetGfxContext().RestoreClipRegion();
+   }
+ }
+@@ -2090,7 +2102,10 @@ void CGUIEPGGridContainer::GetProgrammeCacheOffsets(int& cacheBefore, int& cache
+   }
+ }
+
+-void CGUIEPGGridContainer::HandleChannels(bool bRender, unsigned int currentTime, CDirtyRegionList& dirtyregions)
++void CGUIEPGGridContainer::HandleChannels(bool bRender,
++                                          unsigned int currentTime,
++                                          CDirtyRegionList& dirtyregions,
++                                          bool bAssignDepth)
+ {
+   if (!m_focusedChannelLayout || !m_channelLayout)
+     return;
+@@ -2171,6 +2186,13 @@ void CGUIEPGGridContainer::HandleChannels(bool bRender, unsigned int currentTime
+             RenderItem(pos, originChannel.y, item.get(), false);
+         }
+       }
++      else if (bAssignDepth)
++      {
++        if (focused)
++          focusedItem = item;
++        else
++          AssignItemDepth(item.get(), false);
++      }
+       else
+       {
+         // process our item
+@@ -2198,9 +2220,16 @@ void CGUIEPGGridContainer::HandleChannels(bool bRender, unsigned int currentTime
+
+     CServiceBroker::GetWinSystem()->GetGfxContext().RestoreClipRegion();
+   }
++  else if (bAssignDepth && focusedItem)
++  {
++    AssignItemDepth(focusedItem.get(), true);
++  }
+ }
+
+-void CGUIEPGGridContainer::HandleRulerDate(bool bRender, unsigned int currentTime, CDirtyRegionList& dirtyregions)
++void CGUIEPGGridContainer::HandleRulerDate(bool bRender,
++                                           unsigned int currentTime,
++                                           CDirtyRegionList& dirtyregions,
++                                           bool bAssignDepth)
+ {
+   if (!m_rulerDateLayout || m_gridModel->RulerItemsSize() <= 1 || m_gridModel->IsZeroGridDuration())
+     return;
+@@ -2214,6 +2243,10 @@ void CGUIEPGGridContainer::HandleRulerDate(bool bRender, unsigned int currentTim
+     RenderItem(m_posX, m_posY, item.get(), false);
+     CServiceBroker::GetWinSystem()->GetGfxContext().RestoreClipRegion();
+   }
++  else if (bAssignDepth)
++  {
++    AssignItemDepth(item.get(), false);
++  }
+   else
+   {
+     const int rulerOffset = GetProgrammeScrollOffset();
+@@ -2224,7 +2257,10 @@ void CGUIEPGGridContainer::HandleRulerDate(bool bRender, unsigned int currentTim
+   }
+ }
+
+-void CGUIEPGGridContainer::HandleRuler(bool bRender, unsigned int currentTime, CDirtyRegionList& dirtyregions)
++void CGUIEPGGridContainer::HandleRuler(bool bRender,
++                                       unsigned int currentTime,
++                                       CDirtyRegionList& dirtyregions,
++                                       bool bAssignDepth)
+ {
+   if (!m_rulerLayout || m_gridModel->RulerItemsSize() <= 1 || m_gridModel->IsZeroGridDuration())
+     return;
+@@ -2253,6 +2289,12 @@ void CGUIEPGGridContainer::HandleRuler(bool bRender, unsigned int currentTime, C
+     else
+       CServiceBroker::GetWinSystem()->GetGfxContext().SetClipRegion(m_rulerPosX, m_rulerPosY, m_rulerWidth, m_gridHeight);
+   }
++  else if (bAssignDepth)
++  {
++    if (!m_rulerDateLayout)
++      AssignItemDepth(item.get(), false);
++    GetProgrammeCacheOffsets(cacheBeforeRuler, cacheAfterRuler);
++  }
+   else
+   {
+     if (!m_rulerDateLayout)
+@@ -2311,6 +2353,8 @@ void CGUIEPGGridContainer::HandleRuler(bool bRender, unsigned int currentTime, C
+     {
+       if (bRender)
+         RenderItem(pos, originRuler.y, item.get(), false);
++      else if (bAssignDepth)
++        AssignItemDepth(item.get(), false);
+       else
+         ProcessItem(pos, originRuler.y, item, lastitem, false, m_rulerLayout, m_rulerLayout, currentTime, dirtyregions, m_rulerWidth);
+
+@@ -2320,6 +2364,8 @@ void CGUIEPGGridContainer::HandleRuler(bool bRender, unsigned int currentTime, C
+     {
+       if (bRender)
+         RenderItem(originRuler.x, pos, item.get(), false);
++      else if (bAssignDepth)
++        AssignItemDepth(item.get(), false);
+       else
+         ProcessItem(originRuler.x, pos, item, lastitem, false, m_rulerLayout, m_rulerLayout, currentTime, dirtyregions, m_rulerHeight);
+
+@@ -2333,7 +2379,10 @@ void CGUIEPGGridContainer::HandleRuler(bool bRender, unsigned int currentTime, C
+     CServiceBroker::GetWinSystem()->GetGfxContext().RestoreClipRegion();
+ }
+
+-void CGUIEPGGridContainer::HandleProgrammeGrid(bool bRender, unsigned int currentTime, CDirtyRegionList& dirtyregions)
++void CGUIEPGGridContainer::HandleProgrammeGrid(bool bRender,
++                                               unsigned int currentTime,
++                                               CDirtyRegionList& dirtyregions,
++                                               bool bAssignDepth)
+ {
+   if (!m_focusedProgrammeLayout || !m_programmeLayout || m_gridModel->RulerItemsSize() <= 1 || m_gridModel->IsZeroGridDuration())
+     return;
+@@ -2348,7 +2397,7 @@ void CGUIEPGGridContainer::HandleProgrammeGrid(bool bRender, unsigned int curren
+   {
+     CServiceBroker::GetWinSystem()->GetGfxContext().SetClipRegion(m_gridPosX, m_gridPosY, m_gridWidth, m_gridHeight);
+   }
+-  else
++  else if (!bAssignDepth)
+   {
+     int cacheBeforeChannel, cacheAfterChannel;
+     GetChannelCacheOffsets(cacheBeforeChannel, cacheAfterChannel);
+@@ -2460,6 +2509,24 @@ void CGUIEPGGridContainer::HandleProgrammeGrid(bool bRender, unsigned int curren
+               RenderItem(posB, posA2, item.get(), focused);
+           }
+         }
++        else if (bAssignDepth)
++        {
++          // reset to grid start position if first item is out of grid view
++          if (posA2 < posA)
++            posA2 = posA;
++
++          // render our item
++          if (focused)
++          {
++            focusedPosX = posA2;
++            focusedPosY = posB;
++            focusedItem = item;
++          }
++          else
++          {
++            AssignItemDepth(item.get(), focused);
++          }
++        }
+         else
+         {
+           // calculate the size to truncate if item is out of grid view
+@@ -2512,4 +2579,35 @@ void CGUIEPGGridContainer::HandleProgrammeGrid(bool bRender, unsigned int curren
+
+     CServiceBroker::GetWinSystem()->GetGfxContext().RestoreClipRegion();
+   }
++  else if (bAssignDepth && focusedItem)
++  {
++    AssignItemDepth(focusedItem.get(), true);
++  }
++}
++
++void CGUIEPGGridContainer::AssignDepth()
++{
++  unsigned int dummyTime = 0;
++  CDirtyRegionList dummyRegions;
++  HandleChannels(false, dummyTime, dummyRegions, true);
++  HandleRuler(false, dummyTime, dummyRegions, true);
++  HandleRulerDate(false, dummyTime, dummyRegions, true);
++  HandleProgrammeGrid(false, dummyTime, dummyRegions, true);
++  m_guiProgressIndicatorTextureDepth = CServiceBroker::GetWinSystem()->GetGfxContext().GetDepth();
+ }
++
++void CGUIEPGGridContainer::AssignItemDepth(CGUIListItem* item, bool focused)
++{
++  if (focused)
++  {
++    if (item->GetFocusedLayout())
++      item->GetFocusedLayout()->AssignDepth();
++  }
++  else
++  {
++    if (item->GetFocusedLayout() && item->GetFocusedLayout()->IsAnimating(ANIM_TYPE_UNFOCUS))
++      item->GetFocusedLayout()->AssignDepth();
++    else if (item->GetLayout())
++      item->GetLayout()->AssignDepth();
++  }
++}
+\ No newline at end of file
+diff --git a/xbmc/pvr/guilib/GUIEPGGridContainer.h b/xbmc/pvr/guilib/GUIEPGGridContainer.h
+index 09acfc7426d65..94b6043163137 100644
+--- a/xbmc/pvr/guilib/GUIEPGGridContainer.h
++++ b/xbmc/pvr/guilib/GUIEPGGridContainer.h
+@@ -128,6 +128,10 @@ namespace PVR
+      */
+     bool SetChannel(const CPVRChannelNumber& channelNumber);
+
++    virtual void AssignDepth() override;
++
++    void AssignItemDepth(CGUIListItem* item, bool focused);
++
+   private:
+     bool OnClick(int actionID);
+     bool SelectItemFromPoint(const CPoint& point, bool justGrid = true);
+@@ -201,10 +205,22 @@ namespace PVR
+     bool OnMouseDoubleClick(int dwButton, const CPoint& point);
+     bool OnMouseWheel(char wheel, const CPoint& point);
+
+-    void HandleChannels(bool bRender, unsigned int currentTime, CDirtyRegionList& dirtyregions);
+-    void HandleRuler(bool bRender, unsigned int currentTime, CDirtyRegionList& dirtyregions);
+-    void HandleRulerDate(bool bRender, unsigned int currentTime, CDirtyRegionList& dirtyregions);
+-    void HandleProgrammeGrid(bool bRender, unsigned int currentTime, CDirtyRegionList& dirtyregions);
++    void HandleChannels(bool bRender,
++                        unsigned int currentTime,
++                        CDirtyRegionList& dirtyregions,
++                        bool bAssignDepth = false);
++    void HandleRuler(bool bRender,
++                     unsigned int currentTime,
++                     CDirtyRegionList& dirtyregions,
++                     bool bAssignDepth = false);
++    void HandleRulerDate(bool bRender,
++                         unsigned int currentTime,
++                         CDirtyRegionList& dirtyregions,
++                         bool bAssignDepth = false);
++    void HandleProgrammeGrid(bool bRender,
++                             unsigned int currentTime,
++                             CDirtyRegionList& dirtyregions,
++                             bool bAssignDepth = false);
+
+     float GetCurrentTimePositionOnPage() const;
+     float GetProgressIndicatorWidth() const;
+@@ -248,6 +264,7 @@ namespace PVR
+     float m_analogScrollCount = 0;
+
+     std::unique_ptr<CGUITexture> m_guiProgressIndicatorTexture;
++    uint32_t m_guiProgressIndicatorTextureDepth{0};
+
+     std::shared_ptr<CFileItem> m_lastItem;
+     std::shared_ptr<CFileItem> m_lastChannel;
+diff --git a/xbmc/rendering/RenderSystem.h b/xbmc/rendering/RenderSystem.h
+index 334b74b4f868d..8e188cdf00f19 100644
+--- a/xbmc/rendering/RenderSystem.h
++++ b/xbmc/rendering/RenderSystem.h
+@@ -21,6 +21,13 @@
+  *   This interface is very basic since a lot of the actual details will go in to the derived classes
+  */
+
++enum DEPTH_CULLING
++{
++  DEPTH_CULLING_OFF = 0,
++  DEPTH_CULLING_BACK_TO_FRONT,
++  DEPTH_CULLING_FRONT_TO_BACK,
++};
++
+ class CGUIImage;
+ class CGUITextLayout;
+
+@@ -37,6 +44,7 @@ class CRenderSystemBase
+   virtual bool BeginRender() = 0;
+   virtual bool EndRender() = 0;
+   virtual void PresentRender(bool rendered, bool videoLayer) = 0;
++  virtual void InvalidateColorBuffer() {}
+   virtual bool ClearBuffers(UTILS::COLOR::Color color) = 0;
+   virtual bool IsExtSupported(const char* extension) const = 0;
+
+@@ -49,6 +57,8 @@ class CRenderSystemBase
+   virtual void SetScissors(const CRect &rect) = 0;
+   virtual void ResetScissors() = 0;
+
++  virtual void SetDepthCulling(DEPTH_CULLING culling) {}
++
+   virtual void CaptureStateBlock() = 0;
+   virtual void ApplyStateBlock() = 0;
+
+diff --git a/xbmc/rendering/gl/GLShader.cpp b/xbmc/rendering/gl/GLShader.cpp
+index 77dd6e4ed259e..a67601e77ce35 100644
+--- a/xbmc/rendering/gl/GLShader.cpp
++++ b/xbmc/rendering/gl/GLShader.cpp
+@@ -51,6 +51,7 @@ void CGLShader::OnCompiledAndLinked()
+   m_hMatrix = glGetUniformLocation(ProgramHandle(), "m_matrix");
+   m_hShaderClip = glGetUniformLocation(ProgramHandle(), "m_shaderClip");
+   m_hCoordStep = glGetUniformLocation(ProgramHandle(), "m_cordStep");
++  m_hDepth = glGetUniformLocation(ProgramHandle(), "m_depth");
+
+   // Vertex attributes
+   m_hPos = glGetAttribLocation(ProgramHandle(),  "m_attrpos");
+diff --git a/xbmc/rendering/gl/GLShader.h b/xbmc/rendering/gl/GLShader.h
+index 791c44926bd7e..8355043281c28 100644
+--- a/xbmc/rendering/gl/GLShader.h
++++ b/xbmc/rendering/gl/GLShader.h
+@@ -25,6 +25,7 @@ class CGLShader : public Shaders::CGLSLShaderProgram
+   GLint GetColLoc() {return m_hCol;}
+   GLint GetCord0Loc() {return m_hCord0;}
+   GLint GetCord1Loc() {return m_hCord1;}
++  GLint GetDepthLoc() { return m_hDepth; }
+   GLint GetUniColLoc() {return m_hUniCol;}
+   GLint GetModelLoc() {return m_hModel; }
+   GLint GetMatrixLoc() { return m_hMatrix; }
+@@ -49,6 +50,7 @@ class CGLShader : public Shaders::CGLSLShaderProgram
+   GLint m_hCol = 0;
+   GLint m_hCord0 = 0;
+   GLint m_hCord1 = 0;
++  GLint m_hDepth = 0;
+
+   const GLfloat *m_proj = nullptr;
+   const GLfloat *m_model = nullptr;
+diff --git a/xbmc/rendering/gl/RenderSystemGL.cpp b/xbmc/rendering/gl/RenderSystemGL.cpp
+index 516027ef49134..2e553e2ba50c5 100644
+--- a/xbmc/rendering/gl/RenderSystemGL.cpp
++++ b/xbmc/rendering/gl/RenderSystemGL.cpp
+@@ -222,8 +222,7 @@ bool CRenderSystemGL::ResetRenderSystem(int width, int height)
+   }
+
+   glBlendFunc(GL_SRC_ALPHA, GL_ONE);
+-  glEnable(GL_BLEND);          // Turn Blending On
+-  glDisable(GL_DEPTH_TEST);
++  glEnable(GL_BLEND); // Turn Blending On
+
+   return true;
+ }
+@@ -266,6 +265,30 @@ bool CRenderSystemGL::EndRender()
+   return true;
+ }
+
++void CRenderSystemGL::InvalidateColorBuffer()
++{
++  if (!m_bRenderCreated)
++    return;
++
++  /* clear is not affected by stipple pattern, so we can only clear on first frame */
++  if (m_stereoMode == RENDER_STEREO_MODE_INTERLACED && m_stereoView == RENDER_STEREO_VIEW_RIGHT)
++    return;
++
++  // some platforms prefer a clear, instead of rendering over
++  if (!CServiceBroker::GetSettingsComponent()->GetAdvancedSettings()->m_guiGeometryClear)
++  {
++    ClearBuffers(0);
++    return;
++  }
++
++  if (!CServiceBroker::GetSettingsComponent()->GetAdvancedSettings()->m_guiFrontToBackRendering)
++    return;
++
++  glClearDepthf(0);
++  glDepthMask(GL_TRUE);
++  glClear(GL_DEPTH_BUFFER_BIT);
++}
++
+ bool CRenderSystemGL::ClearBuffers(UTILS::COLOR::Color color)
+ {
+   if (!m_bRenderCreated)
+@@ -283,6 +306,14 @@ bool CRenderSystemGL::ClearBuffers(UTILS::COLOR::Color color)
+   glClearColor(r, g, b, a);
+
+   GLbitfield flags = GL_COLOR_BUFFER_BIT;
++
++  if (CServiceBroker::GetSettingsComponent()->GetAdvancedSettings()->m_guiFrontToBackRendering)
++  {
++    glClearDepthf(0);
++    glDepthMask(GL_TRUE);
++    flags |= GL_DEPTH_BUFFER_BIT;
++  }
++
+   glClear(flags);
+
+   return true;
+@@ -505,6 +536,27 @@ void CRenderSystemGL::ResetScissors()
+   SetScissors(CRect(0, 0, (float)m_width, (float)m_height));
+ }
+
++void CRenderSystemGL::SetDepthCulling(DEPTH_CULLING culling)
++{
++  if (culling == DEPTH_CULLING_OFF)
++  {
++    glDisable(GL_DEPTH_TEST);
++    glDepthMask(GL_FALSE);
++  }
++  else if (culling == DEPTH_CULLING_BACK_TO_FRONT)
++  {
++    glEnable(GL_DEPTH_TEST);
++    glDepthMask(GL_FALSE);
++    glDepthFunc(GL_GEQUAL);
++  }
++  else if (culling == DEPTH_CULLING_FRONT_TO_BACK)
++  {
++    glEnable(GL_DEPTH_TEST);
++    glDepthMask(GL_TRUE);
++    glDepthFunc(GL_GREATER);
++  }
++}
++
+ void CRenderSystemGL::GetGLSLVersion(int& major, int& minor)
+ {
+   major = m_glslMajor;
+@@ -810,6 +862,14 @@ GLint CRenderSystemGL::ShaderGetCoord1()
+   return -1;
+ }
+
++GLint CRenderSystemGL::ShaderGetDepth()
++{
++  if (m_pShader[m_method])
++    return m_pShader[m_method]->GetDepthLoc();
++
++  return -1;
++}
++
+ GLint CRenderSystemGL::ShaderGetUniCol()
+ {
+   if (m_pShader[m_method])
+diff --git a/xbmc/rendering/gl/RenderSystemGL.h b/xbmc/rendering/gl/RenderSystemGL.h
+index 520c552e45ab5..920024a37e2fa 100644
+--- a/xbmc/rendering/gl/RenderSystemGL.h
++++ b/xbmc/rendering/gl/RenderSystemGL.h
+@@ -75,6 +75,7 @@ class CRenderSystemGL : public CRenderSystemBase
+   bool BeginRender() override;
+   bool EndRender() override;
+   void PresentRender(bool rendered, bool videoLayer) override;
++  void InvalidateColorBuffer() override;
+   bool ClearBuffers(UTILS::COLOR::Color color) override;
+   bool IsExtSupported(const char* extension) const override;
+
+@@ -89,6 +90,8 @@ class CRenderSystemGL : public CRenderSystemBase
+   void SetScissors(const CRect &rect) override;
+   void ResetScissors() override;
+
++  void SetDepthCulling(DEPTH_CULLING culling) override;
++
+   void CaptureStateBlock() override;
+   void ApplyStateBlock() override;
+
+@@ -114,6 +117,7 @@ class CRenderSystemGL : public CRenderSystemBase
+   GLint ShaderGetCol();
+   GLint ShaderGetCoord0();
+   GLint ShaderGetCoord1();
++  GLint ShaderGetDepth();
+   GLint ShaderGetUniCol();
+   GLint ShaderGetModel();
+   GLint ShaderGetMatrix();
+diff --git a/xbmc/rendering/gles/GLESShader.cpp b/xbmc/rendering/gles/GLESShader.cpp
+index ba7b83175d57d..1dfebf6cb782a 100644
+--- a/xbmc/rendering/gles/GLESShader.cpp
++++ b/xbmc/rendering/gles/GLESShader.cpp
+@@ -57,6 +57,7 @@ void CGLESShader::OnCompiledAndLinked()
+   m_hMatrix = glGetUniformLocation(ProgramHandle(), "m_matrix");
+   m_hShaderClip = glGetUniformLocation(ProgramHandle(), "m_shaderClip");
+   m_hCoordStep = glGetUniformLocation(ProgramHandle(), "m_cordStep");
++  m_hDepth = glGetUniformLocation(ProgramHandle(), "m_depth");
+
+   // Vertex attributes
+   m_hPos    = glGetAttribLocation(ProgramHandle(),  "m_attrpos");
+diff --git a/xbmc/rendering/gles/GLESShader.h b/xbmc/rendering/gles/GLESShader.h
+index ddc31202c531c..2fd3b0716e670 100644
+--- a/xbmc/rendering/gles/GLESShader.h
++++ b/xbmc/rendering/gles/GLESShader.h
+@@ -25,6 +25,7 @@ class CGLESShader : public Shaders::CGLSLShaderProgram
+   GLint GetColLoc()   { return m_hCol;   }
+   GLint GetCord0Loc() { return m_hCord0; }
+   GLint GetCord1Loc() { return m_hCord1; }
++  GLint GetDepthLoc() { return m_hDepth; }
+   GLint GetUniColLoc() { return m_hUniCol; }
+   GLint GetCoord0MatrixLoc() { return m_hCoord0Matrix; }
+   GLint GetFieldLoc() { return m_hField; }
+@@ -59,6 +60,7 @@ class CGLESShader : public Shaders::CGLSLShaderProgram
+   GLint m_hStep = 0;
+   GLint m_hContrast = 0;
+   GLint m_hBrightness = 0;
++  GLint m_hDepth = 0;
+
+   const GLfloat *m_proj;
+   const GLfloat *m_model;
+diff --git a/xbmc/rendering/gles/RenderSystemGLES.cpp b/xbmc/rendering/gles/RenderSystemGLES.cpp
+index a5c02803b0145..52b734f433453 100644
+--- a/xbmc/rendering/gles/RenderSystemGLES.cpp
++++ b/xbmc/rendering/gles/RenderSystemGLES.cpp
+@@ -135,8 +135,7 @@ bool CRenderSystemGLES::ResetRenderSystem(int width, int height)
+   glMatrixTexture.Load();
+
+   glBlendFunc(GL_SRC_ALPHA, GL_ONE);
+-  glEnable(GL_BLEND);          // Turn Blending On
+-  glDisable(GL_DEPTH_TEST);
++  glEnable(GL_BLEND); // Turn Blending On
+
+   return true;
+ }
+@@ -187,6 +186,23 @@ bool CRenderSystemGLES::EndRender()
+   return true;
+ }
+
++void CRenderSystemGLES::InvalidateColorBuffer()
++{
++  if (!m_bRenderCreated)
++    return;
++
++  // some platforms prefer a clear, instead of rendering over
++  if (!CServiceBroker::GetSettingsComponent()->GetAdvancedSettings()->m_guiGeometryClear)
++    ClearBuffers(0);
++
++  if (!CServiceBroker::GetSettingsComponent()->GetAdvancedSettings()->m_guiFrontToBackRendering)
++    return;
++
++  glClearDepthf(0);
++  glDepthMask(true);
++  glClear(GL_DEPTH_BUFFER_BIT);
++}
++
+ bool CRenderSystemGLES::ClearBuffers(UTILS::COLOR::Color color)
+ {
+   if (!m_bRenderCreated)
+@@ -200,6 +216,14 @@ bool CRenderSystemGLES::ClearBuffers(UTILS::COLOR::Color color)
+   glClearColor(r, g, b, a);
+
+   GLbitfield flags = GL_COLOR_BUFFER_BIT;
++
++  if (CServiceBroker::GetSettingsComponent()->GetAdvancedSettings()->m_guiFrontToBackRendering)
++  {
++    glClearDepthf(0);
++    glDepthMask(GL_TRUE);
++    flags |= GL_DEPTH_BUFFER_BIT;
++  }
++
+   glClear(flags);
+
+   return true;
+@@ -383,6 +407,27 @@ void CRenderSystemGLES::ResetScissors()
+   SetScissors(CRect(0, 0, (float)m_width, (float)m_height));
+ }
+
++void CRenderSystemGLES::SetDepthCulling(DEPTH_CULLING culling)
++{
++  if (culling == DEPTH_CULLING_OFF)
++  {
++    glDisable(GL_DEPTH_TEST);
++    glDepthMask(GL_FALSE);
++  }
++  else if (culling == DEPTH_CULLING_BACK_TO_FRONT)
++  {
++    glEnable(GL_DEPTH_TEST);
++    glDepthMask(GL_FALSE);
++    glDepthFunc(GL_GEQUAL);
++  }
++  else if (culling == DEPTH_CULLING_FRONT_TO_BACK)
++  {
++    glEnable(GL_DEPTH_TEST);
++    glDepthMask(GL_TRUE);
++    glDepthFunc(GL_GREATER);
++  }
++}
++
+ void CRenderSystemGLES::InitialiseShaders()
+ {
+   std::string defines;
+@@ -629,6 +674,14 @@ GLint CRenderSystemGLES::GUIShaderGetCoord1()
+   return -1;
+ }
+
++GLint CRenderSystemGLES::GUIShaderGetDepth()
++{
++  if (m_pShader[m_method])
++    return m_pShader[m_method]->GetDepthLoc();
++
++  return -1;
++}
++
+ GLint CRenderSystemGLES::GUIShaderGetUniCol()
+ {
+   if (m_pShader[m_method])
+diff --git a/xbmc/rendering/gles/RenderSystemGLES.h b/xbmc/rendering/gles/RenderSystemGLES.h
+index 7986f2c0a42cb..a6be00933ea1b 100644
+--- a/xbmc/rendering/gles/RenderSystemGLES.h
++++ b/xbmc/rendering/gles/RenderSystemGLES.h
+@@ -85,6 +85,7 @@ class CRenderSystemGLES : public CRenderSystemBase
+   bool BeginRender() override;
+   bool EndRender() override;
+   void PresentRender(bool rendered, bool videoLayer) override;
++  void InvalidateColorBuffer() override;
+   bool ClearBuffers(UTILS::COLOR::Color color) override;
+   bool IsExtSupported(const char* extension) const override;
+
+@@ -99,6 +100,8 @@ class CRenderSystemGLES : public CRenderSystemBase
+   void SetScissors(const CRect& rect) override;
+   void ResetScissors() override;
+
++  void SetDepthCulling(DEPTH_CULLING culling) override;
++
+   void CaptureStateBlock() override;
+   void ApplyStateBlock() override;
+
+@@ -129,6 +132,7 @@ class CRenderSystemGLES : public CRenderSystemBase
+   GLint GUIShaderGetMatrix();
+   GLint GUIShaderGetClip();
+   GLint GUIShaderGetCoordStep();
++  GLint GUIShaderGetDepth();
+
+ protected:
+   virtual void SetVSyncImpl(bool enable) = 0;
+diff --git a/xbmc/settings/AdvancedSettings.cpp b/xbmc/settings/AdvancedSettings.cpp
+index a9f0f41cc554a..7b78c322997bc 100644
+--- a/xbmc/settings/AdvancedSettings.cpp
++++ b/xbmc/settings/AdvancedSettings.cpp
+@@ -1224,6 +1224,8 @@ void CAdvancedSettings::ParseSettingsFile(const std::string &file)
+     XMLUtils::GetBoolean(pElement, "visualizedirtyregions", m_guiVisualizeDirtyRegions);
+     XMLUtils::GetInt(pElement, "algorithmdirtyregions",     m_guiAlgorithmDirtyRegions);
+     XMLUtils::GetBoolean(pElement, "smartredraw", m_guiSmartRedraw);
++    XMLUtils::GetBoolean(pElement, "fronttobackrendering", m_guiFrontToBackRendering);
++    XMLUtils::GetBoolean(pElement, "geometryclear", m_guiGeometryClear);
+   }
+
+   std::string seekSteps;
+diff --git a/xbmc/settings/AdvancedSettings.h b/xbmc/settings/AdvancedSettings.h
+index 8db9a89a568b3..da6ed96cd07b5 100644
+--- a/xbmc/settings/AdvancedSettings.h
++++ b/xbmc/settings/AdvancedSettings.h
+@@ -334,6 +334,8 @@ class CAdvancedSettings : public ISettingCallback, public ISettingsHandler
+     bool m_guiVisualizeDirtyRegions;
+     int  m_guiAlgorithmDirtyRegions;
+     bool m_guiSmartRedraw;
++    bool m_guiFrontToBackRendering{false};
++    bool m_guiGeometryClear{false};
+     unsigned int m_addonPackageFolderSize;
+
+     bool m_jsonOutputCompact;
+diff --git a/xbmc/utils/TransformMatrix.h b/xbmc/utils/TransformMatrix.h
+index a9bf8fdc74331..0287ad55c534c 100644
+--- a/xbmc/utils/TransformMatrix.h
++++ b/xbmc/utils/TransformMatrix.h
+@@ -36,6 +36,7 @@ class TransformMatrix
+     m[2][0] = m[2][1] = m[2][3] = 0.0f; m[2][2] = 1.0f;
+     alpha = red = green = blue = 1.0f;
+     identity = true;
++    depth = 0;
+   };
+   static TransformMatrix CreateTranslation(float transX, float transY, float transZ = 0)
+   {
+@@ -50,6 +51,7 @@ class TransformMatrix
+     m[2][0] = m[2][1] = 0.0f; m[2][2] = 1.0f; m[2][3] = transZ;
+     alpha = red = green = blue = 1.0f;
+     identity = (transX == 0 && transY == 0 && transZ == 0);
++    depth = 0;
+   }
+   static TransformMatrix CreateScaler(float scaleX, float scaleY, float scaleZ = 1.0f)
+   {
+@@ -69,6 +71,7 @@ class TransformMatrix
+     m[2][0] = 0.0f;    m[2][1] = 0.0f;    m[2][2] = scaleZ;  m[2][3] = centerZ*(1-scaleZ);
+     alpha = red = green = blue = 1.0f;
+     identity = (scaleX == 1 && scaleY == 1);
++    depth = 0;
+   };
+   void SetXRotation(float angle, float y, float z, float ar = 1.0f)
+   { // angle about the X axis, centered at y,z where our coordinate system has aspect ratio ar.
+@@ -79,6 +82,7 @@ class TransformMatrix
+     m[2][0] = 0.0f;  m[2][1] = s;     m[2][2] = c;      m[2][3] = (-y*s-c*z) + z;
+     alpha = red = green = blue = 1.0f;
+     identity = (angle == 0);
++    depth = 0;
+   }
+   void SetYRotation(float angle, float x, float z, float ar = 1.0f)
+   { // angle about the Y axis, centered at x,z where our coordinate system has aspect ratio ar.
+@@ -89,6 +93,7 @@ class TransformMatrix
+     m[2][0] = ar*s;  m[2][1] = 0.0f;  m[2][2] = c;      m[2][3] = -ar*x*s - c*z + z;
+     alpha = red = green = blue = 1.0f;
+     identity = (angle == 0);
++    depth = 0;
+   }
+   static TransformMatrix CreateZRotation(float angle, float x, float y, float ar = 1.0f)
+   { // angle about the Z axis, centered at x,y where our coordinate system has aspect ratio ar.
+@@ -106,6 +111,7 @@ class TransformMatrix
+     m[2][0] = 0.0f;  m[2][1] = 0.0f;   m[2][2] = 1.0f;  m[2][3] = 0.0f;
+     alpha = red = green = blue = 1.0f;
+     identity = (angle == 0);
++    depth = 0;
+   }
+   static TransformMatrix CreateFader(float a)
+   {
+@@ -127,6 +133,7 @@ class TransformMatrix
+     alpha = a;
+     red = green = blue = 1.0f;
+     identity = (a == 1.0f);
++    depth = 0;
+   }
+
+   void SetFader(float a, float r, float g, float b)
+@@ -139,6 +146,7 @@ class TransformMatrix
+     green = g;
+     blue = b;
+     identity = ((a == 1.0f) && (r == 1.0f) && (g == 1.0f) && (b == 1.0f));
++    depth = 0;
+   }
+
+   // multiplication operators
+@@ -171,6 +179,7 @@ class TransformMatrix
+     green *= right.green;
+     blue *= right.blue;
+     identity = false;
++    depth = std::max(depth, right.depth);
+     return *this;
+   }
+
+@@ -198,6 +207,7 @@ class TransformMatrix
+     result.green = green * right.green;
+     result.blue = blue * right.blue;
+     result.identity = false;
++    result.depth = std::max(depth, right.depth);
+     return result;
+   }
+
+@@ -278,12 +288,14 @@ class TransformMatrix
+   float green;
+   float blue;
+   bool identity;
++  uint32_t depth{0};
+ };
+
+ inline bool operator==(const TransformMatrix &a, const TransformMatrix &b)
+ {
+   bool comparison =
+       a.alpha == b.alpha && a.red == b.red && a.green == b.green && a.blue == b.blue &&
++      a.depth == b.depth &&
+       ((a.identity && b.identity) ||
+        (!a.identity && !b.identity &&
+         std::equal(&a.m[0][0], &a.m[0][0] + sizeof(a.m) / sizeof(a.m[0][0]), &b.m[0][0])));
+diff --git a/xbmc/video/dialogs/GUIDialogTeletext.cpp b/xbmc/video/dialogs/GUIDialogTeletext.cpp
+index 13c706b12f93c..26280c7126d34 100644
+--- a/xbmc/video/dialogs/GUIDialogTeletext.cpp
++++ b/xbmc/video/dialogs/GUIDialogTeletext.cpp
+@@ -85,6 +85,9 @@ void CGUIDialogTeletext::Process(unsigned int currentTime, CDirtyRegionList &dir
+
+ void CGUIDialogTeletext::Render()
+ {
++  if (CServiceBroker::GetWinSystem()->GetGfxContext().GetRenderOrder() ==
++      RENDER_ORDER_FRONT_TO_BACK)
++    return;
+   // Do not render if we have no texture
+   if (!m_pTxtTexture)
+   {
+@@ -124,7 +127,7 @@ void CGUIDialogTeletext::Render()
+
+   UTILS::COLOR::Color color =
+       (static_cast<UTILS::COLOR::Color>(teletextFadeAmount * 2.55f) & 0xff) << 24 | 0xFFFFFF;
+-  CGUITexture::DrawQuad(m_vertCoords, color, m_pTxtTexture.get());
++  CGUITexture::DrawQuad(m_vertCoords, color, m_pTxtTexture.get(), nullptr, -1.0f);
+
+   CGUIDialog::Render();
+ }
+diff --git a/xbmc/video/windows/GUIWindowFullScreen.cpp b/xbmc/video/windows/GUIWindowFullScreen.cpp
+index 1fccba980a1d7..eee981056c195 100644
+--- a/xbmc/video/windows/GUIWindowFullScreen.cpp
++++ b/xbmc/video/windows/GUIWindowFullScreen.cpp
+@@ -22,6 +22,7 @@
+ #include "input/actions/Action.h"
+ #include "input/actions/ActionIDs.h"
+ #include "input/mouse/MouseEvent.h"
++#include "settings/AdvancedSettings.h"
+ #include "settings/DisplaySettings.h"
+ #include "settings/Settings.h"
+ #include "settings/SettingsComponent.h"
+@@ -182,6 +183,8 @@ void CGUIWindowFullScreen::ClearBackground()
+   const auto appPlayer = components.GetComponent<CApplicationPlayer>();
+   if (appPlayer->IsRenderingVideoLayer())
+     CServiceBroker::GetWinSystem()->GetGfxContext().Clear(0);
++  else
++    CServiceBroker::GetWinSystem()->GetGfxContext().Clear();
+ }
+
+ void CGUIWindowFullScreen::OnWindowLoaded()
+@@ -377,11 +380,19 @@ void CGUIWindowFullScreen::Process(unsigned int currentTime, CDirtyRegionList &d
+
+ void CGUIWindowFullScreen::Render()
+ {
+-  CServiceBroker::GetWinSystem()->GetGfxContext().SetRenderingResolution(CServiceBroker::GetWinSystem()->GetGfxContext().GetVideoResolution(), false);
+-  auto& components = CServiceBroker::GetAppComponents();
+-  const auto appPlayer = components.GetComponent<CApplicationPlayer>();
+-  appPlayer->Render(true, 255);
+-  CServiceBroker::GetWinSystem()->GetGfxContext().SetRenderingResolution(m_coordsRes, m_needsScaling);
++  if (CServiceBroker::GetWinSystem()->GetGfxContext().GetRenderOrder() !=
++      RENDER_ORDER_FRONT_TO_BACK)
++  {
++    CServiceBroker::GetWinSystem()->GetGfxContext().SetRenderingResolution(
++        CServiceBroker::GetWinSystem()->GetGfxContext().GetVideoResolution(), false);
++    auto& components = CServiceBroker::GetAppComponents();
++    const auto appPlayer = components.GetComponent<CApplicationPlayer>();
++    // FIXME: remove clearing pass from renderer, it should be its own, dedicated function.
++    bool clear = CServiceBroker::GetSettingsComponent()->GetAdvancedSettings()->m_guiGeometryClear;
++    appPlayer->Render(clear, 255);
++    CServiceBroker::GetWinSystem()->GetGfxContext().SetRenderingResolution(m_coordsRes,
++                                                                           m_needsScaling);
++  }
+   CGUIWindow::Render();
+ }
+
+diff --git a/xbmc/windowing/GraphicContext.cpp b/xbmc/windowing/GraphicContext.cpp
+index e3300e925c539..ebaec5b715a6a 100644
+--- a/xbmc/windowing/GraphicContext.cpp
++++ b/xbmc/windowing/GraphicContext.cpp
+@@ -580,6 +580,11 @@ void CGraphicContext::ResetScreenParameters(RESOLUTION res)
+   ResetOverscan(res, info.Overscan);
+ }
+
++void CGraphicContext::Clear()
++{
++  CServiceBroker::GetRenderSystem()->InvalidateColorBuffer();
++}
++
+ void CGraphicContext::Clear(UTILS::COLOR::Color color)
+ {
+   CServiceBroker::GetRenderSystem()->ClearBuffers(color);
+@@ -822,6 +827,22 @@ void CGraphicContext::RestoreStereoFactor()
+   UpdateCameraPosition(m_cameras.top(), m_stereoFactors.top());
+ }
+
++float CGraphicContext::GetNormalizedDepth(uint32_t depth)
++{
++  float normalizedDepth = static_cast<float>(depth);
++  normalizedDepth /= m_layer;
++  normalizedDepth = normalizedDepth * 2 - 1;
++  return normalizedDepth;
++}
++
++float CGraphicContext::GetTransformDepth(int32_t depthOffset)
++{
++  float depth = static_cast<float>(m_finalTransform.matrix.depth + depthOffset);
++  depth /= m_layer;
++  depth = depth * 2 - 1;
++  return depth;
++}
++
+ CRect CGraphicContext::GenerateAABB(const CRect &rect) const
+ {
+ // ------------------------
+@@ -1006,6 +1027,24 @@ void CGraphicContext::GetAllowedResolutions(std::vector<RESOLUTION> &res)
+   }
+ }
+
++void CGraphicContext::SetRenderOrder(RENDER_ORDER renderOrder)
++{
++  m_renderOrder = renderOrder;
++  if (renderOrder == RENDER_ORDER_ALL_BACK_TO_FRONT)
++    CServiceBroker::GetRenderSystem()->SetDepthCulling(DEPTH_CULLING_OFF);
++  else if (renderOrder == RENDER_ORDER_BACK_TO_FRONT)
++    CServiceBroker::GetRenderSystem()->SetDepthCulling(DEPTH_CULLING_BACK_TO_FRONT);
++  else if (renderOrder == RENDER_ORDER_FRONT_TO_BACK)
++    CServiceBroker::GetRenderSystem()->SetDepthCulling(DEPTH_CULLING_FRONT_TO_BACK);
++}
++
++uint32_t CGraphicContext::GetDepth(uint32_t addLayers)
++{
++  uint32_t layer = m_layer;
++  m_layer += addLayers;
++  return layer;
++}
++
+ void CGraphicContext::SetFPS(float fps)
+ {
+   m_fFPSOverride = fps;
+diff --git a/xbmc/windowing/GraphicContext.h b/xbmc/windowing/GraphicContext.h
+index 0c5201f1e7f31..36aff346084f0 100644
+--- a/xbmc/windowing/GraphicContext.h
++++ b/xbmc/windowing/GraphicContext.h
+@@ -57,6 +57,13 @@ enum AdjustRefreshRate
+   ADJUST_REFRESHRATE_ON_START,
+ };
+
++enum RENDER_ORDER
++{
++  RENDER_ORDER_ALL_BACK_TO_FRONT = 0,
++  RENDER_ORDER_BACK_TO_FRONT,
++  RENDER_ORDER_FRONT_TO_BACK,
++};
++
+ class CGraphicContext : public CCriticalSection
+ {
+ public:
+@@ -99,8 +106,33 @@ class CGraphicContext : public CCriticalSection
+   void ResetScreenParameters(RESOLUTION res);
+   void CaptureStateBlock();
+   void ApplyStateBlock();
+-  void Clear(UTILS::COLOR::Color color = 0);
++  /*! \brief Invalidates color buffer, clears the depth buffer (if used).
++   Will result in undefined color buffer values which will have to be
++   repainted. Has to be called at the beginning of a frame.
++   */
++  void Clear();
++  /*! \brief Clears the depth buffer (if used) and the color buffer. Guaranties
++   a defined color buffer value. Has to be called at the beginning of a frame.
++   \param color the specified color.
++   */
++  void Clear(UTILS::COLOR::Color color);
+   void GetAllowedResolutions(std::vector<RESOLUTION> &res);
++  /*! \brief Sets the direction of the current rendering pass.
++   \param renderOrder direction of the pass
++   */
++  void SetRenderOrder(RENDER_ORDER renderOrder);
++  /*! \brief Returns the current render order mode
++   \returns RENDER_ORDER returns the mode
++   */
++  RENDER_ORDER GetRenderOrder() { return m_renderOrder; }
++  /*! \brief Resets the z-depth. Layer 0 and 1 are reserved as presentation (video) layer.
++   */
++  void ResetDepth() { m_layer = 2; }
++  /*! \brief Reserve layers for the caller to use
++   \param addLayers number of layers needed
++   \returns uint32_t returns the absolute layer hight
++   */
++  uint32_t GetDepth(uint32_t addLayers = 2);
+
+   /* \brief Get UI scaling information from a given resolution to the screen resolution.
+    Takes account of overscan and UI zooming.
+@@ -134,6 +166,16 @@ class CGraphicContext : public CCriticalSection
+   void RestoreCameraPosition();
+   void SetStereoFactor(float factor);
+   void RestoreStereoFactor();
++  /*! \brief Gets the depth information of the current transform matrix
++   \param depthOffset adds an offset to the current depth
++   \returns float normalized -1 to 1
++   */
++  float GetTransformDepth(int32_t depthOffset = 0);
++  /*! \brief Gets the (normalized) depth information
++   \param depth to be normalized
++   \returns float normalized -1 to 1
++   */
++  float GetNormalizedDepth(uint32_t depth);
+   /*! \brief Set a region in which to clip all rendering
+    Anything that is rendered after setting a clip region will be clipped so that no part renders
+    outside of the clip region.  Successive calls to SetClipRegion intersect the clip region, which
+@@ -234,4 +276,6 @@ class CGraphicContext : public CCriticalSection
+   RENDER_STEREO_MODE m_nextStereoMode = RENDER_STEREO_MODE_OFF;
+
+   bool m_isTransferPQ{false};
++  RENDER_ORDER m_renderOrder{RENDER_ORDER_ALL_BACK_TO_FRONT};
++  uint32_t m_layer{2};
+ };
+diff --git a/xbmc/windowing/X11/GLContextEGL.cpp b/xbmc/windowing/X11/GLContextEGL.cpp
+index 7999e76b982cb..a7c4c3ea00213 100644
+--- a/xbmc/windowing/X11/GLContextEGL.cpp
++++ b/xbmc/windowing/X11/GLContextEGL.cpp
+@@ -341,7 +341,7 @@ bool CGLContextEGL::SuitableCheck(EGLDisplay eglDisplay, EGLConfig config)
+     return false;
+   if (!eglGetConfigAttrib(eglDisplay, config, EGL_BLUE_SIZE, &value) || value < 8)
+     return false;
+-  if (!eglGetConfigAttrib(eglDisplay, config, EGL_DEPTH_SIZE, &value) || value < 24)
++  if (!eglGetConfigAttrib(eglDisplay, config, EGL_DEPTH_SIZE, &value) || value < 16)
+     return false;
+
+   return true;
+diff --git a/xbmc/windows/GUIWindowDebugInfo.cpp b/xbmc/windows/GUIWindowDebugInfo.cpp
+index 764e6b0b714f7..866d506fe332e 100644
+--- a/xbmc/windows/GUIWindowDebugInfo.cpp
++++ b/xbmc/windows/GUIWindowDebugInfo.cpp
+@@ -179,7 +179,13 @@ void CGUIWindowDebugInfo::Process(unsigned int currentTime, CDirtyRegionList &di
+
+ void CGUIWindowDebugInfo::Render()
+ {
++  RENDER_ORDER renderOrder = CServiceBroker::GetWinSystem()->GetGfxContext().GetRenderOrder();
++  if (renderOrder == RENDER_ORDER_FRONT_TO_BACK)
++    return;
++  else if (renderOrder == RENDER_ORDER_BACK_TO_FRONT)
++    CServiceBroker::GetWinSystem()->GetGfxContext().SetRenderOrder(RENDER_ORDER_ALL_BACK_TO_FRONT);
+   CServiceBroker::GetWinSystem()->GetGfxContext().SetRenderingResolution(CServiceBroker::GetWinSystem()->GetGfxContext().GetResInfo(), false);
+   if (m_layout)
+     m_layout->RenderOutline(m_renderRegion.x1, m_renderRegion.y1, 0xffffffff, 0xff000000, 0, 0);
++  CServiceBroker::GetWinSystem()->GetGfxContext().SetRenderOrder(renderOrder);
+ }
+
+From ad06c5d3c0bcb8c48174fcbc85f88e31f1ec2fe4 Mon Sep 17 00:00:00 2001
+From: sarbes <sarbes@kodi.tv>
+Date: Fri, 26 Apr 2024 21:08:44 +0200
+Subject: [PATCH 2/4] Clear splash in any case
+
+---
+ xbmc/rendering/RenderSystem.cpp | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/xbmc/rendering/RenderSystem.cpp b/xbmc/rendering/RenderSystem.cpp
+index cabbea77b1b1e..3baa8fecaa733 100644
+--- a/xbmc/rendering/RenderSystem.cpp
++++ b/xbmc/rendering/RenderSystem.cpp
+@@ -73,7 +73,7 @@ void CRenderSystemBase::ShowSplash(const std::string& message)
+   }
+
+   CServiceBroker::GetWinSystem()->GetGfxContext().lock();
+-  CServiceBroker::GetWinSystem()->GetGfxContext().Clear();
++  CServiceBroker::GetWinSystem()->GetGfxContext().Clear(0xff000000);
+
+   RESOLUTION_INFO res = CServiceBroker::GetWinSystem()->GetGfxContext().GetResInfo();
+   CServiceBroker::GetWinSystem()->GetGfxContext().SetRenderingResolution(res, true);
+
+From ecdb187fe17ad11c81d748db05301fbfef8e137d Mon Sep 17 00:00:00 2001
+From: sarbes <sarbes@kodi.tv>
+Date: Fri, 26 Apr 2024 21:10:39 +0200
+Subject: [PATCH 3/4] Clear opaque black when not using geometry to cover
+ invalid areas
+
+---
+ xbmc/guilib/GUIWindow.cpp                  | 2 ++
+ xbmc/video/windows/GUIWindowFullScreen.cpp | 2 ++
+ 2 files changed, 4 insertions(+)
+
+diff --git a/xbmc/guilib/GUIWindow.cpp b/xbmc/guilib/GUIWindow.cpp
+index 36306ff90856b..26fae889b7750 100644
+--- a/xbmc/guilib/GUIWindow.cpp
++++ b/xbmc/guilib/GUIWindow.cpp
+@@ -1078,6 +1078,8 @@ void CGUIWindow::ClearBackground()
+   UTILS::COLOR::Color color = m_clearBackground;
+   if (color)
+     CServiceBroker::GetWinSystem()->GetGfxContext().Clear(color);
++  else if (!CServiceBroker::GetSettingsComponent()->GetAdvancedSettings()->m_guiGeometryClear)
++    CServiceBroker::GetWinSystem()->GetGfxContext().Clear(0xff000000);
+   else
+     CServiceBroker::GetWinSystem()->GetGfxContext().Clear();
+ }
+diff --git a/xbmc/video/windows/GUIWindowFullScreen.cpp b/xbmc/video/windows/GUIWindowFullScreen.cpp
+index eee981056c195..28974e405a742 100644
+--- a/xbmc/video/windows/GUIWindowFullScreen.cpp
++++ b/xbmc/video/windows/GUIWindowFullScreen.cpp
+@@ -183,6 +183,8 @@ void CGUIWindowFullScreen::ClearBackground()
+   const auto appPlayer = components.GetComponent<CApplicationPlayer>();
+   if (appPlayer->IsRenderingVideoLayer())
+     CServiceBroker::GetWinSystem()->GetGfxContext().Clear(0);
++  else if (!CServiceBroker::GetSettingsComponent()->GetAdvancedSettings()->m_guiGeometryClear)
++    CServiceBroker::GetWinSystem()->GetGfxContext().Clear(0xff000000);
+   else
+     CServiceBroker::GetWinSystem()->GetGfxContext().Clear();
+ }
+
+From 5987d9f393c28a19a568eeed3de37bab01bef538 Mon Sep 17 00:00:00 2001
+From: sarbes <sarbes@kodi.tv>
+Date: Fri, 26 Apr 2024 21:17:27 +0200
+Subject: [PATCH 4/4] Default to screen clear via geometry
+
+---
+ xbmc/settings/AdvancedSettings.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/xbmc/settings/AdvancedSettings.h b/xbmc/settings/AdvancedSettings.h
+index da6ed96cd07b5..e9adb76b61d9f 100644
+--- a/xbmc/settings/AdvancedSettings.h
++++ b/xbmc/settings/AdvancedSettings.h
+@@ -335,7 +335,7 @@ class CAdvancedSettings : public ISettingCallback, public ISettingsHandler
+     bool m_guiSmartRedraw;
+     int32_t m_guiAnisotropicFiltering{0};
+     bool m_guiFrontToBackRendering{false};
+-    bool m_guiGeometryClear{false};
++    bool m_guiGeometryClear{true};
+     unsigned int m_addonPackageFolderSize;
+
+     bool m_jsonOutputCompact;
diff --git a/projects/Rockchip/devices/RK322X/patches/kodi/kodi-100.21557-enables-use-of-single-dual-channel-textures.patch b/projects/Rockchip/devices/RK322X/patches/kodi/kodi-100.21557-enables-use-of-single-dual-channel-textures.patch
new file mode 100644
index 0000000000..08a5c34503
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/patches/kodi/kodi-100.21557-enables-use-of-single-dual-channel-textures.patch
@@ -0,0 +1,1415 @@
+From cf8ec7e28b6611d92cd2f45d2b638c531b2981c7 Mon Sep 17 00:00:00 2001
+From: sarbes <sarbes@kodi.tv>
+Date: Sun, 12 Mar 2023 15:49:03 +0100
+Subject: [PATCH 1/4] Renaming of the texture format A8 to R8
+
+---
+ xbmc/addons/ImageDecoder.cpp | 2 +-
+ xbmc/guilib/GUIFontTTFDX.cpp | 2 +-
+ xbmc/guilib/GUIFontTTFGL.cpp | 2 +-
+ xbmc/guilib/TextureDX.cpp    | 2 +-
+ xbmc/guilib/TextureFormats.h | 4 +++-
+ 5 files changed, 7 insertions(+), 5 deletions(-)
+
+diff -ruPN xbmc-21.0b2-Omega/xbmc/addons/ImageDecoder.cpp xbmc-new/xbmc/addons/ImageDecoder.cpp
+--- xbmc-21.0b2-Omega/xbmc/addons/ImageDecoder.cpp	2023-12-09 22:24:46.000000000 +0100
++++ xbmc-new/xbmc/addons/ImageDecoder.cpp	2023-12-16 12:23:17.584982235 +0100
+@@ -19,7 +19,7 @@
+
+ constexpr std::array<std::tuple<unsigned int, ADDON_IMG_FMT, size_t>, 4> KodiToAddonFormat = {
+     {{XB_FMT_A8R8G8B8, ADDON_IMG_FMT_A8R8G8B8, sizeof(uint8_t) * 4},
+-     {XB_FMT_A8, ADDON_IMG_FMT_A8, sizeof(uint8_t) * 1},
++     {XB_FMT_R8, ADDON_IMG_FMT_A8, sizeof(uint8_t) * 1},
+      {XB_FMT_RGBA8, ADDON_IMG_FMT_RGBA8, sizeof(uint8_t) * 4},
+      {XB_FMT_RGB8, ADDON_IMG_FMT_RGB8, sizeof(uint8_t) * 3}}};
+
+diff -ruPN xbmc-21.0b2-Omega/xbmc/guilib/GUIFontTTFDX.cpp xbmc-new/xbmc/guilib/GUIFontTTFDX.cpp
+--- xbmc-21.0b2-Omega/xbmc/guilib/GUIFontTTFDX.cpp	2023-12-09 22:24:46.000000000 +0100
++++ xbmc-new/xbmc/guilib/GUIFontTTFDX.cpp	2023-12-16 12:24:00.224981501 +0100
+@@ -239,7 +239,7 @@
+   m_dynamicCache.Flush();
+
+   std::unique_ptr<CDXTexture> pNewTexture =
+-      std::make_unique<CDXTexture>(m_textureWidth, newHeight, XB_FMT_A8);
++      std::make_unique<CDXTexture>(m_textureWidth, newHeight, XB_FMT_R8);
+   std::unique_ptr<CD3DTexture> newSpeedupTexture = std::make_unique<CD3DTexture>();
+   if (!newSpeedupTexture->Create(m_textureWidth, newHeight, 1, D3D11_USAGE_DEFAULT,
+                                  DXGI_FORMAT_R8_UNORM))
+diff -ruPN xbmc-21.0b2-Omega/xbmc/guilib/GUIFontTTFGL.cpp xbmc-new/xbmc/guilib/GUIFontTTFGL.cpp
+--- xbmc-21.0b2-Omega/xbmc/guilib/GUIFontTTFGL.cpp	2023-12-09 22:24:46.000000000 +0100
++++ xbmc-new/xbmc/guilib/GUIFontTTFGL.cpp	2023-12-16 12:24:57.785980511 +0100
+@@ -292,7 +292,7 @@
+   newHeight = CTexture::PadPow2(newHeight);
+
+   std::unique_ptr<CTexture> newTexture =
+-      CTexture::CreateTexture(m_textureWidth, newHeight, XB_FMT_A8);
++      CTexture::CreateTexture(m_textureWidth, newHeight, XB_FMT_R8);
+
+   if (!newTexture || !newTexture->GetPixels())
+   {
+diff -ruPN xbmc-21.0b2-Omega/xbmc/guilib/TextureDX.cpp xbmc-new/xbmc/guilib/TextureDX.cpp
+--- xbmc-21.0b2-Omega/xbmc/guilib/TextureDX.cpp	2023-12-09 22:24:46.000000000 +0100
++++ xbmc-new/xbmc/guilib/TextureDX.cpp	2023-12-16 12:25:27.177980005 +0100
+@@ -55,7 +55,7 @@
+   case XB_FMT_A8R8G8B8:
+     format = DXGI_FORMAT_B8G8R8A8_UNORM; // D3DFMT_A8R8G8B8 -> DXGI_FORMAT_B8G8R8A8_UNORM | DXGI_FORMAT_B8G8R8A8_UNORM_SRGB
+     break;
+-  case XB_FMT_A8:
++  case XB_FMT_R8:
+     format = DXGI_FORMAT_R8_UNORM; // XB_FMT_A8 -> DXGI_FORMAT_A8_UNORM
+     break;
+   }
+diff -ruPN xbmc-21.0b2-Omega/xbmc/guilib/TextureFormats.h xbmc-new/xbmc/guilib/TextureFormats.h
+--- xbmc-21.0b2-Omega/xbmc/guilib/TextureFormats.h	2023-12-09 22:24:46.000000000 +0100
++++ xbmc-new/xbmc/guilib/TextureFormats.h	2023-12-16 12:25:59.113979456 +0100
+@@ -19,7 +19,7 @@
+   XB_FMT_DXT_MASK    = 0xF,
+
+   XB_FMT_A8R8G8B8    = 0x10, // texture.xbt byte order (matches BGRA8)
+-  XB_FMT_A8          = 0x20,
++  XB_FMT_R8          = 0x20,
+   XB_FMT_RGBA8       = 0x40,
+   XB_FMT_RGB8        = 0x80,
+   XB_FMT_MASK        = 0xFFFF,
+
+From e40c15b9a6c1ef157eb4567b654f07463765d5fe Mon Sep 17 00:00:00 2001
+From: sarbes <sarbes@kodi.tv>
+Date: Sun, 12 Mar 2023 18:20:30 +0100
+Subject: [PATCH 2/4] Add GLES shaders for single/dual channel textures
+
+---
+ ...s_shader_multi_blendcolor_alpha_alpha.frag | 44 +++++++++++++++
+ ...s_shader_multi_blendcolor_alpha_color.frag | 43 +++++++++++++++
+ ...s_shader_multi_blendcolor_color_alpha.frag | 43 +++++++++++++++
+ .../GLES/2.0/gles_shader_texture_alpha.frag   | 40 ++++++++++++++
+ xbmc/rendering/gles/RenderSystemGLES.cpp      | 55 +++++++++++++++++++
+ xbmc/rendering/gles/RenderSystemGLES.h        |  8 +++
+ 6 files changed, 233 insertions(+)
+ create mode 100644 system/shaders/GLES/2.0/gles_shader_multi_blendcolor_alpha_alpha.frag
+ create mode 100644 system/shaders/GLES/2.0/gles_shader_multi_blendcolor_alpha_color.frag
+ create mode 100644 system/shaders/GLES/2.0/gles_shader_multi_blendcolor_color_alpha.frag
+ create mode 100644 system/shaders/GLES/2.0/gles_shader_texture_alpha.frag
+
+diff --git a/system/shaders/GLES/2.0/gles_shader_multi_blendcolor_alpha_alpha.frag b/system/shaders/GLES/2.0/gles_shader_multi_blendcolor_alpha_alpha.frag
+new file mode 100644
+index 0000000000000..3bcb3c12cb075
+--- /dev/null
++++ b/system/shaders/GLES/2.0/gles_shader_multi_blendcolor_alpha_alpha.frag
+@@ -0,0 +1,44 @@
++/*
++ *      Copyright (C) 2010-2023 Team XBMC
++ *      http://xbmc.org
++ *
++ *  This Program is free software; you can redistribute it and/or modify
++ *  it under the terms of the GNU General Public License as published by
++ *  the Free Software Foundation; either version 2, or (at your option)
++ *  any later version.
++ *
++ *  This Program is distributed in the hope that it will be useful,
++ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ *  GNU General Public License for more details.
++ *
++ *  You should have received a copy of the GNU General Public License
++ *  along with XBMC; see the file COPYING.  If not, see
++ *  <http://www.gnu.org/licenses/>.
++ *
++ */
++
++#version 100
++
++precision mediump float;
++uniform sampler2D m_samp0;
++uniform sampler2D m_samp1;
++varying vec4 m_cord0;
++varying vec4 m_cord1;
++uniform lowp vec4 m_unicol;
++
++void main ()
++{
++  vec4 rgb;
++
++  rgb = m_unicol;
++  rgb.a *= texture2D(m_samp0, m_cord0.xy).a;
++  rgb.a *= texture2D(m_samp1, m_cord1.xy).a;
++
++#if defined(KODI_LIMITED_RANGE)
++  rgb.rgb *= (235.0 - 16.0) / 255.0;
++  rgb.rgb += 16.0 / 255.0;
++#endif
++
++  gl_FragColor = rgb;
++}
+diff --git a/system/shaders/GLES/2.0/gles_shader_multi_blendcolor_alpha_color.frag b/system/shaders/GLES/2.0/gles_shader_multi_blendcolor_alpha_color.frag
+new file mode 100644
+index 0000000000000..7a60727df2f4b
+--- /dev/null
++++ b/system/shaders/GLES/2.0/gles_shader_multi_blendcolor_alpha_color.frag
+@@ -0,0 +1,43 @@
++/*
++ *      Copyright (C) 2010-2023 Team XBMC
++ *      http://xbmc.org
++ *
++ *  This Program is free software; you can redistribute it and/or modify
++ *  it under the terms of the GNU General Public License as published by
++ *  the Free Software Foundation; either version 2, or (at your option)
++ *  any later version.
++ *
++ *  This Program is distributed in the hope that it will be useful,
++ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ *  GNU General Public License for more details.
++ *
++ *  You should have received a copy of the GNU General Public License
++ *  along with XBMC; see the file COPYING.  If not, see
++ *  <http://www.gnu.org/licenses/>.
++ *
++ */
++
++#version 100
++
++precision mediump float;
++uniform sampler2D m_samp0;
++uniform sampler2D m_samp1;
++varying vec4 m_cord0;
++varying vec4 m_cord1;
++uniform lowp vec4 m_unicol;
++
++void main ()
++{
++  vec4 rgb;
++
++  rgb = m_unicol * texture2D(m_samp1, m_cord1.xy);
++  rgb.a *= texture2D(m_samp0, m_cord0.xy).a;
++
++#if defined(KODI_LIMITED_RANGE)
++  rgb.rgb *= (235.0 - 16.0) / 255.0;
++  rgb.rgb += 16.0 / 255.0;
++#endif
++
++  gl_FragColor = rgb;
++}
+diff --git a/system/shaders/GLES/2.0/gles_shader_multi_blendcolor_color_alpha.frag b/system/shaders/GLES/2.0/gles_shader_multi_blendcolor_color_alpha.frag
+new file mode 100644
+index 0000000000000..11645c46b307d
+--- /dev/null
++++ b/system/shaders/GLES/2.0/gles_shader_multi_blendcolor_color_alpha.frag
+@@ -0,0 +1,43 @@
++/*
++ *      Copyright (C) 2010-2023 Team XBMC
++ *      http://xbmc.org
++ *
++ *  This Program is free software; you can redistribute it and/or modify
++ *  it under the terms of the GNU General Public License as published by
++ *  the Free Software Foundation; either version 2, or (at your option)
++ *  any later version.
++ *
++ *  This Program is distributed in the hope that it will be useful,
++ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ *  GNU General Public License for more details.
++ *
++ *  You should have received a copy of the GNU General Public License
++ *  along with XBMC; see the file COPYING.  If not, see
++ *  <http://www.gnu.org/licenses/>.
++ *
++ */
++
++#version 100
++
++precision mediump float;
++uniform sampler2D m_samp0;
++uniform sampler2D m_samp1;
++varying vec4 m_cord0;
++varying vec4 m_cord1;
++uniform lowp vec4 m_unicol;
++
++void main ()
++{
++  vec4 rgb;
++
++  rgb = m_unicol * texture2D(m_samp0, m_cord0.xy);
++  rgb.a *= texture2D(m_samp1, m_cord1.xy).a;
++
++#if defined(KODI_LIMITED_RANGE)
++  rgb.rgb *= (235.0 - 16.0) / 255.0;
++  rgb.rgb += 16.0 / 255.0;
++#endif
++
++  gl_FragColor = rgb;
++}
+diff --git a/system/shaders/GLES/2.0/gles_shader_texture_alpha.frag b/system/shaders/GLES/2.0/gles_shader_texture_alpha.frag
+new file mode 100644
+index 0000000000000..900b46ec739b4
+--- /dev/null
++++ b/system/shaders/GLES/2.0/gles_shader_texture_alpha.frag
+@@ -0,0 +1,40 @@
++/*
++ *      Copyright (C) 2010-2023 Team XBMC
++ *      http://xbmc.org
++ *
++ *  This Program is free software; you can redistribute it and/or modify
++ *  it under the terms of the GNU General Public License as published by
++ *  the Free Software Foundation; either version 2, or (at your option)
++ *  any later version.
++ *
++ *  This Program is distributed in the hope that it will be useful,
++ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ *  GNU General Public License for more details.
++ *
++ *  You should have received a copy of the GNU General Public License
++ *  along with XBMC; see the file COPYING.  If not, see
++ *  <http://www.gnu.org/licenses/>.
++ *
++ */
++
++#version 100
++
++precision mediump float;
++uniform sampler2D m_samp0;
++uniform lowp vec4 m_unicol;
++varying vec4 m_cord0;
++
++void main ()
++{
++  vec4 rgb;
++  rgb = m_unicol;
++  rgb.a *= texture2D(m_samp0, m_cord0.xy).a;
++
++#if defined(KODI_LIMITED_RANGE)
++  rgb.rgb *= (235.0 - 16.0) / 255.0;
++  rgb.rgb += 16.0 / 255.0;
++#endif
++
++  gl_FragColor = rgb;
++}
+diff --git a/xbmc/rendering/gles/RenderSystemGLES.cpp b/xbmc/rendering/gles/RenderSystemGLES.cpp
+index d8557ff8a0f80..5bc66035ead61 100644
+--- a/xbmc/rendering/gles/RenderSystemGLES.cpp
++++ b/xbmc/rendering/gles/RenderSystemGLES.cpp
+@@ -407,6 +407,15 @@ void CRenderSystemGLES::InitialiseShaders()
+     CLog::Log(LOGERROR, "GUI Shader gles_shader_texture.frag - compile and link failed");
+   }
+
++  m_pShader[ShaderMethodGLES::SM_TEXTURE_ALPHA] =
++      std::make_unique<CGLESShader>("gles_shader_texture_alpha.frag", defines);
++  if (!m_pShader[ShaderMethodGLES::SM_TEXTURE_ALPHA]->CompileAndLink())
++  {
++    m_pShader[ShaderMethodGLES::SM_TEXTURE_ALPHA]->Free();
++    m_pShader[ShaderMethodGLES::SM_TEXTURE_ALPHA].reset();
++    CLog::Log(LOGERROR, "GUI Shader gles_shader_texture_alpha.frag - compile and link failed");
++  }
++
+   m_pShader[ShaderMethodGLES::SM_MULTI] =
+       std::make_unique<CGLESShader>("gles_shader_multi.frag", defines);
+   if (!m_pShader[ShaderMethodGLES::SM_MULTI]->CompileAndLink())
+@@ -443,6 +452,36 @@ void CRenderSystemGLES::InitialiseShaders()
+     CLog::Log(LOGERROR, "GUI Shader gles_shader_multi_blendcolor.frag - compile and link failed");
+   }
+
++  m_pShader[ShaderMethodGLES::SM_MULTI_BLENDCOLOR_COLOR_ALPHA] =
++      std::make_unique<CGLESShader>("gles_shader_multi_blendcolor_color_alpha.frag", defines);
++  if (!m_pShader[ShaderMethodGLES::SM_MULTI_BLENDCOLOR_COLOR_ALPHA]->CompileAndLink())
++  {
++    m_pShader[ShaderMethodGLES::SM_MULTI_BLENDCOLOR_COLOR_ALPHA]->Free();
++    m_pShader[ShaderMethodGLES::SM_MULTI_BLENDCOLOR_COLOR_ALPHA].reset();
++    CLog::Log(LOGERROR,
++              "GUI Shader gles_shader_multi_blendcolor_color_alpha.frag - compile and link failed");
++  }
++
++  m_pShader[ShaderMethodGLES::SM_MULTI_BLENDCOLOR_ALPHA_COLOR] =
++      std::make_unique<CGLESShader>("gles_shader_multi_blendcolor_alpha_color.frag", defines);
++  if (!m_pShader[ShaderMethodGLES::SM_MULTI_BLENDCOLOR_ALPHA_COLOR]->CompileAndLink())
++  {
++    m_pShader[ShaderMethodGLES::SM_MULTI_BLENDCOLOR_ALPHA_COLOR]->Free();
++    m_pShader[ShaderMethodGLES::SM_MULTI_BLENDCOLOR_ALPHA_COLOR].reset();
++    CLog::Log(LOGERROR,
++              "GUI Shader gles_shader_multi_blendcolor_alpha_color.frag - compile and link failed");
++  }
++
++  m_pShader[ShaderMethodGLES::SM_MULTI_BLENDCOLOR_ALPHA_ALPHA] =
++      std::make_unique<CGLESShader>("gles_shader_multi_blendcolor_alpha_alpha.frag", defines);
++  if (!m_pShader[ShaderMethodGLES::SM_MULTI_BLENDCOLOR_ALPHA_ALPHA]->CompileAndLink())
++  {
++    m_pShader[ShaderMethodGLES::SM_MULTI_BLENDCOLOR_ALPHA_ALPHA]->Free();
++    m_pShader[ShaderMethodGLES::SM_MULTI_BLENDCOLOR_ALPHA_ALPHA].reset();
++    CLog::Log(LOGERROR,
++              "GUI Shader gles_shader_multi_blendcolor_alpha_alpha.frag - compile and link failed");
++  }
++
+   m_pShader[ShaderMethodGLES::SM_TEXTURE_RGBA] =
+       std::make_unique<CGLESShader>("gles_shader_rgba.frag", defines);
+   if (!m_pShader[ShaderMethodGLES::SM_TEXTURE_RGBA]->CompileAndLink())
+@@ -512,6 +551,10 @@ void CRenderSystemGLES::ReleaseShaders()
+     m_pShader[ShaderMethodGLES::SM_TEXTURE]->Free();
+   m_pShader[ShaderMethodGLES::SM_TEXTURE].reset();
+
++  if (m_pShader[ShaderMethodGLES::SM_TEXTURE_ALPHA])
++    m_pShader[ShaderMethodGLES::SM_TEXTURE_ALPHA]->Free();
++  m_pShader[ShaderMethodGLES::SM_TEXTURE_ALPHA].reset();
++
+   if (m_pShader[ShaderMethodGLES::SM_MULTI])
+     m_pShader[ShaderMethodGLES::SM_MULTI]->Free();
+   m_pShader[ShaderMethodGLES::SM_MULTI].reset();
+@@ -528,6 +571,18 @@ void CRenderSystemGLES::ReleaseShaders()
+     m_pShader[ShaderMethodGLES::SM_MULTI_BLENDCOLOR]->Free();
+   m_pShader[ShaderMethodGLES::SM_MULTI_BLENDCOLOR].reset();
+
++  if (m_pShader[ShaderMethodGLES::SM_MULTI_BLENDCOLOR_COLOR_ALPHA])
++    m_pShader[ShaderMethodGLES::SM_MULTI_BLENDCOLOR_COLOR_ALPHA]->Free();
++  m_pShader[ShaderMethodGLES::SM_MULTI_BLENDCOLOR_COLOR_ALPHA].reset();
++
++  if (m_pShader[ShaderMethodGLES::SM_MULTI_BLENDCOLOR_ALPHA_COLOR])
++    m_pShader[ShaderMethodGLES::SM_MULTI_BLENDCOLOR_ALPHA_COLOR]->Free();
++  m_pShader[ShaderMethodGLES::SM_MULTI_BLENDCOLOR_ALPHA_COLOR].reset();
++
++  if (m_pShader[ShaderMethodGLES::SM_MULTI_BLENDCOLOR_ALPHA_ALPHA])
++    m_pShader[ShaderMethodGLES::SM_MULTI_BLENDCOLOR_ALPHA_ALPHA]->Free();
++  m_pShader[ShaderMethodGLES::SM_MULTI_BLENDCOLOR_ALPHA_ALPHA].reset();
++
+   if (m_pShader[ShaderMethodGLES::SM_TEXTURE_RGBA])
+     m_pShader[ShaderMethodGLES::SM_TEXTURE_RGBA]->Free();
+   m_pShader[ShaderMethodGLES::SM_TEXTURE_RGBA].reset();
+diff --git a/xbmc/rendering/gles/RenderSystemGLES.h b/xbmc/rendering/gles/RenderSystemGLES.h
+index e0cd72b9c1937..31b4abbaa9d04 100644
+--- a/xbmc/rendering/gles/RenderSystemGLES.h
++++ b/xbmc/rendering/gles/RenderSystemGLES.h
+@@ -23,10 +23,14 @@ enum class ShaderMethodGLES
+ {
+   SM_DEFAULT,
+   SM_TEXTURE,
++  SM_TEXTURE_ALPHA,
+   SM_MULTI,
+   SM_FONTS,
+   SM_TEXTURE_NOBLEND,
+   SM_MULTI_BLENDCOLOR,
++  SM_MULTI_BLENDCOLOR_COLOR_ALPHA,
++  SM_MULTI_BLENDCOLOR_ALPHA_COLOR,
++  SM_MULTI_BLENDCOLOR_ALPHA_ALPHA,
+   SM_TEXTURE_RGBA,
+   SM_TEXTURE_RGBA_OES,
+   SM_TEXTURE_RGBA_BLENDCOLOR,
+@@ -53,10 +57,14 @@ struct fmt::formatter<ShaderMethodGLES> : fmt::formatter<std::string_view>
+   static constexpr auto ShaderMethodGLESMap = make_map<ShaderMethodGLES, std::string_view>({
+       {ShaderMethodGLES::SM_DEFAULT, "default"},
+       {ShaderMethodGLES::SM_TEXTURE, "texture"},
++      {ShaderMethodGLES::SM_TEXTURE_ALPHA, "texture, alpha only"},
+       {ShaderMethodGLES::SM_MULTI, "multi"},
+       {ShaderMethodGLES::SM_FONTS, "fonts"},
+       {ShaderMethodGLES::SM_TEXTURE_NOBLEND, "texture no blending"},
+       {ShaderMethodGLES::SM_MULTI_BLENDCOLOR, "multi blend colour"},
++      {ShaderMethodGLES::SM_MULTI_BLENDCOLOR_COLOR_ALPHA, "multi blend colour and alpha texture"},
++      {ShaderMethodGLES::SM_MULTI_BLENDCOLOR_ALPHA_COLOR, "multi blend alpha and colour texture"},
++      {ShaderMethodGLES::SM_MULTI_BLENDCOLOR_ALPHA_ALPHA, "multi blend alpha textures"},
+       {ShaderMethodGLES::SM_TEXTURE_RGBA, "texure rgba"},
+       {ShaderMethodGLES::SM_TEXTURE_RGBA_OES, "texture rgba OES"},
+       {ShaderMethodGLES::SM_TEXTURE_RGBA_BLENDCOLOR, "texture rgba blend colour"},
+
+From 785e7d847c3a4ff6bf16841c729b0d02a711c441 Mon Sep 17 00:00:00 2001
+From: sarbes <sarbes@kodi.tv>
+Date: Mon, 13 Mar 2023 01:39:32 +0100
+Subject: [PATCH 3/4] Implement single/dual channel textures for GL/GLES
+
+---
+ xbmc/guilib/FFmpegImage.cpp    |  66 ++++++++++++++++---
+ xbmc/guilib/FFmpegImage.h      |   8 ++-
+ xbmc/guilib/GUITextureGLES.cpp |  22 ++++++-
+ xbmc/guilib/Texture.cpp        | 115 ++++++++++++++++++++++++++++-----
+ xbmc/guilib/Texture.h          |  19 ++++--
+ xbmc/guilib/TextureDX.cpp      |  18 ++++++
+ xbmc/guilib/TextureDX.h        |   1 +
+ xbmc/guilib/TextureFormats.h   |   3 +
+ xbmc/guilib/TextureGL.cpp      | 114 ++++++++++++++++++++++++++++++++
+ xbmc/guilib/TextureGL.h        |   1 +
+ xbmc/guilib/TextureManager.cpp |  18 +++++-
+ xbmc/guilib/iimage.h           |  15 ++++-
+ 12 files changed, 362 insertions(+), 38 deletions(-)
+
+diff --git a/xbmc/guilib/FFmpegImage.cpp b/xbmc/guilib/FFmpegImage.cpp
+index e71980998b2e5..a0d3fd14c9cfe 100644
+--- a/xbmc/guilib/FFmpegImage.cpp
++++ b/xbmc/guilib/FFmpegImage.cpp
+@@ -300,6 +300,13 @@ AVFrame* CFFmpegImage::ExtractFrame()
+   m_originalWidth = m_width;
+   m_originalHeight = m_height;
+
++  if (frame->format == AV_PIX_FMT_GRAY8)
++    m_format =XB_FMT_L8;
++  else if (frame->format == AV_PIX_FMT_GRAY8A)
++    m_format = XB_FMT_L8A8;
++  else
++    m_format = XB_FMT_A8R8G8B8;
++
+   const AVPixFmtDescriptor* pixDescriptor = av_pix_fmt_desc_get(static_cast<AVPixelFormat>(frame->format));
+   if (pixDescriptor && ((pixDescriptor->flags & (AV_PIX_FMT_FLAG_ALPHA | AV_PIX_FMT_FLAG_PAL)) != 0))
+     m_hasAlpha = true;
+@@ -349,12 +356,43 @@ void CFFmpegImage::FreeIOCtx(AVIOContext** ioctx)
+   av_freep(ioctx);
+ }
+
+-bool CFFmpegImage::Decode(unsigned char * const pixels, unsigned int width, unsigned int height,
+-                          unsigned int pitch, unsigned int format)
++bool CFFmpegImage::IsFormatSupported(XB_FMT format)
++{
++  switch (format)
++  {
++    case XB_FMT_A8:
++    case XB_FMT_L8:
++    case XB_FMT_L8A8:
++    case XB_FMT_A8R8G8B8:
++      return true;
++    default:
++      return false;
++  }
++}
++
++bool CFFmpegImage::Decode(unsigned char* const pixels,
++                          unsigned int width,
++                          unsigned int height,
++                          unsigned int pitch,
++                          unsigned int textureFormat)
+ {
+-  if (m_width == 0 || m_height == 0 || format != XB_FMT_A8R8G8B8)
++  if (m_width == 0 || m_height == 0)
+     return false;
+
++  AVPixelFormat outputPixelFormat;
++  if (textureFormat == XB_FMT_A8 || textureFormat == XB_FMT_L8)
++    outputPixelFormat = AV_PIX_FMT_GRAY8;
++  else if (textureFormat == XB_FMT_L8A8)
++    outputPixelFormat = AV_PIX_FMT_GRAY8A;
++  else if (textureFormat == XB_FMT_RGB8 || textureFormat == XB_FMT_A8R8G8B8 ||
++           textureFormat == XB_FMT_RGBA8)
++    outputPixelFormat = AV_PIX_FMT_RGB32;
++  else
++  {
++    CLog::Log(LOGERROR, "{} - No valid texture format ({}) passed", __FUNCTION__, textureFormat);
++    return false;
++  }
++
+   if (pixels == nullptr)
+   {
+     CLog::Log(LOGERROR, "{} - No valid buffer pointer (nullptr) passed", __FUNCTION__);
+@@ -367,7 +405,10 @@ bool CFFmpegImage::Decode(unsigned char * const pixels, unsigned int width, unsi
+     return false;
+   }
+
+-  return DecodeFrame(m_pFrame, width, height, pitch, pixels);
++  bool success = DecodeFrame(m_pFrame, width, height, pitch, pixels, outputPixelFormat);
++  if (textureFormat == XB_FMT_A8)
++    m_hasAlpha = true;
++  return success;
+ }
+
+ int CFFmpegImage::EncodeFFmpegFrame(AVCodecContext *avctx, AVPacket *pkt, int *got_packet, AVFrame *frame)
+@@ -414,7 +455,12 @@ int CFFmpegImage::DecodeFFmpegFrame(AVCodecContext *avctx, AVFrame *frame, int *
+   return 0;
+ }
+
+-bool CFFmpegImage::DecodeFrame(AVFrame* frame, unsigned int width, unsigned int height, unsigned int pitch, unsigned char * const pixels)
++bool CFFmpegImage::DecodeFrame(AVFrame* frame,
++                               unsigned int width,
++                               unsigned int height,
++                               unsigned int pitch,
++                               unsigned char* const pixels,
++                               AVPixelFormat outputPixelFormat)
+ {
+   if (pixels == nullptr)
+   {
+@@ -430,7 +476,8 @@ bool CFFmpegImage::DecodeFrame(AVFrame* frame, unsigned int width, unsigned int
+   }
+
+   // we align on 16 as the input provided by the Texture also aligns the buffer size to 16
+-  int size = av_image_fill_arrays(pictureRGB->data, pictureRGB->linesize, NULL, AV_PIX_FMT_RGB32, width, height, 16);
++  int size = av_image_fill_arrays(pictureRGB->data, pictureRGB->linesize, NULL, outputPixelFormat,
++                                  width, height, 16);
+   if (size < 0)
+   {
+     CLog::LogF(LOGERROR, "Could not allocate AVFrame member with {} x {} pixels", width, height);
+@@ -452,7 +499,7 @@ bool CFFmpegImage::DecodeFrame(AVFrame* frame, unsigned int width, unsigned int
+   else
+   {
+     // We need an extra buffer and copy it manually afterwards
+-    pictureRGB->format = AV_PIX_FMT_RGB32;
++    pictureRGB->format = outputPixelFormat;
+     pictureRGB->width = width;
+     pictureRGB->height = height;
+     // we copy the data manually later so give a chance to intrinsics (e.g. mmx, neon)
+@@ -485,8 +532,9 @@ bool CFFmpegImage::DecodeFrame(AVFrame* frame, unsigned int width, unsigned int
+     nHeight = (unsigned int)(nWidth / ratio + 0.5f);
+   }
+
+-  struct SwsContext* context = sws_getContext(m_originalWidth, m_originalHeight, pixFormat,
+-    nWidth, nHeight, AV_PIX_FMT_RGB32, SWS_BICUBIC, NULL, NULL, NULL);
++  struct SwsContext* context =
++      sws_getContext(m_originalWidth, m_originalHeight, pixFormat, nWidth, nHeight,
++                     outputPixelFormat, SWS_BICUBIC, NULL, NULL, NULL);
+
+   if (range == AVCOL_RANGE_JPEG)
+   {
+diff --git a/xbmc/guilib/FFmpegImage.h b/xbmc/guilib/FFmpegImage.h
+index 0f7cee380c253..7be0df1eeb116 100644
+--- a/xbmc/guilib/FFmpegImage.h
++++ b/xbmc/guilib/FFmpegImage.h
+@@ -60,6 +60,7 @@ class CFFmpegImage : public IImage
+
+   bool LoadImageFromMemory(unsigned char* buffer, unsigned int bufSize,
+                            unsigned int width, unsigned int height) override;
++  bool IsFormatSupported(XB_FMT format) override;
+   bool Decode(unsigned char * const pixels, unsigned int width, unsigned int height,
+               unsigned int pitch, unsigned int format) override;
+   bool CreateThumbnailFromSurface(unsigned char* bufferin, unsigned int width,
+@@ -76,7 +77,12 @@ class CFFmpegImage : public IImage
+ private:
+   static void FreeIOCtx(AVIOContext** ioctx);
+   AVFrame* ExtractFrame();
+-  bool DecodeFrame(AVFrame* m_pFrame, unsigned int width, unsigned int height, unsigned int pitch, unsigned char * const pixels);
++  bool DecodeFrame(AVFrame* m_pFrame,
++                   unsigned int width,
++                   unsigned int height,
++                   unsigned int pitch,
++                   unsigned char* const pixels,
++                   AVPixelFormat textureFormat = AV_PIX_FMT_RGB32);
+   static int EncodeFFmpegFrame(AVCodecContext *avctx, AVPacket *pkt, int *got_packet, AVFrame *frame);
+   static int DecodeFFmpegFrame(AVCodecContext *avctx, AVFrame *frame, int *got_frame, AVPacket *pkt);
+   static AVPixelFormat ConvertFormats(AVFrame* frame);
+diff --git a/xbmc/guilib/GUITextureGLES.cpp b/xbmc/guilib/GUITextureGLES.cpp
+index d92201ae7fcce..7830c56feb527 100644
+--- a/xbmc/guilib/GUITextureGLES.cpp
++++ b/xbmc/guilib/GUITextureGLES.cpp
+@@ -65,10 +65,24 @@ void CGUITextureGLES::Begin(UTILS::COLOR::Color color)
+   }
+
+   bool hasAlpha = m_texture.m_textures[m_currentFrame]->HasAlpha() || m_col[3] < 255;
++  bool alphaOnlyTexture = m_texture.m_textures[m_currentFrame]->IsAlphaTexture();
+
+   if (m_diffuse.size())
+   {
+-    if (m_col[0] == 255 && m_col[1] == 255 && m_col[2] == 255 && m_col[3] == 255 )
++    bool alphaOnlyDiffuse = m_diffuse.m_textures[0]->IsAlphaTexture();
++    if (alphaOnlyTexture && alphaOnlyDiffuse)
++    {
++      m_renderSystem->EnableGUIShader(ShaderMethodGLES::SM_MULTI_BLENDCOLOR_ALPHA_ALPHA);
++    }
++    else if (alphaOnlyTexture)
++    {
++      m_renderSystem->EnableGUIShader(ShaderMethodGLES::SM_MULTI_BLENDCOLOR_ALPHA_COLOR);
++    }
++    else if (alphaOnlyDiffuse)
++    {
++      m_renderSystem->EnableGUIShader(ShaderMethodGLES::SM_MULTI_BLENDCOLOR_COLOR_ALPHA);
++    }
++    else if (m_col[0] == 255 && m_col[1] == 255 && m_col[2] == 255 && m_col[3] == 255)
+     {
+       m_renderSystem->EnableGUIShader(ShaderMethodGLES::SM_MULTI);
+     }
+@@ -84,7 +98,11 @@ void CGUITextureGLES::Begin(UTILS::COLOR::Color color)
+   }
+   else
+   {
+-    if (m_col[0] == 255 && m_col[1] == 255 && m_col[2] == 255 && m_col[3] == 255)
++    if (alphaOnlyTexture)
++    {
++      m_renderSystem->EnableGUIShader(ShaderMethodGLES::SM_TEXTURE_ALPHA);
++    }
++    else if (m_col[0] == 255 && m_col[1] == 255 && m_col[2] == 255 && m_col[3] == 255)
+     {
+       m_renderSystem->EnableGUIShader(ShaderMethodGLES::SM_TEXTURE_NOBLEND);
+     }
+diff --git a/xbmc/guilib/Texture.cpp b/xbmc/guilib/Texture.cpp
+index 4a2f80e3622d2..166326db5252f 100644
+--- a/xbmc/guilib/Texture.cpp
++++ b/xbmc/guilib/Texture.cpp
+@@ -15,6 +15,7 @@
+ #include "filesystem/File.h"
+ #include "filesystem/ResourceFile.h"
+ #include "filesystem/XbtFile.h"
++#include "guilib/TextureFormats.h"
+ #include "guilib/iimage.h"
+ #include "guilib/imagefactory.h"
+ #include "utils/URIUtils.h"
+@@ -50,7 +51,7 @@ CTexture::~CTexture()
+   m_pixels = NULL;
+ }
+
+-void CTexture::Allocate(unsigned int width, unsigned int height, XB_FMT format)
++void CTexture::Allocate(unsigned int width, unsigned int height, XB_FMT format, bool scalable)
+ {
+   m_imageWidth = m_originalWidth = width;
+   m_imageHeight = m_originalHeight = height;
+@@ -78,7 +79,7 @@ void CTexture::Allocate(unsigned int width, unsigned int height, unsigned int fo
+     m_textureWidth = ((m_textureWidth + 3) / 4) * 4;
+     m_textureHeight = ((m_textureHeight + 3) / 4) * 4;
+   }
+-  else
++  else if (scalable)
+   {
+     // align all textures so that they have an even width
+     // in some circumstances when we downsize a thumbnail
+@@ -102,9 +103,9 @@ void CTexture::Allocate(unsigned int width, unsigned int height, unsigned int fo
+
+   KODI::MEMORY::AlignedFree(m_pixels);
+   m_pixels = NULL;
+-  if (GetPitch() * GetRows() > 0)
++  if (GetPitch(m_textureWidth, m_format) * GetRows(m_textureHeight, m_format) > 0)
+   {
+-    size_t size = GetPitch() * GetRows();
++    size_t size = GetPitch(m_textureWidth, m_format) * GetRows(m_textureHeight, m_format);
+     m_pixels = static_cast<unsigned char*>(KODI::MEMORY::AlignedMalloc(size, 32));
+
+     if (m_pixels == nullptr)
+@@ -127,15 +128,18 @@ void CTexture::Update(unsigned int width,
+   if (format & XB_FMT_DXT_MASK)
+     return;
+
+-  Allocate(width, height, format);
++  if (IsGPUFormatSupported(format))
++    Allocate(width, height, format, false);
++  else
++    Allocate(width, height, XB_FMT_A8R8G8B8, false);
+
+   if (m_pixels == nullptr)
+     return;
+
+-  unsigned int srcPitch = pitch ? pitch : GetPitch(width);
+-  unsigned int srcRows = GetRows(height);
+-  unsigned int dstPitch = GetPitch(m_textureWidth);
+-  unsigned int dstRows = GetRows(m_textureHeight);
++  unsigned int srcPitch = pitch ? pitch : GetPitch(width, format);
++  unsigned int srcRows = GetRows(height, format);
++  unsigned int dstPitch = GetPitch(m_textureWidth, format);
++  unsigned int dstRows = GetRows(m_textureHeight, format);
+
+   if (srcPitch == dstPitch)
+     memcpy(m_pixels, pixels, srcPitch * std::min(srcRows, dstRows));
+@@ -150,6 +154,10 @@ void CTexture::Update(unsigned int width,
+       dst += dstPitch;
+     }
+   }
++
++  if (!IsGPUFormatSupported(format))
++    ConvertToBGRA(format);
++
+   ClampToEdge();
+
+   if (loadToGPU)
+@@ -193,7 +201,8 @@ std::unique_ptr<CTexture> CTexture::LoadFromFile(const std::string& texturePath,
+                                                  unsigned int idealWidth,
+                                                  unsigned int idealHeight,
+                                                  bool requirePixels,
+-                                                 const std::string& strMimeType)
++                                                 const std::string& strMimeType,
++                                                 XB_FMT format)
+ {
+ #if defined(TARGET_ANDROID)
+   CURL url(texturePath);
+@@ -217,7 +226,7 @@ std::unique_ptr<CTexture> CTexture::LoadFromFile(const std::string& texturePath,
+     }
+   }
+ #endif
+-  std::unique_ptr<CTexture> texture = CTexture::CreateTexture();
++  std::unique_ptr<CTexture> texture = CTexture::CreateTexture(0, 0, format);
+   if (texture->LoadFromFileInternal(texturePath, idealWidth, idealHeight, requirePixels, strMimeType))
+     return texture;
+   return {};
+@@ -227,9 +236,10 @@ std::unique_ptr<CTexture> CTexture::LoadFromFileInMemory(unsigned char* buffer,
+                                                          size_t bufferSize,
+                                                          const std::string& mimeType,
+                                                          unsigned int idealWidth,
+-                                                         unsigned int idealHeight)
++                                                         unsigned int idealHeight,
++                                                         XB_FMT format)
+ {
+-  std::unique_ptr<CTexture> texture = CTexture::CreateTexture();
++  std::unique_ptr<CTexture> texture = CTexture::CreateTexture(0, 0, format);
+   if (texture->LoadFromFileInMem(buffer, bufferSize, mimeType, idealWidth, idealHeight))
+     return texture;
+   return {};
+@@ -336,8 +346,18 @@ bool CTexture::LoadIImage(IImage* pImage,
+   {
+     if (pImage->Width() > 0 && pImage->Height() > 0)
+     {
+-      Allocate(pImage->Width(), pImage->Height(), XB_FMT_A8R8G8B8);
+-      if (m_pixels != nullptr && pImage->Decode(m_pixels, GetTextureWidth(), GetRows(), GetPitch(), XB_FMT_A8R8G8B8))
++      // if we don't request a specific format, the decoder can suggest a compatible one.
++      if (m_format == XB_FMT_UNKNOWN)
++        m_format = pImage->GetCompatibleFormat();
++      // if the decoder can't write to the texture, fall back to our standard four channel texture
++      else if (!pImage->IsFormatSupported(m_format))
++        m_format = XB_FMT_A8R8G8B8;
++      // if not supported on the GPU, we fall back
++      if (!IsGPUFormatSupported(m_format))
++        m_format = XB_FMT_A8R8G8B8;
++      Allocate(pImage->Width(), pImage->Height(), m_format);
++      if (m_pixels != nullptr &&
++          pImage->Decode(m_pixels, GetTextureWidth(), GetRows(), GetPitch(), m_format))
+       {
+         if (pImage->Orientation())
+           m_orientation = pImage->Orientation() - 1;
+@@ -428,7 +448,12 @@ bool CTexture::SwapBlueRed(unsigned char* pixels,
+
+ unsigned int CTexture::GetPitch(unsigned int width) const
+ {
+-  switch (m_format)
++  return GetPitch(width, m_format);
++}
++
++unsigned int CTexture::GetPitch(unsigned int width, XB_FMT format) const
++{
++  switch (format)
+   {
+   case XB_FMT_DXT1:
+     return ((width + 3) / 4) * 8;
+@@ -436,8 +461,12 @@ unsigned int CTexture::GetPitch(unsigned int width) const
+   case XB_FMT_DXT5:
+   case XB_FMT_DXT5_YCoCg:
+     return ((width + 3) / 4) * 16;
++  case XB_FMT_R8:
+   case XB_FMT_A8:
++  case XB_FMT_L8:
+     return width;
++  case XB_FMT_L8A8:
++    return width * 2;
+   case XB_FMT_RGB8:
+     return (((width + 1)* 3 / 4) * 4);
+   case XB_FMT_RGBA8:
+@@ -449,7 +478,12 @@ unsigned int CTexture::GetPitch(unsigned int width) const
+
+ unsigned int CTexture::GetRows(unsigned int height) const
+ {
+-  switch (m_format)
++  return GetRows(height, m_format);
++}
++
++unsigned int CTexture::GetRows(unsigned int height, XB_FMT format) const
++{
++  switch (format)
+   {
+   case XB_FMT_DXT1:
+     return (height + 3) / 4;
+@@ -473,7 +507,11 @@ unsigned int CTexture::GetBlockSize() const
+   case XB_FMT_DXT5_YCoCg:
+     return 16;
+   case XB_FMT_A8:
++  case XB_FMT_L8:
++  case XB_FMT_R8:
+     return 1;
++  case XB_FMT_L8A8:
++    return 2;
+   default:
+     return 4;
+   }
+@@ -484,6 +522,11 @@ bool CTexture::HasAlpha() const
+   return m_hasAlpha;
+ }
+
++bool CTexture::IsAlphaTexture() const
++{
++  return m_format == XB_FMT_A8;
++}
++
+ void CTexture::SetMipmapping()
+ {
+   m_mipmapping = true;
+@@ -493,3 +536,41 @@ bool CTexture::IsMipmapped() const
+ {
+   return m_mipmapping;
+ }
++
++void CTexture::ConvertToBGRA(XB_FMT format)
++{
++  size_t size = GetPitch(m_textureWidth, format) * GetRows(m_textureHeight, format);
++
++  if (format == XB_FMT_A8)
++  {
++    for (int32_t i = size - 1; i >= 0; i--)
++    {
++      m_pixels[i * 4 + 3] = m_pixels[i];
++      m_pixels[i * 4 + 2] = char(0xff);
++      m_pixels[i * 4 + 1] = char(0xff);
++      m_pixels[i * 4] = char(0xff);
++    }
++  }
++  else if (format == XB_FMT_L8)
++  {
++    for (int32_t i = size - 1; i >= 0; i--)
++    {
++      m_pixels[i * 4 + 3] = char(0xff);
++      m_pixels[i * 4 + 2] = m_pixels[i];
++      m_pixels[i * 4 + 1] = m_pixels[i];
++      m_pixels[i * 4] = m_pixels[i];
++    }
++  }
++  else if (format == XB_FMT_L8A8)
++  {
++    for (int32_t i = size / 2 - 1; i >= 0; i--)
++    {
++      m_pixels[i * 4 + 3] = m_pixels[i * 2 + 1];
++      m_pixels[i * 4 + 2] = m_pixels[i * 2];
++      m_pixels[i * 4 + 1] = m_pixels[i * 2];
++      m_pixels[i * 4] = m_pixels[i * 2];
++    }
++  }
++
++  m_format =XB_FMT_A8R8G8B8;
++}
+diff --git a/xbmc/guilib/Texture.h b/xbmc/guilib/Texture.h
+index 343e9968bf53d..95b181f423f6b 100644
+--- a/xbmc/guilib/Texture.h
++++ b/xbmc/guilib/Texture.h
+@@ -55,7 +55,8 @@ class CTexture
+                                                 unsigned int idealWidth = 0,
+                                                 unsigned int idealHeight = 0,
+                                                 bool requirePixels = false,
+-                                                const std::string& strMimeType = "");
++                                                const std::string& strMimeType = "",
++                                                XB_FMT format = XB_FMT_A8R8G8B8);
+
+   /*! \brief Load a texture from a file in memory
+    Loads a texture from a file in memory, restricting in size if needed based on maxHeight and maxWidth.
+@@ -71,7 +71,8 @@
+                                                         size_t bufferSize,
+                                                         const std::string& mimeType,
+                                                         unsigned int idealWidth = 0,
+-                                                        unsigned int idealHeight = 0);
++                                                        unsigned int idealHeight = 0,
++                                                        XB_FMT format = XB_FMT_A8R8G8B8);
+
+   bool LoadFromMemory(unsigned int width,
+                       unsigned int height,
+@@ -88,6 +89,7 @@
+
+   bool HasAlpha() const;
+   void SetAlpha(bool hasAlpha) { m_hasAlpha = hasAlpha; }
++  bool IsAlphaTexture() const;
+
+   void SetMipmapping();
+   bool IsMipmapped() const;
+@@ -91,8 +94,8 @@ class CTexture
+   virtual void BindToUnit(unsigned int unit) = 0;
+
+   unsigned char* GetPixels() const { return m_pixels; }
+-  unsigned int GetPitch() const { return GetPitch(m_textureWidth); }
+-  unsigned int GetRows() const { return GetRows(m_textureHeight); }
++  unsigned int GetPitch() const { return GetPitch(m_textureWidth, m_format); }
++  unsigned int GetRows() const { return GetRows(m_textureHeight, m_format); }
+   unsigned int GetTextureWidth() const { return m_textureWidth; }
+   unsigned int GetTextureHeight() const { return m_textureHeight; }
+   unsigned int GetWidth() const { return m_imageWidth; }
+@@ -122,12 +124,14 @@
+               XB_FMT format,
+               const unsigned char* pixels,
+               bool loadToGPU);
+-  void Allocate(unsigned int width, unsigned int height, XB_FMT format);
++  void Allocate(unsigned int width, unsigned int height, XB_FMT format, bool scalable = true);
+   void ClampToEdge();
+
+   static unsigned int PadPow2(unsigned int x);
+   static bool SwapBlueRed(unsigned char *pixels, unsigned int height, unsigned int pitch, unsigned int elements = 4, unsigned int offset=0);
+
++  virtual bool IsGPUFormatSupported(const uint32_t format) { return format == XB_FMT_A8R8G8B8; }
++
+ private:
+   // no copy constructor
+   CTexture(const CTexture& copy) = delete;
+@@ -123,9 +128,13 @@ class CTexture
+   bool LoadIImage(IImage* pImage, unsigned char* buffer, unsigned int bufSize, unsigned int width, unsigned int height);
+   // helpers for computation of texture parameters for compressed textures
+   unsigned int GetPitch(unsigned int width) const;
++  unsigned int GetPitch(unsigned int width, XB_FMT format) const;
+   unsigned int GetRows(unsigned int height) const;
++  unsigned int GetRows(unsigned int height, XB_FMT format) const;
+   unsigned int GetBlockSize() const;
+
++  void ConvertToBGRA(XB_FMT format);
++
+   unsigned int m_imageWidth;
+   unsigned int m_imageHeight;
+   unsigned int m_textureWidth;
+diff --git a/xbmc/guilib/TextureDX.cpp b/xbmc/guilib/TextureDX.cpp
+index 65aa854163472..2ce799e3f8645 100644
+--- a/xbmc/guilib/TextureDX.cpp
++++ b/xbmc/guilib/TextureDX.cpp
+@@ -191,3 +191,21 @@ void CDXTexture::LoadToGPU()
+ void CDXTexture::BindToUnit(unsigned int unit)
+ {
+ }
++
++bool CDXTexture::IsGPUFormatSupported(XB_FMT format)
++{
++  switch (format)
++  {
++    case XB_FMT_A8R8G8B8:
++    case XB_FMT_RGB8:
++    case XB_FMT_R8:
++    case XB_FMT_DXT1:
++    case XB_FMT_DXT3:
++    case XB_FMT_DXT5:
++    case XB_FMT_DXT5_YCoCg:
++      //FIXME: actually return supported compression
++      return true;
++    default:
++      return false;
++  }
++}
+diff --git a/xbmc/guilib/TextureDX.h b/xbmc/guilib/TextureDX.h
+index 0858780df2f16..0bb9d3bfd0b4f 100644
+--- a/xbmc/guilib/TextureDX.h
++++ b/xbmc/guilib/TextureDX.h
+@@ -24,6 +24,7 @@ class CDXTexture : public CTexture
+   void DestroyTextureObject();
+   virtual void LoadToGPU();
+   void BindToUnit(unsigned int unit);
++  bool IsGPUFormatSupported(const uint32_t format) override;
+
+   ID3D11Texture2D* GetTextureObject()
+   {
+diff --git a/xbmc/guilib/TextureFormats.h b/xbmc/guilib/TextureFormats.h
+index 809d4e5b52463..5ae3dced9c462 100644
+--- a/xbmc/guilib/TextureFormats.h
++++ b/xbmc/guilib/TextureFormats.h
+@@ -20,6 +20,9 @@
+   XB_FMT_RGBA8       = 0x40,
+   XB_FMT_RGB8        = 0x80,
+   XB_FMT_MASK        = 0xFFFF,
++  XB_FMT_A8          = 0x100, // Single channel, used as 1,1,1,A (alpha)
++  XB_FMT_L8          = 0x110, // Single channel, used as L,L,L,1 (luma)
++  XB_FMT_L8A8        = 0x120, // Dual channel, used as L,L,L,A (lumaalpha)
+   XB_FMT_OPAQUE      = 0x10000,
+ };
+ // clang-format on
+diff --git a/xbmc/guilib/TextureGL.cpp b/xbmc/guilib/TextureGL.cpp
+index ef01bdf540196..9cfe999311496 100644
+--- a/xbmc/guilib/TextureGL.cpp
++++ b/xbmc/guilib/TextureGL.cpp
+@@ -110,7 +110,50 @@ void CGLTexture::LoadToGPU()
+     m_textureWidth = maxSize;
+   }
+
++  if (m_format == XB_FMT_A8 || m_format == XB_FMT_L8)
++    glPixelStorei(GL_UNPACK_ALIGNMENT, 1);
++  else if (m_format == XB_FMT_L8A8)
++    glPixelStorei(GL_UNPACK_ALIGNMENT, 2);
++
+ #ifndef HAS_GLES
++
++#ifndef GL_RED
++#define GL_RED 0x1903
++#endif
++#ifndef GL_GREEN
++#define GL_GREEN 0x1904
++#endif
++#ifndef GL_RG
++#define GL_RG 0x8227
++#endif
++#ifndef GL_TEXTURE_SWIZZLE_RGBA
++#define GL_TEXTURE_SWIZZLE_RGBA 0x8E46
++#endif
++
++  if (CServiceBroker::GetRenderSystem()->IsExtSupported("GL_ARB_texture_swizzle"))
++  {
++    if (m_format == XB_FMT_A8)
++    {
++      GLint const swizzle[] = {GL_ONE, GL_ONE, GL_ONE, GL_RED};
++      glTexParameteriv(GL_TEXTURE_2D, GL_TEXTURE_SWIZZLE_RGBA, swizzle);
++    }
++    else if (m_format == XB_FMT_L8)
++    {
++      GLint const swizzle[] = {GL_RED, GL_RED, GL_RED, GL_ONE};
++      glTexParameteriv(GL_TEXTURE_2D, GL_TEXTURE_SWIZZLE_RGBA, swizzle);
++    }
++    else if (m_format == XB_FMT_L8A8)
++    {
++      GLint const swizzle[] = {GL_RED, GL_RED, GL_RED, GL_GREEN};
++      glTexParameteriv(GL_TEXTURE_2D, GL_TEXTURE_SWIZZLE_RGBA, swizzle);
++    }
++  }
++  else if (m_format == XB_FMT_A8 || m_format == XB_FMT_L8 || m_format == XB_FMT_L8A8)
++  {
++    CLog::Log(LOGERROR, "{} Attempted to upload an unsupported texture", __FUNCTION__);
++    return;
++  }
++
+   GLenum format = GL_BGRA;
+   GLint numcomponents = GL_RGBA;
+
+@@ -130,6 +173,16 @@ void CGLTexture::LoadToGPU()
+     format = GL_RGB;
+     numcomponents = GL_RGB;
+     break;
++  case XB_FMT_A8:
++  case XB_FMT_L8:
++  case XB_FMT_R8:
++    format = GL_RED;
++    numcomponents = GL_RED;
++    break;
++  case XB_FMT_L8A8:
++    format = GL_RG;
++    numcomponents = GL_RG;
++    break;
+   case XB_FMT_A8R8G8B8:
+   default:
+     break;
+@@ -164,6 +217,9 @@ void CGLTexture::LoadToGPU()
+   // system headers, and trust the extension list instead.
+ #ifndef GL_BGRA_EXT
+ #define GL_BGRA_EXT 0x80E1
++#endif
++#ifndef GL_RED
++#define GL_RED 0x1903
+ #endif
+
+   GLint internalformat;
+@@ -178,6 +234,21 @@ void CGLTexture::LoadToGPU()
+     case XB_FMT_RGB8:
+       internalformat = pixelformat = GL_RGB;
+       break;
++    case XB_FMT_A8:
++      internalformat = pixelformat = GL_ALPHA;
++      break;
++    case XB_FMT_L8:
++      internalformat = pixelformat = GL_LUMINANCE;
++      break;
++    case XB_FMT_R8:
++      if (m_isOglVersion3orNewer)
++        internalformat = pixelformat = GL_RED;
++      else
++        internalformat = pixelformat = GL_LUMINANCE;
++      break;
++    case XB_FMT_L8A8:
++      internalformat = pixelformat = GL_LUMINANCE_ALPHA;
++      break;
+     case XB_FMT_A8R8G8B8:
+       if (CServiceBroker::GetRenderSystem()->IsExtSupported("GL_EXT_texture_format_BGRA8888") ||
+           CServiceBroker::GetRenderSystem()->IsExtSupported("GL_IMG_texture_format_BGRA8888"))
+@@ -216,6 +287,7 @@ void CGLTexture::LoadToGPU()
+   }
+
+   m_loadedToGPU = true;
++  glPixelStorei(GL_UNPACK_ALIGNMENT, 4);
+ }
+
+ void CGLTexture::BindToUnit(unsigned int unit)
+@@ -224,3 +296,45 @@ void CGLTexture::BindToUnit(unsigned int unit)
+   glBindTexture(GL_TEXTURE_2D, m_texture);
+ }
+
++bool CGLTexture::IsGPUFormatSupported(const uint32_t format)
++{
++#ifdef HAS_GL
++  switch (format)
++  {
++    case XB_FMT_A8R8G8B8:
++    case XB_FMT_RGB8:
++    case XB_FMT_RGBA8:
++      return true;
++    case XB_FMT_L8:
++    case XB_FMT_A8:
++    case XB_FMT_L8A8:
++      return CServiceBroker::GetRenderSystem()->IsExtSupported("GL_ARB_texture_swizzle");
++    case XB_FMT_DXT1:
++    case XB_FMT_DXT3:
++    case XB_FMT_DXT5:
++    case XB_FMT_DXT5_YCoCg:
++      //FIXME: actually return supported compression
++      return true;
++    default:
++      return false;
++  }
++#else
++  switch (format)
++  {
++    case XB_FMT_A8R8G8B8:
++    case XB_FMT_RGB8:
++    case XB_FMT_RGBA8:
++    case XB_FMT_L8:
++    case XB_FMT_A8:
++    case XB_FMT_L8A8:
++    case XB_FMT_DXT1:
++    case XB_FMT_DXT3:
++    case XB_FMT_DXT5:
++    case XB_FMT_DXT5_YCoCg:
++      //FIXME: actually return supported compression
++      return true;
++    default:
++      return false;
++  }
++#endif
++}
+diff --git a/xbmc/guilib/TextureGL.h b/xbmc/guilib/TextureGL.h
+index 51c7035de6ced..980770f711ed1 100644
+--- a/xbmc/guilib/TextureGL.h
++++ b/xbmc/guilib/TextureGL.h
+@@ -25,6 +25,7 @@ class CGLTexture : public CTexture
+   void DestroyTextureObject() override;
+   void LoadToGPU() override;
+   void BindToUnit(unsigned int unit) override;
++  bool IsGPUFormatSupported(const uint32_t format) override;
+
+ protected:
+   GLuint m_texture = 0;
+diff --git a/xbmc/guilib/TextureManager.cpp b/xbmc/guilib/TextureManager.cpp
+index ddf2e77e7f99a..d4f51883164c5 100644
+--- a/xbmc/guilib/TextureManager.cpp
++++ b/xbmc/guilib/TextureManager.cpp
+@@ -297,6 +297,17 @@ const CTextureArray& CGUITextureManager::Load(const std::string& strTextureName,
+   if (!HasTexture(strTextureName, &strPath, &bundle, &size))
+     return emptyTexture;
+
++  XB_FMT textureFormat =XB_FMT_UNKNOWN ;
++  if (StringUtils::StartsWith(strTextureName, "special://skin/"))
++  {
++    if (strTextureName.find("_alpha.") != std::string::npos)
++      textureFormat =  XB_FMT_A8;
++    else if (strTextureName.find("_luma.") != std::string::npos)
++      textureFormat =  XB_FMT_L8;
++    else if (strTextureName.find("_lumaalpha.") != std::string::npos)
++      textureFormat =  XB_FMT_L8A8;
++  }
++
+   if (size) // we found the texture
+   {
+     for (int i = 0; i < (int)m_vecTextures.size(); ++i)
+@@ -393,10 +404,11 @@ const CTextureArray& CGUITextureManager::Load(const std::string& strTextureName,
+     auto frame = anim.ReadFrame();
+     while (frame)
+     {
+-      std::unique_ptr<CTexture> glTexture = CTexture::CreateTexture();
++      std::unique_ptr<CTexture> glTexture = CTexture::CreateTexture(0, 0, textureFormat);
+       if (glTexture)
+       {
+-        glTexture->LoadFromMemory(anim.Width(), anim.Height(), frame->GetPitch(), XB_FMT_A8R8G8B8, true, frame->m_pImage);
++        glTexture->LoadFromMemory(anim.Width(), anim.Height(), frame->GetPitch(), textureFormat,
++                                  true, frame->m_pImage);
+         maxWidth = std::max(maxWidth, glTexture->GetWidth());
+         maxHeight = std::max(maxHeight, glTexture->GetHeight());
+         pMap->Add(std::move(glTexture), frame->m_delay);
+@@ -436,7 +448,7 @@ const CTextureArray& CGUITextureManager::Load(const std::string& strTextureName,
+   }
+   else
+   {
+-    pTexture = CTexture::LoadFromFile(strPath);
++    pTexture = CTexture::LoadFromFile(strPath, 0, 0, false, "", textureFormat);
+     if (!pTexture)
+       return emptyTexture;
+     width = pTexture->GetWidth();
+diff --git a/xbmc/guilib/iimage.h b/xbmc/guilib/iimage.h
+index 299e74c6f2b06..7a0c97243d1cc 100644
+--- a/xbmc/guilib/iimage.h
++++ b/xbmc/guilib/iimage.h
+@@ -8,6 +8,8 @@
+
+ #pragma once
+
++#include "guilib/TextureFormats.h"
++
+ #include <string>
+
+ class IImage
+@@ -25,6 +27,17 @@ class IImage
+    \return true if the image could be loaded
+    */
+   virtual bool LoadImageFromMemory(unsigned char* buffer, unsigned int bufSize, unsigned int width, unsigned int height)=0;
++  /*!
++   \brief Check if a Kodi texture format is compatible
++   \param format The format to check
++   \return true if the decoder can write such a texture
++   */
++  virtual bool IsFormatSupported(XB_FMT format) { return format == XB_FMT_A8R8G8B8; }
++  /*!
++   \brief Reports to what format the image could be decoded into
++   \return the Kodi texture format closest to the source format
++   */
++  XB_FMT GetCompatibleFormat() const { return m_format; }
+   /*!
+    \brief Decodes the previously loaded image data to the output buffer in 32 bit raw bits
+    \param pixels The output buffer
+@@ -70,5 +83,5 @@ class IImage
+   unsigned int m_originalHeight = 0;  ///< original image height before scaling or cropping
+   unsigned int m_orientation = 0;
+   bool m_hasAlpha = false;
+-
++  XB_FMT m_format{XB_FMT_A8R8G8B8};
+ };
+
+From b5ea0990018899d4a5534dca0c3ebb7360d15520 Mon Sep 17 00:00:00 2001
+From: sarbes <sarbes@kodi.tv>
+Date: Thu, 16 Mar 2023 00:56:46 +0100
+Subject: [PATCH 4/4] Implement L/A/LA support for the texture packer
+
+---
+ .../TexturePacker/src/TexturePacker.cpp       | 127 +++++++++++++++---
+ .../TexturePacker/src/decoder/IDecoder.h      |   3 +
+ .../TexturePacker/src/decoder/PNGDecoder.cpp  |   3 +
+ 3 files changed, 116 insertions(+), 17 deletions(-)
+
+diff --git a/tools/depends/native/TexturePacker/src/TexturePacker.cpp b/tools/depends/native/TexturePacker/src/TexturePacker.cpp
+index a6fd4284f1e98..4f80b5251fd10 100644
+--- a/tools/depends/native/TexturePacker/src/TexturePacker.cpp
++++ b/tools/depends/native/TexturePacker/src/TexturePacker.cpp
+@@ -67,6 +67,10 @@ const char *GetFormatString(unsigned int format)
+     return "ARGB ";
+   case XB_FMT_A8:
+     return "A8   ";
++  case XB_FMT_L8:
++    return "L8   ";
++  case XB_FMT_L8A8:
++    return "L8A8 ";
+   default:
+     return "?????";
+   }
+@@ -246,11 +246,107 @@
+   frame.SetUnpackedSize(size);
+   frame.SetWidth(width);
+   frame.SetHeight(height);
+-  frame.SetFormat(hasAlpha ? format : static_cast<XB_FMT>(format | XB_FMT_OPAQUE));
++  //frame.SetFormat(hasAlpha ? format : static_cast<XB_FMT>(format | XB_FMT_OPAQUE));
++  frame.SetFormat(decodedFrame.rgbaImage.format);
+   frame.SetDuration(delay);
+   return frame;
+ }
+
++void convertToSingleChannel(RGBAImage& image, uint32_t channel)
++{
++  uint32_t size = (image.width * image.height);
++  for (uint32_t i = 0; i < size; i++)
++  {
++    image.pixels[i] = image.pixels[i * 4 + channel];
++  }
++  if (channel == 3)
++    image.format =XB_FMT_A8;
++  else
++  {
++    image.format = static_cast<XB_FMT>(XB_FMT_L8 | XB_FMT_OPAQUE);
++    //image.format |= XB_FMT_OPAQUE;
++  }
++  image.bbp = 8;
++  image.pitch = 1 * image.width;
++}
++
++void convertToDualChannel(RGBAImage& image)
++{
++  uint32_t size = (image.width * image.height);
++  for (uint32_t i = 0; i < size; i++)
++  {
++    image.pixels[i * 2] = image.pixels[i * 4];
++    image.pixels[i * 2 + 1] = image.pixels[i * 4 + 3];
++  }
++  image.format =XB_FMT_L8A8;
++  image.bbp = 16;
++  image.pitch = 2 * image.width;
++}
++
++void ReduceChannels(RGBAImage& image)
++{
++  if (image.format != XB_FMT_A8R8G8B8) {
++    return; }
++  uint32_t size = (image.width * image.height);
++  char red = image.pixels[0];
++  char green = image.pixels[1];
++  char blue = image.pixels[2];
++  char alpha = image.pixels[3];
++  bool uniformRed = true;
++  bool uniformGreen = true;
++  bool uniformBlue = true;
++  bool uniformAlpha = true;
++  bool isGrey = true;
++
++  // Checks each pixel for various properties.
++  for (uint32_t i = 0; i < size; i++)
++  {
++    if (image.pixels[i * 4] != red && image.pixels[i * 4 + 3] != (char)0x00)
++      uniformRed = false;
++    if (image.pixels[i * 4 + 1] != green && image.pixels[i * 4 + 3] != (char)0x00)
++      uniformGreen = false;
++    if (image.pixels[i * 4 + 2] != blue && image.pixels[i * 4 + 3] != (char)0x00)
++      uniformBlue = false;
++    if (image.pixels[i * 4 + 3] != alpha)
++      uniformAlpha = false;
++    if (!(image.pixels[i * 4] == image.pixels[i * 4 + 1] &&
++          image.pixels[i * 4] == image.pixels[i * 4 + 2]) &&
++        image.pixels[i * 4 + 3] != (char)0x00)
++      isGrey = false;
++  }
++
++  if (uniformAlpha && alpha != (char)0xff)
++    printf("WARNING: uniform alpha detected! Use diffusecolor!\n");
++
++  bool isWhite = red == (char)0xff && green == (char)0xff && blue == (char)0xff;
++  if (uniformRed && uniformGreen && uniformBlue && !isWhite)
++    printf("WARNING: uniform color detected! Use diffusecolor!\n");
++
++  if (uniformAlpha && alpha == (char)0xff)
++  {
++    image.format = static_cast<XB_FMT>(image.format | XB_FMT_OPAQUE);
++    if (isGrey)
++    {
++      convertToSingleChannel(image, 1);
++      return;
++    }
++    return;
++  }
++  else
++  {
++    if (uniformRed && uniformGreen && uniformBlue && isWhite)
++    {
++      convertToSingleChannel(image, 3);
++      return;
++    }
++    else if (isGrey)
++    {
++      convertToDualChannel(image);
++      return;
++    }
++  }
++}
++
+ bool TexturePacker::CheckDupe(MD5Context* ctx,
+                               unsigned int pos)
+ {
+@@ -338,8 +434,9 @@
+     {
+       for (unsigned int j = 0; j < frames.frameList.size(); j++)
+       {
++        ReduceChannels(frames.frameList[j].rgbaImage);
+         CXBTFFrame frame = CreateXBTFFrame(frames.frameList[j], writer);
+-        file.GetFrames().push_back(frame);
++        file.GetFrames().push_back(frame);
+         printf("    frame %4i (delay:%4i)                         %s%c (%d,%d @ %" PRIu64
+                " bytes)\n",
+                j, frame.GetDuration(), GetFormatString(frame.GetFormat()),
+diff --git a/tools/depends/native/TexturePacker/src/decoder/IDecoder.h b/tools/depends/native/TexturePacker/src/decoder/IDecoder.h
+index c9ac346514f18..f1ca2a9611a03 100644
+--- a/tools/depends/native/TexturePacker/src/decoder/IDecoder.h
++++ b/tools/depends/native/TexturePacker/src/decoder/IDecoder.h
+@@ -20,6 +20,8 @@
+
+ #pragma once
+
++#include "guilib/TextureFormats.h"
++
+ #include <cstdint>
+ #include <string>
+ #include <vector>
+@@ -61,6 +63,7 @@ class RGBAImage
+   int height = 0; // height
+   int bbp = 0; // bits per pixel
+   int pitch = 0; // rowsize in bytes
++  XB_FMT format{ XB_FMT_A8R8G8B8};
+ };
+
+ class DecodedFrame
+diff --git a/tools/depends/native/TexturePacker/src/decoder/PNGDecoder.cpp b/tools/depends/native/TexturePacker/src/decoder/PNGDecoder.cpp
+index f327400f6b9d3..e2cfe51ac6531 100644
+--- a/tools/depends/native/TexturePacker/src/decoder/PNGDecoder.cpp
++++ b/tools/depends/native/TexturePacker/src/decoder/PNGDecoder.cpp
+@@ -178,6 +178,9 @@ bool PNGDecoder::LoadFile(const std::string &filename, DecodedFrames &frames)
+     png_set_gray_to_rgb(png_ptr);
+   }
+
++  if (color_type == PNG_COLOR_TYPE_PALETTE)
++    printf("WARNING: Palette texture might not decode to optimally, please avoid!\n");
++
+   // Update the png info struct.
+   png_read_update_info(png_ptr, info_ptr);
diff --git a/projects/Rockchip/devices/RK322X/patches/kodi/kodi-100.22012-GBMUtils-LockFrontBuffer-should-return-the-front-of-queue.patch b/projects/Rockchip/devices/RK322X/patches/kodi/kodi-100.22012-GBMUtils-LockFrontBuffer-should-return-the-front-of-queue.patch
new file mode 100644
index 0000000000..acbe9442c6
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/patches/kodi/kodi-100.22012-GBMUtils-LockFrontBuffer-should-return-the-front-of-queue.patch
@@ -0,0 +1,26 @@
+From f56249dd6e79cf781da4191421bea477dc1fe5bc Mon Sep 17 00:00:00 2001
+From: Dom Cobley <popcornmix@gmail.com>
+Date: Thu, 6 Oct 2022 19:05:19 +0100
+Subject: [PATCH] GBMUtils: LockFrontBuffer should return the front of queue
+
+We are using emplace to add to back of queue, and pop to remove from front.
+We should be returning the buffer from front of queue, not the one just added.
+
+I believe we are currently only using 2 buffers, when mesa makes 4 available
+---
+ xbmc/windowing/gbm/GBMUtils.cpp | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/xbmc/windowing/gbm/GBMUtils.cpp b/xbmc/windowing/gbm/GBMUtils.cpp
+index 5267c93c8f3d7..15c4cc9d1cd0b 100644
+--- a/xbmc/windowing/gbm/GBMUtils.cpp
++++ b/xbmc/windowing/gbm/GBMUtils.cpp
+@@ -92,7 +92,7 @@ CGBMUtils::CGBMDevice::CGBMSurface::CGBMSurfaceBuffer* CGBMUtils::CGBMDevice::CG
+     m_buffers.pop();
+   }
+
+-  return *m_buffers.back();
++  return *m_buffers.front();
+ }
+
+ CGBMUtils::CGBMDevice::CGBMSurface::CGBMSurfaceBuffer::CGBMSurfaceBuffer(gbm_surface* surface)
diff --git a/projects/Rockchip/devices/RK322X/patches/kodi/kodi-100.25460-RetroPlayer-Fix-gameloop.patch b/projects/Rockchip/devices/RK322X/patches/kodi/kodi-100.25460-RetroPlayer-Fix-gameloop.patch
new file mode 100644
index 0000000000..47312424d4
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/patches/kodi/kodi-100.25460-RetroPlayer-Fix-gameloop.patch
@@ -0,0 +1,156 @@
+From 7a58ce3730408065374ce6049c683b452f289a49 Mon Sep 17 00:00:00 2001
+From: GTechAlpha <31323818+GTechAlpha@users.noreply.github.com>
+Date: Sat, 6 Jul 2024 21:24:41 -0500
+Subject: [PATCH] RetroPlayer: Fix gameloop
+
+---
+ xbmc/cores/RetroPlayer/playback/GameLoop.cpp | 81 +++++++-------------
+ xbmc/cores/RetroPlayer/playback/GameLoop.h   | 10 +--
+ 2 files changed, 31 insertions(+), 60 deletions(-)
+
+diff --git a/xbmc/cores/RetroPlayer/playback/GameLoop.cpp b/xbmc/cores/RetroPlayer/playback/GameLoop.cpp
+index 1abf258ce7453..171777fd3af24 100644
+--- a/xbmc/cores/RetroPlayer/playback/GameLoop.cpp
++++ b/xbmc/cores/RetroPlayer/playback/GameLoop.cpp
+@@ -16,7 +16,6 @@ using namespace RETRO;
+ using namespace std::chrono_literals;
+
+ #define DEFAULT_FPS 60 // In case fps is 0 (shouldn't happen)
+-#define FOREVER_MS (7 * 24 * 60 * 60 * 1000) // 1 week is large enough
+
+ CGameLoop::CGameLoop(IGameLoopCallback* callback, double fps)
+   : CThread("GameLoop"), m_callback(callback), m_fps(fps ? fps : DEFAULT_FPS), m_speedFactor(0.0)
+@@ -56,75 +55,47 @@ void CGameLoop::Process(void)
+ {
+   while (!m_bStop)
+   {
+-    if (m_speedFactor == 0.0)
++    if (m_loopSpeedFactor != m_speedFactor)
++    {
++      m_lastFrameUs = std::chrono::microseconds::zero();
++      m_loopSpeedFactor = m_speedFactor;
++    }
++
++    if (m_loopSpeedFactor == 0.0)
+     {
+-      m_lastFrameMs = 0.0;
+       m_sleepEvent.Wait(5000ms);
+     }
+     else
+     {
+-      if (m_speedFactor > 0.0)
++      if (m_lastFrameUs == std::chrono::microseconds::zero())
++        m_lastFrameUs = NowUs();
++
++      if (m_loopSpeedFactor > 0.0)
+         m_callback->FrameEvent();
+-      else if (m_speedFactor < 0.0)
++      else if (m_loopSpeedFactor < 0.0)
+         m_callback->RewindEvent();
+
+-      if (m_lastFrameMs > 0.0)
+-      {
+-        m_lastFrameMs += FrameTimeMs();
+-        m_adjustTime = m_lastFrameMs - NowMs();
+-      }
+-      else
+-      {
+-        m_lastFrameMs = NowMs();
+-        m_adjustTime = 0.0;
+-      }
+-
+-      // Calculate sleep time
+-      double sleepTimeMs = SleepTimeMs();
+-
+-      // Sleep at least 1 ms to avoid sleeping forever
+-      while (sleepTimeMs > 1.0)
+-      {
+-        m_sleepEvent.Wait(std::chrono::milliseconds(static_cast<unsigned int>(sleepTimeMs)));
+-
+-        if (m_bStop)
+-          break;
+-
+-        // Speed may have changed, update sleep time
+-        sleepTimeMs = SleepTimeMs();
+-      }
++      std::chrono::microseconds nextFrameUs = (m_lastFrameUs += FrameTimeUs());
++
++      std::chrono::microseconds sleepTimeUs = (nextFrameUs - NowUs());
++
++      if (sleepTimeUs > std::chrono::microseconds::zero())
++        m_sleepEvent.Wait(sleepTimeUs);
+     }
+   }
+ }
+
+-double CGameLoop::FrameTimeMs() const
++std::chrono::microseconds CGameLoop::FrameTimeUs() const
+ {
+-  if (m_speedFactor != 0.0)
+-    return 1000.0 / m_fps / std::abs(m_speedFactor);
++  if (m_loopSpeedFactor != 0.0)
++    return std::chrono::duration_cast<std::chrono::microseconds>(1s / m_fps /
++                                                                 std::abs(m_loopSpeedFactor));
+   else
+-    return 1000.0 / m_fps / 1.0;
+-}
+-
+-double CGameLoop::SleepTimeMs() const
+-{
+-  // Calculate next frame time
+-  const double nextFrameMs = m_lastFrameMs + FrameTimeMs();
+-
+-  // Calculate sleep time
+-  double sleepTimeMs = (nextFrameMs - NowMs()) + m_adjustTime;
+-
+-  // Reset adjust time
+-  m_adjustTime = 0.0;
+-
+-  // Positive or zero
+-  sleepTimeMs = (sleepTimeMs >= 0.0 ? sleepTimeMs : 0.0);
+-
+-  return sleepTimeMs;
++    return std::chrono::duration_cast<std::chrono::microseconds>(1s / m_fps);
+ }
+
+-double CGameLoop::NowMs() const
++std::chrono::microseconds CGameLoop::NowUs() const
+ {
+-  return std::chrono::duration<double, std::milli>(
+-             std::chrono::steady_clock::now().time_since_epoch())
+-      .count();
++  return std::chrono::duration_cast<std::chrono::microseconds>(
++      std::chrono::steady_clock::now().time_since_epoch());
+ }
+diff --git a/xbmc/cores/RetroPlayer/playback/GameLoop.h b/xbmc/cores/RetroPlayer/playback/GameLoop.h
+index 4ed8c87fe5795..e8efff374e20e 100644
+--- a/xbmc/cores/RetroPlayer/playback/GameLoop.h
++++ b/xbmc/cores/RetroPlayer/playback/GameLoop.h
+@@ -12,6 +12,7 @@
+ #include "threads/Thread.h"
+
+ #include <atomic>
++#include <chrono>
+
+ namespace KODI
+ {
+@@ -54,15 +55,14 @@ class CGameLoop : protected CThread
+   void Process() override;
+
+ private:
+-  double FrameTimeMs() const;
+-  double SleepTimeMs() const;
+-  double NowMs() const;
++  std::chrono::microseconds FrameTimeUs() const;
++  std::chrono::microseconds NowUs() const;
+
+   IGameLoopCallback* const m_callback;
+   const double m_fps;
+   std::atomic<double> m_speedFactor;
+-  double m_lastFrameMs = 0.0;
+-  mutable double m_adjustTime = 0.0;
++  double m_loopSpeedFactor{0};
++  std::chrono::microseconds m_lastFrameUs{std::chrono::microseconds::zero()};
+   CEvent m_sleepEvent;
+ };
+ } // namespace RETRO
diff --git a/projects/Rockchip/devices/RK322X/patches/kodi/kodi-100.26-shaders-disable-bt709-color-conversion.patch.disabled b/projects/Rockchip/devices/RK322X/patches/kodi/kodi-100.26-shaders-disable-bt709-color-conversion.patch.disabled
new file mode 100644
index 0000000000..80c3e41d6c
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/patches/kodi/kodi-100.26-shaders-disable-bt709-color-conversion.patch.disabled
@@ -0,0 +1,40 @@
+diff -rupN a/system/shaders/GLES/2.0/gles_yuv2rgb_basic.frag b/system/shaders/GLES/2.0/gles_yuv2rgb_basic.frag
+--- a/system/shaders/GLES/2.0/gles_yuv2rgb_basic.frag	2020-05-31 19:01:02.000000000 +0200
++++ b/system/shaders/GLES/2.0/gles_yuv2rgb_basic.frag	2020-06-22 09:25:42.005994335 +0200
+@@ -61,6 +61,7 @@ void main()
+   rgb = m_yuvmat * yuv;
+   rgb.a = m_alpha;
+
++/*
+ #if defined(XBMC_COL_CONVERSION)
+   rgb.rgb = pow(max(vec3(0), rgb.rgb), vec3(m_gammaSrc));
+   rgb.rgb = max(vec3(0), m_primMat * rgb.rgb);
+@@ -72,7 +73,7 @@ void main()
+ #endif
+
+ #endif
+-
++*/
+   gl_FragColor = rgb;
+ }
+
+diff -rupN a/system/shaders/GLES/2.0/gles_yuv2rgb_bob.frag b/system/shaders/GLES/2.0/gles_yuv2rgb_bob.frag
+--- a/system/shaders/GLES/2.0/gles_yuv2rgb_bob.frag	2020-05-31 19:01:02.000000000 +0200
++++ b/system/shaders/GLES/2.0/gles_yuv2rgb_bob.frag	2020-06-22 09:25:56.596994279 +0200
+@@ -81,7 +81,7 @@ void main()
+   rgbBelow.a = m_alpha;
+
+   rgb = mix(rgb, rgbBelow, 0.5);
+-
++/*
+ #if defined(XBMC_COL_CONVERSION)
+   rgb.rgb = pow(max(vec3(0), rgb.rgb), vec3(m_gammaSrc));
+   rgb.rgb = max(vec3(0), m_primMat * rgb.rgb);
+@@ -93,6 +93,6 @@ void main()
+ #endif
+
+ #endif
+-
++*/
+   gl_FragColor = rgb;
+ }
diff --git a/projects/Rockchip/devices/RK322X/patches/kodi/kodi-100.28-estuary-disable-clear.patch.disabled b/projects/Rockchip/devices/RK322X/patches/kodi/kodi-100.28-estuary-disable-clear.patch.disabled
new file mode 100644
index 0000000000..48a118420c
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/patches/kodi/kodi-100.28-estuary-disable-clear.patch.disabled
@@ -0,0 +1,18 @@
+diff -ruPN xbmc-20.1-Nexus/addons/skin.estuary/xml/Includes.xml xbmc-20.1-new/addons/skin.estuary/xml/Includes.xml
+--- xbmc-20.1-Nexus/addons/skin.estuary/xml/Includes.xml	2023-03-11 23:16:38.000000000 +0100
++++ xbmc-20.1-new/addons/skin.estuary/xml/Includes.xml	2023-03-22 15:13:02.403028397 +0100
+@@ -1131,12 +1131,12 @@
+			<aspectratio>scale</aspectratio>
+			<texture colordiffuse="primary_background">special://skin/extras/backgrounds/primary.jpg</texture>
+		</control>
+-		<control type="image">
++		<!--control type="image">
+			<depth>DepthBackground</depth>
+			<include>FullScreenDimensions</include>
+			<aspectratio>scale</aspectratio>
+			<texture colordiffuse="secondary_background" fallback="special://skin/extras/backgrounds/pattern1.jpg">$INFO[Skin.String(background_overlay),special://skin/extras/backgrounds/pattern,.jpg]</texture>
+-		</control>
++		</control-->
+	</include>
+	<include name="DefaultBackground">
+		<definition>
diff --git a/projects/Rockchip/devices/RK322X/patches/kodi/kodi-900.01-hard-gui-limit-size.patch b/projects/Rockchip/devices/RK322X/patches/kodi/kodi-900.01-hard-gui-limit-size.patch
new file mode 100644
index 0000000000..7cd85adf2f
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/patches/kodi/kodi-900.01-hard-gui-limit-size.patch
@@ -0,0 +1,22 @@
+diff -ruPN xbmc-6c9991b8615b04c43b80f16e4335881f4fa06a5e/xbmc/windowing/gbm/drm/DRMUtils.cpp xbmc-new/xbmc/windowing/gbm/drm/DRMUtils.cpp
+--- xbmc-6c9991b8615b04c43b80f16e4335881f4fa06a5e/xbmc/windowing/gbm/drm/DRMUtils.cpp	2023-08-29 08:25:43.000000000 +0200
++++ xbmc-new/xbmc/windowing/gbm/drm/DRMUtils.cpp	2023-09-11 17:16:35.205087250 +0200
+@@ -648,14 +648,13 @@
+
+   int limit = CServiceBroker::GetSettingsComponent()->GetSettings()->GetInt(
+       SETTING_VIDEOSCREEN_LIMITGUISIZE);
+-  if (limit > 0 && res.iScreenWidth > 1920 && res.iScreenHeight > 1080)
++  if (limit && limit == 1) {
++	res.iWidth = 1280;
++        res.iHeight = 720;
++  } else if (limit && res.iScreenWidth > 1920 && res.iScreenHeight > 1080)
+   {
+     switch (limit)
+     {
+-      case 1: // 720p
+-        res.iWidth = 1280;
+-        res.iHeight = 720;
+-        break;
+       case 2: // 1080p / 720p (>30hz)
+         res.iWidth = mode->vrefresh > 30 ? 1280 : 1920;
+         res.iHeight = mode->vrefresh > 30 ? 720 : 1080;
diff --git a/projects/Rockchip/devices/RK322X/patches/linux/default/linux-1000-rockchip-wip.patch b/projects/Rockchip/devices/RK322X/patches/linux/default/linux-1000-rockchip-wip.patch
new file mode 100644
index 0000000000..f4d0844d39
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/patches/linux/default/linux-1000-rockchip-wip.patch
@@ -0,0 +1,803 @@
+From 4707a7fe2103b7600b2ca6097ce9d12bda37d4cf Mon Sep 17 00:00:00 2001
+From: Finley Xiao <finley.xiao@rock-chips.com>
+Date: Thu, 22 Jun 2017 20:22:25 +0800
+Subject: [PATCH] clk: rockchip: rk3228: fix some PLL_NUX_CLKs' gates
+
+Some PLL_NUX_CLKs' gates is actually behind muxs according to latest TRM,
+so move the gates to composite clocks and amend their parent clocks.
+
+Change-Id: Ib6043caa61e9df0473f2d0bdc756850968bb2a55
+Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
+---
+ drivers/clk/rockchip/clk-rk3228.c | 49 ++++++++++---------------------
+ 1 file changed, 15 insertions(+), 34 deletions(-)
+
+diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c
+index c1ef00247e26..6da33172c6ba 100644
+--- a/drivers/clk/rockchip/clk-rk3228.c
++++ b/drivers/clk/rockchip/clk-rk3228.c
+@@ -134,24 +134,22 @@ static const struct rockchip_cpuclk_reg_data rk3228_cpuclk_data = {
+
+ PNAME(mux_pll_p)		= { "clk_24m", "xin24m" };
+
+-PNAME(mux_ddrphy_p)		= { "dpll_ddr", "gpll_ddr", "apll_ddr" };
++PNAME(mux_ddrphy_p)		= { "dpll", "gpll", "apll" };
+ PNAME(mux_armclk_p)		= { "apll_core", "gpll_core", "dpll_core" };
+ PNAME(mux_usb480m_phy_p)	= { "usb480m_phy0", "usb480m_phy1" };
+ PNAME(mux_usb480m_p)		= { "usb480m_phy", "xin24m" };
+ PNAME(mux_hdmiphy_p)		= { "hdmiphy_phy", "xin24m" };
+-PNAME(mux_aclk_cpu_src_p)	= { "cpll_aclk_cpu", "gpll_aclk_cpu", "hdmiphy_aclk_cpu" };
+
+ PNAME(mux_pll_src_4plls_p)	= { "cpll", "gpll", "hdmiphy", "usb480m" };
+ PNAME(mux_pll_src_3plls_p)	= { "cpll", "gpll", "hdmiphy" };
+ PNAME(mux_pll_src_2plls_p)	= { "cpll", "gpll" };
+ PNAME(mux_sclk_hdmi_cec_p)	= { "cpll", "gpll", "xin24m" };
+-PNAME(mux_aclk_peri_src_p)	= { "cpll_peri", "gpll_peri", "hdmiphy_peri" };
+ PNAME(mux_mmc_src_p)		= { "cpll", "gpll", "xin24m", "usb480m" };
+ PNAME(mux_pll_src_cpll_gpll_usb480m_p)	= { "cpll", "gpll", "usb480m" };
+
+ PNAME(mux_sclk_rga_p)		= { "gpll", "cpll", "sclk_rga_src" };
+
+-PNAME(mux_sclk_vop_src_p)	= { "gpll_vop", "cpll_vop" };
++PNAME(mux_sclk_vop_src_p)	= { "gpll", "cpll" };
+ PNAME(mux_dclk_vop_p)		= { "hdmiphy", "sclk_vop_pre" };
+
+ PNAME(mux_i2s0_p)		= { "i2s0_src", "i2s0_frac", "ext_i2s", "xin12m" };
+@@ -220,27 +218,23 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
+			RK2928_CLKSEL_CON(4), 8, 5, DFLAGS),
+
+	/* PD_DDR */
+-	GATE(0, "apll_ddr", "apll", CLK_IGNORE_UNUSED,
++	COMPOSITE(0, "clk_ddrphy_src", mux_ddrphy_p, CLK_IGNORE_UNUSED,
++			RK2928_CLKSEL_CON(26), 8, 2, MFLAGS, 0, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
+			RK2928_CLKGATE_CON(0), 2, GFLAGS),
+-	GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
+-			RK2928_CLKGATE_CON(0), 2, GFLAGS),
+-	GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
+-			RK2928_CLKGATE_CON(0), 2, GFLAGS),
+-	COMPOSITE(0, "ddrphy4x", mux_ddrphy_p, CLK_IGNORE_UNUSED,
+-			RK2928_CLKSEL_CON(26), 8, 2, MFLAGS, 0, 3, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
++	GATE(0, "ddrphy4x", "clk_ddrphy_src", CLK_IGNORE_UNUSED,
+			RK2928_CLKGATE_CON(7), 1, GFLAGS),
+-	GATE(0, "ddrc", "ddrphy_pre", CLK_IGNORE_UNUSED,
++	FACTOR_GATE(0, "ddrc", "clk_ddrphy_src", CLK_IGNORE_UNUSED, 1, 4,
+			RK2928_CLKGATE_CON(8), 5, GFLAGS),
+-	FACTOR_GATE(0, "ddrphy", "ddrphy4x", CLK_IGNORE_UNUSED, 1, 4,
++	FACTOR_GATE(0, "ddrphy", "clk_ddrphy_src", CLK_IGNORE_UNUSED, 1, 4,
+			RK2928_CLKGATE_CON(7), 0, GFLAGS),
+
+	/* PD_CORE */
+-	GATE(0, "dpll_core", "dpll", CLK_IGNORE_UNUSED,
+-			RK2928_CLKGATE_CON(0), 6, GFLAGS),
+	GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED,
+			RK2928_CLKGATE_CON(0), 6, GFLAGS),
+	GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED,
+			RK2928_CLKGATE_CON(0), 6, GFLAGS),
++	GATE(0, "dpll_core", "dpll", CLK_IGNORE_UNUSED,
++			RK2928_CLKGATE_CON(0), 6, GFLAGS),
+	COMPOSITE_NOMUX(0, "pclk_dbg", "armclk", CLK_IGNORE_UNUSED,
+			RK2928_CLKSEL_CON(1), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
+			RK2928_CLKGATE_CON(4), 1, GFLAGS),
+@@ -257,14 +251,9 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
+			RK2928_MISC_CON, 15, 1, MFLAGS),
+
+	/* PD_BUS */
+-	GATE(0, "hdmiphy_aclk_cpu", "hdmiphy", CLK_IGNORE_UNUSED,
++	COMPOSITE(0, "aclk_cpu_src", mux_pll_src_3plls_p, 0,
++			RK2928_CLKSEL_CON(0), 13, 2, MFLAGS, 8, 5, DFLAGS,
+			RK2928_CLKGATE_CON(0), 1, GFLAGS),
+-	GATE(0, "gpll_aclk_cpu", "gpll", CLK_IGNORE_UNUSED,
+-			RK2928_CLKGATE_CON(0), 1, GFLAGS),
+-	GATE(0, "cpll_aclk_cpu", "cpll", CLK_IGNORE_UNUSED,
+-			RK2928_CLKGATE_CON(0), 1, GFLAGS),
+-	COMPOSITE_NOGATE(0, "aclk_cpu_src", mux_aclk_cpu_src_p, 0,
+-			RK2928_CLKSEL_CON(0), 13, 2, MFLAGS, 8, 5, DFLAGS),
+	GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_src", 0,
+			RK2928_CLKGATE_CON(6), 0, GFLAGS),
+	COMPOSITE_NOMUX(HCLK_CPU, "hclk_cpu", "aclk_cpu_src", 0,
+@@ -337,14 +326,9 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
+			RK2928_CLKGATE_CON(3), 8, GFLAGS),
+
+	/* PD_PERI */
+-	GATE(0, "cpll_peri", "cpll", CLK_IGNORE_UNUSED,
+-			RK2928_CLKGATE_CON(2), 0, GFLAGS),
+-	GATE(0, "gpll_peri", "gpll", CLK_IGNORE_UNUSED,
++	COMPOSITE(0, "aclk_peri_src", mux_pll_src_3plls_p, 0,
++			RK2928_CLKSEL_CON(10), 10, 2, MFLAGS, 0, 5, DFLAGS,
+			RK2928_CLKGATE_CON(2), 0, GFLAGS),
+-	GATE(0, "hdmiphy_peri", "hdmiphy", CLK_IGNORE_UNUSED,
+-			RK2928_CLKGATE_CON(2), 0, GFLAGS),
+-	COMPOSITE_NOGATE(0, "aclk_peri_src", mux_aclk_peri_src_p, 0,
+-			RK2928_CLKSEL_CON(10), 10, 2, MFLAGS, 0, 5, DFLAGS),
+	COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_src", 0,
+			RK2928_CLKSEL_CON(10), 12, 3, DFLAGS,
+			RK2928_CLKGATE_CON(5), 2, GFLAGS),
+@@ -402,12 +386,9 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
+	 * Clock-Architecture Diagram 2
+	 */
+
+-	GATE(0, "gpll_vop", "gpll", 0,
+-			RK2928_CLKGATE_CON(3), 1, GFLAGS),
+-	GATE(0, "cpll_vop", "cpll", 0,
++	COMPOSITE_NODIV(0, "sclk_vop_src", mux_sclk_vop_src_p, 0,
++			RK2928_CLKSEL_CON(27), 0, 1, MFLAGS,
+			RK2928_CLKGATE_CON(3), 1, GFLAGS),
+-	MUX(0, "sclk_vop_src", mux_sclk_vop_src_p, 0,
+-			RK2928_CLKSEL_CON(27), 0, 1, MFLAGS),
+	DIV(DCLK_HDMI_PHY, "dclk_hdmiphy", "sclk_vop_src", 0,
+			RK2928_CLKSEL_CON(29), 0, 3, DFLAGS),
+	DIV(0, "sclk_vop_pre", "sclk_vop_src", 0,
+
+From d575c876e7f19e1699471d88edfe8d1874f6dd21 Mon Sep 17 00:00:00 2001
+From: Finley Xiao <finley.xiao@rock-chips.com>
+Date: Sun, 18 Mar 2018 21:41:43 +0800
+Subject: [PATCH] clk: rockchip: rk3228: Fix sclk_wifi div_width
+
+Change-Id: I8e216249fbd588ce55660eba9911fc59aedc920d
+Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
+---
+ drivers/clk/rockchip/clk-rk3228.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c
+index 6da33172c6ba..d59e619425b6 100644
+--- a/drivers/clk/rockchip/clk-rk3228.c
++++ b/drivers/clk/rockchip/clk-rk3228.c
+@@ -363,7 +363,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
+			RK2928_CLKGATE_CON(10), 12, GFLAGS),
+
+	COMPOSITE(SCLK_WIFI, "sclk_wifi", mux_pll_src_cpll_gpll_usb480m_p, 0,
+-			RK2928_CLKSEL_CON(23), 5, 2, MFLAGS, 0, 6, DFLAGS,
++			RK2928_CLKSEL_CON(23), 5, 2, MFLAGS, 0, 5, DFLAGS,
+			RK2928_CLKGATE_CON(2), 15, GFLAGS),
+
+	COMPOSITE(SCLK_SDMMC, "sclk_sdmmc", mux_mmc_src_p, 0,
+
+From 13db1588f0807f2d0569a45b93d6597280e105f6 Mon Sep 17 00:00:00 2001
+From: Chen Lei <lei.chen@rock-chips.com>
+Date: Tue, 25 Dec 2018 18:29:04 +0800
+Subject: [PATCH] clk: rockchip: rk322x: fix wrong mmc phase shift for rk3228
+
+mmc sample shift should be 1 for rk3228, or it will fail
+if we enable mmc tuning for rk3228.
+
+Change-Id: I301c2a7d33de8d519d7c288aef03a82531016373
+Signed-off-by: Chen Lei <lei.chen@rock-chips.com>
+---
+ drivers/clk/rockchip/clk-rk3228.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c
+index d59e619425b6..9c5ad7c71143 100644
+--- a/drivers/clk/rockchip/clk-rk3228.c
++++ b/drivers/clk/rockchip/clk-rk3228.c
+@@ -620,13 +620,13 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
+
+	/* PD_MMC */
+	MMC(SCLK_SDMMC_DRV,    "sdmmc_drv",    "sclk_sdmmc", RK3228_SDMMC_CON0, 1),
+-	MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RK3228_SDMMC_CON1, 0),
++	MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RK3228_SDMMC_CON1, 1),
+
+	MMC(SCLK_SDIO_DRV,     "sdio_drv",     "sclk_sdio",  RK3228_SDIO_CON0,  1),
+-	MMC(SCLK_SDIO_SAMPLE,  "sdio_sample",  "sclk_sdio",  RK3228_SDIO_CON1,  0),
++	MMC(SCLK_SDIO_SAMPLE,  "sdio_sample",  "sclk_sdio",  RK3228_SDIO_CON1,  1),
+
+	MMC(SCLK_EMMC_DRV,     "emmc_drv",     "sclk_emmc",  RK3228_EMMC_CON0,  1),
+-	MMC(SCLK_EMMC_SAMPLE,  "emmc_sample",  "sclk_emmc",  RK3228_EMMC_CON1,  0),
++	MMC(SCLK_EMMC_SAMPLE,  "emmc_sample",  "sclk_emmc",  RK3228_EMMC_CON1,  1),
+ };
+
+ static const char *const rk3228_critical_clocks[] __initconst = {
+
+From 8b9b8802556c4f7ce09699a4a85e19143de43c44 Mon Sep 17 00:00:00 2001
+From: Alex Bee <knaerzche@gmail.com>
+Date: Mon, 14 Dec 2020 21:05:15 +0100
+Subject: [PATCH] clk: rockchip: add *_vio_h2p to RK3228's critical clocks
+
+These are required in order to read the HDMI edid and must not
+get disabled in order to successfully do so.
+
+Signed-off-by: Alex Bee <knaerzche@gmail.com>
+---
+ drivers/clk/rockchip/clk-rk3228.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c
+index 9c5ad7c71143..4b2aca6b1f11 100644
+--- a/drivers/clk/rockchip/clk-rk3228.c
++++ b/drivers/clk/rockchip/clk-rk3228.c
+@@ -641,6 +641,7 @@ static const char *const rk3228_critical_clocks[] __initconst = {
+	"aclk_vop_noc",
+	"aclk_hdcp_noc",
+	"hclk_vio_ahb_arbi",
++	"hclk_vio_h2p",
+	"hclk_vio_noc",
+	"hclk_vop_noc",
+	"hclk_host0_arb",
+@@ -658,6 +659,7 @@ static const char *const rk3228_critical_clocks[] __initconst = {
+	"pclk_ddrphy",
+	"pclk_acodecphy",
+	"pclk_phy_noc",
++	"pclk_vio_h2p",
+	"aclk_vpu_noc",
+	"aclk_rkvdec_noc",
+	"hclk_vpu_noc",
+
+From 3fc147d54b06e6451775465e35de17a6126377c2 Mon Sep 17 00:00:00 2001
+From: Alex Bee <knaerzche@gmail.com>
+Date: Sun, 16 Aug 2020 17:07:35 +0200
+Subject: [PATCH] clk: rockchip add aclk_rkvdec and hclk_rkvdec to RK3228
+ critical clocks
+
+To be prevented from being disabled at any time add aclk_rkvdec and hclk_rkvdec
+to RK3228 critical clocks
+---
+ drivers/clk/rockchip/clk-rk3228.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c
+index 4b2aca6b1f11..2ac006e99c03 100644
+--- a/drivers/clk/rockchip/clk-rk3228.c
++++ b/drivers/clk/rockchip/clk-rk3228.c
+@@ -662,8 +662,10 @@ static const char *const rk3228_critical_clocks[] __initconst = {
+	"pclk_vio_h2p",
+	"aclk_vpu_noc",
+	"aclk_rkvdec_noc",
++	"aclk_rkvdec",
+	"hclk_vpu_noc",
+	"hclk_rkvdec_noc",
++	"hclk_rkvdec",
+ };
+
+ static void __init rk3228_clk_init(struct device_node *np)
+
+From 8384abedb84b4f9c8648a92108de94b4b8d188a6 Mon Sep 17 00:00:00 2001
+From: Alex Bee <knaerzche@gmail.com>
+Date: Fri, 24 Apr 2020 11:42:58 +0200
+Subject: [PATCH] soc: rockchip: Support powerdomains which don't need /
+ support to be switched on / off
+
+Taken from https://github.com/rockchip-linux/kernel/commit/5be2cb19cf8e678655b59ec70c6a5f66f08d9418
+---
+ drivers/genpd/rockchip/pm-domains.c | 23 +++++++++++++++++++++++
+ 1 file changed, 23 insertions(+)
+
+diff --git a/drivers/genpd/rockchip/pm-domains.c b/drivers/genpd/rockchip/pm-domains.c
+index 54eb6cfc5d5b..c6b33f7c43df 100644
+--- a/drivers/pmdomain/rockchip/pm-domains.c
++++ b/drivers/pmdomain/rockchip/pm-domains.c
+@@ -71,6 +71,7 @@ struct rockchip_pm_domain {
+	struct regmap **qos_regmap;
+	u32 *qos_save_regs[MAX_QOS_REGS_NUM];
+	int num_clks;
++	bool is_ignore_pwr;
+	struct clk_bulk_data *clks;
+ };
+
+@@ -330,6 +331,9 @@ static int rockchip_pd_power_on(struct generic_pm_domain *domain)
+ {
+	struct rockchip_pm_domain *pd = to_rockchip_pd(domain);
+
++	if (pd->is_ignore_pwr)
++		return 0;
++
+	ret = rockchip_pd_regulator_enable(pd);
+	if (ret) {
+		dev_err(pd->pmu->dev, "Failed to enable supply: %d\n", ret);
+@@ -337,6 +341,9 @@ static int rockchip_pd_power_off(struct generic_pm_domain *domain)
+ {
+	struct rockchip_pm_domain *pd = to_rockchip_pd(domain);
+
++	if (pd->is_ignore_pwr)
++		return 0;
++
+	ret = rockchip_pd_power(pd, false);
+	if (ret)
+		return ret;
+@@ -416,6 +423,9 @@ static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu,
+	pd->info = pd_info;
+	pd->pmu = pmu;
+
++	if (!pd_info->pwr_mask)
++		pd->is_ignore_pwr = true;
++
+	pd->num_clks = of_clk_get_parent_count(node);
+	if (pd->num_clks > 0) {
+		pd->clks = devm_kcalloc(pmu->dev, pd->num_clks,
+@@ -566,6 +576,7 @@ static int rockchip_pm_add_subdomain(struct rockchip_pmu *pmu,
+ {
+	struct device_node *np;
+	struct generic_pm_domain *child_domain, *parent_domain;
++	struct rockchip_pm_domain *child_pd, *parent_pd;
+	int error;
+
+	for_each_child_of_node(parent, np) {
+@@ -606,6 +617,18 @@ static int rockchip_pm_add_subdomain(struct rockchip_pmu *pmu,
+				parent_domain->name, child_domain->name);
+		}
+
++		/*
++		 * If child_pd doesn't do idle request or power on/off,
++		 * parent_pd may fail to do power on/off, so if parent_pd
++		 * need to power on/off, child_pd can't ignore to do idle
++		 * request and power on/off.
++		 */
++		child_pd = to_rockchip_pd(child_domain);
++		parent_pd = to_rockchip_pd(parent_domain);
++		if (!parent_pd->is_ignore_pwr)
++			child_pd->is_ignore_pwr = false;
++
++
+		rockchip_pm_add_subdomain(pmu, np);
+	}
+
+
+From 14c607b588c49705ac0486d63590876089b41a20 Mon Sep 17 00:00:00 2001
+From: Alex Bee <knaerzche@gmail.com>
+Date: Fri, 24 Apr 2020 09:08:44 +0200
+Subject: [PATCH] phy: rockchip: hdmi: readout hdmi phy flag for RK3228 HDMI
+ phys
+
+Some RK3228 HDMI phys only get a stable pll on frequencies higher 33,75 MHz.
+This is defined in a flag in efuse of those devices.
+---
+ arch/arm/boot/dts/rockchip/rk322x.dtsi                 |  6 +++
+ drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 38 ++++++++++++++++++-
+ 2 files changed, 42 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/boot/dts/rockchip/rk322x.dtsi b/arch/arm/boot/dts/rockchip/rk322x.dtsi
+index 48e6e8d44a1a..a5f1d1a004d4 100644
+--- a/arch/arm/boot/dts/rockchip/rk322x.dtsi
++++ b/arch/arm/boot/dts/rockchip/rk322x.dtsi
+@@ -317,6 +317,10 @@ efuse_id: id@7 {
+		cpu_leakage: cpu_leakage@17 {
+			reg = <0x17 0x1>;
+		};
++		hdmi_phy_flag: hdmi-phy-flag@1d {
++			reg = <0x1d 0x1>;
++			bits = <1 1>;
++		};
+	};
+
+	i2c0: i2c@11050000 {
+@@ -536,6 +540,8 @@ hdmi_phy: hdmi-phy@12030000 {
+		clock-names = "sysclk", "refoclk", "refpclk";
+		#clock-cells = <0>;
+		clock-output-names = "hdmiphy_phy";
++		nvmem-cells = <&hdmi_phy_flag>;
++		nvmem-cell-names = "hdmi-phy-flag";
+		#phy-cells = <0>;
+		status = "disabled";
+	};
+diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
+index bb8bdf5e3301..0c7a97352714 100644
+--- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
++++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
+@@ -237,6 +237,9 @@ struct inno_hdmi_phy {
+	struct clk *refoclk;
+	struct clk *refpclk;
+
++	/* phy_flag flag */
++	bool phy_flag;
++
+	/* platform data */
+	const struct inno_hdmi_phy_drv_data *plat_data;
+	int chip_version;
+@@ -347,6 +350,7 @@ static const struct pre_pll_config pre_pll_cfg_table[] = {
+ static const struct post_pll_config post_pll_cfg_table[] = {
+	{33750000,  1, 40, 8, 1},
+	{33750000,  1, 80, 8, 2},
++	{33750000,  1, 10, 2, 4},
+	{74250000,  1, 40, 8, 1},
+	{74250000, 18, 80, 8, 2},
+	{148500000, 2, 40, 4, 3},
+@@ -497,8 +501,11 @@ static int inno_hdmi_phy_power_on(struct phy *phy)
+		return -EINVAL;
+
+	for (; cfg->tmdsclock != 0; cfg++)
+-		if (tmdsclock <= cfg->tmdsclock &&
+-		    cfg->version & inno->chip_version)
++		if (((!inno->phy_flag || tmdsclock > 33750000)
++		     && tmdsclock <= cfg->tmdsclock
++		     && cfg->version & inno->chip_version) ||
++		    (inno->phy_flag && tmdsclock <= 33750000
++		     && cfg->version & 4))
+			break;
+
+	for (; phy_cfg->tmdsclock != 0; phy_cfg++)
+@@ -909,6 +916,10 @@ static int inno_hdmi_phy_clk_register(struct inno_hdmi_phy *inno)
+
+ static int inno_hdmi_phy_rk3228_init(struct inno_hdmi_phy *inno)
+ {
++	struct nvmem_cell *cell;
++	unsigned char *efuse_buf;
++	size_t len;
++
+	/*
+	 * Use phy internal register control
+	 * rxsense/poweron/pllpd/pdataen signal.
+@@ -923,7 +934,28 @@ static int inno_hdmi_phy_rk3228_init(struct inno_hdmi_phy *inno)
+	inno_update_bits(inno, 0xaa, RK3228_POST_PLL_CTRL_MANUAL,
+			 RK3228_POST_PLL_CTRL_MANUAL);
+
++
+	inno->chip_version = 1;
++	inno->phy_flag = false;
++
++	cell = nvmem_cell_get(inno->dev, "hdmi-phy-flag");
++	if (IS_ERR(cell)) {
++		if (PTR_ERR(cell) == -EPROBE_DEFER)
++			return -EPROBE_DEFER;
++
++		return 0;
++	}
++
++	efuse_buf = nvmem_cell_read(cell, &len);
++	nvmem_cell_put(cell);
++
++	if (IS_ERR(efuse_buf))
++		return 0;
++	if (len == 1)
++		inno->phy_flag = (efuse_buf[0] & BIT(1)) ? true : false;
++	kfree(efuse_buf);
++
++	dev_info(inno->dev, "phy_flag is: %d\n", inno->phy_flag);
+
+	return 0;
+ }
+@@ -1023,6 +1055,8 @@ static int inno_hdmi_phy_rk3328_init(struct inno_hdmi_phy *inno)
+
+	/* try to read the chip-version */
+	inno->chip_version = 1;
++	inno->phy_flag = false;
++
+	cell = nvmem_cell_get(inno->dev, "cpu-version");
+	if (IS_ERR(cell)) {
+		if (PTR_ERR(cell) == -EPROBE_DEFER)
+
+From 01d16d33ee32f2e2de85cbc8a0a399527c2121ad Mon Sep 17 00:00:00 2001
+From: Alex Bee <knaerzche@gmail.com>
+Date: Tue, 26 May 2020 14:41:39 +0200
+Subject: [PATCH] usb: dwc2: QUIRKS: rockchip host only controller needs longer
+ msleep to initialize
+
+---
+ drivers/usb/dwc2/core.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/usb/dwc2/core.c b/drivers/usb/dwc2/core.c
+index fec17a2d2447..eb55c64f63be 100644
+--- a/drivers/usb/dwc2/core.c
++++ b/drivers/usb/dwc2/core.c
+@@ -663,7 +663,7 @@ void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg)
+		 * platforms on their host-only dwc2.
+		 */
+		if (!dwc2_hw_is_otg(hsotg))
+-			msleep(50);
++			msleep(200);
+
+		break;
+	case USB_DR_MODE_PERIPHERAL:
+
+From 713a88dec72631a71bf736e120236f60d06f3989 Mon Sep 17 00:00:00 2001
+From: Alex Bee <knaerzche@gmail.com>
+Date: Sun, 16 Aug 2020 18:51:38 +0200
+Subject: [PATCH] ARM: dts: rockchip add operating-points, power-domain for
+ RK322Xs GPU
+
+This adds the operating-points table and the power-domain and the respective
+qos registers for RK322xs GPU.
+While at this it also adds the GPU to be a cooling cell.
+---
+ arch/arm/boot/dts/rockchip/rk322x.dtsi | 27 ++++++++++++++++++++++++++-
+ 1 file changed, 26 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm/boot/dts/rockchip/rk322x.dtsi b/arch/arm/boot/dts/rockchip/rk322x.dtsi
+index a5f1d1a004d4..dedf84af9e51 100644
+--- a/arch/arm/boot/dts/rockchip/rk322x.dtsi
++++ b/arch/arm/boot/dts/rockchip/rk322x.dtsi
+@@ -510,6 +510,11 @@ map1 {
+						<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+						<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
++				map2 {
++					trip = <&cpu_alert1>;
++					cooling-device =
++						<&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
++				};
+			};
+		};
+	};
+@@ -564,7 +569,28 @@ gpu: gpu@20000000 {
+		clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
+		clock-names = "bus", "core";
+		resets = <&cru SRST_GPU_A>;
+-		status = "disabled";
++		operating-points-v2 = <&gpu_opp_table>;
++		#cooling-cells = <2>; /* min followed by max */
++	};
++
++	gpu_opp_table: opp-table2 {
++		compatible = "operating-points-v2";
++
++		opp-216000000 {
++			opp-hz = /bits/ 64 <216000000>;
++			opp-microvolt = <1100000 1100000 1150000>;
++		};
++
++		opp-408000000 {
++			opp-hz = /bits/ 64 <408000000>;
++			opp-microvolt = <1100000 1100000 1150000>;
++		};
++
++		opp-504000000 {
++			opp-hz = /bits/ 64 <504000000>;
++			opp-microvolt = <1100000 1100000 1150000>;
++			status="disabled";
++		};
+	};
+
+	vpu_mmu: iommu@20020800 {
+
+From 4526da0caf4ecc56cc6e6b8602715dbe839c3eac Mon Sep 17 00:00:00 2001
+From: Alex Bee <knaerzche@gmail.com>
+Date: Sun, 16 Aug 2020 19:44:42 +0200
+Subject: [PATCH] ARM: dts: rockchip: add ethernet0 alias
+
+Add ethernet0 alias for gmac. This will, for example, be used
+by u-boot to inject a "local-mac-address" in the devicetree.
+---
+ arch/arm/boot/dts/rockchip/rk322x.dtsi | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm/boot/dts/rockchip/rk322x.dtsi b/arch/arm/boot/dts/rockchip/rk322x.dtsi
+index dedf84af9e51..3c20ee3a7837 100644
+--- a/arch/arm/boot/dts/rockchip/rk322x.dtsi
++++ b/arch/arm/boot/dts/rockchip/rk322x.dtsi
+@@ -14,6 +14,7 @@ / {
+	interrupt-parent = <&gic>;
+
+	aliases {
++		ethernet0 = &gmac;
+		gpio0 = &gpio0;
+		gpio1 = &gpio1;
+		gpio2 = &gpio2;
+
+From 3d6864134434144078395786338b194704a5a41a Mon Sep 17 00:00:00 2001
+From: Alex Bee <knaerzche@gmail.com>
+Date: Sun, 16 Aug 2020 20:00:01 +0200
+Subject: [PATCH] ARM: dts: rockchip: add hdmi simple-audio-card for RK322x
+
+Add "simple-audio-card" definition for hdmi-sound. While at
+that also add the missing #sound-dai-cells for i2s, spdif and hdmi
+nodes.
+---
+ arch/arm/boot/dts/rockchip/rk322x.dtsi | 20 ++++++++++++++++++++
+ 1 file changed, 20 insertions(+)
+
+diff --git a/arch/arm/boot/dts/rockchip/rk322x.dtsi b/arch/arm/boot/dts/rockchip/rk322x.dtsi
+index 3c20ee3a7837..d10ca04c20d6 100644
+--- a/arch/arm/boot/dts/rockchip/rk322x.dtsi
++++ b/arch/arm/boot/dts/rockchip/rk322x.dtsi
+@@ -123,6 +123,22 @@ arm-pmu {
+		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+	};
+
++	hdmi_sound: hdmi-sound {
++		compatible = "simple-audio-card";
++		simple-audio-card,name = "HDMI";
++		simple-audio-card,format = "i2s";
++		simple-audio-card,mclk-fs = <256>;
++		status = "disabled";
++
++		simple-audio-card,cpu {
++			sound-dai = <&i2s0>;
++		};
++
++		simple-audio-card,codec {
++			sound-dai = <&hdmi>;
++		};
++	};
++
+	psci {
+		compatible = "arm,psci-1.0", "arm,psci-0.2";
+		method = "smc";
+@@ -160,6 +176,7 @@ i2s1: i2s1@100b0000 {
+		dma-names = "tx", "rx";
+		pinctrl-names = "default";
+		pinctrl-0 = <&i2s1_bus>;
++		#sound-dai-cells = <0>;
+		status = "disabled";
+	};
+
+@@ -171,6 +188,7 @@ i2s0: i2s0@100c0000 {
+		clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
+		dmas = <&pdma 11>, <&pdma 12>;
+		dma-names = "tx", "rx";
++		#sound-dai-cells = <0>;
+		status = "disabled";
+	};
+
+@@ -184,6 +202,7 @@ spdif: spdif@100d0000 {
+		dma-names = "tx";
+		pinctrl-names = "default";
+		pinctrl-0 = <&spdif_tx>;
++		#sound-dai-cells = <0>;
+		status = "disabled";
+	};
+
+@@ -685,6 +704,7 @@ hdmi: hdmi@200a0000 {
+		phys = <&hdmi_phy>;
+		phy-names = "hdmi";
+		rockchip,grf = <&grf>;
++		#sound-dai-cells = <0>;
+		status = "disabled";
+
+		ports {
+
+From f917eada6b9f431a797e3bfab7cd06dbd9dfe981 Mon Sep 17 00:00:00 2001
+From: Alex Bee <knaerzche@gmail.com>
+Date: Sun, 16 Aug 2020 21:16:11 +0200
+Subject: [PATCH] ARM: dts: rockchip: add uart1-1 pins for RK322x
+
+Add uart uart1-1 pins.
+While at this also correct the uart2 default pinctrl, which is uart21_xfer.
+---
+ arch/arm/boot/dts/rockchip/rk322x.dtsi | 19 ++++++++++++++++++-
+ 1 file changed, 18 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm/boot/dts/rockchip/rk322x.dtsi b/arch/arm/boot/dts/rockchip/rk322x.dtsi
+index d10ca04c20d6..f675551391c3 100644
+--- a/arch/arm/boot/dts/rockchip/rk322x.dtsi
++++ b/arch/arm/boot/dts/rockchip/rk322x.dtsi
+@@ -316,7 +316,7 @@ uart2: serial@11030000 {
+		clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
+		clock-names = "baudclk", "apb_pclk";
+		pinctrl-names = "default";
+-		pinctrl-0 = <&uart2_xfer>;
++		pinctrl-0 = <&uart21_xfer>;
+		reg-shift = <2>;
+		reg-io-width = <4>;
+		status = "disabled";
+@@ -1194,13 +1194,30 @@ uart1_xfer: uart1-xfer {
+						<1 RK_PB2 1 &pcfg_pull_none>;
+			};
+
++			uart11_xfer: uart11-xfer {
++				rockchip,pins = <3 RK_PB6 1 &pcfg_pull_up>,
++						<3 RK_PB5 1 &pcfg_pull_none>;
++			};
++
+			uart1_cts: uart1-cts {
+				rockchip,pins = <1 RK_PB0 1 &pcfg_pull_none>;
+			};
+
++			uart11_cts: uart11-cts {
++				rockchip,pins = <3 RK_PA7 1 &pcfg_pull_none>;
++			};
++
+			uart1_rts: uart1-rts {
+				rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>;
+			};
++
++			uart11_rts: uart11-rts {
++				rockchip,pins = <3 RK_PA6 1 &pcfg_pull_none>;
++			};
++
++			uart11_rts_gpio: uart11-rts-gpio {
++				rockchip,pins = <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
++			};
+		};
+
+		uart2 {
+
+From cbbb85e00a2b19c1e3e9e4d6591c481718e5fb42 Mon Sep 17 00:00:00 2001
+From: Alex Bee <knaerzche@gmail.com>
+Date: Sun, 16 Aug 2020 21:58:56 +0200
+Subject: [PATCH] ARM: dts: rockchip: align mmc* node properties with driver
+
+Add resets, max-frequency and bus-width properties where required to emmc
+,sdmmc and sdio nodes. While at that also add the sdmmc_pwr pinctrl which
+is required to get the sd-card controller to work, if it was not/wrong
+initialized by the bootloader (i.e. u-boot)
+---
+ arch/arm/boot/dts/rockchip/rk322x.dtsi | 17 ++++++++++++++---
+ 1 file changed, 14 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm/boot/dts/rockchip/rk322x.dtsi b/arch/arm/boot/dts/rockchip/rk322x.dtsi
+index f675551391c3..8e7a866e39e5 100644
+--- a/arch/arm/boot/dts/rockchip/rk322x.dtsi
++++ b/arch/arm/boot/dts/rockchip/rk322x.dtsi
+@@ -726,9 +726,13 @@ sdmmc: mmc@30000000 {
+		clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
+			 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
+		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
++		bus-width = <4>;
+		fifo-depth = <0x100>;
++		max-frequency = <150000000>;
+		pinctrl-names = "default";
+-		pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
++		pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4 &sdmmc_pwr>;
++		resets = <&cru SRST_SDMMC>;
++		reset-names = "reset";
+		status = "disabled";
+	};
+
+@@ -738,10 +742,14 @@ sdio: mmc@30010000 {
+		interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
+			 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
++		bus-width = <4>;
+		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+		fifo-depth = <0x100>;
++		max-frequency = <150000000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>;
++		resets = <&cru SRST_SDIO>;
++		reset-names = "reset";
+		status = "disabled";
+	};
+
+@@ -749,14 +757,13 @@ emmc: mmc@30020000 {
+		compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
+		reg = <0x30020000 0x4000>;
+		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+-		clock-frequency = <37500000>;
+-		max-frequency = <37500000>;
+		clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
+			 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
+		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+		bus-width = <8>;
+		rockchip,default-sample-phase = <158>;
+		fifo-depth = <0x100>;
++		max-frequency = <150000000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
+		resets = <&cru SRST_EMMC>;
+@@ -962,6 +969,10 @@ sdmmc_bus4: sdmmc-bus4 {
+						<1 RK_PC4 1 &pcfg_pull_none_drv_12ma>,
+						<1 RK_PC5 1 &pcfg_pull_none_drv_12ma>;
+			};
++
++			sdmmc_pwr: sdmmc-pwr {
++				rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
++			};
+		};
+
+		sdio {
+
+From 86ae340dabdfbc27ebdb1b43b96d59999dfa4f5a Mon Sep 17 00:00:00 2001
+From: Alex Bee <knaerzche@gmail.com>
+Date: Sun, 16 Aug 2020 23:12:25 +0200
+Subject: [PATCH] ARM: dts: rk322x: add crypto node
+
+In order to add support for RK322x's crypto HW, the node
+has been added t its dts.
+
+Signed-off-by: Alex Bee <knaerzche@gmail.com>
+---
+ arch/arm/boot/dts/rockchip/rk322x.dtsi | 11 +++++++++++
+ 1 file changed, 11 insertions(+)
+
+diff --git a/arch/arm/boot/dts/rockchip/rk322x.dtsi b/arch/arm/boot/dts/rockchip/rk322x.dtsi
+index 8e7a866e39e5..217ee6568f9e 100644
+--- a/arch/arm/boot/dts/rockchip/rk322x.dtsi
++++ b/arch/arm/boot/dts/rockchip/rk322x.dtsi
+@@ -166,6 +166,17 @@ display_subsystem: display-subsystem {
+		ports = <&vop_out>;
+	};
+
++	crypto: cypto-controller@100a0000 {
++		compatible = "rockchip,rk3288-crypto";
++		reg = <0x100a0000 0x4000>;
++		interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
++		clocks = <&cru HCLK_M_CRYPTO>, <&cru HCLK_S_CRYPTO>,
++		<&cru SCLK_CRYPTO>, <&cru ACLK_DMAC>;
++		clock-names = "aclk", "hclk", "sclk", "apb_pclk";
++		resets = <&cru SRST_CRYPTO>;
++		reset-names = "crypto-rst";
++	};
++
+	i2s1: i2s1@100b0000 {
+		compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
+		reg = <0x100b0000 0x4000>;
diff --git a/projects/Rockchip/devices/RK322X/patches/linux/default/linux-1001-drm-wip.patch b/projects/Rockchip/devices/RK322X/patches/linux/default/linux-1001-drm-wip.patch
new file mode 100644
index 0000000000..33ab4d3d42
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/patches/linux/default/linux-1001-drm-wip.patch
@@ -0,0 +1,69 @@
+From 9be348c6cade7e709be7347d336c7638bf603b46 Mon Sep 17 00:00:00 2001
+From: Alex Bee <knaerzche@gmail.com>
+Date: Sat, 15 Aug 2020 23:38:05 +0200
+Subject: [PATCH] rockchip/drm: add dsp_data_swap register for RK3188
+
+---
+ drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+index 27a04c5bc2fd..b47f036d4a2c 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
++++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+@@ -555,6 +555,7 @@ static const struct vop_common rk3188_common = {
+	.dither_up = VOP_REG(RK3188_DSP_CTRL0, 0x1, 9),
+	.dsp_lut_en = VOP_REG(RK3188_SYS_CTRL, 0x1, 28),
+	.data_blank = VOP_REG(RK3188_DSP_CTRL1, 0x1, 25),
++	.dsp_data_swap = VOP_REG(RK3188_DSP_CTRL1, 0x1f, 26),
+ };
+
+ static const struct vop_win_data rk3188_vop_win_data[] = {
+
+From 195b202dbc5abe9c65e029826a7f3e2a2d71067a Mon Sep 17 00:00:00 2001
+From: Alex Bee <knaerzche@gmail.com>
+Date: Wed, 22 Jul 2020 20:22:02 +0200
+Subject: [PATCH] rockchip/drm: add dsp_data_swap register for RK3066
+
+Signed-off-by: Alex Bee <knaerzche@gmail.com>
+---
+ drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+index b47f036d4a2c..ae4a27704ad6 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
++++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+@@ -448,6 +448,7 @@ static const struct vop_common rk3066_common = {
+	.dither_up = VOP_REG(RK3066_DSP_CTRL0, 0x1, 9),
+	.dsp_lut_en = VOP_REG(RK3066_SYS_CTRL1, 0x1, 31),
+	.data_blank = VOP_REG(RK3066_DSP_CTRL1, 0x1, 25),
++	.dsp_data_swap = VOP_REG(RK3066_DSP_CTRL1, 0x1f, 26),
+ };
+
+ static const struct vop_win_data rk3066_vop_win_data[] = {
+
+From a8d962000848a237f8e8f0de8395d4e7df2a7197 Mon Sep 17 00:00:00 2001
+From: Alex Bee <knaerzche@gmail.com>
+Date: Sun, 16 Aug 2020 23:40:24 +0200
+Subject: [PATCH] WIP: ARM: dts: rockchip add vpll clock to RK322Xs hdmi node
+
+---
+ arch/arm/boot/dts/rockchip/rk322x.dtsi | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/boot/dts/rockchip/rk322x.dtsi b/arch/arm/boot/dts/rockchip/rk322x.dtsi
+index 4bc631881c05..f98a945c68d3 100644
+--- a/arch/arm/boot/dts/rockchip/rk322x.dtsi
++++ b/arch/arm/boot/dts/rockchip/rk322x.dtsi
+@@ -766,8 +766,8 @@ hdmi: hdmi@200a0000 {
+		interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+		assigned-clocks = <&cru SCLK_HDMI_PHY>;
+		assigned-clock-parents = <&hdmi_phy>;
+-		clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>;
+-		clock-names = "iahb", "isfr", "cec";
++		clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&hdmi_phy>, <&cru SCLK_HDMI_CEC>;
++		clock-names = "iahb", "isfr", "vpll", "cec";
+		pinctrl-names = "default";
+		pinctrl-0 = <&hdmii2c_xfer &hdmi_hpd &hdmi_cec>;
+		resets = <&cru SRST_HDMI_P>;
diff --git a/projects/Rockchip/devices/RK322X/patches/linux/default/linux-1002-v4l-wip.patch b/projects/Rockchip/devices/RK322X/patches/linux/default/linux-1002-v4l-wip.patch
new file mode 100644
index 0000000000..7616794341
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/patches/linux/default/linux-1002-v4l-wip.patch
@@ -0,0 +1,36 @@
+From e9d4e43dc5a6fbcdff3be92e4ec40c7bb787a897 Mon Sep 17 00:00:00 2001
+From: Alex Bee <knaerzche@gmail.com>
+Date: Sun, 11 Oct 2020 14:48:44 +0200
+Subject: [PATCH] ARM: dts: rockchip: Add IEP node for RK322x
+
+Signed-off-by: Alex Bee <knaerzche@gmail.com>
+---
+ arch/arm/boot/dts/rockchip/rk322x.dtsi | 19 +++++++++++++++++--
+ 1 file changed, 17 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/boot/dts/rockchip/rk322x.dtsi b/arch/arm/boot/dts/rockchip/rk322x.dtsi
+index de5727e0bc94..a2012a44421d 100644
+--- a/arch/arm/boot/dts/rockchip/rk322x.dtsi
++++ b/arch/arm/boot/dts/rockchip/rk322x.dtsi
+@@ -781,6 +781,21 @@ rga: rga@20060000 {
+		power-domains = <&power RK3228_PD_VIO>;
+	};
+
++	iep: iep@20070000 {
++		compatible = "rockchip,rk3228-iep";
++		reg = <0x20070000 0x800>;
++		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
++		interrupt-names = "iep";
++		clocks = <&cru ACLK_IEP>,
++		         <&cru HCLK_IEP>;
++		clock-names = "axi", "ahb";
++		resets = <&cru SRST_IEP_A>,
++		         <&cru SRST_IEP_H>;
++		reset-names = "axi", "ahb";
++		power-domains = <&power RK3228_PD_VIO>;
++		iommus = <&iep_mmu>;
++	};
++
+	iep_mmu: iommu@20070800 {
+		compatible = "rockchip,iommu";
+		reg = <0x20070800 0x100>;
diff --git a/projects/Rockchip/devices/RK322X/patches/linux/default/linux-4001-fix-ddr-clock-gate-add-SIP-v2-calls.patch b/projects/Rockchip/devices/RK322X/patches/linux/default/linux-4001-fix-ddr-clock-gate-add-SIP-v2-calls.patch
new file mode 100644
index 0000000000..f093fc5ac2
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/patches/linux/default/linux-4001-fix-ddr-clock-gate-add-SIP-v2-calls.patch
@@ -0,0 +1,233 @@
+From e039790fb29227f646e91e6d7ec7c3e89c584243 Mon Sep 17 00:00:00 2001
+From: Paolo Sabatino <paolo.sabatino@gmail.com>
+Date: Tue, 6 Jul 2021 14:21:52 +0000
+Subject: [PATCH 1/5] rk3228/rk3328: fix ddr clock gate, add SIP v2 calls
+
+---
+ drivers/clk/rockchip/clk-ddr.c    | 130 ++++++++++++++++++++++++++++++
+ drivers/clk/rockchip/clk-rk3228.c |  14 ++--
+ drivers/clk/rockchip/clk-rk3328.c |   7 +-
+ drivers/clk/rockchip/clk.h        |   3 +-
+ 4 files changed, 143 insertions(+), 11 deletions(-)
+
+diff --git a/drivers/clk/rockchip/clk-ddr.c b/drivers/clk/rockchip/clk-ddr.c
+index 86718c54e..b16b3795f 100644
+--- a/drivers/clk/rockchip/clk-ddr.c
++++ b/drivers/clk/rockchip/clk-ddr.c
+@@ -87,6 +87,133 @@ static const struct clk_ops rockchip_ddrclk_sip_ops = {
+	.get_parent = rockchip_ddrclk_get_parent,
+ };
+
++/* See v4.4/include/dt-bindings/display/rk_fb.h */
++#define SCREEN_NULL			0
++#define SCREEN_HDMI			6
++
++static inline int rk_drm_get_lcdc_type(void)
++{
++	return SCREEN_NULL;
++}
++
++struct share_params {
++	u32 hz;
++	u32 lcdc_type;
++	u32 vop;
++	u32 vop_dclk_mode;
++	u32 sr_idle_en;
++	u32 addr_mcu_el3;
++	/*
++	 * 1: need to wait flag1
++	 * 0: never wait flag1
++	 */
++	u32 wait_flag1;
++	/*
++	 * 1: need to wait flag1
++	 * 0: never wait flag1
++	 */
++	u32 wait_flag0;
++	u32 complt_hwirq;
++	 /* if need, add parameter after */
++};
++
++struct rockchip_ddrclk_data {
++	u32 inited_flag;
++	void __iomem *share_memory;
++};
++
++static struct rockchip_ddrclk_data ddr_data;
++
++static void rockchip_ddrclk_data_init(void)
++{
++	struct arm_smccc_res res;
++
++	arm_smccc_smc(ROCKCHIP_SIP_SHARE_MEM,
++		      1, SHARE_PAGE_TYPE_DDR, 0,
++		      0, 0, 0, 0, &res);
++
++	if (!res.a0) {
++		ddr_data.share_memory = (void __iomem *)ioremap(res.a1, 1<<12);
++		ddr_data.inited_flag = 1;
++	}
++}
++
++static int rockchip_ddrclk_sip_set_rate_v2(struct clk_hw *hw,
++					   unsigned long drate,
++					   unsigned long prate)
++{
++	struct share_params *p;
++	struct arm_smccc_res res;
++
++	if (!ddr_data.inited_flag)
++		rockchip_ddrclk_data_init();
++
++	p = (struct share_params *)ddr_data.share_memory;
++
++	p->hz = drate;
++	p->lcdc_type = rk_drm_get_lcdc_type();
++	p->wait_flag1 = 1;
++	p->wait_flag0 = 1;
++
++	arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ,
++		      SHARE_PAGE_TYPE_DDR, 0,
++		      ROCKCHIP_SIP_CONFIG_DRAM_SET_RATE,
++		      0, 0, 0, 0, &res);
++
++	if ((int)res.a1 == -6) {
++		pr_err("%s: timeout, drate = %lumhz\n", __func__, drate/1000000);
++		/* TODO: rockchip_dmcfreq_wait_complete(); */
++	}
++
++	return res.a0;
++}
++
++static unsigned long rockchip_ddrclk_sip_recalc_rate_v2
++			(struct clk_hw *hw, unsigned long parent_rate)
++{
++	struct arm_smccc_res res;
++
++	arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ,
++		      SHARE_PAGE_TYPE_DDR, 0,
++		      ROCKCHIP_SIP_CONFIG_DRAM_GET_RATE,
++		      0, 0, 0, 0, &res);
++	if (!res.a0)
++		return res.a1;
++	else
++		return 0;
++}
++
++static long rockchip_ddrclk_sip_round_rate_v2(struct clk_hw *hw,
++					      unsigned long rate,
++					      unsigned long *prate)
++{
++	struct share_params *p;
++	struct arm_smccc_res res;
++
++	if (!ddr_data.inited_flag)
++		rockchip_ddrclk_data_init();
++
++	p = (struct share_params *)ddr_data.share_memory;
++
++	p->hz = rate;
++
++	arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ,
++		      SHARE_PAGE_TYPE_DDR, 0,
++		      ROCKCHIP_SIP_CONFIG_DRAM_ROUND_RATE,
++		      0, 0, 0, 0, &res);
++	if (!res.a0)
++		return res.a1;
++	else
++		return 0;
++}
++
++static const struct clk_ops rockchip_ddrclk_sip_ops_v2 = {
++	.recalc_rate = rockchip_ddrclk_sip_recalc_rate_v2,
++	.set_rate = rockchip_ddrclk_sip_set_rate_v2,
++	.round_rate = rockchip_ddrclk_sip_round_rate_v2,
++	.get_parent = rockchip_ddrclk_get_parent,
++};
++
+ struct clk *rockchip_clk_register_ddrclk(const char *name, int flags,
+					 const char *const *parent_names,
+					 u8 num_parents, int mux_offset,
+@@ -114,6 +241,9 @@ struct clk *rockchip_clk_register_ddrclk(const char *name, int flags,
+	case ROCKCHIP_DDRCLK_SIP:
+		init.ops = &rockchip_ddrclk_sip_ops;
+		break;
++	case ROCKCHIP_DDRCLK_SIP_V2:
++		init.ops = &rockchip_ddrclk_sip_ops_v2;
++		break;
+	default:
+		pr_err("%s: unsupported ddrclk type %d\n", __func__, ddr_flag);
+		kfree(ddrclk);
+diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c
+index 1f9176a5c..96393aa16 100644
+--- a/drivers/clk/rockchip/clk-rk3228.c
++++ b/drivers/clk/rockchip/clk-rk3228.c
+@@ -218,9 +218,9 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
+			RK2928_CLKSEL_CON(4), 8, 5, DFLAGS),
+
+	/* PD_DDR */
+-	COMPOSITE(0, "clk_ddrphy_src", mux_ddrphy_p, CLK_IGNORE_UNUSED,
+-			RK2928_CLKSEL_CON(26), 8, 2, MFLAGS, 0, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
+-			RK2928_CLKGATE_CON(0), 2, GFLAGS),
++	COMPOSITE_DDRCLK(SCLK_DDRCLK, "sclk_ddrc", mux_ddrphy_p, 0,
++			RK2928_CLKSEL_CON(26), 8, 2, 0, 2,
++			ROCKCHIP_DDRCLK_SIP_V2),
+	GATE(0, "ddrphy4x", "clk_ddrphy_src", CLK_IGNORE_UNUSED,
+			RK2928_CLKGATE_CON(7), 1, GFLAGS),
+	FACTOR_GATE(0, "ddrc", "clk_ddrphy_src", CLK_IGNORE_UNUSED, 1, 4,
+@@ -576,8 +576,8 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
+	GATE(HCLK_M_CRYPTO, "hclk_crypto_mst", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 11, GFLAGS),
+	GATE(HCLK_S_CRYPTO, "hclk_crypto_slv", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 12, GFLAGS),
+
+-	GATE(0, "pclk_ddrupctl", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(8), 4, GFLAGS),
+-	GATE(0, "pclk_ddrmon", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(8), 6, GFLAGS),
++	GATE(0, "pclk_ddr_upctl", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(8), 4, GFLAGS),
++	GATE(0, "pclk_ddr_mon", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(8), 6, GFLAGS),
+	GATE(0, "pclk_msch_noc", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(10), 2, GFLAGS),
+
+	GATE(PCLK_EFUSE_1024, "pclk_efuse_1024", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 13, GFLAGS),
+@@ -652,8 +652,8 @@ static const char *const rk3228_critical_clocks[] __initconst = {
+	"sclk_initmem_mbist",
+	"aclk_initmem",
+	"hclk_rom",
+-	"pclk_ddrupctl",
+-	"pclk_ddrmon",
++	"pclk_ddr_upctl",
++	"pclk_ddr_mon",
+	"pclk_msch_noc",
+	"pclk_stimer",
+	"pclk_ddrphy",
+diff --git a/drivers/clk/rockchip/clk-rk3328.c b/drivers/clk/rockchip/clk-rk3328.c
+index cc18dbc18..5fdd611bb 100644
+--- a/drivers/clk/rockchip/clk-rk3328.c
++++ b/drivers/clk/rockchip/clk-rk3328.c
+@@ -317,9 +317,10 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
+			RK3328_CLKGATE_CON(14), 1, GFLAGS),
+
+	/* PD_DDR */
+-	COMPOSITE(0, "clk_ddr", mux_ddrphy_p, CLK_IGNORE_UNUSED,
+-			RK3328_CLKSEL_CON(3), 8, 2, MFLAGS, 0, 3, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
+-			RK3328_CLKGATE_CON(0), 4, GFLAGS),
++	COMPOSITE_DDRCLK(SCLK_DDRCLK, "sclk_ddrc", mux_ddrphy_p, 0,
++			RK3328_CLKSEL_CON(3), 8, 2, 0, 3,
++			ROCKCHIP_DDRCLK_SIP_V2),
++
+	GATE(0, "clk_ddrmsch", "clk_ddr", CLK_IGNORE_UNUSED,
+			RK3328_CLKGATE_CON(18), 6, GFLAGS),
+	GATE(0, "clk_ddrupctl", "clk_ddr", CLK_IGNORE_UNUSED,
+diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h
+index ae059b774..fdaa81ebb 100644
+--- a/drivers/clk/rockchip/clk.h
++++ b/drivers/clk/rockchip/clk.h
+@@ -363,7 +363,8 @@ struct clk *rockchip_clk_register_mmc(const char *name,
+  * DDRCLK flags, including method of setting the rate
+  * ROCKCHIP_DDRCLK_SIP: use SIP call to bl31 to change ddrclk rate.
+  */
+-#define ROCKCHIP_DDRCLK_SIP		BIT(0)
++#define ROCKCHIP_DDRCLK_SIP		0x01
++#define ROCKCHIP_DDRCLK_SIP_V2		0x03
+
+ struct clk *rockchip_clk_register_ddrclk(const char *name, int flags,
+					 const char *const *parent_names,
+--
+2.25.1
diff --git a/projects/Rockchip/devices/RK322X/patches/linux/default/linux-4002-rk322x-analog-audio-codec.patch b/projects/Rockchip/devices/RK322X/patches/linux/default/linux-4002-rk322x-analog-audio-codec.patch
new file mode 100644
index 0000000000..e67e191a88
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/patches/linux/default/linux-4002-rk322x-analog-audio-codec.patch
@@ -0,0 +1,913 @@
+From b4f40590a4f946d8ee704faf8579930e53ef4650 Mon Sep 17 00:00:00 2001
+From: Paolo Sabatino <paolo.sabatino@gmail.com>
+Date: Sun, 12 Sep 2021 10:15:56 +0000
+Subject: [PATCH] rk322x: analog audio codec
+
+---
+ .../bindings/sound/rockchip,rk3228-codec.txt  |  22 +
+ arch/arm/boot/dts/rockchip/rk322x.dtsi                 |   9 +
+ drivers/clk/rockchip/clk-rk3228.c             |   2 +-
+ include/dt-bindings/clock/rk3228-cru.h        |   1 +
+ sound/soc/codecs/Kconfig                      |   5 +
+ sound/soc/codecs/Makefile                     |   2 +
+ sound/soc/codecs/rk3228_codec.c               | 545 ++++++++++++++++++
+ sound/soc/codecs/rk3228_codec.h               | 218 +++++++
+ 8 files changed, 803 insertions(+), 1 deletion(-)
+ create mode 100644 Documentation/devicetree/bindings/sound/rockchip,rk3228-codec.txt
+ create mode 100644 sound/soc/codecs/rk3228_codec.c
+ create mode 100644 sound/soc/codecs/rk3228_codec.h
+
+diff --git a/Documentation/devicetree/bindings/sound/rockchip,rk3228-codec.txt b/Documentation/devicetree/bindings/sound/rockchip,rk3228-codec.txt
+new file mode 100644
+index 000000000..9191a8593
+--- /dev/null
++++ b/Documentation/devicetree/bindings/sound/rockchip,rk3228-codec.txt
+@@ -0,0 +1,22 @@
++* Rockchip Rk3228 internal codec
++
++Required properties:
++
++- compatible: "rockchip,rk3228-codec"
++- reg: physical base address of the controller and length of memory mapped
++  region.
++- clocks: a list of phandle + clock-specifer pairs, one for each entry in clock-names.
++- clock-names: a list of clock names, one for each entry in clocks.
++- spk-en-gpio: speaker enable gpio.
++- spk-depop-time-ms: speaker depop time msec.
++
++Example for rk3228 internal codec:
++
++codec: codec@12010000 {
++	compatible = "rockchip,rk3228-codec";
++	reg = <0x12010000 0x1000>;
++	clocks =  <&cru SCLK_I2S_OUT>, <&cru PCLK_ACODECPHY>, <&cru SCLK_I2S1>;
++	clock-names = "mclk", "pclk", "sclk";
++	spk-en-gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
++	status = "disabled";
++};
+diff --git a/arch/arm/boot/dts/rockchip/rk322x.dtsi b/arch/arm/boot/dts/rockchip/rk322x.dtsi
+index 75af99c76..c2670d498 100644
+--- a/arch/arm/boot/dts/rockchip/rk322x.dtsi
++++ b/arch/arm/boot/dts/rockchip/rk322x.dtsi
+@@ -145,6 +145,16 @@ i2s1: i2s1@100b0000 {
+		status = "disabled";
+	};
+
++	analog_codec: analog-codec@12010000 {
++		compatible = "rockchip,rk3228-codec";
++		reg = <0x12010000 0x1000>;
++		clocks =  <&cru SCLK_I2S_OUT>, <&cru PCLK_ACODECPHY>, <&cru SCLK_I2S1>;
++		clock-names = "mclk", "pclk", "sclk";
++		spk-en-gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
++		#sound-dai-cells = <0>;
++		status = "disabled";
++	};
++
+	i2s0: i2s0@100c0000 {
+		compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
+		reg = <0x100c0000 0x4000>;
+diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c
+index a24a35553..69f8c792f 100644
+--- a/drivers/clk/rockchip/clk-rk3228.c
++++ b/drivers/clk/rockchip/clk-rk3228.c
+@@ -620,7 +620,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
+	GATE(0, "pclk_sim", "pclk_cpu", 0, RK2928_CLKGATE_CON(10), 3, GFLAGS),
+
+	GATE(0, "pclk_ddrphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 3, GFLAGS),
+-	GATE(0, "pclk_acodecphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 5, GFLAGS),
++	GATE(PCLK_ACODECPHY, "pclk_acodecphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 5, GFLAGS),
+	GATE(PCLK_HDMI_PHY, "pclk_hdmiphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 7, GFLAGS),
+	GATE(0, "pclk_vdacphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 8, GFLAGS),
+	GATE(0, "pclk_phy_noc", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 9, GFLAGS),
+diff --git a/include/dt-bindings/clock/rk3228-cru.h b/include/dt-bindings/clock/rk3228-cru.h
+index de550ea56..30d44ce90 100644
+--- a/include/dt-bindings/clock/rk3228-cru.h
++++ b/include/dt-bindings/clock/rk3228-cru.h
+@@ -115,6 +115,7 @@
+ #define PCLK_HDMI_CTRL		364
+ #define PCLK_HDMI_PHY		365
+ #define PCLK_GMAC		367
++#define PCLK_ACODECPHY		368
+
+ /* hclk gates */
+ #define HCLK_I2S0_8CH		442
+diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
+index db1607120..5f7f01102 100644
+--- a/sound/soc/codecs/Kconfig
++++ b/sound/soc/codecs/Kconfig
+@@ -154,6 +154,7 @@ config SND_SOC_ALL_CODECS
+	imply SND_SOC_PCM6240
+	imply SND_SOC_PEB2466
+	imply SND_SOC_RK3308
++	imply SND_SOC_RK3228
+	imply SND_SOC_RK3328
+	imply SND_SOC_RK817
+	imply SND_SOC_RT274
+@@ -1063,6 +1064,10 @@ config SND_SOC_RK3308
+	  It has 8 24-bit ADCs and 2 24-bit DACs. The maximum supported
+	  sampling rate is 192 kHz.
+
++config SND_SOC_RK3228
++        select REGMAP_MMIO
++        tristate "Rockchip RK3228 CODEC"
++
+ config SND_SOC_RK3328
+	tristate "Rockchip RK3328 audio CODEC"
+	depends on ARCH_ROCKCHIP || COMPILE_TEST
+diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile
+index 7bb38c370..232b5c43e 100644
+--- a/sound/soc/codecs/Makefile
++++ b/sound/soc/codecs/Makefile
+@@ -165,6 +165,7 @@ snd-soc-pcm512x-spi-y := pcm512x-spi.o
+ snd-soc-pcm6240-y := pcm6240.o
+ snd-soc-peb2466-y := peb2466.o
+ snd-soc-rk3308-y := rk3308_codec.o
++snd-soc-rk3228-y := rk3228_codec.o
+ snd-soc-rk3328-y := rk3328_codec.o
+ snd-soc-rk817-y := rk817_codec.o
+ snd-soc-rl6231-y := rl6231.o
+@@ -491,6 +492,7 @@ obj-$(CONFIG_SND_SOC_PCM512x_SPI)	+= snd-soc-pcm512x-spi.o
+ obj-$(CONFIG_SND_SOC_PCM6240)	+= snd-soc-pcm6240.o
+ obj-$(CONFIG_SND_SOC_PEB2466)	+= snd-soc-peb2466.o
+ obj-$(CONFIG_SND_SOC_RK3308)	+= snd-soc-rk3308.o
++obj-$(CONFIG_SND_SOC_RK3228)	+= snd-soc-rk3228.o
+ obj-$(CONFIG_SND_SOC_RK3328)	+= snd-soc-rk3328.o
+ obj-$(CONFIG_SND_SOC_RK817)	+= snd-soc-rk817.o
+ obj-$(CONFIG_SND_SOC_RL6231)	+= snd-soc-rl6231.o
+diff --git a/sound/soc/codecs/rk3228_codec.c b/sound/soc/codecs/rk3228_codec.c
+new file mode 100644
+index 000000000..b65307435
+--- /dev/null
++++ b/sound/soc/codecs/rk3228_codec.c
+@@ -0,0 +1,545 @@
++// SPDX-License-Identifier: GPL-2.0
++//
++// rk3228_codec.c  --  rk3228 ALSA Soc Audio driver
++//
++// Copyright (c) 2018, Fuzhou Rockchip Electronics Co., Ltd All rights reserved.
++
++#include <linux/module.h>
++#include <linux/device.h>
++#include <linux/delay.h>
++#include <linux/of.h>
++#include <linux/of_gpio.h>
++#include <linux/clk.h>
++#include <linux/platform_device.h>
++#include <linux/pm_runtime.h>
++#include <linux/regmap.h>
++#include <sound/pcm_params.h>
++#include <sound/dmaengine_pcm.h>
++#include "rk3228_codec.h"
++
++/*
++ * volume setting
++ * 0: -39dB
++ * 26: 0dB
++ * 31: 6dB
++ * Step: 1.5dB
++ */
++#define OUT_VOLUME	(0x1a)
++#define INITIAL_FREQ	(11289600)
++
++struct rk3228_codec_priv {
++	struct regmap *regmap;
++	struct clk *mclk;
++	struct clk *pclk;
++	struct clk *sclk;
++	struct gpio_desc *spk_en_gpio;
++	int spk_depop_time; /* msec */
++};
++
++static const struct reg_default rk3228_codec_reg_defaults[] = {
++	{ CODEC_RESET, 0x03 },
++	{ DAC_INIT_CTRL1, 0x00 },
++	{ DAC_INIT_CTRL2, 0x50 },
++	{ DAC_INIT_CTRL3, 0x0e },
++	{ DAC_PRECHARGE_CTRL, 0x01 },
++	{ DAC_PWR_CTRL, 0x00 },
++	{ DAC_CLK_CTRL, 0x00 },
++	{ HPMIX_CTRL, 0x00 },
++	{ HPOUT_CTRL, 0x00 },
++	{ HPOUTL_GAIN_CTRL, 0x00 },
++	{ HPOUTR_GAIN_CTRL, 0x00 },
++	{ HPOUT_POP_CTRL, 0x11 },
++};
++
++static int rk3228_codec_reset(struct snd_soc_component *component)
++{
++	struct rk3228_codec_priv *rk3228 = snd_soc_component_get_drvdata(component);
++
++	regmap_write(rk3228->regmap, CODEC_RESET, 0);
++	mdelay(10);
++	regmap_write(rk3228->regmap, CODEC_RESET, 0x03);
++
++	return 0;
++}
++
++static int rk3228_set_dai_fmt(struct snd_soc_dai *dai,
++			      unsigned int fmt)
++{
++	struct snd_soc_component *component = dai->component;
++	struct rk3228_codec_priv *rk3228 = snd_soc_component_get_drvdata(component);
++	unsigned int val = 0;
++
++	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
++	case SND_SOC_DAIFMT_CBC_CFC:
++		val |= PIN_DIRECTION_IN | DAC_I2S_MODE_SLAVE;
++		break;
++	case SND_SOC_DAIFMT_CBP_CFP:
++		val |= PIN_DIRECTION_OUT | DAC_I2S_MODE_MASTER;
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	regmap_update_bits(rk3228->regmap, DAC_INIT_CTRL1,
++			   PIN_DIRECTION_MASK | DAC_I2S_MODE_MASK, val);
++
++	val = 0;
++	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
++	case SND_SOC_DAIFMT_DSP_A:
++	case SND_SOC_DAIFMT_DSP_B:
++		val |= DAC_MODE_PCM;
++		break;
++	case SND_SOC_DAIFMT_I2S:
++		val |= DAC_MODE_I2S;
++		break;
++	case SND_SOC_DAIFMT_RIGHT_J:
++		val |= DAC_MODE_RJM;
++		break;
++	case SND_SOC_DAIFMT_LEFT_J:
++		val |= DAC_MODE_LJM;
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	regmap_update_bits(rk3228->regmap, DAC_INIT_CTRL2,
++			   DAC_MODE_MASK, val);
++	return 0;
++}
++
++static void rk3228_analog_output(struct rk3228_codec_priv *rk3228, int mute)
++{
++	if (rk3228->spk_en_gpio)
++		gpiod_set_value(rk3228->spk_en_gpio, mute);
++}
++
++static int rk3228_mute_stream(struct snd_soc_dai *dai, int mute, int direction)
++{
++	struct snd_soc_component *component = dai->component;
++	struct rk3228_codec_priv *rk3228 = snd_soc_component_get_drvdata(component);
++	unsigned int val = 0;
++
++	if (direction != SNDRV_PCM_STREAM_PLAYBACK)
++		return 0;
++
++	if (mute)
++		val = HPOUTL_MUTE | HPOUTR_MUTE;
++	else
++		val = HPOUTL_UNMUTE | HPOUTR_UNMUTE;
++
++	regmap_update_bits(rk3228->regmap, HPOUT_CTRL,
++			   HPOUTL_MUTE_MASK | HPOUTR_MUTE_MASK, val);
++	return 0;
++}
++
++static int rk3228_codec_power_on(struct snd_soc_component *component, int wait_ms)
++{
++	struct rk3228_codec_priv *rk3228 = snd_soc_component_get_drvdata(component);
++
++	regmap_update_bits(rk3228->regmap, DAC_PRECHARGE_CTRL,
++			   DAC_CHARGE_XCHARGE_MASK, DAC_CHARGE_PRECHARGE);
++	mdelay(10);
++	regmap_update_bits(rk3228->regmap, DAC_PRECHARGE_CTRL,
++			   DAC_CHARGE_CURRENT_ALL_MASK,
++			   DAC_CHARGE_CURRENT_ALL_ON);
++
++	mdelay(wait_ms);
++
++	return 0;
++}
++
++static int rk3228_codec_power_off(struct snd_soc_component *component, int wait_ms)
++{
++	struct rk3228_codec_priv *rk3228 = snd_soc_component_get_drvdata(component);
++
++	regmap_update_bits(rk3228->regmap, DAC_PRECHARGE_CTRL,
++			   DAC_CHARGE_XCHARGE_MASK, DAC_CHARGE_DISCHARGE);
++	mdelay(10);
++	regmap_update_bits(rk3228->regmap, DAC_PRECHARGE_CTRL,
++			   DAC_CHARGE_CURRENT_ALL_MASK,
++			   DAC_CHARGE_CURRENT_ALL_ON);
++
++	mdelay(wait_ms);
++
++	return 0;
++}
++
++static struct rk3228_reg_msk_val playback_open_list[] = {
++	{ DAC_PWR_CTRL, DAC_PWR_MASK, DAC_PWR_ON },
++	{ DAC_PWR_CTRL, DACL_PATH_REFV_MASK | DACR_PATH_REFV_MASK,
++	  DACL_PATH_REFV_ON | DACR_PATH_REFV_ON },
++	{ DAC_PWR_CTRL, HPOUTL_ZERO_CROSSING_ON | HPOUTR_ZERO_CROSSING_ON,
++	  HPOUTL_ZERO_CROSSING_ON | HPOUTR_ZERO_CROSSING_ON },
++	{ HPOUT_POP_CTRL, HPOUTR_POP_MASK | HPOUTL_POP_MASK,
++	  HPOUTR_POP_WORK | HPOUTL_POP_WORK },
++	{ HPMIX_CTRL, HPMIXL_MASK | HPMIXR_MASK, HPMIXL_EN | HPMIXR_EN },
++	{ HPMIX_CTRL, HPMIXL_INIT_MASK | HPMIXR_INIT_MASK,
++	  HPMIXL_INIT_EN | HPMIXR_INIT_EN },
++	{ HPOUT_CTRL, HPOUTL_MASK | HPOUTR_MASK, HPOUTL_EN | HPOUTR_EN },
++	{ HPOUT_CTRL, HPOUTL_INIT_MASK | HPOUTR_INIT_MASK,
++	  HPOUTL_INIT_EN | HPOUTR_INIT_EN },
++	{ DAC_CLK_CTRL, DACL_REFV_MASK | DACR_REFV_MASK,
++	  DACL_REFV_ON | DACR_REFV_ON },
++	{ DAC_CLK_CTRL, DACL_CLK_MASK | DACR_CLK_MASK,
++	  DACL_CLK_ON | DACR_CLK_ON },
++	{ DAC_CLK_CTRL, DACL_MASK | DACR_MASK, DACL_ON | DACR_ON },
++	{ DAC_CLK_CTRL, DACL_INIT_MASK | DACR_INIT_MASK,
++	  DACL_INIT_ON | DACR_INIT_ON },
++	{ DAC_SELECT, DACL_SELECT_MASK | DACR_SELECT_MASK,
++	  DACL_SELECT | DACR_SELECT },
++	{ HPMIX_CTRL, HPMIXL_INIT2_MASK | HPMIXR_INIT2_MASK,
++	  HPMIXL_INIT2_EN | HPMIXR_INIT2_EN },
++	{ HPOUT_CTRL, HPOUTL_MUTE_MASK | HPOUTR_MUTE_MASK,
++	  HPOUTL_UNMUTE | HPOUTR_UNMUTE },
++};
++
++#define PLAYBACK_OPEN_LIST_LEN ARRAY_SIZE(playback_open_list)
++
++static int rk3228_codec_open_playback(struct snd_soc_component *component)
++{
++	struct rk3228_codec_priv *rk3228 = snd_soc_component_get_drvdata(component);
++	int i = 0;
++
++	regmap_update_bits(rk3228->regmap, DAC_PRECHARGE_CTRL,
++			   DAC_CHARGE_CURRENT_ALL_MASK,
++			   DAC_CHARGE_CURRENT_I);
++
++	for (i = 0; i < PLAYBACK_OPEN_LIST_LEN; i++) {
++		regmap_update_bits(rk3228->regmap,
++				   playback_open_list[i].reg,
++				   playback_open_list[i].msk,
++				   playback_open_list[i].val);
++		mdelay(1);
++	}
++
++	msleep(rk3228->spk_depop_time);
++	rk3228_analog_output(rk3228, 1);
++
++	regmap_update_bits(rk3228->regmap, HPOUTL_GAIN_CTRL,
++			   HPOUTL_GAIN_MASK, OUT_VOLUME);
++	regmap_update_bits(rk3228->regmap, HPOUTR_GAIN_CTRL,
++			   HPOUTR_GAIN_MASK, OUT_VOLUME);
++	return 0;
++}
++
++static struct rk3228_reg_msk_val playback_close_list[] = {
++	{ HPMIX_CTRL, HPMIXL_INIT2_MASK | HPMIXR_INIT2_MASK,
++	  HPMIXL_INIT2_DIS | HPMIXR_INIT2_DIS },
++	{ DAC_SELECT, DACL_SELECT_MASK | DACR_SELECT_MASK,
++	  DACL_DESELECT | DACR_DESELECT },
++	{ HPOUT_CTRL, HPOUTL_MUTE_MASK | HPOUTR_MUTE_MASK,
++	  HPOUTL_MUTE | HPOUTR_MUTE },
++	{ HPOUT_CTRL, HPOUTL_INIT_MASK | HPOUTR_INIT_MASK,
++	  HPOUTL_INIT_DIS | HPOUTR_INIT_DIS },
++	{ HPOUT_CTRL, HPOUTL_MASK | HPOUTR_MASK, HPOUTL_DIS | HPOUTR_DIS },
++	{ HPMIX_CTRL, HPMIXL_MASK | HPMIXR_MASK, HPMIXL_DIS | HPMIXR_DIS },
++	{ DAC_CLK_CTRL, DACL_MASK | DACR_MASK, DACL_OFF | DACR_OFF },
++	{ DAC_CLK_CTRL, DACL_CLK_MASK | DACR_CLK_MASK,
++	  DACL_CLK_OFF | DACR_CLK_OFF },
++	{ DAC_CLK_CTRL, DACL_REFV_MASK | DACR_REFV_MASK,
++	  DACL_REFV_OFF | DACR_REFV_OFF },
++	{ HPOUT_POP_CTRL, HPOUTR_POP_MASK | HPOUTL_POP_MASK,
++	  HPOUTR_POP_XCHARGE | HPOUTL_POP_XCHARGE },
++	{ DAC_PWR_CTRL, DACL_PATH_REFV_MASK | DACR_PATH_REFV_MASK,
++	  DACL_PATH_REFV_OFF | DACR_PATH_REFV_OFF },
++	{ DAC_PWR_CTRL, DAC_PWR_MASK, DAC_PWR_OFF },
++	{ HPMIX_CTRL, HPMIXL_INIT_MASK | HPMIXR_INIT_MASK,
++	  HPMIXL_INIT_DIS | HPMIXR_INIT_DIS },
++	{ DAC_CLK_CTRL, DACL_INIT_MASK | DACR_INIT_MASK,
++	  DACL_INIT_OFF | DACR_INIT_OFF },
++};
++
++#define PLAYBACK_CLOSE_LIST_LEN ARRAY_SIZE(playback_close_list)
++
++static int rk3228_codec_close_playback(struct snd_soc_component *component)
++{
++	struct rk3228_codec_priv *rk3228 = snd_soc_component_get_drvdata(component);
++	int i = 0;
++
++	rk3228_analog_output(rk3228, 0);
++
++	regmap_update_bits(rk3228->regmap, HPOUTL_GAIN_CTRL,
++			   HPOUTL_GAIN_MASK, 0);
++	regmap_update_bits(rk3228->regmap, HPOUTR_GAIN_CTRL,
++			   HPOUTR_GAIN_MASK, 0);
++
++	for (i = 0; i < PLAYBACK_CLOSE_LIST_LEN; i++) {
++		regmap_update_bits(rk3228->regmap,
++				   playback_close_list[i].reg,
++				   playback_close_list[i].msk,
++				   playback_close_list[i].val);
++		mdelay(1);
++	}
++
++	regmap_update_bits(rk3228->regmap, DAC_PRECHARGE_CTRL,
++			   DAC_CHARGE_CURRENT_ALL_MASK,
++			   DAC_CHARGE_CURRENT_I);
++	return 0;
++}
++
++static int rk3228_hw_params(struct snd_pcm_substream *substream,
++			    struct snd_pcm_hw_params *params,
++			    struct snd_soc_dai *dai)
++{
++	struct snd_soc_component *component = dai->component;
++	struct rk3228_codec_priv *rk3228 = snd_soc_component_get_drvdata(component);
++	unsigned int val = 0;
++
++	switch (params_format(params)) {
++	case SNDRV_PCM_FORMAT_S16_LE:
++		val |= DAC_VDL_16BITS;
++		break;
++	case SNDRV_PCM_FORMAT_S20_3LE:
++		val |= DAC_VDL_20BITS;
++		break;
++	case SNDRV_PCM_FORMAT_S24_LE:
++		val |= DAC_VDL_24BITS;
++		break;
++	case SNDRV_PCM_FORMAT_S32_LE:
++		val |= DAC_VDL_32BITS;
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	regmap_update_bits(rk3228->regmap, DAC_INIT_CTRL2, DAC_VDL_MASK, val);
++	val = DAC_WL_32BITS | DAC_RST_DIS;
++	regmap_update_bits(rk3228->regmap, DAC_INIT_CTRL3,
++			   DAC_WL_MASK | DAC_RST_MASK, val);
++
++	return 0;
++}
++
++static int rk3228_pcm_startup(struct snd_pcm_substream *substream,
++			      struct snd_soc_dai *dai)
++{
++	struct snd_soc_component *component = dai->component;
++
++	return rk3228_codec_open_playback(component);
++}
++
++static void rk3228_pcm_shutdown(struct snd_pcm_substream *substream,
++				struct snd_soc_dai *dai)
++{
++	struct snd_soc_component *component = dai->component;
++
++	rk3228_codec_close_playback(component);
++}
++
++static struct snd_soc_dai_ops rk3228_dai_ops = {
++	.hw_params = rk3228_hw_params,
++	.set_fmt = rk3228_set_dai_fmt,
++	.mute_stream = rk3228_mute_stream,
++	.startup = rk3228_pcm_startup,
++	.shutdown = rk3228_pcm_shutdown,
++};
++
++static struct snd_soc_dai_driver rk3228_dai[] = {
++	{
++		.name = "rk3228-hifi",
++		.id = RK3228_HIFI,
++		.playback = {
++			.stream_name = "HIFI Playback",
++			.channels_min = 1,
++			.channels_max = 2,
++			.rates = SNDRV_PCM_RATE_8000_96000,
++			.formats = (SNDRV_PCM_FMTBIT_S16_LE |
++				    SNDRV_PCM_FMTBIT_S20_3LE |
++				    SNDRV_PCM_FMTBIT_S24_LE |
++				    SNDRV_PCM_FMTBIT_S32_LE),
++		},
++		/*.capture = {
++			.stream_name = "HIFI Capture",
++			.channels_min = 2,
++			.channels_max = 8,
++			.rates = SNDRV_PCM_RATE_8000_96000,
++			.formats = (SNDRV_PCM_FMTBIT_S16_LE |
++				    SNDRV_PCM_FMTBIT_S20_3LE |
++				    SNDRV_PCM_FMTBIT_S24_LE |
++				    SNDRV_PCM_FMTBIT_S32_LE),
++		},*/
++		.ops = &rk3228_dai_ops,
++	},
++};
++
++static int rk3228_codec_probe(struct snd_soc_component *component)
++{
++	rk3228_codec_reset(component);
++	rk3228_codec_power_on(component, 0);
++
++	return 0;
++}
++
++static void rk3228_codec_remove(struct snd_soc_component *component)
++{
++	rk3228_codec_close_playback(component);
++	rk3228_codec_power_off(component, 0);
++}
++
++static struct snd_soc_component_driver soc_codec_dev_rk3228 = {
++	.probe = rk3228_codec_probe,
++	.remove = rk3228_codec_remove,
++};
++
++static bool rk3228_codec_write_read_reg(struct device *dev, unsigned int reg)
++{
++	switch (reg) {
++	case CODEC_RESET:
++	case DAC_INIT_CTRL1:
++	case DAC_INIT_CTRL2:
++	case DAC_INIT_CTRL3:
++	case DAC_PRECHARGE_CTRL:
++	case DAC_PWR_CTRL:
++	case DAC_CLK_CTRL:
++	case HPMIX_CTRL:
++	case DAC_SELECT:
++	case HPOUT_CTRL:
++	case HPOUTL_GAIN_CTRL:
++	case HPOUTR_GAIN_CTRL:
++	case HPOUT_POP_CTRL:
++		return true;
++	default:
++		return false;
++	}
++}
++
++static bool rk3228_codec_volatile_reg(struct device *dev, unsigned int reg)
++{
++	switch (reg) {
++	case CODEC_RESET:
++		return true;
++	default:
++		return false;
++	}
++}
++
++static const struct regmap_config rk3228_codec_regmap_config = {
++	.reg_bits = 32,
++	.reg_stride = 4,
++	.val_bits = 32,
++	.max_register = HPOUT_POP_CTRL,
++	.writeable_reg = rk3228_codec_write_read_reg,
++	.readable_reg = rk3228_codec_write_read_reg,
++	.volatile_reg = rk3228_codec_volatile_reg,
++	.reg_defaults = rk3228_codec_reg_defaults,
++	.num_reg_defaults = ARRAY_SIZE(rk3228_codec_reg_defaults),
++	.cache_type = REGCACHE_FLAT,
++};
++
++#ifdef CONFIG_OF
++static const struct of_device_id rk3228codec_of_match[] = {
++	{ .compatible = "rockchip,rk3228-codec", },
++	{},
++};
++MODULE_DEVICE_TABLE(of, rk3228codec_of_match);
++#endif
++
++static int rk3228_platform_probe(struct platform_device *pdev)
++{
++	struct device_node *rk3228_np = pdev->dev.of_node;
++	struct rk3228_codec_priv *rk3228;
++	struct resource *res;
++	void __iomem *base;
++	int ret = 0;
++
++	rk3228 = devm_kzalloc(&pdev->dev, sizeof(*rk3228), GFP_KERNEL);
++	if (!rk3228)
++		return -ENOMEM;
++
++	rk3228->mclk = devm_clk_get(&pdev->dev, "mclk");
++	if (PTR_ERR(rk3228->mclk) == -EPROBE_DEFER)
++		return -EPROBE_DEFER;
++
++	rk3228->pclk = devm_clk_get(&pdev->dev, "pclk");
++	if (IS_ERR(rk3228->pclk))
++		return PTR_ERR(rk3228->pclk);
++
++	rk3228->sclk = devm_clk_get(&pdev->dev, "sclk");
++	if (IS_ERR(rk3228->sclk))
++		return PTR_ERR(rk3228->sclk);
++
++	rk3228->spk_en_gpio = devm_gpiod_get_optional(&pdev->dev,
++						      "spk-en",
++						      GPIOD_OUT_LOW);
++	if (IS_ERR(rk3228->spk_en_gpio))
++		return PTR_ERR(rk3228->spk_en_gpio);
++
++	ret = of_property_read_u32(rk3228_np, "spk-depop-time-ms",
++				   &rk3228->spk_depop_time);
++	if (ret < 0) {
++		dev_info(&pdev->dev, "spk_depop_time use default value.\n");
++		rk3228->spk_depop_time = 100;
++	}
++
++	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	base = devm_ioremap_resource(&pdev->dev, res);
++	if (IS_ERR(base))
++		return PTR_ERR(base);
++
++	ret = clk_prepare_enable(rk3228->mclk);
++	if (ret)
++		return ret;
++
++	ret = clk_prepare_enable(rk3228->pclk);
++	if (ret < 0)
++		goto err_pclk;
++
++	ret = clk_prepare_enable(rk3228->sclk);
++	if (ret)
++		goto err_sclk;
++
++	clk_set_rate(rk3228->sclk, INITIAL_FREQ);
++
++	rk3228->regmap = devm_regmap_init_mmio(&pdev->dev, base,
++					       &rk3228_codec_regmap_config);
++	if (IS_ERR(rk3228->regmap)) {
++		ret = PTR_ERR(rk3228->regmap);
++		goto err_clk;
++	}
++
++	platform_set_drvdata(pdev, rk3228);
++
++	ret = devm_snd_soc_register_component(&pdev->dev, &soc_codec_dev_rk3228,
++					      rk3228_dai, ARRAY_SIZE(rk3228_dai));
++	if (!ret)
++		return 0;
++
++err_clk:
++	clk_disable_unprepare(rk3228->sclk);
++err_sclk:
++	clk_disable_unprepare(rk3228->pclk);
++err_pclk:
++	clk_disable_unprepare(rk3228->mclk);
++
++	return ret;
++}
++
++static void rk3228_platform_remove(struct platform_device *pdev)
++{
++	struct rk3228_codec_priv *rk3228 = platform_get_drvdata(pdev);
++
++	if (!IS_ERR(rk3228->mclk))
++		clk_disable_unprepare(rk3228->mclk);
++
++	if (!IS_ERR(rk3228->pclk))
++		clk_disable_unprepare(rk3228->pclk);
++
++	if (!IS_ERR(rk3228->sclk))
++		clk_disable_unprepare(rk3228->sclk);
++
++	//return 0;
++}
++
++static struct platform_driver rk3228_codec_driver = {
++	.driver = {
++		   .name = "rk3228-codec",
++		   .of_match_table = of_match_ptr(rk3228codec_of_match),
++	},
++	.probe = rk3228_platform_probe,
++	.remove = rk3228_platform_remove,
++};
++module_platform_driver(rk3228_codec_driver);
++
++MODULE_AUTHOR("Sugar Zhang <sugar.zhang@rock-chips.com>");
++MODULE_DESCRIPTION("ASoC rk3228 codec driver");
++MODULE_LICENSE("GPL v2");
+diff --git a/sound/soc/codecs/rk3228_codec.h b/sound/soc/codecs/rk3228_codec.h
+new file mode 100644
+index 000000000..7283d0ba8
+--- /dev/null
++++ b/sound/soc/codecs/rk3228_codec.h
+@@ -0,0 +1,218 @@
++/*
++ * rk3228_codec.h  --  rk3228 ALSA Soc Audio driver
++ *
++ * Copyright (c) 2018, Fuzhou Rockchip Electronics Co., Ltd All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms and conditions of the GNU General Public License,
++ * version 2, as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
++ *
++ */
++
++#ifndef _RK3228_CODEC_H
++#define _RK3228_CODEC_H
++
++/* codec register */
++#define CODEC_RESET			(0x00 << 2)
++#define DAC_INIT_CTRL1			(0x03 << 2)
++#define DAC_INIT_CTRL2			(0x04 << 2)
++#define DAC_INIT_CTRL3			(0x05 << 2)
++#define DAC_PRECHARGE_CTRL		(0x22 << 2)
++#define DAC_PWR_CTRL			(0x23 << 2)
++#define DAC_CLK_CTRL			(0x24 << 2)
++#define HPMIX_CTRL			(0x25 << 2)
++#define DAC_SELECT			(0x26 << 2)
++#define HPOUT_CTRL			(0x27 << 2)
++#define HPOUTL_GAIN_CTRL		(0x28 << 2)
++#define HPOUTR_GAIN_CTRL		(0x29 << 2)
++#define HPOUT_POP_CTRL			(0x2a << 2)
++
++/* REG00: CODEC_RESET */
++#define PWR_RST_BYPASS_DIS		BIT(6)
++#define PWR_RST_BYPASS_EN		BIT(6)
++#define DIG_CORE_RST			(0 << 1)
++#define DIG_CORE_WORK			BIT(1)
++#define SYS_RST				(0)
++#define SYS_WORK			BIT(0)
++
++/* REG03: DAC_INIT_CTRL1 */
++#define PIN_DIRECTION_MASK		BIT(5)
++#define PIN_DIRECTION_IN		(0 << 5)
++#define PIN_DIRECTION_OUT		BIT(5)
++#define DAC_I2S_MODE_MASK		BIT(4)
++#define DAC_I2S_MODE_SLAVE		(0 << 4)
++#define DAC_I2S_MODE_MASTER		BIT(4)
++
++/* REG04: DAC_INIT_CTRL2 */
++#define DAC_I2S_LRP_MASK		BIT(7)
++#define DAC_I2S_LRP_NORMAL		(0 << 7)
++#define DAC_I2S_LRP_REVERSAL		BIT(7)
++#define DAC_VDL_MASK			(3 << 5)
++#define DAC_VDL_16BITS			(0 << 5)
++#define DAC_VDL_20BITS			BIT(5)
++#define DAC_VDL_24BITS			(2 << 5)
++#define DAC_VDL_32BITS			(3 << 5)
++#define DAC_MODE_MASK			(3 << 3)
++#define DAC_MODE_RJM			(0 << 3)
++#define DAC_MODE_LJM			BIT(3)
++#define DAC_MODE_I2S			(2 << 3)
++#define DAC_MODE_PCM			(3 << 3)
++#define DAC_LR_SWAP_MASK		BIT(2)
++#define DAC_LR_SWAP_DIS			(0 << 2)
++#define DAC_LR_SWAP_EN			BIT(2)
++
++/* REG05: DAC_INIT_CTRL3 */
++#define DAC_WL_MASK			(3 << 2)
++#define DAC_WL_16BITS			(0 << 2)
++#define DAC_WL_20BITS			BIT(2)
++#define DAC_WL_24BITS			(2 << 2)
++#define DAC_WL_32BITS			(3 << 2)
++#define DAC_RST_MASK			BIT(1)
++#define DAC_RST_EN			(0 << 1)
++#define DAC_RST_DIS			BIT(1)
++#define DAC_BCP_MASK			BIT(0)
++#define DAC_BCP_NORMAL			(0 << 0)
++#define DAC_BCP_REVERSAL		BIT(0)
++
++/* REG22: DAC_PRECHARGE_CTRL */
++#define DAC_CHARGE_PRECHARGE		BIT(7)
++#define DAC_CHARGE_DISCHARGE		(0 << 7)
++#define DAC_CHARGE_XCHARGE_MASK		BIT(7)
++#define DAC_CHARGE_CURRENT_64I		BIT(6)
++#define DAC_CHARGE_CURRENT_64I_MASK	BIT(6)
++#define DAC_CHARGE_CURRENT_32I		BIT(5)
++#define DAC_CHARGE_CURRENT_32I_MASK	BIT(5)
++#define DAC_CHARGE_CURRENT_16I		BIT(4)
++#define DAC_CHARGE_CURRENT_16I_MASK	BIT(4)
++#define DAC_CHARGE_CURRENT_08I		BIT(3)
++#define DAC_CHARGE_CURRENT_08I_MASK	BIT(3)
++#define DAC_CHARGE_CURRENT_04I		BIT(2)
++#define DAC_CHARGE_CURRENT_04I_MASK	BIT(2)
++#define DAC_CHARGE_CURRENT_02I		BIT(1)
++#define DAC_CHARGE_CURRENT_02I_MASK	BIT(1)
++#define DAC_CHARGE_CURRENT_I		BIT(0)
++#define DAC_CHARGE_CURRENT_I_MASK	BIT(0)
++#define DAC_CHARGE_CURRENT_ALL_MASK	(0x7f)
++#define DAC_CHARGE_CURRENT_ALL_OFF	(0x0)
++#define DAC_CHARGE_CURRENT_ALL_ON	(0x7f)
++
++/* REG23: DAC_PWR_CTRL */
++#define DAC_PWR_OFF			(0 << 6)
++#define DAC_PWR_ON			BIT(6)
++#define DAC_PWR_MASK			BIT(6)
++#define DACL_PATH_REFV_OFF		(0 << 5)
++#define DACL_PATH_REFV_ON		BIT(5)
++#define DACL_PATH_REFV_MASK		BIT(5)
++#define HPOUTL_ZERO_CROSSING_OFF	(0 << 4)
++#define HPOUTL_ZERO_CROSSING_ON		BIT(4)
++#define DACR_PATH_REFV_OFF		(0 << 1)
++#define DACR_PATH_REFV_ON		BIT(1)
++#define DACR_PATH_REFV_MASK		BIT(1)
++#define HPOUTR_ZERO_CROSSING_OFF	(0 << 0)
++#define HPOUTR_ZERO_CROSSING_ON		BIT(0)
++
++/* REG24: DAC_CLK_CTRL */
++#define DACL_REFV_OFF			(0 << 7)
++#define DACL_REFV_ON			BIT(7)
++#define DACL_REFV_MASK			BIT(7)
++#define DACL_CLK_OFF			(0 << 6)
++#define DACL_CLK_ON			BIT(6)
++#define DACL_CLK_MASK			BIT(6)
++#define DACL_OFF			(0 << 5)
++#define DACL_ON				BIT(5)
++#define DACL_MASK			BIT(5)
++#define DACL_INIT_OFF			(0 << 4)
++#define DACL_INIT_ON			BIT(4)
++#define DACL_INIT_MASK			BIT(4)
++#define DACR_REFV_OFF			(0 << 3)
++#define DACR_REFV_ON			BIT(3)
++#define DACR_REFV_MASK			BIT(3)
++#define DACR_CLK_OFF			(0 << 2)
++#define DACR_CLK_ON			BIT(2)
++#define DACR_CLK_MASK			BIT(2)
++#define DACR_OFF			(0 << 1)
++#define DACR_ON				BIT(1)
++#define DACR_MASK			BIT(1)
++#define DACR_INIT_OFF			(0 << 0)
++#define DACR_INIT_ON			BIT(0)
++#define DACR_INIT_MASK			BIT(0)
++
++/* REG25: HPMIX_CTRL*/
++#define HPMIXL_DIS			(0 << 6)
++#define HPMIXL_EN			BIT(6)
++#define HPMIXL_MASK			BIT(6)
++#define HPMIXL_INIT_DIS			(0 << 5)
++#define HPMIXL_INIT_EN			BIT(5)
++#define HPMIXL_INIT_MASK		BIT(5)
++#define HPMIXL_INIT2_DIS		(0 << 4)
++#define HPMIXL_INIT2_EN			BIT(4)
++#define HPMIXL_INIT2_MASK		BIT(4)
++#define HPMIXR_DIS			(0 << 2)
++#define HPMIXR_EN			BIT(2)
++#define HPMIXR_MASK			BIT(2)
++#define HPMIXR_INIT_DIS			(0 << 1)
++#define HPMIXR_INIT_EN			BIT(1)
++#define HPMIXR_INIT_MASK		BIT(1)
++#define HPMIXR_INIT2_DIS		(0 << 0)
++#define HPMIXR_INIT2_EN			BIT(0)
++#define HPMIXR_INIT2_MASK		BIT(0)
++
++/* REG26: DAC_SELECT */
++#define DACL_SELECT			BIT(4)
++#define DACL_SELECT_MASK		BIT(4)
++#define DACL_DESELECT			(0 << 4)
++#define DACR_SELECT			BIT(0)
++#define DACR_SELECT_MASK		BIT(0)
++#define DACR_DESELECT			(0 << 0)
++
++/* REG27: HPOUT_CTRL */
++#define HPOUTL_DIS			(0 << 7)
++#define HPOUTL_EN			BIT(7)
++#define HPOUTL_MASK			BIT(7)
++#define HPOUTL_INIT_DIS			(0 << 6)
++#define HPOUTL_INIT_EN			BIT(6)
++#define HPOUTL_INIT_MASK		BIT(6)
++#define HPOUTL_MUTE			(0 << 5)
++#define HPOUTL_UNMUTE			BIT(5)
++#define HPOUTL_MUTE_MASK		BIT(5)
++#define HPOUTR_DIS			(0 << 4)
++#define HPOUTR_EN			BIT(4)
++#define HPOUTR_MASK			BIT(4)
++#define HPOUTR_INIT_DIS			(0 << 3)
++#define HPOUTR_INIT_EN			BIT(3)
++#define HPOUTR_INIT_MASK		BIT(3)
++#define HPOUTR_MUTE			(0 << 2)
++#define HPOUTR_UNMUTE			BIT(2)
++#define HPOUTR_MUTE_MASK		BIT(2)
++
++/* REG28: HPOUTL_GAIN_CTRL */
++#define HPOUTL_GAIN_MASK		(0X1f << 0)
++
++/* REG29: HPOUTR_GAIN_CTRL */
++#define HPOUTR_GAIN_MASK		(0X1f << 0)
++
++/* REG2a: HPOUT_POP_CTRL */
++#define HPOUTR_POP_XCHARGE		BIT(4)
++#define HPOUTR_POP_WORK			(2 << 4)
++#define HPOUTR_POP_MASK			(3 << 4)
++#define HPOUTL_POP_XCHARGE		BIT(0)
++#define HPOUTL_POP_WORK			(2 << 0)
++#define HPOUTL_POP_MASK			(3 << 0)
++
++#define RK3228_HIFI			(0)
++
++struct rk3228_reg_msk_val {
++	unsigned int reg;
++	unsigned int msk;
++	unsigned int val;
++};
++
++#endif
+--
+2.25.1
diff --git a/projects/Rockchip/devices/RK322X/patches/linux/default/linux-4003-add-bcm43342-chip.patch b/projects/Rockchip/devices/RK322X/patches/linux/default/linux-4003-add-bcm43342-chip.patch
new file mode 100644
index 0000000000..4cae7a9b08
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/patches/linux/default/linux-4003-add-bcm43342-chip.patch
@@ -0,0 +1,44 @@
+From 01b579a527b5c77e6adfbb2c277fb2c7cc158b8b Mon Sep 17 00:00:00 2001
+From: Paolo Sabatino <paolo.sabatino@gmail.com>
+Date: Thu, 10 Feb 2022 21:30:54 +0000
+Subject: [PATCH] add broadcom bcm43342 chip id
+
+---
+ drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c       | 2 ++
+ drivers/net/wireless/broadcom/brcm80211/include/brcm_hw_ids.h | 1 +
+ 2 files changed, 3 insertions(+)
+
+diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c
+index 8effeb7a726..f45c1056e42 100644
+--- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c
++++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c
+@@ -611,6 +611,7 @@ BRCMF_FW_DEF(4329, "brcmfmac4329-sdio");
+ BRCMF_FW_DEF(4330, "brcmfmac4330-sdio");
+ BRCMF_FW_DEF(4334, "brcmfmac4334-sdio");
+ BRCMF_FW_DEF(43340, "brcmfmac43340-sdio");
++BRCMF_FW_DEF(43342, "brcmfmac43342-sdio");
+ BRCMF_FW_DEF(4335, "brcmfmac4335-sdio");
+ BRCMF_FW_DEF(43362, "brcmfmac43362-sdio");
+ BRCMF_FW_DEF(4339, "brcmfmac4339-sdio");
+@@ -644,6 +645,7 @@ static const struct brcmf_firmware_mapping brcmf_sdio_fwnames[] = {
+	BRCMF_FW_ENTRY(BRCM_CC_4334_CHIP_ID, 0xFFFFFFFF, 4334),
+	BRCMF_FW_ENTRY(BRCM_CC_43340_CHIP_ID, 0xFFFFFFFF, 43340),
+	BRCMF_FW_ENTRY(BRCM_CC_43341_CHIP_ID, 0xFFFFFFFF, 43340),
++	BRCMF_FW_ENTRY(BRCM_CC_43342_CHIP_ID, 0xFFFFFFFF, 43342),
+	BRCMF_FW_ENTRY(BRCM_CC_4335_CHIP_ID, 0xFFFFFFFF, 4335),
+	BRCMF_FW_ENTRY(BRCM_CC_43362_CHIP_ID, 0xFFFFFFFE, 43362),
+	BRCMF_FW_ENTRY(BRCM_CC_4339_CHIP_ID, 0xFFFFFFFF, 4339),
+diff --git a/drivers/net/wireless/broadcom/brcm80211/include/brcm_hw_ids.h b/drivers/net/wireless/broadcom/brcm80211/include/brcm_hw_ids.h
+index 9d81320164c..71de0dce4f4 100644
+--- a/drivers/net/wireless/broadcom/brcm80211/include/brcm_hw_ids.h
++++ b/drivers/net/wireless/broadcom/brcm80211/include/brcm_hw_ids.h
+@@ -27,6 +27,7 @@
+ #define BRCM_CC_4334_CHIP_ID		0x4334
+ #define BRCM_CC_43340_CHIP_ID		43340
+ #define BRCM_CC_43341_CHIP_ID		43341
++#define BRCM_CC_43342_CHIP_ID		43342
+ #define BRCM_CC_43362_CHIP_ID		43362
+ #define BRCM_CC_4335_CHIP_ID		0x4335
+ #define BRCM_CC_4339_CHIP_ID		0x4339
+--
+2.30.2
diff --git a/projects/Rockchip/devices/RK322X/patches/linux/default/linux-4003-add-ddr-clock-and-SIP-related-constant.patch b/projects/Rockchip/devices/RK322X/patches/linux/default/linux-4003-add-ddr-clock-and-SIP-related-constant.patch
new file mode 100644
index 0000000000..0c1400f624
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/patches/linux/default/linux-4003-add-ddr-clock-and-SIP-related-constant.patch
@@ -0,0 +1,66 @@
+From 95358ea4a4434ad4af5545b3f762508e4f015fc3 Mon Sep 17 00:00:00 2001
+From: Paolo Sabatino <paolo.sabatino@gmail.com>
+Date: Tue, 6 Jul 2021 14:23:36 +0000
+Subject: [PATCH 2/5] rk3228/rk3328: add ddr clock and SIP related constants
+ and defines
+
+---
+ include/dt-bindings/clock/rk3228-cru.h |  1 +
+ include/soc/rockchip/rockchip_sip.h    | 24 ++++++++++++++++++++++++
+ 2 files changed, 25 insertions(+)
+
+diff --git a/include/dt-bindings/clock/rk3228-cru.h b/include/dt-bindings/clock/rk3228-cru.h
+index de550ea56..911824731 100644
+--- a/include/dt-bindings/clock/rk3228-cru.h
++++ b/include/dt-bindings/clock/rk3228-cru.h
+@@ -15,6 +15,7 @@
+ #define ARMCLK			5
+
+ /* sclk gates (special clocks) */
++#define SCLK_DDRCLK		64
+ #define SCLK_SPI0		65
+ #define SCLK_NANDC		67
+ #define SCLK_SDMMC		68
+diff --git a/include/soc/rockchip/rockchip_sip.h b/include/soc/rockchip/rockchip_sip.h
+index c46a9ae2a..34e653751 100644
+--- a/include/soc/rockchip/rockchip_sip.h
++++ b/include/soc/rockchip/rockchip_sip.h
+@@ -6,6 +6,7 @@
+ #ifndef __SOC_ROCKCHIP_SIP_H
+ #define __SOC_ROCKCHIP_SIP_H
+
++#define ROCKCHIP_SIP_ATF_VERSION		0x82000001
+ #define ROCKCHIP_SIP_DRAM_FREQ			0x82000008
+ #define ROCKCHIP_SIP_CONFIG_DRAM_INIT		0x00
+ #define ROCKCHIP_SIP_CONFIG_DRAM_SET_RATE	0x01
+@@ -16,5 +17,28 @@
+ #define ROCKCHIP_SIP_CONFIG_DRAM_CLR_IRQ	0x06
+ #define ROCKCHIP_SIP_CONFIG_DRAM_SET_PARAM	0x07
+ #define ROCKCHIP_SIP_CONFIG_DRAM_SET_ODT_PD	0x08
++#define ROCKCHIP_SIP_CONFIG_DRAM_GET_VERSION	0x08
++#define ROCKCHIP_SIP_CONFIG_DRAM_POST_SET_RATE  0x09
++#define ROCKCHIP_SIP_CONFIG_DRAM_SET_MSCH_RL    0x0a
++#define ROCKCHIP_SIP_CONFIG_DRAM_DEBUG          0x0b
++
++#define ROCKCHIP_SIP_SHARE_MEM			0x82000009
++#define ROCKCHIP_SIP_SIP_VERSION		0x8200000a
++
++/* Rockchip Sip version */
++#define ROCKCHIP_SIP_IMPLEMENT_V1                (1)
++#define ROCKCHIP_SIP_IMPLEMENT_V2                (2)
++
++/* SIP_ACCESS_REG: read or write */
++#define SECURE_REG_RD			0x0
++#define SECURE_REG_WR			0x1
++
++/* Share mem page types */
++typedef enum {
++    SHARE_PAGE_TYPE_INVALID = 0,
++    SHARE_PAGE_TYPE_UARTDBG,
++    SHARE_PAGE_TYPE_DDR,
++    SHARE_PAGE_TYPE_MAX,
++} share_page_type_t;
+
+ #endif
+--
+2.25.1
diff --git a/projects/Rockchip/devices/RK322X/patches/linux/default/linux-4003-extend-rockchip-dfi-driver.patch b/projects/Rockchip/devices/RK322X/patches/linux/default/linux-4003-extend-rockchip-dfi-driver.patch
new file mode 100644
index 0000000000..b4c5f737e7
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/patches/linux/default/linux-4003-extend-rockchip-dfi-driver.patch
@@ -0,0 +1,827 @@
+From 415ed43c9b64ca38bc433bd5dc0359292dd80380 Mon Sep 17 00:00:00 2001
+From: Paolo Sabatino <paolo.sabatino@gmail.com>
+Date: Tue, 6 Jul 2021 14:25:41 +0000
+Subject: [PATCH 3/5] rk3228/rk3328: extend rockchip dfi driver
+
+---
+ arch/arm/boot/dts/rockchip/rk322x.dtsi        |   7 +
+ drivers/devfreq/event/rockchip-dfi.c | 598 ++++++++++++++++++++++++---
+ 2 files changed, 557 insertions(+), 48 deletions(-)
+
+diff --git a/arch/arm/boot/dts/rockchip/rk322x.dtsi b/arch/arm/boot/dts/rockchip/rk322x.dtsi
+index ad98fcf37..7e06acc31 100644
+--- a/arch/arm/boot/dts/rockchip/rk322x.dtsi
++++ b/arch/arm/boot/dts/rockchip/rk322x.dtsi
+@@ -97,6 +97,13 @@ opp-1200000000 {
+		};
+	};
+
++	dfi: dfi@11210000 {
++		reg = <0x11210000 0x400>;
++		compatible = "rockchip,rk3228-dfi";
++		rockchip,grf = <&grf>;
++		status = "okay";
++	};
++
+	arm-pmu {
+		compatible = "arm,cortex-a7-pmu";
+		interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
+diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c
+index 0470d7c175..24034f1a67 100644
+--- a/drivers/devfreq/event/rockchip-dfi.c
++++ b/drivers/devfreq/event/rockchip-dfi.c
+@@ -20,6 +20,7 @@
+ #include <linux/of.h>
+ #include <linux/of_device.h>
+ #include <linux/bitfield.h>
++#include <linux/hw_bitfield.h>
+ #include <linux/bits.h>
+ #include <linux/perf_event.h>
+
+@@ -28,21 +29,66 @@
+ #include <soc/rockchip/rk3568_grf.h>
+ #include <soc/rockchip/rk3588_grf.h>
+
+-#define DMC_MAX_CHANNELS	4
++/* --- Legacy & SoC Specific Definitions --- */
++#define PX30_PMUGRF_OS_REG2			0x208
++
++#define RK3128_GRF_SOC_CON0			0x140
++#define RK3128_GRF_DFI_WRNUM		0x220
++#define RK3128_GRF_DFI_RDNUM		0x224
++#define RK3128_GRF_DFI_TIMERVAL		0x22c
++#define RK3128_DDR_MONITOR_EN		((1 << (16 + 6)) + (1 << 6))
++#define RK3128_DDR_MONITOR_DISB		((1 << (16 + 6)) + (0 << 6))
++
++#define RK3228_GRF_OS_REG2			0x5d0
++
++#define RK3288_PMU_SYS_REG2			0x9c
++#define RK3288_GRF_SOC_CON4			0x254
++#define RK3288_GRF_SOC_STATUS(n)	(0x280 + (n) * 4)
++#define RK3288_DFI_EN				(0x30003 << 14)
++#define RK3288_DFI_DIS				(0x30000 << 14)
++#define RK3288_LPDDR_SEL			(0x10001 << 13)
++#define RK3288_DDR3_SEL				(0x10000 << 13)
++
++#define RK3328_GRF_OS_REG2			0x5d0
++
++#define RK3368_GRF_DDRC0_CON0		0x600
++#define RK3368_GRF_SOC_STATUS5		0x494
++#define RK3368_GRF_SOC_STATUS6		0x498
++#define RK3368_GRF_SOC_STATUS8		0x4a0
++#define RK3368_GRF_SOC_STATUS9		0x4a4
++#define RK3368_GRF_SOC_STATUS10		0x4a8
++#define RK3368_DFI_EN				(0x30003 << 5)
++#define RK3368_DFI_DIS				(0x30000 << 5)
++
++#define RK3528_PMUGRF_OFFSET		0x70000
++#define RK3528_PMUGRF_OS_REG18		0x248
++#define RK3528_PMUGRF_OS_REG19		0x24c
++
++#define RV1126B_PMUGRF_OS_REG2		(0x208 + 0x30000)
++#define RV1126B_PMUGRF_OS_REG3		(0x20c + 0x30000)
++
++#define READ_DRAMTYPE_INFO(n)		(((n) >> 13) & 0x7)
++#define READ_CH_INFO(n)				(((n) >> 28) & 0x3)
++#define READ_DRAMTYPE_INFO_V3(n, m)	((((n) >> 13) & 0x7) | ((((m) >> 12) & 0x3) << 3))
++#define READ_SYSREG_VERSION(m)		(((m) >> 28) & 0xf)
++
++/* Extra DFI Registers */
++#define DDRMON_CTRL1				0x08
++#define PART_CLK_GATE_EN			((0x7 << (16 + 4)) | (0x7 << 4))
+
+-#define HIWORD_UPDATE(val, mask)	((val) | (mask) << 16)
++#define DMC_MAX_CHANNELS	4
+
+ /* DDRMON_CTRL */
+ #define DDRMON_CTRL	0x04
++#define DDRMON_CTRL_LPDDR5		BIT(6)
+ #define DDRMON_CTRL_DDR4		BIT(5)
+ #define DDRMON_CTRL_LPDDR4		BIT(4)
+ #define DDRMON_CTRL_HARDWARE_EN		BIT(3)
+ #define DDRMON_CTRL_LPDDR23		BIT(2)
++#define DDRMON_CTRL_DDR23		BIT(15)
+ #define DDRMON_CTRL_SOFTWARE_EN		BIT(1)
+ #define DDRMON_CTRL_TIMER_CNT_EN	BIT(0)
+-#define DDRMON_CTRL_DDR_TYPE_MASK	(DDRMON_CTRL_DDR4 | \
+-					 DDRMON_CTRL_LPDDR4 | \
+-					 DDRMON_CTRL_LPDDR23)
++#define DDRMON_CTRL_LP5_BANK_MODE_MASK	GENMASK(8, 7)
+
+ #define DDRMON_CH0_WR_NUM		0x20
+ #define DDRMON_CH0_RD_NUM		0x24
+@@ -100,6 +146,8 @@ struct rockchip_dfi {
+	struct device *dev;
+	void __iomem *regs;
+	struct regmap *regmap_pmu;
++	struct regmap *regmap_grf;
++	struct regmap *regmap_pmugrf;
+	struct clk *clk;
+	int usecount;
+	struct mutex mutex;
+@@ -116,12 +164,80 @@ struct rockchip_dfi {
+	int buswidth[DMC_MAX_CHANNELS];
+	int ddrmon_stride;
+	bool ddrmon_ctrl_single;
++	u32 lp5_bank_mode;
++	bool lp5_ckr;	/* true if in 4:1 command-to-data clock ratio mode */
++	unsigned int count_multiplier;	/* number of data clocks per count */
+ };
+
++static int rockchip_dfi_ddrtype_to_ctrl(struct rockchip_dfi *dfi, u32 *ctrl)
++{
++	u32 ddrmon_ver;
++
++	switch (dfi->ddr_type) {
++	case ROCKCHIP_DDRTYPE_LPDDR2:
++	case ROCKCHIP_DDRTYPE_LPDDR3:
++		*ctrl = FIELD_PREP_WM16(DDRMON_CTRL_LPDDR23, 1) |
++			FIELD_PREP_WM16(DDRMON_CTRL_DDR23, 0) |
++			FIELD_PREP_WM16(DDRMON_CTRL_LPDDR4, 0) |
++			FIELD_PREP_WM16(DDRMON_CTRL_LPDDR5, 0);
++		break;
++	case ROCKCHIP_DDRTYPE_DDR2:
++	case ROCKCHIP_DDRTYPE_DDR3:
++		*ctrl = FIELD_PREP_WM16(DDRMON_CTRL_LPDDR23, 0) |
++			FIELD_PREP_WM16(DDRMON_CTRL_DDR23, 1) |
++			FIELD_PREP_WM16(DDRMON_CTRL_LPDDR4, 0) |
++			FIELD_PREP_WM16(DDRMON_CTRL_LPDDR5, 0);
++		break;
++	case ROCKCHIP_DDRTYPE_LPDDR4:
++	case ROCKCHIP_DDRTYPE_LPDDR4X:
++		*ctrl = FIELD_PREP_WM16(DDRMON_CTRL_LPDDR23, 0) |
++			FIELD_PREP_WM16(DDRMON_CTRL_DDR23, 0) |
++			FIELD_PREP_WM16(DDRMON_CTRL_LPDDR4, 1) |
++			FIELD_PREP_WM16(DDRMON_CTRL_LPDDR5, 0);
++		break;
++	case ROCKCHIP_DDRTYPE_DDR4:
++		*ctrl = FIELD_PREP_WM16(DDRMON_CTRL_LPDDR23, 0) |
++			FIELD_PREP_WM16(DDRMON_CTRL_DDR23, 0) |
++			FIELD_PREP_WM16(DDRMON_CTRL_LPDDR4, 0) |
++			FIELD_PREP_WM16(DDRMON_CTRL_DDR4, 1) |
++			FIELD_PREP_WM16(DDRMON_CTRL_LPDDR5, 0);
++		break;
++	case ROCKCHIP_DDRTYPE_LPDDR5:
++		ddrmon_ver = readl_relaxed(dfi->regs);
++		if (ddrmon_ver < 0x40) {
++			*ctrl = FIELD_PREP_WM16(DDRMON_CTRL_LPDDR23, 0) |
++				FIELD_PREP_WM16(DDRMON_CTRL_DDR23, 0) |
++				FIELD_PREP_WM16(DDRMON_CTRL_LPDDR4, 0) |
++				FIELD_PREP_WM16(DDRMON_CTRL_LPDDR5, 1) |
++				FIELD_PREP_WM16(DDRMON_CTRL_LP5_BANK_MODE_MASK,
++						dfi->lp5_bank_mode);
++			break;
++		}
++
++		/*
++		 * As it is unknown whether the unpleasant special case
++		 * behaviour used by the vendor kernel is needed for any
++		 * shipping hardware, ask users to report if they have
++		 * some of that hardware.
++		 */
++		dev_err(&dfi->edev->dev,
++			"unsupported DDRMON version 0x%04X, please let linux-rockchip know!\n",
++			ddrmon_ver);
++		return -EOPNOTSUPP;
++	default:
++		dev_err(&dfi->edev->dev, "unsupported memory type 0x%X\n",
++			dfi->ddr_type);
++		return -EOPNOTSUPP;
++	}
++
++	return 0;
++}
++
+ static int rockchip_dfi_enable(struct rockchip_dfi *dfi)
+ {
+	void __iomem *dfi_regs = dfi->regs;
+	int i, ret = 0;
++	u32 ctrl;
+
+	mutex_lock(&dfi->mutex);
+
+@@ -135,36 +251,26 @@ static int rockchip_dfi_enable(struct rockchip_dfi *dfi)
+		goto out;
+	}
+
++	ret = rockchip_dfi_ddrtype_to_ctrl(dfi, &ctrl);
++	if (ret)
++		goto out;
++
+	for (i = 0; i < dfi->max_channels; i++) {
+-		u32 ctrl = 0;
+
+		if (!(dfi->channel_mask & BIT(i)))
+			continue;
+
+		/* clear DDRMON_CTRL setting */
+-		writel_relaxed(HIWORD_UPDATE(0, DDRMON_CTRL_TIMER_CNT_EN |
+-			       DDRMON_CTRL_SOFTWARE_EN | DDRMON_CTRL_HARDWARE_EN),
++		writel_relaxed(FIELD_PREP_WM16(DDRMON_CTRL_TIMER_CNT_EN, 0) |
++			       FIELD_PREP_WM16(DDRMON_CTRL_SOFTWARE_EN, 0) |
++			       FIELD_PREP_WM16(DDRMON_CTRL_HARDWARE_EN, 0),
+			       dfi_regs + i * dfi->ddrmon_stride + DDRMON_CTRL);
+
+-		/* set ddr type to dfi */
+-		switch (dfi->ddr_type) {
+-		case ROCKCHIP_DDRTYPE_LPDDR2:
+-		case ROCKCHIP_DDRTYPE_LPDDR3:
+-			ctrl = DDRMON_CTRL_LPDDR23;
+-			break;
+-		case ROCKCHIP_DDRTYPE_LPDDR4:
+-		case ROCKCHIP_DDRTYPE_LPDDR4X:
+-			ctrl = DDRMON_CTRL_LPDDR4;
+-			break;
+-		default:
+-			break;
+-		}
+-
+-		writel_relaxed(HIWORD_UPDATE(ctrl, DDRMON_CTRL_DDR_TYPE_MASK),
+-			       dfi_regs + i * dfi->ddrmon_stride + DDRMON_CTRL);
++		writel_relaxed(ctrl, dfi_regs + i * dfi->ddrmon_stride +
++			       DDRMON_CTRL);
+
+		/* enable count, use software mode */
+-		writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_SOFTWARE_EN, DDRMON_CTRL_SOFTWARE_EN),
++		writel_relaxed(FIELD_PREP_WM16(DDRMON_CTRL_SOFTWARE_EN, 1),
+			       dfi_regs + i * dfi->ddrmon_stride + DDRMON_CTRL);
+
+		if (dfi->ddrmon_ctrl_single)
+@@ -194,8 +300,8 @@ static void rockchip_dfi_disable(struct rockchip_dfi *dfi)
+		if (!(dfi->channel_mask & BIT(i)))
+			continue;
+
+-		writel_relaxed(HIWORD_UPDATE(0, DDRMON_CTRL_SOFTWARE_EN),
+-			      dfi_regs + i * dfi->ddrmon_stride + DDRMON_CTRL);
++		writel_relaxed(FIELD_PREP_WM16(DDRMON_CTRL_SOFTWARE_EN, 0),
++			       dfi_regs + i * dfi->ddrmon_stride + DDRMON_CTRL);
+
+		if (dfi->ddrmon_ctrl_single)
+			break;
+@@ -435,7 +541,7 @@ static u64 rockchip_ddr_perf_event_get_count(struct perf_event *event)
+
+	switch (event->attr.config) {
+	case PERF_EVENT_CYCLES:
+-		count = total.c[0].clock_cycles;
++		count = total.c[0].clock_cycles * dfi->count_multiplier;
+		break;
+	case PERF_EVENT_READ_BYTES:
+		for (i = 0; i < dfi->max_channels; i++)
+@@ -651,10 +757,14 @@ static int rockchip_ddr_perf_init(struct rockchip_dfi *dfi)
+		break;
+	case ROCKCHIP_DDRTYPE_LPDDR4:
+	case ROCKCHIP_DDRTYPE_LPDDR4X:
++	case ROCKCHIP_DDRTYPE_LPDDR5:
+		dfi->burst_len = 16;
+		break;
+	}
+
++	if (!dfi->count_multiplier)
++		dfi->count_multiplier = 1;
++
+	ret = perf_pmu_register(pmu, "rockchip_ddr", -1);
+	if (ret)
+		return ret;
+@@ -726,7 +836,7 @@ static int rk3568_dfi_init(struct rockchip_dfi *dfi)
+ static int rk3588_dfi_init(struct rockchip_dfi *dfi)
+ {
+	struct regmap *regmap_pmu = dfi->regmap_pmu;
+-	u32 reg2, reg3, reg4;
++	u32 reg2, reg3, reg4, reg6;
+
+	regmap_read(regmap_pmu, RK3588_PMUGRF_OS_REG2, &reg2);
+	regmap_read(regmap_pmu, RK3588_PMUGRF_OS_REG3, &reg3);
+@@ -751,14 +861,400 @@ static int rk3588_dfi_init(struct rockchip_dfi *dfi)
+	dfi->max_channels = 4;
+
+	dfi->ddrmon_stride = 0x4000;
++	dfi->count_multiplier = 2;
++
++	if (dfi->ddr_type == ROCKCHIP_DDRTYPE_LPDDR5) {
++		regmap_read(regmap_pmu, RK3588_PMUGRF_OS_REG6, &reg6);
++		dfi->lp5_bank_mode = FIELD_GET(RK3588_PMUGRF_OS_REG6_LP5_BANK_MODE, reg6) << 7;
++		dfi->lp5_ckr = FIELD_GET(RK3588_PMUGRF_OS_REG6_LP5_CKR, reg6);
++		if (dfi->lp5_ckr)
++			dfi->count_multiplier *= 2;
++	}
++
++	return 0;
++};
++
++/* --- New & Hybrid SoCs (Standard Ops, Custom Init) --- */
++static int px30_dfi_init(struct rockchip_dfi *dfi)
++{
++	struct device_node *node;
++	u32 val_2, val_3;
++
++	node = of_parse_phandle(dfi->dev->of_node, "rockchip,pmugrf", 0);
++	if (node) {
++		dfi->regmap_pmugrf = syscon_node_to_regmap(node);
++		of_node_put(node);
++	}
++	if (IS_ERR_OR_NULL(dfi->regmap_pmugrf))
++		return -ENODEV;
++
++	regmap_read(dfi->regmap_pmugrf, PX30_PMUGRF_OS_REG2, &val_2);
++	/* Try to read version from REG3 if available */
++	regmap_read(dfi->regmap_pmugrf, PX30_PMUGRF_OS_REG2 + 4, &val_3);
++
++	if (READ_SYSREG_VERSION(val_3) >= 0x3)
++		dfi->ddr_type = READ_DRAMTYPE_INFO_V3(val_2, val_3);
++	else
++		dfi->ddr_type = READ_DRAMTYPE_INFO(val_2);
++
++	dfi->channel_mask = 1;
++	return 0;
++}
++
++static int rk3228_dfi_init(struct rockchip_dfi *dfi)
++{
++	struct device_node *node;
++	u32 val;
++
++	node = of_parse_phandle(dfi->dev->of_node, "rockchip,grf", 0);
++	if (node) {
++		dfi->regmap_grf = syscon_node_to_regmap(node);
++		of_node_put(node);
++	}
++	if (IS_ERR_OR_NULL(dfi->regmap_grf))
++		return -ENODEV;
++
++	regmap_read(dfi->regmap_grf, RK3228_GRF_OS_REG2, &val);
++	dfi->ddr_type = READ_DRAMTYPE_INFO(val);
++	dfi->channel_mask = 1;
++	return 0;
++}
++
++static int rk3328_dfi_init(struct rockchip_dfi *dfi)
++{
++	struct device_node *node;
++	u32 val;
++
++	node = of_parse_phandle(dfi->dev->of_node, "rockchip,grf", 0);
++	if (node) {
++		dfi->regmap_grf = syscon_node_to_regmap(node);
++		of_node_put(node);
++	}
++	if (IS_ERR_OR_NULL(dfi->regmap_grf))
++		return -ENODEV;
++
++	regmap_read(dfi->regmap_grf, RK3328_GRF_OS_REG2, &val);
++	dfi->ddr_type = READ_DRAMTYPE_INFO(val);
++	dfi->channel_mask = 1;
++	return 0;
++}
++
++static int rk3528_dfi_init(struct rockchip_dfi *dfi)
++{
++	struct device_node *node;
++	u32 val_18, val_19;
++
++	node = of_parse_phandle(dfi->dev->of_node, "rockchip,grf", 0);
++	if (node) {
++		dfi->regmap_grf = syscon_node_to_regmap(node);
++		of_node_put(node);
++	}
++	if (IS_ERR_OR_NULL(dfi->regmap_grf))
++		return -ENODEV;
++
++	regmap_read(dfi->regmap_grf, RK3528_PMUGRF_OFFSET + RK3528_PMUGRF_OS_REG18, &val_18);
++	regmap_read(dfi->regmap_grf, RK3528_PMUGRF_OFFSET + RK3528_PMUGRF_OS_REG19, &val_19);
++
++	if (READ_SYSREG_VERSION(val_19) >= 0x3)
++		dfi->ddr_type = READ_DRAMTYPE_INFO_V3(val_18, val_19);
++	else
++		dfi->ddr_type = READ_DRAMTYPE_INFO(val_18);
++
++	dfi->count_multiplier = 2;
++	dfi->channel_mask = 1;
++	return 0;
++}
++
++static int rk3576_dfi_init(struct rockchip_dfi *dfi)
++{
++	u32 reg2, reg3, reg4, reg6;
++
++	dfi->regmap_pmu = syscon_regmap_lookup_by_phandle(dfi->dev->of_node, "rockchip,pmu_grf");
++	if (IS_ERR(dfi->regmap_pmu))
++		return PTR_ERR(dfi->regmap_pmu);
++
++	regmap_read(dfi->regmap_pmu, RK3588_PMUGRF_OS_REG2, &reg2);
++	regmap_read(dfi->regmap_pmu, RK3588_PMUGRF_OS_REG3, &reg3);
++	regmap_read(dfi->regmap_pmu, RK3588_PMUGRF_OS_REG4, &reg4);
++
++	dfi->ddr_type = FIELD_GET(RK3588_PMUGRF_OS_REG2_DRAMTYPE_INFO, reg2);
++	if (FIELD_GET(RK3588_PMUGRF_OS_REG3_SYSREG_VERSION, reg3) >= 0x3)
++		dfi->ddr_type |= FIELD_GET(RK3588_PMUGRF_OS_REG3_DRAMTYPE_INFO_V3, reg3) << 3;
++
++	dfi->buswidth[0] = FIELD_GET(RK3588_PMUGRF_OS_REG2_BW_CH0, reg2) == 0 ? 4 : 2;
++	dfi->buswidth[1] = FIELD_GET(RK3588_PMUGRF_OS_REG2_BW_CH1, reg2) == 0 ? 4 : 2;
++	dfi->buswidth[2] = FIELD_GET(RK3568_PMUGRF_OS_REG2_BW_CH0, reg4) == 0 ? 4 : 2;
++	dfi->buswidth[3] = FIELD_GET(RK3588_PMUGRF_OS_REG2_BW_CH1, reg4) == 0 ? 4 : 2;
++
++	dfi->channel_mask = FIELD_GET(RK3588_PMUGRF_OS_REG2_CH_INFO, reg2) |
++			    FIELD_GET(RK3588_PMUGRF_OS_REG2_CH_INFO, reg4) << 2;
++	dfi->max_channels = 4;
++
++	dfi->ddrmon_stride = 0x10000;
++	dfi->count_multiplier = 2;
++
++	if (dfi->ddr_type == ROCKCHIP_DDRTYPE_LPDDR5) {
++		regmap_read(dfi->regmap_pmu, RK3588_PMUGRF_OS_REG6, &reg6);
++		dfi->lp5_bank_mode = FIELD_GET(RK3588_PMUGRF_OS_REG6_LP5_BANK_MODE, reg6) << 7;
++		dfi->lp5_ckr = FIELD_GET(RK3588_PMUGRF_OS_REG6_LP5_CKR, reg6);
++		if (dfi->lp5_ckr)
++			dfi->count_multiplier *= 2;
++	}
++
++	return 0;
++}
++
++static int rv1126b_dfi_init(struct rockchip_dfi *dfi)
++{
++	struct device_node *node;
++	u32 val_2, val_3;
++
++	/* Enable part pclk gate */
++	if (dfi->regs)
++		writel_relaxed(PART_CLK_GATE_EN, dfi->regs + DDRMON_CTRL1);
++
++	node = of_parse_phandle(dfi->dev->of_node, "rockchip,pmugrf", 0);
++	if (node) {
++		dfi->regmap_pmugrf = syscon_node_to_regmap(node);
++		of_node_put(node);
++	}
++	if (IS_ERR_OR_NULL(dfi->regmap_pmugrf))
++		return -ENODEV;
+
++	regmap_read(dfi->regmap_pmugrf, RV1126B_PMUGRF_OS_REG2, &val_2);
++	regmap_read(dfi->regmap_pmugrf, RV1126B_PMUGRF_OS_REG3, &val_3);
++
++	if (READ_SYSREG_VERSION(val_3) >= 0x3)
++		dfi->ddr_type = READ_DRAMTYPE_INFO_V3(val_2, val_3);
++	else
++		dfi->ddr_type = READ_DRAMTYPE_INFO(val_2);
++
++	dfi->channel_mask = 1;
++	return 0;
++}
++
++/* --- Legacy SoCs (RK3128, RK3288, RK3368) --- */
++
++static int rk3128_dfi_enable(struct devfreq_event_dev *edev)
++{
++	struct rockchip_dfi *dfi = devfreq_event_get_drvdata(edev);
++	regmap_write(dfi->regmap_grf, RK3128_GRF_SOC_CON0, RK3128_DDR_MONITOR_EN);
++	return 0;
++}
++
++static int rk3128_dfi_disable(struct devfreq_event_dev *edev)
++{
++	struct rockchip_dfi *dfi = devfreq_event_get_drvdata(edev);
++	regmap_write(dfi->regmap_grf, RK3128_GRF_SOC_CON0, RK3128_DDR_MONITOR_DISB);
++	return 0;
++}
++
++static int rk3128_dfi_set_event(struct devfreq_event_dev *edev)
++{
++	return 0;
++}
++
++static int rk3128_dfi_get_event(struct devfreq_event_dev *edev,
++				struct devfreq_event_data *edata)
++{
++	struct rockchip_dfi *dfi = devfreq_event_get_drvdata(edev);
++	u32 dfi_wr, dfi_rd, dfi_timer;
++
++	rk3128_dfi_disable(edev);
++	regmap_read(dfi->regmap_grf, RK3128_GRF_DFI_WRNUM, &dfi_wr);
++	regmap_read(dfi->regmap_grf, RK3128_GRF_DFI_RDNUM, &dfi_rd);
++	regmap_read(dfi->regmap_grf, RK3128_GRF_DFI_TIMERVAL, &dfi_timer);
++	edata->load_count = (dfi_wr + dfi_rd) * 4;
++	edata->total_count = dfi_timer;
++	rk3128_dfi_enable(edev);
++
++	return 0;
++}
++
++static const struct devfreq_event_ops rk3128_dfi_ops = {
++	.disable = rk3128_dfi_disable,
++	.enable = rk3128_dfi_enable,
++	.get_event = rk3128_dfi_get_event,
++	.set_event = rk3128_dfi_set_event,
++};
++
++static int rk3128_dfi_init(struct rockchip_dfi *dfi)
++{
++	struct device_node *node;
++	node = of_parse_phandle(dfi->dev->of_node, "rockchip,grf", 0);
++	if (node) {
++		dfi->regmap_grf = syscon_node_to_regmap(node);
++		of_node_put(node);
++	}
++	if (IS_ERR_OR_NULL(dfi->regmap_grf))
++		return -ENODEV;
++
++	dfi->desc.ops = &rk3128_dfi_ops;
++	return 0;
++}
++
++/* RK3288 Legacy Ops */
++static int rk3288_dfi_enable(struct devfreq_event_dev *edev)
++{
++	struct rockchip_dfi *dfi = devfreq_event_get_drvdata(edev);
++	regmap_write(dfi->regmap_grf, RK3288_GRF_SOC_CON4, RK3288_DFI_EN);
++	return 0;
++}
++
++static int rk3288_dfi_disable(struct devfreq_event_dev *edev)
++{
++	struct rockchip_dfi *dfi = devfreq_event_get_drvdata(edev);
++	regmap_write(dfi->regmap_grf, RK3288_GRF_SOC_CON4, RK3288_DFI_DIS);
++	return 0;
++}
++
++static int rk3288_dfi_set_event(struct devfreq_event_dev *edev)
++{
++	return 0;
++}
++
++static int rk3288_dfi_get_event(struct devfreq_event_dev *edev,
++				struct devfreq_event_data *edata)
++{
++	struct rockchip_dfi *dfi = devfreq_event_get_drvdata(edev);
++	u32 tmp, max = 0;
++	u32 i, busier_ch = 0;
++	u32 rd_count, wr_count, total_count;
++
++	rk3288_dfi_disable(edev);
++	for (i = 0; i < DMC_MAX_CHANNELS; i++) {
++		if (!(dfi->channel_mask & BIT(i)))
++			continue;
++		regmap_read(dfi->regmap_grf, RK3288_GRF_SOC_STATUS(11 + i * 4), &wr_count);
++		regmap_read(dfi->regmap_grf, RK3288_GRF_SOC_STATUS(12 + i * 4), &rd_count);
++		regmap_read(dfi->regmap_grf, RK3288_GRF_SOC_STATUS(14 + i * 4), &total_count);
++		tmp = (wr_count + rd_count) * 4;
++		if (tmp > max) {
++			busier_ch = i;
++			max = tmp;
++			edata->load_count = tmp;
++			edata->total_count = total_count;
++		}
++	}
++	rk3288_dfi_enable(edev);
+	return 0;
++}
++
++static const struct devfreq_event_ops rk3288_dfi_ops = {
++	.disable = rk3288_dfi_disable,
++	.enable = rk3288_dfi_enable,
++	.get_event = rk3288_dfi_get_event,
++	.set_event = rk3288_dfi_set_event,
+ };
+
++static int rk3288_dfi_init(struct rockchip_dfi *dfi)
++{
++	struct device_node *node;
++	u32 val;
++
++	node = of_parse_phandle(dfi->dev->of_node, "rockchip,pmu", 0);
++	if (node) {
++		dfi->regmap_pmu = syscon_node_to_regmap(node);
++		of_node_put(node);
++	}
++	if (IS_ERR_OR_NULL(dfi->regmap_pmu))
++		return -ENODEV;
++
++	node = of_parse_phandle(dfi->dev->of_node, "rockchip,grf", 0);
++	if (node) {
++		dfi->regmap_grf = syscon_node_to_regmap(node);
++		of_node_put(node);
++	}
++	if (IS_ERR_OR_NULL(dfi->regmap_grf))
++		return -ENODEV;
++
++	regmap_read(dfi->regmap_pmu, RK3288_PMU_SYS_REG2, &val);
++	dfi->ddr_type = READ_DRAMTYPE_INFO(val);
++	dfi->channel_mask = READ_CH_INFO(val);
++
++	if (dfi->ddr_type == ROCKCHIP_DDRTYPE_DDR3)
++		regmap_write(dfi->regmap_grf, RK3288_GRF_SOC_CON4, RK3288_DDR3_SEL);
++	else
++		regmap_write(dfi->regmap_grf, RK3288_GRF_SOC_CON4, RK3288_LPDDR_SEL);
++
++	dfi->desc.ops = &rk3288_dfi_ops;
++	return 0;
++}
++
++/* RK3368 Legacy Ops */
++static int rk3368_dfi_enable(struct devfreq_event_dev *edev)
++{
++	struct rockchip_dfi *dfi = devfreq_event_get_drvdata(edev);
++	regmap_write(dfi->regmap_grf, RK3368_GRF_DDRC0_CON0, RK3368_DFI_EN);
++	return 0;
++}
++
++static int rk3368_dfi_disable(struct devfreq_event_dev *edev)
++{
++	struct rockchip_dfi *dfi = devfreq_event_get_drvdata(edev);
++	regmap_write(dfi->regmap_grf, RK3368_GRF_DDRC0_CON0, RK3368_DFI_DIS);
++	return 0;
++}
++
++static int rk3368_dfi_set_event(struct devfreq_event_dev *edev)
++{
++	return 0;
++}
++
++static int rk3368_dfi_get_event(struct devfreq_event_dev *edev,
++				struct devfreq_event_data *edata)
++{
++	struct rockchip_dfi *dfi = devfreq_event_get_drvdata(edev);
++	u32 dfi0_wr, dfi0_rd, dfi1_wr, dfi1_rd, dfi_timer;
++
++	rk3368_dfi_disable(edev);
++	regmap_read(dfi->regmap_grf, RK3368_GRF_SOC_STATUS5, &dfi0_wr);
++	regmap_read(dfi->regmap_grf, RK3368_GRF_SOC_STATUS6, &dfi0_rd);
++	regmap_read(dfi->regmap_grf, RK3368_GRF_SOC_STATUS9, &dfi1_wr);
++	regmap_read(dfi->regmap_grf, RK3368_GRF_SOC_STATUS10, &dfi1_rd);
++	regmap_read(dfi->regmap_grf, RK3368_GRF_SOC_STATUS8, &dfi_timer);
++	edata->load_count = (dfi0_wr + dfi0_rd + dfi1_wr + dfi1_rd) * 2;
++	edata->total_count = dfi_timer;
++	rk3368_dfi_enable(edev);
++	return 0;
++}
++
++static const struct devfreq_event_ops rk3368_dfi_ops = {
++	.disable = rk3368_dfi_disable,
++	.enable = rk3368_dfi_enable,
++	.get_event = rk3368_dfi_get_event,
++	.set_event = rk3368_dfi_set_event,
++};
++
++static int rk3368_dfi_init(struct rockchip_dfi *dfi)
++{
++	struct device *dev = dfi->dev;
++	if (dev->parent && dev->parent->of_node)
++		dfi->regmap_grf = syscon_node_to_regmap(dev->parent->of_node);
++
++	if (IS_ERR_OR_NULL(dfi->regmap_grf))
++		return -ENODEV;
++
++	dfi->desc.ops = &rk3368_dfi_ops;
++	return 0;
++}
++
+ static const struct of_device_id rockchip_dfi_id_match[] = {
++	{ .compatible = "rockchip,px30-dfi", .data = px30_dfi_init },
++	{ .compatible = "rockchip,rk1808-dfi", .data = px30_dfi_init },
++	{ .compatible = "rockchip,rk3128-dfi", .data = rk3128_dfi_init },
++	{ .compatible = "rockchip,rk3228-dfi", .data = rk3228_dfi_init },
++	{ .compatible = "rockchip,rk3288-dfi", .data = rk3288_dfi_init },
++	{ .compatible = "rockchip,rk3328-dfi", .data = rk3328_dfi_init },
++	{ .compatible = "rockchip,rk3368-dfi", .data = rk3368_dfi_init },
+	{ .compatible = "rockchip,rk3399-dfi", .data = rk3399_dfi_init },
++	{ .compatible = "rockchip,rk3528-dfi", .data = rk3528_dfi_init },
++	{ .compatible = "rockchip,rk3562-dfi", .data = px30_dfi_init },
+	{ .compatible = "rockchip,rk3568-dfi", .data = rk3568_dfi_init },
++	{ .compatible = "rockchip,rk3576-dfi", .data = rk3576_dfi_init },
+	{ .compatible = "rockchip,rk3588-dfi", .data = rk3588_dfi_init },
++	{ .compatible = "rockchip,rv1126-dfi", .data = px30_dfi_init },
++	{ .compatible = "rockchip,rv1126b-dfi", .data = rv1126b_dfi_init },
+	{ },
+ };
+
+@@ -781,9 +1277,10 @@ static int rockchip_dfi_probe(struct platform_device *pdev)
+	if (!dfi)
+		return -ENOMEM;
+
++	/* Not all variants have a resource 0 (e.g. those using pure GRF), so we use optional */
+	dfi->regs = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(dfi->regs))
+-		return PTR_ERR(dfi->regs);
++		dfi->regs = NULL; /* Some legacy SoCs don't use this */
+
+	node = of_parse_phandle(np, "rockchip,pmu", 0);
+	if (!node)
+@@ -813,9 +1310,12 @@ static int rockchip_dfi_probe(struct platform_device *pdev)
+		return PTR_ERR(dfi->edev);
+	}
+
+-	ret = rockchip_ddr_perf_init(dfi);
+-	if (ret)
+-		return ret;
++	/* Only initialize perf counters if we are using the standard DFI ops */
++	if (dfi->desc.ops == &rockchip_dfi_ops) {
++		ret = rockchip_ddr_perf_init(dfi);
++		if (ret)
++			return ret;
++	}
+
+	platform_set_drvdata(pdev, dfi);
+
+diff --git a/include/soc/rockchip/rockchip_grf.h b/include/soc/rockchip/rockchip_grf.h
+index e46fd72aea..0f94a7d530 100644
+--- a/include/soc/rockchip/rockchip_grf.h
++++ b/include/soc/rockchip/rockchip_grf.h
+@@ -8,11 +8,16 @@
+
+ /* Rockchip DDRTYPE defines */
+ enum {
++	ROCKCHIP_DDRTYPE_DDR4	= 0,
++	ROCKCHIP_DDRTYPE_DDR2	= 2,
+	ROCKCHIP_DDRTYPE_DDR3	= 3,
+	ROCKCHIP_DDRTYPE_LPDDR2	= 5,
+	ROCKCHIP_DDRTYPE_LPDDR3	= 6,
+	ROCKCHIP_DDRTYPE_LPDDR4	= 7,
+	ROCKCHIP_DDRTYPE_LPDDR4X = 8,
++	ROCKCHIP_DDRTYPE_LPDDR5	= 9,
++	ROCKCHIP_DDRTYPE_DDR5	= 10,
++	ROCKCHIP_DDRTYPE_UNUSED = 0xFF
+ };
+
+ #endif /* __SOC_ROCKCHIP_GRF_H */
+diff --git a/include/soc/rockchip/rk3588_grf.h b/include/soc/rockchip/rk3588_grf.h
+index 630b35a550..9a5172e010 100644
+--- a/include/soc/rockchip/rk3588_grf.h
++++ b/include/soc/rockchip/rk3588_grf.h
+@@ -14,5 +14,9 @@
+
+ #define RK3588_PMUGRF_OS_REG4           0x210
+ #define RK3588_PMUGRF_OS_REG5           0x214
++#define RK3588_PMUGRF_OS_REG6			0x218
++#define RK3588_PMUGRF_OS_REG6_LP5_BANK_MODE		GENMASK(2, 1)
++/* Whether the LPDDR5 is in 2:1 (= 0) or 4:1 (= 1) CKR a.k.a. DQS mode */
++#define RK3588_PMUGRF_OS_REG6_LP5_CKR			BIT(0)
+
+ #endif /* __SOC_RK3588_GRF_H */
+diff --git a/include/linux/hw_bitfield.h b/include/linux/hw_bitfield.h
+new file mode 100644
+index 0000000000..df202e167c
+--- /dev/null
++++ b/include/linux/hw_bitfield.h
+@@ -0,0 +1,62 @@
++/* SPDX-License-Identifier: GPL-2.0-or-later */
++/*
++ * Copyright (C) 2025, Collabora Ltd.
++ */
++
++#ifndef _LINUX_HW_BITFIELD_H
++#define _LINUX_HW_BITFIELD_H
++
++#include <linux/bitfield.h>
++#include <linux/build_bug.h>
++#include <linux/limits.h>
++
++/**
++ * FIELD_PREP_WM16() - prepare a bitfield element with a mask in the upper half
++ * @_mask: shifted mask defining the field's length and position
++ * @_val:  value to put in the field
++ *
++ * FIELD_PREP_WM16() masks and shifts up the value, as well as bitwise ORs the
++ * result with the mask shifted up by 16.
++ *
++ * This is useful for a common design of hardware registers where the upper
++ * 16-bit half of a 32-bit register is used as a write-enable mask. In such a
++ * register, a bit in the lower half is only updated if the corresponding bit
++ * in the upper half is high.
++ */
++#define FIELD_PREP_WM16(_mask, _val)					     \
++	({								     \
++		typeof(_val) __val = _val;				     \
++		typeof(_mask) __mask = _mask;				     \
++		__BF_FIELD_CHECK(__mask, ((u16)0U), __val,		     \
++				 "HWORD_UPDATE: ");			     \
++		(((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) | \
++		((__mask) << 16);					     \
++	})
++
++/**
++ * FIELD_PREP_WM16_CONST() - prepare a constant bitfield element with a mask in
++ *                           the upper half
++ * @_mask: shifted mask defining the field's length and position
++ * @_val:  value to put in the field
++ *
++ * FIELD_PREP_WM16_CONST() masks and shifts up the value, as well as bitwise ORs
++ * the result with the mask shifted up by 16.
++ *
++ * This is useful for a common design of hardware registers where the upper
++ * 16-bit half of a 32-bit register is used as a write-enable mask. In such a
++ * register, a bit in the lower half is only updated if the corresponding bit
++ * in the upper half is high.
++ *
++ * Unlike FIELD_PREP_WM16(), this is a constant expression and can therefore
++ * be used in initializers. Error checking is less comfortable for this
++ * version.
++ */
++#define FIELD_PREP_WM16_CONST(_mask, _val)				 \
++	(								 \
++		FIELD_PREP_CONST(_mask, _val) |				 \
++		(BUILD_BUG_ON_ZERO(const_true((u64)(_mask) > U16_MAX)) + \
++		 ((_mask) << 16))					 \
++	)
++
++
++#endif /* _LINUX_HW_BITFIELD_H */
+--
+2.25.1
diff --git a/projects/Rockchip/devices/RK322X/patches/linux/default/linux-4003-ssv-6051-driver.patch b/projects/Rockchip/devices/RK322X/patches/linux/default/linux-4003-ssv-6051-driver.patch
new file mode 100644
index 0000000000..7f4e0e5840
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/patches/linux/default/linux-4003-ssv-6051-driver.patch
@@ -0,0 +1,49481 @@
+From 3f30a652fb3e6ead83f65312d0240d5c9ea8c340 Mon Sep 17 00:00:00 2001
+From: Paolo Sabatino <paolo.sabatino@gmail.com>
+Date: Wed, 2 Nov 2022 15:40:06 +0000
+Subject: [PATCH] add ssv6xxx wifi driver
+
+---
+ drivers/net/wireless/Kconfig                  |     1 +
+ drivers/net/wireless/Makefile                 |     1 +
+ drivers/net/wireless/ssv6051/Kconfig          |    11 +
+ drivers/net/wireless/ssv6051/Makefile         |    26 +
+ drivers/net/wireless/ssv6051/Makefile.bak     |   107 +
+ .../ssv6051/firmware/ssv6051-wifi.cfg         |    91 +
+ drivers/net/wireless/ssv6051/hci/hctrl.h      |   178 +
+ drivers/net/wireless/ssv6051/hci/ssv_hci.c    |   967 +
+ drivers/net/wireless/ssv6051/hci/ssv_hci.h    |    77 +
+ drivers/net/wireless/ssv6051/hwif/hwif.h      |    84 +
+ drivers/net/wireless/ssv6051/hwif/sdio/sdio.c |  1254 ++
+ .../net/wireless/ssv6051/hwif/sdio/sdio_def.h |    80 +
+ drivers/net/wireless/ssv6051/include/cabrio.h |    28 +
+ .../net/wireless/ssv6051/include/ssv6200.h    |    76 +
+ .../wireless/ssv6051/include/ssv6200_aux.h    | 18221 ++++++++++++++++
+ .../wireless/ssv6051/include/ssv6200_common.h |   452 +
+ .../ssv6051/include/ssv6200_configuration.h   |   317 +
+ .../wireless/ssv6051/include/ssv6200_reg.h    |  9694 ++++++++
+ .../ssv6051/include/ssv6200_reg_sim.h         |   176 +
+ .../net/wireless/ssv6051/include/ssv_cfg.h    |    60 +
+ .../ssv6051/include/ssv_firmware_version.h    |    25 +
+ .../wireless/ssv6051/include/ssv_version.h    |    12 +
+ .../net/wireless/ssv6051/platform-config.mak  |    97 +
+ drivers/net/wireless/ssv6051/rules.mak        |    19 +
+ drivers/net/wireless/ssv6051/smac/ampdu.c     |  2111 ++
+ drivers/net/wireless/ssv6051/smac/ampdu.h     |   215 +
+ drivers/net/wireless/ssv6051/smac/ap.c        |   598 +
+ drivers/net/wireless/ssv6051/smac/ap.h        |    41 +
+ drivers/net/wireless/ssv6051/smac/dev.c       |  3880 ++++
+ drivers/net/wireless/ssv6051/smac/dev.h       |   445 +
+ drivers/net/wireless/ssv6051/smac/dev_tbl.h   |   141 +
+ drivers/net/wireless/ssv6051/smac/drv_comm.h  |    61 +
+ drivers/net/wireless/ssv6051/smac/efuse.c     |   334 +
+ drivers/net/wireless/ssv6051/smac/efuse.h     |    40 +
+ drivers/net/wireless/ssv6051/smac/init.c      |  1347 ++
+ drivers/net/wireless/ssv6051/smac/init.h      |    23 +
+ drivers/net/wireless/ssv6051/smac/lib.c       |    33 +
+ drivers/net/wireless/ssv6051/smac/lib.h       |    23 +
+ .../net/wireless/ssv6051/smac/linux_80211.h   |    24 +
+ drivers/net/wireless/ssv6051/smac/p2p.c       |   305 +
+ drivers/net/wireless/ssv6051/smac/p2p.h       |    58 +
+ drivers/net/wireless/ssv6051/smac/sar.c       |   208 +
+ drivers/net/wireless/ssv6051/smac/sar.h       |    63 +
+ drivers/net/wireless/ssv6051/smac/sec.h       |    52 +
+ drivers/net/wireless/ssv6051/smac/smartlink.c |   340 +
+ .../wireless/ssv6051/smac/ssv6xxx_debugfs.c   |   223 +
+ .../wireless/ssv6051/smac/ssv6xxx_debugfs.h   |    27 +
+ .../net/wireless/ssv6051/smac/ssv_cfgvendor.c |  1384 ++
+ .../net/wireless/ssv6051/smac/ssv_cfgvendor.h |   247 +
+ drivers/net/wireless/ssv6051/smac/ssv_ht_rc.c |   546 +
+ drivers/net/wireless/ssv6051/smac/ssv_ht_rc.h |    31 +
+ drivers/net/wireless/ssv6051/smac/ssv_pm.c    |    19 +
+ drivers/net/wireless/ssv6051/smac/ssv_pm.h    |    20 +
+ drivers/net/wireless/ssv6051/smac/ssv_rc.c    |  1716 ++
+ drivers/net/wireless/ssv6051/smac/ssv_rc.h    |    50 +
+ .../net/wireless/ssv6051/smac/ssv_rc_common.h |   175 +
+ .../wireless/ssv6051/ssv6051-generic-wlan.c   |    76 +
+ .../net/wireless/ssv6051/ssvdevice/ssv_cmd.c  |  1765 ++
+ .../net/wireless/ssv6051/ssvdevice/ssv_cmd.h  |    50 +
+ .../wireless/ssv6051/ssvdevice/ssvdevice.c    |   256 +
+ 60 files changed, 48983 insertions(+)
+ create mode 100644 drivers/net/wireless/ssv6051/Kconfig
+ create mode 100644 drivers/net/wireless/ssv6051/Makefile
+ create mode 100644 drivers/net/wireless/ssv6051/Makefile.bak
+ create mode 100644 drivers/net/wireless/ssv6051/firmware/ssv6051-wifi.cfg
+ create mode 100644 drivers/net/wireless/ssv6051/hci/hctrl.h
+ create mode 100644 drivers/net/wireless/ssv6051/hci/ssv_hci.c
+ create mode 100644 drivers/net/wireless/ssv6051/hci/ssv_hci.h
+ create mode 100644 drivers/net/wireless/ssv6051/hwif/hwif.h
+ create mode 100644 drivers/net/wireless/ssv6051/hwif/sdio/sdio.c
+ create mode 100644 drivers/net/wireless/ssv6051/hwif/sdio/sdio_def.h
+ create mode 100644 drivers/net/wireless/ssv6051/include/cabrio.h
+ create mode 100644 drivers/net/wireless/ssv6051/include/ssv6200.h
+ create mode 100644 drivers/net/wireless/ssv6051/include/ssv6200_aux.h
+ create mode 100644 drivers/net/wireless/ssv6051/include/ssv6200_common.h
+ create mode 100644 drivers/net/wireless/ssv6051/include/ssv6200_configuration.h
+ create mode 100644 drivers/net/wireless/ssv6051/include/ssv6200_reg.h
+ create mode 100644 drivers/net/wireless/ssv6051/include/ssv6200_reg_sim.h
+ create mode 100644 drivers/net/wireless/ssv6051/include/ssv_cfg.h
+ create mode 100644 drivers/net/wireless/ssv6051/include/ssv_firmware_version.h
+ create mode 100644 drivers/net/wireless/ssv6051/include/ssv_version.h
+ create mode 100644 drivers/net/wireless/ssv6051/platform-config.mak
+ create mode 100644 drivers/net/wireless/ssv6051/rules.mak
+ create mode 100644 drivers/net/wireless/ssv6051/smac/ampdu.c
+ create mode 100644 drivers/net/wireless/ssv6051/smac/ampdu.h
+ create mode 100644 drivers/net/wireless/ssv6051/smac/ap.c
+ create mode 100644 drivers/net/wireless/ssv6051/smac/ap.h
+ create mode 100644 drivers/net/wireless/ssv6051/smac/dev.c
+ create mode 100644 drivers/net/wireless/ssv6051/smac/dev.h
+ create mode 100644 drivers/net/wireless/ssv6051/smac/dev_tbl.h
+ create mode 100644 drivers/net/wireless/ssv6051/smac/drv_comm.h
+ create mode 100644 drivers/net/wireless/ssv6051/smac/efuse.c
+ create mode 100644 drivers/net/wireless/ssv6051/smac/efuse.h
+ create mode 100644 drivers/net/wireless/ssv6051/smac/init.c
+ create mode 100644 drivers/net/wireless/ssv6051/smac/init.h
+ create mode 100644 drivers/net/wireless/ssv6051/smac/lib.c
+ create mode 100644 drivers/net/wireless/ssv6051/smac/lib.h
+ create mode 100644 drivers/net/wireless/ssv6051/smac/linux_80211.h
+ create mode 100644 drivers/net/wireless/ssv6051/smac/p2p.c
+ create mode 100644 drivers/net/wireless/ssv6051/smac/p2p.h
+ create mode 100644 drivers/net/wireless/ssv6051/smac/sar.c
+ create mode 100644 drivers/net/wireless/ssv6051/smac/sar.h
+ create mode 100644 drivers/net/wireless/ssv6051/smac/sec.h
+ create mode 100644 drivers/net/wireless/ssv6051/smac/smartlink.c
+ create mode 100644 drivers/net/wireless/ssv6051/smac/ssv6xxx_debugfs.c
+ create mode 100644 drivers/net/wireless/ssv6051/smac/ssv6xxx_debugfs.h
+ create mode 100644 drivers/net/wireless/ssv6051/smac/ssv_cfgvendor.c
+ create mode 100644 drivers/net/wireless/ssv6051/smac/ssv_cfgvendor.h
+ create mode 100644 drivers/net/wireless/ssv6051/smac/ssv_ht_rc.c
+ create mode 100644 drivers/net/wireless/ssv6051/smac/ssv_ht_rc.h
+ create mode 100644 drivers/net/wireless/ssv6051/smac/ssv_pm.c
+ create mode 100644 drivers/net/wireless/ssv6051/smac/ssv_pm.h
+ create mode 100644 drivers/net/wireless/ssv6051/smac/ssv_rc.c
+ create mode 100644 drivers/net/wireless/ssv6051/smac/ssv_rc.h
+ create mode 100644 drivers/net/wireless/ssv6051/smac/ssv_rc_common.h
+ create mode 100644 drivers/net/wireless/ssv6051/ssv6051-generic-wlan.c
+ create mode 100644 drivers/net/wireless/ssv6051/ssvdevice/ssv_cmd.c
+ create mode 100644 drivers/net/wireless/ssv6051/ssvdevice/ssv_cmd.h
+ create mode 100644 drivers/net/wireless/ssv6051/ssvdevice/ssvdevice.c
+
+diff --git a/drivers/net/wireless/Kconfig b/drivers/net/wireless/Kconfig
+index de5e37846397..aa2cac9abdd3 100644
+--- a/drivers/net/wireless/Kconfig
++++ b/drivers/net/wireless/Kconfig
+@@ -18,6 +18,7 @@ menuconfig WLAN
+
+ if WLAN
+
++source "drivers/net/wireless/ssv6051/Kconfig"
+ source "drivers/net/wireless/admtek/Kconfig"
+ source "drivers/net/wireless/ath/Kconfig"
+ source "drivers/net/wireless/atmel/Kconfig"
+diff --git a/drivers/net/wireless/Makefile b/drivers/net/wireless/Makefile
+index 92ffd2cef51c..8b56a42e97a6 100644
+--- a/drivers/net/wireless/Makefile
++++ b/drivers/net/wireless/Makefile
+@@ -3,6 +3,7 @@
+ # Makefile for the Linux Wireless network device drivers.
+ #
+
++obj-$(CONFIG_SSV6051) += ssv6051/
+ obj-$(CONFIG_WLAN_VENDOR_ADMTEK) += admtek/
+ obj-$(CONFIG_WLAN_VENDOR_ATH) += ath/
+ obj-$(CONFIG_WLAN_VENDOR_ATMEL) += atmel/
+diff --git a/drivers/net/wireless/ssv6051/Kconfig b/drivers/net/wireless/ssv6051/Kconfig
+new file mode 100644
+index 000000000000..7706ad52ed7b
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/Kconfig
+@@ -0,0 +1,11 @@
++# SPDX-License-Identifier: GPL-2.0-only
++config SSV6051
++        tristate "South Silicon Valley (ssv) 6051 family WLAN support"
++	depends on MAC80211
++	depends on (MMC = y)
++        default n
++	select FW_LOADER
++        help
++		Enable South Silicon Valley (SSV) 6051 family support.
++
++
+diff --git a/drivers/net/wireless/ssv6051/Makefile b/drivers/net/wireless/ssv6051/Makefile
+new file mode 100644
+index 000000000000..985d730f3d50
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/Makefile
+@@ -0,0 +1,26 @@
++# SPDX-License-Identifier: ISC
++
++include $(src)/platform-config.mak
++
++ccflags-y += \
++	-I $(srctree)/$(src) \
++        -I $(srctree)/$(src)/include
++
++obj-$(CONFIG_SSV6051) += ssv6051.o
++ssv6051-objs += \
++	ssv6051-generic-wlan.o \
++	ssvdevice/ssvdevice.o \
++	ssvdevice/ssv_cmd.o \
++	hci/ssv_hci.o \
++	smac/init.o \
++	smac/dev.o \
++	smac/ssv_rc.o \
++	smac/ssv_ht_rc.o \
++	smac/ap.o \
++	smac/ampdu.o \
++	smac/efuse.o \
++	smac/ssv_pm.o \
++	smac/sar.o \
++	smac/ssv_cfgvendor.o \
++	hwif/sdio/sdio.o
++
+diff --git a/drivers/net/wireless/ssv6051/Makefile.bak b/drivers/net/wireless/ssv6051/Makefile.bak
+new file mode 100644
+index 000000000000..2733fa4dd3b7
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/Makefile.bak
+@@ -0,0 +1,107 @@
++KMODULE_NAME=ssv6051
++
++KBUILD_TOP := $(PWD)
++
++ifeq ($(KERNELRELEASE),)
++
++KVERS_UNAME ?= $(shell uname -r)
++KVERS_ARCH ?= $(shell arch)
++
++KBUILD ?= $(shell readlink -f /lib/modules/$(KVERS_UNAME)/build)
++
++ifeq (,$(KBUILD))
++$(error kernel build tree not found - set KBUILD to configured kernel)
++endif
++
++#KCONFIG := $(KBUILD)/config
++#ifeq (,$(wildcard $(KCONFIG)))
++#$(error No .config found in $(KBUILD), set KBUILD to configured kernel)
++#endif
++
++ifneq (,$(wildcard $(KBUILD)/include/linux/version.h))
++ifneq (,$(wildcard $(KBUILD)/include/generated/uapi/linux/version.h))
++$(error Multiple copied of version.h found, clean build tree)
++endif
++endif
++
++# Kernel Makefile doesn't always know the exact kernel version, so we
++# get it from the kernel headers instead and pass it to make.
++VERSION_H := $(KBUILD)/include/generated/utsrelease.h
++ifeq (,$(wildcard $(VERSION_H)))
++VERSION_H := $(KBUILD)/include/linux/utsrelease.h
++endif
++ifeq (,$(wildcard $(VERSION_H)))
++VERSION_H := $(KBUILD)/include/linux/version.h
++endif
++ifeq (,$(wildcard $(VERSION_H)))
++$(error Please run 'make modules_prepare' in $(KBUILD))
++endif
++
++KVERS := $(shell sed -ne 's/"//g;s/^\#define UTS_RELEASE //p' $(VERSION_H))
++
++ifeq (,$(KVERS))
++$(error Cannot find UTS_RELEASE in $(VERSION_H), please report)
++endif
++
++INST_DIR = /lib/modules/$(KVERS)/misc
++
++#include $(KCONFIG)
++
++endif
++
++include $(KBUILD_TOP)/platform-config.mak
++
++EXTRA_CFLAGS := -I$(KBUILD_TOP) -I$(KBUILD_TOP)/include #-Wno-error=missing-attributes
++DEF_PARSER_H = $(KBUILD_TOP)/include/ssv_conf_parser.h
++
++OBJS := ssvdevice/ssvdevice.c \
++	ssvdevice/ssv_cmd.c \
++	hci/ssv_hci.c \
++	smac/init.c \
++	smac/dev.c \
++	smac/ssv_rc.c \
++	smac/ssv_ht_rc.c \
++	smac/ap.c \
++	smac/ampdu.c \
++	smac/efuse.c \
++	smac/ssv_pm.c \
++	smac/sar.c \
++	hwif/sdio/sdio.c \
++	ssv6051-generic-wlan.c
++
++ifeq ($(findstring -DCONFIG_SSV6XXX_DEBUGFS, $(ccflags-y)), -DCONFIG_SSV6XXX_DEBUGFS)
++OBJS +=	smac/ssv6xxx_debugfs.c
++endif
++
++ifeq ($(findstring -DCONFIG_SSV_VENDOR_EXT_SUPPORT, $(ccflags-y)), -DCONFIG_SSV_VENDOR_EXT_SUPPORT)
++OBJS +=	smac/ssv_cfgvendor.c
++endif
++
++ifeq ($(findstring -DCONFIG_SSV_SMARTLINK, $(ccflags-y)), -DCONFIG_SSV_SMARTLINK)
++OBJS += smac/smartlink.c
++endif
++
++$(KMODULE_NAME)-y += $(ASMS:.S=.o)
++$(KMODULE_NAME)-y += $(OBJS:.c=.o)
++
++obj-$(CONFIG_SSV6200_CORE) += $(KMODULE_NAME).o
++
++all: modules
++
++modules:
++	ARCH=arm $(MAKE) -C $(KBUILD) M=$(KBUILD_TOP)
++
++clean:
++	find -type f -iname '*.o' -exec rm {} \;
++	find -type f -iname '*.o.cmd' -exec rm {} \;
++	rm -f *.o *.ko .*.cmd *.mod.c *.symvers modules.order
++	rm -rf .tmp_versions
++
++install: modules
++	mkdir -p -m 755 $(DESTDIR)$(INST_DIR)
++	install -m 0644 $(KMODULE_NAME).ko $(DESTDIR)$(INST_DIR)
++ifndef DESTDIR
++	-/sbin/depmod -a $(KVERS)
++endif
++
++.PHONY: all modules clean install
+diff --git a/drivers/net/wireless/ssv6051/firmware/ssv6051-wifi.cfg b/drivers/net/wireless/ssv6051/firmware/ssv6051-wifi.cfg
+new file mode 100644
+index 000000000000..c072960f6dea
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/firmware/ssv6051-wifi.cfg
+@@ -0,0 +1,91 @@
++############################################################
++# ROCKCHIP RK3X28 & RK322X
++# WIFI-CONFIGURATION
++##################################################
++
++##################################################
++# Firmware setting
++# Priority.1 insmod parameter "cfgfirmwarepath"
++# Priority.2 firmware_path
++# Priority.3 default firmware
++##################################################
++firmware_path = /vendor/etc/firmware/
++
++############################################################
++# MAC address
++#
++# Priority 1. From wifi.cfg [ hw_mac & hw_mac_2 ]
++#
++# Priority 2. From e-fuse[ON/OFF switch by wifi.cfg]
++#
++# Priority 3. From insert module parameter
++#
++# Priority 4. From external file path
++#   path only support some special charater "_" ":" "/" "." "-"
++#
++# Priority 5. Default[Software mode]
++#
++#   0. => 00:33:33:33:33:33
++#   1. => Always random
++#   2. => First random and write to file[Default path mac_output_path]
++#
++############################################################
++ignore_efuse_mac = 0
++#mac_address_path = /xxxx/xxxx
++mac_address_mode = 2
++mac_output_path = /data/wifimac
++
++##################################################
++# Hardware setting
++#
++#volt regulator(DCDC-0 LDO-1)
++#
++##################################################
++xtal_clock = 24
++volt_regulator = 1
++
++##################################################
++# Default channel after wifi on
++# value range: [1 ~ 14]
++##################################################
++def_chan = 6
++##################################################
++# Hardware Capability Settings:
++##################################################
++hw_cap_ht = on
++hw_cap_gf = off
++hw_cap_2ghz = on
++hw_cap_5ghz = off
++hw_cap_security = on
++hw_cap_sgi_20 = on
++hw_cap_sgi_40 = off
++hw_cap_ap = on
++hw_cap_p2p = on
++hw_cap_ampdu_rx = on
++hw_cap_ampdu_tx = on
++use_wpa2_only = 1
++##################################################
++# TX power level setting [0-14]
++# The larger the number the smaller the TX power
++# 0 - The maximum power
++# 1 level = -0.5db
++#
++# 6051Z .. 4 or 4
++# 6051Q .. 2 or 5
++# 6051P .. 0 or 0
++#
++##################################################
++#wifi_tx_gain_level_b = 2
++#wifi_tx_gain_level_gn = 5
++################################################
++# Signal strength control
++# rssi control
++#rssi_ctl = 10
++
++
++##################################################
++# Import extenal configuration(UP to 64 groups)
++# example:
++#    register = CE010010:91919191
++#    register = 00CC0010:00091919
++##################################################
+diff --git a/drivers/net/wireless/ssv6051/hci/hctrl.h b/drivers/net/wireless/ssv6051/hci/hctrl.h
+new file mode 100644
+index 000000000000..95218c8040e7
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/hci/hctrl.h
+@@ -0,0 +1,178 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation, either version 3 of the License, or
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _HCTRL_H_
++#define _HCTRL_H_
++#define MAX_FRAME_SIZE 4096
++#define SSV6XXX_INT_RX 0x00000001
++#define SSV6XXX_INT_TX 0x00000002
++#define SSV6XXX_INT_SOC 0x00000004
++#define SSV6XXX_INT_LOW_EDCA_0 0x00000008
++#define SSV6XXX_INT_LOW_EDCA_1 0x00000010
++#define SSV6XXX_INT_LOW_EDCA_2 0x00000020
++#define SSV6XXX_INT_LOW_EDCA_3 0x00000040
++#define SSV6XXX_INT_RESOURCE_LOW 0x00000080
++#define IFDEV(_ct) ((_ct)->shi->dev)
++#define IFOPS(_ct) ((_ct)->shi->if_ops)
++#define HCI_REG_READ(_ct,_adr,_val) IFOPS(_ct)->readreg(IFDEV(_ct), _adr, _val)
++#define HCI_REG_WRITE(_ct,_adr,_val) IFOPS(_ct)->writereg(IFDEV(_ct), _adr, _val)
++#define HCI_REG_SET_BITS(_ct,_reg,_set,_clr) \
++{ \
++    u32 _regval; \
++    if(HCI_REG_READ(_ct, _reg, &_regval)); \
++    _regval &= ~(_clr); \
++    _regval |= (_set); \
++    if(HCI_REG_WRITE(_ct, _reg, _regval)); \
++}
++#define IF_SEND(_ct,_bf,_len,_qid) IFOPS(_ct)->write(IFDEV(_ct), _bf, _len, _qid)
++#define IF_RECV(ct,bf,len) IFOPS(ct)->read(IFDEV(ct), bf, len)
++#define HCI_LOAD_FW(ct,_bf,open) IFOPS(ct)->load_fw(IFDEV(ct), _bf, open)
++#define HCI_IFC_RESET(ct) IFOPS(ct)->interface_reset(IFDEV(ct))
++struct ssv6xxx_hci_ctrl {
++	struct ssv6xxx_hci_info *shi;
++	spinlock_t int_lock;
++	u32 int_status;
++	u32 int_mask;
++	struct mutex txq_mask_lock;
++	u32 txq_mask;
++	struct ssv_hw_txq hw_txq[SSV_HW_TXQ_NUM];
++	struct mutex hci_mutex;
++	bool hci_start;
++	struct sk_buff *rx_buf;
++	u32 rx_pkt;
++	struct workqueue_struct *hci_work_queue;
++	struct work_struct hci_rx_work;
++	struct work_struct hci_tx_work;
++	u32 read_rs0_info_fail;
++	u32 read_rs1_info_fail;
++	u32 rx_work_running;
++	u32 isr_running;
++	u32 xmit_running;
++	u32 isr_summary_eable;
++	u32 isr_routine_time;
++	u32 isr_tx_time;
++	u32 isr_rx_time;
++	u32 isr_idle_time;
++	u32 isr_rx_idle_time;
++	u32 isr_miss_cnt;
++	unsigned long prev_isr_jiffes;
++	unsigned long prev_rx_isr_jiffes;
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	struct dentry *debugfs_dir;
++	u32 isr_mib_enable;
++	u32 isr_mib_reset;
++	long long isr_total_time;
++	long long isr_tx_io_time;
++	long long isr_rx_io_time;
++	u32 isr_rx_io_count;
++	u32 isr_tx_io_count;
++	long long isr_rx_proc_time;
++#ifdef CONFIG_IRQ_DEBUG_COUNT
++	bool irq_enable;
++	u32 irq_count;
++	u32 invalid_irq_count;
++	u32 tx_irq_count;
++	u32 real_tx_irq_count;
++	u32 rx_irq_count;
++	u32 irq_rx_pkt_count;
++	u32 irq_tx_pkt_count;
++#endif
++#endif
++};
++struct ssv6xxx_hci_txq_info {
++	u32 tx_use_page:8;
++	u32 tx_use_id:6;
++	u32 txq0_size:4;
++	u32 txq1_size:4;
++	u32 txq2_size:5;
++	u32 txq3_size:5;
++};
++struct ssv6xxx_hci_txq_info2 {
++	u32 tx_use_page:9;
++	u32 tx_use_id:8;
++	u32 txq4_size:4;
++	u32 rsvd:11;
++};
++struct ssv6xxx_hw_resource {
++	u32 free_tx_page;
++	u32 free_tx_id;
++	int max_tx_frame[SSV_HW_TXQ_NUM];
++};
++static inline void ssv6xxx_hwif_irq_request(struct ssv6xxx_hci_ctrl *hctrl,
++					    irq_handler_t irq_handler)
++{
++	if (hctrl->shi->if_ops->irq_request)
++		hctrl->shi->if_ops->irq_request(IFDEV(hctrl), irq_handler,
++						hctrl);
++}
++
++static inline void ssv6xxx_hwif_irq_enable(struct ssv6xxx_hci_ctrl *hctrl)
++{
++	if (hctrl->shi->if_ops->irq_enable)
++		hctrl->shi->if_ops->irq_enable(IFDEV(hctrl));
++}
++
++static inline void ssv6xxx_hwif_irq_disable(struct ssv6xxx_hci_ctrl *hctrl)
++{
++	if (hctrl->shi->if_ops->irq_disable)
++		hctrl->shi->if_ops->irq_disable(IFDEV(hctrl), false);
++}
++
++static inline int ssv6xxx_hwif_irq_getstatus(struct ssv6xxx_hci_ctrl *hctrl,
++					     int *status)
++{
++	if (hctrl->shi->if_ops->irq_getstatus)
++		return hctrl->shi->if_ops->irq_getstatus(IFDEV(hctrl), status);
++	return 0;
++}
++
++static inline void ssv6xxx_hwif_irq_setmask(struct ssv6xxx_hci_ctrl *hctrl,
++					    int mask)
++{
++	if (hctrl->shi->if_ops->irq_setmask)
++		hctrl->shi->if_ops->irq_setmask(IFDEV(hctrl), mask);
++}
++
++static inline void ssv6xxx_hwif_irq_trigger(struct ssv6xxx_hci_ctrl *hctrl)
++{
++	if (hctrl->shi->if_ops->irq_trigger)
++		hctrl->shi->if_ops->irq_trigger(IFDEV(hctrl));
++}
++
++static inline void ssv6xxx_hwif_pmu_wakeup(struct ssv6xxx_hci_ctrl *hctrl)
++{
++	if (hctrl->shi->if_ops->pmu_wakeup)
++		hctrl->shi->if_ops->pmu_wakeup(IFDEV(hctrl));
++}
++
++static inline int ssv6xxx_hwif_write_sram(struct ssv6xxx_hci_ctrl *hctrl,
++					  u32 addr, u8 * data, u32 size)
++{
++	if (hctrl->shi->if_ops->write_sram)
++		return hctrl->shi->if_ops->write_sram(IFDEV(hctrl), addr, data,
++						      size);
++	return 0;
++}
++
++#define HCI_IRQ_REQUEST(ct,hdle) ssv6xxx_hwif_irq_request(ct, hdle)
++#define HCI_IRQ_ENABLE(ct) ssv6xxx_hwif_irq_enable(ct)
++#define HCI_IRQ_DISABLE(ct) ssv6xxx_hwif_irq_disable(ct)
++#define HCI_IRQ_STATUS(ct,sts) ssv6xxx_hwif_irq_getstatus(ct, sts)
++#define HCI_IRQ_SET_MASK(ct,mk) ssv6xxx_hwif_irq_setmask(ct, mk)
++#define HCI_IRQ_TRIGGER(ct) ssv6xxx_hwif_irq_trigger(ct)
++#define HCI_PMU_WAKEUP(ct) ssv6xxx_hwif_pmu_wakeup(ct)
++#define HCI_SRAM_WRITE(_ct,_adr,_dat,_size) ssv6xxx_hwif_write_sram(_ct, _adr, _dat, _size);
++#endif
+diff --git a/drivers/net/wireless/ssv6051/hci/ssv_hci.c b/drivers/net/wireless/ssv6051/hci/ssv_hci.c
+new file mode 100644
+index 000000000000..9fedbeb55754
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/hci/ssv_hci.c
+@@ -0,0 +1,967 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation, either version 3 of the License, or
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <linux/kernel.h>
++#include <linux/version.h>
++#include <linux/module.h>
++#include <linux/delay.h>
++#include <linux/jiffies.h>
++#include <ssv6200.h>
++#include "hctrl.h"
++
++static struct ssv6xxx_hci_ctrl *ctrl_hci = NULL;
++
++struct sk_buff *ssv_skb_alloc(s32 len)
++{
++	struct sk_buff *skb;
++	skb = __dev_alloc_skb(len + SSV6200_ALLOC_RSVD, GFP_KERNEL);
++	if (skb != NULL) {
++		skb_reserve(skb, SSV_SKB_info_size);
++	}
++	return skb;
++}
++
++void ssv_skb_free(struct sk_buff *skb)
++{
++	dev_kfree_skb_any(skb);
++}
++
++static int ssv6xxx_hci_irq_enable(void)
++{
++	HCI_IRQ_SET_MASK(ctrl_hci, ~(ctrl_hci->int_mask));
++	HCI_IRQ_ENABLE(ctrl_hci);
++	return 0;
++}
++
++static int ssv6xxx_hci_irq_disable(void)
++{
++	HCI_IRQ_SET_MASK(ctrl_hci, 0xffffffff);
++	HCI_IRQ_DISABLE(ctrl_hci);
++	return 0;
++}
++
++static void ssv6xxx_hci_irq_register(u32 irq_mask)
++{
++	unsigned long flags;
++	u32 regval;
++	mutex_lock(&ctrl_hci->hci_mutex);
++	spin_lock_irqsave(&ctrl_hci->int_lock, flags);
++	ctrl_hci->int_mask |= irq_mask;
++	regval = ~ctrl_hci->int_mask;
++	spin_unlock_irqrestore(&ctrl_hci->int_lock, flags);
++	smp_mb();
++	HCI_IRQ_SET_MASK(ctrl_hci, regval);
++	mutex_unlock(&ctrl_hci->hci_mutex);
++}
++
++static inline u32 ssv6xxx_hci_get_int_bitno(int txqid)
++{
++	if (txqid == SSV_HW_TXQ_NUM - 1)
++		return 1;
++	else
++		return txqid + 3;
++}
++
++static int ssv6xxx_hci_start(void)
++{
++	ssv6xxx_hci_irq_enable();
++	ctrl_hci->hci_start = true;
++	HCI_IRQ_TRIGGER(ctrl_hci);
++	return 0;
++}
++
++static int ssv6xxx_hci_stop(void)
++{
++	ssv6xxx_hci_irq_disable();
++	ctrl_hci->hci_start = false;
++	return 0;
++}
++
++static int ssv6xxx_hci_read_word(u32 addr, u32 * regval)
++{
++	int ret = HCI_REG_READ(ctrl_hci, addr, regval);
++	return ret;
++}
++
++static int ssv6xxx_hci_write_word(u32 addr, u32 regval)
++{
++	return HCI_REG_WRITE(ctrl_hci, addr, regval);
++}
++
++static int ssv6xxx_hci_load_fw(u8 * firmware_name, u8 openfile)
++{
++	return HCI_LOAD_FW(ctrl_hci, firmware_name, openfile);
++}
++
++static int ssv6xxx_hci_write_sram(u32 addr, u8 * data, u32 size)
++{
++	return HCI_SRAM_WRITE(ctrl_hci, addr, data, size);
++}
++
++static int ssv6xxx_hci_pmu_wakeup(void)
++{
++	HCI_PMU_WAKEUP(ctrl_hci);
++	return 0;
++}
++
++static int ssv6xxx_hci_interface_reset(void)
++{
++	HCI_IFC_RESET(ctrl_hci);
++	return 0;
++}
++
++static int ssv6xxx_hci_send_cmd(struct sk_buff *skb)
++{
++	int ret;
++	ret = IF_SEND(ctrl_hci, (void *)skb->data, skb->len, 0);
++
++	if (ret < 0)
++		pr_warn("ssv6xxx_hci_send_cmd failed, ret=%d\n", ret);
++
++	return ret;
++}
++
++static int ssv6xxx_hci_enqueue(struct sk_buff *skb, int txqid, u32 tx_flags)
++{
++	struct ssv_hw_txq *hw_txq;
++	unsigned long flags;
++	u32 status;
++	int qlen = 0;
++	BUG_ON(txqid >= SSV_HW_TXQ_NUM || txqid < 0);
++	if (txqid >= SSV_HW_TXQ_NUM || txqid < 0)
++		return -1;
++	hw_txq = &ctrl_hci->hw_txq[txqid];
++	hw_txq->tx_flags = tx_flags;
++	if (tx_flags & HCI_FLAGS_ENQUEUE_HEAD)
++		skb_queue_head(&hw_txq->qhead, skb);
++	else
++		skb_queue_tail(&hw_txq->qhead, skb);
++	qlen = (int)skb_queue_len(&hw_txq->qhead);
++	if (!(tx_flags & HCI_FLAGS_NO_FLOWCTRL)) {
++		if (skb_queue_len(&hw_txq->qhead) >= hw_txq->max_qsize) {
++			ctrl_hci->shi->hci_tx_flow_ctrl_cb(ctrl_hci->
++							   shi->tx_fctrl_cb_args,
++							   hw_txq->txq_no, true,
++							   2000);
++		}
++	}
++
++	mutex_lock(&ctrl_hci->hci_mutex);
++	spin_lock_irqsave(&ctrl_hci->int_lock, flags);
++	status = ctrl_hci->int_mask;
++
++	if ((ctrl_hci->int_mask & SSV6XXX_INT_RESOURCE_LOW) == 0) {
++		if (ctrl_hci->shi->if_ops->trigger_tx_rx == NULL) {
++			u32 regval;
++			ctrl_hci->int_mask |= SSV6XXX_INT_RESOURCE_LOW;
++			regval = ~ctrl_hci->int_mask;
++			spin_unlock_irqrestore(&ctrl_hci->int_lock, flags);
++			HCI_IRQ_SET_MASK(ctrl_hci, regval);
++			mutex_unlock(&ctrl_hci->hci_mutex);
++		} else {
++			ctrl_hci->int_status |= SSV6XXX_INT_RESOURCE_LOW;
++			smp_mb();
++			spin_unlock_irqrestore(&ctrl_hci->int_lock, flags);
++			mutex_unlock(&ctrl_hci->hci_mutex);
++			ctrl_hci->shi->if_ops->trigger_tx_rx(ctrl_hci->
++							     shi->dev);
++		}
++	} else {
++		spin_unlock_irqrestore(&ctrl_hci->int_lock, flags);
++		mutex_unlock(&ctrl_hci->hci_mutex);
++	}
++
++	return qlen;
++}
++
++static bool ssv6xxx_hci_is_txq_empty(int txqid)
++{
++	struct ssv_hw_txq *hw_txq;
++	BUG_ON(txqid >= SSV_HW_TXQ_NUM);
++	if (txqid >= SSV_HW_TXQ_NUM)
++		return false;
++	hw_txq = &ctrl_hci->hw_txq[txqid];
++	if (skb_queue_len(&hw_txq->qhead) <= 0)
++		return true;
++	return false;
++}
++
++static int ssv6xxx_hci_txq_flush(u32 txq_mask)
++{
++	struct ssv_hw_txq *hw_txq;
++	struct sk_buff *skb = NULL;
++	int txqid;
++	for (txqid = 0; txqid < SSV_HW_TXQ_NUM; txqid++) {
++		if ((txq_mask & (1 << txqid)) != 0)
++			continue;
++		hw_txq = &ctrl_hci->hw_txq[txqid];
++		while ((skb = skb_dequeue(&hw_txq->qhead))) {
++			ctrl_hci->shi->hci_tx_buf_free_cb(skb,
++							  ctrl_hci->
++							  shi->tx_buf_free_args);
++		}
++	}
++	return 0;
++}
++
++static int ssv6xxx_hci_txq_flush_by_sta(int aid)
++{
++	return 0;
++}
++
++static int ssv6xxx_hci_txq_pause(u32 txq_mask)
++{
++	struct ssv_hw_txq *hw_txq;
++	int txqid;
++	mutex_lock(&ctrl_hci->txq_mask_lock);
++	ctrl_hci->txq_mask |= (txq_mask & 0x1F);
++	for (txqid = 0; txqid < SSV_HW_TXQ_NUM; txqid++) {
++		if ((ctrl_hci->txq_mask & (1 << txqid)) == 0)
++			continue;
++		hw_txq = &ctrl_hci->hw_txq[txqid];
++		hw_txq->paused = true;
++	}
++	HCI_REG_SET_BITS(ctrl_hci, ADR_MTX_MISC_EN,
++			 (ctrl_hci->txq_mask << 16), (0x1F << 16));
++	mutex_unlock(&ctrl_hci->txq_mask_lock);
++	return 0;
++}
++
++static int ssv6xxx_hci_txq_resume(u32 txq_mask)
++{
++	struct ssv_hw_txq *hw_txq;
++	int txqid;
++	mutex_lock(&ctrl_hci->txq_mask_lock);
++	ctrl_hci->txq_mask &= ~(txq_mask & 0x1F);
++	for (txqid = 0; txqid < SSV_HW_TXQ_NUM; txqid++) {
++		if ((ctrl_hci->txq_mask & (1 << txqid)) != 0)
++			continue;
++		hw_txq = &ctrl_hci->hw_txq[txqid];
++		hw_txq->paused = false;
++	}
++	HCI_REG_SET_BITS(ctrl_hci, ADR_MTX_MISC_EN,
++			 (ctrl_hci->txq_mask << 16), (0x1F << 16));
++	mutex_unlock(&ctrl_hci->txq_mask_lock);
++	return 0;
++}
++
++static int ssv6xxx_hci_xmit(struct ssv_hw_txq *hw_txq, int max_count,
++			    struct ssv6xxx_hw_resource *phw_resource)
++{
++	struct sk_buff_head tx_cb_list;
++	struct sk_buff *skb = NULL;
++	int tx_count, ret, page_count;
++	struct ssv6200_tx_desc *tx_desc = NULL;
++	ctrl_hci->xmit_running = 1;
++	skb_queue_head_init(&tx_cb_list);
++	for (tx_count = 0; tx_count < max_count; tx_count++) {
++		if (ctrl_hci->hci_start == false) {
++			pr_debug("ssv6xxx_hci_xmit - hci_start = false\n");
++			goto xmit_out;
++		}
++		skb = skb_dequeue(&hw_txq->qhead);
++		if (!skb) {
++			pr_debug("ssv6xxx_hci_xmit - queue empty\n");
++			goto xmit_out;
++		}
++		page_count = (skb->len + SSV6200_ALLOC_RSVD);
++		if (page_count & HW_MMU_PAGE_MASK)
++			page_count = (page_count >> HW_MMU_PAGE_SHIFT) + 1;
++		else
++			page_count = page_count >> HW_MMU_PAGE_SHIFT;
++		if (page_count > (SSV6200_PAGE_TX_THRESHOLD / 2))
++			pr_err("Asking page %d(%d) exceeds resource limit %d.\n",
++			       page_count, skb->len,
++			       (SSV6200_PAGE_TX_THRESHOLD / 2));
++		if ((phw_resource->free_tx_page < page_count)
++		    || (phw_resource->free_tx_id <= 0)
++		    || (phw_resource->max_tx_frame[hw_txq->txq_no] <= 0)) {
++			skb_queue_head(&hw_txq->qhead, skb);
++			break;
++		}
++		phw_resource->free_tx_page -= page_count;
++		phw_resource->free_tx_id--;
++		phw_resource->max_tx_frame[hw_txq->txq_no]--;
++		tx_desc = (struct ssv6200_tx_desc *)skb->data;
++
++		if (ctrl_hci->shi->hci_skb_update_cb != NULL
++		    && tx_desc->reason != ID_TRAP_SW_TXTPUT) {
++			ctrl_hci->shi->hci_skb_update_cb(skb,
++							 ctrl_hci->
++							 shi->skb_update_args);
++		}
++
++		ret =
++		    IF_SEND(ctrl_hci, (void *)skb->data, skb->len,
++			    hw_txq->txq_no);
++		if (ret < 0) {
++			pr_err("ssv6xxx_hci_xmit failure\n");
++			skb_queue_head(&hw_txq->qhead, skb);
++			break;
++		}
++		if (tx_desc->reason != ID_TRAP_SW_TXTPUT)
++			skb_queue_tail(&tx_cb_list, skb);
++		else
++			ssv_skb_free(skb);
++		hw_txq->tx_pkt++;
++
++		if (!(hw_txq->tx_flags & HCI_FLAGS_NO_FLOWCTRL)) {
++			if (skb_queue_len(&hw_txq->qhead) < hw_txq->resum_thres) {
++				ctrl_hci->shi->
++				    hci_tx_flow_ctrl_cb
++				    (ctrl_hci->shi->tx_fctrl_cb_args,
++				     hw_txq->txq_no, false, 2000);
++			}
++		}
++	}
++ xmit_out:
++	if (ctrl_hci->shi->hci_tx_cb && tx_desc
++	    && tx_desc->reason != ID_TRAP_SW_TXTPUT) {
++		ctrl_hci->shi->hci_tx_cb(&tx_cb_list,
++					 ctrl_hci->shi->tx_cb_args);
++	}
++	ctrl_hci->xmit_running = 0;
++	return tx_count;
++}
++
++static int ssv6xxx_hci_tx_handler(void *dev, int max_count)
++{
++	struct ssv6xxx_hci_txq_info txq_info;
++	struct ssv6xxx_hci_txq_info2 txq_info2;
++	struct ssv6xxx_hw_resource hw_resource;
++	struct ssv_hw_txq *hw_txq = dev;
++	int ret, tx_count = 0;
++	max_count = skb_queue_len(&hw_txq->qhead);
++	if (max_count == 0)
++		return 0;
++	if (hw_txq->txq_no == 4) {
++		ret =
++		    HCI_REG_READ(ctrl_hci, ADR_TX_ID_ALL_INFO2,
++				 (u32 *) & txq_info2);
++		if (ret < 0) {
++			ctrl_hci->read_rs1_info_fail++;
++			return 0;
++		}
++		//BUG_ON(SSV6200_PAGE_TX_THRESHOLD < txq_info2.tx_use_page);
++		//BUG_ON(SSV6200_ID_TX_THRESHOLD < txq_info2.tx_use_id);
++		if (SSV6200_PAGE_TX_THRESHOLD < txq_info2.tx_use_page)
++			return 0;
++		if (SSV6200_ID_TX_THRESHOLD < txq_info2.tx_use_page)
++			return 0;
++		hw_resource.free_tx_page =
++		    SSV6200_PAGE_TX_THRESHOLD - txq_info2.tx_use_page;
++		hw_resource.free_tx_id =
++		    SSV6200_ID_TX_THRESHOLD - txq_info2.tx_use_id;
++		hw_resource.max_tx_frame[4] =
++		    SSV6200_ID_MANAGER_QUEUE - txq_info2.txq4_size;
++	} else {
++		ret =
++		    HCI_REG_READ(ctrl_hci, ADR_TX_ID_ALL_INFO,
++				 (u32 *) & txq_info);
++		if (ret < 0) {
++			ctrl_hci->read_rs0_info_fail++;
++			return 0;
++		}
++		//BUG_ON(SSV6200_PAGE_TX_THRESHOLD < txq_info.tx_use_page);
++		//BUG_ON(SSV6200_ID_TX_THRESHOLD < txq_info.tx_use_id);
++		if (SSV6200_PAGE_TX_THRESHOLD < txq_info.tx_use_page)
++			return 0;
++		if (SSV6200_ID_TX_THRESHOLD < txq_info.tx_use_page)
++			return 0;
++		hw_resource.free_tx_page =
++		    SSV6200_PAGE_TX_THRESHOLD - txq_info.tx_use_page;
++		hw_resource.free_tx_id =
++		    SSV6200_ID_TX_THRESHOLD - txq_info.tx_use_id;
++		hw_resource.max_tx_frame[0] =
++		    SSV6200_ID_AC_BK_OUT_QUEUE - txq_info.txq0_size;
++		hw_resource.max_tx_frame[1] =
++		    SSV6200_ID_AC_BE_OUT_QUEUE - txq_info.txq1_size;
++		hw_resource.max_tx_frame[2] =
++		    SSV6200_ID_AC_VI_OUT_QUEUE - txq_info.txq2_size;
++		hw_resource.max_tx_frame[3] =
++		    SSV6200_ID_AC_VO_OUT_QUEUE - txq_info.txq3_size;
++		BUG_ON(hw_resource.max_tx_frame[3] < 0);
++		BUG_ON(hw_resource.max_tx_frame[2] < 0);
++		BUG_ON(hw_resource.max_tx_frame[1] < 0);
++		BUG_ON(hw_resource.max_tx_frame[0] < 0);
++	}
++	{
++		tx_count = ssv6xxx_hci_xmit(hw_txq, max_count, &hw_resource);
++	}
++	if ((ctrl_hci->shi->hci_tx_q_empty_cb != NULL)
++	    && (skb_queue_len(&hw_txq->qhead) == 0)) {
++		ctrl_hci->shi->hci_tx_q_empty_cb(hw_txq->txq_no,
++						 ctrl_hci->
++						 shi->tx_q_empty_args);
++	}
++	return tx_count;
++}
++
++void ssv6xxx_hci_tx_work(struct work_struct *work)
++{
++	ssv6xxx_hci_irq_register(SSV6XXX_INT_RESOURCE_LOW);
++}
++
++static int _do_rx(struct ssv6xxx_hci_ctrl *hctl, u32 isr_status)
++{
++#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
++	struct sk_buff_head rx_list;
++#endif
++	struct sk_buff *rx_mpdu;
++	int rx_cnt, ret = 0;
++	size_t dlen;
++	u32 status = isr_status;
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	struct timespec rx_io_start_time, rx_io_end_time, rx_io_diff_time;
++	struct timespec rx_proc_start_time, rx_proc_end_time, rx_proc_diff_time;
++#endif
++#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
++	skb_queue_head_init(&rx_list);
++#endif
++	for (rx_cnt = 0; (status & SSV6XXX_INT_RX) && (rx_cnt < 32); rx_cnt++) {
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++		if (hctl->isr_mib_enable)
++			getnstimeofday(&rx_io_start_time);
++#endif
++		ret = IF_RECV(hctl, hctl->rx_buf->data, &dlen);
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++		if (hctl->isr_mib_enable)
++			getnstimeofday(&rx_io_end_time);
++#endif
++		if (ret < 0 || dlen <= 0) {
++			pr_warn("%s(): IF_RECV() retruns %d (dlen=%d)\n",
++			       __FUNCTION__, ret, (int)dlen);
++			if (ret != -84 || dlen > MAX_FRAME_SIZE)
++				break;
++		}
++		rx_mpdu = hctl->rx_buf;
++		hctl->rx_buf = ssv_skb_alloc(MAX_FRAME_SIZE);
++		if (hctl->rx_buf == NULL) {
++			pr_err("RX buffer allocation failure!\n");
++			hctl->rx_buf = rx_mpdu;
++			break;
++		}
++		hctl->rx_pkt++;
++		skb_put(rx_mpdu, dlen);
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++		if (hctl->isr_mib_enable)
++			getnstimeofday(&rx_proc_start_time);
++#endif
++#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
++		__skb_queue_tail(&rx_list, rx_mpdu);
++#else
++		hctl->shi->hci_rx_cb(rx_mpdu, hctl->shi->rx_cb_args);
++#endif
++		HCI_IRQ_STATUS(hctl, &status);
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++		if (hctl->isr_mib_enable) {
++			getnstimeofday(&rx_proc_end_time);
++			hctl->isr_rx_io_count++;
++			rx_io_diff_time =
++			    timespec_sub(rx_io_end_time, rx_io_start_time);
++			hctl->isr_rx_io_time +=
++			    timespec_to_ns(&rx_io_diff_time);
++			rx_proc_diff_time =
++			    timespec_sub(rx_proc_end_time, rx_proc_start_time);
++			hctl->isr_rx_proc_time +=
++			    timespec_to_ns(&rx_proc_diff_time);
++		}
++#endif
++	}
++#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	if (hctl->isr_mib_enable)
++		getnstimeofday(&rx_proc_start_time);
++#endif
++	hctl->shi->hci_rx_cb(&rx_list, hctl->shi->rx_cb_args);
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	if (hctl->isr_mib_enable) {
++		getnstimeofday(&rx_proc_end_time);
++		rx_proc_diff_time =
++		    timespec_sub(rx_proc_end_time, rx_proc_start_time);
++		hctl->isr_rx_proc_time += timespec_to_ns(&rx_proc_diff_time);
++	}
++#endif
++#endif
++	return ret;
++}
++
++static void ssv6xxx_hci_rx_work(struct work_struct *work)
++{
++#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
++	struct sk_buff_head rx_list;
++#endif
++	struct sk_buff *rx_mpdu;
++	int rx_cnt, ret;
++	size_t dlen;
++	u32 status;
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	struct timespec rx_io_start_time, rx_io_end_time, rx_io_diff_time;
++	struct timespec rx_proc_start_time, rx_proc_end_time, rx_proc_diff_time;
++#endif
++	ctrl_hci->rx_work_running = 1;
++#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
++	skb_queue_head_init(&rx_list);
++#endif
++	status = SSV6XXX_INT_RX;
++	for (rx_cnt = 0; (status & SSV6XXX_INT_RX) && (rx_cnt < 32); rx_cnt++) {
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++		if (ctrl_hci->isr_mib_enable)
++			getnstimeofday(&rx_io_start_time);
++#endif
++		ret = IF_RECV(ctrl_hci, ctrl_hci->rx_buf->data, &dlen);
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++		if (ctrl_hci->isr_mib_enable)
++			getnstimeofday(&rx_io_end_time);
++#endif
++		if (ret < 0 || dlen <= 0) {
++			pr_warn("%s(): IF_RECV() retruns %d (dlen=%d)\n",
++			       __FUNCTION__, ret, (int)dlen);
++			if (ret != -84 || dlen > MAX_FRAME_SIZE)
++				break;
++		}
++		rx_mpdu = ctrl_hci->rx_buf;
++		ctrl_hci->rx_buf = ssv_skb_alloc(MAX_FRAME_SIZE);
++		if (ctrl_hci->rx_buf == NULL) {
++			pr_err("RX buffer allocation failure!\n");
++			ctrl_hci->rx_buf = rx_mpdu;
++			break;
++		}
++		ctrl_hci->rx_pkt++;
++		skb_put(rx_mpdu, dlen);
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++		if (ctrl_hci->isr_mib_enable)
++			getnstimeofday(&rx_proc_start_time);
++#endif
++#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
++		__skb_queue_tail(&rx_list, rx_mpdu);
++#else
++		ctrl_hci->shi->hci_rx_cb(rx_mpdu, ctrl_hci->shi->rx_cb_args);
++#endif
++		HCI_IRQ_STATUS(ctrl_hci, &status);
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++		if (ctrl_hci->isr_mib_enable) {
++			getnstimeofday(&rx_proc_end_time);
++			ctrl_hci->isr_rx_io_count++;
++			rx_io_diff_time =
++			    timespec_sub(rx_io_end_time, rx_io_start_time);
++			ctrl_hci->isr_rx_io_time +=
++			    timespec_to_ns(&rx_io_diff_time);
++			rx_proc_diff_time =
++			    timespec_sub(rx_proc_end_time, rx_proc_start_time);
++			ctrl_hci->isr_rx_proc_time +=
++			    timespec_to_ns(&rx_proc_diff_time);
++		}
++#endif
++	}
++#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	if (ctrl_hci->isr_mib_enable)
++		getnstimeofday(&rx_proc_start_time);
++#endif
++	ctrl_hci->shi->hci_rx_cb(&rx_list, ctrl_hci->shi->rx_cb_args);
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	if (ctrl_hci->isr_mib_enable) {
++		getnstimeofday(&rx_proc_end_time);
++		rx_proc_diff_time =
++		    timespec_sub(rx_proc_end_time, rx_proc_start_time);
++		ctrl_hci->isr_rx_proc_time +=
++		    timespec_to_ns(&rx_proc_diff_time);
++	}
++#endif
++#endif
++	ctrl_hci->rx_work_running = 0;
++}
++
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++static void ssv6xxx_isr_mib_reset(void)
++{
++	ctrl_hci->isr_mib_reset = 0;
++	ctrl_hci->isr_total_time = 0;
++	ctrl_hci->isr_rx_io_time = 0;
++	ctrl_hci->isr_tx_io_time = 0;
++	ctrl_hci->isr_rx_io_count = 0;
++	ctrl_hci->isr_tx_io_count = 0;
++	ctrl_hci->isr_rx_proc_time = 0;
++}
++
++static int hw_txq_len_open(struct inode *inode, struct file *filp)
++{
++	filp->private_data = inode->i_private;
++	return 0;
++}
++
++static ssize_t hw_txq_len_read(struct file *filp, char __user * buffer,
++			       size_t count, loff_t * ppos)
++{
++	ssize_t ret;
++	struct ssv6xxx_hci_ctrl *hctl =
++	    (struct ssv6xxx_hci_ctrl *)filp->private_data;
++	char *summary_buf = kzalloc(1024, GFP_KERNEL);
++	char *prn_ptr = summary_buf;
++	int prt_size;
++	int buf_size = 1024;
++	int i = 0;
++	if (!summary_buf)
++		return -ENOMEM;
++	for (i = 0; i < SSV_HW_TXQ_NUM; i++) {
++		prt_size =
++		    snprintf(prn_ptr, buf_size, "\n\rhw_txq%d_len: %d", i,
++			     skb_queue_len(&hctl->hw_txq[i].qhead));
++		prn_ptr += prt_size;
++		buf_size -= prt_size;
++	}
++	buf_size = 1024 - buf_size;
++	ret =
++	    simple_read_from_buffer(buffer, count, ppos, summary_buf, buf_size);
++	kfree(summary_buf);
++	return ret;
++}
++
++struct file_operations hw_txq_len_fops = {
++	.owner = THIS_MODULE,
++	.open = hw_txq_len_open,
++	.read = hw_txq_len_read,
++};
++
++bool ssv6xxx_hci_init_debugfs(struct dentry *dev_deugfs_dir)
++{
++	ctrl_hci->debugfs_dir = debugfs_create_dir("hci", dev_deugfs_dir);
++	if (ctrl_hci->debugfs_dir == NULL) {
++		dev_err(ctrl_hci->shi->dev,
++			"Failed to create HCI debugfs directory.\n");
++		return false;
++	}
++	debugfs_create_u32("TXQ_mask", 00444, ctrl_hci->debugfs_dir,
++			   &ctrl_hci->txq_mask);
++	debugfs_create_u32("hci_isr_mib_enable", 00644, ctrl_hci->debugfs_dir,
++			   &ctrl_hci->isr_mib_enable);
++	debugfs_create_u32("hci_isr_mib_reset", 00644, ctrl_hci->debugfs_dir,
++			   &ctrl_hci->isr_mib_reset);
++	debugfs_create_u64("isr_total_time", 00444, ctrl_hci->debugfs_dir,
++			   &ctrl_hci->isr_total_time);
++	debugfs_create_u64("tx_io_time", 00444, ctrl_hci->debugfs_dir,
++			   &ctrl_hci->isr_tx_io_time);
++	debugfs_create_u64("rx_io_time", 00444, ctrl_hci->debugfs_dir,
++			   &ctrl_hci->isr_rx_io_time);
++	debugfs_create_u32("tx_io_count", 00444, ctrl_hci->debugfs_dir,
++			   &ctrl_hci->isr_tx_io_count);
++	debugfs_create_u32("rx_io_count", 00444, ctrl_hci->debugfs_dir,
++			   &ctrl_hci->isr_rx_io_count);
++	debugfs_create_u64("rx_proc_time", 00444, ctrl_hci->debugfs_dir,
++			   &ctrl_hci->isr_rx_proc_time);
++	debugfs_create_file("hw_txq_len", 00444, ctrl_hci->debugfs_dir,
++			    ctrl_hci, &hw_txq_len_fops);
++	return true;
++}
++
++void ssv6xxx_hci_deinit_debugfs(void)
++{
++	if (ctrl_hci->debugfs_dir == NULL)
++		return;
++	ctrl_hci->debugfs_dir = NULL;
++}
++#endif
++static int _isr_do_rx(struct ssv6xxx_hci_ctrl *hctl, u32 isr_status)
++{
++	int status;
++	u32 before = jiffies;
++
++	if (hctl->isr_summary_eable && hctl->prev_rx_isr_jiffes) {
++		if (hctl->isr_rx_idle_time) {
++			hctl->isr_rx_idle_time +=
++			    (jiffies - hctl->prev_rx_isr_jiffes);
++			hctl->isr_rx_idle_time = hctl->isr_rx_idle_time >> 1;
++		} else {
++			hctl->isr_rx_idle_time +=
++			    (jiffies - hctl->prev_rx_isr_jiffes);
++		}
++	}
++	status = _do_rx(hctl, isr_status);
++	if (hctl->isr_summary_eable) {
++		if (hctl->isr_rx_time) {
++			hctl->isr_rx_time += (jiffies - before);
++			hctl->isr_rx_time = hctl->isr_rx_time >> 1;
++		} else {
++			hctl->isr_rx_time += (jiffies - before);
++		}
++		hctl->prev_rx_isr_jiffes = jiffies;
++	}
++	return status;
++}
++
++static int _do_tx(struct ssv6xxx_hci_ctrl *hctl, u32 status)
++{
++	int q_num;
++	int tx_count = 0;
++	u32 to_disable_int = 1;
++	unsigned long flags;
++	struct ssv_hw_txq *hw_txq;
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	struct timespec tx_io_start_time, tx_io_end_time, tx_io_diff_time;
++#endif
++#ifdef CONFIG_IRQ_DEBUG_COUNT
++	if ((!(status & SSV6XXX_INT_RX)) && htcl->irq_enable)
++		hctl->tx_irq_count++;
++#endif
++	if ((status & SSV6XXX_INT_RESOURCE_LOW) == 0)
++		return 0;
++	for (q_num = (SSV_HW_TXQ_NUM - 1); q_num >= 0; q_num--) {
++		u32 before = jiffies;
++		hw_txq = &hctl->hw_txq[q_num];
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++		if (hctl->isr_mib_enable)
++			getnstimeofday(&tx_io_start_time);
++#endif
++		tx_count += ssv6xxx_hci_tx_handler(hw_txq, 999);
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++		if (hctl->isr_mib_enable) {
++			getnstimeofday(&tx_io_end_time);
++			tx_io_diff_time =
++			    timespec_sub(tx_io_end_time, tx_io_start_time);
++			hctl->isr_tx_io_time +=
++			    timespec_to_ns(&tx_io_diff_time);
++		}
++#endif
++		if (hctl->isr_summary_eable) {
++			if (hctl->isr_tx_time) {
++				hctl->isr_tx_time += (jiffies - before);
++				hctl->isr_tx_time = hctl->isr_tx_time >> 1;
++			} else {
++				hctl->isr_tx_time += (jiffies - before);
++			}
++		}
++	}
++	mutex_lock(&hctl->hci_mutex);
++	spin_lock_irqsave(&hctl->int_lock, flags);
++	for (q_num = (SSV_HW_TXQ_NUM - 1); q_num >= 0; q_num--) {
++		hw_txq = &hctl->hw_txq[q_num];
++		if (skb_queue_len(&hw_txq->qhead) > 0) {
++			to_disable_int = 0;
++			break;
++		}
++	}
++	if (to_disable_int) {
++		u32 reg_val;
++		hctl->int_mask &= ~(SSV6XXX_INT_RESOURCE_LOW | SSV6XXX_INT_TX);
++		reg_val = ~hctl->int_mask;
++		spin_unlock_irqrestore(&hctl->int_lock, flags);
++		HCI_IRQ_SET_MASK(hctl, reg_val);
++	} else {
++		spin_unlock_irqrestore(&hctl->int_lock, flags);
++	}
++	mutex_unlock(&hctl->hci_mutex);
++	return tx_count;
++}
++
++irqreturn_t ssv6xxx_hci_isr(int irq, void *args)
++{
++	struct ssv6xxx_hci_ctrl *hctl = args;
++	u32 status;
++	unsigned long flags;
++	int ret = IRQ_HANDLED;
++	bool dbg_isr_miss = true;
++	if (ctrl_hci->isr_summary_eable && ctrl_hci->prev_isr_jiffes) {
++		if (ctrl_hci->isr_idle_time) {
++			ctrl_hci->isr_idle_time +=
++			    (jiffies - ctrl_hci->prev_isr_jiffes);
++			ctrl_hci->isr_idle_time = ctrl_hci->isr_idle_time >> 1;
++		} else {
++			ctrl_hci->isr_idle_time +=
++			    (jiffies - ctrl_hci->prev_isr_jiffes);
++		}
++	}
++	BUG_ON(!args);
++	do {
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++		struct timespec start_time, end_time, diff_time;
++		if (hctl->isr_mib_reset)
++			ssv6xxx_isr_mib_reset();
++		if (hctl->isr_mib_enable)
++			getnstimeofday(&start_time);
++#endif
++#ifdef CONFIG_IRQ_DEBUG_COUNT
++		if (ctrl_hci->irq_enable)
++			ctrl_hci->irq_count++;
++#endif
++		mutex_lock(&hctl->hci_mutex);
++		if (hctl->int_status) {
++			u32 regval;
++			spin_lock_irqsave(&hctl->int_lock, flags);
++			hctl->int_mask |= hctl->int_status;
++			hctl->int_status = 0;
++			regval = ~ctrl_hci->int_mask;
++			smp_mb();
++			spin_unlock_irqrestore(&hctl->int_lock, flags);
++			HCI_IRQ_SET_MASK(hctl, regval);
++		}
++		ret = HCI_IRQ_STATUS(hctl, &status);
++		if ((ret < 0) || ((status & hctl->int_mask) == 0)) {
++#ifdef CONFIG_IRQ_DEBUG_COUNT
++			if (ctrl_hci->irq_enable)
++				ctrl_hci->invalid_irq_count++;
++#endif
++			mutex_unlock(&hctl->hci_mutex);
++			ret = IRQ_NONE;
++			break;
++		}
++		spin_lock_irqsave(&hctl->int_lock, flags);
++		status &= hctl->int_mask;
++		spin_unlock_irqrestore(&hctl->int_lock, flags);
++		mutex_unlock(&hctl->hci_mutex);
++		ctrl_hci->isr_running = 1;
++		if (status & SSV6XXX_INT_RX) {
++			ret = _isr_do_rx(hctl, status);
++			if (ret < 0) {
++				ret = IRQ_NONE;
++				break;
++			}
++			dbg_isr_miss = false;
++		}
++		if (_do_tx(hctl, status)) {
++			dbg_isr_miss = false;
++		}
++		ctrl_hci->isr_running = 0;
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++		if (ctrl_hci->isr_mib_enable) {
++			getnstimeofday(&end_time);
++			diff_time = timespec_sub(end_time, start_time);
++			ctrl_hci->isr_total_time += timespec_to_ns(&diff_time);
++		}
++#endif
++	} while (1);
++	if (ctrl_hci->isr_summary_eable) {
++		if (dbg_isr_miss)
++			ctrl_hci->isr_miss_cnt++;
++		ctrl_hci->prev_isr_jiffes = jiffies;
++	}
++	return ret;
++}
++
++static struct ssv6xxx_hci_ops hci_ops = {
++	.hci_start = ssv6xxx_hci_start,
++	.hci_stop = ssv6xxx_hci_stop,
++	.hci_read_word = ssv6xxx_hci_read_word,
++	.hci_write_word = ssv6xxx_hci_write_word,
++	.hci_tx = ssv6xxx_hci_enqueue,
++	.hci_tx_pause = ssv6xxx_hci_txq_pause,
++	.hci_tx_resume = ssv6xxx_hci_txq_resume,
++	.hci_txq_flush = ssv6xxx_hci_txq_flush,
++	.hci_txq_flush_by_sta = ssv6xxx_hci_txq_flush_by_sta,
++	.hci_txq_empty = ssv6xxx_hci_is_txq_empty,
++	.hci_load_fw = ssv6xxx_hci_load_fw,
++	.hci_pmu_wakeup = ssv6xxx_hci_pmu_wakeup,
++	.hci_send_cmd = ssv6xxx_hci_send_cmd,
++	.hci_write_sram = ssv6xxx_hci_write_sram,
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	.hci_init_debugfs = ssv6xxx_hci_init_debugfs,
++	.hci_deinit_debugfs = ssv6xxx_hci_deinit_debugfs,
++#endif
++	.hci_interface_reset = ssv6xxx_hci_interface_reset,
++};
++
++int ssv6xxx_hci_deregister(void)
++{
++	u32 regval;
++	pr_debug("%s(): \n", __FUNCTION__);
++	if (ctrl_hci->shi == NULL)
++		return -1;
++	regval = 1;
++	ssv6xxx_hci_irq_disable();
++	flush_workqueue(ctrl_hci->hci_work_queue);
++	destroy_workqueue(ctrl_hci->hci_work_queue);
++	ctrl_hci->shi = NULL;
++	return 0;
++}
++
++EXPORT_SYMBOL(ssv6xxx_hci_deregister);
++int ssv6xxx_hci_register(struct ssv6xxx_hci_info *shi)
++{
++	int i;
++	if (shi == NULL || ctrl_hci->shi)
++		return -1;
++	shi->hci_ops = &hci_ops;
++	ctrl_hci->shi = shi;
++	ctrl_hci->txq_mask = 0;
++	mutex_init(&ctrl_hci->txq_mask_lock);
++	mutex_init(&ctrl_hci->hci_mutex);
++	spin_lock_init(&ctrl_hci->int_lock);
++
++	for (i = 0; i < SSV_HW_TXQ_NUM; i++) {
++		memset(&ctrl_hci->hw_txq[i], 0, sizeof(struct ssv_hw_txq));
++		skb_queue_head_init(&ctrl_hci->hw_txq[i].qhead);
++		ctrl_hci->hw_txq[i].txq_no = (u32) i;
++		ctrl_hci->hw_txq[i].max_qsize = SSV_HW_TXQ_MAX_SIZE;
++		ctrl_hci->hw_txq[i].resum_thres = SSV_HW_TXQ_RESUME_THRES;
++	}
++	ctrl_hci->hci_work_queue =
++	    create_singlethread_workqueue("ssv6xxx_hci_wq");
++	INIT_WORK(&ctrl_hci->hci_rx_work, ssv6xxx_hci_rx_work);
++	INIT_WORK(&ctrl_hci->hci_tx_work, ssv6xxx_hci_tx_work);
++	ctrl_hci->int_mask = SSV6XXX_INT_RX | SSV6XXX_INT_RESOURCE_LOW;
++	ctrl_hci->int_status = 0;
++	HCI_IRQ_SET_MASK(ctrl_hci, 0xFFFFFFFF);
++	ssv6xxx_hci_irq_disable();
++	HCI_IRQ_REQUEST(ctrl_hci, ssv6xxx_hci_isr);
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	ctrl_hci->debugfs_dir = NULL;
++	ctrl_hci->isr_mib_enable = false;
++	ctrl_hci->isr_mib_reset = 0;
++	ctrl_hci->isr_total_time = 0;
++	ctrl_hci->isr_rx_io_time = 0;
++	ctrl_hci->isr_tx_io_time = 0;
++	ctrl_hci->isr_rx_io_count = 0;
++	ctrl_hci->isr_tx_io_count = 0;
++	ctrl_hci->isr_rx_proc_time = 0;
++#endif
++	return 0;
++}
++
++EXPORT_SYMBOL(ssv6xxx_hci_register);
++int ssv6xxx_hci_init(void)
++{
++#ifdef CONFIG_SSV6200_CLI_ENABLE
++	extern struct ssv6xxx_hci_ctrl *ssv_dbg_ctrl_hci;
++#endif
++	ctrl_hci = kzalloc(sizeof(*ctrl_hci), GFP_KERNEL);
++	if (ctrl_hci == NULL)
++		return -ENOMEM;
++	memset((void *)ctrl_hci, 0, sizeof(*ctrl_hci));
++	ctrl_hci->rx_buf = ssv_skb_alloc(MAX_FRAME_SIZE);
++	if (ctrl_hci->rx_buf == NULL) {
++		kfree(ctrl_hci);
++		return -ENOMEM;
++	}
++#ifdef CONFIG_SSV6200_CLI_ENABLE
++	ssv_dbg_ctrl_hci = ctrl_hci;
++#endif
++	return 0;
++}
++
++void ssv6xxx_hci_exit(void)
++{
++#ifdef CONFIG_SSV6200_CLI_ENABLE
++	extern struct ssv6xxx_hci_ctrl *ssv_dbg_ctrl_hci;
++#endif
++	kfree(ctrl_hci);
++	ctrl_hci = NULL;
++#ifdef CONFIG_SSV6200_CLI_ENABLE
++	ssv_dbg_ctrl_hci = NULL;
++#endif
++}
++
++EXPORT_SYMBOL(ssv6xxx_hci_init);
++EXPORT_SYMBOL(ssv6xxx_hci_exit);
+diff --git a/drivers/net/wireless/ssv6051/hci/ssv_hci.h b/drivers/net/wireless/ssv6051/hci/ssv_hci.h
+new file mode 100644
+index 000000000000..dd166c607d5d
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/hci/ssv_hci.h
+@@ -0,0 +1,77 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation, either version 3 of the License, or
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _SSV_HCI_H_
++#define _SSV_HCI_H_
++#define SSV_HW_TXQ_NUM 5
++#define SSV_HW_TXQ_MAX_SIZE 64
++#define SSV_HW_TXQ_RESUME_THRES ((SSV_HW_TXQ_MAX_SIZE >> 2) *3)
++#define HCI_FLAGS_ENQUEUE_HEAD 0x00000001
++#define HCI_FLAGS_NO_FLOWCTRL 0x00000002
++struct ssv_hw_txq {
++	u32 txq_no;
++	struct sk_buff_head qhead;
++	int max_qsize;
++	int resum_thres;
++	bool paused;
++	u32 tx_pkt;
++	u32 tx_flags;
++};
++struct ssv6xxx_hci_ops {
++	int (*hci_start)(void);
++	int (*hci_stop)(void);
++	int (*hci_read_word)(u32 addr, u32 * regval);
++	int (*hci_write_word)(u32 addr, u32 regval);
++	int (*hci_load_fw)(u8 * firmware_name, u8 openfile);
++	int (*hci_tx)(struct sk_buff *, int, u32);
++	int (*hci_tx_pause)(u32 txq_mask);
++	int (*hci_tx_resume)(u32 txq_mask);
++	int (*hci_txq_flush)(u32 txq_mask);
++	int (*hci_txq_flush_by_sta)(int aid);
++	bool (*hci_txq_empty)(int txqid);
++	int (*hci_pmu_wakeup)(void);
++	int (*hci_send_cmd)(struct sk_buff *);
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	bool (*hci_init_debugfs)(struct dentry * dev_deugfs_dir);
++	void (*hci_deinit_debugfs)(void);
++#endif
++	int (*hci_write_sram)(u32 addr, u8 * data, u32 size);
++	int (*hci_interface_reset)(void);
++};
++struct ssv6xxx_hci_info {
++	struct device *dev;
++	struct ssv6xxx_hwif_ops *if_ops;
++	struct ssv6xxx_hci_ops *hci_ops;
++#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
++	int (*hci_rx_cb)(struct sk_buff_head *, void *);
++#else
++	int (*hci_rx_cb)(struct sk_buff *, void *);
++#endif
++	void *rx_cb_args;
++	void (*hci_tx_cb)(struct sk_buff_head *, void *);
++	void *tx_cb_args;
++	int (*hci_tx_flow_ctrl_cb)(void *, int, bool, int debug);
++	void *tx_fctrl_cb_args;
++	void (*hci_tx_buf_free_cb)(struct sk_buff *, void *);
++	void *tx_buf_free_args;
++	void (*hci_skb_update_cb)(struct sk_buff *, void *);
++	void *skb_update_args;
++	void (*hci_tx_q_empty_cb)(u32 txq_no, void *);
++	void *tx_q_empty_args;
++};
++int ssv6xxx_hci_deregister(void);
++int ssv6xxx_hci_register(struct ssv6xxx_hci_info *);
++#endif
+diff --git a/drivers/net/wireless/ssv6051/hwif/hwif.h b/drivers/net/wireless/ssv6051/hwif/hwif.h
+new file mode 100644
+index 000000000000..6b5263d157d8
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/hwif/hwif.h
+@@ -0,0 +1,84 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation, either version 3 of the License, or
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _LINUX_SSVCABRIO_PLATFORM_H
++#define _LINUX_SSVCABRIO_PLATFORM_H
++#include <linux/mmc/host.h>
++#include <hwif/sdio/sdio_def.h>
++#define SSVCABRIO_PLAT_EEP_MAX_WORDS 2048
++#define SSV_REG_WRITE(dev,reg,val) \
++        (sh)->priv->ops->writereg((sh)->sc->dev, (reg), (val))
++#define SSV_REG_READ(dev,reg,buf) \
++        (sh)->priv->ops->readreg((sh)->sc->dev, (reg), (buf))
++#if 0
++#define SSV_REG_WRITE(sh,reg,val) \
++        (sh)->priv->ops->writereg((sh)->sc->dev, (reg), (val))
++#define SSV_REG_READ(sh,reg,buf) \
++        (sh)->priv->ops->readreg((sh)->sc->dev, (reg), (buf))
++#define SSV_REG_CONFIRM(sh,reg,val) \
++{ \
++    u32 regval; \
++    SSV_REG_READ(sh, reg, &regval); \
++    if (regval != (val)) { \
++        printk("[0x%08x]: 0x%08x!=0x%08x\n",\
++        (reg), (val), regval); \
++        return -1; \
++    } \
++}
++#define SSV_REG_SET_BITS(sh,reg,set,clr) \
++{ \
++    u32 reg_val; \
++    SSV_REG_READ(sh, reg, &reg_val); \
++    reg_val &= ~(clr); \
++    reg_val |= (set); \
++    SSV_REG_WRITE(sh, reg, reg_val); \
++}
++#endif
++struct ssv6xxx_hwif_ops {
++    int __must_check (*read)(struct device *child, void *buf,size_t *size);
++    int __must_check (*write)(struct device *child, void *buf, size_t len,u8 queue_num);
++    int __must_check (*readreg)(struct device *child, u32 addr, u32 *buf);
++    int __must_check (*writereg)(struct device *child, u32 addr, u32 buf);
++    int (*trigger_tx_rx)(struct device *child);
++    int (*irq_getmask)(struct device *child, u32 *mask);
++    void (*irq_setmask)(struct device *child,int mask);
++    void (*irq_enable)(struct device *child);
++    void (*irq_disable)(struct device *child,bool iswaitirq);
++    int (*irq_getstatus)(struct device *child,int *status);
++    void (*irq_request)(struct device *child,irq_handler_t irq_handler,void *irq_dev);
++    void (*irq_trigger)(struct device *child);
++    void (*pmu_wakeup)(struct device *child);
++    int __must_check (*load_fw)(struct device *child, u8 *firmware_name, u8 openfile);
++    int (*cmd52_read)(struct device *child, u32 addr, u32 *value);
++    int (*cmd52_write)(struct device *child, u32 addr, u32 value);
++    bool (*support_scatter)(struct device *child);
++    int (*rw_scatter)(struct device *child, struct sdio_scatter_req *scat_req);
++    bool (*is_ready)(struct device *child);
++    int (*write_sram)(struct device *child, u32 addr, u8 *data, u32 size);
++    void (*interface_reset)(struct device *child);
++};
++struct ssv6xxx_if_debug {
++    struct device *dev;
++    struct platform_device *pdev;
++};
++struct ssv6xxx_platform_data {
++    atomic_t irq_handling;
++    bool is_enabled;
++    unsigned short vendor;
++    unsigned short device;
++    struct ssv6xxx_hwif_ops *ops;
++};
++#endif
+diff --git a/drivers/net/wireless/ssv6051/hwif/sdio/sdio.c b/drivers/net/wireless/ssv6051/hwif/sdio/sdio.c
+new file mode 100644
+index 000000000000..273777cd0485
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/hwif/sdio/sdio.c
+@@ -0,0 +1,1254 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation, either version 3 of the License, or
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <linux/irq.h>
++#include <linux/module.h>
++#include <linux/vmalloc.h>
++#include <linux/platform_device.h>
++#include <linux/mmc/sdio.h>
++#include <linux/mmc/sdio_func.h>
++#include <linux/mmc/sdio_ids.h>
++#include <linux/mmc/card.h>
++#include <linux/mmc/host.h>
++#include "sdio_def.h"
++#include <linux/pm_runtime.h>
++#include <linux/version.h>
++#include <linux/firmware.h>
++#include <linux/reboot.h>
++#include <ssv6200.h>
++#include <linux/skbuff.h>
++
++#define LOW_SPEED_SDIO_CLOCK (25000000)
++#define HIGH_SPEED_SDIO_CLOCK (45000000)
++#define MAX_RX_FRAME_SIZE 0x900
++#define SSV_VENDOR_ID 0x3030
++#define SSV_CABRIO_DEVID 0x3030
++#define ENABLE_FW_SELF_CHECK 1
++#define FW_BLOCK_SIZE 0x8000
++#define CHECKSUM_BLOCK_SIZE 1024
++#define FW_CHECKSUM_INIT (0x12345678)
++#define FW_STATUS_REG ADR_TX_SEG
++#define FW_STATUS_MASK (0x00FF0000)
++
++#define ret_if_not_ready(value) \
++    do { \
++    if ((wlan_data.is_enabled == false) || \
++        (glue == NULL) || (glue->dev_ready == false)) { \
++        pr_warn("ret_if_not_ready() called when not ready"); \
++        return value; }\
++    } while(0)
++
++static int ssv6xxx_sdio_trigger_pmu(struct device *dev);
++static void ssv6xxx_sdio_reset(struct device *child);
++
++static void ssv6xxx_high_sdio_clk(struct sdio_func *func);
++static void ssv6xxx_low_sdio_clk(struct sdio_func *func);
++extern void *ssv6xxx_ifdebug_info[];
++extern int ssv_devicetype;
++extern void ssv6xxx_deinit_prepare(void);
++
++static struct ssv6xxx_platform_data wlan_data;
++
++static int ssv6xxx_sdio_status = 0;
++u32 sdio_sr_bhvr = SUSPEND_RESUME_0;
++EXPORT_SYMBOL(sdio_sr_bhvr);
++
++u32 shutdown_flags = SSV_SYS_REBOOT;
++
++struct ssv6xxx_sdio_glue {
++	struct device *dev;
++	struct platform_device *core;
++	struct sk_buff *dma_skb;
++#ifdef CONFIG_PM
++	struct sk_buff *cmd_skb;
++#endif
++	unsigned int ioport_data;
++	unsigned int ioport_reg;
++	irq_handler_t irq_handler;
++	void *irq_dev;
++	bool dev_ready;
++};
++
++static const struct sdio_device_id ssv6xxx_sdio_devices[] = {
++	{SDIO_DEVICE(SSV_VENDOR_ID, SSV_CABRIO_DEVID)},
++	{}
++};
++
++MODULE_DEVICE_TABLE(sdio, ssv6xxx_sdio_devices);
++
++static bool ssv6xxx_is_ready(struct device *child)
++{
++	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
++
++	ret_if_not_ready(false);
++
++	return true;
++}
++
++static int ssv6xxx_sdio_cmd52_read(struct device *child, u32 addr, u32 * value)
++{
++	int ret;
++	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
++	struct sdio_func *func;
++
++	ret_if_not_ready(-1);
++
++    func = dev_to_sdio_func(glue->dev);
++    sdio_claim_host(func);
++    *value = sdio_readb(func, addr, &ret);
++    sdio_release_host(func);
++
++	return ret;
++}
++
++static int ssv6xxx_sdio_cmd52_write(struct device *child, u32 addr, u32 value)
++{
++	int ret;
++	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
++	struct sdio_func *func;
++
++    ret_if_not_ready(-1);
++
++	func = dev_to_sdio_func(glue->dev);
++    sdio_claim_host(func);
++    sdio_writeb(func, value, addr, &ret);
++    sdio_release_host(func);
++
++	return ret;
++}
++
++static int __must_check
++ssv6xxx_sdio_read_reg(struct device *child, u32 addr, u32 * buf)
++{
++	int ret;
++
++	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
++	struct sdio_func *func;
++	u32 data;
++
++    ret_if_not_ready(-1);
++
++    func = dev_to_sdio_func(glue->dev);
++
++    sdio_claim_host(func);
++
++    data = addr;
++
++    sdio_writel(func, addr, glue->ioport_reg, &ret);
++
++    if (unlikely(ret)) {
++        dev_err(child->parent, "sdio read reg write address failed (%d)\n", ret);
++        goto io_err;
++    }
++
++    data = sdio_readl(func, glue->ioport_reg, &ret);
++
++    if (unlikely(ret)) {
++        *buf = 0xffffffff;
++        dev_err(child->parent, "sdio read reg from I/O failed (%d)\n", ret);
++        goto io_err;
++    }
++
++    *buf = data;
++
++io_err:
++    sdio_release_host(func);
++
++	return ret;
++}
++
++#ifdef ENABLE_WAKE_IO_ISR_WHEN_HCI_ENQUEUE
++static int ssv6xxx_sdio_trigger_tx_rx(struct device *child)
++{
++	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
++	struct sdio_func *func;
++	struct mmc_host *host;
++
++	if (glue == NULL)
++		return -1;
++
++	func = dev_to_sdio_func(glue->dev);
++	host = func->card->host;
++	mmc_signal_sdio_irq(host);
++
++	return 0;
++
++}
++#endif
++
++static int __must_check
++ssv6xxx_sdio_write_reg(struct device *child, u32 addr, u32 buf)
++{
++	int ret;
++
++	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
++	struct sdio_func *func;
++
++    u32 data[2];
++
++    ret_if_not_ready(-1);
++
++    func = dev_to_sdio_func(glue->dev);
++
++    sdio_claim_host(func);
++    data[0] = addr;
++    data[1] = buf;
++
++    ret = sdio_memcpy_toio(func, glue->ioport_reg, data, sizeof(data));
++    sdio_release_host(func);
++
++	return ret;
++}
++
++static int
++ssv6xxx_sdio_write_sram(struct device *child, u32 addr, u8 * data, u32 size)
++{
++	int ret = 0;
++	struct ssv6xxx_sdio_glue *glue;
++	struct sdio_func *func = NULL;
++	glue = dev_get_drvdata(child->parent);
++
++    ret_if_not_ready(-1);
++
++	func = dev_to_sdio_func(glue->dev);
++	sdio_claim_host(func);
++
++    ret |= ssv6xxx_sdio_write_reg(child, 0xc0000860, addr);
++    if (unlikely(ret))
++        goto out;
++
++    sdio_writeb(func, 0x2, REG_Fn1_STATUS, &ret);
++    if (unlikely(ret))
++        goto out;
++
++    ret = sdio_memcpy_toio(func, glue->ioport_data, data, size);
++    if (unlikely(ret))
++        goto out;
++
++    sdio_writeb(func, 0, REG_Fn1_STATUS, &ret);
++    if (unlikely(ret))
++        goto out;
++
++out:
++	sdio_release_host(func);
++	return ret;
++
++}
++
++struct file *ssv6xxx_open_firmware(char *user_mainfw)
++{
++	struct file *fp;
++	fp = filp_open(user_mainfw, O_RDONLY, 0);
++
++	if (IS_ERR(fp))
++		fp = NULL;
++
++	return fp;
++}
++
++int ssv6xxx_read_fw_block(char *buf, int len, struct file *fp)
++{
++
++	int read;
++	loff_t pos;
++
++	pos = fp->f_pos;
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,14,0)
++	read = kernel_read(fp, (void *)buf, len, &pos);
++#else
++	read = kernel_read(fp, pos, buf, len);
++#endif
++
++	if (read > 0)
++		fp->f_pos += read;
++
++	return read;
++
++}
++
++void ssv6xxx_close_firmware(struct file *fp)
++{
++	if (fp)
++		filp_close(fp, NULL);
++}
++
++static int
++ssv6xxx_sdio_upload_firmware(struct device *child, const u8 *firmware, u32 firmware_length)
++{
++	int ret;
++    u32 clk_en;
++	u32 word_count, i;
++    u32 block_size;
++	u8 *buffer;
++	u32 sram_ptr = 0;
++	u32 block_count = 0;
++    u32 firmware_ptr = 0;
++
++	u32 checksum = FW_CHECKSUM_INIT;
++	u32 fw_checksum, fw_blkcnt;
++
++	struct ssv6xxx_sdio_glue *glue;
++
++	glue = dev_get_drvdata(child->parent);
++
++    if ((wlan_data.is_enabled == false) &&
++        (glue == NULL) &&
++        (glue->dev_ready == false))
++        goto out;
++
++    buffer = (u8 *)kzalloc(FW_BLOCK_SIZE, GFP_KERNEL);
++    if (buffer == NULL) {
++        dev_err(child, "Failed to allocate buffer for firmware.\n");
++        ret = -ENOMEM;
++        goto out;
++    }
++
++    dev_dbg(child, "preparing registers and clock for firmware upload\n");
++
++    ret = ssv6xxx_sdio_write_reg(child, ADR_BRG_SW_RST, 0x0);
++    if (unlikely(ret))
++        goto out;
++
++    ret = ssv6xxx_sdio_write_reg(child, ADR_BOOT, 0x01);
++    if (unlikely(ret))
++        goto out;
++
++    ret = ssv6xxx_sdio_read_reg(child, ADR_PLATFORM_CLOCK_ENABLE, &clk_en);
++    if (unlikely(ret))
++        goto out;
++
++    ret = ssv6xxx_sdio_write_reg(child, ADR_PLATFORM_CLOCK_ENABLE, clk_en | (1 << 2));
++    if (unlikely(ret))
++        goto out;
++
++    dev_dbg(child, "begin writing firmware\n");
++
++    while (firmware_length > 0) {
++
++        memset(buffer, 0xA5, FW_BLOCK_SIZE);
++
++        block_size = firmware_length;
++        if (block_size > FW_BLOCK_SIZE)
++            block_size = FW_BLOCK_SIZE;
++
++        memcpy(buffer, &firmware[firmware_ptr], block_size);
++
++        firmware_ptr += block_size;
++        firmware_length -= block_size;
++
++        /*
++         * Uploading to chip sram and checksumming happens in chunks of CHECKSUM_BLOCK_SIZE,
++         * so we round the block size accordingly and use that valueù
++         */
++        block_size = DIV_ROUND_UP(block_size, CHECKSUM_BLOCK_SIZE) * CHECKSUM_BLOCK_SIZE;
++        ret = ssv6xxx_sdio_write_sram(child, sram_ptr, (u8 *)buffer, block_size);
++
++        if (ret) {
++            dev_err(child, "firmware upload failed\n");
++            goto out;
++        }
++
++        sram_ptr += block_size;
++
++        word_count = block_size / sizeof(u32);
++        for (i = 0; i < word_count; i++)
++            checksum += ((u32 *)buffer)[i];
++
++    }
++
++    checksum = ((checksum >> 24) +
++                (checksum >> 16) +
++                (checksum >> 8) +
++                checksum) & 0x0FF;
++    checksum <<= 16;
++
++    block_count = DIV_ROUND_UP(sram_ptr, CHECKSUM_BLOCK_SIZE);
++    ret = ssv6xxx_sdio_write_reg(child, FW_STATUS_REG, (block_count << 16));
++    if (unlikely(ret))
++        goto out;
++
++    ret = ssv6xxx_sdio_read_reg(child, FW_STATUS_REG, &fw_blkcnt);
++    if (unlikely(ret))
++        goto out;
++
++    ret = ssv6xxx_sdio_write_reg(child, ADR_BRG_SW_RST, 0x1);
++    if (unlikely(ret))
++        goto out;
++
++    dev_info(child, "firmware upload complete (wrote %d blocks, verified %d blocks)\n", block_count, fw_blkcnt >> 16);
++
++    msleep(50);
++
++    ret = ssv6xxx_sdio_read_reg(child, FW_STATUS_REG, &fw_checksum);
++    fw_checksum = fw_checksum & FW_STATUS_MASK;
++
++    if (fw_checksum == checksum) {
++        dev_dbg(child, "firmware check ok, checksum=0x%x\n", checksum);
++        ret = ssv6xxx_sdio_write_reg(child, FW_STATUS_REG, (~checksum & FW_STATUS_MASK));
++        if (unlikely(ret))
++            dev_warn(child, "could not clear checksum condition");
++    } else {
++        dev_err(child, "firmware checksum mismatch, local=0x%x, sram=0x%x\n", checksum, fw_checksum);
++    }
++
++    msleep(50);
++
++    ret = 0;
++
++ out:
++
++	if (buffer)
++		kfree(buffer);
++
++	return ret;
++
++}
++
++static int
++ssv6xxx_sdio_load_firmware(struct device *child, u8 *firmware_name, u8 openfile)
++{
++
++    int ret;
++    const struct firmware *firmware = NULL;
++    struct sdio_func *func;
++   	struct ssv6xxx_sdio_glue *glue;
++
++    glue = dev_get_drvdata(child->parent);
++
++    ret = request_firmware(&firmware, firmware_name, glue->dev);
++
++    if (ret) {
++        dev_err(child, "could not find firmware file %s, err=%d\n", firmware_name, ret);
++        goto out;
++    }
++
++    ret = ssv6xxx_sdio_upload_firmware(child, firmware->data, firmware->size);
++
++    if (ret) {
++        dev_err(child, "could not upload firmware to device, err=%d\n", ret);
++        goto out;
++    }
++
++    if (glue != NULL) {
++		func = dev_to_sdio_func(glue->dev);
++		ssv6xxx_high_sdio_clk(func);
++	}
++
++out:
++    if (firmware != NULL)
++        release_firmware(firmware);
++
++    return ret;
++
++}
++
++static int ssv6xxx_sdio_irq_getstatus(struct device *child, int *status)
++{
++	int ret = (-1);
++	struct ssv6xxx_sdio_glue *glue;
++	struct sdio_func *func;
++	glue = dev_get_drvdata(child->parent);
++
++    ret_if_not_ready(-1);
++
++    func = dev_to_sdio_func(glue->dev);
++    sdio_claim_host(func);
++    *status = sdio_readb(func, REG_INT_STATUS, &ret);
++    sdio_release_host(func);
++
++    return ret;
++
++}
++
++static int __must_check
++ssv6xxx_sdio_read(struct device *child, void *buf, size_t *size)
++{
++
++	int ret;
++    u32 data_size;
++
++	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
++	struct sdio_func *func;
++
++    ret_if_not_ready(-1);
++
++    func = dev_to_sdio_func(glue->dev);
++    sdio_claim_host(func);
++
++    data_size = sdio_readb(func, REG_CARD_PKT_LEN_0, &ret);
++
++    if (unlikely(ret)) {
++        dev_err(child->parent, "sdio read high byte len failed, ret=%d\n", ret);
++        goto out;
++    }
++
++    data_size = data_size | (sdio_readb(func, REG_CARD_PKT_LEN_1, &ret) << 0x8);
++
++    if (unlikely(ret)) {
++        dev_err(child->parent, "sdio read low len failed ret[%d]\n", ret);
++        goto out;
++    }
++
++    ret = sdio_memcpy_fromio(func, buf, glue->ioport_data, sdio_align_size(func, data_size));
++
++    if (unlikely(ret)) {
++        dev_err(child->parent, "sdio read failed size ret[%d]\n", ret);
++        goto out;
++    }
++
++    *size = data_size;
++
++out:
++
++    sdio_release_host(func);
++
++	return ret;
++}
++
++static int __must_check
++ssv6xxx_sdio_write(struct device *child, void *buf, size_t len, u8 queue_num)
++{
++	int ret;
++	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
++	struct sdio_func *func;
++	void *ptr;
++
++    ret_if_not_ready(-1);
++
++#ifdef CONFIG_ARM64
++    if (((u64) buf) & 3) {
++#else
++    if (((u32) buf) & 3) {
++#endif
++        memcpy(glue->dma_skb->data, buf, len);
++        ptr = glue->dma_skb->data;
++    } else
++        ptr = buf;
++
++    func = dev_to_sdio_func(glue->dev);
++
++    sdio_claim_host(func);
++
++    len = sdio_align_size(func, len);
++    ret = sdio_memcpy_toio(func, glue->ioport_data, ptr, len);
++
++    if (unlikely(ret))
++        dev_err(glue->dev, "sdio write failed, ret=%d\n", ret);
++
++    sdio_release_host(func);
++
++    return ret;
++
++}
++
++static void ssv6xxx_sdio_irq_handler(struct sdio_func *func)
++{
++	int status;
++	struct ssv6xxx_sdio_glue *glue = sdio_get_drvdata(func);
++	struct ssv6xxx_platform_data *pwlan_data = &wlan_data;
++
++    ret_if_not_ready();
++
++    if (glue->irq_handler == NULL)
++        return;
++
++    atomic_set(&pwlan_data->irq_handling, 1);
++    sdio_release_host(func);
++    if (glue->irq_handler != NULL)
++        status = glue->irq_handler(0, glue->irq_dev);
++    sdio_claim_host(func);
++    atomic_set(&pwlan_data->irq_handling, 0);
++
++}
++
++static void ssv6xxx_sdio_irq_setmask(struct device *child, int mask)
++{
++	int err_ret;
++	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
++	struct sdio_func *func;
++
++    ret_if_not_ready();
++
++    func = dev_to_sdio_func(glue->dev);
++    sdio_claim_host(func);
++    sdio_writeb(func, mask, REG_INT_MASK, &err_ret);
++    sdio_release_host(func);
++
++}
++
++static void ssv6xxx_sdio_irq_trigger(struct device *child)
++{
++	int err_ret;
++	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
++	struct sdio_func *func;
++
++    ret_if_not_ready();
++
++    func = dev_to_sdio_func(glue->dev);
++    sdio_claim_host(func);
++    sdio_writeb(func, 0x2, REG_INT_TRIGGER, &err_ret);
++    sdio_release_host(func);
++
++}
++
++static int ssv6xxx_sdio_irq_getmask(struct device *child, u32 * mask)
++{
++	u8 imask = 0;
++	int ret = (-1);
++	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
++	struct sdio_func *func;
++
++    ret_if_not_ready(-1);
++
++    func = dev_to_sdio_func(glue->dev);
++    sdio_claim_host(func);
++    imask = sdio_readb(func, REG_INT_MASK, &ret);
++    *mask = imask;
++    sdio_release_host(func);
++
++	return ret;
++
++}
++
++static void ssv6xxx_sdio_irq_enable(struct device *child)
++{
++	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
++	struct sdio_func *func;
++	int ret;
++	struct ssv6xxx_platform_data *pwlan_data = &wlan_data;
++	if ((pwlan_data->is_enabled == false)
++	    || (glue == NULL) || (glue->dev_ready == false))
++		return;
++
++    func = dev_to_sdio_func(glue->dev);
++    sdio_claim_host(func);
++    ret = sdio_claim_irq(func, ssv6xxx_sdio_irq_handler);
++    if (ret)
++        dev_err(child->parent, "Failed to claim sdio irq: %d\n",
++            ret);
++    sdio_release_host(func);
++
++	dev_dbg(child, "ssv6xxx_sdio_irq_enable\n");
++
++}
++
++static void ssv6xxx_sdio_irq_disable(struct device *child, bool iswaitirq)
++{
++	struct ssv6xxx_sdio_glue *glue = NULL;
++	struct sdio_func *func;
++	struct ssv6xxx_platform_data *pwlan_data = &wlan_data;
++	int ret;
++
++	dev_dbg(child, "ssv6xxx_sdio_irq_disable\n");
++
++	if ((wlan_data.is_enabled == false) || (child->parent == NULL))
++		return;
++
++	glue = dev_get_drvdata(child->parent);
++
++
++	if ((glue == NULL) || (glue->dev_ready == false)
++	    || (glue->dev == NULL))
++		return;
++
++    func = dev_to_sdio_func(glue->dev);
++
++    if (func == NULL) {
++        dev_dbg(child, "sdio func == NULL\n");
++        return;
++    }
++
++    sdio_claim_host(func);
++    while (atomic_read(&pwlan_data->irq_handling)) {
++        sdio_release_host(func);
++        schedule_timeout(HZ / 10);
++        sdio_claim_host(func);
++    }
++    ret = sdio_release_irq(func);
++
++    if (ret)
++        dev_err(child->parent,
++            "Failed to release sdio irq: %d\n", ret);
++
++    sdio_release_host(func);
++
++}
++
++static void
++ssv6xxx_sdio_irq_request(struct device *child, irq_handler_t irq_handler,
++			 void *irq_dev)
++{
++	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
++	struct sdio_func *func;
++	bool isIrqEn = false;
++
++    ret_if_not_ready();
++
++    func = dev_to_sdio_func(glue->dev);
++    glue->irq_handler = irq_handler;
++    glue->irq_dev = irq_dev;
++    if (isIrqEn) {
++        ssv6xxx_sdio_irq_enable(child);
++    }
++
++}
++
++static void
++ssv6xxx_sdio_read_parameter(struct sdio_func *func,
++			    struct ssv6xxx_sdio_glue *glue)
++{
++	int err_ret;
++	sdio_claim_host(func);
++	glue->ioport_data = 0;
++	glue->ioport_data =
++	    glue->ioport_data | (sdio_readb(func, REG_DATA_IO_PORT_0, &err_ret)
++				<< (8 * 0));
++	glue->ioport_data =
++	    glue->ioport_data | (sdio_readb(func, REG_DATA_IO_PORT_1, &err_ret)
++				<< (8 * 1));
++	glue->ioport_data =
++	    glue->ioport_data | (sdio_readb(func, REG_DATA_IO_PORT_2, &err_ret)
++				<< (8 * 2));
++	glue->ioport_reg = 0;
++	glue->ioport_reg =
++	    glue->ioport_reg | (sdio_readb(func, REG_REG_IO_PORT_0, &err_ret) <<
++			       (8 * 0));
++	glue->ioport_reg =
++	    glue->ioport_reg | (sdio_readb(func, REG_REG_IO_PORT_1, &err_ret) <<
++			       (8 * 1));
++	glue->ioport_reg =
++	    glue->ioport_reg | (sdio_readb(func, REG_REG_IO_PORT_2, &err_ret) <<
++			       (8 * 2));
++	dev_dbg(&func->dev, "ioport_data=0x%x ioport_reg=0x%x\n",
++		glue->ioport_data, glue->ioport_reg);
++	err_ret = sdio_set_block_size(func, CONFIG_PLATFORM_SDIO_BLOCK_SIZE);
++	if (err_ret != 0) {
++		dev_warn(&func->dev, "SDIO setting SDIO_DEF_BLOCK_SIZE fail!!\n");
++	}
++	sdio_writeb(func, CONFIG_PLATFORM_SDIO_OUTPUT_TIMING,
++		    REG_OUTPUT_TIMING_REG, &err_ret);
++	sdio_writeb(func, 0x00, REG_Fn1_STATUS, &err_ret);
++	sdio_release_host(func);
++}
++
++static void ssv6xxx_do_sdio_wakeup(struct sdio_func *func)
++{
++	int err_ret;
++	if (func != NULL) {
++		sdio_claim_host(func);
++		sdio_writeb(func, 0x01, REG_PMU_WAKEUP, &err_ret);
++		mdelay(10);
++		sdio_writeb(func, 0x00, REG_PMU_WAKEUP, &err_ret);
++		sdio_release_host(func);
++	}
++}
++
++static void ssv6xxx_sdio_pmu_wakeup(struct device *child)
++{
++	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
++	struct sdio_func *func;
++	if (glue != NULL) {
++		func = dev_to_sdio_func(glue->dev);
++		ssv6xxx_do_sdio_wakeup(func);
++	}
++}
++
++static bool ssv6xxx_sdio_support_scatter(struct device *child)
++{
++	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
++	struct sdio_func *func;
++
++    if (!glue) {
++        dev_err(child->parent, "ssv6xxx_sdio_enable_scatter glue == NULL!!!\n");
++        return false;
++    }
++
++    func = dev_to_sdio_func(glue->dev);
++
++    if (func->card->host->max_segs < MAX_SCATTER_ENTRIES_PER_REQ) {
++        dev_err(child->parent,
++            "host controller only supports scatter of :%d entries, driver need: %d\n",
++            func->card->host->max_segs,
++            MAX_SCATTER_ENTRIES_PER_REQ);
++        return false;
++    }
++
++    return true;
++
++}
++
++static void
++ssv6xxx_sdio_setup_scat_data(struct sdio_scatter_req *scat_req,
++			     struct mmc_data *data)
++{
++	struct scatterlist *sg;
++	int i;
++	data->blksz = SDIO_DEF_BLOCK_SIZE;
++	data->blocks = scat_req->len / SDIO_DEF_BLOCK_SIZE;
++	pr_debug
++	    ("scatter: (%s)  (block len: %d, block count: %d) , (tot:%d,sg:%d)\n",
++	     (scat_req->req & SDIO_WRITE) ? "WR" : "RD", data->blksz,
++	     data->blocks, scat_req->len, scat_req->scat_entries);
++	data->flags =
++	    (scat_req->req & SDIO_WRITE) ? MMC_DATA_WRITE : MMC_DATA_READ;
++	sg = scat_req->sgentries;
++	sg_init_table(sg, scat_req->scat_entries);
++	for (i = 0; i < scat_req->scat_entries; i++, sg++) {
++		pr_debug("%d: addr:0x%p, len:%d\n",
++		       i, scat_req->scat_list[i].buf,
++		       scat_req->scat_list[i].len);
++		sg_set_buf(sg, scat_req->scat_list[i].buf,
++			   scat_req->scat_list[i].len);
++	}
++	data->sg = scat_req->sgentries;
++	data->sg_len = scat_req->scat_entries;
++}
++
++static inline void
++ssv6xxx_sdio_set_cmd53_arg(u32 * arg, u8 rw, u8 func,
++			   u8 mode, u8 opcode, u32 addr, u16 blksz)
++{
++	*arg = (((rw & 1) << 31) |
++		((func & 0x7) << 28) |
++		((mode & 1) << 27) |
++		((opcode & 1) << 26) | ((addr & 0x1FFFF) << 9) | (blksz &
++								  0x1FF));
++}
++
++static int
++ssv6xxx_sdio_rw_scatter(struct device *child, struct sdio_scatter_req *scat_req)
++{
++	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
++	struct sdio_func *func;
++	struct mmc_request mmc_req;
++	struct mmc_command cmd;
++	struct mmc_data data;
++	u8 opcode, rw;
++	int status = 1;
++
++    if (!glue) {
++        dev_err(child->parent, "ssv6xxx_sdio_enable_scatter glue == NULL!!!\n");
++        return 1;
++    }
++
++    func = dev_to_sdio_func(glue->dev);
++    memset(&mmc_req, 0, sizeof(struct mmc_request));
++    memset(&cmd, 0, sizeof(struct mmc_command));
++    memset(&data, 0, sizeof(struct mmc_data));
++    ssv6xxx_sdio_setup_scat_data(scat_req, &data);
++    opcode = 0;
++    rw = (scat_req->req & SDIO_WRITE) ? CMD53_ARG_WRITE :
++        CMD53_ARG_READ;
++    ssv6xxx_sdio_set_cmd53_arg(&cmd.arg, rw, func->num,
++                    CMD53_ARG_BLOCK_BASIS, opcode,
++                    glue->ioport_data, data.blocks);
++    cmd.opcode = SD_IO_RW_EXTENDED;
++    cmd.flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_ADTC;
++    mmc_req.cmd = &cmd;
++    mmc_req.data = &data;
++    mmc_set_data_timeout(&data, func->card);
++    mmc_wait_for_req(func->card->host, &mmc_req);
++
++    status = cmd.error ? cmd.error : data.error;
++
++    if (cmd.error)
++        return cmd.error;
++
++    if (data.error)
++        return data.error;
++
++    return status;
++
++}
++
++static void ssv6xxx_set_sdio_clk(struct sdio_func *func, u32 sdio_hz)
++{
++	struct mmc_host *host;
++	host = func->card->host;
++	if (sdio_hz < host->f_min)
++		sdio_hz = host->f_min;
++	else if (sdio_hz > host->f_max)
++		sdio_hz = host->f_max;
++	dev_dbg(&func->dev, "%s:set sdio clk %dHz\n", __FUNCTION__, sdio_hz);
++	sdio_claim_host(func);
++	host->ios.clock = sdio_hz;
++	host->ops->set_ios(host, &host->ios);
++	mdelay(20);
++	sdio_release_host(func);
++}
++
++static void ssv6xxx_low_sdio_clk(struct sdio_func *func)
++{
++	ssv6xxx_set_sdio_clk(func, LOW_SPEED_SDIO_CLOCK);
++}
++
++static void ssv6xxx_high_sdio_clk(struct sdio_func *func)
++{
++#ifndef SDIO_USE_SLOW_CLOCK
++	ssv6xxx_set_sdio_clk(func, HIGH_SPEED_SDIO_CLOCK);
++#endif
++}
++
++static struct ssv6xxx_hwif_ops sdio_ops = {
++	.read = ssv6xxx_sdio_read,
++	.write = ssv6xxx_sdio_write,
++	.readreg = ssv6xxx_sdio_read_reg,
++	.writereg = ssv6xxx_sdio_write_reg,
++#ifdef ENABLE_WAKE_IO_ISR_WHEN_HCI_ENQUEUE
++	.trigger_tx_rx = ssv6xxx_sdio_trigger_tx_rx,
++#endif
++	.irq_getmask = ssv6xxx_sdio_irq_getmask,
++	.irq_setmask = ssv6xxx_sdio_irq_setmask,
++	.irq_enable = ssv6xxx_sdio_irq_enable,
++	.irq_disable = ssv6xxx_sdio_irq_disable,
++	.irq_getstatus = ssv6xxx_sdio_irq_getstatus,
++	.irq_request = ssv6xxx_sdio_irq_request,
++	.irq_trigger = ssv6xxx_sdio_irq_trigger,
++	.pmu_wakeup = ssv6xxx_sdio_pmu_wakeup,
++	.load_fw = ssv6xxx_sdio_load_firmware,
++	.cmd52_read = ssv6xxx_sdio_cmd52_read,
++	.cmd52_write = ssv6xxx_sdio_cmd52_write,
++	.support_scatter = ssv6xxx_sdio_support_scatter,
++	.rw_scatter = ssv6xxx_sdio_rw_scatter,
++	.is_ready = ssv6xxx_is_ready,
++	.write_sram = ssv6xxx_sdio_write_sram,
++	.interface_reset = ssv6xxx_sdio_reset,
++};
++
++static int
++ssv6xxx_sdio_power_on(struct ssv6xxx_platform_data *pdata,
++		      struct sdio_func *func)
++{
++	int ret = 0;
++	if (pdata->is_enabled == true)
++		return 0;
++
++	dev_dbg(&func->dev, "ssv6xxx_sdio_power_on\n");
++
++	sdio_claim_host(func);
++	ret = sdio_enable_func(func);
++	sdio_release_host(func);
++
++	if (ret) {
++		dev_err(&func->dev, "Unable to enable sdio func: %d)\n", ret);
++		return ret;
++	}
++
++	msleep(10);
++	pdata->is_enabled = true;
++
++	return ret;
++}
++
++static int
++ssv6xxx_sdio_power_off(struct ssv6xxx_platform_data *pdata,
++		       struct sdio_func *func)
++{
++	int ret;
++	if (pdata->is_enabled == false)
++		return 0;
++	dev_dbg(&func->dev, "ssv6xxx_sdio_power_off\n");
++	sdio_claim_host(func);
++	ret = sdio_disable_func(func);
++	sdio_release_host(func);
++	if (ret)
++		return ret;
++	pdata->is_enabled = false;
++	return ret;
++}
++
++int ssv6xxx_get_dev_status(void)
++{
++	return ssv6xxx_sdio_status;
++}
++
++EXPORT_SYMBOL(ssv6xxx_get_dev_status);
++
++static int
++ssv6xxx_sdio_probe(struct sdio_func *func, const struct sdio_device_id *id)
++{
++	struct ssv6xxx_platform_data *pwlan_data = &wlan_data;
++	struct ssv6xxx_sdio_glue *glue;
++	int ret;
++	const char *chip_family = "ssv6200";
++
++	if (ssv_devicetype != 0) {
++		dev_info(&func->dev, "Not using SSV6200 normal SDIO driver.\n");
++		return -ENODEV;
++	}
++
++	if (func->num != 0x01)
++		return -ENODEV;
++
++	glue = kzalloc(sizeof(*glue), GFP_KERNEL);
++
++	if (!glue) {
++		dev_err(&func->dev, "can't allocate glue\n");
++		return -ENOMEM;
++	}
++
++	ssv6xxx_sdio_status = 1;
++	ssv6xxx_low_sdio_clk(func);
++
++	glue->dma_skb = __dev_alloc_skb(SDIO_DMA_BUFFER_LEN, GFP_KERNEL);
++
++#ifdef CONFIG_PM
++	glue->cmd_skb = __dev_alloc_skb(SDIO_COMMAND_BUFFER_LEN, GFP_KERNEL);
++#endif
++	memset(pwlan_data, 0, sizeof(struct ssv6xxx_platform_data));
++	atomic_set(&pwlan_data->irq_handling, 0);
++	glue->dev = &func->dev;
++	func->card->quirks |= MMC_QUIRK_LENIENT_FN0;
++	func->card->quirks |= MMC_QUIRK_BLKSZ_FOR_BYTE_MODE;
++	glue->dev_ready = true;
++	pwlan_data->vendor = func->vendor;
++	pwlan_data->device = func->device;
++	dev_info(glue->dev, "device id: %x:%x\n", pwlan_data->vendor,
++		pwlan_data->device);
++	pwlan_data->ops = &sdio_ops;
++	sdio_set_drvdata(func, glue);
++#ifdef CONFIG_PM
++	ssv6xxx_do_sdio_wakeup(func);
++#endif
++	ssv6xxx_sdio_power_on(pwlan_data, func);
++	ssv6xxx_sdio_read_parameter(func, glue);
++	glue->core = platform_device_alloc(chip_family, -1);
++
++	if (!glue->core) {
++		dev_err(glue->dev, "can't allocate platform_device");
++		ret = -ENOMEM;
++		goto out_free_glue;
++	}
++
++	glue->core->dev.parent = &func->dev;
++
++	ret = platform_device_add_data(glue->core, pwlan_data,
++				       sizeof(*pwlan_data));
++
++	if (ret) {
++		dev_err(glue->dev, "can't add platform data\n");
++		goto out_dev_put;
++	}
++
++	ret = platform_device_add(glue->core);
++
++	if (ret) {
++		dev_err(glue->dev, "can't add platform device\n");
++		goto out_dev_put;
++	}
++
++	ssv6xxx_sdio_irq_setmask(&glue->core->dev, 0xff);
++
++	ssv6xxx_ifdebug_info[0] = (void *)&glue->core->dev;
++	ssv6xxx_ifdebug_info[1] = (void *)glue->core;
++	ssv6xxx_ifdebug_info[2] = (void *)&sdio_ops;
++	return 0;
++
++ out_dev_put:
++	platform_device_put(glue->core);
++ out_free_glue:
++	kfree(glue);
++
++	return ret;
++
++}
++
++static void ssv6xxx_sdio_remove(struct sdio_func *func)
++{
++	struct ssv6xxx_sdio_glue *glue = sdio_get_drvdata(func);
++	struct ssv6xxx_platform_data *pwlan_data = &wlan_data;
++
++	dev_dbg(&func->dev, "ssv6xxx_sdio_remove enter\n");
++
++	ssv6xxx_sdio_status = 0;
++
++	if (glue) {
++		dev_dbg(&func->dev, "ssv6xxx_sdio_remove - ssv6xxx_sdio_irq_disable\n");
++		ssv6xxx_sdio_irq_disable(&glue->core->dev, false);
++		glue->dev_ready = false;
++		ssv6xxx_low_sdio_clk(func);
++
++		if (glue->dma_skb != NULL)
++			dev_kfree_skb(glue->dma_skb);
++
++		dev_dbg(&func->dev, "ssv6xxx_sdio_remove - disable mask\n");
++		ssv6xxx_sdio_irq_setmask(&glue->core->dev, 0xff);
++#ifdef CONFIG_PM
++		ssv6xxx_sdio_trigger_pmu(glue->dev);
++		if (glue->cmd_skb != NULL)
++			dev_kfree_skb(glue->cmd_skb);
++#endif
++		ssv6xxx_sdio_power_off(pwlan_data, func);
++		dev_dbg(&func->dev, "platform_device_del \n");
++		platform_device_del(glue->core);
++		dev_dbg(&func->dev, "platform_device_put \n");
++		platform_device_put(glue->core);
++		kfree(glue);
++	}
++
++	sdio_set_drvdata(func, NULL);
++	dev_dbg(&func->dev, "ssv6xxx_sdio_remove leave\n");
++
++}
++
++static int ssv6xxx_sdio_trigger_pmu(struct device *dev)
++{
++
++	int ret = 0;
++
++#ifdef CONFIG_PM
++	struct sdio_func *func = dev_to_sdio_func(dev);
++	struct ssv6xxx_sdio_glue *glue = sdio_get_drvdata(func);
++	struct cfg_host_cmd *host_cmd;
++	int writesize;
++	void *tempPointer;
++
++	if (ssv6xxx_sdio_write_reg
++	    (dev, ADR_RX_FLOW_MNG, M_ENG_MACRX | (M_ENG_TRASH_CAN << 4))) ;
++	if (ssv6xxx_sdio_write_reg
++	    (dev, ADR_RX_FLOW_DATA, M_ENG_MACRX | (M_ENG_TRASH_CAN << 4))) ;
++	if (ssv6xxx_sdio_write_reg
++	    (dev, ADR_RX_FLOW_CTRL, M_ENG_MACRX | (M_ENG_TRASH_CAN << 4))) ;
++
++	host_cmd = (struct cfg_host_cmd *)glue->cmd_skb->data;
++	host_cmd->c_type = HOST_CMD;
++	host_cmd->RSVD0 = 0;
++	host_cmd->h_cmd = (u8) SSV6XXX_HOST_CMD_PS;
++	host_cmd->len = sizeof(struct cfg_host_cmd);
++
++	host_cmd->dummy = 0;
++
++	{
++		tempPointer = glue->cmd_skb->data;
++		sdio_claim_host(func);
++		writesize = sdio_align_size(func, sizeof(struct cfg_host_cmd));
++		do {
++			ret =
++			    sdio_memcpy_toio(func, glue->ioport_data,
++					     tempPointer, writesize);
++			if (ret == -EILSEQ || ret == -ETIMEDOUT) {
++				ret = -1;
++				break;
++			} else {
++				if (ret)
++					dev_err(glue->dev,
++						"Unexpected return value ret=[%d]\n",
++						ret);
++			}
++		}
++		while (ret == -EILSEQ || ret == -ETIMEDOUT);
++		sdio_release_host(func);
++		if (ret)
++			dev_err(glue->dev, "sdio write failed (%d)\n", ret);
++	}
++
++#endif
++
++	return ret;
++
++}
++
++static void ssv6xxx_sdio_reset(struct device *child)
++{
++
++#ifdef CONFIG_PM
++	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
++	struct sdio_func *func = dev_to_sdio_func(glue->dev);
++	dev_dbg(child, "%s\n", __FUNCTION__);
++	if (glue == NULL || glue->dev == NULL || func == NULL)
++		return;
++	ssv6xxx_sdio_trigger_pmu(glue->dev);
++	ssv6xxx_do_sdio_wakeup(func);
++#endif
++
++	return;
++
++}
++
++#ifdef CONFIG_PM
++static int ssv6xxx_sdio_suspend(struct device *dev)
++{
++	struct sdio_func *func = dev_to_sdio_func(dev);
++	mmc_pm_flag_t flags = sdio_get_host_pm_caps(func);
++	{
++		int ret = 0;
++		dev_info(dev, "%s: suspend: PM flags = 0x%x\n",
++			 sdio_func_id(func), flags);
++		ssv6xxx_low_sdio_clk(func);
++		ret = ssv6xxx_sdio_trigger_pmu(dev);
++		if (ret)
++			dev_warn(dev, "ssv6xxx_sdio_trigger_pmu fail!!\n");
++		if (!(flags & MMC_PM_KEEP_POWER)) {
++			dev_err(dev,
++				"%s: cannot remain alive while host is suspended\n",
++				sdio_func_id(func));
++		}
++		ret = sdio_set_host_pm_flags(func, MMC_PM_KEEP_POWER);
++		if (ret)
++			return ret;
++		mdelay(10);
++		return ret;
++	}
++}
++
++static int ssv6xxx_sdio_resume(struct device *dev)
++{
++	struct sdio_func *func = dev_to_sdio_func(dev);
++	{
++		dev_dbg(dev, "ssv6xxx_sdio_resume\n");
++		{
++			ssv6xxx_do_sdio_wakeup(func);
++			mdelay(10);
++			ssv6xxx_high_sdio_clk(func);
++			mdelay(10);
++		}
++	}
++	return 0;
++}
++
++static const struct dev_pm_ops ssv6xxx_sdio_pm_ops = {
++	.suspend = ssv6xxx_sdio_suspend,
++	.resume = ssv6xxx_sdio_resume,
++};
++#endif
++
++struct sdio_driver ssv6xxx_sdio_driver = {
++	.name = "ssv6051",
++	.id_table = ssv6xxx_sdio_devices,
++	.probe = ssv6xxx_sdio_probe,
++	.remove = ssv6xxx_sdio_remove,
++#ifdef CONFIG_PM
++	.drv = {
++		.pm = &ssv6xxx_sdio_pm_ops,
++		},
++#endif
++};
++
++EXPORT_SYMBOL(ssv6xxx_sdio_driver);
++
++int ssv6xxx_sdio_init(void)
++{
++	return sdio_register_driver(&ssv6xxx_sdio_driver);
++}
++
++void ssv6xxx_sdio_exit(void)
++{
++	pr_info("ssv6xxx_sdio_exit\n");
++	sdio_unregister_driver(&ssv6xxx_sdio_driver);
++}
++
++EXPORT_SYMBOL(ssv6xxx_sdio_init);
++EXPORT_SYMBOL(ssv6xxx_sdio_exit);
+diff --git a/drivers/net/wireless/ssv6051/hwif/sdio/sdio_def.h b/drivers/net/wireless/ssv6051/hwif/sdio/sdio_def.h
+new file mode 100644
+index 000000000000..57aefd3bf9fa
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/hwif/sdio/sdio_def.h
+@@ -0,0 +1,80 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation, either version 3 of the License, or
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _SDIO_DEF_H_
++#define _SDIO_DEF_H_
++#include <linux/scatterlist.h>
++#define BASE_SDIO 0
++#define REG_DATA_IO_PORT_0 (BASE_SDIO + 0x00)
++#define REG_DATA_IO_PORT_1 (BASE_SDIO + 0x01)
++#define REG_DATA_IO_PORT_2 (BASE_SDIO + 0x02)
++#define REG_INT_MASK (BASE_SDIO + 0x04)
++#define REG_INT_STATUS (BASE_SDIO + 0x08)
++#define REG_INT_TRIGGER (BASE_SDIO + 0x09)
++#define REG_Fn1_STATUS (BASE_SDIO + 0x0c)
++#define REG_CARD_PKT_LEN_0 (BASE_SDIO + 0x10)
++#define REG_CARD_PKT_LEN_1 (BASE_SDIO + 0x11)
++#define REG_CARD_FW_DL_STATUS (BASE_SDIO + 0x12)
++#define REG_CARD_SELF_TEST (BASE_SDIO + 0x13)
++#define REG_CARD_RCA_0 (BASE_SDIO + 0x20)
++#define REG_CARD_RCA_1 (BASE_SDIO + 0x21)
++#define REG_SDIO_FIFO_WR_THLD_0 (BASE_SDIO + 0x24)
++#define REG_SDIO_FIFO_WR_THLD_1 (BASE_SDIO + 0x25)
++#define REG_OUTPUT_TIMING_REG (BASE_SDIO + 0x55)
++#define REG_PMU_WAKEUP (BASE_SDIO + 0x67)
++#define REG_REG_IO_PORT_0 (BASE_SDIO + 0x70)
++#define REG_REG_IO_PORT_1 (BASE_SDIO + 0x71)
++#define REG_REG_IO_PORT_2 (BASE_SDIO + 0x72)
++#define REG_SDIO_TX_ALLOC_SIZE (BASE_SDIO + 0x98)
++#define REG_SDIO_TX_ALLOC_SHIFT (BASE_SDIO + 0x99)
++#define REG_SDIO_TX_ALLOC_STATE (BASE_SDIO + 0x9a)
++#define REG_SDIO_TX_INFORM_0 (BASE_SDIO + 0x9c)
++#define REG_SDIO_TX_INFORM_1 (BASE_SDIO + 0x9d)
++#define REG_SDIO_TX_INFORM_2 (BASE_SDIO + 0x9e)
++#define SDIO_DEF_BLOCK_SIZE 0x80
++#if (SDIO_DEF_BLOCK_SIZE % 8)
++#error Wrong SDIO_DEF_BLOCK_SIZE value!! Should be the multiple of 8 bytes!!!!!!!!!!!!!!!!!!!!!!
++#endif
++#define SDIO_DEF_OUTPUT_TIMING 0
++#define SDIO_DEF_BLOCK_MODE_THRD 128
++#if (SDIO_DEF_BLOCK_MODE_THRD % 8)
++#error Wrong SDIO_DEF_BLOCK_MODE_THRD value!! Should be the multiple of 8 bytes!!!!!!!!!!!!!!!!!!!!!!
++#endif
++#define SDIO_DEF_FORCE_BLOCK_MODE 0
++#define MAX_SCATTER_ENTRIES_PER_REQ 8
++struct sdio_scatter_item {
++	u8 *buf;
++	int len;
++};
++struct sdio_scatter_req {
++	u32 req;
++	u32 len;
++	int scat_entries;
++	struct sdio_scatter_item scat_list[MAX_SCATTER_ENTRIES_PER_REQ];
++	struct scatterlist sgentries[MAX_SCATTER_ENTRIES_PER_REQ];
++};
++#define SDIO_READ 0x00000001
++#define SDIO_WRITE 0x00000002
++#define CMD53_ARG_READ 0
++#define CMD53_ARG_WRITE 1
++#define CMD53_ARG_BLOCK_BASIS 1
++#define CMD53_ARG_FIXED_ADDRESS 0
++#define CMD53_ARG_INCR_ADDRESS 1
++#define SDIO_DMA_BUFFER_LEN 2048
++#ifdef CONFIG_PM
++#define SDIO_COMMAND_BUFFER_LEN 256
++#endif
++#endif
+diff --git a/drivers/net/wireless/ssv6051/include/cabrio.h b/drivers/net/wireless/ssv6051/include/cabrio.h
+new file mode 100644
+index 000000000000..0b1327865c6b
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/include/cabrio.h
+@@ -0,0 +1,28 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation, either version 3 of the License, or
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef CABRIO_H
++#define CABRIO_H
++#define SSV_VENDOR_ID 0x3030
++#define SSV_CABRIO_DEVID 0x3030
++#define SSV_SUBVENDOR_ID_NOG 0x0e11
++#define SSV_SUBVENDOR_ID_NEW_A 0x7065
++#define SSV_CABRIO_MAGIC 0x19641014
++#define SSV_AMPDU_LIMIT_MAX (64 * 1024 - 1)
++#define SSV_DEFAULT_NOISE_FLOOR -95
++#define SSVCABRIO_RSSI_BAD -128
++#define SSVCABRIO_NUM_CHANNELS 38
++#endif
+diff --git a/drivers/net/wireless/ssv6051/include/ssv6200.h b/drivers/net/wireless/ssv6051/include/ssv6200.h
+new file mode 100644
+index 000000000000..22eaceaf285d
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/include/ssv6200.h
+@@ -0,0 +1,76 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation, either version 3 of the License, or
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _SSV6200_H_
++#define _SSV6200_H_
++#include <linux/device.h>
++#include <linux/interrupt.h>
++#include <net/mac80211.h>
++#ifdef ECLIPSE
++#include <ssv_mod_conf.h>
++#endif
++#include <ssv6200_reg.h>
++#include <ssv6200_aux.h>
++#include <hwif/hwif.h>
++#include <hci/ssv_hci.h>
++#include "ssv6200_common.h"
++#define SSV6200_TOTAL_ID 128
++#ifndef HUW_DRV
++#define SSV6200_ID_TX_THRESHOLD 19
++#define SSV6200_ID_RX_THRESHOLD 60
++#define SSV6200_PAGE_TX_THRESHOLD 115
++#define SSV6200_PAGE_RX_THRESHOLD 115
++#define SSV6XXX_AMPDU_DIVIDER (2)
++#define SSV6200_TX_LOWTHRESHOLD_PAGE_TRIGGER (SSV6200_PAGE_TX_THRESHOLD - (SSV6200_PAGE_TX_THRESHOLD/SSV6XXX_AMPDU_DIVIDER))
++#define SSV6200_TX_LOWTHRESHOLD_ID_TRIGGER 2
++#else
++#undef SSV6200_ID_TX_THRESHOLD
++#undef SSV6200_ID_RX_THRESHOLD
++#undef SSV6200_PAGE_TX_THRESHOLD
++#undef SSV6200_PAGE_RX_THRESHOLD
++#undef SSV6200_TX_LOWTHRESHOLD_PAGE_TRIGGER
++#undef SSV6200_TX_LOWTHRESHOLD_ID_TRIGGER
++#define SSV6200_ID_TX_THRESHOLD 31
++#define SSV6200_ID_RX_THRESHOLD 31
++#define SSV6200_PAGE_TX_THRESHOLD 61
++#define SSV6200_PAGE_RX_THRESHOLD 61
++#define SSV6200_TX_LOWTHRESHOLD_PAGE_TRIGGER 45
++#define SSV6200_TX_LOWTHRESHOLD_ID_TRIGGER 2
++#endif
++#define SSV6200_ID_NUMBER (128)
++#define PACKET_ADDR_2_ID(addr) ((addr >> 16) & 0x7F)
++#define SSV6200_ID_AC_RESERVED 1
++#define SSV6200_ID_AC_BK_OUT_QUEUE 8
++#define SSV6200_ID_AC_BE_OUT_QUEUE 15
++#define SSV6200_ID_AC_VI_OUT_QUEUE 16
++#define SSV6200_ID_AC_VO_OUT_QUEUE 16
++#define SSV6200_ID_MANAGER_QUEUE 8
++#define HW_MMU_PAGE_SHIFT 0x8
++#define HW_MMU_PAGE_MASK 0xff
++#define SSV6200_BT_PRI_SMP_TIME 0
++#define SSV6200_BT_STA_SMP_TIME (SSV6200_BT_PRI_SMP_TIME+0)
++#define SSV6200_WLAN_REMAIN_TIME 0
++#define BT_2WIRE_EN_MSK 0x00000400
++struct txResourceControl {
++	u32 txUsePage:8;
++	u32 txUseID:6;
++	u32 edca0:4;
++	u32 edca1:4;
++	u32 edca2:5;
++	u32 edca3:5;
++};
++#include <ssv_cfg.h>
++#endif
+diff --git a/drivers/net/wireless/ssv6051/include/ssv6200_aux.h b/drivers/net/wireless/ssv6051/include/ssv6200_aux.h
+new file mode 100644
+index 000000000000..03ec3f07d330
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/include/ssv6200_aux.h
+@@ -0,0 +1,18221 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation, either version 3 of the License, or
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#define MCU_ENABLE_MSK 0x00000001
++#define MCU_ENABLE_I_MSK 0xfffffffe
++#define MCU_ENABLE_SFT 0
++#define MCU_ENABLE_HI 0
++#define MCU_ENABLE_SZ 1
++#define MAC_SW_RST_MSK 0x00000002
++#define MAC_SW_RST_I_MSK 0xfffffffd
++#define MAC_SW_RST_SFT 1
++#define MAC_SW_RST_HI 1
++#define MAC_SW_RST_SZ 1
++#define MCU_SW_RST_MSK 0x00000004
++#define MCU_SW_RST_I_MSK 0xfffffffb
++#define MCU_SW_RST_SFT 2
++#define MCU_SW_RST_HI 2
++#define MCU_SW_RST_SZ 1
++#define SDIO_SW_RST_MSK 0x00000008
++#define SDIO_SW_RST_I_MSK 0xfffffff7
++#define SDIO_SW_RST_SFT 3
++#define SDIO_SW_RST_HI 3
++#define SDIO_SW_RST_SZ 1
++#define SPI_SLV_SW_RST_MSK 0x00000010
++#define SPI_SLV_SW_RST_I_MSK 0xffffffef
++#define SPI_SLV_SW_RST_SFT 4
++#define SPI_SLV_SW_RST_HI 4
++#define SPI_SLV_SW_RST_SZ 1
++#define UART_SW_RST_MSK 0x00000020
++#define UART_SW_RST_I_MSK 0xffffffdf
++#define UART_SW_RST_SFT 5
++#define UART_SW_RST_HI 5
++#define UART_SW_RST_SZ 1
++#define DMA_SW_RST_MSK 0x00000040
++#define DMA_SW_RST_I_MSK 0xffffffbf
++#define DMA_SW_RST_SFT 6
++#define DMA_SW_RST_HI 6
++#define DMA_SW_RST_SZ 1
++#define WDT_SW_RST_MSK 0x00000080
++#define WDT_SW_RST_I_MSK 0xffffff7f
++#define WDT_SW_RST_SFT 7
++#define WDT_SW_RST_HI 7
++#define WDT_SW_RST_SZ 1
++#define I2C_SLV_SW_RST_MSK 0x00000100
++#define I2C_SLV_SW_RST_I_MSK 0xfffffeff
++#define I2C_SLV_SW_RST_SFT 8
++#define I2C_SLV_SW_RST_HI 8
++#define I2C_SLV_SW_RST_SZ 1
++#define INT_CTL_SW_RST_MSK 0x00000200
++#define INT_CTL_SW_RST_I_MSK 0xfffffdff
++#define INT_CTL_SW_RST_SFT 9
++#define INT_CTL_SW_RST_HI 9
++#define INT_CTL_SW_RST_SZ 1
++#define BTCX_SW_RST_MSK 0x00000400
++#define BTCX_SW_RST_I_MSK 0xfffffbff
++#define BTCX_SW_RST_SFT 10
++#define BTCX_SW_RST_HI 10
++#define BTCX_SW_RST_SZ 1
++#define GPIO_SW_RST_MSK 0x00000800
++#define GPIO_SW_RST_I_MSK 0xfffff7ff
++#define GPIO_SW_RST_SFT 11
++#define GPIO_SW_RST_HI 11
++#define GPIO_SW_RST_SZ 1
++#define US0TMR_SW_RST_MSK 0x00001000
++#define US0TMR_SW_RST_I_MSK 0xffffefff
++#define US0TMR_SW_RST_SFT 12
++#define US0TMR_SW_RST_HI 12
++#define US0TMR_SW_RST_SZ 1
++#define US1TMR_SW_RST_MSK 0x00002000
++#define US1TMR_SW_RST_I_MSK 0xffffdfff
++#define US1TMR_SW_RST_SFT 13
++#define US1TMR_SW_RST_HI 13
++#define US1TMR_SW_RST_SZ 1
++#define US2TMR_SW_RST_MSK 0x00004000
++#define US2TMR_SW_RST_I_MSK 0xffffbfff
++#define US2TMR_SW_RST_SFT 14
++#define US2TMR_SW_RST_HI 14
++#define US2TMR_SW_RST_SZ 1
++#define US3TMR_SW_RST_MSK 0x00008000
++#define US3TMR_SW_RST_I_MSK 0xffff7fff
++#define US3TMR_SW_RST_SFT 15
++#define US3TMR_SW_RST_HI 15
++#define US3TMR_SW_RST_SZ 1
++#define MS0TMR_SW_RST_MSK 0x00010000
++#define MS0TMR_SW_RST_I_MSK 0xfffeffff
++#define MS0TMR_SW_RST_SFT 16
++#define MS0TMR_SW_RST_HI 16
++#define MS0TMR_SW_RST_SZ 1
++#define MS1TMR_SW_RST_MSK 0x00020000
++#define MS1TMR_SW_RST_I_MSK 0xfffdffff
++#define MS1TMR_SW_RST_SFT 17
++#define MS1TMR_SW_RST_HI 17
++#define MS1TMR_SW_RST_SZ 1
++#define MS2TMR_SW_RST_MSK 0x00040000
++#define MS2TMR_SW_RST_I_MSK 0xfffbffff
++#define MS2TMR_SW_RST_SFT 18
++#define MS2TMR_SW_RST_HI 18
++#define MS2TMR_SW_RST_SZ 1
++#define MS3TMR_SW_RST_MSK 0x00080000
++#define MS3TMR_SW_RST_I_MSK 0xfff7ffff
++#define MS3TMR_SW_RST_SFT 19
++#define MS3TMR_SW_RST_HI 19
++#define MS3TMR_SW_RST_SZ 1
++#define RF_BB_SW_RST_MSK 0x00100000
++#define RF_BB_SW_RST_I_MSK 0xffefffff
++#define RF_BB_SW_RST_SFT 20
++#define RF_BB_SW_RST_HI 20
++#define RF_BB_SW_RST_SZ 1
++#define SYS_ALL_RST_MSK 0x00200000
++#define SYS_ALL_RST_I_MSK 0xffdfffff
++#define SYS_ALL_RST_SFT 21
++#define SYS_ALL_RST_HI 21
++#define SYS_ALL_RST_SZ 1
++#define DAT_UART_SW_RST_MSK 0x00400000
++#define DAT_UART_SW_RST_I_MSK 0xffbfffff
++#define DAT_UART_SW_RST_SFT 22
++#define DAT_UART_SW_RST_HI 22
++#define DAT_UART_SW_RST_SZ 1
++#define I2C_MST_SW_RST_MSK 0x00800000
++#define I2C_MST_SW_RST_I_MSK 0xff7fffff
++#define I2C_MST_SW_RST_SFT 23
++#define I2C_MST_SW_RST_HI 23
++#define I2C_MST_SW_RST_SZ 1
++#define RG_REBOOT_MSK 0x00000001
++#define RG_REBOOT_I_MSK 0xfffffffe
++#define RG_REBOOT_SFT 0
++#define RG_REBOOT_HI 0
++#define RG_REBOOT_SZ 1
++#define TRAP_IMG_FLS_MSK 0x00010000
++#define TRAP_IMG_FLS_I_MSK 0xfffeffff
++#define TRAP_IMG_FLS_SFT 16
++#define TRAP_IMG_FLS_HI 16
++#define TRAP_IMG_FLS_SZ 1
++#define TRAP_REBOOT_MSK 0x00020000
++#define TRAP_REBOOT_I_MSK 0xfffdffff
++#define TRAP_REBOOT_SFT 17
++#define TRAP_REBOOT_HI 17
++#define TRAP_REBOOT_SZ 1
++#define TRAP_BOOT_FLS_MSK 0x00040000
++#define TRAP_BOOT_FLS_I_MSK 0xfffbffff
++#define TRAP_BOOT_FLS_SFT 18
++#define TRAP_BOOT_FLS_HI 18
++#define TRAP_BOOT_FLS_SZ 1
++#define CHIP_ID_31_0_MSK 0xffffffff
++#define CHIP_ID_31_0_I_MSK 0x00000000
++#define CHIP_ID_31_0_SFT 0
++#define CHIP_ID_31_0_HI 31
++#define CHIP_ID_31_0_SZ 32
++#define CHIP_ID_63_32_MSK 0xffffffff
++#define CHIP_ID_63_32_I_MSK 0x00000000
++#define CHIP_ID_63_32_SFT 0
++#define CHIP_ID_63_32_HI 31
++#define CHIP_ID_63_32_SZ 32
++#define CHIP_ID_95_64_MSK 0xffffffff
++#define CHIP_ID_95_64_I_MSK 0x00000000
++#define CHIP_ID_95_64_SFT 0
++#define CHIP_ID_95_64_HI 31
++#define CHIP_ID_95_64_SZ 32
++#define CHIP_ID_127_96_MSK 0xffffffff
++#define CHIP_ID_127_96_I_MSK 0x00000000
++#define CHIP_ID_127_96_SFT 0
++#define CHIP_ID_127_96_HI 31
++#define CHIP_ID_127_96_SZ 32
++#define CK_SEL_1_0_MSK 0x00000003
++#define CK_SEL_1_0_I_MSK 0xfffffffc
++#define CK_SEL_1_0_SFT 0
++#define CK_SEL_1_0_HI 1
++#define CK_SEL_1_0_SZ 2
++#define CK_SEL_2_MSK 0x00000004
++#define CK_SEL_2_I_MSK 0xfffffffb
++#define CK_SEL_2_SFT 2
++#define CK_SEL_2_HI 2
++#define CK_SEL_2_SZ 1
++#define SYS_CLK_EN_MSK 0x00000001
++#define SYS_CLK_EN_I_MSK 0xfffffffe
++#define SYS_CLK_EN_SFT 0
++#define SYS_CLK_EN_HI 0
++#define SYS_CLK_EN_SZ 1
++#define MAC_CLK_EN_MSK 0x00000002
++#define MAC_CLK_EN_I_MSK 0xfffffffd
++#define MAC_CLK_EN_SFT 1
++#define MAC_CLK_EN_HI 1
++#define MAC_CLK_EN_SZ 1
++#define MCU_CLK_EN_MSK 0x00000004
++#define MCU_CLK_EN_I_MSK 0xfffffffb
++#define MCU_CLK_EN_SFT 2
++#define MCU_CLK_EN_HI 2
++#define MCU_CLK_EN_SZ 1
++#define SDIO_CLK_EN_MSK 0x00000008
++#define SDIO_CLK_EN_I_MSK 0xfffffff7
++#define SDIO_CLK_EN_SFT 3
++#define SDIO_CLK_EN_HI 3
++#define SDIO_CLK_EN_SZ 1
++#define SPI_SLV_CLK_EN_MSK 0x00000010
++#define SPI_SLV_CLK_EN_I_MSK 0xffffffef
++#define SPI_SLV_CLK_EN_SFT 4
++#define SPI_SLV_CLK_EN_HI 4
++#define SPI_SLV_CLK_EN_SZ 1
++#define UART_CLK_EN_MSK 0x00000020
++#define UART_CLK_EN_I_MSK 0xffffffdf
++#define UART_CLK_EN_SFT 5
++#define UART_CLK_EN_HI 5
++#define UART_CLK_EN_SZ 1
++#define DMA_CLK_EN_MSK 0x00000040
++#define DMA_CLK_EN_I_MSK 0xffffffbf
++#define DMA_CLK_EN_SFT 6
++#define DMA_CLK_EN_HI 6
++#define DMA_CLK_EN_SZ 1
++#define WDT_CLK_EN_MSK 0x00000080
++#define WDT_CLK_EN_I_MSK 0xffffff7f
++#define WDT_CLK_EN_SFT 7
++#define WDT_CLK_EN_HI 7
++#define WDT_CLK_EN_SZ 1
++#define I2C_SLV_CLK_EN_MSK 0x00000100
++#define I2C_SLV_CLK_EN_I_MSK 0xfffffeff
++#define I2C_SLV_CLK_EN_SFT 8
++#define I2C_SLV_CLK_EN_HI 8
++#define I2C_SLV_CLK_EN_SZ 1
++#define INT_CTL_CLK_EN_MSK 0x00000200
++#define INT_CTL_CLK_EN_I_MSK 0xfffffdff
++#define INT_CTL_CLK_EN_SFT 9
++#define INT_CTL_CLK_EN_HI 9
++#define INT_CTL_CLK_EN_SZ 1
++#define BTCX_CLK_EN_MSK 0x00000400
++#define BTCX_CLK_EN_I_MSK 0xfffffbff
++#define BTCX_CLK_EN_SFT 10
++#define BTCX_CLK_EN_HI 10
++#define BTCX_CLK_EN_SZ 1
++#define GPIO_CLK_EN_MSK 0x00000800
++#define GPIO_CLK_EN_I_MSK 0xfffff7ff
++#define GPIO_CLK_EN_SFT 11
++#define GPIO_CLK_EN_HI 11
++#define GPIO_CLK_EN_SZ 1
++#define US0TMR_CLK_EN_MSK 0x00001000
++#define US0TMR_CLK_EN_I_MSK 0xffffefff
++#define US0TMR_CLK_EN_SFT 12
++#define US0TMR_CLK_EN_HI 12
++#define US0TMR_CLK_EN_SZ 1
++#define US1TMR_CLK_EN_MSK 0x00002000
++#define US1TMR_CLK_EN_I_MSK 0xffffdfff
++#define US1TMR_CLK_EN_SFT 13
++#define US1TMR_CLK_EN_HI 13
++#define US1TMR_CLK_EN_SZ 1
++#define US2TMR_CLK_EN_MSK 0x00004000
++#define US2TMR_CLK_EN_I_MSK 0xffffbfff
++#define US2TMR_CLK_EN_SFT 14
++#define US2TMR_CLK_EN_HI 14
++#define US2TMR_CLK_EN_SZ 1
++#define US3TMR_CLK_EN_MSK 0x00008000
++#define US3TMR_CLK_EN_I_MSK 0xffff7fff
++#define US3TMR_CLK_EN_SFT 15
++#define US3TMR_CLK_EN_HI 15
++#define US3TMR_CLK_EN_SZ 1
++#define MS0TMR_CLK_EN_MSK 0x00010000
++#define MS0TMR_CLK_EN_I_MSK 0xfffeffff
++#define MS0TMR_CLK_EN_SFT 16
++#define MS0TMR_CLK_EN_HI 16
++#define MS0TMR_CLK_EN_SZ 1
++#define MS1TMR_CLK_EN_MSK 0x00020000
++#define MS1TMR_CLK_EN_I_MSK 0xfffdffff
++#define MS1TMR_CLK_EN_SFT 17
++#define MS1TMR_CLK_EN_HI 17
++#define MS1TMR_CLK_EN_SZ 1
++#define MS2TMR_CLK_EN_MSK 0x00040000
++#define MS2TMR_CLK_EN_I_MSK 0xfffbffff
++#define MS2TMR_CLK_EN_SFT 18
++#define MS2TMR_CLK_EN_HI 18
++#define MS2TMR_CLK_EN_SZ 1
++#define MS3TMR_CLK_EN_MSK 0x00080000
++#define MS3TMR_CLK_EN_I_MSK 0xfff7ffff
++#define MS3TMR_CLK_EN_SFT 19
++#define MS3TMR_CLK_EN_HI 19
++#define MS3TMR_CLK_EN_SZ 1
++#define BIST_CLK_EN_MSK 0x00100000
++#define BIST_CLK_EN_I_MSK 0xffefffff
++#define BIST_CLK_EN_SFT 20
++#define BIST_CLK_EN_HI 20
++#define BIST_CLK_EN_SZ 1
++#define I2C_MST_CLK_EN_MSK 0x00800000
++#define I2C_MST_CLK_EN_I_MSK 0xff7fffff
++#define I2C_MST_CLK_EN_SFT 23
++#define I2C_MST_CLK_EN_HI 23
++#define I2C_MST_CLK_EN_SZ 1
++#define BTCX_CSR_CLK_EN_MSK 0x00000400
++#define BTCX_CSR_CLK_EN_I_MSK 0xfffffbff
++#define BTCX_CSR_CLK_EN_SFT 10
++#define BTCX_CSR_CLK_EN_HI 10
++#define BTCX_CSR_CLK_EN_SZ 1
++#define MCU_DBG_SEL_MSK 0x0000003f
++#define MCU_DBG_SEL_I_MSK 0xffffffc0
++#define MCU_DBG_SEL_SFT 0
++#define MCU_DBG_SEL_HI 5
++#define MCU_DBG_SEL_SZ 6
++#define MCU_STOP_NOGRANT_MSK 0x00000100
++#define MCU_STOP_NOGRANT_I_MSK 0xfffffeff
++#define MCU_STOP_NOGRANT_SFT 8
++#define MCU_STOP_NOGRANT_HI 8
++#define MCU_STOP_NOGRANT_SZ 1
++#define MCU_STOP_ANYTIME_MSK 0x00000200
++#define MCU_STOP_ANYTIME_I_MSK 0xfffffdff
++#define MCU_STOP_ANYTIME_SFT 9
++#define MCU_STOP_ANYTIME_HI 9
++#define MCU_STOP_ANYTIME_SZ 1
++#define MCU_DBG_DATA_MSK 0xffffffff
++#define MCU_DBG_DATA_I_MSK 0x00000000
++#define MCU_DBG_DATA_SFT 0
++#define MCU_DBG_DATA_HI 31
++#define MCU_DBG_DATA_SZ 32
++#define AHB_SW_RST_MSK 0x00000001
++#define AHB_SW_RST_I_MSK 0xfffffffe
++#define AHB_SW_RST_SFT 0
++#define AHB_SW_RST_HI 0
++#define AHB_SW_RST_SZ 1
++#define AHB_ERR_RST_MSK 0x00000002
++#define AHB_ERR_RST_I_MSK 0xfffffffd
++#define AHB_ERR_RST_SFT 1
++#define AHB_ERR_RST_HI 1
++#define AHB_ERR_RST_SZ 1
++#define REG_AHB_DEBUG_MX_MSK 0x00000030
++#define REG_AHB_DEBUG_MX_I_MSK 0xffffffcf
++#define REG_AHB_DEBUG_MX_SFT 4
++#define REG_AHB_DEBUG_MX_HI 5
++#define REG_AHB_DEBUG_MX_SZ 2
++#define REG_PKT_W_NBRT_MSK 0x00000100
++#define REG_PKT_W_NBRT_I_MSK 0xfffffeff
++#define REG_PKT_W_NBRT_SFT 8
++#define REG_PKT_W_NBRT_HI 8
++#define REG_PKT_W_NBRT_SZ 1
++#define REG_PKT_R_NBRT_MSK 0x00000200
++#define REG_PKT_R_NBRT_I_MSK 0xfffffdff
++#define REG_PKT_R_NBRT_SFT 9
++#define REG_PKT_R_NBRT_HI 9
++#define REG_PKT_R_NBRT_SZ 1
++#define IQ_SRAM_SEL_0_MSK 0x00001000
++#define IQ_SRAM_SEL_0_I_MSK 0xffffefff
++#define IQ_SRAM_SEL_0_SFT 12
++#define IQ_SRAM_SEL_0_HI 12
++#define IQ_SRAM_SEL_0_SZ 1
++#define IQ_SRAM_SEL_1_MSK 0x00002000
++#define IQ_SRAM_SEL_1_I_MSK 0xffffdfff
++#define IQ_SRAM_SEL_1_SFT 13
++#define IQ_SRAM_SEL_1_HI 13
++#define IQ_SRAM_SEL_1_SZ 1
++#define IQ_SRAM_SEL_2_MSK 0x00004000
++#define IQ_SRAM_SEL_2_I_MSK 0xffffbfff
++#define IQ_SRAM_SEL_2_SFT 14
++#define IQ_SRAM_SEL_2_HI 14
++#define IQ_SRAM_SEL_2_SZ 1
++#define AHB_STATUS_MSK 0xffff0000
++#define AHB_STATUS_I_MSK 0x0000ffff
++#define AHB_STATUS_SFT 16
++#define AHB_STATUS_HI 31
++#define AHB_STATUS_SZ 16
++#define PARALLEL_DR_MSK 0x00000001
++#define PARALLEL_DR_I_MSK 0xfffffffe
++#define PARALLEL_DR_SFT 0
++#define PARALLEL_DR_HI 0
++#define PARALLEL_DR_SZ 1
++#define MBRUN_MSK 0x00000010
++#define MBRUN_I_MSK 0xffffffef
++#define MBRUN_SFT 4
++#define MBRUN_HI 4
++#define MBRUN_SZ 1
++#define SHIFT_DR_MSK 0x00000100
++#define SHIFT_DR_I_MSK 0xfffffeff
++#define SHIFT_DR_SFT 8
++#define SHIFT_DR_HI 8
++#define SHIFT_DR_SZ 1
++#define MODE_REG_SI_MSK 0x00000200
++#define MODE_REG_SI_I_MSK 0xfffffdff
++#define MODE_REG_SI_SFT 9
++#define MODE_REG_SI_HI 9
++#define MODE_REG_SI_SZ 1
++#define SIMULATION_MODE_MSK 0x00000400
++#define SIMULATION_MODE_I_MSK 0xfffffbff
++#define SIMULATION_MODE_SFT 10
++#define SIMULATION_MODE_HI 10
++#define SIMULATION_MODE_SZ 1
++#define DBIST_MODE_MSK 0x00000800
++#define DBIST_MODE_I_MSK 0xfffff7ff
++#define DBIST_MODE_SFT 11
++#define DBIST_MODE_HI 11
++#define DBIST_MODE_SZ 1
++#define MODE_REG_IN_MSK 0x001fffff
++#define MODE_REG_IN_I_MSK 0xffe00000
++#define MODE_REG_IN_SFT 0
++#define MODE_REG_IN_HI 20
++#define MODE_REG_IN_SZ 21
++#define MODE_REG_OUT_MCU_MSK 0x001fffff
++#define MODE_REG_OUT_MCU_I_MSK 0xffe00000
++#define MODE_REG_OUT_MCU_SFT 0
++#define MODE_REG_OUT_MCU_HI 20
++#define MODE_REG_OUT_MCU_SZ 21
++#define MODE_REG_SO_MCU_MSK 0x80000000
++#define MODE_REG_SO_MCU_I_MSK 0x7fffffff
++#define MODE_REG_SO_MCU_SFT 31
++#define MODE_REG_SO_MCU_HI 31
++#define MODE_REG_SO_MCU_SZ 1
++#define MONITOR_BUS_MCU_31_0_MSK 0xffffffff
++#define MONITOR_BUS_MCU_31_0_I_MSK 0x00000000
++#define MONITOR_BUS_MCU_31_0_SFT 0
++#define MONITOR_BUS_MCU_31_0_HI 31
++#define MONITOR_BUS_MCU_31_0_SZ 32
++#define MONITOR_BUS_MCU_33_32_MSK 0x00000003
++#define MONITOR_BUS_MCU_33_32_I_MSK 0xfffffffc
++#define MONITOR_BUS_MCU_33_32_SFT 0
++#define MONITOR_BUS_MCU_33_32_HI 1
++#define MONITOR_BUS_MCU_33_32_SZ 2
++#define TB_ADR_SEL_MSK 0x0000ffff
++#define TB_ADR_SEL_I_MSK 0xffff0000
++#define TB_ADR_SEL_SFT 0
++#define TB_ADR_SEL_HI 15
++#define TB_ADR_SEL_SZ 16
++#define TB_CS_MSK 0x80000000
++#define TB_CS_I_MSK 0x7fffffff
++#define TB_CS_SFT 31
++#define TB_CS_HI 31
++#define TB_CS_SZ 1
++#define TB_RDATA_MSK 0xffffffff
++#define TB_RDATA_I_MSK 0x00000000
++#define TB_RDATA_SFT 0
++#define TB_RDATA_HI 31
++#define TB_RDATA_SZ 32
++#define UART_W2B_EN_MSK 0x00000001
++#define UART_W2B_EN_I_MSK 0xfffffffe
++#define UART_W2B_EN_SFT 0
++#define UART_W2B_EN_HI 0
++#define UART_W2B_EN_SZ 1
++#define DATA_UART_W2B_EN_MSK 0x00000010
++#define DATA_UART_W2B_EN_I_MSK 0xffffffef
++#define DATA_UART_W2B_EN_SFT 4
++#define DATA_UART_W2B_EN_HI 4
++#define DATA_UART_W2B_EN_SZ 1
++#define AHB_ILL_ADDR_MSK 0xffffffff
++#define AHB_ILL_ADDR_I_MSK 0x00000000
++#define AHB_ILL_ADDR_SFT 0
++#define AHB_ILL_ADDR_HI 31
++#define AHB_ILL_ADDR_SZ 32
++#define AHB_FEN_ADDR_MSK 0xffffffff
++#define AHB_FEN_ADDR_I_MSK 0x00000000
++#define AHB_FEN_ADDR_SFT 0
++#define AHB_FEN_ADDR_HI 31
++#define AHB_FEN_ADDR_SZ 32
++#define ILL_ADDR_CLR_MSK 0x00000001
++#define ILL_ADDR_CLR_I_MSK 0xfffffffe
++#define ILL_ADDR_CLR_SFT 0
++#define ILL_ADDR_CLR_HI 0
++#define ILL_ADDR_CLR_SZ 1
++#define FENCE_HIT_CLR_MSK 0x00000002
++#define FENCE_HIT_CLR_I_MSK 0xfffffffd
++#define FENCE_HIT_CLR_SFT 1
++#define FENCE_HIT_CLR_HI 1
++#define FENCE_HIT_CLR_SZ 1
++#define ILL_ADDR_INT_MSK 0x00000010
++#define ILL_ADDR_INT_I_MSK 0xffffffef
++#define ILL_ADDR_INT_SFT 4
++#define ILL_ADDR_INT_HI 4
++#define ILL_ADDR_INT_SZ 1
++#define FENCE_HIT_INT_MSK 0x00000020
++#define FENCE_HIT_INT_I_MSK 0xffffffdf
++#define FENCE_HIT_INT_SFT 5
++#define FENCE_HIT_INT_HI 5
++#define FENCE_HIT_INT_SZ 1
++#define PWM_INI_VALUE_P_A_MSK 0x000000ff
++#define PWM_INI_VALUE_P_A_I_MSK 0xffffff00
++#define PWM_INI_VALUE_P_A_SFT 0
++#define PWM_INI_VALUE_P_A_HI 7
++#define PWM_INI_VALUE_P_A_SZ 8
++#define PWM_INI_VALUE_N_A_MSK 0x0000ff00
++#define PWM_INI_VALUE_N_A_I_MSK 0xffff00ff
++#define PWM_INI_VALUE_N_A_SFT 8
++#define PWM_INI_VALUE_N_A_HI 15
++#define PWM_INI_VALUE_N_A_SZ 8
++#define PWM_POST_SCALER_A_MSK 0x000f0000
++#define PWM_POST_SCALER_A_I_MSK 0xfff0ffff
++#define PWM_POST_SCALER_A_SFT 16
++#define PWM_POST_SCALER_A_HI 19
++#define PWM_POST_SCALER_A_SZ 4
++#define PWM_ALWAYSON_A_MSK 0x20000000
++#define PWM_ALWAYSON_A_I_MSK 0xdfffffff
++#define PWM_ALWAYSON_A_SFT 29
++#define PWM_ALWAYSON_A_HI 29
++#define PWM_ALWAYSON_A_SZ 1
++#define PWM_INVERT_A_MSK 0x40000000
++#define PWM_INVERT_A_I_MSK 0xbfffffff
++#define PWM_INVERT_A_SFT 30
++#define PWM_INVERT_A_HI 30
++#define PWM_INVERT_A_SZ 1
++#define PWM_ENABLE_A_MSK 0x80000000
++#define PWM_ENABLE_A_I_MSK 0x7fffffff
++#define PWM_ENABLE_A_SFT 31
++#define PWM_ENABLE_A_HI 31
++#define PWM_ENABLE_A_SZ 1
++#define PWM_INI_VALUE_P_B_MSK 0x000000ff
++#define PWM_INI_VALUE_P_B_I_MSK 0xffffff00
++#define PWM_INI_VALUE_P_B_SFT 0
++#define PWM_INI_VALUE_P_B_HI 7
++#define PWM_INI_VALUE_P_B_SZ 8
++#define PWM_INI_VALUE_N_B_MSK 0x0000ff00
++#define PWM_INI_VALUE_N_B_I_MSK 0xffff00ff
++#define PWM_INI_VALUE_N_B_SFT 8
++#define PWM_INI_VALUE_N_B_HI 15
++#define PWM_INI_VALUE_N_B_SZ 8
++#define PWM_POST_SCALER_B_MSK 0x000f0000
++#define PWM_POST_SCALER_B_I_MSK 0xfff0ffff
++#define PWM_POST_SCALER_B_SFT 16
++#define PWM_POST_SCALER_B_HI 19
++#define PWM_POST_SCALER_B_SZ 4
++#define PWM_ALWAYSON_B_MSK 0x20000000
++#define PWM_ALWAYSON_B_I_MSK 0xdfffffff
++#define PWM_ALWAYSON_B_SFT 29
++#define PWM_ALWAYSON_B_HI 29
++#define PWM_ALWAYSON_B_SZ 1
++#define PWM_INVERT_B_MSK 0x40000000
++#define PWM_INVERT_B_I_MSK 0xbfffffff
++#define PWM_INVERT_B_SFT 30
++#define PWM_INVERT_B_HI 30
++#define PWM_INVERT_B_SZ 1
++#define PWM_ENABLE_B_MSK 0x80000000
++#define PWM_ENABLE_B_I_MSK 0x7fffffff
++#define PWM_ENABLE_B_SFT 31
++#define PWM_ENABLE_B_HI 31
++#define PWM_ENABLE_B_SZ 1
++#define HBUSREQ_LOCK_MSK 0x00001fff
++#define HBUSREQ_LOCK_I_MSK 0xffffe000
++#define HBUSREQ_LOCK_SFT 0
++#define HBUSREQ_LOCK_HI 12
++#define HBUSREQ_LOCK_SZ 13
++#define HBURST_LOCK_MSK 0x00001fff
++#define HBURST_LOCK_I_MSK 0xffffe000
++#define HBURST_LOCK_SFT 0
++#define HBURST_LOCK_HI 12
++#define HBURST_LOCK_SZ 13
++#define PRESCALER_USTIMER_MSK 0x000001ff
++#define PRESCALER_USTIMER_I_MSK 0xfffffe00
++#define PRESCALER_USTIMER_SFT 0
++#define PRESCALER_USTIMER_HI 8
++#define PRESCALER_USTIMER_SZ 9
++#define MODE_REG_IN_MMU_MSK 0x0000ffff
++#define MODE_REG_IN_MMU_I_MSK 0xffff0000
++#define MODE_REG_IN_MMU_SFT 0
++#define MODE_REG_IN_MMU_HI 15
++#define MODE_REG_IN_MMU_SZ 16
++#define MODE_REG_OUT_MMU_MSK 0x0000ffff
++#define MODE_REG_OUT_MMU_I_MSK 0xffff0000
++#define MODE_REG_OUT_MMU_SFT 0
++#define MODE_REG_OUT_MMU_HI 15
++#define MODE_REG_OUT_MMU_SZ 16
++#define MODE_REG_SO_MMU_MSK 0x80000000
++#define MODE_REG_SO_MMU_I_MSK 0x7fffffff
++#define MODE_REG_SO_MMU_SFT 31
++#define MODE_REG_SO_MMU_HI 31
++#define MODE_REG_SO_MMU_SZ 1
++#define MONITOR_BUS_MMU_MSK 0x0007ffff
++#define MONITOR_BUS_MMU_I_MSK 0xfff80000
++#define MONITOR_BUS_MMU_SFT 0
++#define MONITOR_BUS_MMU_HI 18
++#define MONITOR_BUS_MMU_SZ 19
++#define TEST_MODE0_MSK 0x00000001
++#define TEST_MODE0_I_MSK 0xfffffffe
++#define TEST_MODE0_SFT 0
++#define TEST_MODE0_HI 0
++#define TEST_MODE0_SZ 1
++#define TEST_MODE1_MSK 0x00000002
++#define TEST_MODE1_I_MSK 0xfffffffd
++#define TEST_MODE1_SFT 1
++#define TEST_MODE1_HI 1
++#define TEST_MODE1_SZ 1
++#define TEST_MODE2_MSK 0x00000004
++#define TEST_MODE2_I_MSK 0xfffffffb
++#define TEST_MODE2_SFT 2
++#define TEST_MODE2_HI 2
++#define TEST_MODE2_SZ 1
++#define TEST_MODE3_MSK 0x00000008
++#define TEST_MODE3_I_MSK 0xfffffff7
++#define TEST_MODE3_SFT 3
++#define TEST_MODE3_HI 3
++#define TEST_MODE3_SZ 1
++#define TEST_MODE4_MSK 0x00000010
++#define TEST_MODE4_I_MSK 0xffffffef
++#define TEST_MODE4_SFT 4
++#define TEST_MODE4_HI 4
++#define TEST_MODE4_SZ 1
++#define TEST_MODE_ALL_MSK 0x00000020
++#define TEST_MODE_ALL_I_MSK 0xffffffdf
++#define TEST_MODE_ALL_SFT 5
++#define TEST_MODE_ALL_HI 5
++#define TEST_MODE_ALL_SZ 1
++#define WDT_INIT_MSK 0x00000001
++#define WDT_INIT_I_MSK 0xfffffffe
++#define WDT_INIT_SFT 0
++#define WDT_INIT_HI 0
++#define WDT_INIT_SZ 1
++#define SD_HOST_INIT_MSK 0x00000002
++#define SD_HOST_INIT_I_MSK 0xfffffffd
++#define SD_HOST_INIT_SFT 1
++#define SD_HOST_INIT_HI 1
++#define SD_HOST_INIT_SZ 1
++#define ALLOW_SD_RESET_MSK 0x00000001
++#define ALLOW_SD_RESET_I_MSK 0xfffffffe
++#define ALLOW_SD_RESET_SFT 0
++#define ALLOW_SD_RESET_HI 0
++#define ALLOW_SD_RESET_SZ 1
++#define UART_NRTS_MSK 0x00000001
++#define UART_NRTS_I_MSK 0xfffffffe
++#define UART_NRTS_SFT 0
++#define UART_NRTS_HI 0
++#define UART_NRTS_SZ 1
++#define UART_NCTS_MSK 0x00000002
++#define UART_NCTS_I_MSK 0xfffffffd
++#define UART_NCTS_SFT 1
++#define UART_NCTS_HI 1
++#define UART_NCTS_SZ 1
++#define TU0_TM_INIT_VALUE_MSK 0x0000ffff
++#define TU0_TM_INIT_VALUE_I_MSK 0xffff0000
++#define TU0_TM_INIT_VALUE_SFT 0
++#define TU0_TM_INIT_VALUE_HI 15
++#define TU0_TM_INIT_VALUE_SZ 16
++#define TU0_TM_MODE_MSK 0x00010000
++#define TU0_TM_MODE_I_MSK 0xfffeffff
++#define TU0_TM_MODE_SFT 16
++#define TU0_TM_MODE_HI 16
++#define TU0_TM_MODE_SZ 1
++#define TU0_TM_INT_STS_DONE_MSK 0x00020000
++#define TU0_TM_INT_STS_DONE_I_MSK 0xfffdffff
++#define TU0_TM_INT_STS_DONE_SFT 17
++#define TU0_TM_INT_STS_DONE_HI 17
++#define TU0_TM_INT_STS_DONE_SZ 1
++#define TU0_TM_INT_MASK_MSK 0x00040000
++#define TU0_TM_INT_MASK_I_MSK 0xfffbffff
++#define TU0_TM_INT_MASK_SFT 18
++#define TU0_TM_INT_MASK_HI 18
++#define TU0_TM_INT_MASK_SZ 1
++#define TU0_TM_CUR_VALUE_MSK 0x0000ffff
++#define TU0_TM_CUR_VALUE_I_MSK 0xffff0000
++#define TU0_TM_CUR_VALUE_SFT 0
++#define TU0_TM_CUR_VALUE_HI 15
++#define TU0_TM_CUR_VALUE_SZ 16
++#define TU1_TM_INIT_VALUE_MSK 0x0000ffff
++#define TU1_TM_INIT_VALUE_I_MSK 0xffff0000
++#define TU1_TM_INIT_VALUE_SFT 0
++#define TU1_TM_INIT_VALUE_HI 15
++#define TU1_TM_INIT_VALUE_SZ 16
++#define TU1_TM_MODE_MSK 0x00010000
++#define TU1_TM_MODE_I_MSK 0xfffeffff
++#define TU1_TM_MODE_SFT 16
++#define TU1_TM_MODE_HI 16
++#define TU1_TM_MODE_SZ 1
++#define TU1_TM_INT_STS_DONE_MSK 0x00020000
++#define TU1_TM_INT_STS_DONE_I_MSK 0xfffdffff
++#define TU1_TM_INT_STS_DONE_SFT 17
++#define TU1_TM_INT_STS_DONE_HI 17
++#define TU1_TM_INT_STS_DONE_SZ 1
++#define TU1_TM_INT_MASK_MSK 0x00040000
++#define TU1_TM_INT_MASK_I_MSK 0xfffbffff
++#define TU1_TM_INT_MASK_SFT 18
++#define TU1_TM_INT_MASK_HI 18
++#define TU1_TM_INT_MASK_SZ 1
++#define TU1_TM_CUR_VALUE_MSK 0x0000ffff
++#define TU1_TM_CUR_VALUE_I_MSK 0xffff0000
++#define TU1_TM_CUR_VALUE_SFT 0
++#define TU1_TM_CUR_VALUE_HI 15
++#define TU1_TM_CUR_VALUE_SZ 16
++#define TU2_TM_INIT_VALUE_MSK 0x0000ffff
++#define TU2_TM_INIT_VALUE_I_MSK 0xffff0000
++#define TU2_TM_INIT_VALUE_SFT 0
++#define TU2_TM_INIT_VALUE_HI 15
++#define TU2_TM_INIT_VALUE_SZ 16
++#define TU2_TM_MODE_MSK 0x00010000
++#define TU2_TM_MODE_I_MSK 0xfffeffff
++#define TU2_TM_MODE_SFT 16
++#define TU2_TM_MODE_HI 16
++#define TU2_TM_MODE_SZ 1
++#define TU2_TM_INT_STS_DONE_MSK 0x00020000
++#define TU2_TM_INT_STS_DONE_I_MSK 0xfffdffff
++#define TU2_TM_INT_STS_DONE_SFT 17
++#define TU2_TM_INT_STS_DONE_HI 17
++#define TU2_TM_INT_STS_DONE_SZ 1
++#define TU2_TM_INT_MASK_MSK 0x00040000
++#define TU2_TM_INT_MASK_I_MSK 0xfffbffff
++#define TU2_TM_INT_MASK_SFT 18
++#define TU2_TM_INT_MASK_HI 18
++#define TU2_TM_INT_MASK_SZ 1
++#define TU2_TM_CUR_VALUE_MSK 0x0000ffff
++#define TU2_TM_CUR_VALUE_I_MSK 0xffff0000
++#define TU2_TM_CUR_VALUE_SFT 0
++#define TU2_TM_CUR_VALUE_HI 15
++#define TU2_TM_CUR_VALUE_SZ 16
++#define TU3_TM_INIT_VALUE_MSK 0x0000ffff
++#define TU3_TM_INIT_VALUE_I_MSK 0xffff0000
++#define TU3_TM_INIT_VALUE_SFT 0
++#define TU3_TM_INIT_VALUE_HI 15
++#define TU3_TM_INIT_VALUE_SZ 16
++#define TU3_TM_MODE_MSK 0x00010000
++#define TU3_TM_MODE_I_MSK 0xfffeffff
++#define TU3_TM_MODE_SFT 16
++#define TU3_TM_MODE_HI 16
++#define TU3_TM_MODE_SZ 1
++#define TU3_TM_INT_STS_DONE_MSK 0x00020000
++#define TU3_TM_INT_STS_DONE_I_MSK 0xfffdffff
++#define TU3_TM_INT_STS_DONE_SFT 17
++#define TU3_TM_INT_STS_DONE_HI 17
++#define TU3_TM_INT_STS_DONE_SZ 1
++#define TU3_TM_INT_MASK_MSK 0x00040000
++#define TU3_TM_INT_MASK_I_MSK 0xfffbffff
++#define TU3_TM_INT_MASK_SFT 18
++#define TU3_TM_INT_MASK_HI 18
++#define TU3_TM_INT_MASK_SZ 1
++#define TU3_TM_CUR_VALUE_MSK 0x0000ffff
++#define TU3_TM_CUR_VALUE_I_MSK 0xffff0000
++#define TU3_TM_CUR_VALUE_SFT 0
++#define TU3_TM_CUR_VALUE_HI 15
++#define TU3_TM_CUR_VALUE_SZ 16
++#define TM0_TM_INIT_VALUE_MSK 0x0000ffff
++#define TM0_TM_INIT_VALUE_I_MSK 0xffff0000
++#define TM0_TM_INIT_VALUE_SFT 0
++#define TM0_TM_INIT_VALUE_HI 15
++#define TM0_TM_INIT_VALUE_SZ 16
++#define TM0_TM_MODE_MSK 0x00010000
++#define TM0_TM_MODE_I_MSK 0xfffeffff
++#define TM0_TM_MODE_SFT 16
++#define TM0_TM_MODE_HI 16
++#define TM0_TM_MODE_SZ 1
++#define TM0_TM_INT_STS_DONE_MSK 0x00020000
++#define TM0_TM_INT_STS_DONE_I_MSK 0xfffdffff
++#define TM0_TM_INT_STS_DONE_SFT 17
++#define TM0_TM_INT_STS_DONE_HI 17
++#define TM0_TM_INT_STS_DONE_SZ 1
++#define TM0_TM_INT_MASK_MSK 0x00040000
++#define TM0_TM_INT_MASK_I_MSK 0xfffbffff
++#define TM0_TM_INT_MASK_SFT 18
++#define TM0_TM_INT_MASK_HI 18
++#define TM0_TM_INT_MASK_SZ 1
++#define TM0_TM_CUR_VALUE_MSK 0x0000ffff
++#define TM0_TM_CUR_VALUE_I_MSK 0xffff0000
++#define TM0_TM_CUR_VALUE_SFT 0
++#define TM0_TM_CUR_VALUE_HI 15
++#define TM0_TM_CUR_VALUE_SZ 16
++#define TM1_TM_INIT_VALUE_MSK 0x0000ffff
++#define TM1_TM_INIT_VALUE_I_MSK 0xffff0000
++#define TM1_TM_INIT_VALUE_SFT 0
++#define TM1_TM_INIT_VALUE_HI 15
++#define TM1_TM_INIT_VALUE_SZ 16
++#define TM1_TM_MODE_MSK 0x00010000
++#define TM1_TM_MODE_I_MSK 0xfffeffff
++#define TM1_TM_MODE_SFT 16
++#define TM1_TM_MODE_HI 16
++#define TM1_TM_MODE_SZ 1
++#define TM1_TM_INT_STS_DONE_MSK 0x00020000
++#define TM1_TM_INT_STS_DONE_I_MSK 0xfffdffff
++#define TM1_TM_INT_STS_DONE_SFT 17
++#define TM1_TM_INT_STS_DONE_HI 17
++#define TM1_TM_INT_STS_DONE_SZ 1
++#define TM1_TM_INT_MASK_MSK 0x00040000
++#define TM1_TM_INT_MASK_I_MSK 0xfffbffff
++#define TM1_TM_INT_MASK_SFT 18
++#define TM1_TM_INT_MASK_HI 18
++#define TM1_TM_INT_MASK_SZ 1
++#define TM1_TM_CUR_VALUE_MSK 0x0000ffff
++#define TM1_TM_CUR_VALUE_I_MSK 0xffff0000
++#define TM1_TM_CUR_VALUE_SFT 0
++#define TM1_TM_CUR_VALUE_HI 15
++#define TM1_TM_CUR_VALUE_SZ 16
++#define TM2_TM_INIT_VALUE_MSK 0x0000ffff
++#define TM2_TM_INIT_VALUE_I_MSK 0xffff0000
++#define TM2_TM_INIT_VALUE_SFT 0
++#define TM2_TM_INIT_VALUE_HI 15
++#define TM2_TM_INIT_VALUE_SZ 16
++#define TM2_TM_MODE_MSK 0x00010000
++#define TM2_TM_MODE_I_MSK 0xfffeffff
++#define TM2_TM_MODE_SFT 16
++#define TM2_TM_MODE_HI 16
++#define TM2_TM_MODE_SZ 1
++#define TM2_TM_INT_STS_DONE_MSK 0x00020000
++#define TM2_TM_INT_STS_DONE_I_MSK 0xfffdffff
++#define TM2_TM_INT_STS_DONE_SFT 17
++#define TM2_TM_INT_STS_DONE_HI 17
++#define TM2_TM_INT_STS_DONE_SZ 1
++#define TM2_TM_INT_MASK_MSK 0x00040000
++#define TM2_TM_INT_MASK_I_MSK 0xfffbffff
++#define TM2_TM_INT_MASK_SFT 18
++#define TM2_TM_INT_MASK_HI 18
++#define TM2_TM_INT_MASK_SZ 1
++#define TM2_TM_CUR_VALUE_MSK 0x0000ffff
++#define TM2_TM_CUR_VALUE_I_MSK 0xffff0000
++#define TM2_TM_CUR_VALUE_SFT 0
++#define TM2_TM_CUR_VALUE_HI 15
++#define TM2_TM_CUR_VALUE_SZ 16
++#define TM3_TM_INIT_VALUE_MSK 0x0000ffff
++#define TM3_TM_INIT_VALUE_I_MSK 0xffff0000
++#define TM3_TM_INIT_VALUE_SFT 0
++#define TM3_TM_INIT_VALUE_HI 15
++#define TM3_TM_INIT_VALUE_SZ 16
++#define TM3_TM_MODE_MSK 0x00010000
++#define TM3_TM_MODE_I_MSK 0xfffeffff
++#define TM3_TM_MODE_SFT 16
++#define TM3_TM_MODE_HI 16
++#define TM3_TM_MODE_SZ 1
++#define TM3_TM_INT_STS_DONE_MSK 0x00020000
++#define TM3_TM_INT_STS_DONE_I_MSK 0xfffdffff
++#define TM3_TM_INT_STS_DONE_SFT 17
++#define TM3_TM_INT_STS_DONE_HI 17
++#define TM3_TM_INT_STS_DONE_SZ 1
++#define TM3_TM_INT_MASK_MSK 0x00040000
++#define TM3_TM_INT_MASK_I_MSK 0xfffbffff
++#define TM3_TM_INT_MASK_SFT 18
++#define TM3_TM_INT_MASK_HI 18
++#define TM3_TM_INT_MASK_SZ 1
++#define TM3_TM_CUR_VALUE_MSK 0x0000ffff
++#define TM3_TM_CUR_VALUE_I_MSK 0xffff0000
++#define TM3_TM_CUR_VALUE_SFT 0
++#define TM3_TM_CUR_VALUE_HI 15
++#define TM3_TM_CUR_VALUE_SZ 16
++#define MCU_WDT_TIME_CNT_MSK 0x0000ffff
++#define MCU_WDT_TIME_CNT_I_MSK 0xffff0000
++#define MCU_WDT_TIME_CNT_SFT 0
++#define MCU_WDT_TIME_CNT_HI 15
++#define MCU_WDT_TIME_CNT_SZ 16
++#define MCU_WDT_STATUS_MSK 0x00020000
++#define MCU_WDT_STATUS_I_MSK 0xfffdffff
++#define MCU_WDT_STATUS_SFT 17
++#define MCU_WDT_STATUS_HI 17
++#define MCU_WDT_STATUS_SZ 1
++#define MCU_WDOG_ENA_MSK 0x80000000
++#define MCU_WDOG_ENA_I_MSK 0x7fffffff
++#define MCU_WDOG_ENA_SFT 31
++#define MCU_WDOG_ENA_HI 31
++#define MCU_WDOG_ENA_SZ 1
++#define SYS_WDT_TIME_CNT_MSK 0x0000ffff
++#define SYS_WDT_TIME_CNT_I_MSK 0xffff0000
++#define SYS_WDT_TIME_CNT_SFT 0
++#define SYS_WDT_TIME_CNT_HI 15
++#define SYS_WDT_TIME_CNT_SZ 16
++#define SYS_WDT_STATUS_MSK 0x00020000
++#define SYS_WDT_STATUS_I_MSK 0xfffdffff
++#define SYS_WDT_STATUS_SFT 17
++#define SYS_WDT_STATUS_HI 17
++#define SYS_WDT_STATUS_SZ 1
++#define SYS_WDOG_ENA_MSK 0x80000000
++#define SYS_WDOG_ENA_I_MSK 0x7fffffff
++#define SYS_WDOG_ENA_SFT 31
++#define SYS_WDOG_ENA_HI 31
++#define SYS_WDOG_ENA_SZ 1
++#define XLNA_EN_O_OE_MSK 0x00000001
++#define XLNA_EN_O_OE_I_MSK 0xfffffffe
++#define XLNA_EN_O_OE_SFT 0
++#define XLNA_EN_O_OE_HI 0
++#define XLNA_EN_O_OE_SZ 1
++#define XLNA_EN_O_PE_MSK 0x00000002
++#define XLNA_EN_O_PE_I_MSK 0xfffffffd
++#define XLNA_EN_O_PE_SFT 1
++#define XLNA_EN_O_PE_HI 1
++#define XLNA_EN_O_PE_SZ 1
++#define PAD6_IE_MSK 0x00000008
++#define PAD6_IE_I_MSK 0xfffffff7
++#define PAD6_IE_SFT 3
++#define PAD6_IE_HI 3
++#define PAD6_IE_SZ 1
++#define PAD6_SEL_I_MSK 0x00000030
++#define PAD6_SEL_I_I_MSK 0xffffffcf
++#define PAD6_SEL_I_SFT 4
++#define PAD6_SEL_I_HI 5
++#define PAD6_SEL_I_SZ 2
++#define PAD6_OD_MSK 0x00000100
++#define PAD6_OD_I_MSK 0xfffffeff
++#define PAD6_OD_SFT 8
++#define PAD6_OD_HI 8
++#define PAD6_OD_SZ 1
++#define PAD6_SEL_O_MSK 0x00001000
++#define PAD6_SEL_O_I_MSK 0xffffefff
++#define PAD6_SEL_O_SFT 12
++#define PAD6_SEL_O_HI 12
++#define PAD6_SEL_O_SZ 1
++#define XLNA_EN_O_C_MSK 0x10000000
++#define XLNA_EN_O_C_I_MSK 0xefffffff
++#define XLNA_EN_O_C_SFT 28
++#define XLNA_EN_O_C_HI 28
++#define XLNA_EN_O_C_SZ 1
++#define WIFI_TX_SW_O_OE_MSK 0x00000001
++#define WIFI_TX_SW_O_OE_I_MSK 0xfffffffe
++#define WIFI_TX_SW_O_OE_SFT 0
++#define WIFI_TX_SW_O_OE_HI 0
++#define WIFI_TX_SW_O_OE_SZ 1
++#define WIFI_TX_SW_O_PE_MSK 0x00000002
++#define WIFI_TX_SW_O_PE_I_MSK 0xfffffffd
++#define WIFI_TX_SW_O_PE_SFT 1
++#define WIFI_TX_SW_O_PE_HI 1
++#define WIFI_TX_SW_O_PE_SZ 1
++#define PAD7_IE_MSK 0x00000008
++#define PAD7_IE_I_MSK 0xfffffff7
++#define PAD7_IE_SFT 3
++#define PAD7_IE_HI 3
++#define PAD7_IE_SZ 1
++#define PAD7_SEL_I_MSK 0x00000030
++#define PAD7_SEL_I_I_MSK 0xffffffcf
++#define PAD7_SEL_I_SFT 4
++#define PAD7_SEL_I_HI 5
++#define PAD7_SEL_I_SZ 2
++#define PAD7_OD_MSK 0x00000100
++#define PAD7_OD_I_MSK 0xfffffeff
++#define PAD7_OD_SFT 8
++#define PAD7_OD_HI 8
++#define PAD7_OD_SZ 1
++#define PAD7_SEL_O_MSK 0x00001000
++#define PAD7_SEL_O_I_MSK 0xffffefff
++#define PAD7_SEL_O_SFT 12
++#define PAD7_SEL_O_HI 12
++#define PAD7_SEL_O_SZ 1
++#define WIFI_TX_SW_O_C_MSK 0x10000000
++#define WIFI_TX_SW_O_C_I_MSK 0xefffffff
++#define WIFI_TX_SW_O_C_SFT 28
++#define WIFI_TX_SW_O_C_HI 28
++#define WIFI_TX_SW_O_C_SZ 1
++#define WIFI_RX_SW_O_OE_MSK 0x00000001
++#define WIFI_RX_SW_O_OE_I_MSK 0xfffffffe
++#define WIFI_RX_SW_O_OE_SFT 0
++#define WIFI_RX_SW_O_OE_HI 0
++#define WIFI_RX_SW_O_OE_SZ 1
++#define WIFI_RX_SW_O_PE_MSK 0x00000002
++#define WIFI_RX_SW_O_PE_I_MSK 0xfffffffd
++#define WIFI_RX_SW_O_PE_SFT 1
++#define WIFI_RX_SW_O_PE_HI 1
++#define WIFI_RX_SW_O_PE_SZ 1
++#define PAD8_IE_MSK 0x00000008
++#define PAD8_IE_I_MSK 0xfffffff7
++#define PAD8_IE_SFT 3
++#define PAD8_IE_HI 3
++#define PAD8_IE_SZ 1
++#define PAD8_SEL_I_MSK 0x00000030
++#define PAD8_SEL_I_I_MSK 0xffffffcf
++#define PAD8_SEL_I_SFT 4
++#define PAD8_SEL_I_HI 5
++#define PAD8_SEL_I_SZ 2
++#define PAD8_OD_MSK 0x00000100
++#define PAD8_OD_I_MSK 0xfffffeff
++#define PAD8_OD_SFT 8
++#define PAD8_OD_HI 8
++#define PAD8_OD_SZ 1
++#define WIFI_RX_SW_O_C_MSK 0x10000000
++#define WIFI_RX_SW_O_C_I_MSK 0xefffffff
++#define WIFI_RX_SW_O_C_SFT 28
++#define WIFI_RX_SW_O_C_HI 28
++#define WIFI_RX_SW_O_C_SZ 1
++#define BT_SW_O_OE_MSK 0x00000001
++#define BT_SW_O_OE_I_MSK 0xfffffffe
++#define BT_SW_O_OE_SFT 0
++#define BT_SW_O_OE_HI 0
++#define BT_SW_O_OE_SZ 1
++#define BT_SW_O_PE_MSK 0x00000002
++#define BT_SW_O_PE_I_MSK 0xfffffffd
++#define BT_SW_O_PE_SFT 1
++#define BT_SW_O_PE_HI 1
++#define BT_SW_O_PE_SZ 1
++#define PAD9_IE_MSK 0x00000008
++#define PAD9_IE_I_MSK 0xfffffff7
++#define PAD9_IE_SFT 3
++#define PAD9_IE_HI 3
++#define PAD9_IE_SZ 1
++#define PAD9_SEL_I_MSK 0x00000030
++#define PAD9_SEL_I_I_MSK 0xffffffcf
++#define PAD9_SEL_I_SFT 4
++#define PAD9_SEL_I_HI 5
++#define PAD9_SEL_I_SZ 2
++#define PAD9_OD_MSK 0x00000100
++#define PAD9_OD_I_MSK 0xfffffeff
++#define PAD9_OD_SFT 8
++#define PAD9_OD_HI 8
++#define PAD9_OD_SZ 1
++#define PAD9_SEL_O_MSK 0x00001000
++#define PAD9_SEL_O_I_MSK 0xffffefff
++#define PAD9_SEL_O_SFT 12
++#define PAD9_SEL_O_HI 12
++#define PAD9_SEL_O_SZ 1
++#define BT_SW_O_C_MSK 0x10000000
++#define BT_SW_O_C_I_MSK 0xefffffff
++#define BT_SW_O_C_SFT 28
++#define BT_SW_O_C_HI 28
++#define BT_SW_O_C_SZ 1
++#define XPA_EN_O_OE_MSK 0x00000001
++#define XPA_EN_O_OE_I_MSK 0xfffffffe
++#define XPA_EN_O_OE_SFT 0
++#define XPA_EN_O_OE_HI 0
++#define XPA_EN_O_OE_SZ 1
++#define XPA_EN_O_PE_MSK 0x00000002
++#define XPA_EN_O_PE_I_MSK 0xfffffffd
++#define XPA_EN_O_PE_SFT 1
++#define XPA_EN_O_PE_HI 1
++#define XPA_EN_O_PE_SZ 1
++#define PAD11_IE_MSK 0x00000008
++#define PAD11_IE_I_MSK 0xfffffff7
++#define PAD11_IE_SFT 3
++#define PAD11_IE_HI 3
++#define PAD11_IE_SZ 1
++#define PAD11_SEL_I_MSK 0x00000030
++#define PAD11_SEL_I_I_MSK 0xffffffcf
++#define PAD11_SEL_I_SFT 4
++#define PAD11_SEL_I_HI 5
++#define PAD11_SEL_I_SZ 2
++#define PAD11_OD_MSK 0x00000100
++#define PAD11_OD_I_MSK 0xfffffeff
++#define PAD11_OD_SFT 8
++#define PAD11_OD_HI 8
++#define PAD11_OD_SZ 1
++#define PAD11_SEL_O_MSK 0x00001000
++#define PAD11_SEL_O_I_MSK 0xffffefff
++#define PAD11_SEL_O_SFT 12
++#define PAD11_SEL_O_HI 12
++#define PAD11_SEL_O_SZ 1
++#define XPA_EN_O_C_MSK 0x10000000
++#define XPA_EN_O_C_I_MSK 0xefffffff
++#define XPA_EN_O_C_SFT 28
++#define XPA_EN_O_C_HI 28
++#define XPA_EN_O_C_SZ 1
++#define PAD15_OE_MSK 0x00000001
++#define PAD15_OE_I_MSK 0xfffffffe
++#define PAD15_OE_SFT 0
++#define PAD15_OE_HI 0
++#define PAD15_OE_SZ 1
++#define PAD15_PE_MSK 0x00000002
++#define PAD15_PE_I_MSK 0xfffffffd
++#define PAD15_PE_SFT 1
++#define PAD15_PE_HI 1
++#define PAD15_PE_SZ 1
++#define PAD15_DS_MSK 0x00000004
++#define PAD15_DS_I_MSK 0xfffffffb
++#define PAD15_DS_SFT 2
++#define PAD15_DS_HI 2
++#define PAD15_DS_SZ 1
++#define PAD15_IE_MSK 0x00000008
++#define PAD15_IE_I_MSK 0xfffffff7
++#define PAD15_IE_SFT 3
++#define PAD15_IE_HI 3
++#define PAD15_IE_SZ 1
++#define PAD15_SEL_I_MSK 0x00000030
++#define PAD15_SEL_I_I_MSK 0xffffffcf
++#define PAD15_SEL_I_SFT 4
++#define PAD15_SEL_I_HI 5
++#define PAD15_SEL_I_SZ 2
++#define PAD15_OD_MSK 0x00000100
++#define PAD15_OD_I_MSK 0xfffffeff
++#define PAD15_OD_SFT 8
++#define PAD15_OD_HI 8
++#define PAD15_OD_SZ 1
++#define PAD15_SEL_O_MSK 0x00001000
++#define PAD15_SEL_O_I_MSK 0xffffefff
++#define PAD15_SEL_O_SFT 12
++#define PAD15_SEL_O_HI 12
++#define PAD15_SEL_O_SZ 1
++#define TEST_1_ID_MSK 0x10000000
++#define TEST_1_ID_I_MSK 0xefffffff
++#define TEST_1_ID_SFT 28
++#define TEST_1_ID_HI 28
++#define TEST_1_ID_SZ 1
++#define PAD16_OE_MSK 0x00000001
++#define PAD16_OE_I_MSK 0xfffffffe
++#define PAD16_OE_SFT 0
++#define PAD16_OE_HI 0
++#define PAD16_OE_SZ 1
++#define PAD16_PE_MSK 0x00000002
++#define PAD16_PE_I_MSK 0xfffffffd
++#define PAD16_PE_SFT 1
++#define PAD16_PE_HI 1
++#define PAD16_PE_SZ 1
++#define PAD16_DS_MSK 0x00000004
++#define PAD16_DS_I_MSK 0xfffffffb
++#define PAD16_DS_SFT 2
++#define PAD16_DS_HI 2
++#define PAD16_DS_SZ 1
++#define PAD16_IE_MSK 0x00000008
++#define PAD16_IE_I_MSK 0xfffffff7
++#define PAD16_IE_SFT 3
++#define PAD16_IE_HI 3
++#define PAD16_IE_SZ 1
++#define PAD16_SEL_I_MSK 0x00000030
++#define PAD16_SEL_I_I_MSK 0xffffffcf
++#define PAD16_SEL_I_SFT 4
++#define PAD16_SEL_I_HI 5
++#define PAD16_SEL_I_SZ 2
++#define PAD16_OD_MSK 0x00000100
++#define PAD16_OD_I_MSK 0xfffffeff
++#define PAD16_OD_SFT 8
++#define PAD16_OD_HI 8
++#define PAD16_OD_SZ 1
++#define PAD16_SEL_O_MSK 0x00001000
++#define PAD16_SEL_O_I_MSK 0xffffefff
++#define PAD16_SEL_O_SFT 12
++#define PAD16_SEL_O_HI 12
++#define PAD16_SEL_O_SZ 1
++#define TEST_2_ID_MSK 0x10000000
++#define TEST_2_ID_I_MSK 0xefffffff
++#define TEST_2_ID_SFT 28
++#define TEST_2_ID_HI 28
++#define TEST_2_ID_SZ 1
++#define PAD17_OE_MSK 0x00000001
++#define PAD17_OE_I_MSK 0xfffffffe
++#define PAD17_OE_SFT 0
++#define PAD17_OE_HI 0
++#define PAD17_OE_SZ 1
++#define PAD17_PE_MSK 0x00000002
++#define PAD17_PE_I_MSK 0xfffffffd
++#define PAD17_PE_SFT 1
++#define PAD17_PE_HI 1
++#define PAD17_PE_SZ 1
++#define PAD17_DS_MSK 0x00000004
++#define PAD17_DS_I_MSK 0xfffffffb
++#define PAD17_DS_SFT 2
++#define PAD17_DS_HI 2
++#define PAD17_DS_SZ 1
++#define PAD17_IE_MSK 0x00000008
++#define PAD17_IE_I_MSK 0xfffffff7
++#define PAD17_IE_SFT 3
++#define PAD17_IE_HI 3
++#define PAD17_IE_SZ 1
++#define PAD17_SEL_I_MSK 0x00000030
++#define PAD17_SEL_I_I_MSK 0xffffffcf
++#define PAD17_SEL_I_SFT 4
++#define PAD17_SEL_I_HI 5
++#define PAD17_SEL_I_SZ 2
++#define PAD17_OD_MSK 0x00000100
++#define PAD17_OD_I_MSK 0xfffffeff
++#define PAD17_OD_SFT 8
++#define PAD17_OD_HI 8
++#define PAD17_OD_SZ 1
++#define PAD17_SEL_O_MSK 0x00001000
++#define PAD17_SEL_O_I_MSK 0xffffefff
++#define PAD17_SEL_O_SFT 12
++#define PAD17_SEL_O_HI 12
++#define PAD17_SEL_O_SZ 1
++#define TEST_3_ID_MSK 0x10000000
++#define TEST_3_ID_I_MSK 0xefffffff
++#define TEST_3_ID_SFT 28
++#define TEST_3_ID_HI 28
++#define TEST_3_ID_SZ 1
++#define PAD18_OE_MSK 0x00000001
++#define PAD18_OE_I_MSK 0xfffffffe
++#define PAD18_OE_SFT 0
++#define PAD18_OE_HI 0
++#define PAD18_OE_SZ 1
++#define PAD18_PE_MSK 0x00000002
++#define PAD18_PE_I_MSK 0xfffffffd
++#define PAD18_PE_SFT 1
++#define PAD18_PE_HI 1
++#define PAD18_PE_SZ 1
++#define PAD18_DS_MSK 0x00000004
++#define PAD18_DS_I_MSK 0xfffffffb
++#define PAD18_DS_SFT 2
++#define PAD18_DS_HI 2
++#define PAD18_DS_SZ 1
++#define PAD18_IE_MSK 0x00000008
++#define PAD18_IE_I_MSK 0xfffffff7
++#define PAD18_IE_SFT 3
++#define PAD18_IE_HI 3
++#define PAD18_IE_SZ 1
++#define PAD18_SEL_I_MSK 0x00000030
++#define PAD18_SEL_I_I_MSK 0xffffffcf
++#define PAD18_SEL_I_SFT 4
++#define PAD18_SEL_I_HI 5
++#define PAD18_SEL_I_SZ 2
++#define PAD18_OD_MSK 0x00000100
++#define PAD18_OD_I_MSK 0xfffffeff
++#define PAD18_OD_SFT 8
++#define PAD18_OD_HI 8
++#define PAD18_OD_SZ 1
++#define PAD18_SEL_O_MSK 0x00003000
++#define PAD18_SEL_O_I_MSK 0xffffcfff
++#define PAD18_SEL_O_SFT 12
++#define PAD18_SEL_O_HI 13
++#define PAD18_SEL_O_SZ 2
++#define TEST_4_ID_MSK 0x10000000
++#define TEST_4_ID_I_MSK 0xefffffff
++#define TEST_4_ID_SFT 28
++#define TEST_4_ID_HI 28
++#define TEST_4_ID_SZ 1
++#define PAD19_OE_MSK 0x00000001
++#define PAD19_OE_I_MSK 0xfffffffe
++#define PAD19_OE_SFT 0
++#define PAD19_OE_HI 0
++#define PAD19_OE_SZ 1
++#define PAD19_PE_MSK 0x00000002
++#define PAD19_PE_I_MSK 0xfffffffd
++#define PAD19_PE_SFT 1
++#define PAD19_PE_HI 1
++#define PAD19_PE_SZ 1
++#define PAD19_DS_MSK 0x00000004
++#define PAD19_DS_I_MSK 0xfffffffb
++#define PAD19_DS_SFT 2
++#define PAD19_DS_HI 2
++#define PAD19_DS_SZ 1
++#define PAD19_IE_MSK 0x00000008
++#define PAD19_IE_I_MSK 0xfffffff7
++#define PAD19_IE_SFT 3
++#define PAD19_IE_HI 3
++#define PAD19_IE_SZ 1
++#define PAD19_SEL_I_MSK 0x00000030
++#define PAD19_SEL_I_I_MSK 0xffffffcf
++#define PAD19_SEL_I_SFT 4
++#define PAD19_SEL_I_HI 5
++#define PAD19_SEL_I_SZ 2
++#define PAD19_OD_MSK 0x00000100
++#define PAD19_OD_I_MSK 0xfffffeff
++#define PAD19_OD_SFT 8
++#define PAD19_OD_HI 8
++#define PAD19_OD_SZ 1
++#define PAD19_SEL_O_MSK 0x00007000
++#define PAD19_SEL_O_I_MSK 0xffff8fff
++#define PAD19_SEL_O_SFT 12
++#define PAD19_SEL_O_HI 14
++#define PAD19_SEL_O_SZ 3
++#define SHORT_TO_20_ID_MSK 0x10000000
++#define SHORT_TO_20_ID_I_MSK 0xefffffff
++#define SHORT_TO_20_ID_SFT 28
++#define SHORT_TO_20_ID_HI 28
++#define SHORT_TO_20_ID_SZ 1
++#define PAD20_OE_MSK 0x00000001
++#define PAD20_OE_I_MSK 0xfffffffe
++#define PAD20_OE_SFT 0
++#define PAD20_OE_HI 0
++#define PAD20_OE_SZ 1
++#define PAD20_PE_MSK 0x00000002
++#define PAD20_PE_I_MSK 0xfffffffd
++#define PAD20_PE_SFT 1
++#define PAD20_PE_HI 1
++#define PAD20_PE_SZ 1
++#define PAD20_DS_MSK 0x00000004
++#define PAD20_DS_I_MSK 0xfffffffb
++#define PAD20_DS_SFT 2
++#define PAD20_DS_HI 2
++#define PAD20_DS_SZ 1
++#define PAD20_IE_MSK 0x00000008
++#define PAD20_IE_I_MSK 0xfffffff7
++#define PAD20_IE_SFT 3
++#define PAD20_IE_HI 3
++#define PAD20_IE_SZ 1
++#define PAD20_SEL_I_MSK 0x000000f0
++#define PAD20_SEL_I_I_MSK 0xffffff0f
++#define PAD20_SEL_I_SFT 4
++#define PAD20_SEL_I_HI 7
++#define PAD20_SEL_I_SZ 4
++#define PAD20_OD_MSK 0x00000100
++#define PAD20_OD_I_MSK 0xfffffeff
++#define PAD20_OD_SFT 8
++#define PAD20_OD_HI 8
++#define PAD20_OD_SZ 1
++#define PAD20_SEL_O_MSK 0x00003000
++#define PAD20_SEL_O_I_MSK 0xffffcfff
++#define PAD20_SEL_O_SFT 12
++#define PAD20_SEL_O_HI 13
++#define PAD20_SEL_O_SZ 2
++#define STRAP0_MSK 0x08000000
++#define STRAP0_I_MSK 0xf7ffffff
++#define STRAP0_SFT 27
++#define STRAP0_HI 27
++#define STRAP0_SZ 1
++#define GPIO_TEST_1_ID_MSK 0x10000000
++#define GPIO_TEST_1_ID_I_MSK 0xefffffff
++#define GPIO_TEST_1_ID_SFT 28
++#define GPIO_TEST_1_ID_HI 28
++#define GPIO_TEST_1_ID_SZ 1
++#define PAD21_OE_MSK 0x00000001
++#define PAD21_OE_I_MSK 0xfffffffe
++#define PAD21_OE_SFT 0
++#define PAD21_OE_HI 0
++#define PAD21_OE_SZ 1
++#define PAD21_PE_MSK 0x00000002
++#define PAD21_PE_I_MSK 0xfffffffd
++#define PAD21_PE_SFT 1
++#define PAD21_PE_HI 1
++#define PAD21_PE_SZ 1
++#define PAD21_DS_MSK 0x00000004
++#define PAD21_DS_I_MSK 0xfffffffb
++#define PAD21_DS_SFT 2
++#define PAD21_DS_HI 2
++#define PAD21_DS_SZ 1
++#define PAD21_IE_MSK 0x00000008
++#define PAD21_IE_I_MSK 0xfffffff7
++#define PAD21_IE_SFT 3
++#define PAD21_IE_HI 3
++#define PAD21_IE_SZ 1
++#define PAD21_SEL_I_MSK 0x00000070
++#define PAD21_SEL_I_I_MSK 0xffffff8f
++#define PAD21_SEL_I_SFT 4
++#define PAD21_SEL_I_HI 6
++#define PAD21_SEL_I_SZ 3
++#define PAD21_OD_MSK 0x00000100
++#define PAD21_OD_I_MSK 0xfffffeff
++#define PAD21_OD_SFT 8
++#define PAD21_OD_HI 8
++#define PAD21_OD_SZ 1
++#define PAD21_SEL_O_MSK 0x00003000
++#define PAD21_SEL_O_I_MSK 0xffffcfff
++#define PAD21_SEL_O_SFT 12
++#define PAD21_SEL_O_HI 13
++#define PAD21_SEL_O_SZ 2
++#define STRAP3_MSK 0x08000000
++#define STRAP3_I_MSK 0xf7ffffff
++#define STRAP3_SFT 27
++#define STRAP3_HI 27
++#define STRAP3_SZ 1
++#define GPIO_TEST_2_ID_MSK 0x10000000
++#define GPIO_TEST_2_ID_I_MSK 0xefffffff
++#define GPIO_TEST_2_ID_SFT 28
++#define GPIO_TEST_2_ID_HI 28
++#define GPIO_TEST_2_ID_SZ 1
++#define PAD22_OE_MSK 0x00000001
++#define PAD22_OE_I_MSK 0xfffffffe
++#define PAD22_OE_SFT 0
++#define PAD22_OE_HI 0
++#define PAD22_OE_SZ 1
++#define PAD22_PE_MSK 0x00000002
++#define PAD22_PE_I_MSK 0xfffffffd
++#define PAD22_PE_SFT 1
++#define PAD22_PE_HI 1
++#define PAD22_PE_SZ 1
++#define PAD22_DS_MSK 0x00000004
++#define PAD22_DS_I_MSK 0xfffffffb
++#define PAD22_DS_SFT 2
++#define PAD22_DS_HI 2
++#define PAD22_DS_SZ 1
++#define PAD22_IE_MSK 0x00000008
++#define PAD22_IE_I_MSK 0xfffffff7
++#define PAD22_IE_SFT 3
++#define PAD22_IE_HI 3
++#define PAD22_IE_SZ 1
++#define PAD22_SEL_I_MSK 0x00000070
++#define PAD22_SEL_I_I_MSK 0xffffff8f
++#define PAD22_SEL_I_SFT 4
++#define PAD22_SEL_I_HI 6
++#define PAD22_SEL_I_SZ 3
++#define PAD22_OD_MSK 0x00000100
++#define PAD22_OD_I_MSK 0xfffffeff
++#define PAD22_OD_SFT 8
++#define PAD22_OD_HI 8
++#define PAD22_OD_SZ 1
++#define PAD22_SEL_O_MSK 0x00007000
++#define PAD22_SEL_O_I_MSK 0xffff8fff
++#define PAD22_SEL_O_SFT 12
++#define PAD22_SEL_O_HI 14
++#define PAD22_SEL_O_SZ 3
++#define PAD22_SEL_OE_MSK 0x00100000
++#define PAD22_SEL_OE_I_MSK 0xffefffff
++#define PAD22_SEL_OE_SFT 20
++#define PAD22_SEL_OE_HI 20
++#define PAD22_SEL_OE_SZ 1
++#define GPIO_TEST_3_ID_MSK 0x10000000
++#define GPIO_TEST_3_ID_I_MSK 0xefffffff
++#define GPIO_TEST_3_ID_SFT 28
++#define GPIO_TEST_3_ID_HI 28
++#define GPIO_TEST_3_ID_SZ 1
++#define PAD24_OE_MSK 0x00000001
++#define PAD24_OE_I_MSK 0xfffffffe
++#define PAD24_OE_SFT 0
++#define PAD24_OE_HI 0
++#define PAD24_OE_SZ 1
++#define PAD24_PE_MSK 0x00000002
++#define PAD24_PE_I_MSK 0xfffffffd
++#define PAD24_PE_SFT 1
++#define PAD24_PE_HI 1
++#define PAD24_PE_SZ 1
++#define PAD24_DS_MSK 0x00000004
++#define PAD24_DS_I_MSK 0xfffffffb
++#define PAD24_DS_SFT 2
++#define PAD24_DS_HI 2
++#define PAD24_DS_SZ 1
++#define PAD24_IE_MSK 0x00000008
++#define PAD24_IE_I_MSK 0xfffffff7
++#define PAD24_IE_SFT 3
++#define PAD24_IE_HI 3
++#define PAD24_IE_SZ 1
++#define PAD24_SEL_I_MSK 0x00000030
++#define PAD24_SEL_I_I_MSK 0xffffffcf
++#define PAD24_SEL_I_SFT 4
++#define PAD24_SEL_I_HI 5
++#define PAD24_SEL_I_SZ 2
++#define PAD24_OD_MSK 0x00000100
++#define PAD24_OD_I_MSK 0xfffffeff
++#define PAD24_OD_SFT 8
++#define PAD24_OD_HI 8
++#define PAD24_OD_SZ 1
++#define PAD24_SEL_O_MSK 0x00007000
++#define PAD24_SEL_O_I_MSK 0xffff8fff
++#define PAD24_SEL_O_SFT 12
++#define PAD24_SEL_O_HI 14
++#define PAD24_SEL_O_SZ 3
++#define GPIO_TEST_4_ID_MSK 0x10000000
++#define GPIO_TEST_4_ID_I_MSK 0xefffffff
++#define GPIO_TEST_4_ID_SFT 28
++#define GPIO_TEST_4_ID_HI 28
++#define GPIO_TEST_4_ID_SZ 1
++#define PAD25_OE_MSK 0x00000001
++#define PAD25_OE_I_MSK 0xfffffffe
++#define PAD25_OE_SFT 0
++#define PAD25_OE_HI 0
++#define PAD25_OE_SZ 1
++#define PAD25_PE_MSK 0x00000002
++#define PAD25_PE_I_MSK 0xfffffffd
++#define PAD25_PE_SFT 1
++#define PAD25_PE_HI 1
++#define PAD25_PE_SZ 1
++#define PAD25_DS_MSK 0x00000004
++#define PAD25_DS_I_MSK 0xfffffffb
++#define PAD25_DS_SFT 2
++#define PAD25_DS_HI 2
++#define PAD25_DS_SZ 1
++#define PAD25_IE_MSK 0x00000008
++#define PAD25_IE_I_MSK 0xfffffff7
++#define PAD25_IE_SFT 3
++#define PAD25_IE_HI 3
++#define PAD25_IE_SZ 1
++#define PAD25_SEL_I_MSK 0x00000070
++#define PAD25_SEL_I_I_MSK 0xffffff8f
++#define PAD25_SEL_I_SFT 4
++#define PAD25_SEL_I_HI 6
++#define PAD25_SEL_I_SZ 3
++#define PAD25_OD_MSK 0x00000100
++#define PAD25_OD_I_MSK 0xfffffeff
++#define PAD25_OD_SFT 8
++#define PAD25_OD_HI 8
++#define PAD25_OD_SZ 1
++#define PAD25_SEL_O_MSK 0x00007000
++#define PAD25_SEL_O_I_MSK 0xffff8fff
++#define PAD25_SEL_O_SFT 12
++#define PAD25_SEL_O_HI 14
++#define PAD25_SEL_O_SZ 3
++#define PAD25_SEL_OE_MSK 0x00100000
++#define PAD25_SEL_OE_I_MSK 0xffefffff
++#define PAD25_SEL_OE_SFT 20
++#define PAD25_SEL_OE_HI 20
++#define PAD25_SEL_OE_SZ 1
++#define STRAP1_MSK 0x08000000
++#define STRAP1_I_MSK 0xf7ffffff
++#define STRAP1_SFT 27
++#define STRAP1_HI 27
++#define STRAP1_SZ 1
++#define GPIO_1_ID_MSK 0x10000000
++#define GPIO_1_ID_I_MSK 0xefffffff
++#define GPIO_1_ID_SFT 28
++#define GPIO_1_ID_HI 28
++#define GPIO_1_ID_SZ 1
++#define PAD27_OE_MSK 0x00000001
++#define PAD27_OE_I_MSK 0xfffffffe
++#define PAD27_OE_SFT 0
++#define PAD27_OE_HI 0
++#define PAD27_OE_SZ 1
++#define PAD27_PE_MSK 0x00000002
++#define PAD27_PE_I_MSK 0xfffffffd
++#define PAD27_PE_SFT 1
++#define PAD27_PE_HI 1
++#define PAD27_PE_SZ 1
++#define PAD27_DS_MSK 0x00000004
++#define PAD27_DS_I_MSK 0xfffffffb
++#define PAD27_DS_SFT 2
++#define PAD27_DS_HI 2
++#define PAD27_DS_SZ 1
++#define PAD27_IE_MSK 0x00000008
++#define PAD27_IE_I_MSK 0xfffffff7
++#define PAD27_IE_SFT 3
++#define PAD27_IE_HI 3
++#define PAD27_IE_SZ 1
++#define PAD27_SEL_I_MSK 0x00000070
++#define PAD27_SEL_I_I_MSK 0xffffff8f
++#define PAD27_SEL_I_SFT 4
++#define PAD27_SEL_I_HI 6
++#define PAD27_SEL_I_SZ 3
++#define PAD27_OD_MSK 0x00000100
++#define PAD27_OD_I_MSK 0xfffffeff
++#define PAD27_OD_SFT 8
++#define PAD27_OD_HI 8
++#define PAD27_OD_SZ 1
++#define PAD27_SEL_O_MSK 0x00007000
++#define PAD27_SEL_O_I_MSK 0xffff8fff
++#define PAD27_SEL_O_SFT 12
++#define PAD27_SEL_O_HI 14
++#define PAD27_SEL_O_SZ 3
++#define GPIO_2_ID_MSK 0x10000000
++#define GPIO_2_ID_I_MSK 0xefffffff
++#define GPIO_2_ID_SFT 28
++#define GPIO_2_ID_HI 28
++#define GPIO_2_ID_SZ 1
++#define PAD28_OE_MSK 0x00000001
++#define PAD28_OE_I_MSK 0xfffffffe
++#define PAD28_OE_SFT 0
++#define PAD28_OE_HI 0
++#define PAD28_OE_SZ 1
++#define PAD28_PE_MSK 0x00000002
++#define PAD28_PE_I_MSK 0xfffffffd
++#define PAD28_PE_SFT 1
++#define PAD28_PE_HI 1
++#define PAD28_PE_SZ 1
++#define PAD28_DS_MSK 0x00000004
++#define PAD28_DS_I_MSK 0xfffffffb
++#define PAD28_DS_SFT 2
++#define PAD28_DS_HI 2
++#define PAD28_DS_SZ 1
++#define PAD28_IE_MSK 0x00000008
++#define PAD28_IE_I_MSK 0xfffffff7
++#define PAD28_IE_SFT 3
++#define PAD28_IE_HI 3
++#define PAD28_IE_SZ 1
++#define PAD28_SEL_I_MSK 0x00000070
++#define PAD28_SEL_I_I_MSK 0xffffff8f
++#define PAD28_SEL_I_SFT 4
++#define PAD28_SEL_I_HI 6
++#define PAD28_SEL_I_SZ 3
++#define PAD28_OD_MSK 0x00000100
++#define PAD28_OD_I_MSK 0xfffffeff
++#define PAD28_OD_SFT 8
++#define PAD28_OD_HI 8
++#define PAD28_OD_SZ 1
++#define PAD28_SEL_O_MSK 0x0000f000
++#define PAD28_SEL_O_I_MSK 0xffff0fff
++#define PAD28_SEL_O_SFT 12
++#define PAD28_SEL_O_HI 15
++#define PAD28_SEL_O_SZ 4
++#define PAD28_SEL_OE_MSK 0x00100000
++#define PAD28_SEL_OE_I_MSK 0xffefffff
++#define PAD28_SEL_OE_SFT 20
++#define PAD28_SEL_OE_HI 20
++#define PAD28_SEL_OE_SZ 1
++#define GPIO_3_ID_MSK 0x10000000
++#define GPIO_3_ID_I_MSK 0xefffffff
++#define GPIO_3_ID_SFT 28
++#define GPIO_3_ID_HI 28
++#define GPIO_3_ID_SZ 1
++#define PAD29_OE_MSK 0x00000001
++#define PAD29_OE_I_MSK 0xfffffffe
++#define PAD29_OE_SFT 0
++#define PAD29_OE_HI 0
++#define PAD29_OE_SZ 1
++#define PAD29_PE_MSK 0x00000002
++#define PAD29_PE_I_MSK 0xfffffffd
++#define PAD29_PE_SFT 1
++#define PAD29_PE_HI 1
++#define PAD29_PE_SZ 1
++#define PAD29_DS_MSK 0x00000004
++#define PAD29_DS_I_MSK 0xfffffffb
++#define PAD29_DS_SFT 2
++#define PAD29_DS_HI 2
++#define PAD29_DS_SZ 1
++#define PAD29_IE_MSK 0x00000008
++#define PAD29_IE_I_MSK 0xfffffff7
++#define PAD29_IE_SFT 3
++#define PAD29_IE_HI 3
++#define PAD29_IE_SZ 1
++#define PAD29_SEL_I_MSK 0x00000070
++#define PAD29_SEL_I_I_MSK 0xffffff8f
++#define PAD29_SEL_I_SFT 4
++#define PAD29_SEL_I_HI 6
++#define PAD29_SEL_I_SZ 3
++#define PAD29_OD_MSK 0x00000100
++#define PAD29_OD_I_MSK 0xfffffeff
++#define PAD29_OD_SFT 8
++#define PAD29_OD_HI 8
++#define PAD29_OD_SZ 1
++#define PAD29_SEL_O_MSK 0x00007000
++#define PAD29_SEL_O_I_MSK 0xffff8fff
++#define PAD29_SEL_O_SFT 12
++#define PAD29_SEL_O_HI 14
++#define PAD29_SEL_O_SZ 3
++#define GPIO_TEST_5_ID_MSK 0x10000000
++#define GPIO_TEST_5_ID_I_MSK 0xefffffff
++#define GPIO_TEST_5_ID_SFT 28
++#define GPIO_TEST_5_ID_HI 28
++#define GPIO_TEST_5_ID_SZ 1
++#define PAD30_OE_MSK 0x00000001
++#define PAD30_OE_I_MSK 0xfffffffe
++#define PAD30_OE_SFT 0
++#define PAD30_OE_HI 0
++#define PAD30_OE_SZ 1
++#define PAD30_PE_MSK 0x00000002
++#define PAD30_PE_I_MSK 0xfffffffd
++#define PAD30_PE_SFT 1
++#define PAD30_PE_HI 1
++#define PAD30_PE_SZ 1
++#define PAD30_DS_MSK 0x00000004
++#define PAD30_DS_I_MSK 0xfffffffb
++#define PAD30_DS_SFT 2
++#define PAD30_DS_HI 2
++#define PAD30_DS_SZ 1
++#define PAD30_IE_MSK 0x00000008
++#define PAD30_IE_I_MSK 0xfffffff7
++#define PAD30_IE_SFT 3
++#define PAD30_IE_HI 3
++#define PAD30_IE_SZ 1
++#define PAD30_SEL_I_MSK 0x00000030
++#define PAD30_SEL_I_I_MSK 0xffffffcf
++#define PAD30_SEL_I_SFT 4
++#define PAD30_SEL_I_HI 5
++#define PAD30_SEL_I_SZ 2
++#define PAD30_OD_MSK 0x00000100
++#define PAD30_OD_I_MSK 0xfffffeff
++#define PAD30_OD_SFT 8
++#define PAD30_OD_HI 8
++#define PAD30_OD_SZ 1
++#define PAD30_SEL_O_MSK 0x00003000
++#define PAD30_SEL_O_I_MSK 0xffffcfff
++#define PAD30_SEL_O_SFT 12
++#define PAD30_SEL_O_HI 13
++#define PAD30_SEL_O_SZ 2
++#define TEST_6_ID_MSK 0x10000000
++#define TEST_6_ID_I_MSK 0xefffffff
++#define TEST_6_ID_SFT 28
++#define TEST_6_ID_HI 28
++#define TEST_6_ID_SZ 1
++#define PAD31_OE_MSK 0x00000001
++#define PAD31_OE_I_MSK 0xfffffffe
++#define PAD31_OE_SFT 0
++#define PAD31_OE_HI 0
++#define PAD31_OE_SZ 1
++#define PAD31_PE_MSK 0x00000002
++#define PAD31_PE_I_MSK 0xfffffffd
++#define PAD31_PE_SFT 1
++#define PAD31_PE_HI 1
++#define PAD31_PE_SZ 1
++#define PAD31_DS_MSK 0x00000004
++#define PAD31_DS_I_MSK 0xfffffffb
++#define PAD31_DS_SFT 2
++#define PAD31_DS_HI 2
++#define PAD31_DS_SZ 1
++#define PAD31_IE_MSK 0x00000008
++#define PAD31_IE_I_MSK 0xfffffff7
++#define PAD31_IE_SFT 3
++#define PAD31_IE_HI 3
++#define PAD31_IE_SZ 1
++#define PAD31_SEL_I_MSK 0x00000030
++#define PAD31_SEL_I_I_MSK 0xffffffcf
++#define PAD31_SEL_I_SFT 4
++#define PAD31_SEL_I_HI 5
++#define PAD31_SEL_I_SZ 2
++#define PAD31_OD_MSK 0x00000100
++#define PAD31_OD_I_MSK 0xfffffeff
++#define PAD31_OD_SFT 8
++#define PAD31_OD_HI 8
++#define PAD31_OD_SZ 1
++#define PAD31_SEL_O_MSK 0x00003000
++#define PAD31_SEL_O_I_MSK 0xffffcfff
++#define PAD31_SEL_O_SFT 12
++#define PAD31_SEL_O_HI 13
++#define PAD31_SEL_O_SZ 2
++#define TEST_7_ID_MSK 0x10000000
++#define TEST_7_ID_I_MSK 0xefffffff
++#define TEST_7_ID_SFT 28
++#define TEST_7_ID_HI 28
++#define TEST_7_ID_SZ 1
++#define PAD32_OE_MSK 0x00000001
++#define PAD32_OE_I_MSK 0xfffffffe
++#define PAD32_OE_SFT 0
++#define PAD32_OE_HI 0
++#define PAD32_OE_SZ 1
++#define PAD32_PE_MSK 0x00000002
++#define PAD32_PE_I_MSK 0xfffffffd
++#define PAD32_PE_SFT 1
++#define PAD32_PE_HI 1
++#define PAD32_PE_SZ 1
++#define PAD32_DS_MSK 0x00000004
++#define PAD32_DS_I_MSK 0xfffffffb
++#define PAD32_DS_SFT 2
++#define PAD32_DS_HI 2
++#define PAD32_DS_SZ 1
++#define PAD32_IE_MSK 0x00000008
++#define PAD32_IE_I_MSK 0xfffffff7
++#define PAD32_IE_SFT 3
++#define PAD32_IE_HI 3
++#define PAD32_IE_SZ 1
++#define PAD32_SEL_I_MSK 0x00000030
++#define PAD32_SEL_I_I_MSK 0xffffffcf
++#define PAD32_SEL_I_SFT 4
++#define PAD32_SEL_I_HI 5
++#define PAD32_SEL_I_SZ 2
++#define PAD32_OD_MSK 0x00000100
++#define PAD32_OD_I_MSK 0xfffffeff
++#define PAD32_OD_SFT 8
++#define PAD32_OD_HI 8
++#define PAD32_OD_SZ 1
++#define PAD32_SEL_O_MSK 0x00003000
++#define PAD32_SEL_O_I_MSK 0xffffcfff
++#define PAD32_SEL_O_SFT 12
++#define PAD32_SEL_O_HI 13
++#define PAD32_SEL_O_SZ 2
++#define TEST_8_ID_MSK 0x10000000
++#define TEST_8_ID_I_MSK 0xefffffff
++#define TEST_8_ID_SFT 28
++#define TEST_8_ID_HI 28
++#define TEST_8_ID_SZ 1
++#define PAD33_OE_MSK 0x00000001
++#define PAD33_OE_I_MSK 0xfffffffe
++#define PAD33_OE_SFT 0
++#define PAD33_OE_HI 0
++#define PAD33_OE_SZ 1
++#define PAD33_PE_MSK 0x00000002
++#define PAD33_PE_I_MSK 0xfffffffd
++#define PAD33_PE_SFT 1
++#define PAD33_PE_HI 1
++#define PAD33_PE_SZ 1
++#define PAD33_DS_MSK 0x00000004
++#define PAD33_DS_I_MSK 0xfffffffb
++#define PAD33_DS_SFT 2
++#define PAD33_DS_HI 2
++#define PAD33_DS_SZ 1
++#define PAD33_IE_MSK 0x00000008
++#define PAD33_IE_I_MSK 0xfffffff7
++#define PAD33_IE_SFT 3
++#define PAD33_IE_HI 3
++#define PAD33_IE_SZ 1
++#define PAD33_SEL_I_MSK 0x00000030
++#define PAD33_SEL_I_I_MSK 0xffffffcf
++#define PAD33_SEL_I_SFT 4
++#define PAD33_SEL_I_HI 5
++#define PAD33_SEL_I_SZ 2
++#define PAD33_OD_MSK 0x00000100
++#define PAD33_OD_I_MSK 0xfffffeff
++#define PAD33_OD_SFT 8
++#define PAD33_OD_HI 8
++#define PAD33_OD_SZ 1
++#define PAD33_SEL_O_MSK 0x00003000
++#define PAD33_SEL_O_I_MSK 0xffffcfff
++#define PAD33_SEL_O_SFT 12
++#define PAD33_SEL_O_HI 13
++#define PAD33_SEL_O_SZ 2
++#define TEST_9_ID_MSK 0x10000000
++#define TEST_9_ID_I_MSK 0xefffffff
++#define TEST_9_ID_SFT 28
++#define TEST_9_ID_HI 28
++#define TEST_9_ID_SZ 1
++#define PAD34_OE_MSK 0x00000001
++#define PAD34_OE_I_MSK 0xfffffffe
++#define PAD34_OE_SFT 0
++#define PAD34_OE_HI 0
++#define PAD34_OE_SZ 1
++#define PAD34_PE_MSK 0x00000002
++#define PAD34_PE_I_MSK 0xfffffffd
++#define PAD34_PE_SFT 1
++#define PAD34_PE_HI 1
++#define PAD34_PE_SZ 1
++#define PAD34_DS_MSK 0x00000004
++#define PAD34_DS_I_MSK 0xfffffffb
++#define PAD34_DS_SFT 2
++#define PAD34_DS_HI 2
++#define PAD34_DS_SZ 1
++#define PAD34_IE_MSK 0x00000008
++#define PAD34_IE_I_MSK 0xfffffff7
++#define PAD34_IE_SFT 3
++#define PAD34_IE_HI 3
++#define PAD34_IE_SZ 1
++#define PAD34_SEL_I_MSK 0x00000030
++#define PAD34_SEL_I_I_MSK 0xffffffcf
++#define PAD34_SEL_I_SFT 4
++#define PAD34_SEL_I_HI 5
++#define PAD34_SEL_I_SZ 2
++#define PAD34_OD_MSK 0x00000100
++#define PAD34_OD_I_MSK 0xfffffeff
++#define PAD34_OD_SFT 8
++#define PAD34_OD_HI 8
++#define PAD34_OD_SZ 1
++#define PAD34_SEL_O_MSK 0x00003000
++#define PAD34_SEL_O_I_MSK 0xffffcfff
++#define PAD34_SEL_O_SFT 12
++#define PAD34_SEL_O_HI 13
++#define PAD34_SEL_O_SZ 2
++#define TEST_10_ID_MSK 0x10000000
++#define TEST_10_ID_I_MSK 0xefffffff
++#define TEST_10_ID_SFT 28
++#define TEST_10_ID_HI 28
++#define TEST_10_ID_SZ 1
++#define PAD42_OE_MSK 0x00000001
++#define PAD42_OE_I_MSK 0xfffffffe
++#define PAD42_OE_SFT 0
++#define PAD42_OE_HI 0
++#define PAD42_OE_SZ 1
++#define PAD42_PE_MSK 0x00000002
++#define PAD42_PE_I_MSK 0xfffffffd
++#define PAD42_PE_SFT 1
++#define PAD42_PE_HI 1
++#define PAD42_PE_SZ 1
++#define PAD42_DS_MSK 0x00000004
++#define PAD42_DS_I_MSK 0xfffffffb
++#define PAD42_DS_SFT 2
++#define PAD42_DS_HI 2
++#define PAD42_DS_SZ 1
++#define PAD42_IE_MSK 0x00000008
++#define PAD42_IE_I_MSK 0xfffffff7
++#define PAD42_IE_SFT 3
++#define PAD42_IE_HI 3
++#define PAD42_IE_SZ 1
++#define PAD42_SEL_I_MSK 0x00000030
++#define PAD42_SEL_I_I_MSK 0xffffffcf
++#define PAD42_SEL_I_SFT 4
++#define PAD42_SEL_I_HI 5
++#define PAD42_SEL_I_SZ 2
++#define PAD42_OD_MSK 0x00000100
++#define PAD42_OD_I_MSK 0xfffffeff
++#define PAD42_OD_SFT 8
++#define PAD42_OD_HI 8
++#define PAD42_OD_SZ 1
++#define PAD42_SEL_O_MSK 0x00001000
++#define PAD42_SEL_O_I_MSK 0xffffefff
++#define PAD42_SEL_O_SFT 12
++#define PAD42_SEL_O_HI 12
++#define PAD42_SEL_O_SZ 1
++#define TEST_11_ID_MSK 0x10000000
++#define TEST_11_ID_I_MSK 0xefffffff
++#define TEST_11_ID_SFT 28
++#define TEST_11_ID_HI 28
++#define TEST_11_ID_SZ 1
++#define PAD43_OE_MSK 0x00000001
++#define PAD43_OE_I_MSK 0xfffffffe
++#define PAD43_OE_SFT 0
++#define PAD43_OE_HI 0
++#define PAD43_OE_SZ 1
++#define PAD43_PE_MSK 0x00000002
++#define PAD43_PE_I_MSK 0xfffffffd
++#define PAD43_PE_SFT 1
++#define PAD43_PE_HI 1
++#define PAD43_PE_SZ 1
++#define PAD43_DS_MSK 0x00000004
++#define PAD43_DS_I_MSK 0xfffffffb
++#define PAD43_DS_SFT 2
++#define PAD43_DS_HI 2
++#define PAD43_DS_SZ 1
++#define PAD43_IE_MSK 0x00000008
++#define PAD43_IE_I_MSK 0xfffffff7
++#define PAD43_IE_SFT 3
++#define PAD43_IE_HI 3
++#define PAD43_IE_SZ 1
++#define PAD43_SEL_I_MSK 0x00000030
++#define PAD43_SEL_I_I_MSK 0xffffffcf
++#define PAD43_SEL_I_SFT 4
++#define PAD43_SEL_I_HI 5
++#define PAD43_SEL_I_SZ 2
++#define PAD43_OD_MSK 0x00000100
++#define PAD43_OD_I_MSK 0xfffffeff
++#define PAD43_OD_SFT 8
++#define PAD43_OD_HI 8
++#define PAD43_OD_SZ 1
++#define PAD43_SEL_O_MSK 0x00001000
++#define PAD43_SEL_O_I_MSK 0xffffefff
++#define PAD43_SEL_O_SFT 12
++#define PAD43_SEL_O_HI 12
++#define PAD43_SEL_O_SZ 1
++#define TEST_12_ID_MSK 0x10000000
++#define TEST_12_ID_I_MSK 0xefffffff
++#define TEST_12_ID_SFT 28
++#define TEST_12_ID_HI 28
++#define TEST_12_ID_SZ 1
++#define PAD44_OE_MSK 0x00000001
++#define PAD44_OE_I_MSK 0xfffffffe
++#define PAD44_OE_SFT 0
++#define PAD44_OE_HI 0
++#define PAD44_OE_SZ 1
++#define PAD44_PE_MSK 0x00000002
++#define PAD44_PE_I_MSK 0xfffffffd
++#define PAD44_PE_SFT 1
++#define PAD44_PE_HI 1
++#define PAD44_PE_SZ 1
++#define PAD44_DS_MSK 0x00000004
++#define PAD44_DS_I_MSK 0xfffffffb
++#define PAD44_DS_SFT 2
++#define PAD44_DS_HI 2
++#define PAD44_DS_SZ 1
++#define PAD44_IE_MSK 0x00000008
++#define PAD44_IE_I_MSK 0xfffffff7
++#define PAD44_IE_SFT 3
++#define PAD44_IE_HI 3
++#define PAD44_IE_SZ 1
++#define PAD44_SEL_I_MSK 0x00000030
++#define PAD44_SEL_I_I_MSK 0xffffffcf
++#define PAD44_SEL_I_SFT 4
++#define PAD44_SEL_I_HI 5
++#define PAD44_SEL_I_SZ 2
++#define PAD44_OD_MSK 0x00000100
++#define PAD44_OD_I_MSK 0xfffffeff
++#define PAD44_OD_SFT 8
++#define PAD44_OD_HI 8
++#define PAD44_OD_SZ 1
++#define PAD44_SEL_O_MSK 0x00003000
++#define PAD44_SEL_O_I_MSK 0xffffcfff
++#define PAD44_SEL_O_SFT 12
++#define PAD44_SEL_O_HI 13
++#define PAD44_SEL_O_SZ 2
++#define TEST_13_ID_MSK 0x10000000
++#define TEST_13_ID_I_MSK 0xefffffff
++#define TEST_13_ID_SFT 28
++#define TEST_13_ID_HI 28
++#define TEST_13_ID_SZ 1
++#define PAD45_OE_MSK 0x00000001
++#define PAD45_OE_I_MSK 0xfffffffe
++#define PAD45_OE_SFT 0
++#define PAD45_OE_HI 0
++#define PAD45_OE_SZ 1
++#define PAD45_PE_MSK 0x00000002
++#define PAD45_PE_I_MSK 0xfffffffd
++#define PAD45_PE_SFT 1
++#define PAD45_PE_HI 1
++#define PAD45_PE_SZ 1
++#define PAD45_DS_MSK 0x00000004
++#define PAD45_DS_I_MSK 0xfffffffb
++#define PAD45_DS_SFT 2
++#define PAD45_DS_HI 2
++#define PAD45_DS_SZ 1
++#define PAD45_IE_MSK 0x00000008
++#define PAD45_IE_I_MSK 0xfffffff7
++#define PAD45_IE_SFT 3
++#define PAD45_IE_HI 3
++#define PAD45_IE_SZ 1
++#define PAD45_SEL_I_MSK 0x00000030
++#define PAD45_SEL_I_I_MSK 0xffffffcf
++#define PAD45_SEL_I_SFT 4
++#define PAD45_SEL_I_HI 5
++#define PAD45_SEL_I_SZ 2
++#define PAD45_OD_MSK 0x00000100
++#define PAD45_OD_I_MSK 0xfffffeff
++#define PAD45_OD_SFT 8
++#define PAD45_OD_HI 8
++#define PAD45_OD_SZ 1
++#define PAD45_SEL_O_MSK 0x00003000
++#define PAD45_SEL_O_I_MSK 0xffffcfff
++#define PAD45_SEL_O_SFT 12
++#define PAD45_SEL_O_HI 13
++#define PAD45_SEL_O_SZ 2
++#define TEST_14_ID_MSK 0x10000000
++#define TEST_14_ID_I_MSK 0xefffffff
++#define TEST_14_ID_SFT 28
++#define TEST_14_ID_HI 28
++#define TEST_14_ID_SZ 1
++#define PAD46_OE_MSK 0x00000001
++#define PAD46_OE_I_MSK 0xfffffffe
++#define PAD46_OE_SFT 0
++#define PAD46_OE_HI 0
++#define PAD46_OE_SZ 1
++#define PAD46_PE_MSK 0x00000002
++#define PAD46_PE_I_MSK 0xfffffffd
++#define PAD46_PE_SFT 1
++#define PAD46_PE_HI 1
++#define PAD46_PE_SZ 1
++#define PAD46_DS_MSK 0x00000004
++#define PAD46_DS_I_MSK 0xfffffffb
++#define PAD46_DS_SFT 2
++#define PAD46_DS_HI 2
++#define PAD46_DS_SZ 1
++#define PAD46_IE_MSK 0x00000008
++#define PAD46_IE_I_MSK 0xfffffff7
++#define PAD46_IE_SFT 3
++#define PAD46_IE_HI 3
++#define PAD46_IE_SZ 1
++#define PAD46_SEL_I_MSK 0x00000030
++#define PAD46_SEL_I_I_MSK 0xffffffcf
++#define PAD46_SEL_I_SFT 4
++#define PAD46_SEL_I_HI 5
++#define PAD46_SEL_I_SZ 2
++#define PAD46_OD_MSK 0x00000100
++#define PAD46_OD_I_MSK 0xfffffeff
++#define PAD46_OD_SFT 8
++#define PAD46_OD_HI 8
++#define PAD46_OD_SZ 1
++#define PAD46_SEL_O_MSK 0x00003000
++#define PAD46_SEL_O_I_MSK 0xffffcfff
++#define PAD46_SEL_O_SFT 12
++#define PAD46_SEL_O_HI 13
++#define PAD46_SEL_O_SZ 2
++#define TEST_15_ID_MSK 0x10000000
++#define TEST_15_ID_I_MSK 0xefffffff
++#define TEST_15_ID_SFT 28
++#define TEST_15_ID_HI 28
++#define TEST_15_ID_SZ 1
++#define PAD47_OE_MSK 0x00000001
++#define PAD47_OE_I_MSK 0xfffffffe
++#define PAD47_OE_SFT 0
++#define PAD47_OE_HI 0
++#define PAD47_OE_SZ 1
++#define PAD47_PE_MSK 0x00000002
++#define PAD47_PE_I_MSK 0xfffffffd
++#define PAD47_PE_SFT 1
++#define PAD47_PE_HI 1
++#define PAD47_PE_SZ 1
++#define PAD47_DS_MSK 0x00000004
++#define PAD47_DS_I_MSK 0xfffffffb
++#define PAD47_DS_SFT 2
++#define PAD47_DS_HI 2
++#define PAD47_DS_SZ 1
++#define PAD47_SEL_I_MSK 0x00000030
++#define PAD47_SEL_I_I_MSK 0xffffffcf
++#define PAD47_SEL_I_SFT 4
++#define PAD47_SEL_I_HI 5
++#define PAD47_SEL_I_SZ 2
++#define PAD47_OD_MSK 0x00000100
++#define PAD47_OD_I_MSK 0xfffffeff
++#define PAD47_OD_SFT 8
++#define PAD47_OD_HI 8
++#define PAD47_OD_SZ 1
++#define PAD47_SEL_O_MSK 0x00003000
++#define PAD47_SEL_O_I_MSK 0xffffcfff
++#define PAD47_SEL_O_SFT 12
++#define PAD47_SEL_O_HI 13
++#define PAD47_SEL_O_SZ 2
++#define PAD47_SEL_OE_MSK 0x00100000
++#define PAD47_SEL_OE_I_MSK 0xffefffff
++#define PAD47_SEL_OE_SFT 20
++#define PAD47_SEL_OE_HI 20
++#define PAD47_SEL_OE_SZ 1
++#define GPIO_9_ID_MSK 0x10000000
++#define GPIO_9_ID_I_MSK 0xefffffff
++#define GPIO_9_ID_SFT 28
++#define GPIO_9_ID_HI 28
++#define GPIO_9_ID_SZ 1
++#define PAD48_OE_MSK 0x00000001
++#define PAD48_OE_I_MSK 0xfffffffe
++#define PAD48_OE_SFT 0
++#define PAD48_OE_HI 0
++#define PAD48_OE_SZ 1
++#define PAD48_PE_MSK 0x00000002
++#define PAD48_PE_I_MSK 0xfffffffd
++#define PAD48_PE_SFT 1
++#define PAD48_PE_HI 1
++#define PAD48_PE_SZ 1
++#define PAD48_DS_MSK 0x00000004
++#define PAD48_DS_I_MSK 0xfffffffb
++#define PAD48_DS_SFT 2
++#define PAD48_DS_HI 2
++#define PAD48_DS_SZ 1
++#define PAD48_IE_MSK 0x00000008
++#define PAD48_IE_I_MSK 0xfffffff7
++#define PAD48_IE_SFT 3
++#define PAD48_IE_HI 3
++#define PAD48_IE_SZ 1
++#define PAD48_SEL_I_MSK 0x00000070
++#define PAD48_SEL_I_I_MSK 0xffffff8f
++#define PAD48_SEL_I_SFT 4
++#define PAD48_SEL_I_HI 6
++#define PAD48_SEL_I_SZ 3
++#define PAD48_OD_MSK 0x00000100
++#define PAD48_OD_I_MSK 0xfffffeff
++#define PAD48_OD_SFT 8
++#define PAD48_OD_HI 8
++#define PAD48_OD_SZ 1
++#define PAD48_PE_SEL_MSK 0x00000800
++#define PAD48_PE_SEL_I_MSK 0xfffff7ff
++#define PAD48_PE_SEL_SFT 11
++#define PAD48_PE_SEL_HI 11
++#define PAD48_PE_SEL_SZ 1
++#define PAD48_SEL_O_MSK 0x00003000
++#define PAD48_SEL_O_I_MSK 0xffffcfff
++#define PAD48_SEL_O_SFT 12
++#define PAD48_SEL_O_HI 13
++#define PAD48_SEL_O_SZ 2
++#define PAD48_SEL_OE_MSK 0x00100000
++#define PAD48_SEL_OE_I_MSK 0xffefffff
++#define PAD48_SEL_OE_SFT 20
++#define PAD48_SEL_OE_HI 20
++#define PAD48_SEL_OE_SZ 1
++#define GPIO_10_ID_MSK 0x10000000
++#define GPIO_10_ID_I_MSK 0xefffffff
++#define GPIO_10_ID_SFT 28
++#define GPIO_10_ID_HI 28
++#define GPIO_10_ID_SZ 1
++#define PAD49_OE_MSK 0x00000001
++#define PAD49_OE_I_MSK 0xfffffffe
++#define PAD49_OE_SFT 0
++#define PAD49_OE_HI 0
++#define PAD49_OE_SZ 1
++#define PAD49_PE_MSK 0x00000002
++#define PAD49_PE_I_MSK 0xfffffffd
++#define PAD49_PE_SFT 1
++#define PAD49_PE_HI 1
++#define PAD49_PE_SZ 1
++#define PAD49_DS_MSK 0x00000004
++#define PAD49_DS_I_MSK 0xfffffffb
++#define PAD49_DS_SFT 2
++#define PAD49_DS_HI 2
++#define PAD49_DS_SZ 1
++#define PAD49_IE_MSK 0x00000008
++#define PAD49_IE_I_MSK 0xfffffff7
++#define PAD49_IE_SFT 3
++#define PAD49_IE_HI 3
++#define PAD49_IE_SZ 1
++#define PAD49_SEL_I_MSK 0x00000070
++#define PAD49_SEL_I_I_MSK 0xffffff8f
++#define PAD49_SEL_I_SFT 4
++#define PAD49_SEL_I_HI 6
++#define PAD49_SEL_I_SZ 3
++#define PAD49_OD_MSK 0x00000100
++#define PAD49_OD_I_MSK 0xfffffeff
++#define PAD49_OD_SFT 8
++#define PAD49_OD_HI 8
++#define PAD49_OD_SZ 1
++#define PAD49_SEL_O_MSK 0x00003000
++#define PAD49_SEL_O_I_MSK 0xffffcfff
++#define PAD49_SEL_O_SFT 12
++#define PAD49_SEL_O_HI 13
++#define PAD49_SEL_O_SZ 2
++#define PAD49_SEL_OE_MSK 0x00100000
++#define PAD49_SEL_OE_I_MSK 0xffefffff
++#define PAD49_SEL_OE_SFT 20
++#define PAD49_SEL_OE_HI 20
++#define PAD49_SEL_OE_SZ 1
++#define GPIO_11_ID_MSK 0x10000000
++#define GPIO_11_ID_I_MSK 0xefffffff
++#define GPIO_11_ID_SFT 28
++#define GPIO_11_ID_HI 28
++#define GPIO_11_ID_SZ 1
++#define PAD50_OE_MSK 0x00000001
++#define PAD50_OE_I_MSK 0xfffffffe
++#define PAD50_OE_SFT 0
++#define PAD50_OE_HI 0
++#define PAD50_OE_SZ 1
++#define PAD50_PE_MSK 0x00000002
++#define PAD50_PE_I_MSK 0xfffffffd
++#define PAD50_PE_SFT 1
++#define PAD50_PE_HI 1
++#define PAD50_PE_SZ 1
++#define PAD50_DS_MSK 0x00000004
++#define PAD50_DS_I_MSK 0xfffffffb
++#define PAD50_DS_SFT 2
++#define PAD50_DS_HI 2
++#define PAD50_DS_SZ 1
++#define PAD50_IE_MSK 0x00000008
++#define PAD50_IE_I_MSK 0xfffffff7
++#define PAD50_IE_SFT 3
++#define PAD50_IE_HI 3
++#define PAD50_IE_SZ 1
++#define PAD50_SEL_I_MSK 0x00000070
++#define PAD50_SEL_I_I_MSK 0xffffff8f
++#define PAD50_SEL_I_SFT 4
++#define PAD50_SEL_I_HI 6
++#define PAD50_SEL_I_SZ 3
++#define PAD50_OD_MSK 0x00000100
++#define PAD50_OD_I_MSK 0xfffffeff
++#define PAD50_OD_SFT 8
++#define PAD50_OD_HI 8
++#define PAD50_OD_SZ 1
++#define PAD50_SEL_O_MSK 0x00003000
++#define PAD50_SEL_O_I_MSK 0xffffcfff
++#define PAD50_SEL_O_SFT 12
++#define PAD50_SEL_O_HI 13
++#define PAD50_SEL_O_SZ 2
++#define PAD50_SEL_OE_MSK 0x00100000
++#define PAD50_SEL_OE_I_MSK 0xffefffff
++#define PAD50_SEL_OE_SFT 20
++#define PAD50_SEL_OE_HI 20
++#define PAD50_SEL_OE_SZ 1
++#define GPIO_12_ID_MSK 0x10000000
++#define GPIO_12_ID_I_MSK 0xefffffff
++#define GPIO_12_ID_SFT 28
++#define GPIO_12_ID_HI 28
++#define GPIO_12_ID_SZ 1
++#define PAD51_OE_MSK 0x00000001
++#define PAD51_OE_I_MSK 0xfffffffe
++#define PAD51_OE_SFT 0
++#define PAD51_OE_HI 0
++#define PAD51_OE_SZ 1
++#define PAD51_PE_MSK 0x00000002
++#define PAD51_PE_I_MSK 0xfffffffd
++#define PAD51_PE_SFT 1
++#define PAD51_PE_HI 1
++#define PAD51_PE_SZ 1
++#define PAD51_DS_MSK 0x00000004
++#define PAD51_DS_I_MSK 0xfffffffb
++#define PAD51_DS_SFT 2
++#define PAD51_DS_HI 2
++#define PAD51_DS_SZ 1
++#define PAD51_IE_MSK 0x00000008
++#define PAD51_IE_I_MSK 0xfffffff7
++#define PAD51_IE_SFT 3
++#define PAD51_IE_HI 3
++#define PAD51_IE_SZ 1
++#define PAD51_SEL_I_MSK 0x00000030
++#define PAD51_SEL_I_I_MSK 0xffffffcf
++#define PAD51_SEL_I_SFT 4
++#define PAD51_SEL_I_HI 5
++#define PAD51_SEL_I_SZ 2
++#define PAD51_OD_MSK 0x00000100
++#define PAD51_OD_I_MSK 0xfffffeff
++#define PAD51_OD_SFT 8
++#define PAD51_OD_HI 8
++#define PAD51_OD_SZ 1
++#define PAD51_SEL_O_MSK 0x00001000
++#define PAD51_SEL_O_I_MSK 0xffffefff
++#define PAD51_SEL_O_SFT 12
++#define PAD51_SEL_O_HI 12
++#define PAD51_SEL_O_SZ 1
++#define PAD51_SEL_OE_MSK 0x00100000
++#define PAD51_SEL_OE_I_MSK 0xffefffff
++#define PAD51_SEL_OE_SFT 20
++#define PAD51_SEL_OE_HI 20
++#define PAD51_SEL_OE_SZ 1
++#define GPIO_13_ID_MSK 0x10000000
++#define GPIO_13_ID_I_MSK 0xefffffff
++#define GPIO_13_ID_SFT 28
++#define GPIO_13_ID_HI 28
++#define GPIO_13_ID_SZ 1
++#define PAD52_OE_MSK 0x00000001
++#define PAD52_OE_I_MSK 0xfffffffe
++#define PAD52_OE_SFT 0
++#define PAD52_OE_HI 0
++#define PAD52_OE_SZ 1
++#define PAD52_PE_MSK 0x00000002
++#define PAD52_PE_I_MSK 0xfffffffd
++#define PAD52_PE_SFT 1
++#define PAD52_PE_HI 1
++#define PAD52_PE_SZ 1
++#define PAD52_DS_MSK 0x00000004
++#define PAD52_DS_I_MSK 0xfffffffb
++#define PAD52_DS_SFT 2
++#define PAD52_DS_HI 2
++#define PAD52_DS_SZ 1
++#define PAD52_SEL_I_MSK 0x00000030
++#define PAD52_SEL_I_I_MSK 0xffffffcf
++#define PAD52_SEL_I_SFT 4
++#define PAD52_SEL_I_HI 5
++#define PAD52_SEL_I_SZ 2
++#define PAD52_OD_MSK 0x00000100
++#define PAD52_OD_I_MSK 0xfffffeff
++#define PAD52_OD_SFT 8
++#define PAD52_OD_HI 8
++#define PAD52_OD_SZ 1
++#define PAD52_SEL_O_MSK 0x00001000
++#define PAD52_SEL_O_I_MSK 0xffffefff
++#define PAD52_SEL_O_SFT 12
++#define PAD52_SEL_O_HI 12
++#define PAD52_SEL_O_SZ 1
++#define PAD52_SEL_OE_MSK 0x00100000
++#define PAD52_SEL_OE_I_MSK 0xffefffff
++#define PAD52_SEL_OE_SFT 20
++#define PAD52_SEL_OE_HI 20
++#define PAD52_SEL_OE_SZ 1
++#define GPIO_14_ID_MSK 0x10000000
++#define GPIO_14_ID_I_MSK 0xefffffff
++#define GPIO_14_ID_SFT 28
++#define GPIO_14_ID_HI 28
++#define GPIO_14_ID_SZ 1
++#define PAD53_OE_MSK 0x00000001
++#define PAD53_OE_I_MSK 0xfffffffe
++#define PAD53_OE_SFT 0
++#define PAD53_OE_HI 0
++#define PAD53_OE_SZ 1
++#define PAD53_PE_MSK 0x00000002
++#define PAD53_PE_I_MSK 0xfffffffd
++#define PAD53_PE_SFT 1
++#define PAD53_PE_HI 1
++#define PAD53_PE_SZ 1
++#define PAD53_DS_MSK 0x00000004
++#define PAD53_DS_I_MSK 0xfffffffb
++#define PAD53_DS_SFT 2
++#define PAD53_DS_HI 2
++#define PAD53_DS_SZ 1
++#define PAD53_IE_MSK 0x00000008
++#define PAD53_IE_I_MSK 0xfffffff7
++#define PAD53_IE_SFT 3
++#define PAD53_IE_HI 3
++#define PAD53_IE_SZ 1
++#define PAD53_SEL_I_MSK 0x00000030
++#define PAD53_SEL_I_I_MSK 0xffffffcf
++#define PAD53_SEL_I_SFT 4
++#define PAD53_SEL_I_HI 5
++#define PAD53_SEL_I_SZ 2
++#define PAD53_OD_MSK 0x00000100
++#define PAD53_OD_I_MSK 0xfffffeff
++#define PAD53_OD_SFT 8
++#define PAD53_OD_HI 8
++#define PAD53_OD_SZ 1
++#define PAD53_SEL_O_MSK 0x00001000
++#define PAD53_SEL_O_I_MSK 0xffffefff
++#define PAD53_SEL_O_SFT 12
++#define PAD53_SEL_O_HI 12
++#define PAD53_SEL_O_SZ 1
++#define JTAG_TMS_ID_MSK 0x10000000
++#define JTAG_TMS_ID_I_MSK 0xefffffff
++#define JTAG_TMS_ID_SFT 28
++#define JTAG_TMS_ID_HI 28
++#define JTAG_TMS_ID_SZ 1
++#define PAD54_OE_MSK 0x00000001
++#define PAD54_OE_I_MSK 0xfffffffe
++#define PAD54_OE_SFT 0
++#define PAD54_OE_HI 0
++#define PAD54_OE_SZ 1
++#define PAD54_PE_MSK 0x00000002
++#define PAD54_PE_I_MSK 0xfffffffd
++#define PAD54_PE_SFT 1
++#define PAD54_PE_HI 1
++#define PAD54_PE_SZ 1
++#define PAD54_DS_MSK 0x00000004
++#define PAD54_DS_I_MSK 0xfffffffb
++#define PAD54_DS_SFT 2
++#define PAD54_DS_HI 2
++#define PAD54_DS_SZ 1
++#define PAD54_OD_MSK 0x00000100
++#define PAD54_OD_I_MSK 0xfffffeff
++#define PAD54_OD_SFT 8
++#define PAD54_OD_HI 8
++#define PAD54_OD_SZ 1
++#define PAD54_SEL_O_MSK 0x00003000
++#define PAD54_SEL_O_I_MSK 0xffffcfff
++#define PAD54_SEL_O_SFT 12
++#define PAD54_SEL_O_HI 13
++#define PAD54_SEL_O_SZ 2
++#define JTAG_TCK_ID_MSK 0x10000000
++#define JTAG_TCK_ID_I_MSK 0xefffffff
++#define JTAG_TCK_ID_SFT 28
++#define JTAG_TCK_ID_HI 28
++#define JTAG_TCK_ID_SZ 1
++#define PAD56_PE_MSK 0x00000002
++#define PAD56_PE_I_MSK 0xfffffffd
++#define PAD56_PE_SFT 1
++#define PAD56_PE_HI 1
++#define PAD56_PE_SZ 1
++#define PAD56_DS_MSK 0x00000004
++#define PAD56_DS_I_MSK 0xfffffffb
++#define PAD56_DS_SFT 2
++#define PAD56_DS_HI 2
++#define PAD56_DS_SZ 1
++#define PAD56_SEL_I_MSK 0x00000010
++#define PAD56_SEL_I_I_MSK 0xffffffef
++#define PAD56_SEL_I_SFT 4
++#define PAD56_SEL_I_HI 4
++#define PAD56_SEL_I_SZ 1
++#define PAD56_OD_MSK 0x00000100
++#define PAD56_OD_I_MSK 0xfffffeff
++#define PAD56_OD_SFT 8
++#define PAD56_OD_HI 8
++#define PAD56_OD_SZ 1
++#define JTAG_TDI_ID_MSK 0x10000000
++#define JTAG_TDI_ID_I_MSK 0xefffffff
++#define JTAG_TDI_ID_SFT 28
++#define JTAG_TDI_ID_HI 28
++#define JTAG_TDI_ID_SZ 1
++#define PAD57_OE_MSK 0x00000001
++#define PAD57_OE_I_MSK 0xfffffffe
++#define PAD57_OE_SFT 0
++#define PAD57_OE_HI 0
++#define PAD57_OE_SZ 1
++#define PAD57_PE_MSK 0x00000002
++#define PAD57_PE_I_MSK 0xfffffffd
++#define PAD57_PE_SFT 1
++#define PAD57_PE_HI 1
++#define PAD57_PE_SZ 1
++#define PAD57_DS_MSK 0x00000004
++#define PAD57_DS_I_MSK 0xfffffffb
++#define PAD57_DS_SFT 2
++#define PAD57_DS_HI 2
++#define PAD57_DS_SZ 1
++#define PAD57_IE_MSK 0x00000008
++#define PAD57_IE_I_MSK 0xfffffff7
++#define PAD57_IE_SFT 3
++#define PAD57_IE_HI 3
++#define PAD57_IE_SZ 1
++#define PAD57_SEL_I_MSK 0x00000030
++#define PAD57_SEL_I_I_MSK 0xffffffcf
++#define PAD57_SEL_I_SFT 4
++#define PAD57_SEL_I_HI 5
++#define PAD57_SEL_I_SZ 2
++#define PAD57_OD_MSK 0x00000100
++#define PAD57_OD_I_MSK 0xfffffeff
++#define PAD57_OD_SFT 8
++#define PAD57_OD_HI 8
++#define PAD57_OD_SZ 1
++#define PAD57_SEL_O_MSK 0x00003000
++#define PAD57_SEL_O_I_MSK 0xffffcfff
++#define PAD57_SEL_O_SFT 12
++#define PAD57_SEL_O_HI 13
++#define PAD57_SEL_O_SZ 2
++#define PAD57_SEL_OE_MSK 0x00100000
++#define PAD57_SEL_OE_I_MSK 0xffefffff
++#define PAD57_SEL_OE_SFT 20
++#define PAD57_SEL_OE_HI 20
++#define PAD57_SEL_OE_SZ 1
++#define JTAG_TDO_ID_MSK 0x10000000
++#define JTAG_TDO_ID_I_MSK 0xefffffff
++#define JTAG_TDO_ID_SFT 28
++#define JTAG_TDO_ID_HI 28
++#define JTAG_TDO_ID_SZ 1
++#define PAD58_OE_MSK 0x00000001
++#define PAD58_OE_I_MSK 0xfffffffe
++#define PAD58_OE_SFT 0
++#define PAD58_OE_HI 0
++#define PAD58_OE_SZ 1
++#define PAD58_PE_MSK 0x00000002
++#define PAD58_PE_I_MSK 0xfffffffd
++#define PAD58_PE_SFT 1
++#define PAD58_PE_HI 1
++#define PAD58_PE_SZ 1
++#define PAD58_DS_MSK 0x00000004
++#define PAD58_DS_I_MSK 0xfffffffb
++#define PAD58_DS_SFT 2
++#define PAD58_DS_HI 2
++#define PAD58_DS_SZ 1
++#define PAD58_IE_MSK 0x00000008
++#define PAD58_IE_I_MSK 0xfffffff7
++#define PAD58_IE_SFT 3
++#define PAD58_IE_HI 3
++#define PAD58_IE_SZ 1
++#define PAD58_SEL_I_MSK 0x00000030
++#define PAD58_SEL_I_I_MSK 0xffffffcf
++#define PAD58_SEL_I_SFT 4
++#define PAD58_SEL_I_HI 5
++#define PAD58_SEL_I_SZ 2
++#define PAD58_OD_MSK 0x00000100
++#define PAD58_OD_I_MSK 0xfffffeff
++#define PAD58_OD_SFT 8
++#define PAD58_OD_HI 8
++#define PAD58_OD_SZ 1
++#define PAD58_SEL_O_MSK 0x00001000
++#define PAD58_SEL_O_I_MSK 0xffffefff
++#define PAD58_SEL_O_SFT 12
++#define PAD58_SEL_O_HI 12
++#define PAD58_SEL_O_SZ 1
++#define TEST_16_ID_MSK 0x10000000
++#define TEST_16_ID_I_MSK 0xefffffff
++#define TEST_16_ID_SFT 28
++#define TEST_16_ID_HI 28
++#define TEST_16_ID_SZ 1
++#define PAD59_OE_MSK 0x00000001
++#define PAD59_OE_I_MSK 0xfffffffe
++#define PAD59_OE_SFT 0
++#define PAD59_OE_HI 0
++#define PAD59_OE_SZ 1
++#define PAD59_PE_MSK 0x00000002
++#define PAD59_PE_I_MSK 0xfffffffd
++#define PAD59_PE_SFT 1
++#define PAD59_PE_HI 1
++#define PAD59_PE_SZ 1
++#define PAD59_DS_MSK 0x00000004
++#define PAD59_DS_I_MSK 0xfffffffb
++#define PAD59_DS_SFT 2
++#define PAD59_DS_HI 2
++#define PAD59_DS_SZ 1
++#define PAD59_IE_MSK 0x00000008
++#define PAD59_IE_I_MSK 0xfffffff7
++#define PAD59_IE_SFT 3
++#define PAD59_IE_HI 3
++#define PAD59_IE_SZ 1
++#define PAD59_SEL_I_MSK 0x00000030
++#define PAD59_SEL_I_I_MSK 0xffffffcf
++#define PAD59_SEL_I_SFT 4
++#define PAD59_SEL_I_HI 5
++#define PAD59_SEL_I_SZ 2
++#define PAD59_OD_MSK 0x00000100
++#define PAD59_OD_I_MSK 0xfffffeff
++#define PAD59_OD_SFT 8
++#define PAD59_OD_HI 8
++#define PAD59_OD_SZ 1
++#define PAD59_SEL_O_MSK 0x00001000
++#define PAD59_SEL_O_I_MSK 0xffffefff
++#define PAD59_SEL_O_SFT 12
++#define PAD59_SEL_O_HI 12
++#define PAD59_SEL_O_SZ 1
++#define TEST_17_ID_MSK 0x10000000
++#define TEST_17_ID_I_MSK 0xefffffff
++#define TEST_17_ID_SFT 28
++#define TEST_17_ID_HI 28
++#define TEST_17_ID_SZ 1
++#define PAD60_OE_MSK 0x00000001
++#define PAD60_OE_I_MSK 0xfffffffe
++#define PAD60_OE_SFT 0
++#define PAD60_OE_HI 0
++#define PAD60_OE_SZ 1
++#define PAD60_PE_MSK 0x00000002
++#define PAD60_PE_I_MSK 0xfffffffd
++#define PAD60_PE_SFT 1
++#define PAD60_PE_HI 1
++#define PAD60_PE_SZ 1
++#define PAD60_DS_MSK 0x00000004
++#define PAD60_DS_I_MSK 0xfffffffb
++#define PAD60_DS_SFT 2
++#define PAD60_DS_HI 2
++#define PAD60_DS_SZ 1
++#define PAD60_IE_MSK 0x00000008
++#define PAD60_IE_I_MSK 0xfffffff7
++#define PAD60_IE_SFT 3
++#define PAD60_IE_HI 3
++#define PAD60_IE_SZ 1
++#define PAD60_SEL_I_MSK 0x00000030
++#define PAD60_SEL_I_I_MSK 0xffffffcf
++#define PAD60_SEL_I_SFT 4
++#define PAD60_SEL_I_HI 5
++#define PAD60_SEL_I_SZ 2
++#define PAD60_OD_MSK 0x00000100
++#define PAD60_OD_I_MSK 0xfffffeff
++#define PAD60_OD_SFT 8
++#define PAD60_OD_HI 8
++#define PAD60_OD_SZ 1
++#define PAD60_SEL_O_MSK 0x00001000
++#define PAD60_SEL_O_I_MSK 0xffffefff
++#define PAD60_SEL_O_SFT 12
++#define PAD60_SEL_O_HI 12
++#define PAD60_SEL_O_SZ 1
++#define TEST_18_ID_MSK 0x10000000
++#define TEST_18_ID_I_MSK 0xefffffff
++#define TEST_18_ID_SFT 28
++#define TEST_18_ID_HI 28
++#define TEST_18_ID_SZ 1
++#define PAD61_OE_MSK 0x00000001
++#define PAD61_OE_I_MSK 0xfffffffe
++#define PAD61_OE_SFT 0
++#define PAD61_OE_HI 0
++#define PAD61_OE_SZ 1
++#define PAD61_PE_MSK 0x00000002
++#define PAD61_PE_I_MSK 0xfffffffd
++#define PAD61_PE_SFT 1
++#define PAD61_PE_HI 1
++#define PAD61_PE_SZ 1
++#define PAD61_DS_MSK 0x00000004
++#define PAD61_DS_I_MSK 0xfffffffb
++#define PAD61_DS_SFT 2
++#define PAD61_DS_HI 2
++#define PAD61_DS_SZ 1
++#define PAD61_IE_MSK 0x00000008
++#define PAD61_IE_I_MSK 0xfffffff7
++#define PAD61_IE_SFT 3
++#define PAD61_IE_HI 3
++#define PAD61_IE_SZ 1
++#define PAD61_SEL_I_MSK 0x00000010
++#define PAD61_SEL_I_I_MSK 0xffffffef
++#define PAD61_SEL_I_SFT 4
++#define PAD61_SEL_I_HI 4
++#define PAD61_SEL_I_SZ 1
++#define PAD61_OD_MSK 0x00000100
++#define PAD61_OD_I_MSK 0xfffffeff
++#define PAD61_OD_SFT 8
++#define PAD61_OD_HI 8
++#define PAD61_OD_SZ 1
++#define PAD61_SEL_O_MSK 0x00003000
++#define PAD61_SEL_O_I_MSK 0xffffcfff
++#define PAD61_SEL_O_SFT 12
++#define PAD61_SEL_O_HI 13
++#define PAD61_SEL_O_SZ 2
++#define TEST_19_ID_MSK 0x10000000
++#define TEST_19_ID_I_MSK 0xefffffff
++#define TEST_19_ID_SFT 28
++#define TEST_19_ID_HI 28
++#define TEST_19_ID_SZ 1
++#define PAD62_OE_MSK 0x00000001
++#define PAD62_OE_I_MSK 0xfffffffe
++#define PAD62_OE_SFT 0
++#define PAD62_OE_HI 0
++#define PAD62_OE_SZ 1
++#define PAD62_PE_MSK 0x00000002
++#define PAD62_PE_I_MSK 0xfffffffd
++#define PAD62_PE_SFT 1
++#define PAD62_PE_HI 1
++#define PAD62_PE_SZ 1
++#define PAD62_DS_MSK 0x00000004
++#define PAD62_DS_I_MSK 0xfffffffb
++#define PAD62_DS_SFT 2
++#define PAD62_DS_HI 2
++#define PAD62_DS_SZ 1
++#define PAD62_IE_MSK 0x00000008
++#define PAD62_IE_I_MSK 0xfffffff7
++#define PAD62_IE_SFT 3
++#define PAD62_IE_HI 3
++#define PAD62_IE_SZ 1
++#define PAD62_SEL_I_MSK 0x00000010
++#define PAD62_SEL_I_I_MSK 0xffffffef
++#define PAD62_SEL_I_SFT 4
++#define PAD62_SEL_I_HI 4
++#define PAD62_SEL_I_SZ 1
++#define PAD62_OD_MSK 0x00000100
++#define PAD62_OD_I_MSK 0xfffffeff
++#define PAD62_OD_SFT 8
++#define PAD62_OD_HI 8
++#define PAD62_OD_SZ 1
++#define PAD62_SEL_O_MSK 0x00001000
++#define PAD62_SEL_O_I_MSK 0xffffefff
++#define PAD62_SEL_O_SFT 12
++#define PAD62_SEL_O_HI 12
++#define PAD62_SEL_O_SZ 1
++#define TEST_20_ID_MSK 0x10000000
++#define TEST_20_ID_I_MSK 0xefffffff
++#define TEST_20_ID_SFT 28
++#define TEST_20_ID_HI 28
++#define TEST_20_ID_SZ 1
++#define PAD64_OE_MSK 0x00000001
++#define PAD64_OE_I_MSK 0xfffffffe
++#define PAD64_OE_SFT 0
++#define PAD64_OE_HI 0
++#define PAD64_OE_SZ 1
++#define PAD64_PE_MSK 0x00000002
++#define PAD64_PE_I_MSK 0xfffffffd
++#define PAD64_PE_SFT 1
++#define PAD64_PE_HI 1
++#define PAD64_PE_SZ 1
++#define PAD64_DS_MSK 0x00000004
++#define PAD64_DS_I_MSK 0xfffffffb
++#define PAD64_DS_SFT 2
++#define PAD64_DS_HI 2
++#define PAD64_DS_SZ 1
++#define PAD64_IE_MSK 0x00000008
++#define PAD64_IE_I_MSK 0xfffffff7
++#define PAD64_IE_SFT 3
++#define PAD64_IE_HI 3
++#define PAD64_IE_SZ 1
++#define PAD64_SEL_I_MSK 0x00000070
++#define PAD64_SEL_I_I_MSK 0xffffff8f
++#define PAD64_SEL_I_SFT 4
++#define PAD64_SEL_I_HI 6
++#define PAD64_SEL_I_SZ 3
++#define PAD64_OD_MSK 0x00000100
++#define PAD64_OD_I_MSK 0xfffffeff
++#define PAD64_OD_SFT 8
++#define PAD64_OD_HI 8
++#define PAD64_OD_SZ 1
++#define PAD64_SEL_O_MSK 0x00003000
++#define PAD64_SEL_O_I_MSK 0xffffcfff
++#define PAD64_SEL_O_SFT 12
++#define PAD64_SEL_O_HI 13
++#define PAD64_SEL_O_SZ 2
++#define PAD64_SEL_OE_MSK 0x00100000
++#define PAD64_SEL_OE_I_MSK 0xffefffff
++#define PAD64_SEL_OE_SFT 20
++#define PAD64_SEL_OE_HI 20
++#define PAD64_SEL_OE_SZ 1
++#define GPIO_15_IP_ID_MSK 0x10000000
++#define GPIO_15_IP_ID_I_MSK 0xefffffff
++#define GPIO_15_IP_ID_SFT 28
++#define GPIO_15_IP_ID_HI 28
++#define GPIO_15_IP_ID_SZ 1
++#define PAD65_OE_MSK 0x00000001
++#define PAD65_OE_I_MSK 0xfffffffe
++#define PAD65_OE_SFT 0
++#define PAD65_OE_HI 0
++#define PAD65_OE_SZ 1
++#define PAD65_PE_MSK 0x00000002
++#define PAD65_PE_I_MSK 0xfffffffd
++#define PAD65_PE_SFT 1
++#define PAD65_PE_HI 1
++#define PAD65_PE_SZ 1
++#define PAD65_DS_MSK 0x00000004
++#define PAD65_DS_I_MSK 0xfffffffb
++#define PAD65_DS_SFT 2
++#define PAD65_DS_HI 2
++#define PAD65_DS_SZ 1
++#define PAD65_IE_MSK 0x00000008
++#define PAD65_IE_I_MSK 0xfffffff7
++#define PAD65_IE_SFT 3
++#define PAD65_IE_HI 3
++#define PAD65_IE_SZ 1
++#define PAD65_SEL_I_MSK 0x00000070
++#define PAD65_SEL_I_I_MSK 0xffffff8f
++#define PAD65_SEL_I_SFT 4
++#define PAD65_SEL_I_HI 6
++#define PAD65_SEL_I_SZ 3
++#define PAD65_OD_MSK 0x00000100
++#define PAD65_OD_I_MSK 0xfffffeff
++#define PAD65_OD_SFT 8
++#define PAD65_OD_HI 8
++#define PAD65_OD_SZ 1
++#define PAD65_SEL_O_MSK 0x00001000
++#define PAD65_SEL_O_I_MSK 0xffffefff
++#define PAD65_SEL_O_SFT 12
++#define PAD65_SEL_O_HI 12
++#define PAD65_SEL_O_SZ 1
++#define GPIO_TEST_7_IN_ID_MSK 0x10000000
++#define GPIO_TEST_7_IN_ID_I_MSK 0xefffffff
++#define GPIO_TEST_7_IN_ID_SFT 28
++#define GPIO_TEST_7_IN_ID_HI 28
++#define GPIO_TEST_7_IN_ID_SZ 1
++#define PAD66_OE_MSK 0x00000001
++#define PAD66_OE_I_MSK 0xfffffffe
++#define PAD66_OE_SFT 0
++#define PAD66_OE_HI 0
++#define PAD66_OE_SZ 1
++#define PAD66_PE_MSK 0x00000002
++#define PAD66_PE_I_MSK 0xfffffffd
++#define PAD66_PE_SFT 1
++#define PAD66_PE_HI 1
++#define PAD66_PE_SZ 1
++#define PAD66_DS_MSK 0x00000004
++#define PAD66_DS_I_MSK 0xfffffffb
++#define PAD66_DS_SFT 2
++#define PAD66_DS_HI 2
++#define PAD66_DS_SZ 1
++#define PAD66_IE_MSK 0x00000008
++#define PAD66_IE_I_MSK 0xfffffff7
++#define PAD66_IE_SFT 3
++#define PAD66_IE_HI 3
++#define PAD66_IE_SZ 1
++#define PAD66_SEL_I_MSK 0x00000030
++#define PAD66_SEL_I_I_MSK 0xffffffcf
++#define PAD66_SEL_I_SFT 4
++#define PAD66_SEL_I_HI 5
++#define PAD66_SEL_I_SZ 2
++#define PAD66_OD_MSK 0x00000100
++#define PAD66_OD_I_MSK 0xfffffeff
++#define PAD66_OD_SFT 8
++#define PAD66_OD_HI 8
++#define PAD66_OD_SZ 1
++#define PAD66_SEL_O_MSK 0x00003000
++#define PAD66_SEL_O_I_MSK 0xffffcfff
++#define PAD66_SEL_O_SFT 12
++#define PAD66_SEL_O_HI 13
++#define PAD66_SEL_O_SZ 2
++#define GPIO_17_QP_ID_MSK 0x10000000
++#define GPIO_17_QP_ID_I_MSK 0xefffffff
++#define GPIO_17_QP_ID_SFT 28
++#define GPIO_17_QP_ID_HI 28
++#define GPIO_17_QP_ID_SZ 1
++#define PAD68_OE_MSK 0x00000001
++#define PAD68_OE_I_MSK 0xfffffffe
++#define PAD68_OE_SFT 0
++#define PAD68_OE_HI 0
++#define PAD68_OE_SZ 1
++#define PAD68_PE_MSK 0x00000002
++#define PAD68_PE_I_MSK 0xfffffffd
++#define PAD68_PE_SFT 1
++#define PAD68_PE_HI 1
++#define PAD68_PE_SZ 1
++#define PAD68_DS_MSK 0x00000004
++#define PAD68_DS_I_MSK 0xfffffffb
++#define PAD68_DS_SFT 2
++#define PAD68_DS_HI 2
++#define PAD68_DS_SZ 1
++#define PAD68_IE_MSK 0x00000008
++#define PAD68_IE_I_MSK 0xfffffff7
++#define PAD68_IE_SFT 3
++#define PAD68_IE_HI 3
++#define PAD68_IE_SZ 1
++#define PAD68_OD_MSK 0x00000100
++#define PAD68_OD_I_MSK 0xfffffeff
++#define PAD68_OD_SFT 8
++#define PAD68_OD_HI 8
++#define PAD68_OD_SZ 1
++#define PAD68_SEL_O_MSK 0x00001000
++#define PAD68_SEL_O_I_MSK 0xffffefff
++#define PAD68_SEL_O_SFT 12
++#define PAD68_SEL_O_HI 12
++#define PAD68_SEL_O_SZ 1
++#define GPIO_19_ID_MSK 0x10000000
++#define GPIO_19_ID_I_MSK 0xefffffff
++#define GPIO_19_ID_SFT 28
++#define GPIO_19_ID_HI 28
++#define GPIO_19_ID_SZ 1
++#define PAD67_OE_MSK 0x00000001
++#define PAD67_OE_I_MSK 0xfffffffe
++#define PAD67_OE_SFT 0
++#define PAD67_OE_HI 0
++#define PAD67_OE_SZ 1
++#define PAD67_PE_MSK 0x00000002
++#define PAD67_PE_I_MSK 0xfffffffd
++#define PAD67_PE_SFT 1
++#define PAD67_PE_HI 1
++#define PAD67_PE_SZ 1
++#define PAD67_DS_MSK 0x00000004
++#define PAD67_DS_I_MSK 0xfffffffb
++#define PAD67_DS_SFT 2
++#define PAD67_DS_HI 2
++#define PAD67_DS_SZ 1
++#define PAD67_IE_MSK 0x00000008
++#define PAD67_IE_I_MSK 0xfffffff7
++#define PAD67_IE_SFT 3
++#define PAD67_IE_HI 3
++#define PAD67_IE_SZ 1
++#define PAD67_SEL_I_MSK 0x00000070
++#define PAD67_SEL_I_I_MSK 0xffffff8f
++#define PAD67_SEL_I_SFT 4
++#define PAD67_SEL_I_HI 6
++#define PAD67_SEL_I_SZ 3
++#define PAD67_OD_MSK 0x00000100
++#define PAD67_OD_I_MSK 0xfffffeff
++#define PAD67_OD_SFT 8
++#define PAD67_OD_HI 8
++#define PAD67_OD_SZ 1
++#define PAD67_SEL_O_MSK 0x00003000
++#define PAD67_SEL_O_I_MSK 0xffffcfff
++#define PAD67_SEL_O_SFT 12
++#define PAD67_SEL_O_HI 13
++#define PAD67_SEL_O_SZ 2
++#define GPIO_TEST_8_QN_ID_MSK 0x10000000
++#define GPIO_TEST_8_QN_ID_I_MSK 0xefffffff
++#define GPIO_TEST_8_QN_ID_SFT 28
++#define GPIO_TEST_8_QN_ID_HI 28
++#define GPIO_TEST_8_QN_ID_SZ 1
++#define PAD69_OE_MSK 0x00000001
++#define PAD69_OE_I_MSK 0xfffffffe
++#define PAD69_OE_SFT 0
++#define PAD69_OE_HI 0
++#define PAD69_OE_SZ 1
++#define PAD69_PE_MSK 0x00000002
++#define PAD69_PE_I_MSK 0xfffffffd
++#define PAD69_PE_SFT 1
++#define PAD69_PE_HI 1
++#define PAD69_PE_SZ 1
++#define PAD69_DS_MSK 0x00000004
++#define PAD69_DS_I_MSK 0xfffffffb
++#define PAD69_DS_SFT 2
++#define PAD69_DS_HI 2
++#define PAD69_DS_SZ 1
++#define PAD69_IE_MSK 0x00000008
++#define PAD69_IE_I_MSK 0xfffffff7
++#define PAD69_IE_SFT 3
++#define PAD69_IE_HI 3
++#define PAD69_IE_SZ 1
++#define PAD69_SEL_I_MSK 0x00000030
++#define PAD69_SEL_I_I_MSK 0xffffffcf
++#define PAD69_SEL_I_SFT 4
++#define PAD69_SEL_I_HI 5
++#define PAD69_SEL_I_SZ 2
++#define PAD69_OD_MSK 0x00000100
++#define PAD69_OD_I_MSK 0xfffffeff
++#define PAD69_OD_SFT 8
++#define PAD69_OD_HI 8
++#define PAD69_OD_SZ 1
++#define PAD69_SEL_O_MSK 0x00001000
++#define PAD69_SEL_O_I_MSK 0xffffefff
++#define PAD69_SEL_O_SFT 12
++#define PAD69_SEL_O_HI 12
++#define PAD69_SEL_O_SZ 1
++#define STRAP2_MSK 0x08000000
++#define STRAP2_I_MSK 0xf7ffffff
++#define STRAP2_SFT 27
++#define STRAP2_HI 27
++#define STRAP2_SZ 1
++#define GPIO_20_ID_MSK 0x10000000
++#define GPIO_20_ID_I_MSK 0xefffffff
++#define GPIO_20_ID_SFT 28
++#define GPIO_20_ID_HI 28
++#define GPIO_20_ID_SZ 1
++#define PAD70_OE_MSK 0x00000001
++#define PAD70_OE_I_MSK 0xfffffffe
++#define PAD70_OE_SFT 0
++#define PAD70_OE_HI 0
++#define PAD70_OE_SZ 1
++#define PAD70_PE_MSK 0x00000002
++#define PAD70_PE_I_MSK 0xfffffffd
++#define PAD70_PE_SFT 1
++#define PAD70_PE_HI 1
++#define PAD70_PE_SZ 1
++#define PAD70_DS_MSK 0x00000004
++#define PAD70_DS_I_MSK 0xfffffffb
++#define PAD70_DS_SFT 2
++#define PAD70_DS_HI 2
++#define PAD70_DS_SZ 1
++#define PAD70_IE_MSK 0x00000008
++#define PAD70_IE_I_MSK 0xfffffff7
++#define PAD70_IE_SFT 3
++#define PAD70_IE_HI 3
++#define PAD70_IE_SZ 1
++#define PAD70_SEL_I_MSK 0x00000030
++#define PAD70_SEL_I_I_MSK 0xffffffcf
++#define PAD70_SEL_I_SFT 4
++#define PAD70_SEL_I_HI 5
++#define PAD70_SEL_I_SZ 2
++#define PAD70_OD_MSK 0x00000100
++#define PAD70_OD_I_MSK 0xfffffeff
++#define PAD70_OD_SFT 8
++#define PAD70_OD_HI 8
++#define PAD70_OD_SZ 1
++#define PAD70_SEL_O_MSK 0x00007000
++#define PAD70_SEL_O_I_MSK 0xffff8fff
++#define PAD70_SEL_O_SFT 12
++#define PAD70_SEL_O_HI 14
++#define PAD70_SEL_O_SZ 3
++#define GPIO_21_ID_MSK 0x10000000
++#define GPIO_21_ID_I_MSK 0xefffffff
++#define GPIO_21_ID_SFT 28
++#define GPIO_21_ID_HI 28
++#define GPIO_21_ID_SZ 1
++#define PAD231_OE_MSK 0x00000001
++#define PAD231_OE_I_MSK 0xfffffffe
++#define PAD231_OE_SFT 0
++#define PAD231_OE_HI 0
++#define PAD231_OE_SZ 1
++#define PAD231_PE_MSK 0x00000002
++#define PAD231_PE_I_MSK 0xfffffffd
++#define PAD231_PE_SFT 1
++#define PAD231_PE_HI 1
++#define PAD231_PE_SZ 1
++#define PAD231_DS_MSK 0x00000004
++#define PAD231_DS_I_MSK 0xfffffffb
++#define PAD231_DS_SFT 2
++#define PAD231_DS_HI 2
++#define PAD231_DS_SZ 1
++#define PAD231_IE_MSK 0x00000008
++#define PAD231_IE_I_MSK 0xfffffff7
++#define PAD231_IE_SFT 3
++#define PAD231_IE_HI 3
++#define PAD231_IE_SZ 1
++#define PAD231_OD_MSK 0x00000100
++#define PAD231_OD_I_MSK 0xfffffeff
++#define PAD231_OD_SFT 8
++#define PAD231_OD_HI 8
++#define PAD231_OD_SZ 1
++#define PIN_40_OR_56_ID_MSK 0x10000000
++#define PIN_40_OR_56_ID_I_MSK 0xefffffff
++#define PIN_40_OR_56_ID_SFT 28
++#define PIN_40_OR_56_ID_HI 28
++#define PIN_40_OR_56_ID_SZ 1
++#define MP_PHY2RX_DATA__0_SEL_MSK 0x00000001
++#define MP_PHY2RX_DATA__0_SEL_I_MSK 0xfffffffe
++#define MP_PHY2RX_DATA__0_SEL_SFT 0
++#define MP_PHY2RX_DATA__0_SEL_HI 0
++#define MP_PHY2RX_DATA__0_SEL_SZ 1
++#define MP_PHY2RX_DATA__1_SEL_MSK 0x00000002
++#define MP_PHY2RX_DATA__1_SEL_I_MSK 0xfffffffd
++#define MP_PHY2RX_DATA__1_SEL_SFT 1
++#define MP_PHY2RX_DATA__1_SEL_HI 1
++#define MP_PHY2RX_DATA__1_SEL_SZ 1
++#define MP_TX_FF_RPTR__1_SEL_MSK 0x00000004
++#define MP_TX_FF_RPTR__1_SEL_I_MSK 0xfffffffb
++#define MP_TX_FF_RPTR__1_SEL_SFT 2
++#define MP_TX_FF_RPTR__1_SEL_HI 2
++#define MP_TX_FF_RPTR__1_SEL_SZ 1
++#define MP_RX_FF_WPTR__2_SEL_MSK 0x00000008
++#define MP_RX_FF_WPTR__2_SEL_I_MSK 0xfffffff7
++#define MP_RX_FF_WPTR__2_SEL_SFT 3
++#define MP_RX_FF_WPTR__2_SEL_HI 3
++#define MP_RX_FF_WPTR__2_SEL_SZ 1
++#define MP_RX_FF_WPTR__1_SEL_MSK 0x00000010
++#define MP_RX_FF_WPTR__1_SEL_I_MSK 0xffffffef
++#define MP_RX_FF_WPTR__1_SEL_SFT 4
++#define MP_RX_FF_WPTR__1_SEL_HI 4
++#define MP_RX_FF_WPTR__1_SEL_SZ 1
++#define MP_RX_FF_WPTR__0_SEL_MSK 0x00000020
++#define MP_RX_FF_WPTR__0_SEL_I_MSK 0xffffffdf
++#define MP_RX_FF_WPTR__0_SEL_SFT 5
++#define MP_RX_FF_WPTR__0_SEL_HI 5
++#define MP_RX_FF_WPTR__0_SEL_SZ 1
++#define MP_PHY2RX_DATA__2_SEL_MSK 0x00000040
++#define MP_PHY2RX_DATA__2_SEL_I_MSK 0xffffffbf
++#define MP_PHY2RX_DATA__2_SEL_SFT 6
++#define MP_PHY2RX_DATA__2_SEL_HI 6
++#define MP_PHY2RX_DATA__2_SEL_SZ 1
++#define MP_PHY2RX_DATA__4_SEL_MSK 0x00000080
++#define MP_PHY2RX_DATA__4_SEL_I_MSK 0xffffff7f
++#define MP_PHY2RX_DATA__4_SEL_SFT 7
++#define MP_PHY2RX_DATA__4_SEL_HI 7
++#define MP_PHY2RX_DATA__4_SEL_SZ 1
++#define I2CM_SDA_ID_SEL_MSK 0x00000300
++#define I2CM_SDA_ID_SEL_I_MSK 0xfffffcff
++#define I2CM_SDA_ID_SEL_SFT 8
++#define I2CM_SDA_ID_SEL_HI 9
++#define I2CM_SDA_ID_SEL_SZ 2
++#define CRYSTAL_OUT_REQ_SEL_MSK 0x00000400
++#define CRYSTAL_OUT_REQ_SEL_I_MSK 0xfffffbff
++#define CRYSTAL_OUT_REQ_SEL_SFT 10
++#define CRYSTAL_OUT_REQ_SEL_HI 10
++#define CRYSTAL_OUT_REQ_SEL_SZ 1
++#define MP_PHY2RX_DATA__5_SEL_MSK 0x00000800
++#define MP_PHY2RX_DATA__5_SEL_I_MSK 0xfffff7ff
++#define MP_PHY2RX_DATA__5_SEL_SFT 11
++#define MP_PHY2RX_DATA__5_SEL_HI 11
++#define MP_PHY2RX_DATA__5_SEL_SZ 1
++#define MP_PHY2RX_DATA__3_SEL_MSK 0x00001000
++#define MP_PHY2RX_DATA__3_SEL_I_MSK 0xffffefff
++#define MP_PHY2RX_DATA__3_SEL_SFT 12
++#define MP_PHY2RX_DATA__3_SEL_HI 12
++#define MP_PHY2RX_DATA__3_SEL_SZ 1
++#define UART_RXD_SEL_MSK 0x00006000
++#define UART_RXD_SEL_I_MSK 0xffff9fff
++#define UART_RXD_SEL_SFT 13
++#define UART_RXD_SEL_HI 14
++#define UART_RXD_SEL_SZ 2
++#define MP_PHY2RX_DATA__6_SEL_MSK 0x00008000
++#define MP_PHY2RX_DATA__6_SEL_I_MSK 0xffff7fff
++#define MP_PHY2RX_DATA__6_SEL_SFT 15
++#define MP_PHY2RX_DATA__6_SEL_HI 15
++#define MP_PHY2RX_DATA__6_SEL_SZ 1
++#define DAT_UART_NCTS_SEL_MSK 0x00010000
++#define DAT_UART_NCTS_SEL_I_MSK 0xfffeffff
++#define DAT_UART_NCTS_SEL_SFT 16
++#define DAT_UART_NCTS_SEL_HI 16
++#define DAT_UART_NCTS_SEL_SZ 1
++#define GPIO_LOG_STOP_SEL_MSK 0x000e0000
++#define GPIO_LOG_STOP_SEL_I_MSK 0xfff1ffff
++#define GPIO_LOG_STOP_SEL_SFT 17
++#define GPIO_LOG_STOP_SEL_HI 19
++#define GPIO_LOG_STOP_SEL_SZ 3
++#define MP_TX_FF_RPTR__0_SEL_MSK 0x00100000
++#define MP_TX_FF_RPTR__0_SEL_I_MSK 0xffefffff
++#define MP_TX_FF_RPTR__0_SEL_SFT 20
++#define MP_TX_FF_RPTR__0_SEL_HI 20
++#define MP_TX_FF_RPTR__0_SEL_SZ 1
++#define MP_PHY_RX_WRST_N_SEL_MSK 0x00200000
++#define MP_PHY_RX_WRST_N_SEL_I_MSK 0xffdfffff
++#define MP_PHY_RX_WRST_N_SEL_SFT 21
++#define MP_PHY_RX_WRST_N_SEL_HI 21
++#define MP_PHY_RX_WRST_N_SEL_SZ 1
++#define EXT_32K_SEL_MSK 0x00c00000
++#define EXT_32K_SEL_I_MSK 0xff3fffff
++#define EXT_32K_SEL_SFT 22
++#define EXT_32K_SEL_HI 23
++#define EXT_32K_SEL_SZ 2
++#define MP_PHY2RX_DATA__7_SEL_MSK 0x01000000
++#define MP_PHY2RX_DATA__7_SEL_I_MSK 0xfeffffff
++#define MP_PHY2RX_DATA__7_SEL_SFT 24
++#define MP_PHY2RX_DATA__7_SEL_HI 24
++#define MP_PHY2RX_DATA__7_SEL_SZ 1
++#define MP_TX_FF_RPTR__2_SEL_MSK 0x02000000
++#define MP_TX_FF_RPTR__2_SEL_I_MSK 0xfdffffff
++#define MP_TX_FF_RPTR__2_SEL_SFT 25
++#define MP_TX_FF_RPTR__2_SEL_HI 25
++#define MP_TX_FF_RPTR__2_SEL_SZ 1
++#define PMUINT_WAKE_SEL_MSK 0x1c000000
++#define PMUINT_WAKE_SEL_I_MSK 0xe3ffffff
++#define PMUINT_WAKE_SEL_SFT 26
++#define PMUINT_WAKE_SEL_HI 28
++#define PMUINT_WAKE_SEL_SZ 3
++#define I2CM_SCL_ID_SEL_MSK 0x20000000
++#define I2CM_SCL_ID_SEL_I_MSK 0xdfffffff
++#define I2CM_SCL_ID_SEL_SFT 29
++#define I2CM_SCL_ID_SEL_HI 29
++#define I2CM_SCL_ID_SEL_SZ 1
++#define MP_MRX_RX_EN_SEL_MSK 0x40000000
++#define MP_MRX_RX_EN_SEL_I_MSK 0xbfffffff
++#define MP_MRX_RX_EN_SEL_SFT 30
++#define MP_MRX_RX_EN_SEL_HI 30
++#define MP_MRX_RX_EN_SEL_SZ 1
++#define DAT_UART_RXD_SEL_0_MSK 0x80000000
++#define DAT_UART_RXD_SEL_0_I_MSK 0x7fffffff
++#define DAT_UART_RXD_SEL_0_SFT 31
++#define DAT_UART_RXD_SEL_0_HI 31
++#define DAT_UART_RXD_SEL_0_SZ 1
++#define DAT_UART_RXD_SEL_1_MSK 0x00000001
++#define DAT_UART_RXD_SEL_1_I_MSK 0xfffffffe
++#define DAT_UART_RXD_SEL_1_SFT 0
++#define DAT_UART_RXD_SEL_1_HI 0
++#define DAT_UART_RXD_SEL_1_SZ 1
++#define SPI_DI_SEL_MSK 0x00000002
++#define SPI_DI_SEL_I_MSK 0xfffffffd
++#define SPI_DI_SEL_SFT 1
++#define SPI_DI_SEL_HI 1
++#define SPI_DI_SEL_SZ 1
++#define IO_PORT_REG_MSK 0x0001ffff
++#define IO_PORT_REG_I_MSK 0xfffe0000
++#define IO_PORT_REG_SFT 0
++#define IO_PORT_REG_HI 16
++#define IO_PORT_REG_SZ 17
++#define MASK_RX_INT_MSK 0x00000001
++#define MASK_RX_INT_I_MSK 0xfffffffe
++#define MASK_RX_INT_SFT 0
++#define MASK_RX_INT_HI 0
++#define MASK_RX_INT_SZ 1
++#define MASK_TX_INT_MSK 0x00000002
++#define MASK_TX_INT_I_MSK 0xfffffffd
++#define MASK_TX_INT_SFT 1
++#define MASK_TX_INT_HI 1
++#define MASK_TX_INT_SZ 1
++#define MASK_SOC_SYSTEM_INT_MSK 0x00000004
++#define MASK_SOC_SYSTEM_INT_I_MSK 0xfffffffb
++#define MASK_SOC_SYSTEM_INT_SFT 2
++#define MASK_SOC_SYSTEM_INT_HI 2
++#define MASK_SOC_SYSTEM_INT_SZ 1
++#define EDCA0_LOW_THR_INT_MASK_MSK 0x00000008
++#define EDCA0_LOW_THR_INT_MASK_I_MSK 0xfffffff7
++#define EDCA0_LOW_THR_INT_MASK_SFT 3
++#define EDCA0_LOW_THR_INT_MASK_HI 3
++#define EDCA0_LOW_THR_INT_MASK_SZ 1
++#define EDCA1_LOW_THR_INT_MASK_MSK 0x00000010
++#define EDCA1_LOW_THR_INT_MASK_I_MSK 0xffffffef
++#define EDCA1_LOW_THR_INT_MASK_SFT 4
++#define EDCA1_LOW_THR_INT_MASK_HI 4
++#define EDCA1_LOW_THR_INT_MASK_SZ 1
++#define EDCA2_LOW_THR_INT_MASK_MSK 0x00000020
++#define EDCA2_LOW_THR_INT_MASK_I_MSK 0xffffffdf
++#define EDCA2_LOW_THR_INT_MASK_SFT 5
++#define EDCA2_LOW_THR_INT_MASK_HI 5
++#define EDCA2_LOW_THR_INT_MASK_SZ 1
++#define EDCA3_LOW_THR_INT_MASK_MSK 0x00000040
++#define EDCA3_LOW_THR_INT_MASK_I_MSK 0xffffffbf
++#define EDCA3_LOW_THR_INT_MASK_SFT 6
++#define EDCA3_LOW_THR_INT_MASK_HI 6
++#define EDCA3_LOW_THR_INT_MASK_SZ 1
++#define TX_LIMIT_INT_MASK_MSK 0x00000080
++#define TX_LIMIT_INT_MASK_I_MSK 0xffffff7f
++#define TX_LIMIT_INT_MASK_SFT 7
++#define TX_LIMIT_INT_MASK_HI 7
++#define TX_LIMIT_INT_MASK_SZ 1
++#define RX_INT_MSK 0x00000001
++#define RX_INT_I_MSK 0xfffffffe
++#define RX_INT_SFT 0
++#define RX_INT_HI 0
++#define RX_INT_SZ 1
++#define TX_COMPLETE_INT_MSK 0x00000002
++#define TX_COMPLETE_INT_I_MSK 0xfffffffd
++#define TX_COMPLETE_INT_SFT 1
++#define TX_COMPLETE_INT_HI 1
++#define TX_COMPLETE_INT_SZ 1
++#define SOC_SYSTEM_INT_STATUS_MSK 0x00000004
++#define SOC_SYSTEM_INT_STATUS_I_MSK 0xfffffffb
++#define SOC_SYSTEM_INT_STATUS_SFT 2
++#define SOC_SYSTEM_INT_STATUS_HI 2
++#define SOC_SYSTEM_INT_STATUS_SZ 1
++#define EDCA0_LOW_THR_INT_STS_MSK 0x00000008
++#define EDCA0_LOW_THR_INT_STS_I_MSK 0xfffffff7
++#define EDCA0_LOW_THR_INT_STS_SFT 3
++#define EDCA0_LOW_THR_INT_STS_HI 3
++#define EDCA0_LOW_THR_INT_STS_SZ 1
++#define EDCA1_LOW_THR_INT_STS_MSK 0x00000010
++#define EDCA1_LOW_THR_INT_STS_I_MSK 0xffffffef
++#define EDCA1_LOW_THR_INT_STS_SFT 4
++#define EDCA1_LOW_THR_INT_STS_HI 4
++#define EDCA1_LOW_THR_INT_STS_SZ 1
++#define EDCA2_LOW_THR_INT_STS_MSK 0x00000020
++#define EDCA2_LOW_THR_INT_STS_I_MSK 0xffffffdf
++#define EDCA2_LOW_THR_INT_STS_SFT 5
++#define EDCA2_LOW_THR_INT_STS_HI 5
++#define EDCA2_LOW_THR_INT_STS_SZ 1
++#define EDCA3_LOW_THR_INT_STS_MSK 0x00000040
++#define EDCA3_LOW_THR_INT_STS_I_MSK 0xffffffbf
++#define EDCA3_LOW_THR_INT_STS_SFT 6
++#define EDCA3_LOW_THR_INT_STS_HI 6
++#define EDCA3_LOW_THR_INT_STS_SZ 1
++#define TX_LIMIT_INT_STS_MSK 0x00000080
++#define TX_LIMIT_INT_STS_I_MSK 0xffffff7f
++#define TX_LIMIT_INT_STS_SFT 7
++#define TX_LIMIT_INT_STS_HI 7
++#define TX_LIMIT_INT_STS_SZ 1
++#define HOST_TRIGGERED_RX_INT_MSK 0x00000100
++#define HOST_TRIGGERED_RX_INT_I_MSK 0xfffffeff
++#define HOST_TRIGGERED_RX_INT_SFT 8
++#define HOST_TRIGGERED_RX_INT_HI 8
++#define HOST_TRIGGERED_RX_INT_SZ 1
++#define HOST_TRIGGERED_TX_INT_MSK 0x00000200
++#define HOST_TRIGGERED_TX_INT_I_MSK 0xfffffdff
++#define HOST_TRIGGERED_TX_INT_SFT 9
++#define HOST_TRIGGERED_TX_INT_HI 9
++#define HOST_TRIGGERED_TX_INT_SZ 1
++#define SOC_TRIGGER_RX_INT_MSK 0x00000400
++#define SOC_TRIGGER_RX_INT_I_MSK 0xfffffbff
++#define SOC_TRIGGER_RX_INT_SFT 10
++#define SOC_TRIGGER_RX_INT_HI 10
++#define SOC_TRIGGER_RX_INT_SZ 1
++#define SOC_TRIGGER_TX_INT_MSK 0x00000800
++#define SOC_TRIGGER_TX_INT_I_MSK 0xfffff7ff
++#define SOC_TRIGGER_TX_INT_SFT 11
++#define SOC_TRIGGER_TX_INT_HI 11
++#define SOC_TRIGGER_TX_INT_SZ 1
++#define RDY_FOR_TX_RX_MSK 0x00000001
++#define RDY_FOR_TX_RX_I_MSK 0xfffffffe
++#define RDY_FOR_TX_RX_SFT 0
++#define RDY_FOR_TX_RX_HI 0
++#define RDY_FOR_TX_RX_SZ 1
++#define RDY_FOR_FW_DOWNLOAD_MSK 0x00000002
++#define RDY_FOR_FW_DOWNLOAD_I_MSK 0xfffffffd
++#define RDY_FOR_FW_DOWNLOAD_SFT 1
++#define RDY_FOR_FW_DOWNLOAD_HI 1
++#define RDY_FOR_FW_DOWNLOAD_SZ 1
++#define ILLEGAL_CMD_RESP_OPTION_MSK 0x00000004
++#define ILLEGAL_CMD_RESP_OPTION_I_MSK 0xfffffffb
++#define ILLEGAL_CMD_RESP_OPTION_SFT 2
++#define ILLEGAL_CMD_RESP_OPTION_HI 2
++#define ILLEGAL_CMD_RESP_OPTION_SZ 1
++#define SDIO_TRX_DATA_SEQUENCE_MSK 0x00000008
++#define SDIO_TRX_DATA_SEQUENCE_I_MSK 0xfffffff7
++#define SDIO_TRX_DATA_SEQUENCE_SFT 3
++#define SDIO_TRX_DATA_SEQUENCE_HI 3
++#define SDIO_TRX_DATA_SEQUENCE_SZ 1
++#define GPIO_INT_TRIGGER_OPTION_MSK 0x00000010
++#define GPIO_INT_TRIGGER_OPTION_I_MSK 0xffffffef
++#define GPIO_INT_TRIGGER_OPTION_SFT 4
++#define GPIO_INT_TRIGGER_OPTION_HI 4
++#define GPIO_INT_TRIGGER_OPTION_SZ 1
++#define TRIGGER_FUNCTION_SETTING_MSK 0x00000060
++#define TRIGGER_FUNCTION_SETTING_I_MSK 0xffffff9f
++#define TRIGGER_FUNCTION_SETTING_SFT 5
++#define TRIGGER_FUNCTION_SETTING_HI 6
++#define TRIGGER_FUNCTION_SETTING_SZ 2
++#define CMD52_ABORT_RESPONSE_MSK 0x00000080
++#define CMD52_ABORT_RESPONSE_I_MSK 0xffffff7f
++#define CMD52_ABORT_RESPONSE_SFT 7
++#define CMD52_ABORT_RESPONSE_HI 7
++#define CMD52_ABORT_RESPONSE_SZ 1
++#define RX_PACKET_LENGTH_MSK 0x0000ffff
++#define RX_PACKET_LENGTH_I_MSK 0xffff0000
++#define RX_PACKET_LENGTH_SFT 0
++#define RX_PACKET_LENGTH_HI 15
++#define RX_PACKET_LENGTH_SZ 16
++#define CARD_FW_DL_STATUS_MSK 0x00ff0000
++#define CARD_FW_DL_STATUS_I_MSK 0xff00ffff
++#define CARD_FW_DL_STATUS_SFT 16
++#define CARD_FW_DL_STATUS_HI 23
++#define CARD_FW_DL_STATUS_SZ 8
++#define TX_RX_LOOP_BACK_TEST_MSK 0x01000000
++#define TX_RX_LOOP_BACK_TEST_I_MSK 0xfeffffff
++#define TX_RX_LOOP_BACK_TEST_SFT 24
++#define TX_RX_LOOP_BACK_TEST_HI 24
++#define TX_RX_LOOP_BACK_TEST_SZ 1
++#define SDIO_LOOP_BACK_TEST_MSK 0x02000000
++#define SDIO_LOOP_BACK_TEST_I_MSK 0xfdffffff
++#define SDIO_LOOP_BACK_TEST_SFT 25
++#define SDIO_LOOP_BACK_TEST_HI 25
++#define SDIO_LOOP_BACK_TEST_SZ 1
++#define CMD52_ABORT_ACTIVE_MSK 0x10000000
++#define CMD52_ABORT_ACTIVE_I_MSK 0xefffffff
++#define CMD52_ABORT_ACTIVE_SFT 28
++#define CMD52_ABORT_ACTIVE_HI 28
++#define CMD52_ABORT_ACTIVE_SZ 1
++#define CMD52_RESET_ACTIVE_MSK 0x20000000
++#define CMD52_RESET_ACTIVE_I_MSK 0xdfffffff
++#define CMD52_RESET_ACTIVE_SFT 29
++#define CMD52_RESET_ACTIVE_HI 29
++#define CMD52_RESET_ACTIVE_SZ 1
++#define SDIO_PARTIAL_RESET_ACTIVE_MSK 0x40000000
++#define SDIO_PARTIAL_RESET_ACTIVE_I_MSK 0xbfffffff
++#define SDIO_PARTIAL_RESET_ACTIVE_SFT 30
++#define SDIO_PARTIAL_RESET_ACTIVE_HI 30
++#define SDIO_PARTIAL_RESET_ACTIVE_SZ 1
++#define SDIO_ALL_RESE_ACTIVE_MSK 0x80000000
++#define SDIO_ALL_RESE_ACTIVE_I_MSK 0x7fffffff
++#define SDIO_ALL_RESE_ACTIVE_SFT 31
++#define SDIO_ALL_RESE_ACTIVE_HI 31
++#define SDIO_ALL_RESE_ACTIVE_SZ 1
++#define RX_PACKET_LENGTH2_MSK 0x0000ffff
++#define RX_PACKET_LENGTH2_I_MSK 0xffff0000
++#define RX_PACKET_LENGTH2_SFT 0
++#define RX_PACKET_LENGTH2_HI 15
++#define RX_PACKET_LENGTH2_SZ 16
++#define RX_INT1_MSK 0x00010000
++#define RX_INT1_I_MSK 0xfffeffff
++#define RX_INT1_SFT 16
++#define RX_INT1_HI 16
++#define RX_INT1_SZ 1
++#define TX_DONE_MSK 0x00020000
++#define TX_DONE_I_MSK 0xfffdffff
++#define TX_DONE_SFT 17
++#define TX_DONE_HI 17
++#define TX_DONE_SZ 1
++#define HCI_TRX_FINISH_MSK 0x00040000
++#define HCI_TRX_FINISH_I_MSK 0xfffbffff
++#define HCI_TRX_FINISH_SFT 18
++#define HCI_TRX_FINISH_HI 18
++#define HCI_TRX_FINISH_SZ 1
++#define ALLOCATE_STATUS_MSK 0x00080000
++#define ALLOCATE_STATUS_I_MSK 0xfff7ffff
++#define ALLOCATE_STATUS_SFT 19
++#define ALLOCATE_STATUS_HI 19
++#define ALLOCATE_STATUS_SZ 1
++#define HCI_INPUT_FF_CNT_MSK 0x00f00000
++#define HCI_INPUT_FF_CNT_I_MSK 0xff0fffff
++#define HCI_INPUT_FF_CNT_SFT 20
++#define HCI_INPUT_FF_CNT_HI 23
++#define HCI_INPUT_FF_CNT_SZ 4
++#define HCI_OUTPUT_FF_CNT_MSK 0x1f000000
++#define HCI_OUTPUT_FF_CNT_I_MSK 0xe0ffffff
++#define HCI_OUTPUT_FF_CNT_SFT 24
++#define HCI_OUTPUT_FF_CNT_HI 28
++#define HCI_OUTPUT_FF_CNT_SZ 5
++#define AHB_HANG4_MSK 0x20000000
++#define AHB_HANG4_I_MSK 0xdfffffff
++#define AHB_HANG4_SFT 29
++#define AHB_HANG4_HI 29
++#define AHB_HANG4_SZ 1
++#define HCI_IN_QUE_EMPTY_MSK 0x40000000
++#define HCI_IN_QUE_EMPTY_I_MSK 0xbfffffff
++#define HCI_IN_QUE_EMPTY_SFT 30
++#define HCI_IN_QUE_EMPTY_HI 30
++#define HCI_IN_QUE_EMPTY_SZ 1
++#define SYSTEM_INT_MSK 0x80000000
++#define SYSTEM_INT_I_MSK 0x7fffffff
++#define SYSTEM_INT_SFT 31
++#define SYSTEM_INT_HI 31
++#define SYSTEM_INT_SZ 1
++#define CARD_RCA_REG_MSK 0x0000ffff
++#define CARD_RCA_REG_I_MSK 0xffff0000
++#define CARD_RCA_REG_SFT 0
++#define CARD_RCA_REG_HI 15
++#define CARD_RCA_REG_SZ 16
++#define SDIO_FIFO_WR_THLD_REG_MSK 0x000001ff
++#define SDIO_FIFO_WR_THLD_REG_I_MSK 0xfffffe00
++#define SDIO_FIFO_WR_THLD_REG_SFT 0
++#define SDIO_FIFO_WR_THLD_REG_HI 8
++#define SDIO_FIFO_WR_THLD_REG_SZ 9
++#define SDIO_FIFO_WR_LIMIT_REG_MSK 0x000001ff
++#define SDIO_FIFO_WR_LIMIT_REG_I_MSK 0xfffffe00
++#define SDIO_FIFO_WR_LIMIT_REG_SFT 0
++#define SDIO_FIFO_WR_LIMIT_REG_HI 8
++#define SDIO_FIFO_WR_LIMIT_REG_SZ 9
++#define SDIO_TX_DATA_BATCH_SIZE_REG_MSK 0x000001ff
++#define SDIO_TX_DATA_BATCH_SIZE_REG_I_MSK 0xfffffe00
++#define SDIO_TX_DATA_BATCH_SIZE_REG_SFT 0
++#define SDIO_TX_DATA_BATCH_SIZE_REG_HI 8
++#define SDIO_TX_DATA_BATCH_SIZE_REG_SZ 9
++#define SDIO_THLD_FOR_CMD53RD_REG_MSK 0x000001ff
++#define SDIO_THLD_FOR_CMD53RD_REG_I_MSK 0xfffffe00
++#define SDIO_THLD_FOR_CMD53RD_REG_SFT 0
++#define SDIO_THLD_FOR_CMD53RD_REG_HI 8
++#define SDIO_THLD_FOR_CMD53RD_REG_SZ 9
++#define SDIO_RX_DATA_BATCH_SIZE_REG_MSK 0x000001ff
++#define SDIO_RX_DATA_BATCH_SIZE_REG_I_MSK 0xfffffe00
++#define SDIO_RX_DATA_BATCH_SIZE_REG_SFT 0
++#define SDIO_RX_DATA_BATCH_SIZE_REG_HI 8
++#define SDIO_RX_DATA_BATCH_SIZE_REG_SZ 9
++#define START_BYTE_VALUE_MSK 0x000000ff
++#define START_BYTE_VALUE_I_MSK 0xffffff00
++#define START_BYTE_VALUE_SFT 0
++#define START_BYTE_VALUE_HI 7
++#define START_BYTE_VALUE_SZ 8
++#define END_BYTE_VALUE_MSK 0x0000ff00
++#define END_BYTE_VALUE_I_MSK 0xffff00ff
++#define END_BYTE_VALUE_SFT 8
++#define END_BYTE_VALUE_HI 15
++#define END_BYTE_VALUE_SZ 8
++#define SDIO_BYTE_MODE_BATCH_SIZE_REG_MSK 0x000000ff
++#define SDIO_BYTE_MODE_BATCH_SIZE_REG_I_MSK 0xffffff00
++#define SDIO_BYTE_MODE_BATCH_SIZE_REG_SFT 0
++#define SDIO_BYTE_MODE_BATCH_SIZE_REG_HI 7
++#define SDIO_BYTE_MODE_BATCH_SIZE_REG_SZ 8
++#define SDIO_LAST_CMD_INDEX_REG_MSK 0x0000003f
++#define SDIO_LAST_CMD_INDEX_REG_I_MSK 0xffffffc0
++#define SDIO_LAST_CMD_INDEX_REG_SFT 0
++#define SDIO_LAST_CMD_INDEX_REG_HI 5
++#define SDIO_LAST_CMD_INDEX_REG_SZ 6
++#define SDIO_LAST_CMD_CRC_REG_MSK 0x00007f00
++#define SDIO_LAST_CMD_CRC_REG_I_MSK 0xffff80ff
++#define SDIO_LAST_CMD_CRC_REG_SFT 8
++#define SDIO_LAST_CMD_CRC_REG_HI 14
++#define SDIO_LAST_CMD_CRC_REG_SZ 7
++#define SDIO_LAST_CMD_ARG_REG_MSK 0xffffffff
++#define SDIO_LAST_CMD_ARG_REG_I_MSK 0x00000000
++#define SDIO_LAST_CMD_ARG_REG_SFT 0
++#define SDIO_LAST_CMD_ARG_REG_HI 31
++#define SDIO_LAST_CMD_ARG_REG_SZ 32
++#define SDIO_BUS_STATE_REG_MSK 0x0000001f
++#define SDIO_BUS_STATE_REG_I_MSK 0xffffffe0
++#define SDIO_BUS_STATE_REG_SFT 0
++#define SDIO_BUS_STATE_REG_HI 4
++#define SDIO_BUS_STATE_REG_SZ 5
++#define SDIO_BUSY_LONG_CNT_MSK 0xffff0000
++#define SDIO_BUSY_LONG_CNT_I_MSK 0x0000ffff
++#define SDIO_BUSY_LONG_CNT_SFT 16
++#define SDIO_BUSY_LONG_CNT_HI 31
++#define SDIO_BUSY_LONG_CNT_SZ 16
++#define SDIO_CARD_STATUS_REG_MSK 0xffffffff
++#define SDIO_CARD_STATUS_REG_I_MSK 0x00000000
++#define SDIO_CARD_STATUS_REG_SFT 0
++#define SDIO_CARD_STATUS_REG_HI 31
++#define SDIO_CARD_STATUS_REG_SZ 32
++#define R5_RESPONSE_FLAG_MSK 0x000000ff
++#define R5_RESPONSE_FLAG_I_MSK 0xffffff00
++#define R5_RESPONSE_FLAG_SFT 0
++#define R5_RESPONSE_FLAG_HI 7
++#define R5_RESPONSE_FLAG_SZ 8
++#define RESP_OUT_EDGE_MSK 0x00000100
++#define RESP_OUT_EDGE_I_MSK 0xfffffeff
++#define RESP_OUT_EDGE_SFT 8
++#define RESP_OUT_EDGE_HI 8
++#define RESP_OUT_EDGE_SZ 1
++#define DAT_OUT_EDGE_MSK 0x00000200
++#define DAT_OUT_EDGE_I_MSK 0xfffffdff
++#define DAT_OUT_EDGE_SFT 9
++#define DAT_OUT_EDGE_HI 9
++#define DAT_OUT_EDGE_SZ 1
++#define MCU_TO_SDIO_INFO_MASK_MSK 0x00010000
++#define MCU_TO_SDIO_INFO_MASK_I_MSK 0xfffeffff
++#define MCU_TO_SDIO_INFO_MASK_SFT 16
++#define MCU_TO_SDIO_INFO_MASK_HI 16
++#define MCU_TO_SDIO_INFO_MASK_SZ 1
++#define INT_THROUGH_PIN_MSK 0x00020000
++#define INT_THROUGH_PIN_I_MSK 0xfffdffff
++#define INT_THROUGH_PIN_SFT 17
++#define INT_THROUGH_PIN_HI 17
++#define INT_THROUGH_PIN_SZ 1
++#define WRITE_DATA_MSK 0x000000ff
++#define WRITE_DATA_I_MSK 0xffffff00
++#define WRITE_DATA_SFT 0
++#define WRITE_DATA_HI 7
++#define WRITE_DATA_SZ 8
++#define WRITE_ADDRESS_MSK 0x0000ff00
++#define WRITE_ADDRESS_I_MSK 0xffff00ff
++#define WRITE_ADDRESS_SFT 8
++#define WRITE_ADDRESS_HI 15
++#define WRITE_ADDRESS_SZ 8
++#define READ_DATA_MSK 0x00ff0000
++#define READ_DATA_I_MSK 0xff00ffff
++#define READ_DATA_SFT 16
++#define READ_DATA_HI 23
++#define READ_DATA_SZ 8
++#define READ_ADDRESS_MSK 0xff000000
++#define READ_ADDRESS_I_MSK 0x00ffffff
++#define READ_ADDRESS_SFT 24
++#define READ_ADDRESS_HI 31
++#define READ_ADDRESS_SZ 8
++#define FN1_DMA_START_ADDR_REG_MSK 0xffffffff
++#define FN1_DMA_START_ADDR_REG_I_MSK 0x00000000
++#define FN1_DMA_START_ADDR_REG_SFT 0
++#define FN1_DMA_START_ADDR_REG_HI 31
++#define FN1_DMA_START_ADDR_REG_SZ 32
++#define SDIO_TO_MCU_INFO_MSK 0x000000ff
++#define SDIO_TO_MCU_INFO_I_MSK 0xffffff00
++#define SDIO_TO_MCU_INFO_SFT 0
++#define SDIO_TO_MCU_INFO_HI 7
++#define SDIO_TO_MCU_INFO_SZ 8
++#define SDIO_PARTIAL_RESET_MSK 0x00000100
++#define SDIO_PARTIAL_RESET_I_MSK 0xfffffeff
++#define SDIO_PARTIAL_RESET_SFT 8
++#define SDIO_PARTIAL_RESET_HI 8
++#define SDIO_PARTIAL_RESET_SZ 1
++#define SDIO_ALL_RESET_MSK 0x00000200
++#define SDIO_ALL_RESET_I_MSK 0xfffffdff
++#define SDIO_ALL_RESET_SFT 9
++#define SDIO_ALL_RESET_HI 9
++#define SDIO_ALL_RESET_SZ 1
++#define PERI_MAC_ALL_RESET_MSK 0x00000400
++#define PERI_MAC_ALL_RESET_I_MSK 0xfffffbff
++#define PERI_MAC_ALL_RESET_SFT 10
++#define PERI_MAC_ALL_RESET_HI 10
++#define PERI_MAC_ALL_RESET_SZ 1
++#define MAC_ALL_RESET_MSK 0x00000800
++#define MAC_ALL_RESET_I_MSK 0xfffff7ff
++#define MAC_ALL_RESET_SFT 11
++#define MAC_ALL_RESET_HI 11
++#define MAC_ALL_RESET_SZ 1
++#define AHB_BRIDGE_RESET_MSK 0x00001000
++#define AHB_BRIDGE_RESET_I_MSK 0xffffefff
++#define AHB_BRIDGE_RESET_SFT 12
++#define AHB_BRIDGE_RESET_HI 12
++#define AHB_BRIDGE_RESET_SZ 1
++#define IO_REG_PORT_REG_MSK 0x0001ffff
++#define IO_REG_PORT_REG_I_MSK 0xfffe0000
++#define IO_REG_PORT_REG_SFT 0
++#define IO_REG_PORT_REG_HI 16
++#define IO_REG_PORT_REG_SZ 17
++#define SDIO_FIFO_EMPTY_CNT_MSK 0x0000ffff
++#define SDIO_FIFO_EMPTY_CNT_I_MSK 0xffff0000
++#define SDIO_FIFO_EMPTY_CNT_SFT 0
++#define SDIO_FIFO_EMPTY_CNT_HI 15
++#define SDIO_FIFO_EMPTY_CNT_SZ 16
++#define SDIO_FIFO_FULL_CNT_MSK 0xffff0000
++#define SDIO_FIFO_FULL_CNT_I_MSK 0x0000ffff
++#define SDIO_FIFO_FULL_CNT_SFT 16
++#define SDIO_FIFO_FULL_CNT_HI 31
++#define SDIO_FIFO_FULL_CNT_SZ 16
++#define SDIO_CRC7_ERROR_CNT_MSK 0x0000ffff
++#define SDIO_CRC7_ERROR_CNT_I_MSK 0xffff0000
++#define SDIO_CRC7_ERROR_CNT_SFT 0
++#define SDIO_CRC7_ERROR_CNT_HI 15
++#define SDIO_CRC7_ERROR_CNT_SZ 16
++#define SDIO_CRC16_ERROR_CNT_MSK 0xffff0000
++#define SDIO_CRC16_ERROR_CNT_I_MSK 0x0000ffff
++#define SDIO_CRC16_ERROR_CNT_SFT 16
++#define SDIO_CRC16_ERROR_CNT_HI 31
++#define SDIO_CRC16_ERROR_CNT_SZ 16
++#define SDIO_RD_BLOCK_CNT_MSK 0x000001ff
++#define SDIO_RD_BLOCK_CNT_I_MSK 0xfffffe00
++#define SDIO_RD_BLOCK_CNT_SFT 0
++#define SDIO_RD_BLOCK_CNT_HI 8
++#define SDIO_RD_BLOCK_CNT_SZ 9
++#define SDIO_WR_BLOCK_CNT_MSK 0x01ff0000
++#define SDIO_WR_BLOCK_CNT_I_MSK 0xfe00ffff
++#define SDIO_WR_BLOCK_CNT_SFT 16
++#define SDIO_WR_BLOCK_CNT_HI 24
++#define SDIO_WR_BLOCK_CNT_SZ 9
++#define CMD52_RD_ABORT_CNT_MSK 0x000f0000
++#define CMD52_RD_ABORT_CNT_I_MSK 0xfff0ffff
++#define CMD52_RD_ABORT_CNT_SFT 16
++#define CMD52_RD_ABORT_CNT_HI 19
++#define CMD52_RD_ABORT_CNT_SZ 4
++#define CMD52_WR_ABORT_CNT_MSK 0x00f00000
++#define CMD52_WR_ABORT_CNT_I_MSK 0xff0fffff
++#define CMD52_WR_ABORT_CNT_SFT 20
++#define CMD52_WR_ABORT_CNT_HI 23
++#define CMD52_WR_ABORT_CNT_SZ 4
++#define SDIO_FIFO_WR_PTR_REG_MSK 0x000000ff
++#define SDIO_FIFO_WR_PTR_REG_I_MSK 0xffffff00
++#define SDIO_FIFO_WR_PTR_REG_SFT 0
++#define SDIO_FIFO_WR_PTR_REG_HI 7
++#define SDIO_FIFO_WR_PTR_REG_SZ 8
++#define SDIO_FIFO_RD_PTR_REG_MSK 0x0000ff00
++#define SDIO_FIFO_RD_PTR_REG_I_MSK 0xffff00ff
++#define SDIO_FIFO_RD_PTR_REG_SFT 8
++#define SDIO_FIFO_RD_PTR_REG_HI 15
++#define SDIO_FIFO_RD_PTR_REG_SZ 8
++#define SDIO_READ_DATA_CTRL_MSK 0x00010000
++#define SDIO_READ_DATA_CTRL_I_MSK 0xfffeffff
++#define SDIO_READ_DATA_CTRL_SFT 16
++#define SDIO_READ_DATA_CTRL_HI 16
++#define SDIO_READ_DATA_CTRL_SZ 1
++#define TX_SIZE_BEFORE_SHIFT_MSK 0x000000ff
++#define TX_SIZE_BEFORE_SHIFT_I_MSK 0xffffff00
++#define TX_SIZE_BEFORE_SHIFT_SFT 0
++#define TX_SIZE_BEFORE_SHIFT_HI 7
++#define TX_SIZE_BEFORE_SHIFT_SZ 8
++#define TX_SIZE_SHIFT_BITS_MSK 0x00000700
++#define TX_SIZE_SHIFT_BITS_I_MSK 0xfffff8ff
++#define TX_SIZE_SHIFT_BITS_SFT 8
++#define TX_SIZE_SHIFT_BITS_HI 10
++#define TX_SIZE_SHIFT_BITS_SZ 3
++#define SDIO_TX_ALLOC_STATE_MSK 0x00001000
++#define SDIO_TX_ALLOC_STATE_I_MSK 0xffffefff
++#define SDIO_TX_ALLOC_STATE_SFT 12
++#define SDIO_TX_ALLOC_STATE_HI 12
++#define SDIO_TX_ALLOC_STATE_SZ 1
++#define ALLOCATE_STATUS2_MSK 0x00010000
++#define ALLOCATE_STATUS2_I_MSK 0xfffeffff
++#define ALLOCATE_STATUS2_SFT 16
++#define ALLOCATE_STATUS2_HI 16
++#define ALLOCATE_STATUS2_SZ 1
++#define NO_ALLOCATE_SEND_ERROR_MSK 0x00020000
++#define NO_ALLOCATE_SEND_ERROR_I_MSK 0xfffdffff
++#define NO_ALLOCATE_SEND_ERROR_SFT 17
++#define NO_ALLOCATE_SEND_ERROR_HI 17
++#define NO_ALLOCATE_SEND_ERROR_SZ 1
++#define DOUBLE_ALLOCATE_ERROR_MSK 0x00040000
++#define DOUBLE_ALLOCATE_ERROR_I_MSK 0xfffbffff
++#define DOUBLE_ALLOCATE_ERROR_SFT 18
++#define DOUBLE_ALLOCATE_ERROR_HI 18
++#define DOUBLE_ALLOCATE_ERROR_SZ 1
++#define TX_DONE_STATUS_MSK 0x00080000
++#define TX_DONE_STATUS_I_MSK 0xfff7ffff
++#define TX_DONE_STATUS_SFT 19
++#define TX_DONE_STATUS_HI 19
++#define TX_DONE_STATUS_SZ 1
++#define AHB_HANG2_MSK 0x00100000
++#define AHB_HANG2_I_MSK 0xffefffff
++#define AHB_HANG2_SFT 20
++#define AHB_HANG2_HI 20
++#define AHB_HANG2_SZ 1
++#define HCI_TRX_FINISH2_MSK 0x00200000
++#define HCI_TRX_FINISH2_I_MSK 0xffdfffff
++#define HCI_TRX_FINISH2_SFT 21
++#define HCI_TRX_FINISH2_HI 21
++#define HCI_TRX_FINISH2_SZ 1
++#define INTR_RX_MSK 0x00400000
++#define INTR_RX_I_MSK 0xffbfffff
++#define INTR_RX_SFT 22
++#define INTR_RX_HI 22
++#define INTR_RX_SZ 1
++#define HCI_INPUT_QUEUE_FULL_MSK 0x00800000
++#define HCI_INPUT_QUEUE_FULL_I_MSK 0xff7fffff
++#define HCI_INPUT_QUEUE_FULL_SFT 23
++#define HCI_INPUT_QUEUE_FULL_HI 23
++#define HCI_INPUT_QUEUE_FULL_SZ 1
++#define ALLOCATESTATUS_MSK 0x00000001
++#define ALLOCATESTATUS_I_MSK 0xfffffffe
++#define ALLOCATESTATUS_SFT 0
++#define ALLOCATESTATUS_HI 0
++#define ALLOCATESTATUS_SZ 1
++#define HCI_TRX_FINISH3_MSK 0x00000002
++#define HCI_TRX_FINISH3_I_MSK 0xfffffffd
++#define HCI_TRX_FINISH3_SFT 1
++#define HCI_TRX_FINISH3_HI 1
++#define HCI_TRX_FINISH3_SZ 1
++#define HCI_IN_QUE_EMPTY2_MSK 0x00000004
++#define HCI_IN_QUE_EMPTY2_I_MSK 0xfffffffb
++#define HCI_IN_QUE_EMPTY2_SFT 2
++#define HCI_IN_QUE_EMPTY2_HI 2
++#define HCI_IN_QUE_EMPTY2_SZ 1
++#define MTX_MNG_UPTHOLD_INT_MSK 0x00000008
++#define MTX_MNG_UPTHOLD_INT_I_MSK 0xfffffff7
++#define MTX_MNG_UPTHOLD_INT_SFT 3
++#define MTX_MNG_UPTHOLD_INT_HI 3
++#define MTX_MNG_UPTHOLD_INT_SZ 1
++#define EDCA0_UPTHOLD_INT_MSK 0x00000010
++#define EDCA0_UPTHOLD_INT_I_MSK 0xffffffef
++#define EDCA0_UPTHOLD_INT_SFT 4
++#define EDCA0_UPTHOLD_INT_HI 4
++#define EDCA0_UPTHOLD_INT_SZ 1
++#define EDCA1_UPTHOLD_INT_MSK 0x00000020
++#define EDCA1_UPTHOLD_INT_I_MSK 0xffffffdf
++#define EDCA1_UPTHOLD_INT_SFT 5
++#define EDCA1_UPTHOLD_INT_HI 5
++#define EDCA1_UPTHOLD_INT_SZ 1
++#define EDCA2_UPTHOLD_INT_MSK 0x00000040
++#define EDCA2_UPTHOLD_INT_I_MSK 0xffffffbf
++#define EDCA2_UPTHOLD_INT_SFT 6
++#define EDCA2_UPTHOLD_INT_HI 6
++#define EDCA2_UPTHOLD_INT_SZ 1
++#define EDCA3_UPTHOLD_INT_MSK 0x00000080
++#define EDCA3_UPTHOLD_INT_I_MSK 0xffffff7f
++#define EDCA3_UPTHOLD_INT_SFT 7
++#define EDCA3_UPTHOLD_INT_HI 7
++#define EDCA3_UPTHOLD_INT_SZ 1
++#define TX_PAGE_REMAIN2_MSK 0x0000ff00
++#define TX_PAGE_REMAIN2_I_MSK 0xffff00ff
++#define TX_PAGE_REMAIN2_SFT 8
++#define TX_PAGE_REMAIN2_HI 15
++#define TX_PAGE_REMAIN2_SZ 8
++#define TX_ID_REMAIN3_MSK 0x007f0000
++#define TX_ID_REMAIN3_I_MSK 0xff80ffff
++#define TX_ID_REMAIN3_SFT 16
++#define TX_ID_REMAIN3_HI 22
++#define TX_ID_REMAIN3_SZ 7
++#define HCI_OUTPUT_FF_CNT_0_MSK 0x00800000
++#define HCI_OUTPUT_FF_CNT_0_I_MSK 0xff7fffff
++#define HCI_OUTPUT_FF_CNT_0_SFT 23
++#define HCI_OUTPUT_FF_CNT_0_HI 23
++#define HCI_OUTPUT_FF_CNT_0_SZ 1
++#define HCI_OUTPUT_FF_CNT2_MSK 0x0f000000
++#define HCI_OUTPUT_FF_CNT2_I_MSK 0xf0ffffff
++#define HCI_OUTPUT_FF_CNT2_SFT 24
++#define HCI_OUTPUT_FF_CNT2_HI 27
++#define HCI_OUTPUT_FF_CNT2_SZ 4
++#define HCI_INPUT_FF_CNT2_MSK 0xf0000000
++#define HCI_INPUT_FF_CNT2_I_MSK 0x0fffffff
++#define HCI_INPUT_FF_CNT2_SFT 28
++#define HCI_INPUT_FF_CNT2_HI 31
++#define HCI_INPUT_FF_CNT2_SZ 4
++#define F1_BLOCK_SIZE_0_REG_MSK 0x00000fff
++#define F1_BLOCK_SIZE_0_REG_I_MSK 0xfffff000
++#define F1_BLOCK_SIZE_0_REG_SFT 0
++#define F1_BLOCK_SIZE_0_REG_HI 11
++#define F1_BLOCK_SIZE_0_REG_SZ 12
++#define START_BYTE_VALUE2_MSK 0x000000ff
++#define START_BYTE_VALUE2_I_MSK 0xffffff00
++#define START_BYTE_VALUE2_SFT 0
++#define START_BYTE_VALUE2_HI 7
++#define START_BYTE_VALUE2_SZ 8
++#define COMMAND_COUNTER_MSK 0x0000ff00
++#define COMMAND_COUNTER_I_MSK 0xffff00ff
++#define COMMAND_COUNTER_SFT 8
++#define COMMAND_COUNTER_HI 15
++#define COMMAND_COUNTER_SZ 8
++#define CMD_LOG_PART1_MSK 0xffff0000
++#define CMD_LOG_PART1_I_MSK 0x0000ffff
++#define CMD_LOG_PART1_SFT 16
++#define CMD_LOG_PART1_HI 31
++#define CMD_LOG_PART1_SZ 16
++#define CMD_LOG_PART2_MSK 0x00ffffff
++#define CMD_LOG_PART2_I_MSK 0xff000000
++#define CMD_LOG_PART2_SFT 0
++#define CMD_LOG_PART2_HI 23
++#define CMD_LOG_PART2_SZ 24
++#define END_BYTE_VALUE2_MSK 0xff000000
++#define END_BYTE_VALUE2_I_MSK 0x00ffffff
++#define END_BYTE_VALUE2_SFT 24
++#define END_BYTE_VALUE2_HI 31
++#define END_BYTE_VALUE2_SZ 8
++#define RX_PACKET_LENGTH3_MSK 0x0000ffff
++#define RX_PACKET_LENGTH3_I_MSK 0xffff0000
++#define RX_PACKET_LENGTH3_SFT 0
++#define RX_PACKET_LENGTH3_HI 15
++#define RX_PACKET_LENGTH3_SZ 16
++#define RX_INT3_MSK 0x00010000
++#define RX_INT3_I_MSK 0xfffeffff
++#define RX_INT3_SFT 16
++#define RX_INT3_HI 16
++#define RX_INT3_SZ 1
++#define TX_ID_REMAIN2_MSK 0x00fe0000
++#define TX_ID_REMAIN2_I_MSK 0xff01ffff
++#define TX_ID_REMAIN2_SFT 17
++#define TX_ID_REMAIN2_HI 23
++#define TX_ID_REMAIN2_SZ 7
++#define TX_PAGE_REMAIN3_MSK 0xff000000
++#define TX_PAGE_REMAIN3_I_MSK 0x00ffffff
++#define TX_PAGE_REMAIN3_SFT 24
++#define TX_PAGE_REMAIN3_HI 31
++#define TX_PAGE_REMAIN3_SZ 8
++#define CCCR_00H_REG_MSK 0x000000ff
++#define CCCR_00H_REG_I_MSK 0xffffff00
++#define CCCR_00H_REG_SFT 0
++#define CCCR_00H_REG_HI 7
++#define CCCR_00H_REG_SZ 8
++#define CCCR_02H_REG_MSK 0x00ff0000
++#define CCCR_02H_REG_I_MSK 0xff00ffff
++#define CCCR_02H_REG_SFT 16
++#define CCCR_02H_REG_HI 23
++#define CCCR_02H_REG_SZ 8
++#define CCCR_03H_REG_MSK 0xff000000
++#define CCCR_03H_REG_I_MSK 0x00ffffff
++#define CCCR_03H_REG_SFT 24
++#define CCCR_03H_REG_HI 31
++#define CCCR_03H_REG_SZ 8
++#define CCCR_04H_REG_MSK 0x000000ff
++#define CCCR_04H_REG_I_MSK 0xffffff00
++#define CCCR_04H_REG_SFT 0
++#define CCCR_04H_REG_HI 7
++#define CCCR_04H_REG_SZ 8
++#define CCCR_05H_REG_MSK 0x0000ff00
++#define CCCR_05H_REG_I_MSK 0xffff00ff
++#define CCCR_05H_REG_SFT 8
++#define CCCR_05H_REG_HI 15
++#define CCCR_05H_REG_SZ 8
++#define CCCR_06H_REG_MSK 0x000f0000
++#define CCCR_06H_REG_I_MSK 0xfff0ffff
++#define CCCR_06H_REG_SFT 16
++#define CCCR_06H_REG_HI 19
++#define CCCR_06H_REG_SZ 4
++#define CCCR_07H_REG_MSK 0xff000000
++#define CCCR_07H_REG_I_MSK 0x00ffffff
++#define CCCR_07H_REG_SFT 24
++#define CCCR_07H_REG_HI 31
++#define CCCR_07H_REG_SZ 8
++#define SUPPORT_DIRECT_COMMAND_SDIO_MSK 0x00000001
++#define SUPPORT_DIRECT_COMMAND_SDIO_I_MSK 0xfffffffe
++#define SUPPORT_DIRECT_COMMAND_SDIO_SFT 0
++#define SUPPORT_DIRECT_COMMAND_SDIO_HI 0
++#define SUPPORT_DIRECT_COMMAND_SDIO_SZ 1
++#define SUPPORT_MULTIPLE_BLOCK_TRANSFER_MSK 0x00000002
++#define SUPPORT_MULTIPLE_BLOCK_TRANSFER_I_MSK 0xfffffffd
++#define SUPPORT_MULTIPLE_BLOCK_TRANSFER_SFT 1
++#define SUPPORT_MULTIPLE_BLOCK_TRANSFER_HI 1
++#define SUPPORT_MULTIPLE_BLOCK_TRANSFER_SZ 1
++#define SUPPORT_READ_WAIT_MSK 0x00000004
++#define SUPPORT_READ_WAIT_I_MSK 0xfffffffb
++#define SUPPORT_READ_WAIT_SFT 2
++#define SUPPORT_READ_WAIT_HI 2
++#define SUPPORT_READ_WAIT_SZ 1
++#define SUPPORT_BUS_CONTROL_MSK 0x00000008
++#define SUPPORT_BUS_CONTROL_I_MSK 0xfffffff7
++#define SUPPORT_BUS_CONTROL_SFT 3
++#define SUPPORT_BUS_CONTROL_HI 3
++#define SUPPORT_BUS_CONTROL_SZ 1
++#define SUPPORT_BLOCK_GAP_INTERRUPT_MSK 0x00000010
++#define SUPPORT_BLOCK_GAP_INTERRUPT_I_MSK 0xffffffef
++#define SUPPORT_BLOCK_GAP_INTERRUPT_SFT 4
++#define SUPPORT_BLOCK_GAP_INTERRUPT_HI 4
++#define SUPPORT_BLOCK_GAP_INTERRUPT_SZ 1
++#define ENABLE_BLOCK_GAP_INTERRUPT_MSK 0x00000020
++#define ENABLE_BLOCK_GAP_INTERRUPT_I_MSK 0xffffffdf
++#define ENABLE_BLOCK_GAP_INTERRUPT_SFT 5
++#define ENABLE_BLOCK_GAP_INTERRUPT_HI 5
++#define ENABLE_BLOCK_GAP_INTERRUPT_SZ 1
++#define LOW_SPEED_CARD_MSK 0x00000040
++#define LOW_SPEED_CARD_I_MSK 0xffffffbf
++#define LOW_SPEED_CARD_SFT 6
++#define LOW_SPEED_CARD_HI 6
++#define LOW_SPEED_CARD_SZ 1
++#define LOW_SPEED_CARD_4BIT_MSK 0x00000080
++#define LOW_SPEED_CARD_4BIT_I_MSK 0xffffff7f
++#define LOW_SPEED_CARD_4BIT_SFT 7
++#define LOW_SPEED_CARD_4BIT_HI 7
++#define LOW_SPEED_CARD_4BIT_SZ 1
++#define COMMON_CIS_PONTER_MSK 0x01ffff00
++#define COMMON_CIS_PONTER_I_MSK 0xfe0000ff
++#define COMMON_CIS_PONTER_SFT 8
++#define COMMON_CIS_PONTER_HI 24
++#define COMMON_CIS_PONTER_SZ 17
++#define SUPPORT_HIGH_SPEED_MSK 0x01000000
++#define SUPPORT_HIGH_SPEED_I_MSK 0xfeffffff
++#define SUPPORT_HIGH_SPEED_SFT 24
++#define SUPPORT_HIGH_SPEED_HI 24
++#define SUPPORT_HIGH_SPEED_SZ 1
++#define BSS_MSK 0x0e000000
++#define BSS_I_MSK 0xf1ffffff
++#define BSS_SFT 25
++#define BSS_HI 27
++#define BSS_SZ 3
++#define FBR_100H_REG_MSK 0x0000000f
++#define FBR_100H_REG_I_MSK 0xfffffff0
++#define FBR_100H_REG_SFT 0
++#define FBR_100H_REG_HI 3
++#define FBR_100H_REG_SZ 4
++#define CSASUPPORT_MSK 0x00000040
++#define CSASUPPORT_I_MSK 0xffffffbf
++#define CSASUPPORT_SFT 6
++#define CSASUPPORT_HI 6
++#define CSASUPPORT_SZ 1
++#define ENABLECSA_MSK 0x00000080
++#define ENABLECSA_I_MSK 0xffffff7f
++#define ENABLECSA_SFT 7
++#define ENABLECSA_HI 7
++#define ENABLECSA_SZ 1
++#define FBR_101H_REG_MSK 0x0000ff00
++#define FBR_101H_REG_I_MSK 0xffff00ff
++#define FBR_101H_REG_SFT 8
++#define FBR_101H_REG_HI 15
++#define FBR_101H_REG_SZ 8
++#define FBR_109H_REG_MSK 0x01ffff00
++#define FBR_109H_REG_I_MSK 0xfe0000ff
++#define FBR_109H_REG_SFT 8
++#define FBR_109H_REG_HI 24
++#define FBR_109H_REG_SZ 17
++#define F0_CIS_CONTENT_REG_31_0_MSK 0xffffffff
++#define F0_CIS_CONTENT_REG_31_0_I_MSK 0x00000000
++#define F0_CIS_CONTENT_REG_31_0_SFT 0
++#define F0_CIS_CONTENT_REG_31_0_HI 31
++#define F0_CIS_CONTENT_REG_31_0_SZ 32
++#define F0_CIS_CONTENT_REG_63_32_MSK 0xffffffff
++#define F0_CIS_CONTENT_REG_63_32_I_MSK 0x00000000
++#define F0_CIS_CONTENT_REG_63_32_SFT 0
++#define F0_CIS_CONTENT_REG_63_32_HI 31
++#define F0_CIS_CONTENT_REG_63_32_SZ 32
++#define F0_CIS_CONTENT_REG_95_64_MSK 0xffffffff
++#define F0_CIS_CONTENT_REG_95_64_I_MSK 0x00000000
++#define F0_CIS_CONTENT_REG_95_64_SFT 0
++#define F0_CIS_CONTENT_REG_95_64_HI 31
++#define F0_CIS_CONTENT_REG_95_64_SZ 32
++#define F0_CIS_CONTENT_REG_127_96_MSK 0xffffffff
++#define F0_CIS_CONTENT_REG_127_96_I_MSK 0x00000000
++#define F0_CIS_CONTENT_REG_127_96_SFT 0
++#define F0_CIS_CONTENT_REG_127_96_HI 31
++#define F0_CIS_CONTENT_REG_127_96_SZ 32
++#define F0_CIS_CONTENT_REG_159_128_MSK 0xffffffff
++#define F0_CIS_CONTENT_REG_159_128_I_MSK 0x00000000
++#define F0_CIS_CONTENT_REG_159_128_SFT 0
++#define F0_CIS_CONTENT_REG_159_128_HI 31
++#define F0_CIS_CONTENT_REG_159_128_SZ 32
++#define F0_CIS_CONTENT_REG_191_160_MSK 0xffffffff
++#define F0_CIS_CONTENT_REG_191_160_I_MSK 0x00000000
++#define F0_CIS_CONTENT_REG_191_160_SFT 0
++#define F0_CIS_CONTENT_REG_191_160_HI 31
++#define F0_CIS_CONTENT_REG_191_160_SZ 32
++#define F0_CIS_CONTENT_REG_223_192_MSK 0xffffffff
++#define F0_CIS_CONTENT_REG_223_192_I_MSK 0x00000000
++#define F0_CIS_CONTENT_REG_223_192_SFT 0
++#define F0_CIS_CONTENT_REG_223_192_HI 31
++#define F0_CIS_CONTENT_REG_223_192_SZ 32
++#define F0_CIS_CONTENT_REG_255_224_MSK 0xffffffff
++#define F0_CIS_CONTENT_REG_255_224_I_MSK 0x00000000
++#define F0_CIS_CONTENT_REG_255_224_SFT 0
++#define F0_CIS_CONTENT_REG_255_224_HI 31
++#define F0_CIS_CONTENT_REG_255_224_SZ 32
++#define F0_CIS_CONTENT_REG_287_256_MSK 0xffffffff
++#define F0_CIS_CONTENT_REG_287_256_I_MSK 0x00000000
++#define F0_CIS_CONTENT_REG_287_256_SFT 0
++#define F0_CIS_CONTENT_REG_287_256_HI 31
++#define F0_CIS_CONTENT_REG_287_256_SZ 32
++#define F0_CIS_CONTENT_REG_319_288_MSK 0xffffffff
++#define F0_CIS_CONTENT_REG_319_288_I_MSK 0x00000000
++#define F0_CIS_CONTENT_REG_319_288_SFT 0
++#define F0_CIS_CONTENT_REG_319_288_HI 31
++#define F0_CIS_CONTENT_REG_319_288_SZ 32
++#define F0_CIS_CONTENT_REG_351_320_MSK 0xffffffff
++#define F0_CIS_CONTENT_REG_351_320_I_MSK 0x00000000
++#define F0_CIS_CONTENT_REG_351_320_SFT 0
++#define F0_CIS_CONTENT_REG_351_320_HI 31
++#define F0_CIS_CONTENT_REG_351_320_SZ 32
++#define F0_CIS_CONTENT_REG_383_352_MSK 0xffffffff
++#define F0_CIS_CONTENT_REG_383_352_I_MSK 0x00000000
++#define F0_CIS_CONTENT_REG_383_352_SFT 0
++#define F0_CIS_CONTENT_REG_383_352_HI 31
++#define F0_CIS_CONTENT_REG_383_352_SZ 32
++#define F0_CIS_CONTENT_REG_415_384_MSK 0xffffffff
++#define F0_CIS_CONTENT_REG_415_384_I_MSK 0x00000000
++#define F0_CIS_CONTENT_REG_415_384_SFT 0
++#define F0_CIS_CONTENT_REG_415_384_HI 31
++#define F0_CIS_CONTENT_REG_415_384_SZ 32
++#define F0_CIS_CONTENT_REG_447_416_MSK 0xffffffff
++#define F0_CIS_CONTENT_REG_447_416_I_MSK 0x00000000
++#define F0_CIS_CONTENT_REG_447_416_SFT 0
++#define F0_CIS_CONTENT_REG_447_416_HI 31
++#define F0_CIS_CONTENT_REG_447_416_SZ 32
++#define F0_CIS_CONTENT_REG_479_448_MSK 0xffffffff
++#define F0_CIS_CONTENT_REG_479_448_I_MSK 0x00000000
++#define F0_CIS_CONTENT_REG_479_448_SFT 0
++#define F0_CIS_CONTENT_REG_479_448_HI 31
++#define F0_CIS_CONTENT_REG_479_448_SZ 32
++#define F0_CIS_CONTENT_REG_511_480_MSK 0xffffffff
++#define F0_CIS_CONTENT_REG_511_480_I_MSK 0x00000000
++#define F0_CIS_CONTENT_REG_511_480_SFT 0
++#define F0_CIS_CONTENT_REG_511_480_HI 31
++#define F0_CIS_CONTENT_REG_511_480_SZ 32
++#define F1_CIS_CONTENT_REG_31_0_MSK 0xffffffff
++#define F1_CIS_CONTENT_REG_31_0_I_MSK 0x00000000
++#define F1_CIS_CONTENT_REG_31_0_SFT 0
++#define F1_CIS_CONTENT_REG_31_0_HI 31
++#define F1_CIS_CONTENT_REG_31_0_SZ 32
++#define F1_CIS_CONTENT_REG_63_32_MSK 0xffffffff
++#define F1_CIS_CONTENT_REG_63_32_I_MSK 0x00000000
++#define F1_CIS_CONTENT_REG_63_32_SFT 0
++#define F1_CIS_CONTENT_REG_63_32_HI 31
++#define F1_CIS_CONTENT_REG_63_32_SZ 32
++#define F1_CIS_CONTENT_REG_95_64_MSK 0xffffffff
++#define F1_CIS_CONTENT_REG_95_64_I_MSK 0x00000000
++#define F1_CIS_CONTENT_REG_95_64_SFT 0
++#define F1_CIS_CONTENT_REG_95_64_HI 31
++#define F1_CIS_CONTENT_REG_95_64_SZ 32
++#define F1_CIS_CONTENT_REG_127_96_MSK 0xffffffff
++#define F1_CIS_CONTENT_REG_127_96_I_MSK 0x00000000
++#define F1_CIS_CONTENT_REG_127_96_SFT 0
++#define F1_CIS_CONTENT_REG_127_96_HI 31
++#define F1_CIS_CONTENT_REG_127_96_SZ 32
++#define F1_CIS_CONTENT_REG_159_128_MSK 0xffffffff
++#define F1_CIS_CONTENT_REG_159_128_I_MSK 0x00000000
++#define F1_CIS_CONTENT_REG_159_128_SFT 0
++#define F1_CIS_CONTENT_REG_159_128_HI 31
++#define F1_CIS_CONTENT_REG_159_128_SZ 32
++#define F1_CIS_CONTENT_REG_191_160_MSK 0xffffffff
++#define F1_CIS_CONTENT_REG_191_160_I_MSK 0x00000000
++#define F1_CIS_CONTENT_REG_191_160_SFT 0
++#define F1_CIS_CONTENT_REG_191_160_HI 31
++#define F1_CIS_CONTENT_REG_191_160_SZ 32
++#define F1_CIS_CONTENT_REG_223_192_MSK 0xffffffff
++#define F1_CIS_CONTENT_REG_223_192_I_MSK 0x00000000
++#define F1_CIS_CONTENT_REG_223_192_SFT 0
++#define F1_CIS_CONTENT_REG_223_192_HI 31
++#define F1_CIS_CONTENT_REG_223_192_SZ 32
++#define F1_CIS_CONTENT_REG_255_224_MSK 0xffffffff
++#define F1_CIS_CONTENT_REG_255_224_I_MSK 0x00000000
++#define F1_CIS_CONTENT_REG_255_224_SFT 0
++#define F1_CIS_CONTENT_REG_255_224_HI 31
++#define F1_CIS_CONTENT_REG_255_224_SZ 32
++#define F1_CIS_CONTENT_REG_287_256_MSK 0xffffffff
++#define F1_CIS_CONTENT_REG_287_256_I_MSK 0x00000000
++#define F1_CIS_CONTENT_REG_287_256_SFT 0
++#define F1_CIS_CONTENT_REG_287_256_HI 31
++#define F1_CIS_CONTENT_REG_287_256_SZ 32
++#define F1_CIS_CONTENT_REG_319_288_MSK 0xffffffff
++#define F1_CIS_CONTENT_REG_319_288_I_MSK 0x00000000
++#define F1_CIS_CONTENT_REG_319_288_SFT 0
++#define F1_CIS_CONTENT_REG_319_288_HI 31
++#define F1_CIS_CONTENT_REG_319_288_SZ 32
++#define F1_CIS_CONTENT_REG_351_320_MSK 0xffffffff
++#define F1_CIS_CONTENT_REG_351_320_I_MSK 0x00000000
++#define F1_CIS_CONTENT_REG_351_320_SFT 0
++#define F1_CIS_CONTENT_REG_351_320_HI 31
++#define F1_CIS_CONTENT_REG_351_320_SZ 32
++#define F1_CIS_CONTENT_REG_383_352_MSK 0xffffffff
++#define F1_CIS_CONTENT_REG_383_352_I_MSK 0x00000000
++#define F1_CIS_CONTENT_REG_383_352_SFT 0
++#define F1_CIS_CONTENT_REG_383_352_HI 31
++#define F1_CIS_CONTENT_REG_383_352_SZ 32
++#define F1_CIS_CONTENT_REG_415_384_MSK 0xffffffff
++#define F1_CIS_CONTENT_REG_415_384_I_MSK 0x00000000
++#define F1_CIS_CONTENT_REG_415_384_SFT 0
++#define F1_CIS_CONTENT_REG_415_384_HI 31
++#define F1_CIS_CONTENT_REG_415_384_SZ 32
++#define F1_CIS_CONTENT_REG_447_416_MSK 0xffffffff
++#define F1_CIS_CONTENT_REG_447_416_I_MSK 0x00000000
++#define F1_CIS_CONTENT_REG_447_416_SFT 0
++#define F1_CIS_CONTENT_REG_447_416_HI 31
++#define F1_CIS_CONTENT_REG_447_416_SZ 32
++#define F1_CIS_CONTENT_REG_479_448_MSK 0xffffffff
++#define F1_CIS_CONTENT_REG_479_448_I_MSK 0x00000000
++#define F1_CIS_CONTENT_REG_479_448_SFT 0
++#define F1_CIS_CONTENT_REG_479_448_HI 31
++#define F1_CIS_CONTENT_REG_479_448_SZ 32
++#define F1_CIS_CONTENT_REG_511_480_MSK 0xffffffff
++#define F1_CIS_CONTENT_REG_511_480_I_MSK 0x00000000
++#define F1_CIS_CONTENT_REG_511_480_SFT 0
++#define F1_CIS_CONTENT_REG_511_480_HI 31
++#define F1_CIS_CONTENT_REG_511_480_SZ 32
++#define SPI_MODE_MSK 0xffffffff
++#define SPI_MODE_I_MSK 0x00000000
++#define SPI_MODE_SFT 0
++#define SPI_MODE_HI 31
++#define SPI_MODE_SZ 32
++#define RX_QUOTA_MSK 0x0000ffff
++#define RX_QUOTA_I_MSK 0xffff0000
++#define RX_QUOTA_SFT 0
++#define RX_QUOTA_HI 15
++#define RX_QUOTA_SZ 16
++#define CONDI_NUM_MSK 0x000000ff
++#define CONDI_NUM_I_MSK 0xffffff00
++#define CONDI_NUM_SFT 0
++#define CONDI_NUM_HI 7
++#define CONDI_NUM_SZ 8
++#define HOST_PATH_MSK 0x00000001
++#define HOST_PATH_I_MSK 0xfffffffe
++#define HOST_PATH_SFT 0
++#define HOST_PATH_HI 0
++#define HOST_PATH_SZ 1
++#define TX_SEG_MSK 0xffffffff
++#define TX_SEG_I_MSK 0x00000000
++#define TX_SEG_SFT 0
++#define TX_SEG_HI 31
++#define TX_SEG_SZ 32
++#define BRST_MODE_MSK 0x00000001
++#define BRST_MODE_I_MSK 0xfffffffe
++#define BRST_MODE_SFT 0
++#define BRST_MODE_HI 0
++#define BRST_MODE_SZ 1
++#define CLK_WIDTH_MSK 0x0000ffff
++#define CLK_WIDTH_I_MSK 0xffff0000
++#define CLK_WIDTH_SFT 0
++#define CLK_WIDTH_HI 15
++#define CLK_WIDTH_SZ 16
++#define CSN_INTER_MSK 0xffff0000
++#define CSN_INTER_I_MSK 0x0000ffff
++#define CSN_INTER_SFT 16
++#define CSN_INTER_HI 31
++#define CSN_INTER_SZ 16
++#define BACK_DLY_MSK 0x0000ffff
++#define BACK_DLY_I_MSK 0xffff0000
++#define BACK_DLY_SFT 0
++#define BACK_DLY_HI 15
++#define BACK_DLY_SZ 16
++#define FRONT_DLY_MSK 0xffff0000
++#define FRONT_DLY_I_MSK 0x0000ffff
++#define FRONT_DLY_SFT 16
++#define FRONT_DLY_HI 31
++#define FRONT_DLY_SZ 16
++#define RX_FIFO_FAIL_MSK 0x00000002
++#define RX_FIFO_FAIL_I_MSK 0xfffffffd
++#define RX_FIFO_FAIL_SFT 1
++#define RX_FIFO_FAIL_HI 1
++#define RX_FIFO_FAIL_SZ 1
++#define RX_HOST_FAIL_MSK 0x00000004
++#define RX_HOST_FAIL_I_MSK 0xfffffffb
++#define RX_HOST_FAIL_SFT 2
++#define RX_HOST_FAIL_HI 2
++#define RX_HOST_FAIL_SZ 1
++#define TX_FIFO_FAIL_MSK 0x00000008
++#define TX_FIFO_FAIL_I_MSK 0xfffffff7
++#define TX_FIFO_FAIL_SFT 3
++#define TX_FIFO_FAIL_HI 3
++#define TX_FIFO_FAIL_SZ 1
++#define TX_HOST_FAIL_MSK 0x00000010
++#define TX_HOST_FAIL_I_MSK 0xffffffef
++#define TX_HOST_FAIL_SFT 4
++#define TX_HOST_FAIL_HI 4
++#define TX_HOST_FAIL_SZ 1
++#define SPI_DOUBLE_ALLOC_MSK 0x00000020
++#define SPI_DOUBLE_ALLOC_I_MSK 0xffffffdf
++#define SPI_DOUBLE_ALLOC_SFT 5
++#define SPI_DOUBLE_ALLOC_HI 5
++#define SPI_DOUBLE_ALLOC_SZ 1
++#define SPI_TX_NO_ALLOC_MSK 0x00000040
++#define SPI_TX_NO_ALLOC_I_MSK 0xffffffbf
++#define SPI_TX_NO_ALLOC_SFT 6
++#define SPI_TX_NO_ALLOC_HI 6
++#define SPI_TX_NO_ALLOC_SZ 1
++#define RDATA_RDY_MSK 0x00000080
++#define RDATA_RDY_I_MSK 0xffffff7f
++#define RDATA_RDY_SFT 7
++#define RDATA_RDY_HI 7
++#define RDATA_RDY_SZ 1
++#define SPI_ALLOC_STATUS_MSK 0x00000100
++#define SPI_ALLOC_STATUS_I_MSK 0xfffffeff
++#define SPI_ALLOC_STATUS_SFT 8
++#define SPI_ALLOC_STATUS_HI 8
++#define SPI_ALLOC_STATUS_SZ 1
++#define SPI_DBG_WR_FIFO_FULL_MSK 0x00000200
++#define SPI_DBG_WR_FIFO_FULL_I_MSK 0xfffffdff
++#define SPI_DBG_WR_FIFO_FULL_SFT 9
++#define SPI_DBG_WR_FIFO_FULL_HI 9
++#define SPI_DBG_WR_FIFO_FULL_SZ 1
++#define RX_LEN_MSK 0xffff0000
++#define RX_LEN_I_MSK 0x0000ffff
++#define RX_LEN_SFT 16
++#define RX_LEN_HI 31
++#define RX_LEN_SZ 16
++#define SPI_TX_ALLOC_SIZE_SHIFT_BITS_MSK 0x00000007
++#define SPI_TX_ALLOC_SIZE_SHIFT_BITS_I_MSK 0xfffffff8
++#define SPI_TX_ALLOC_SIZE_SHIFT_BITS_SFT 0
++#define SPI_TX_ALLOC_SIZE_SHIFT_BITS_HI 2
++#define SPI_TX_ALLOC_SIZE_SHIFT_BITS_SZ 3
++#define SPI_HOST_TX_ALLOC_PKBUF_MSK 0x00000100
++#define SPI_HOST_TX_ALLOC_PKBUF_I_MSK 0xfffffeff
++#define SPI_HOST_TX_ALLOC_PKBUF_SFT 8
++#define SPI_HOST_TX_ALLOC_PKBUF_HI 8
++#define SPI_HOST_TX_ALLOC_PKBUF_SZ 1
++#define SPI_TX_ALLOC_SIZE_MSK 0x000000ff
++#define SPI_TX_ALLOC_SIZE_I_MSK 0xffffff00
++#define SPI_TX_ALLOC_SIZE_SFT 0
++#define SPI_TX_ALLOC_SIZE_HI 7
++#define SPI_TX_ALLOC_SIZE_SZ 8
++#define RD_DAT_CNT_MSK 0x0000ffff
++#define RD_DAT_CNT_I_MSK 0xffff0000
++#define RD_DAT_CNT_SFT 0
++#define RD_DAT_CNT_HI 15
++#define RD_DAT_CNT_SZ 16
++#define RD_STS_CNT_MSK 0xffff0000
++#define RD_STS_CNT_I_MSK 0x0000ffff
++#define RD_STS_CNT_SFT 16
++#define RD_STS_CNT_HI 31
++#define RD_STS_CNT_SZ 16
++#define JUDGE_CNT_MSK 0x0000ffff
++#define JUDGE_CNT_I_MSK 0xffff0000
++#define JUDGE_CNT_SFT 0
++#define JUDGE_CNT_HI 15
++#define JUDGE_CNT_SZ 16
++#define RD_STS_CNT_CLR_MSK 0x00010000
++#define RD_STS_CNT_CLR_I_MSK 0xfffeffff
++#define RD_STS_CNT_CLR_SFT 16
++#define RD_STS_CNT_CLR_HI 16
++#define RD_STS_CNT_CLR_SZ 1
++#define RD_DAT_CNT_CLR_MSK 0x00020000
++#define RD_DAT_CNT_CLR_I_MSK 0xfffdffff
++#define RD_DAT_CNT_CLR_SFT 17
++#define RD_DAT_CNT_CLR_HI 17
++#define RD_DAT_CNT_CLR_SZ 1
++#define JUDGE_CNT_CLR_MSK 0x00040000
++#define JUDGE_CNT_CLR_I_MSK 0xfffbffff
++#define JUDGE_CNT_CLR_SFT 18
++#define JUDGE_CNT_CLR_HI 18
++#define JUDGE_CNT_CLR_SZ 1
++#define TX_DONE_CNT_MSK 0x0000ffff
++#define TX_DONE_CNT_I_MSK 0xffff0000
++#define TX_DONE_CNT_SFT 0
++#define TX_DONE_CNT_HI 15
++#define TX_DONE_CNT_SZ 16
++#define TX_DISCARD_CNT_MSK 0xffff0000
++#define TX_DISCARD_CNT_I_MSK 0x0000ffff
++#define TX_DISCARD_CNT_SFT 16
++#define TX_DISCARD_CNT_HI 31
++#define TX_DISCARD_CNT_SZ 16
++#define TX_SET_CNT_MSK 0x0000ffff
++#define TX_SET_CNT_I_MSK 0xffff0000
++#define TX_SET_CNT_SFT 0
++#define TX_SET_CNT_HI 15
++#define TX_SET_CNT_SZ 16
++#define TX_DISCARD_CNT_CLR_MSK 0x00010000
++#define TX_DISCARD_CNT_CLR_I_MSK 0xfffeffff
++#define TX_DISCARD_CNT_CLR_SFT 16
++#define TX_DISCARD_CNT_CLR_HI 16
++#define TX_DISCARD_CNT_CLR_SZ 1
++#define TX_DONE_CNT_CLR_MSK 0x00020000
++#define TX_DONE_CNT_CLR_I_MSK 0xfffdffff
++#define TX_DONE_CNT_CLR_SFT 17
++#define TX_DONE_CNT_CLR_HI 17
++#define TX_DONE_CNT_CLR_SZ 1
++#define TX_SET_CNT_CLR_MSK 0x00040000
++#define TX_SET_CNT_CLR_I_MSK 0xfffbffff
++#define TX_SET_CNT_CLR_SFT 18
++#define TX_SET_CNT_CLR_HI 18
++#define TX_SET_CNT_CLR_SZ 1
++#define DAT_MODE_OFF_MSK 0x00080000
++#define DAT_MODE_OFF_I_MSK 0xfff7ffff
++#define DAT_MODE_OFF_SFT 19
++#define DAT_MODE_OFF_HI 19
++#define DAT_MODE_OFF_SZ 1
++#define TX_FIFO_RESIDUE_MSK 0x00700000
++#define TX_FIFO_RESIDUE_I_MSK 0xff8fffff
++#define TX_FIFO_RESIDUE_SFT 20
++#define TX_FIFO_RESIDUE_HI 22
++#define TX_FIFO_RESIDUE_SZ 3
++#define RX_FIFO_RESIDUE_MSK 0x07000000
++#define RX_FIFO_RESIDUE_I_MSK 0xf8ffffff
++#define RX_FIFO_RESIDUE_SFT 24
++#define RX_FIFO_RESIDUE_HI 26
++#define RX_FIFO_RESIDUE_SZ 3
++#define RX_RDY_MSK 0x00000001
++#define RX_RDY_I_MSK 0xfffffffe
++#define RX_RDY_SFT 0
++#define RX_RDY_HI 0
++#define RX_RDY_SZ 1
++#define SDIO_SYS_INT_MSK 0x00000004
++#define SDIO_SYS_INT_I_MSK 0xfffffffb
++#define SDIO_SYS_INT_SFT 2
++#define SDIO_SYS_INT_HI 2
++#define SDIO_SYS_INT_SZ 1
++#define EDCA0_LOWTHOLD_INT_MSK 0x00000008
++#define EDCA0_LOWTHOLD_INT_I_MSK 0xfffffff7
++#define EDCA0_LOWTHOLD_INT_SFT 3
++#define EDCA0_LOWTHOLD_INT_HI 3
++#define EDCA0_LOWTHOLD_INT_SZ 1
++#define EDCA1_LOWTHOLD_INT_MSK 0x00000010
++#define EDCA1_LOWTHOLD_INT_I_MSK 0xffffffef
++#define EDCA1_LOWTHOLD_INT_SFT 4
++#define EDCA1_LOWTHOLD_INT_HI 4
++#define EDCA1_LOWTHOLD_INT_SZ 1
++#define EDCA2_LOWTHOLD_INT_MSK 0x00000020
++#define EDCA2_LOWTHOLD_INT_I_MSK 0xffffffdf
++#define EDCA2_LOWTHOLD_INT_SFT 5
++#define EDCA2_LOWTHOLD_INT_HI 5
++#define EDCA2_LOWTHOLD_INT_SZ 1
++#define EDCA3_LOWTHOLD_INT_MSK 0x00000040
++#define EDCA3_LOWTHOLD_INT_I_MSK 0xffffffbf
++#define EDCA3_LOWTHOLD_INT_SFT 6
++#define EDCA3_LOWTHOLD_INT_HI 6
++#define EDCA3_LOWTHOLD_INT_SZ 1
++#define TX_LIMIT_INT_IN_MSK 0x00000080
++#define TX_LIMIT_INT_IN_I_MSK 0xffffff7f
++#define TX_LIMIT_INT_IN_SFT 7
++#define TX_LIMIT_INT_IN_HI 7
++#define TX_LIMIT_INT_IN_SZ 1
++#define SPI_FN1_MSK 0x00007f00
++#define SPI_FN1_I_MSK 0xffff80ff
++#define SPI_FN1_SFT 8
++#define SPI_FN1_HI 14
++#define SPI_FN1_SZ 7
++#define SPI_CLK_EN_INT_MSK 0x00008000
++#define SPI_CLK_EN_INT_I_MSK 0xffff7fff
++#define SPI_CLK_EN_INT_SFT 15
++#define SPI_CLK_EN_INT_HI 15
++#define SPI_CLK_EN_INT_SZ 1
++#define SPI_HOST_MASK_MSK 0x00ff0000
++#define SPI_HOST_MASK_I_MSK 0xff00ffff
++#define SPI_HOST_MASK_SFT 16
++#define SPI_HOST_MASK_HI 23
++#define SPI_HOST_MASK_SZ 8
++#define I2CM_INT_WDONE_MSK 0x00000001
++#define I2CM_INT_WDONE_I_MSK 0xfffffffe
++#define I2CM_INT_WDONE_SFT 0
++#define I2CM_INT_WDONE_HI 0
++#define I2CM_INT_WDONE_SZ 1
++#define I2CM_INT_RDONE_MSK 0x00000002
++#define I2CM_INT_RDONE_I_MSK 0xfffffffd
++#define I2CM_INT_RDONE_SFT 1
++#define I2CM_INT_RDONE_HI 1
++#define I2CM_INT_RDONE_SZ 1
++#define I2CM_IDLE_MSK 0x00000004
++#define I2CM_IDLE_I_MSK 0xfffffffb
++#define I2CM_IDLE_SFT 2
++#define I2CM_IDLE_HI 2
++#define I2CM_IDLE_SZ 1
++#define I2CM_INT_MISMATCH_MSK 0x00000008
++#define I2CM_INT_MISMATCH_I_MSK 0xfffffff7
++#define I2CM_INT_MISMATCH_SFT 3
++#define I2CM_INT_MISMATCH_HI 3
++#define I2CM_INT_MISMATCH_SZ 1
++#define I2CM_PSCL_MSK 0x00003ff0
++#define I2CM_PSCL_I_MSK 0xffffc00f
++#define I2CM_PSCL_SFT 4
++#define I2CM_PSCL_HI 13
++#define I2CM_PSCL_SZ 10
++#define I2CM_MANUAL_MODE_MSK 0x00010000
++#define I2CM_MANUAL_MODE_I_MSK 0xfffeffff
++#define I2CM_MANUAL_MODE_SFT 16
++#define I2CM_MANUAL_MODE_HI 16
++#define I2CM_MANUAL_MODE_SZ 1
++#define I2CM_INT_WDATA_NEED_MSK 0x00020000
++#define I2CM_INT_WDATA_NEED_I_MSK 0xfffdffff
++#define I2CM_INT_WDATA_NEED_SFT 17
++#define I2CM_INT_WDATA_NEED_HI 17
++#define I2CM_INT_WDATA_NEED_SZ 1
++#define I2CM_INT_RDATA_NEED_MSK 0x00040000
++#define I2CM_INT_RDATA_NEED_I_MSK 0xfffbffff
++#define I2CM_INT_RDATA_NEED_SFT 18
++#define I2CM_INT_RDATA_NEED_HI 18
++#define I2CM_INT_RDATA_NEED_SZ 1
++#define I2CM_DEV_A_MSK 0x000003ff
++#define I2CM_DEV_A_I_MSK 0xfffffc00
++#define I2CM_DEV_A_SFT 0
++#define I2CM_DEV_A_HI 9
++#define I2CM_DEV_A_SZ 10
++#define I2CM_DEV_A10B_MSK 0x00004000
++#define I2CM_DEV_A10B_I_MSK 0xffffbfff
++#define I2CM_DEV_A10B_SFT 14
++#define I2CM_DEV_A10B_HI 14
++#define I2CM_DEV_A10B_SZ 1
++#define I2CM_RX_MSK 0x00008000
++#define I2CM_RX_I_MSK 0xffff7fff
++#define I2CM_RX_SFT 15
++#define I2CM_RX_HI 15
++#define I2CM_RX_SZ 1
++#define I2CM_LEN_MSK 0x0000ffff
++#define I2CM_LEN_I_MSK 0xffff0000
++#define I2CM_LEN_SFT 0
++#define I2CM_LEN_HI 15
++#define I2CM_LEN_SZ 16
++#define I2CM_T_LEFT_MSK 0x00070000
++#define I2CM_T_LEFT_I_MSK 0xfff8ffff
++#define I2CM_T_LEFT_SFT 16
++#define I2CM_T_LEFT_HI 18
++#define I2CM_T_LEFT_SZ 3
++#define I2CM_R_GET_MSK 0x07000000
++#define I2CM_R_GET_I_MSK 0xf8ffffff
++#define I2CM_R_GET_SFT 24
++#define I2CM_R_GET_HI 26
++#define I2CM_R_GET_SZ 3
++#define I2CM_WDAT_MSK 0xffffffff
++#define I2CM_WDAT_I_MSK 0x00000000
++#define I2CM_WDAT_SFT 0
++#define I2CM_WDAT_HI 31
++#define I2CM_WDAT_SZ 32
++#define I2CM_RDAT_MSK 0xffffffff
++#define I2CM_RDAT_I_MSK 0x00000000
++#define I2CM_RDAT_SFT 0
++#define I2CM_RDAT_HI 31
++#define I2CM_RDAT_SZ 32
++#define I2CM_SR_LEN_MSK 0x0000ffff
++#define I2CM_SR_LEN_I_MSK 0xffff0000
++#define I2CM_SR_LEN_SFT 0
++#define I2CM_SR_LEN_HI 15
++#define I2CM_SR_LEN_SZ 16
++#define I2CM_SR_RX_MSK 0x00010000
++#define I2CM_SR_RX_I_MSK 0xfffeffff
++#define I2CM_SR_RX_SFT 16
++#define I2CM_SR_RX_HI 16
++#define I2CM_SR_RX_SZ 1
++#define I2CM_REPEAT_START_MSK 0x00020000
++#define I2CM_REPEAT_START_I_MSK 0xfffdffff
++#define I2CM_REPEAT_START_SFT 17
++#define I2CM_REPEAT_START_HI 17
++#define I2CM_REPEAT_START_SZ 1
++#define UART_DATA_MSK 0x000000ff
++#define UART_DATA_I_MSK 0xffffff00
++#define UART_DATA_SFT 0
++#define UART_DATA_HI 7
++#define UART_DATA_SZ 8
++#define DATA_RDY_IE_MSK 0x00000001
++#define DATA_RDY_IE_I_MSK 0xfffffffe
++#define DATA_RDY_IE_SFT 0
++#define DATA_RDY_IE_HI 0
++#define DATA_RDY_IE_SZ 1
++#define THR_EMPTY_IE_MSK 0x00000002
++#define THR_EMPTY_IE_I_MSK 0xfffffffd
++#define THR_EMPTY_IE_SFT 1
++#define THR_EMPTY_IE_HI 1
++#define THR_EMPTY_IE_SZ 1
++#define RX_LINESTS_IE_MSK 0x00000004
++#define RX_LINESTS_IE_I_MSK 0xfffffffb
++#define RX_LINESTS_IE_SFT 2
++#define RX_LINESTS_IE_HI 2
++#define RX_LINESTS_IE_SZ 1
++#define MDM_STS_IE_MSK 0x00000008
++#define MDM_STS_IE_I_MSK 0xfffffff7
++#define MDM_STS_IE_SFT 3
++#define MDM_STS_IE_HI 3
++#define MDM_STS_IE_SZ 1
++#define DMA_RXEND_IE_MSK 0x00000040
++#define DMA_RXEND_IE_I_MSK 0xffffffbf
++#define DMA_RXEND_IE_SFT 6
++#define DMA_RXEND_IE_HI 6
++#define DMA_RXEND_IE_SZ 1
++#define DMA_TXEND_IE_MSK 0x00000080
++#define DMA_TXEND_IE_I_MSK 0xffffff7f
++#define DMA_TXEND_IE_SFT 7
++#define DMA_TXEND_IE_HI 7
++#define DMA_TXEND_IE_SZ 1
++#define FIFO_EN_MSK 0x00000001
++#define FIFO_EN_I_MSK 0xfffffffe
++#define FIFO_EN_SFT 0
++#define FIFO_EN_HI 0
++#define FIFO_EN_SZ 1
++#define RXFIFO_RST_MSK 0x00000002
++#define RXFIFO_RST_I_MSK 0xfffffffd
++#define RXFIFO_RST_SFT 1
++#define RXFIFO_RST_HI 1
++#define RXFIFO_RST_SZ 1
++#define TXFIFO_RST_MSK 0x00000004
++#define TXFIFO_RST_I_MSK 0xfffffffb
++#define TXFIFO_RST_SFT 2
++#define TXFIFO_RST_HI 2
++#define TXFIFO_RST_SZ 1
++#define DMA_MODE_MSK 0x00000008
++#define DMA_MODE_I_MSK 0xfffffff7
++#define DMA_MODE_SFT 3
++#define DMA_MODE_HI 3
++#define DMA_MODE_SZ 1
++#define EN_AUTO_RTS_MSK 0x00000010
++#define EN_AUTO_RTS_I_MSK 0xffffffef
++#define EN_AUTO_RTS_SFT 4
++#define EN_AUTO_RTS_HI 4
++#define EN_AUTO_RTS_SZ 1
++#define EN_AUTO_CTS_MSK 0x00000020
++#define EN_AUTO_CTS_I_MSK 0xffffffdf
++#define EN_AUTO_CTS_SFT 5
++#define EN_AUTO_CTS_HI 5
++#define EN_AUTO_CTS_SZ 1
++#define RXFIFO_TRGLVL_MSK 0x000000c0
++#define RXFIFO_TRGLVL_I_MSK 0xffffff3f
++#define RXFIFO_TRGLVL_SFT 6
++#define RXFIFO_TRGLVL_HI 7
++#define RXFIFO_TRGLVL_SZ 2
++#define WORD_LEN_MSK 0x00000003
++#define WORD_LEN_I_MSK 0xfffffffc
++#define WORD_LEN_SFT 0
++#define WORD_LEN_HI 1
++#define WORD_LEN_SZ 2
++#define STOP_BIT_MSK 0x00000004
++#define STOP_BIT_I_MSK 0xfffffffb
++#define STOP_BIT_SFT 2
++#define STOP_BIT_HI 2
++#define STOP_BIT_SZ 1
++#define PARITY_EN_MSK 0x00000008
++#define PARITY_EN_I_MSK 0xfffffff7
++#define PARITY_EN_SFT 3
++#define PARITY_EN_HI 3
++#define PARITY_EN_SZ 1
++#define EVEN_PARITY_MSK 0x00000010
++#define EVEN_PARITY_I_MSK 0xffffffef
++#define EVEN_PARITY_SFT 4
++#define EVEN_PARITY_HI 4
++#define EVEN_PARITY_SZ 1
++#define FORCE_PARITY_MSK 0x00000020
++#define FORCE_PARITY_I_MSK 0xffffffdf
++#define FORCE_PARITY_SFT 5
++#define FORCE_PARITY_HI 5
++#define FORCE_PARITY_SZ 1
++#define SET_BREAK_MSK 0x00000040
++#define SET_BREAK_I_MSK 0xffffffbf
++#define SET_BREAK_SFT 6
++#define SET_BREAK_HI 6
++#define SET_BREAK_SZ 1
++#define DLAB_MSK 0x00000080
++#define DLAB_I_MSK 0xffffff7f
++#define DLAB_SFT 7
++#define DLAB_HI 7
++#define DLAB_SZ 1
++#define DTR_MSK 0x00000001
++#define DTR_I_MSK 0xfffffffe
++#define DTR_SFT 0
++#define DTR_HI 0
++#define DTR_SZ 1
++#define RTS_MSK 0x00000002
++#define RTS_I_MSK 0xfffffffd
++#define RTS_SFT 1
++#define RTS_HI 1
++#define RTS_SZ 1
++#define OUT_1_MSK 0x00000004
++#define OUT_1_I_MSK 0xfffffffb
++#define OUT_1_SFT 2
++#define OUT_1_HI 2
++#define OUT_1_SZ 1
++#define OUT_2_MSK 0x00000008
++#define OUT_2_I_MSK 0xfffffff7
++#define OUT_2_SFT 3
++#define OUT_2_HI 3
++#define OUT_2_SZ 1
++#define LOOP_BACK_MSK 0x00000010
++#define LOOP_BACK_I_MSK 0xffffffef
++#define LOOP_BACK_SFT 4
++#define LOOP_BACK_HI 4
++#define LOOP_BACK_SZ 1
++#define DATA_RDY_MSK 0x00000001
++#define DATA_RDY_I_MSK 0xfffffffe
++#define DATA_RDY_SFT 0
++#define DATA_RDY_HI 0
++#define DATA_RDY_SZ 1
++#define OVERRUN_ERR_MSK 0x00000002
++#define OVERRUN_ERR_I_MSK 0xfffffffd
++#define OVERRUN_ERR_SFT 1
++#define OVERRUN_ERR_HI 1
++#define OVERRUN_ERR_SZ 1
++#define PARITY_ERR_MSK 0x00000004
++#define PARITY_ERR_I_MSK 0xfffffffb
++#define PARITY_ERR_SFT 2
++#define PARITY_ERR_HI 2
++#define PARITY_ERR_SZ 1
++#define FRAMING_ERR_MSK 0x00000008
++#define FRAMING_ERR_I_MSK 0xfffffff7
++#define FRAMING_ERR_SFT 3
++#define FRAMING_ERR_HI 3
++#define FRAMING_ERR_SZ 1
++#define BREAK_INT_MSK 0x00000010
++#define BREAK_INT_I_MSK 0xffffffef
++#define BREAK_INT_SFT 4
++#define BREAK_INT_HI 4
++#define BREAK_INT_SZ 1
++#define THR_EMPTY_MSK 0x00000020
++#define THR_EMPTY_I_MSK 0xffffffdf
++#define THR_EMPTY_SFT 5
++#define THR_EMPTY_HI 5
++#define THR_EMPTY_SZ 1
++#define TX_EMPTY_MSK 0x00000040
++#define TX_EMPTY_I_MSK 0xffffffbf
++#define TX_EMPTY_SFT 6
++#define TX_EMPTY_HI 6
++#define TX_EMPTY_SZ 1
++#define FIFODATA_ERR_MSK 0x00000080
++#define FIFODATA_ERR_I_MSK 0xffffff7f
++#define FIFODATA_ERR_SFT 7
++#define FIFODATA_ERR_HI 7
++#define FIFODATA_ERR_SZ 1
++#define DELTA_CTS_MSK 0x00000001
++#define DELTA_CTS_I_MSK 0xfffffffe
++#define DELTA_CTS_SFT 0
++#define DELTA_CTS_HI 0
++#define DELTA_CTS_SZ 1
++#define DELTA_DSR_MSK 0x00000002
++#define DELTA_DSR_I_MSK 0xfffffffd
++#define DELTA_DSR_SFT 1
++#define DELTA_DSR_HI 1
++#define DELTA_DSR_SZ 1
++#define TRAILEDGE_RI_MSK 0x00000004
++#define TRAILEDGE_RI_I_MSK 0xfffffffb
++#define TRAILEDGE_RI_SFT 2
++#define TRAILEDGE_RI_HI 2
++#define TRAILEDGE_RI_SZ 1
++#define DELTA_CD_MSK 0x00000008
++#define DELTA_CD_I_MSK 0xfffffff7
++#define DELTA_CD_SFT 3
++#define DELTA_CD_HI 3
++#define DELTA_CD_SZ 1
++#define CTS_MSK 0x00000010
++#define CTS_I_MSK 0xffffffef
++#define CTS_SFT 4
++#define CTS_HI 4
++#define CTS_SZ 1
++#define DSR_MSK 0x00000020
++#define DSR_I_MSK 0xffffffdf
++#define DSR_SFT 5
++#define DSR_HI 5
++#define DSR_SZ 1
++#define RI_MSK 0x00000040
++#define RI_I_MSK 0xffffffbf
++#define RI_SFT 6
++#define RI_HI 6
++#define RI_SZ 1
++#define CD_MSK 0x00000080
++#define CD_I_MSK 0xffffff7f
++#define CD_SFT 7
++#define CD_HI 7
++#define CD_SZ 1
++#define BRDC_DIV_MSK 0x0000ffff
++#define BRDC_DIV_I_MSK 0xffff0000
++#define BRDC_DIV_SFT 0
++#define BRDC_DIV_HI 15
++#define BRDC_DIV_SZ 16
++#define RTHR_L_MSK 0x0000000f
++#define RTHR_L_I_MSK 0xfffffff0
++#define RTHR_L_SFT 0
++#define RTHR_L_HI 3
++#define RTHR_L_SZ 4
++#define RTHR_H_MSK 0x000000f0
++#define RTHR_H_I_MSK 0xffffff0f
++#define RTHR_H_SFT 4
++#define RTHR_H_HI 7
++#define RTHR_H_SZ 4
++#define INT_IDCODE_MSK 0x0000000f
++#define INT_IDCODE_I_MSK 0xfffffff0
++#define INT_IDCODE_SFT 0
++#define INT_IDCODE_HI 3
++#define INT_IDCODE_SZ 4
++#define FIFOS_ENABLED_MSK 0x000000c0
++#define FIFOS_ENABLED_I_MSK 0xffffff3f
++#define FIFOS_ENABLED_SFT 6
++#define FIFOS_ENABLED_HI 7
++#define FIFOS_ENABLED_SZ 2
++#define DAT_UART_DATA_MSK 0x000000ff
++#define DAT_UART_DATA_I_MSK 0xffffff00
++#define DAT_UART_DATA_SFT 0
++#define DAT_UART_DATA_HI 7
++#define DAT_UART_DATA_SZ 8
++#define DAT_DATA_RDY_IE_MSK 0x00000001
++#define DAT_DATA_RDY_IE_I_MSK 0xfffffffe
++#define DAT_DATA_RDY_IE_SFT 0
++#define DAT_DATA_RDY_IE_HI 0
++#define DAT_DATA_RDY_IE_SZ 1
++#define DAT_THR_EMPTY_IE_MSK 0x00000002
++#define DAT_THR_EMPTY_IE_I_MSK 0xfffffffd
++#define DAT_THR_EMPTY_IE_SFT 1
++#define DAT_THR_EMPTY_IE_HI 1
++#define DAT_THR_EMPTY_IE_SZ 1
++#define DAT_RX_LINESTS_IE_MSK 0x00000004
++#define DAT_RX_LINESTS_IE_I_MSK 0xfffffffb
++#define DAT_RX_LINESTS_IE_SFT 2
++#define DAT_RX_LINESTS_IE_HI 2
++#define DAT_RX_LINESTS_IE_SZ 1
++#define DAT_MDM_STS_IE_MSK 0x00000008
++#define DAT_MDM_STS_IE_I_MSK 0xfffffff7
++#define DAT_MDM_STS_IE_SFT 3
++#define DAT_MDM_STS_IE_HI 3
++#define DAT_MDM_STS_IE_SZ 1
++#define DAT_DMA_RXEND_IE_MSK 0x00000040
++#define DAT_DMA_RXEND_IE_I_MSK 0xffffffbf
++#define DAT_DMA_RXEND_IE_SFT 6
++#define DAT_DMA_RXEND_IE_HI 6
++#define DAT_DMA_RXEND_IE_SZ 1
++#define DAT_DMA_TXEND_IE_MSK 0x00000080
++#define DAT_DMA_TXEND_IE_I_MSK 0xffffff7f
++#define DAT_DMA_TXEND_IE_SFT 7
++#define DAT_DMA_TXEND_IE_HI 7
++#define DAT_DMA_TXEND_IE_SZ 1
++#define DAT_FIFO_EN_MSK 0x00000001
++#define DAT_FIFO_EN_I_MSK 0xfffffffe
++#define DAT_FIFO_EN_SFT 0
++#define DAT_FIFO_EN_HI 0
++#define DAT_FIFO_EN_SZ 1
++#define DAT_RXFIFO_RST_MSK 0x00000002
++#define DAT_RXFIFO_RST_I_MSK 0xfffffffd
++#define DAT_RXFIFO_RST_SFT 1
++#define DAT_RXFIFO_RST_HI 1
++#define DAT_RXFIFO_RST_SZ 1
++#define DAT_TXFIFO_RST_MSK 0x00000004
++#define DAT_TXFIFO_RST_I_MSK 0xfffffffb
++#define DAT_TXFIFO_RST_SFT 2
++#define DAT_TXFIFO_RST_HI 2
++#define DAT_TXFIFO_RST_SZ 1
++#define DAT_DMA_MODE_MSK 0x00000008
++#define DAT_DMA_MODE_I_MSK 0xfffffff7
++#define DAT_DMA_MODE_SFT 3
++#define DAT_DMA_MODE_HI 3
++#define DAT_DMA_MODE_SZ 1
++#define DAT_EN_AUTO_RTS_MSK 0x00000010
++#define DAT_EN_AUTO_RTS_I_MSK 0xffffffef
++#define DAT_EN_AUTO_RTS_SFT 4
++#define DAT_EN_AUTO_RTS_HI 4
++#define DAT_EN_AUTO_RTS_SZ 1
++#define DAT_EN_AUTO_CTS_MSK 0x00000020
++#define DAT_EN_AUTO_CTS_I_MSK 0xffffffdf
++#define DAT_EN_AUTO_CTS_SFT 5
++#define DAT_EN_AUTO_CTS_HI 5
++#define DAT_EN_AUTO_CTS_SZ 1
++#define DAT_RXFIFO_TRGLVL_MSK 0x000000c0
++#define DAT_RXFIFO_TRGLVL_I_MSK 0xffffff3f
++#define DAT_RXFIFO_TRGLVL_SFT 6
++#define DAT_RXFIFO_TRGLVL_HI 7
++#define DAT_RXFIFO_TRGLVL_SZ 2
++#define DAT_WORD_LEN_MSK 0x00000003
++#define DAT_WORD_LEN_I_MSK 0xfffffffc
++#define DAT_WORD_LEN_SFT 0
++#define DAT_WORD_LEN_HI 1
++#define DAT_WORD_LEN_SZ 2
++#define DAT_STOP_BIT_MSK 0x00000004
++#define DAT_STOP_BIT_I_MSK 0xfffffffb
++#define DAT_STOP_BIT_SFT 2
++#define DAT_STOP_BIT_HI 2
++#define DAT_STOP_BIT_SZ 1
++#define DAT_PARITY_EN_MSK 0x00000008
++#define DAT_PARITY_EN_I_MSK 0xfffffff7
++#define DAT_PARITY_EN_SFT 3
++#define DAT_PARITY_EN_HI 3
++#define DAT_PARITY_EN_SZ 1
++#define DAT_EVEN_PARITY_MSK 0x00000010
++#define DAT_EVEN_PARITY_I_MSK 0xffffffef
++#define DAT_EVEN_PARITY_SFT 4
++#define DAT_EVEN_PARITY_HI 4
++#define DAT_EVEN_PARITY_SZ 1
++#define DAT_FORCE_PARITY_MSK 0x00000020
++#define DAT_FORCE_PARITY_I_MSK 0xffffffdf
++#define DAT_FORCE_PARITY_SFT 5
++#define DAT_FORCE_PARITY_HI 5
++#define DAT_FORCE_PARITY_SZ 1
++#define DAT_SET_BREAK_MSK 0x00000040
++#define DAT_SET_BREAK_I_MSK 0xffffffbf
++#define DAT_SET_BREAK_SFT 6
++#define DAT_SET_BREAK_HI 6
++#define DAT_SET_BREAK_SZ 1
++#define DAT_DLAB_MSK 0x00000080
++#define DAT_DLAB_I_MSK 0xffffff7f
++#define DAT_DLAB_SFT 7
++#define DAT_DLAB_HI 7
++#define DAT_DLAB_SZ 1
++#define DAT_DTR_MSK 0x00000001
++#define DAT_DTR_I_MSK 0xfffffffe
++#define DAT_DTR_SFT 0
++#define DAT_DTR_HI 0
++#define DAT_DTR_SZ 1
++#define DAT_RTS_MSK 0x00000002
++#define DAT_RTS_I_MSK 0xfffffffd
++#define DAT_RTS_SFT 1
++#define DAT_RTS_HI 1
++#define DAT_RTS_SZ 1
++#define DAT_OUT_1_MSK 0x00000004
++#define DAT_OUT_1_I_MSK 0xfffffffb
++#define DAT_OUT_1_SFT 2
++#define DAT_OUT_1_HI 2
++#define DAT_OUT_1_SZ 1
++#define DAT_OUT_2_MSK 0x00000008
++#define DAT_OUT_2_I_MSK 0xfffffff7
++#define DAT_OUT_2_SFT 3
++#define DAT_OUT_2_HI 3
++#define DAT_OUT_2_SZ 1
++#define DAT_LOOP_BACK_MSK 0x00000010
++#define DAT_LOOP_BACK_I_MSK 0xffffffef
++#define DAT_LOOP_BACK_SFT 4
++#define DAT_LOOP_BACK_HI 4
++#define DAT_LOOP_BACK_SZ 1
++#define DAT_DATA_RDY_MSK 0x00000001
++#define DAT_DATA_RDY_I_MSK 0xfffffffe
++#define DAT_DATA_RDY_SFT 0
++#define DAT_DATA_RDY_HI 0
++#define DAT_DATA_RDY_SZ 1
++#define DAT_OVERRUN_ERR_MSK 0x00000002
++#define DAT_OVERRUN_ERR_I_MSK 0xfffffffd
++#define DAT_OVERRUN_ERR_SFT 1
++#define DAT_OVERRUN_ERR_HI 1
++#define DAT_OVERRUN_ERR_SZ 1
++#define DAT_PARITY_ERR_MSK 0x00000004
++#define DAT_PARITY_ERR_I_MSK 0xfffffffb
++#define DAT_PARITY_ERR_SFT 2
++#define DAT_PARITY_ERR_HI 2
++#define DAT_PARITY_ERR_SZ 1
++#define DAT_FRAMING_ERR_MSK 0x00000008
++#define DAT_FRAMING_ERR_I_MSK 0xfffffff7
++#define DAT_FRAMING_ERR_SFT 3
++#define DAT_FRAMING_ERR_HI 3
++#define DAT_FRAMING_ERR_SZ 1
++#define DAT_BREAK_INT_MSK 0x00000010
++#define DAT_BREAK_INT_I_MSK 0xffffffef
++#define DAT_BREAK_INT_SFT 4
++#define DAT_BREAK_INT_HI 4
++#define DAT_BREAK_INT_SZ 1
++#define DAT_THR_EMPTY_MSK 0x00000020
++#define DAT_THR_EMPTY_I_MSK 0xffffffdf
++#define DAT_THR_EMPTY_SFT 5
++#define DAT_THR_EMPTY_HI 5
++#define DAT_THR_EMPTY_SZ 1
++#define DAT_TX_EMPTY_MSK 0x00000040
++#define DAT_TX_EMPTY_I_MSK 0xffffffbf
++#define DAT_TX_EMPTY_SFT 6
++#define DAT_TX_EMPTY_HI 6
++#define DAT_TX_EMPTY_SZ 1
++#define DAT_FIFODATA_ERR_MSK 0x00000080
++#define DAT_FIFODATA_ERR_I_MSK 0xffffff7f
++#define DAT_FIFODATA_ERR_SFT 7
++#define DAT_FIFODATA_ERR_HI 7
++#define DAT_FIFODATA_ERR_SZ 1
++#define DAT_DELTA_CTS_MSK 0x00000001
++#define DAT_DELTA_CTS_I_MSK 0xfffffffe
++#define DAT_DELTA_CTS_SFT 0
++#define DAT_DELTA_CTS_HI 0
++#define DAT_DELTA_CTS_SZ 1
++#define DAT_DELTA_DSR_MSK 0x00000002
++#define DAT_DELTA_DSR_I_MSK 0xfffffffd
++#define DAT_DELTA_DSR_SFT 1
++#define DAT_DELTA_DSR_HI 1
++#define DAT_DELTA_DSR_SZ 1
++#define DAT_TRAILEDGE_RI_MSK 0x00000004
++#define DAT_TRAILEDGE_RI_I_MSK 0xfffffffb
++#define DAT_TRAILEDGE_RI_SFT 2
++#define DAT_TRAILEDGE_RI_HI 2
++#define DAT_TRAILEDGE_RI_SZ 1
++#define DAT_DELTA_CD_MSK 0x00000008
++#define DAT_DELTA_CD_I_MSK 0xfffffff7
++#define DAT_DELTA_CD_SFT 3
++#define DAT_DELTA_CD_HI 3
++#define DAT_DELTA_CD_SZ 1
++#define DAT_CTS_MSK 0x00000010
++#define DAT_CTS_I_MSK 0xffffffef
++#define DAT_CTS_SFT 4
++#define DAT_CTS_HI 4
++#define DAT_CTS_SZ 1
++#define DAT_DSR_MSK 0x00000020
++#define DAT_DSR_I_MSK 0xffffffdf
++#define DAT_DSR_SFT 5
++#define DAT_DSR_HI 5
++#define DAT_DSR_SZ 1
++#define DAT_RI_MSK 0x00000040
++#define DAT_RI_I_MSK 0xffffffbf
++#define DAT_RI_SFT 6
++#define DAT_RI_HI 6
++#define DAT_RI_SZ 1
++#define DAT_CD_MSK 0x00000080
++#define DAT_CD_I_MSK 0xffffff7f
++#define DAT_CD_SFT 7
++#define DAT_CD_HI 7
++#define DAT_CD_SZ 1
++#define DAT_BRDC_DIV_MSK 0x0000ffff
++#define DAT_BRDC_DIV_I_MSK 0xffff0000
++#define DAT_BRDC_DIV_SFT 0
++#define DAT_BRDC_DIV_HI 15
++#define DAT_BRDC_DIV_SZ 16
++#define DAT_RTHR_L_MSK 0x0000000f
++#define DAT_RTHR_L_I_MSK 0xfffffff0
++#define DAT_RTHR_L_SFT 0
++#define DAT_RTHR_L_HI 3
++#define DAT_RTHR_L_SZ 4
++#define DAT_RTHR_H_MSK 0x000000f0
++#define DAT_RTHR_H_I_MSK 0xffffff0f
++#define DAT_RTHR_H_SFT 4
++#define DAT_RTHR_H_HI 7
++#define DAT_RTHR_H_SZ 4
++#define DAT_INT_IDCODE_MSK 0x0000000f
++#define DAT_INT_IDCODE_I_MSK 0xfffffff0
++#define DAT_INT_IDCODE_SFT 0
++#define DAT_INT_IDCODE_HI 3
++#define DAT_INT_IDCODE_SZ 4
++#define DAT_FIFOS_ENABLED_MSK 0x000000c0
++#define DAT_FIFOS_ENABLED_I_MSK 0xffffff3f
++#define DAT_FIFOS_ENABLED_SFT 6
++#define DAT_FIFOS_ENABLED_HI 7
++#define DAT_FIFOS_ENABLED_SZ 2
++#define MASK_TOP_MSK 0xffffffff
++#define MASK_TOP_I_MSK 0x00000000
++#define MASK_TOP_SFT 0
++#define MASK_TOP_HI 31
++#define MASK_TOP_SZ 32
++#define INT_MODE_MSK 0xffffffff
++#define INT_MODE_I_MSK 0x00000000
++#define INT_MODE_SFT 0
++#define INT_MODE_HI 31
++#define INT_MODE_SZ 32
++#define IRQ_PHY_0_MSK 0x00000001
++#define IRQ_PHY_0_I_MSK 0xfffffffe
++#define IRQ_PHY_0_SFT 0
++#define IRQ_PHY_0_HI 0
++#define IRQ_PHY_0_SZ 1
++#define IRQ_PHY_1_MSK 0x00000002
++#define IRQ_PHY_1_I_MSK 0xfffffffd
++#define IRQ_PHY_1_SFT 1
++#define IRQ_PHY_1_HI 1
++#define IRQ_PHY_1_SZ 1
++#define IRQ_SDIO_MSK 0x00000004
++#define IRQ_SDIO_I_MSK 0xfffffffb
++#define IRQ_SDIO_SFT 2
++#define IRQ_SDIO_HI 2
++#define IRQ_SDIO_SZ 1
++#define IRQ_BEACON_DONE_MSK 0x00000008
++#define IRQ_BEACON_DONE_I_MSK 0xfffffff7
++#define IRQ_BEACON_DONE_SFT 3
++#define IRQ_BEACON_DONE_HI 3
++#define IRQ_BEACON_DONE_SZ 1
++#define IRQ_BEACON_MSK 0x00000010
++#define IRQ_BEACON_I_MSK 0xffffffef
++#define IRQ_BEACON_SFT 4
++#define IRQ_BEACON_HI 4
++#define IRQ_BEACON_SZ 1
++#define IRQ_PRE_BEACON_MSK 0x00000020
++#define IRQ_PRE_BEACON_I_MSK 0xffffffdf
++#define IRQ_PRE_BEACON_SFT 5
++#define IRQ_PRE_BEACON_HI 5
++#define IRQ_PRE_BEACON_SZ 1
++#define IRQ_EDCA0_TX_DONE_MSK 0x00000040
++#define IRQ_EDCA0_TX_DONE_I_MSK 0xffffffbf
++#define IRQ_EDCA0_TX_DONE_SFT 6
++#define IRQ_EDCA0_TX_DONE_HI 6
++#define IRQ_EDCA0_TX_DONE_SZ 1
++#define IRQ_EDCA1_TX_DONE_MSK 0x00000080
++#define IRQ_EDCA1_TX_DONE_I_MSK 0xffffff7f
++#define IRQ_EDCA1_TX_DONE_SFT 7
++#define IRQ_EDCA1_TX_DONE_HI 7
++#define IRQ_EDCA1_TX_DONE_SZ 1
++#define IRQ_EDCA2_TX_DONE_MSK 0x00000100
++#define IRQ_EDCA2_TX_DONE_I_MSK 0xfffffeff
++#define IRQ_EDCA2_TX_DONE_SFT 8
++#define IRQ_EDCA2_TX_DONE_HI 8
++#define IRQ_EDCA2_TX_DONE_SZ 1
++#define IRQ_EDCA3_TX_DONE_MSK 0x00000200
++#define IRQ_EDCA3_TX_DONE_I_MSK 0xfffffdff
++#define IRQ_EDCA3_TX_DONE_SFT 9
++#define IRQ_EDCA3_TX_DONE_HI 9
++#define IRQ_EDCA3_TX_DONE_SZ 1
++#define IRQ_EDCA4_TX_DONE_MSK 0x00000400
++#define IRQ_EDCA4_TX_DONE_I_MSK 0xfffffbff
++#define IRQ_EDCA4_TX_DONE_SFT 10
++#define IRQ_EDCA4_TX_DONE_HI 10
++#define IRQ_EDCA4_TX_DONE_SZ 1
++#define IRQ_BEACON_DTIM_MSK 0x00001000
++#define IRQ_BEACON_DTIM_I_MSK 0xffffefff
++#define IRQ_BEACON_DTIM_SFT 12
++#define IRQ_BEACON_DTIM_HI 12
++#define IRQ_BEACON_DTIM_SZ 1
++#define IRQ_EDCA0_LOWTHOLD_INT_MSK 0x00002000
++#define IRQ_EDCA0_LOWTHOLD_INT_I_MSK 0xffffdfff
++#define IRQ_EDCA0_LOWTHOLD_INT_SFT 13
++#define IRQ_EDCA0_LOWTHOLD_INT_HI 13
++#define IRQ_EDCA0_LOWTHOLD_INT_SZ 1
++#define IRQ_EDCA1_LOWTHOLD_INT_MSK 0x00004000
++#define IRQ_EDCA1_LOWTHOLD_INT_I_MSK 0xffffbfff
++#define IRQ_EDCA1_LOWTHOLD_INT_SFT 14
++#define IRQ_EDCA1_LOWTHOLD_INT_HI 14
++#define IRQ_EDCA1_LOWTHOLD_INT_SZ 1
++#define IRQ_EDCA2_LOWTHOLD_INT_MSK 0x00008000
++#define IRQ_EDCA2_LOWTHOLD_INT_I_MSK 0xffff7fff
++#define IRQ_EDCA2_LOWTHOLD_INT_SFT 15
++#define IRQ_EDCA2_LOWTHOLD_INT_HI 15
++#define IRQ_EDCA2_LOWTHOLD_INT_SZ 1
++#define IRQ_EDCA3_LOWTHOLD_INT_MSK 0x00010000
++#define IRQ_EDCA3_LOWTHOLD_INT_I_MSK 0xfffeffff
++#define IRQ_EDCA3_LOWTHOLD_INT_SFT 16
++#define IRQ_EDCA3_LOWTHOLD_INT_HI 16
++#define IRQ_EDCA3_LOWTHOLD_INT_SZ 1
++#define IRQ_FENCE_HIT_INT_MSK 0x00020000
++#define IRQ_FENCE_HIT_INT_I_MSK 0xfffdffff
++#define IRQ_FENCE_HIT_INT_SFT 17
++#define IRQ_FENCE_HIT_INT_HI 17
++#define IRQ_FENCE_HIT_INT_SZ 1
++#define IRQ_ILL_ADDR_INT_MSK 0x00040000
++#define IRQ_ILL_ADDR_INT_I_MSK 0xfffbffff
++#define IRQ_ILL_ADDR_INT_SFT 18
++#define IRQ_ILL_ADDR_INT_HI 18
++#define IRQ_ILL_ADDR_INT_SZ 1
++#define IRQ_MBOX_MSK 0x00080000
++#define IRQ_MBOX_I_MSK 0xfff7ffff
++#define IRQ_MBOX_SFT 19
++#define IRQ_MBOX_HI 19
++#define IRQ_MBOX_SZ 1
++#define IRQ_US_TIMER0_MSK 0x00100000
++#define IRQ_US_TIMER0_I_MSK 0xffefffff
++#define IRQ_US_TIMER0_SFT 20
++#define IRQ_US_TIMER0_HI 20
++#define IRQ_US_TIMER0_SZ 1
++#define IRQ_US_TIMER1_MSK 0x00200000
++#define IRQ_US_TIMER1_I_MSK 0xffdfffff
++#define IRQ_US_TIMER1_SFT 21
++#define IRQ_US_TIMER1_HI 21
++#define IRQ_US_TIMER1_SZ 1
++#define IRQ_US_TIMER2_MSK 0x00400000
++#define IRQ_US_TIMER2_I_MSK 0xffbfffff
++#define IRQ_US_TIMER2_SFT 22
++#define IRQ_US_TIMER2_HI 22
++#define IRQ_US_TIMER2_SZ 1
++#define IRQ_US_TIMER3_MSK 0x00800000
++#define IRQ_US_TIMER3_I_MSK 0xff7fffff
++#define IRQ_US_TIMER3_SFT 23
++#define IRQ_US_TIMER3_HI 23
++#define IRQ_US_TIMER3_SZ 1
++#define IRQ_MS_TIMER0_MSK 0x01000000
++#define IRQ_MS_TIMER0_I_MSK 0xfeffffff
++#define IRQ_MS_TIMER0_SFT 24
++#define IRQ_MS_TIMER0_HI 24
++#define IRQ_MS_TIMER0_SZ 1
++#define IRQ_MS_TIMER1_MSK 0x02000000
++#define IRQ_MS_TIMER1_I_MSK 0xfdffffff
++#define IRQ_MS_TIMER1_SFT 25
++#define IRQ_MS_TIMER1_HI 25
++#define IRQ_MS_TIMER1_SZ 1
++#define IRQ_MS_TIMER2_MSK 0x04000000
++#define IRQ_MS_TIMER2_I_MSK 0xfbffffff
++#define IRQ_MS_TIMER2_SFT 26
++#define IRQ_MS_TIMER2_HI 26
++#define IRQ_MS_TIMER2_SZ 1
++#define IRQ_MS_TIMER3_MSK 0x08000000
++#define IRQ_MS_TIMER3_I_MSK 0xf7ffffff
++#define IRQ_MS_TIMER3_SFT 27
++#define IRQ_MS_TIMER3_HI 27
++#define IRQ_MS_TIMER3_SZ 1
++#define IRQ_TX_LIMIT_INT_MSK 0x10000000
++#define IRQ_TX_LIMIT_INT_I_MSK 0xefffffff
++#define IRQ_TX_LIMIT_INT_SFT 28
++#define IRQ_TX_LIMIT_INT_HI 28
++#define IRQ_TX_LIMIT_INT_SZ 1
++#define IRQ_DMA0_MSK 0x20000000
++#define IRQ_DMA0_I_MSK 0xdfffffff
++#define IRQ_DMA0_SFT 29
++#define IRQ_DMA0_HI 29
++#define IRQ_DMA0_SZ 1
++#define IRQ_CO_DMA_MSK 0x40000000
++#define IRQ_CO_DMA_I_MSK 0xbfffffff
++#define IRQ_CO_DMA_SFT 30
++#define IRQ_CO_DMA_HI 30
++#define IRQ_CO_DMA_SZ 1
++#define IRQ_PERI_GROUP_MSK 0x80000000
++#define IRQ_PERI_GROUP_I_MSK 0x7fffffff
++#define IRQ_PERI_GROUP_SFT 31
++#define IRQ_PERI_GROUP_HI 31
++#define IRQ_PERI_GROUP_SZ 1
++#define FIQ_STATUS_MSK 0xffffffff
++#define FIQ_STATUS_I_MSK 0x00000000
++#define FIQ_STATUS_SFT 0
++#define FIQ_STATUS_HI 31
++#define FIQ_STATUS_SZ 32
++#define IRQ_RAW_MSK 0xffffffff
++#define IRQ_RAW_I_MSK 0x00000000
++#define IRQ_RAW_SFT 0
++#define IRQ_RAW_HI 31
++#define IRQ_RAW_SZ 32
++#define FIQ_RAW_MSK 0xffffffff
++#define FIQ_RAW_I_MSK 0x00000000
++#define FIQ_RAW_SFT 0
++#define FIQ_RAW_HI 31
++#define FIQ_RAW_SZ 32
++#define INT_PERI_MASK_MSK 0xffffffff
++#define INT_PERI_MASK_I_MSK 0x00000000
++#define INT_PERI_MASK_SFT 0
++#define INT_PERI_MASK_HI 31
++#define INT_PERI_MASK_SZ 32
++#define PERI_RTC_MSK 0x00000001
++#define PERI_RTC_I_MSK 0xfffffffe
++#define PERI_RTC_SFT 0
++#define PERI_RTC_HI 0
++#define PERI_RTC_SZ 1
++#define IRQ_UART0_TX_MSK 0x00000002
++#define IRQ_UART0_TX_I_MSK 0xfffffffd
++#define IRQ_UART0_TX_SFT 1
++#define IRQ_UART0_TX_HI 1
++#define IRQ_UART0_TX_SZ 1
++#define IRQ_UART0_RX_MSK 0x00000004
++#define IRQ_UART0_RX_I_MSK 0xfffffffb
++#define IRQ_UART0_RX_SFT 2
++#define IRQ_UART0_RX_HI 2
++#define IRQ_UART0_RX_SZ 1
++#define PERI_GPI_2_MSK 0x00000008
++#define PERI_GPI_2_I_MSK 0xfffffff7
++#define PERI_GPI_2_SFT 3
++#define PERI_GPI_2_HI 3
++#define PERI_GPI_2_SZ 1
++#define IRQ_SPI_IPC_MSK 0x00000010
++#define IRQ_SPI_IPC_I_MSK 0xffffffef
++#define IRQ_SPI_IPC_SFT 4
++#define IRQ_SPI_IPC_HI 4
++#define IRQ_SPI_IPC_SZ 1
++#define PERI_GPI_1_0_MSK 0x00000060
++#define PERI_GPI_1_0_I_MSK 0xffffff9f
++#define PERI_GPI_1_0_SFT 5
++#define PERI_GPI_1_0_HI 6
++#define PERI_GPI_1_0_SZ 2
++#define SCRT_INT_1_MSK 0x00000080
++#define SCRT_INT_1_I_MSK 0xffffff7f
++#define SCRT_INT_1_SFT 7
++#define SCRT_INT_1_HI 7
++#define SCRT_INT_1_SZ 1
++#define MMU_ALC_ERR_MSK 0x00000100
++#define MMU_ALC_ERR_I_MSK 0xfffffeff
++#define MMU_ALC_ERR_SFT 8
++#define MMU_ALC_ERR_HI 8
++#define MMU_ALC_ERR_SZ 1
++#define MMU_RLS_ERR_MSK 0x00000200
++#define MMU_RLS_ERR_I_MSK 0xfffffdff
++#define MMU_RLS_ERR_SFT 9
++#define MMU_RLS_ERR_HI 9
++#define MMU_RLS_ERR_SZ 1
++#define ID_MNG_INT_1_MSK 0x00000400
++#define ID_MNG_INT_1_I_MSK 0xfffffbff
++#define ID_MNG_INT_1_SFT 10
++#define ID_MNG_INT_1_HI 10
++#define ID_MNG_INT_1_SZ 1
++#define MBOX_INT_1_MSK 0x00000800
++#define MBOX_INT_1_I_MSK 0xfffff7ff
++#define MBOX_INT_1_SFT 11
++#define MBOX_INT_1_HI 11
++#define MBOX_INT_1_SZ 1
++#define MBOX_INT_2_MSK 0x00001000
++#define MBOX_INT_2_I_MSK 0xffffefff
++#define MBOX_INT_2_SFT 12
++#define MBOX_INT_2_HI 12
++#define MBOX_INT_2_SZ 1
++#define MBOX_INT_3_MSK 0x00002000
++#define MBOX_INT_3_I_MSK 0xffffdfff
++#define MBOX_INT_3_SFT 13
++#define MBOX_INT_3_HI 13
++#define MBOX_INT_3_SZ 1
++#define HCI_INT_1_MSK 0x00004000
++#define HCI_INT_1_I_MSK 0xffffbfff
++#define HCI_INT_1_SFT 14
++#define HCI_INT_1_HI 14
++#define HCI_INT_1_SZ 1
++#define UART_RX_TIMEOUT_MSK 0x00008000
++#define UART_RX_TIMEOUT_I_MSK 0xffff7fff
++#define UART_RX_TIMEOUT_SFT 15
++#define UART_RX_TIMEOUT_HI 15
++#define UART_RX_TIMEOUT_SZ 1
++#define UART_MULTI_IRQ_MSK 0x00010000
++#define UART_MULTI_IRQ_I_MSK 0xfffeffff
++#define UART_MULTI_IRQ_SFT 16
++#define UART_MULTI_IRQ_HI 16
++#define UART_MULTI_IRQ_SZ 1
++#define ID_MNG_INT_2_MSK 0x00020000
++#define ID_MNG_INT_2_I_MSK 0xfffdffff
++#define ID_MNG_INT_2_SFT 17
++#define ID_MNG_INT_2_HI 17
++#define ID_MNG_INT_2_SZ 1
++#define DMN_NOHIT_INT_MSK 0x00040000
++#define DMN_NOHIT_INT_I_MSK 0xfffbffff
++#define DMN_NOHIT_INT_SFT 18
++#define DMN_NOHIT_INT_HI 18
++#define DMN_NOHIT_INT_SZ 1
++#define ID_THOLD_RX_MSK 0x00080000
++#define ID_THOLD_RX_I_MSK 0xfff7ffff
++#define ID_THOLD_RX_SFT 19
++#define ID_THOLD_RX_HI 19
++#define ID_THOLD_RX_SZ 1
++#define ID_THOLD_TX_MSK 0x00100000
++#define ID_THOLD_TX_I_MSK 0xffefffff
++#define ID_THOLD_TX_SFT 20
++#define ID_THOLD_TX_HI 20
++#define ID_THOLD_TX_SZ 1
++#define ID_DOUBLE_RLS_MSK 0x00200000
++#define ID_DOUBLE_RLS_I_MSK 0xffdfffff
++#define ID_DOUBLE_RLS_SFT 21
++#define ID_DOUBLE_RLS_HI 21
++#define ID_DOUBLE_RLS_SZ 1
++#define RX_ID_LEN_THOLD_MSK 0x00400000
++#define RX_ID_LEN_THOLD_I_MSK 0xffbfffff
++#define RX_ID_LEN_THOLD_SFT 22
++#define RX_ID_LEN_THOLD_HI 22
++#define RX_ID_LEN_THOLD_SZ 1
++#define TX_ID_LEN_THOLD_MSK 0x00800000
++#define TX_ID_LEN_THOLD_I_MSK 0xff7fffff
++#define TX_ID_LEN_THOLD_SFT 23
++#define TX_ID_LEN_THOLD_HI 23
++#define TX_ID_LEN_THOLD_SZ 1
++#define ALL_ID_LEN_THOLD_MSK 0x01000000
++#define ALL_ID_LEN_THOLD_I_MSK 0xfeffffff
++#define ALL_ID_LEN_THOLD_SFT 24
++#define ALL_ID_LEN_THOLD_HI 24
++#define ALL_ID_LEN_THOLD_SZ 1
++#define DMN_MCU_INT_MSK 0x02000000
++#define DMN_MCU_INT_I_MSK 0xfdffffff
++#define DMN_MCU_INT_SFT 25
++#define DMN_MCU_INT_HI 25
++#define DMN_MCU_INT_SZ 1
++#define IRQ_DAT_UART_TX_MSK 0x04000000
++#define IRQ_DAT_UART_TX_I_MSK 0xfbffffff
++#define IRQ_DAT_UART_TX_SFT 26
++#define IRQ_DAT_UART_TX_HI 26
++#define IRQ_DAT_UART_TX_SZ 1
++#define IRQ_DAT_UART_RX_MSK 0x08000000
++#define IRQ_DAT_UART_RX_I_MSK 0xf7ffffff
++#define IRQ_DAT_UART_RX_SFT 27
++#define IRQ_DAT_UART_RX_HI 27
++#define IRQ_DAT_UART_RX_SZ 1
++#define DAT_UART_RX_TIMEOUT_MSK 0x10000000
++#define DAT_UART_RX_TIMEOUT_I_MSK 0xefffffff
++#define DAT_UART_RX_TIMEOUT_SFT 28
++#define DAT_UART_RX_TIMEOUT_HI 28
++#define DAT_UART_RX_TIMEOUT_SZ 1
++#define DAT_UART_MULTI_IRQ_MSK 0x20000000
++#define DAT_UART_MULTI_IRQ_I_MSK 0xdfffffff
++#define DAT_UART_MULTI_IRQ_SFT 29
++#define DAT_UART_MULTI_IRQ_HI 29
++#define DAT_UART_MULTI_IRQ_SZ 1
++#define ALR_ABT_NOCHG_INT_IRQ_MSK 0x40000000
++#define ALR_ABT_NOCHG_INT_IRQ_I_MSK 0xbfffffff
++#define ALR_ABT_NOCHG_INT_IRQ_SFT 30
++#define ALR_ABT_NOCHG_INT_IRQ_HI 30
++#define ALR_ABT_NOCHG_INT_IRQ_SZ 1
++#define TBLNEQ_MNGPKT_INT_IRQ_MSK 0x80000000
++#define TBLNEQ_MNGPKT_INT_IRQ_I_MSK 0x7fffffff
++#define TBLNEQ_MNGPKT_INT_IRQ_SFT 31
++#define TBLNEQ_MNGPKT_INT_IRQ_HI 31
++#define TBLNEQ_MNGPKT_INT_IRQ_SZ 1
++#define INTR_PERI_RAW_MSK 0xffffffff
++#define INTR_PERI_RAW_I_MSK 0x00000000
++#define INTR_PERI_RAW_SFT 0
++#define INTR_PERI_RAW_HI 31
++#define INTR_PERI_RAW_SZ 32
++#define INTR_GPI00_CFG_MSK 0x00000003
++#define INTR_GPI00_CFG_I_MSK 0xfffffffc
++#define INTR_GPI00_CFG_SFT 0
++#define INTR_GPI00_CFG_HI 1
++#define INTR_GPI00_CFG_SZ 2
++#define INTR_GPI01_CFG_MSK 0x0000000c
++#define INTR_GPI01_CFG_I_MSK 0xfffffff3
++#define INTR_GPI01_CFG_SFT 2
++#define INTR_GPI01_CFG_HI 3
++#define INTR_GPI01_CFG_SZ 2
++#define SYS_RST_INT_MSK 0x00000001
++#define SYS_RST_INT_I_MSK 0xfffffffe
++#define SYS_RST_INT_SFT 0
++#define SYS_RST_INT_HI 0
++#define SYS_RST_INT_SZ 1
++#define SPI_IPC_ADDR_MSK 0xffffffff
++#define SPI_IPC_ADDR_I_MSK 0x00000000
++#define SPI_IPC_ADDR_SFT 0
++#define SPI_IPC_ADDR_HI 31
++#define SPI_IPC_ADDR_SZ 32
++#define SD_MASK_TOP_MSK 0xffffffff
++#define SD_MASK_TOP_I_MSK 0x00000000
++#define SD_MASK_TOP_SFT 0
++#define SD_MASK_TOP_HI 31
++#define SD_MASK_TOP_SZ 32
++#define IRQ_PHY_0_SD_MSK 0x00000001
++#define IRQ_PHY_0_SD_I_MSK 0xfffffffe
++#define IRQ_PHY_0_SD_SFT 0
++#define IRQ_PHY_0_SD_HI 0
++#define IRQ_PHY_0_SD_SZ 1
++#define IRQ_PHY_1_SD_MSK 0x00000002
++#define IRQ_PHY_1_SD_I_MSK 0xfffffffd
++#define IRQ_PHY_1_SD_SFT 1
++#define IRQ_PHY_1_SD_HI 1
++#define IRQ_PHY_1_SD_SZ 1
++#define IRQ_SDIO_SD_MSK 0x00000004
++#define IRQ_SDIO_SD_I_MSK 0xfffffffb
++#define IRQ_SDIO_SD_SFT 2
++#define IRQ_SDIO_SD_HI 2
++#define IRQ_SDIO_SD_SZ 1
++#define IRQ_BEACON_DONE_SD_MSK 0x00000008
++#define IRQ_BEACON_DONE_SD_I_MSK 0xfffffff7
++#define IRQ_BEACON_DONE_SD_SFT 3
++#define IRQ_BEACON_DONE_SD_HI 3
++#define IRQ_BEACON_DONE_SD_SZ 1
++#define IRQ_BEACON_SD_MSK 0x00000010
++#define IRQ_BEACON_SD_I_MSK 0xffffffef
++#define IRQ_BEACON_SD_SFT 4
++#define IRQ_BEACON_SD_HI 4
++#define IRQ_BEACON_SD_SZ 1
++#define IRQ_PRE_BEACON_SD_MSK 0x00000020
++#define IRQ_PRE_BEACON_SD_I_MSK 0xffffffdf
++#define IRQ_PRE_BEACON_SD_SFT 5
++#define IRQ_PRE_BEACON_SD_HI 5
++#define IRQ_PRE_BEACON_SD_SZ 1
++#define IRQ_EDCA0_TX_DONE_SD_MSK 0x00000040
++#define IRQ_EDCA0_TX_DONE_SD_I_MSK 0xffffffbf
++#define IRQ_EDCA0_TX_DONE_SD_SFT 6
++#define IRQ_EDCA0_TX_DONE_SD_HI 6
++#define IRQ_EDCA0_TX_DONE_SD_SZ 1
++#define IRQ_EDCA1_TX_DONE_SD_MSK 0x00000080
++#define IRQ_EDCA1_TX_DONE_SD_I_MSK 0xffffff7f
++#define IRQ_EDCA1_TX_DONE_SD_SFT 7
++#define IRQ_EDCA1_TX_DONE_SD_HI 7
++#define IRQ_EDCA1_TX_DONE_SD_SZ 1
++#define IRQ_EDCA2_TX_DONE_SD_MSK 0x00000100
++#define IRQ_EDCA2_TX_DONE_SD_I_MSK 0xfffffeff
++#define IRQ_EDCA2_TX_DONE_SD_SFT 8
++#define IRQ_EDCA2_TX_DONE_SD_HI 8
++#define IRQ_EDCA2_TX_DONE_SD_SZ 1
++#define IRQ_EDCA3_TX_DONE_SD_MSK 0x00000200
++#define IRQ_EDCA3_TX_DONE_SD_I_MSK 0xfffffdff
++#define IRQ_EDCA3_TX_DONE_SD_SFT 9
++#define IRQ_EDCA3_TX_DONE_SD_HI 9
++#define IRQ_EDCA3_TX_DONE_SD_SZ 1
++#define IRQ_EDCA4_TX_DONE_SD_MSK 0x00000400
++#define IRQ_EDCA4_TX_DONE_SD_I_MSK 0xfffffbff
++#define IRQ_EDCA4_TX_DONE_SD_SFT 10
++#define IRQ_EDCA4_TX_DONE_SD_HI 10
++#define IRQ_EDCA4_TX_DONE_SD_SZ 1
++#define IRQ_BEACON_DTIM_SD_MSK 0x00001000
++#define IRQ_BEACON_DTIM_SD_I_MSK 0xffffefff
++#define IRQ_BEACON_DTIM_SD_SFT 12
++#define IRQ_BEACON_DTIM_SD_HI 12
++#define IRQ_BEACON_DTIM_SD_SZ 1
++#define IRQ_EDCA0_LOWTHOLD_INT_SD_MSK 0x00002000
++#define IRQ_EDCA0_LOWTHOLD_INT_SD_I_MSK 0xffffdfff
++#define IRQ_EDCA0_LOWTHOLD_INT_SD_SFT 13
++#define IRQ_EDCA0_LOWTHOLD_INT_SD_HI 13
++#define IRQ_EDCA0_LOWTHOLD_INT_SD_SZ 1
++#define IRQ_EDCA1_LOWTHOLD_INT_SD_MSK 0x00004000
++#define IRQ_EDCA1_LOWTHOLD_INT_SD_I_MSK 0xffffbfff
++#define IRQ_EDCA1_LOWTHOLD_INT_SD_SFT 14
++#define IRQ_EDCA1_LOWTHOLD_INT_SD_HI 14
++#define IRQ_EDCA1_LOWTHOLD_INT_SD_SZ 1
++#define IRQ_EDCA2_LOWTHOLD_INT_SD_MSK 0x00008000
++#define IRQ_EDCA2_LOWTHOLD_INT_SD_I_MSK 0xffff7fff
++#define IRQ_EDCA2_LOWTHOLD_INT_SD_SFT 15
++#define IRQ_EDCA2_LOWTHOLD_INT_SD_HI 15
++#define IRQ_EDCA2_LOWTHOLD_INT_SD_SZ 1
++#define IRQ_EDCA3_LOWTHOLD_INT_SD_MSK 0x00010000
++#define IRQ_EDCA3_LOWTHOLD_INT_SD_I_MSK 0xfffeffff
++#define IRQ_EDCA3_LOWTHOLD_INT_SD_SFT 16
++#define IRQ_EDCA3_LOWTHOLD_INT_SD_HI 16
++#define IRQ_EDCA3_LOWTHOLD_INT_SD_SZ 1
++#define IRQ_FENCE_HIT_INT_SD_MSK 0x00020000
++#define IRQ_FENCE_HIT_INT_SD_I_MSK 0xfffdffff
++#define IRQ_FENCE_HIT_INT_SD_SFT 17
++#define IRQ_FENCE_HIT_INT_SD_HI 17
++#define IRQ_FENCE_HIT_INT_SD_SZ 1
++#define IRQ_ILL_ADDR_INT_SD_MSK 0x00040000
++#define IRQ_ILL_ADDR_INT_SD_I_MSK 0xfffbffff
++#define IRQ_ILL_ADDR_INT_SD_SFT 18
++#define IRQ_ILL_ADDR_INT_SD_HI 18
++#define IRQ_ILL_ADDR_INT_SD_SZ 1
++#define IRQ_MBOX_SD_MSK 0x00080000
++#define IRQ_MBOX_SD_I_MSK 0xfff7ffff
++#define IRQ_MBOX_SD_SFT 19
++#define IRQ_MBOX_SD_HI 19
++#define IRQ_MBOX_SD_SZ 1
++#define IRQ_US_TIMER0_SD_MSK 0x00100000
++#define IRQ_US_TIMER0_SD_I_MSK 0xffefffff
++#define IRQ_US_TIMER0_SD_SFT 20
++#define IRQ_US_TIMER0_SD_HI 20
++#define IRQ_US_TIMER0_SD_SZ 1
++#define IRQ_US_TIMER1_SD_MSK 0x00200000
++#define IRQ_US_TIMER1_SD_I_MSK 0xffdfffff
++#define IRQ_US_TIMER1_SD_SFT 21
++#define IRQ_US_TIMER1_SD_HI 21
++#define IRQ_US_TIMER1_SD_SZ 1
++#define IRQ_US_TIMER2_SD_MSK 0x00400000
++#define IRQ_US_TIMER2_SD_I_MSK 0xffbfffff
++#define IRQ_US_TIMER2_SD_SFT 22
++#define IRQ_US_TIMER2_SD_HI 22
++#define IRQ_US_TIMER2_SD_SZ 1
++#define IRQ_US_TIMER3_SD_MSK 0x00800000
++#define IRQ_US_TIMER3_SD_I_MSK 0xff7fffff
++#define IRQ_US_TIMER3_SD_SFT 23
++#define IRQ_US_TIMER3_SD_HI 23
++#define IRQ_US_TIMER3_SD_SZ 1
++#define IRQ_MS_TIMER0_SD_MSK 0x01000000
++#define IRQ_MS_TIMER0_SD_I_MSK 0xfeffffff
++#define IRQ_MS_TIMER0_SD_SFT 24
++#define IRQ_MS_TIMER0_SD_HI 24
++#define IRQ_MS_TIMER0_SD_SZ 1
++#define IRQ_MS_TIMER1_SD_MSK 0x02000000
++#define IRQ_MS_TIMER1_SD_I_MSK 0xfdffffff
++#define IRQ_MS_TIMER1_SD_SFT 25
++#define IRQ_MS_TIMER1_SD_HI 25
++#define IRQ_MS_TIMER1_SD_SZ 1
++#define IRQ_MS_TIMER2_SD_MSK 0x04000000
++#define IRQ_MS_TIMER2_SD_I_MSK 0xfbffffff
++#define IRQ_MS_TIMER2_SD_SFT 26
++#define IRQ_MS_TIMER2_SD_HI 26
++#define IRQ_MS_TIMER2_SD_SZ 1
++#define IRQ_MS_TIMER3_SD_MSK 0x08000000
++#define IRQ_MS_TIMER3_SD_I_MSK 0xf7ffffff
++#define IRQ_MS_TIMER3_SD_SFT 27
++#define IRQ_MS_TIMER3_SD_HI 27
++#define IRQ_MS_TIMER3_SD_SZ 1
++#define IRQ_TX_LIMIT_INT_SD_MSK 0x10000000
++#define IRQ_TX_LIMIT_INT_SD_I_MSK 0xefffffff
++#define IRQ_TX_LIMIT_INT_SD_SFT 28
++#define IRQ_TX_LIMIT_INT_SD_HI 28
++#define IRQ_TX_LIMIT_INT_SD_SZ 1
++#define IRQ_DMA0_SD_MSK 0x20000000
++#define IRQ_DMA0_SD_I_MSK 0xdfffffff
++#define IRQ_DMA0_SD_SFT 29
++#define IRQ_DMA0_SD_HI 29
++#define IRQ_DMA0_SD_SZ 1
++#define IRQ_CO_DMA_SD_MSK 0x40000000
++#define IRQ_CO_DMA_SD_I_MSK 0xbfffffff
++#define IRQ_CO_DMA_SD_SFT 30
++#define IRQ_CO_DMA_SD_HI 30
++#define IRQ_CO_DMA_SD_SZ 1
++#define IRQ_PERI_GROUP_SD_MSK 0x80000000
++#define IRQ_PERI_GROUP_SD_I_MSK 0x7fffffff
++#define IRQ_PERI_GROUP_SD_SFT 31
++#define IRQ_PERI_GROUP_SD_HI 31
++#define IRQ_PERI_GROUP_SD_SZ 1
++#define INT_PERI_MASK_SD_MSK 0xffffffff
++#define INT_PERI_MASK_SD_I_MSK 0x00000000
++#define INT_PERI_MASK_SD_SFT 0
++#define INT_PERI_MASK_SD_HI 31
++#define INT_PERI_MASK_SD_SZ 32
++#define PERI_RTC_SD_MSK 0x00000001
++#define PERI_RTC_SD_I_MSK 0xfffffffe
++#define PERI_RTC_SD_SFT 0
++#define PERI_RTC_SD_HI 0
++#define PERI_RTC_SD_SZ 1
++#define IRQ_UART0_TX_SD_MSK 0x00000002
++#define IRQ_UART0_TX_SD_I_MSK 0xfffffffd
++#define IRQ_UART0_TX_SD_SFT 1
++#define IRQ_UART0_TX_SD_HI 1
++#define IRQ_UART0_TX_SD_SZ 1
++#define IRQ_UART0_RX_SD_MSK 0x00000004
++#define IRQ_UART0_RX_SD_I_MSK 0xfffffffb
++#define IRQ_UART0_RX_SD_SFT 2
++#define IRQ_UART0_RX_SD_HI 2
++#define IRQ_UART0_RX_SD_SZ 1
++#define PERI_GPI_SD_2_MSK 0x00000008
++#define PERI_GPI_SD_2_I_MSK 0xfffffff7
++#define PERI_GPI_SD_2_SFT 3
++#define PERI_GPI_SD_2_HI 3
++#define PERI_GPI_SD_2_SZ 1
++#define IRQ_SPI_IPC_SD_MSK 0x00000010
++#define IRQ_SPI_IPC_SD_I_MSK 0xffffffef
++#define IRQ_SPI_IPC_SD_SFT 4
++#define IRQ_SPI_IPC_SD_HI 4
++#define IRQ_SPI_IPC_SD_SZ 1
++#define PERI_GPI_SD_1_0_MSK 0x00000060
++#define PERI_GPI_SD_1_0_I_MSK 0xffffff9f
++#define PERI_GPI_SD_1_0_SFT 5
++#define PERI_GPI_SD_1_0_HI 6
++#define PERI_GPI_SD_1_0_SZ 2
++#define SCRT_INT_1_SD_MSK 0x00000080
++#define SCRT_INT_1_SD_I_MSK 0xffffff7f
++#define SCRT_INT_1_SD_SFT 7
++#define SCRT_INT_1_SD_HI 7
++#define SCRT_INT_1_SD_SZ 1
++#define MMU_ALC_ERR_SD_MSK 0x00000100
++#define MMU_ALC_ERR_SD_I_MSK 0xfffffeff
++#define MMU_ALC_ERR_SD_SFT 8
++#define MMU_ALC_ERR_SD_HI 8
++#define MMU_ALC_ERR_SD_SZ 1
++#define MMU_RLS_ERR_SD_MSK 0x00000200
++#define MMU_RLS_ERR_SD_I_MSK 0xfffffdff
++#define MMU_RLS_ERR_SD_SFT 9
++#define MMU_RLS_ERR_SD_HI 9
++#define MMU_RLS_ERR_SD_SZ 1
++#define ID_MNG_INT_1_SD_MSK 0x00000400
++#define ID_MNG_INT_1_SD_I_MSK 0xfffffbff
++#define ID_MNG_INT_1_SD_SFT 10
++#define ID_MNG_INT_1_SD_HI 10
++#define ID_MNG_INT_1_SD_SZ 1
++#define MBOX_INT_1_SD_MSK 0x00000800
++#define MBOX_INT_1_SD_I_MSK 0xfffff7ff
++#define MBOX_INT_1_SD_SFT 11
++#define MBOX_INT_1_SD_HI 11
++#define MBOX_INT_1_SD_SZ 1
++#define MBOX_INT_2_SD_MSK 0x00001000
++#define MBOX_INT_2_SD_I_MSK 0xffffefff
++#define MBOX_INT_2_SD_SFT 12
++#define MBOX_INT_2_SD_HI 12
++#define MBOX_INT_2_SD_SZ 1
++#define MBOX_INT_3_SD_MSK 0x00002000
++#define MBOX_INT_3_SD_I_MSK 0xffffdfff
++#define MBOX_INT_3_SD_SFT 13
++#define MBOX_INT_3_SD_HI 13
++#define MBOX_INT_3_SD_SZ 1
++#define HCI_INT_1_SD_MSK 0x00004000
++#define HCI_INT_1_SD_I_MSK 0xffffbfff
++#define HCI_INT_1_SD_SFT 14
++#define HCI_INT_1_SD_HI 14
++#define HCI_INT_1_SD_SZ 1
++#define UART_RX_TIMEOUT_SD_MSK 0x00008000
++#define UART_RX_TIMEOUT_SD_I_MSK 0xffff7fff
++#define UART_RX_TIMEOUT_SD_SFT 15
++#define UART_RX_TIMEOUT_SD_HI 15
++#define UART_RX_TIMEOUT_SD_SZ 1
++#define UART_MULTI_IRQ_SD_MSK 0x00010000
++#define UART_MULTI_IRQ_SD_I_MSK 0xfffeffff
++#define UART_MULTI_IRQ_SD_SFT 16
++#define UART_MULTI_IRQ_SD_HI 16
++#define UART_MULTI_IRQ_SD_SZ 1
++#define ID_MNG_INT_2_SD_MSK 0x00020000
++#define ID_MNG_INT_2_SD_I_MSK 0xfffdffff
++#define ID_MNG_INT_2_SD_SFT 17
++#define ID_MNG_INT_2_SD_HI 17
++#define ID_MNG_INT_2_SD_SZ 1
++#define DMN_NOHIT_INT_SD_MSK 0x00040000
++#define DMN_NOHIT_INT_SD_I_MSK 0xfffbffff
++#define DMN_NOHIT_INT_SD_SFT 18
++#define DMN_NOHIT_INT_SD_HI 18
++#define DMN_NOHIT_INT_SD_SZ 1
++#define ID_THOLD_RX_SD_MSK 0x00080000
++#define ID_THOLD_RX_SD_I_MSK 0xfff7ffff
++#define ID_THOLD_RX_SD_SFT 19
++#define ID_THOLD_RX_SD_HI 19
++#define ID_THOLD_RX_SD_SZ 1
++#define ID_THOLD_TX_SD_MSK 0x00100000
++#define ID_THOLD_TX_SD_I_MSK 0xffefffff
++#define ID_THOLD_TX_SD_SFT 20
++#define ID_THOLD_TX_SD_HI 20
++#define ID_THOLD_TX_SD_SZ 1
++#define ID_DOUBLE_RLS_SD_MSK 0x00200000
++#define ID_DOUBLE_RLS_SD_I_MSK 0xffdfffff
++#define ID_DOUBLE_RLS_SD_SFT 21
++#define ID_DOUBLE_RLS_SD_HI 21
++#define ID_DOUBLE_RLS_SD_SZ 1
++#define RX_ID_LEN_THOLD_SD_MSK 0x00400000
++#define RX_ID_LEN_THOLD_SD_I_MSK 0xffbfffff
++#define RX_ID_LEN_THOLD_SD_SFT 22
++#define RX_ID_LEN_THOLD_SD_HI 22
++#define RX_ID_LEN_THOLD_SD_SZ 1
++#define TX_ID_LEN_THOLD_SD_MSK 0x00800000
++#define TX_ID_LEN_THOLD_SD_I_MSK 0xff7fffff
++#define TX_ID_LEN_THOLD_SD_SFT 23
++#define TX_ID_LEN_THOLD_SD_HI 23
++#define TX_ID_LEN_THOLD_SD_SZ 1
++#define ALL_ID_LEN_THOLD_SD_MSK 0x01000000
++#define ALL_ID_LEN_THOLD_SD_I_MSK 0xfeffffff
++#define ALL_ID_LEN_THOLD_SD_SFT 24
++#define ALL_ID_LEN_THOLD_SD_HI 24
++#define ALL_ID_LEN_THOLD_SD_SZ 1
++#define DMN_MCU_INT_SD_MSK 0x02000000
++#define DMN_MCU_INT_SD_I_MSK 0xfdffffff
++#define DMN_MCU_INT_SD_SFT 25
++#define DMN_MCU_INT_SD_HI 25
++#define DMN_MCU_INT_SD_SZ 1
++#define IRQ_DAT_UART_TX_SD_MSK 0x04000000
++#define IRQ_DAT_UART_TX_SD_I_MSK 0xfbffffff
++#define IRQ_DAT_UART_TX_SD_SFT 26
++#define IRQ_DAT_UART_TX_SD_HI 26
++#define IRQ_DAT_UART_TX_SD_SZ 1
++#define IRQ_DAT_UART_RX_SD_MSK 0x08000000
++#define IRQ_DAT_UART_RX_SD_I_MSK 0xf7ffffff
++#define IRQ_DAT_UART_RX_SD_SFT 27
++#define IRQ_DAT_UART_RX_SD_HI 27
++#define IRQ_DAT_UART_RX_SD_SZ 1
++#define DAT_UART_RX_TIMEOUT_SD_MSK 0x10000000
++#define DAT_UART_RX_TIMEOUT_SD_I_MSK 0xefffffff
++#define DAT_UART_RX_TIMEOUT_SD_SFT 28
++#define DAT_UART_RX_TIMEOUT_SD_HI 28
++#define DAT_UART_RX_TIMEOUT_SD_SZ 1
++#define DAT_UART_MULTI_IRQ_SD_MSK 0x20000000
++#define DAT_UART_MULTI_IRQ_SD_I_MSK 0xdfffffff
++#define DAT_UART_MULTI_IRQ_SD_SFT 29
++#define DAT_UART_MULTI_IRQ_SD_HI 29
++#define DAT_UART_MULTI_IRQ_SD_SZ 1
++#define ALR_ABT_NOCHG_INT_IRQ_SD_MSK 0x40000000
++#define ALR_ABT_NOCHG_INT_IRQ_SD_I_MSK 0xbfffffff
++#define ALR_ABT_NOCHG_INT_IRQ_SD_SFT 30
++#define ALR_ABT_NOCHG_INT_IRQ_SD_HI 30
++#define ALR_ABT_NOCHG_INT_IRQ_SD_SZ 1
++#define TBLNEQ_MNGPKT_INT_IRQ_SD_MSK 0x80000000
++#define TBLNEQ_MNGPKT_INT_IRQ_SD_I_MSK 0x7fffffff
++#define TBLNEQ_MNGPKT_INT_IRQ_SD_SFT 31
++#define TBLNEQ_MNGPKT_INT_IRQ_SD_HI 31
++#define TBLNEQ_MNGPKT_INT_IRQ_SD_SZ 1
++#define DBG_SPI_MODE_MSK 0xffffffff
++#define DBG_SPI_MODE_I_MSK 0x00000000
++#define DBG_SPI_MODE_SFT 0
++#define DBG_SPI_MODE_HI 31
++#define DBG_SPI_MODE_SZ 32
++#define DBG_RX_QUOTA_MSK 0x0000ffff
++#define DBG_RX_QUOTA_I_MSK 0xffff0000
++#define DBG_RX_QUOTA_SFT 0
++#define DBG_RX_QUOTA_HI 15
++#define DBG_RX_QUOTA_SZ 16
++#define DBG_CONDI_NUM_MSK 0x000000ff
++#define DBG_CONDI_NUM_I_MSK 0xffffff00
++#define DBG_CONDI_NUM_SFT 0
++#define DBG_CONDI_NUM_HI 7
++#define DBG_CONDI_NUM_SZ 8
++#define DBG_HOST_PATH_MSK 0x00000001
++#define DBG_HOST_PATH_I_MSK 0xfffffffe
++#define DBG_HOST_PATH_SFT 0
++#define DBG_HOST_PATH_HI 0
++#define DBG_HOST_PATH_SZ 1
++#define DBG_TX_SEG_MSK 0xffffffff
++#define DBG_TX_SEG_I_MSK 0x00000000
++#define DBG_TX_SEG_SFT 0
++#define DBG_TX_SEG_HI 31
++#define DBG_TX_SEG_SZ 32
++#define DBG_BRST_MODE_MSK 0x00000001
++#define DBG_BRST_MODE_I_MSK 0xfffffffe
++#define DBG_BRST_MODE_SFT 0
++#define DBG_BRST_MODE_HI 0
++#define DBG_BRST_MODE_SZ 1
++#define DBG_CLK_WIDTH_MSK 0x0000ffff
++#define DBG_CLK_WIDTH_I_MSK 0xffff0000
++#define DBG_CLK_WIDTH_SFT 0
++#define DBG_CLK_WIDTH_HI 15
++#define DBG_CLK_WIDTH_SZ 16
++#define DBG_CSN_INTER_MSK 0xffff0000
++#define DBG_CSN_INTER_I_MSK 0x0000ffff
++#define DBG_CSN_INTER_SFT 16
++#define DBG_CSN_INTER_HI 31
++#define DBG_CSN_INTER_SZ 16
++#define DBG_BACK_DLY_MSK 0x0000ffff
++#define DBG_BACK_DLY_I_MSK 0xffff0000
++#define DBG_BACK_DLY_SFT 0
++#define DBG_BACK_DLY_HI 15
++#define DBG_BACK_DLY_SZ 16
++#define DBG_FRONT_DLY_MSK 0xffff0000
++#define DBG_FRONT_DLY_I_MSK 0x0000ffff
++#define DBG_FRONT_DLY_SFT 16
++#define DBG_FRONT_DLY_HI 31
++#define DBG_FRONT_DLY_SZ 16
++#define DBG_RX_FIFO_FAIL_MSK 0x00000002
++#define DBG_RX_FIFO_FAIL_I_MSK 0xfffffffd
++#define DBG_RX_FIFO_FAIL_SFT 1
++#define DBG_RX_FIFO_FAIL_HI 1
++#define DBG_RX_FIFO_FAIL_SZ 1
++#define DBG_RX_HOST_FAIL_MSK 0x00000004
++#define DBG_RX_HOST_FAIL_I_MSK 0xfffffffb
++#define DBG_RX_HOST_FAIL_SFT 2
++#define DBG_RX_HOST_FAIL_HI 2
++#define DBG_RX_HOST_FAIL_SZ 1
++#define DBG_TX_FIFO_FAIL_MSK 0x00000008
++#define DBG_TX_FIFO_FAIL_I_MSK 0xfffffff7
++#define DBG_TX_FIFO_FAIL_SFT 3
++#define DBG_TX_FIFO_FAIL_HI 3
++#define DBG_TX_FIFO_FAIL_SZ 1
++#define DBG_TX_HOST_FAIL_MSK 0x00000010
++#define DBG_TX_HOST_FAIL_I_MSK 0xffffffef
++#define DBG_TX_HOST_FAIL_SFT 4
++#define DBG_TX_HOST_FAIL_HI 4
++#define DBG_TX_HOST_FAIL_SZ 1
++#define DBG_SPI_DOUBLE_ALLOC_MSK 0x00000020
++#define DBG_SPI_DOUBLE_ALLOC_I_MSK 0xffffffdf
++#define DBG_SPI_DOUBLE_ALLOC_SFT 5
++#define DBG_SPI_DOUBLE_ALLOC_HI 5
++#define DBG_SPI_DOUBLE_ALLOC_SZ 1
++#define DBG_SPI_TX_NO_ALLOC_MSK 0x00000040
++#define DBG_SPI_TX_NO_ALLOC_I_MSK 0xffffffbf
++#define DBG_SPI_TX_NO_ALLOC_SFT 6
++#define DBG_SPI_TX_NO_ALLOC_HI 6
++#define DBG_SPI_TX_NO_ALLOC_SZ 1
++#define DBG_RDATA_RDY_MSK 0x00000080
++#define DBG_RDATA_RDY_I_MSK 0xffffff7f
++#define DBG_RDATA_RDY_SFT 7
++#define DBG_RDATA_RDY_HI 7
++#define DBG_RDATA_RDY_SZ 1
++#define DBG_SPI_ALLOC_STATUS_MSK 0x00000100
++#define DBG_SPI_ALLOC_STATUS_I_MSK 0xfffffeff
++#define DBG_SPI_ALLOC_STATUS_SFT 8
++#define DBG_SPI_ALLOC_STATUS_HI 8
++#define DBG_SPI_ALLOC_STATUS_SZ 1
++#define DBG_SPI_DBG_WR_FIFO_FULL_MSK 0x00000200
++#define DBG_SPI_DBG_WR_FIFO_FULL_I_MSK 0xfffffdff
++#define DBG_SPI_DBG_WR_FIFO_FULL_SFT 9
++#define DBG_SPI_DBG_WR_FIFO_FULL_HI 9
++#define DBG_SPI_DBG_WR_FIFO_FULL_SZ 1
++#define DBG_RX_LEN_MSK 0xffff0000
++#define DBG_RX_LEN_I_MSK 0x0000ffff
++#define DBG_RX_LEN_SFT 16
++#define DBG_RX_LEN_HI 31
++#define DBG_RX_LEN_SZ 16
++#define DBG_SPI_TX_ALLOC_SIZE_SHIFT_BITS_MSK 0x00000007
++#define DBG_SPI_TX_ALLOC_SIZE_SHIFT_BITS_I_MSK 0xfffffff8
++#define DBG_SPI_TX_ALLOC_SIZE_SHIFT_BITS_SFT 0
++#define DBG_SPI_TX_ALLOC_SIZE_SHIFT_BITS_HI 2
++#define DBG_SPI_TX_ALLOC_SIZE_SHIFT_BITS_SZ 3
++#define DBG_SPI_HOST_TX_ALLOC_PKBUF_MSK 0x00000100
++#define DBG_SPI_HOST_TX_ALLOC_PKBUF_I_MSK 0xfffffeff
++#define DBG_SPI_HOST_TX_ALLOC_PKBUF_SFT 8
++#define DBG_SPI_HOST_TX_ALLOC_PKBUF_HI 8
++#define DBG_SPI_HOST_TX_ALLOC_PKBUF_SZ 1
++#define DBG_SPI_TX_ALLOC_SIZE_MSK 0x000000ff
++#define DBG_SPI_TX_ALLOC_SIZE_I_MSK 0xffffff00
++#define DBG_SPI_TX_ALLOC_SIZE_SFT 0
++#define DBG_SPI_TX_ALLOC_SIZE_HI 7
++#define DBG_SPI_TX_ALLOC_SIZE_SZ 8
++#define DBG_RD_DAT_CNT_MSK 0x0000ffff
++#define DBG_RD_DAT_CNT_I_MSK 0xffff0000
++#define DBG_RD_DAT_CNT_SFT 0
++#define DBG_RD_DAT_CNT_HI 15
++#define DBG_RD_DAT_CNT_SZ 16
++#define DBG_RD_STS_CNT_MSK 0xffff0000
++#define DBG_RD_STS_CNT_I_MSK 0x0000ffff
++#define DBG_RD_STS_CNT_SFT 16
++#define DBG_RD_STS_CNT_HI 31
++#define DBG_RD_STS_CNT_SZ 16
++#define DBG_JUDGE_CNT_MSK 0x0000ffff
++#define DBG_JUDGE_CNT_I_MSK 0xffff0000
++#define DBG_JUDGE_CNT_SFT 0
++#define DBG_JUDGE_CNT_HI 15
++#define DBG_JUDGE_CNT_SZ 16
++#define DBG_RD_STS_CNT_CLR_MSK 0x00010000
++#define DBG_RD_STS_CNT_CLR_I_MSK 0xfffeffff
++#define DBG_RD_STS_CNT_CLR_SFT 16
++#define DBG_RD_STS_CNT_CLR_HI 16
++#define DBG_RD_STS_CNT_CLR_SZ 1
++#define DBG_RD_DAT_CNT_CLR_MSK 0x00020000
++#define DBG_RD_DAT_CNT_CLR_I_MSK 0xfffdffff
++#define DBG_RD_DAT_CNT_CLR_SFT 17
++#define DBG_RD_DAT_CNT_CLR_HI 17
++#define DBG_RD_DAT_CNT_CLR_SZ 1
++#define DBG_JUDGE_CNT_CLR_MSK 0x00040000
++#define DBG_JUDGE_CNT_CLR_I_MSK 0xfffbffff
++#define DBG_JUDGE_CNT_CLR_SFT 18
++#define DBG_JUDGE_CNT_CLR_HI 18
++#define DBG_JUDGE_CNT_CLR_SZ 1
++#define DBG_TX_DONE_CNT_MSK 0x0000ffff
++#define DBG_TX_DONE_CNT_I_MSK 0xffff0000
++#define DBG_TX_DONE_CNT_SFT 0
++#define DBG_TX_DONE_CNT_HI 15
++#define DBG_TX_DONE_CNT_SZ 16
++#define DBG_TX_DISCARD_CNT_MSK 0xffff0000
++#define DBG_TX_DISCARD_CNT_I_MSK 0x0000ffff
++#define DBG_TX_DISCARD_CNT_SFT 16
++#define DBG_TX_DISCARD_CNT_HI 31
++#define DBG_TX_DISCARD_CNT_SZ 16
++#define DBG_TX_SET_CNT_MSK 0x0000ffff
++#define DBG_TX_SET_CNT_I_MSK 0xffff0000
++#define DBG_TX_SET_CNT_SFT 0
++#define DBG_TX_SET_CNT_HI 15
++#define DBG_TX_SET_CNT_SZ 16
++#define DBG_TX_DISCARD_CNT_CLR_MSK 0x00010000
++#define DBG_TX_DISCARD_CNT_CLR_I_MSK 0xfffeffff
++#define DBG_TX_DISCARD_CNT_CLR_SFT 16
++#define DBG_TX_DISCARD_CNT_CLR_HI 16
++#define DBG_TX_DISCARD_CNT_CLR_SZ 1
++#define DBG_TX_DONE_CNT_CLR_MSK 0x00020000
++#define DBG_TX_DONE_CNT_CLR_I_MSK 0xfffdffff
++#define DBG_TX_DONE_CNT_CLR_SFT 17
++#define DBG_TX_DONE_CNT_CLR_HI 17
++#define DBG_TX_DONE_CNT_CLR_SZ 1
++#define DBG_TX_SET_CNT_CLR_MSK 0x00040000
++#define DBG_TX_SET_CNT_CLR_I_MSK 0xfffbffff
++#define DBG_TX_SET_CNT_CLR_SFT 18
++#define DBG_TX_SET_CNT_CLR_HI 18
++#define DBG_TX_SET_CNT_CLR_SZ 1
++#define DBG_DAT_MODE_OFF_MSK 0x00080000
++#define DBG_DAT_MODE_OFF_I_MSK 0xfff7ffff
++#define DBG_DAT_MODE_OFF_SFT 19
++#define DBG_DAT_MODE_OFF_HI 19
++#define DBG_DAT_MODE_OFF_SZ 1
++#define DBG_TX_FIFO_RESIDUE_MSK 0x00700000
++#define DBG_TX_FIFO_RESIDUE_I_MSK 0xff8fffff
++#define DBG_TX_FIFO_RESIDUE_SFT 20
++#define DBG_TX_FIFO_RESIDUE_HI 22
++#define DBG_TX_FIFO_RESIDUE_SZ 3
++#define DBG_RX_FIFO_RESIDUE_MSK 0x07000000
++#define DBG_RX_FIFO_RESIDUE_I_MSK 0xf8ffffff
++#define DBG_RX_FIFO_RESIDUE_SFT 24
++#define DBG_RX_FIFO_RESIDUE_HI 26
++#define DBG_RX_FIFO_RESIDUE_SZ 3
++#define DBG_RX_RDY_MSK 0x00000001
++#define DBG_RX_RDY_I_MSK 0xfffffffe
++#define DBG_RX_RDY_SFT 0
++#define DBG_RX_RDY_HI 0
++#define DBG_RX_RDY_SZ 1
++#define DBG_SDIO_SYS_INT_MSK 0x00000004
++#define DBG_SDIO_SYS_INT_I_MSK 0xfffffffb
++#define DBG_SDIO_SYS_INT_SFT 2
++#define DBG_SDIO_SYS_INT_HI 2
++#define DBG_SDIO_SYS_INT_SZ 1
++#define DBG_EDCA0_LOWTHOLD_INT_MSK 0x00000008
++#define DBG_EDCA0_LOWTHOLD_INT_I_MSK 0xfffffff7
++#define DBG_EDCA0_LOWTHOLD_INT_SFT 3
++#define DBG_EDCA0_LOWTHOLD_INT_HI 3
++#define DBG_EDCA0_LOWTHOLD_INT_SZ 1
++#define DBG_EDCA1_LOWTHOLD_INT_MSK 0x00000010
++#define DBG_EDCA1_LOWTHOLD_INT_I_MSK 0xffffffef
++#define DBG_EDCA1_LOWTHOLD_INT_SFT 4
++#define DBG_EDCA1_LOWTHOLD_INT_HI 4
++#define DBG_EDCA1_LOWTHOLD_INT_SZ 1
++#define DBG_EDCA2_LOWTHOLD_INT_MSK 0x00000020
++#define DBG_EDCA2_LOWTHOLD_INT_I_MSK 0xffffffdf
++#define DBG_EDCA2_LOWTHOLD_INT_SFT 5
++#define DBG_EDCA2_LOWTHOLD_INT_HI 5
++#define DBG_EDCA2_LOWTHOLD_INT_SZ 1
++#define DBG_EDCA3_LOWTHOLD_INT_MSK 0x00000040
++#define DBG_EDCA3_LOWTHOLD_INT_I_MSK 0xffffffbf
++#define DBG_EDCA3_LOWTHOLD_INT_SFT 6
++#define DBG_EDCA3_LOWTHOLD_INT_HI 6
++#define DBG_EDCA3_LOWTHOLD_INT_SZ 1
++#define DBG_TX_LIMIT_INT_IN_MSK 0x00000080
++#define DBG_TX_LIMIT_INT_IN_I_MSK 0xffffff7f
++#define DBG_TX_LIMIT_INT_IN_SFT 7
++#define DBG_TX_LIMIT_INT_IN_HI 7
++#define DBG_TX_LIMIT_INT_IN_SZ 1
++#define DBG_SPI_FN1_MSK 0x00007f00
++#define DBG_SPI_FN1_I_MSK 0xffff80ff
++#define DBG_SPI_FN1_SFT 8
++#define DBG_SPI_FN1_HI 14
++#define DBG_SPI_FN1_SZ 7
++#define DBG_SPI_CLK_EN_INT_MSK 0x00008000
++#define DBG_SPI_CLK_EN_INT_I_MSK 0xffff7fff
++#define DBG_SPI_CLK_EN_INT_SFT 15
++#define DBG_SPI_CLK_EN_INT_HI 15
++#define DBG_SPI_CLK_EN_INT_SZ 1
++#define DBG_SPI_HOST_MASK_MSK 0x00ff0000
++#define DBG_SPI_HOST_MASK_I_MSK 0xff00ffff
++#define DBG_SPI_HOST_MASK_SFT 16
++#define DBG_SPI_HOST_MASK_HI 23
++#define DBG_SPI_HOST_MASK_SZ 8
++#define BOOT_ADDR_MSK 0x00ffffff
++#define BOOT_ADDR_I_MSK 0xff000000
++#define BOOT_ADDR_SFT 0
++#define BOOT_ADDR_HI 23
++#define BOOT_ADDR_SZ 24
++#define CHECK_SUM_FAIL_MSK 0x80000000
++#define CHECK_SUM_FAIL_I_MSK 0x7fffffff
++#define CHECK_SUM_FAIL_SFT 31
++#define CHECK_SUM_FAIL_HI 31
++#define CHECK_SUM_FAIL_SZ 1
++#define VERIFY_DATA_MSK 0xffffffff
++#define VERIFY_DATA_I_MSK 0x00000000
++#define VERIFY_DATA_SFT 0
++#define VERIFY_DATA_HI 31
++#define VERIFY_DATA_SZ 32
++#define FLASH_ADDR_MSK 0x00ffffff
++#define FLASH_ADDR_I_MSK 0xff000000
++#define FLASH_ADDR_SFT 0
++#define FLASH_ADDR_HI 23
++#define FLASH_ADDR_SZ 24
++#define FLASH_CMD_CLR_MSK 0x10000000
++#define FLASH_CMD_CLR_I_MSK 0xefffffff
++#define FLASH_CMD_CLR_SFT 28
++#define FLASH_CMD_CLR_HI 28
++#define FLASH_CMD_CLR_SZ 1
++#define FLASH_DMA_CLR_MSK 0x20000000
++#define FLASH_DMA_CLR_I_MSK 0xdfffffff
++#define FLASH_DMA_CLR_SFT 29
++#define FLASH_DMA_CLR_HI 29
++#define FLASH_DMA_CLR_SZ 1
++#define DMA_EN_MSK 0x40000000
++#define DMA_EN_I_MSK 0xbfffffff
++#define DMA_EN_SFT 30
++#define DMA_EN_HI 30
++#define DMA_EN_SZ 1
++#define DMA_BUSY_MSK 0x80000000
++#define DMA_BUSY_I_MSK 0x7fffffff
++#define DMA_BUSY_SFT 31
++#define DMA_BUSY_HI 31
++#define DMA_BUSY_SZ 1
++#define SRAM_ADDR_MSK 0xffffffff
++#define SRAM_ADDR_I_MSK 0x00000000
++#define SRAM_ADDR_SFT 0
++#define SRAM_ADDR_HI 31
++#define SRAM_ADDR_SZ 32
++#define FLASH_DMA_LEN_MSK 0xffffffff
++#define FLASH_DMA_LEN_I_MSK 0x00000000
++#define FLASH_DMA_LEN_SFT 0
++#define FLASH_DMA_LEN_HI 31
++#define FLASH_DMA_LEN_SZ 32
++#define FLASH_FRONT_DLY_MSK 0x0000ffff
++#define FLASH_FRONT_DLY_I_MSK 0xffff0000
++#define FLASH_FRONT_DLY_SFT 0
++#define FLASH_FRONT_DLY_HI 15
++#define FLASH_FRONT_DLY_SZ 16
++#define FLASH_BACK_DLY_MSK 0xffff0000
++#define FLASH_BACK_DLY_I_MSK 0x0000ffff
++#define FLASH_BACK_DLY_SFT 16
++#define FLASH_BACK_DLY_HI 31
++#define FLASH_BACK_DLY_SZ 16
++#define FLASH_CLK_WIDTH_MSK 0x0000ffff
++#define FLASH_CLK_WIDTH_I_MSK 0xffff0000
++#define FLASH_CLK_WIDTH_SFT 0
++#define FLASH_CLK_WIDTH_HI 15
++#define FLASH_CLK_WIDTH_SZ 16
++#define SPI_BUSY_MSK 0x00010000
++#define SPI_BUSY_I_MSK 0xfffeffff
++#define SPI_BUSY_SFT 16
++#define SPI_BUSY_HI 16
++#define SPI_BUSY_SZ 1
++#define FLS_REMAP_MSK 0x00020000
++#define FLS_REMAP_I_MSK 0xfffdffff
++#define FLS_REMAP_SFT 17
++#define FLS_REMAP_HI 17
++#define FLS_REMAP_SZ 1
++#define PBUS_SWP_MSK 0x00040000
++#define PBUS_SWP_I_MSK 0xfffbffff
++#define PBUS_SWP_SFT 18
++#define PBUS_SWP_HI 18
++#define PBUS_SWP_SZ 1
++#define BIT_MODE1_MSK 0x00080000
++#define BIT_MODE1_I_MSK 0xfff7ffff
++#define BIT_MODE1_SFT 19
++#define BIT_MODE1_HI 19
++#define BIT_MODE1_SZ 1
++#define BIT_MODE2_MSK 0x00100000
++#define BIT_MODE2_I_MSK 0xffefffff
++#define BIT_MODE2_SFT 20
++#define BIT_MODE2_HI 20
++#define BIT_MODE2_SZ 1
++#define BIT_MODE4_MSK 0x00200000
++#define BIT_MODE4_I_MSK 0xffdfffff
++#define BIT_MODE4_SFT 21
++#define BIT_MODE4_HI 21
++#define BIT_MODE4_SZ 1
++#define BOOT_CHECK_SUM_MSK 0xffffffff
++#define BOOT_CHECK_SUM_I_MSK 0x00000000
++#define BOOT_CHECK_SUM_SFT 0
++#define BOOT_CHECK_SUM_HI 31
++#define BOOT_CHECK_SUM_SZ 32
++#define CHECK_SUM_TAG_MSK 0xffffffff
++#define CHECK_SUM_TAG_I_MSK 0x00000000
++#define CHECK_SUM_TAG_SFT 0
++#define CHECK_SUM_TAG_HI 31
++#define CHECK_SUM_TAG_SZ 32
++#define CMD_LEN_MSK 0x0000ffff
++#define CMD_LEN_I_MSK 0xffff0000
++#define CMD_LEN_SFT 0
++#define CMD_LEN_HI 15
++#define CMD_LEN_SZ 16
++#define CMD_ADDR_MSK 0xffffffff
++#define CMD_ADDR_I_MSK 0x00000000
++#define CMD_ADDR_SFT 0
++#define CMD_ADDR_HI 31
++#define CMD_ADDR_SZ 32
++#define DMA_ADR_SRC_MSK 0xffffffff
++#define DMA_ADR_SRC_I_MSK 0x00000000
++#define DMA_ADR_SRC_SFT 0
++#define DMA_ADR_SRC_HI 31
++#define DMA_ADR_SRC_SZ 32
++#define DMA_ADR_DST_MSK 0xffffffff
++#define DMA_ADR_DST_I_MSK 0x00000000
++#define DMA_ADR_DST_SFT 0
++#define DMA_ADR_DST_HI 31
++#define DMA_ADR_DST_SZ 32
++#define DMA_SRC_SIZE_MSK 0x00000007
++#define DMA_SRC_SIZE_I_MSK 0xfffffff8
++#define DMA_SRC_SIZE_SFT 0
++#define DMA_SRC_SIZE_HI 2
++#define DMA_SRC_SIZE_SZ 3
++#define DMA_SRC_INC_MSK 0x00000008
++#define DMA_SRC_INC_I_MSK 0xfffffff7
++#define DMA_SRC_INC_SFT 3
++#define DMA_SRC_INC_HI 3
++#define DMA_SRC_INC_SZ 1
++#define DMA_DST_SIZE_MSK 0x00000070
++#define DMA_DST_SIZE_I_MSK 0xffffff8f
++#define DMA_DST_SIZE_SFT 4
++#define DMA_DST_SIZE_HI 6
++#define DMA_DST_SIZE_SZ 3
++#define DMA_DST_INC_MSK 0x00000080
++#define DMA_DST_INC_I_MSK 0xffffff7f
++#define DMA_DST_INC_SFT 7
++#define DMA_DST_INC_HI 7
++#define DMA_DST_INC_SZ 1
++#define DMA_FAST_FILL_MSK 0x00000100
++#define DMA_FAST_FILL_I_MSK 0xfffffeff
++#define DMA_FAST_FILL_SFT 8
++#define DMA_FAST_FILL_HI 8
++#define DMA_FAST_FILL_SZ 1
++#define DMA_SDIO_KICK_MSK 0x00001000
++#define DMA_SDIO_KICK_I_MSK 0xffffefff
++#define DMA_SDIO_KICK_SFT 12
++#define DMA_SDIO_KICK_HI 12
++#define DMA_SDIO_KICK_SZ 1
++#define DMA_BADR_EN_MSK 0x00002000
++#define DMA_BADR_EN_I_MSK 0xffffdfff
++#define DMA_BADR_EN_SFT 13
++#define DMA_BADR_EN_HI 13
++#define DMA_BADR_EN_SZ 1
++#define DMA_LEN_MSK 0xffff0000
++#define DMA_LEN_I_MSK 0x0000ffff
++#define DMA_LEN_SFT 16
++#define DMA_LEN_HI 31
++#define DMA_LEN_SZ 16
++#define DMA_INT_MASK_MSK 0x00000001
++#define DMA_INT_MASK_I_MSK 0xfffffffe
++#define DMA_INT_MASK_SFT 0
++#define DMA_INT_MASK_HI 0
++#define DMA_INT_MASK_SZ 1
++#define DMA_STS_MSK 0x00000100
++#define DMA_STS_I_MSK 0xfffffeff
++#define DMA_STS_SFT 8
++#define DMA_STS_HI 8
++#define DMA_STS_SZ 1
++#define DMA_FINISH_MSK 0x80000000
++#define DMA_FINISH_I_MSK 0x7fffffff
++#define DMA_FINISH_SFT 31
++#define DMA_FINISH_HI 31
++#define DMA_FINISH_SZ 1
++#define DMA_CONST_MSK 0xffffffff
++#define DMA_CONST_I_MSK 0x00000000
++#define DMA_CONST_SFT 0
++#define DMA_CONST_HI 31
++#define DMA_CONST_SZ 32
++#define SLEEP_WAKE_CNT_MSK 0x00ffffff
++#define SLEEP_WAKE_CNT_I_MSK 0xff000000
++#define SLEEP_WAKE_CNT_SFT 0
++#define SLEEP_WAKE_CNT_HI 23
++#define SLEEP_WAKE_CNT_SZ 24
++#define RG_DLDO_LEVEL_MSK 0x07000000
++#define RG_DLDO_LEVEL_I_MSK 0xf8ffffff
++#define RG_DLDO_LEVEL_SFT 24
++#define RG_DLDO_LEVEL_HI 26
++#define RG_DLDO_LEVEL_SZ 3
++#define RG_DLDO_BOOST_IQ_MSK 0x08000000
++#define RG_DLDO_BOOST_IQ_I_MSK 0xf7ffffff
++#define RG_DLDO_BOOST_IQ_SFT 27
++#define RG_DLDO_BOOST_IQ_HI 27
++#define RG_DLDO_BOOST_IQ_SZ 1
++#define RG_BUCK_LEVEL_MSK 0x70000000
++#define RG_BUCK_LEVEL_I_MSK 0x8fffffff
++#define RG_BUCK_LEVEL_SFT 28
++#define RG_BUCK_LEVEL_HI 30
++#define RG_BUCK_LEVEL_SZ 3
++#define RG_BUCK_VREF_SEL_MSK 0x80000000
++#define RG_BUCK_VREF_SEL_I_MSK 0x7fffffff
++#define RG_BUCK_VREF_SEL_SFT 31
++#define RG_BUCK_VREF_SEL_HI 31
++#define RG_BUCK_VREF_SEL_SZ 1
++#define RG_RTC_OSC_RES_SW_MANUAL_MSK 0x000003ff
++#define RG_RTC_OSC_RES_SW_MANUAL_I_MSK 0xfffffc00
++#define RG_RTC_OSC_RES_SW_MANUAL_SFT 0
++#define RG_RTC_OSC_RES_SW_MANUAL_HI 9
++#define RG_RTC_OSC_RES_SW_MANUAL_SZ 10
++#define RG_RTC_OSC_RES_SW_MSK 0x03ff0000
++#define RG_RTC_OSC_RES_SW_I_MSK 0xfc00ffff
++#define RG_RTC_OSC_RES_SW_SFT 16
++#define RG_RTC_OSC_RES_SW_HI 25
++#define RG_RTC_OSC_RES_SW_SZ 10
++#define RTC_OSC_CAL_RES_RDY_MSK 0x80000000
++#define RTC_OSC_CAL_RES_RDY_I_MSK 0x7fffffff
++#define RTC_OSC_CAL_RES_RDY_SFT 31
++#define RTC_OSC_CAL_RES_RDY_HI 31
++#define RTC_OSC_CAL_RES_RDY_SZ 1
++#define RG_DCDC_MODE_MSK 0x00000001
++#define RG_DCDC_MODE_I_MSK 0xfffffffe
++#define RG_DCDC_MODE_SFT 0
++#define RG_DCDC_MODE_HI 0
++#define RG_DCDC_MODE_SZ 1
++#define RG_BUCK_EN_PSM_MSK 0x00000010
++#define RG_BUCK_EN_PSM_I_MSK 0xffffffef
++#define RG_BUCK_EN_PSM_SFT 4
++#define RG_BUCK_EN_PSM_HI 4
++#define RG_BUCK_EN_PSM_SZ 1
++#define RG_BUCK_PSM_VTH_MSK 0x00000100
++#define RG_BUCK_PSM_VTH_I_MSK 0xfffffeff
++#define RG_BUCK_PSM_VTH_SFT 8
++#define RG_BUCK_PSM_VTH_HI 8
++#define RG_BUCK_PSM_VTH_SZ 1
++#define RG_RTC_OSC_RES_SW_MANUAL_EN_MSK 0x00001000
++#define RG_RTC_OSC_RES_SW_MANUAL_EN_I_MSK 0xffffefff
++#define RG_RTC_OSC_RES_SW_MANUAL_EN_SFT 12
++#define RG_RTC_OSC_RES_SW_MANUAL_EN_HI 12
++#define RG_RTC_OSC_RES_SW_MANUAL_EN_SZ 1
++#define RG_RTC_RDY_DEGLITCH_TIMER_MSK 0x00006000
++#define RG_RTC_RDY_DEGLITCH_TIMER_I_MSK 0xffff9fff
++#define RG_RTC_RDY_DEGLITCH_TIMER_SFT 13
++#define RG_RTC_RDY_DEGLITCH_TIMER_HI 14
++#define RG_RTC_RDY_DEGLITCH_TIMER_SZ 2
++#define RTC_CAL_ENA_MSK 0x00010000
++#define RTC_CAL_ENA_I_MSK 0xfffeffff
++#define RTC_CAL_ENA_SFT 16
++#define RTC_CAL_ENA_HI 16
++#define RTC_CAL_ENA_SZ 1
++#define PMU_WAKE_TRIG_EVENT_MSK 0x00000003
++#define PMU_WAKE_TRIG_EVENT_I_MSK 0xfffffffc
++#define PMU_WAKE_TRIG_EVENT_SFT 0
++#define PMU_WAKE_TRIG_EVENT_HI 1
++#define PMU_WAKE_TRIG_EVENT_SZ 2
++#define DIGI_TOP_POR_MASK_MSK 0x00000010
++#define DIGI_TOP_POR_MASK_I_MSK 0xffffffef
++#define DIGI_TOP_POR_MASK_SFT 4
++#define DIGI_TOP_POR_MASK_HI 4
++#define DIGI_TOP_POR_MASK_SZ 1
++#define PMU_ENTER_SLEEP_MODE_MSK 0x00000100
++#define PMU_ENTER_SLEEP_MODE_I_MSK 0xfffffeff
++#define PMU_ENTER_SLEEP_MODE_SFT 8
++#define PMU_ENTER_SLEEP_MODE_HI 8
++#define PMU_ENTER_SLEEP_MODE_SZ 1
++#define RG_RTC_DUMMIES_MSK 0xffff0000
++#define RG_RTC_DUMMIES_I_MSK 0x0000ffff
++#define RG_RTC_DUMMIES_SFT 16
++#define RG_RTC_DUMMIES_HI 31
++#define RG_RTC_DUMMIES_SZ 16
++#define RTC_EN_MSK 0x00000001
++#define RTC_EN_I_MSK 0xfffffffe
++#define RTC_EN_SFT 0
++#define RTC_EN_HI 0
++#define RTC_EN_SZ 1
++#define RTC_SRC_MSK 0x00000002
++#define RTC_SRC_I_MSK 0xfffffffd
++#define RTC_SRC_SFT 1
++#define RTC_SRC_HI 1
++#define RTC_SRC_SZ 1
++#define RTC_TICK_CNT_MSK 0x7fff0000
++#define RTC_TICK_CNT_I_MSK 0x8000ffff
++#define RTC_TICK_CNT_SFT 16
++#define RTC_TICK_CNT_HI 30
++#define RTC_TICK_CNT_SZ 15
++#define RTC_INT_SEC_MASK_MSK 0x00000001
++#define RTC_INT_SEC_MASK_I_MSK 0xfffffffe
++#define RTC_INT_SEC_MASK_SFT 0
++#define RTC_INT_SEC_MASK_HI 0
++#define RTC_INT_SEC_MASK_SZ 1
++#define RTC_INT_ALARM_MASK_MSK 0x00000002
++#define RTC_INT_ALARM_MASK_I_MSK 0xfffffffd
++#define RTC_INT_ALARM_MASK_SFT 1
++#define RTC_INT_ALARM_MASK_HI 1
++#define RTC_INT_ALARM_MASK_SZ 1
++#define RTC_INT_SEC_MSK 0x00010000
++#define RTC_INT_SEC_I_MSK 0xfffeffff
++#define RTC_INT_SEC_SFT 16
++#define RTC_INT_SEC_HI 16
++#define RTC_INT_SEC_SZ 1
++#define RTC_INT_ALARM_MSK 0x00020000
++#define RTC_INT_ALARM_I_MSK 0xfffdffff
++#define RTC_INT_ALARM_SFT 17
++#define RTC_INT_ALARM_HI 17
++#define RTC_INT_ALARM_SZ 1
++#define RTC_SEC_START_CNT_MSK 0xffffffff
++#define RTC_SEC_START_CNT_I_MSK 0x00000000
++#define RTC_SEC_START_CNT_SFT 0
++#define RTC_SEC_START_CNT_HI 31
++#define RTC_SEC_START_CNT_SZ 32
++#define RTC_SEC_CNT_MSK 0xffffffff
++#define RTC_SEC_CNT_I_MSK 0x00000000
++#define RTC_SEC_CNT_SFT 0
++#define RTC_SEC_CNT_HI 31
++#define RTC_SEC_CNT_SZ 32
++#define RTC_SEC_ALARM_VALUE_MSK 0xffffffff
++#define RTC_SEC_ALARM_VALUE_I_MSK 0x00000000
++#define RTC_SEC_ALARM_VALUE_SFT 0
++#define RTC_SEC_ALARM_VALUE_HI 31
++#define RTC_SEC_ALARM_VALUE_SZ 32
++#define D2_DMA_ADR_SRC_MSK 0xffffffff
++#define D2_DMA_ADR_SRC_I_MSK 0x00000000
++#define D2_DMA_ADR_SRC_SFT 0
++#define D2_DMA_ADR_SRC_HI 31
++#define D2_DMA_ADR_SRC_SZ 32
++#define D2_DMA_ADR_DST_MSK 0xffffffff
++#define D2_DMA_ADR_DST_I_MSK 0x00000000
++#define D2_DMA_ADR_DST_SFT 0
++#define D2_DMA_ADR_DST_HI 31
++#define D2_DMA_ADR_DST_SZ 32
++#define D2_DMA_SRC_SIZE_MSK 0x00000007
++#define D2_DMA_SRC_SIZE_I_MSK 0xfffffff8
++#define D2_DMA_SRC_SIZE_SFT 0
++#define D2_DMA_SRC_SIZE_HI 2
++#define D2_DMA_SRC_SIZE_SZ 3
++#define D2_DMA_SRC_INC_MSK 0x00000008
++#define D2_DMA_SRC_INC_I_MSK 0xfffffff7
++#define D2_DMA_SRC_INC_SFT 3
++#define D2_DMA_SRC_INC_HI 3
++#define D2_DMA_SRC_INC_SZ 1
++#define D2_DMA_DST_SIZE_MSK 0x00000070
++#define D2_DMA_DST_SIZE_I_MSK 0xffffff8f
++#define D2_DMA_DST_SIZE_SFT 4
++#define D2_DMA_DST_SIZE_HI 6
++#define D2_DMA_DST_SIZE_SZ 3
++#define D2_DMA_DST_INC_MSK 0x00000080
++#define D2_DMA_DST_INC_I_MSK 0xffffff7f
++#define D2_DMA_DST_INC_SFT 7
++#define D2_DMA_DST_INC_HI 7
++#define D2_DMA_DST_INC_SZ 1
++#define D2_DMA_FAST_FILL_MSK 0x00000100
++#define D2_DMA_FAST_FILL_I_MSK 0xfffffeff
++#define D2_DMA_FAST_FILL_SFT 8
++#define D2_DMA_FAST_FILL_HI 8
++#define D2_DMA_FAST_FILL_SZ 1
++#define D2_DMA_SDIO_KICK_MSK 0x00001000
++#define D2_DMA_SDIO_KICK_I_MSK 0xffffefff
++#define D2_DMA_SDIO_KICK_SFT 12
++#define D2_DMA_SDIO_KICK_HI 12
++#define D2_DMA_SDIO_KICK_SZ 1
++#define D2_DMA_BADR_EN_MSK 0x00002000
++#define D2_DMA_BADR_EN_I_MSK 0xffffdfff
++#define D2_DMA_BADR_EN_SFT 13
++#define D2_DMA_BADR_EN_HI 13
++#define D2_DMA_BADR_EN_SZ 1
++#define D2_DMA_LEN_MSK 0xffff0000
++#define D2_DMA_LEN_I_MSK 0x0000ffff
++#define D2_DMA_LEN_SFT 16
++#define D2_DMA_LEN_HI 31
++#define D2_DMA_LEN_SZ 16
++#define D2_DMA_INT_MASK_MSK 0x00000001
++#define D2_DMA_INT_MASK_I_MSK 0xfffffffe
++#define D2_DMA_INT_MASK_SFT 0
++#define D2_DMA_INT_MASK_HI 0
++#define D2_DMA_INT_MASK_SZ 1
++#define D2_DMA_STS_MSK 0x00000100
++#define D2_DMA_STS_I_MSK 0xfffffeff
++#define D2_DMA_STS_SFT 8
++#define D2_DMA_STS_HI 8
++#define D2_DMA_STS_SZ 1
++#define D2_DMA_FINISH_MSK 0x80000000
++#define D2_DMA_FINISH_I_MSK 0x7fffffff
++#define D2_DMA_FINISH_SFT 31
++#define D2_DMA_FINISH_HI 31
++#define D2_DMA_FINISH_SZ 1
++#define D2_DMA_CONST_MSK 0xffffffff
++#define D2_DMA_CONST_I_MSK 0x00000000
++#define D2_DMA_CONST_SFT 0
++#define D2_DMA_CONST_HI 31
++#define D2_DMA_CONST_SZ 32
++#define TRAP_UNKNOWN_TYPE_MSK 0x00000001
++#define TRAP_UNKNOWN_TYPE_I_MSK 0xfffffffe
++#define TRAP_UNKNOWN_TYPE_SFT 0
++#define TRAP_UNKNOWN_TYPE_HI 0
++#define TRAP_UNKNOWN_TYPE_SZ 1
++#define TX_ON_DEMAND_ENA_MSK 0x00000002
++#define TX_ON_DEMAND_ENA_I_MSK 0xfffffffd
++#define TX_ON_DEMAND_ENA_SFT 1
++#define TX_ON_DEMAND_ENA_HI 1
++#define TX_ON_DEMAND_ENA_SZ 1
++#define RX_2_HOST_MSK 0x00000004
++#define RX_2_HOST_I_MSK 0xfffffffb
++#define RX_2_HOST_SFT 2
++#define RX_2_HOST_HI 2
++#define RX_2_HOST_SZ 1
++#define AUTO_SEQNO_MSK 0x00000008
++#define AUTO_SEQNO_I_MSK 0xfffffff7
++#define AUTO_SEQNO_SFT 3
++#define AUTO_SEQNO_HI 3
++#define AUTO_SEQNO_SZ 1
++#define BYPASSS_TX_PARSER_ENCAP_MSK 0x00000010
++#define BYPASSS_TX_PARSER_ENCAP_I_MSK 0xffffffef
++#define BYPASSS_TX_PARSER_ENCAP_SFT 4
++#define BYPASSS_TX_PARSER_ENCAP_HI 4
++#define BYPASSS_TX_PARSER_ENCAP_SZ 1
++#define HDR_STRIP_MSK 0x00000020
++#define HDR_STRIP_I_MSK 0xffffffdf
++#define HDR_STRIP_SFT 5
++#define HDR_STRIP_HI 5
++#define HDR_STRIP_SZ 1
++#define ERP_PROTECT_MSK 0x000000c0
++#define ERP_PROTECT_I_MSK 0xffffff3f
++#define ERP_PROTECT_SFT 6
++#define ERP_PROTECT_HI 7
++#define ERP_PROTECT_SZ 2
++#define PRO_VER_MSK 0x00000300
++#define PRO_VER_I_MSK 0xfffffcff
++#define PRO_VER_SFT 8
++#define PRO_VER_HI 9
++#define PRO_VER_SZ 2
++#define TXQ_ID0_MSK 0x00007000
++#define TXQ_ID0_I_MSK 0xffff8fff
++#define TXQ_ID0_SFT 12
++#define TXQ_ID0_HI 14
++#define TXQ_ID0_SZ 3
++#define TXQ_ID1_MSK 0x00070000
++#define TXQ_ID1_I_MSK 0xfff8ffff
++#define TXQ_ID1_SFT 16
++#define TXQ_ID1_HI 18
++#define TXQ_ID1_SZ 3
++#define TX_ETHER_TRAP_EN_MSK 0x00100000
++#define TX_ETHER_TRAP_EN_I_MSK 0xffefffff
++#define TX_ETHER_TRAP_EN_SFT 20
++#define TX_ETHER_TRAP_EN_HI 20
++#define TX_ETHER_TRAP_EN_SZ 1
++#define RX_ETHER_TRAP_EN_MSK 0x00200000
++#define RX_ETHER_TRAP_EN_I_MSK 0xffdfffff
++#define RX_ETHER_TRAP_EN_SFT 21
++#define RX_ETHER_TRAP_EN_HI 21
++#define RX_ETHER_TRAP_EN_SZ 1
++#define RX_NULL_TRAP_EN_MSK 0x00400000
++#define RX_NULL_TRAP_EN_I_MSK 0xffbfffff
++#define RX_NULL_TRAP_EN_SFT 22
++#define RX_NULL_TRAP_EN_HI 22
++#define RX_NULL_TRAP_EN_SZ 1
++#define RX_GET_TX_QUEUE_EN_MSK 0x02000000
++#define RX_GET_TX_QUEUE_EN_I_MSK 0xfdffffff
++#define RX_GET_TX_QUEUE_EN_SFT 25
++#define RX_GET_TX_QUEUE_EN_HI 25
++#define RX_GET_TX_QUEUE_EN_SZ 1
++#define HCI_INQ_SEL_MSK 0x04000000
++#define HCI_INQ_SEL_I_MSK 0xfbffffff
++#define HCI_INQ_SEL_SFT 26
++#define HCI_INQ_SEL_HI 26
++#define HCI_INQ_SEL_SZ 1
++#define TRX_DEBUG_CNT_ENA_MSK 0x10000000
++#define TRX_DEBUG_CNT_ENA_I_MSK 0xefffffff
++#define TRX_DEBUG_CNT_ENA_SFT 28
++#define TRX_DEBUG_CNT_ENA_HI 28
++#define TRX_DEBUG_CNT_ENA_SZ 1
++#define WAKE_SOON_WITH_SCK_MSK 0x00000001
++#define WAKE_SOON_WITH_SCK_I_MSK 0xfffffffe
++#define WAKE_SOON_WITH_SCK_SFT 0
++#define WAKE_SOON_WITH_SCK_HI 0
++#define WAKE_SOON_WITH_SCK_SZ 1
++#define TX_FLOW_CTRL_MSK 0x0000ffff
++#define TX_FLOW_CTRL_I_MSK 0xffff0000
++#define TX_FLOW_CTRL_SFT 0
++#define TX_FLOW_CTRL_HI 15
++#define TX_FLOW_CTRL_SZ 16
++#define TX_FLOW_MGMT_MSK 0xffff0000
++#define TX_FLOW_MGMT_I_MSK 0x0000ffff
++#define TX_FLOW_MGMT_SFT 16
++#define TX_FLOW_MGMT_HI 31
++#define TX_FLOW_MGMT_SZ 16
++#define TX_FLOW_DATA_MSK 0xffffffff
++#define TX_FLOW_DATA_I_MSK 0x00000000
++#define TX_FLOW_DATA_SFT 0
++#define TX_FLOW_DATA_HI 31
++#define TX_FLOW_DATA_SZ 32
++#define DOT11RTSTHRESHOLD_MSK 0xffff0000
++#define DOT11RTSTHRESHOLD_I_MSK 0x0000ffff
++#define DOT11RTSTHRESHOLD_SFT 16
++#define DOT11RTSTHRESHOLD_HI 31
++#define DOT11RTSTHRESHOLD_SZ 16
++#define TXF_ID_MSK 0x0000003f
++#define TXF_ID_I_MSK 0xffffffc0
++#define TXF_ID_SFT 0
++#define TXF_ID_HI 5
++#define TXF_ID_SZ 6
++#define SEQ_CTRL_MSK 0x0000ffff
++#define SEQ_CTRL_I_MSK 0xffff0000
++#define SEQ_CTRL_SFT 0
++#define SEQ_CTRL_HI 15
++#define SEQ_CTRL_SZ 16
++#define TX_PBOFFSET_MSK 0x000000ff
++#define TX_PBOFFSET_I_MSK 0xffffff00
++#define TX_PBOFFSET_SFT 0
++#define TX_PBOFFSET_HI 7
++#define TX_PBOFFSET_SZ 8
++#define TX_INFO_SIZE_MSK 0x0000ff00
++#define TX_INFO_SIZE_I_MSK 0xffff00ff
++#define TX_INFO_SIZE_SFT 8
++#define TX_INFO_SIZE_HI 15
++#define TX_INFO_SIZE_SZ 8
++#define RX_INFO_SIZE_MSK 0x00ff0000
++#define RX_INFO_SIZE_I_MSK 0xff00ffff
++#define RX_INFO_SIZE_SFT 16
++#define RX_INFO_SIZE_HI 23
++#define RX_INFO_SIZE_SZ 8
++#define RX_LAST_PHY_SIZE_MSK 0xff000000
++#define RX_LAST_PHY_SIZE_I_MSK 0x00ffffff
++#define RX_LAST_PHY_SIZE_SFT 24
++#define RX_LAST_PHY_SIZE_HI 31
++#define RX_LAST_PHY_SIZE_SZ 8
++#define TX_INFO_CLEAR_SIZE_MSK 0x0000003f
++#define TX_INFO_CLEAR_SIZE_I_MSK 0xffffffc0
++#define TX_INFO_CLEAR_SIZE_SFT 0
++#define TX_INFO_CLEAR_SIZE_HI 5
++#define TX_INFO_CLEAR_SIZE_SZ 6
++#define TX_INFO_CLEAR_ENABLE_MSK 0x00000100
++#define TX_INFO_CLEAR_ENABLE_I_MSK 0xfffffeff
++#define TX_INFO_CLEAR_ENABLE_SFT 8
++#define TX_INFO_CLEAR_ENABLE_HI 8
++#define TX_INFO_CLEAR_ENABLE_SZ 1
++#define TXTRAP_ETHTYPE1_MSK 0x0000ffff
++#define TXTRAP_ETHTYPE1_I_MSK 0xffff0000
++#define TXTRAP_ETHTYPE1_SFT 0
++#define TXTRAP_ETHTYPE1_HI 15
++#define TXTRAP_ETHTYPE1_SZ 16
++#define TXTRAP_ETHTYPE0_MSK 0xffff0000
++#define TXTRAP_ETHTYPE0_I_MSK 0x0000ffff
++#define TXTRAP_ETHTYPE0_SFT 16
++#define TXTRAP_ETHTYPE0_HI 31
++#define TXTRAP_ETHTYPE0_SZ 16
++#define RXTRAP_ETHTYPE1_MSK 0x0000ffff
++#define RXTRAP_ETHTYPE1_I_MSK 0xffff0000
++#define RXTRAP_ETHTYPE1_SFT 0
++#define RXTRAP_ETHTYPE1_HI 15
++#define RXTRAP_ETHTYPE1_SZ 16
++#define RXTRAP_ETHTYPE0_MSK 0xffff0000
++#define RXTRAP_ETHTYPE0_I_MSK 0x0000ffff
++#define RXTRAP_ETHTYPE0_SFT 16
++#define RXTRAP_ETHTYPE0_HI 31
++#define RXTRAP_ETHTYPE0_SZ 16
++#define TX_PKT_COUNTER_MSK 0xffffffff
++#define TX_PKT_COUNTER_I_MSK 0x00000000
++#define TX_PKT_COUNTER_SFT 0
++#define TX_PKT_COUNTER_HI 31
++#define TX_PKT_COUNTER_SZ 32
++#define RX_PKT_COUNTER_MSK 0xffffffff
++#define RX_PKT_COUNTER_I_MSK 0x00000000
++#define RX_PKT_COUNTER_SFT 0
++#define RX_PKT_COUNTER_HI 31
++#define RX_PKT_COUNTER_SZ 32
++#define HOST_CMD_COUNTER_MSK 0x000000ff
++#define HOST_CMD_COUNTER_I_MSK 0xffffff00
++#define HOST_CMD_COUNTER_SFT 0
++#define HOST_CMD_COUNTER_HI 7
++#define HOST_CMD_COUNTER_SZ 8
++#define HOST_EVENT_COUNTER_MSK 0x000000ff
++#define HOST_EVENT_COUNTER_I_MSK 0xffffff00
++#define HOST_EVENT_COUNTER_SFT 0
++#define HOST_EVENT_COUNTER_HI 7
++#define HOST_EVENT_COUNTER_SZ 8
++#define TX_PKT_DROP_COUNTER_MSK 0x000000ff
++#define TX_PKT_DROP_COUNTER_I_MSK 0xffffff00
++#define TX_PKT_DROP_COUNTER_SFT 0
++#define TX_PKT_DROP_COUNTER_HI 7
++#define TX_PKT_DROP_COUNTER_SZ 8
++#define RX_PKT_DROP_COUNTER_MSK 0x000000ff
++#define RX_PKT_DROP_COUNTER_I_MSK 0xffffff00
++#define RX_PKT_DROP_COUNTER_SFT 0
++#define RX_PKT_DROP_COUNTER_HI 7
++#define RX_PKT_DROP_COUNTER_SZ 8
++#define TX_PKT_TRAP_COUNTER_MSK 0x000000ff
++#define TX_PKT_TRAP_COUNTER_I_MSK 0xffffff00
++#define TX_PKT_TRAP_COUNTER_SFT 0
++#define TX_PKT_TRAP_COUNTER_HI 7
++#define TX_PKT_TRAP_COUNTER_SZ 8
++#define RX_PKT_TRAP_COUNTER_MSK 0x000000ff
++#define RX_PKT_TRAP_COUNTER_I_MSK 0xffffff00
++#define RX_PKT_TRAP_COUNTER_SFT 0
++#define RX_PKT_TRAP_COUNTER_HI 7
++#define RX_PKT_TRAP_COUNTER_SZ 8
++#define HOST_TX_FAIL_COUNTER_MSK 0x000000ff
++#define HOST_TX_FAIL_COUNTER_I_MSK 0xffffff00
++#define HOST_TX_FAIL_COUNTER_SFT 0
++#define HOST_TX_FAIL_COUNTER_HI 7
++#define HOST_TX_FAIL_COUNTER_SZ 8
++#define HOST_RX_FAIL_COUNTER_MSK 0x000000ff
++#define HOST_RX_FAIL_COUNTER_I_MSK 0xffffff00
++#define HOST_RX_FAIL_COUNTER_SFT 0
++#define HOST_RX_FAIL_COUNTER_HI 7
++#define HOST_RX_FAIL_COUNTER_SZ 8
++#define HCI_STATE_MONITOR_MSK 0xffffffff
++#define HCI_STATE_MONITOR_I_MSK 0x00000000
++#define HCI_STATE_MONITOR_SFT 0
++#define HCI_STATE_MONITOR_HI 31
++#define HCI_STATE_MONITOR_SZ 32
++#define HCI_ST_TIMEOUT_MONITOR_MSK 0xffffffff
++#define HCI_ST_TIMEOUT_MONITOR_I_MSK 0x00000000
++#define HCI_ST_TIMEOUT_MONITOR_SFT 0
++#define HCI_ST_TIMEOUT_MONITOR_HI 31
++#define HCI_ST_TIMEOUT_MONITOR_SZ 32
++#define TX_ON_DEMAND_LENGTH_MSK 0xffffffff
++#define TX_ON_DEMAND_LENGTH_I_MSK 0x00000000
++#define TX_ON_DEMAND_LENGTH_SFT 0
++#define TX_ON_DEMAND_LENGTH_HI 31
++#define TX_ON_DEMAND_LENGTH_SZ 32
++#define HCI_MONITOR_REG1_MSK 0xffffffff
++#define HCI_MONITOR_REG1_I_MSK 0x00000000
++#define HCI_MONITOR_REG1_SFT 0
++#define HCI_MONITOR_REG1_HI 31
++#define HCI_MONITOR_REG1_SZ 32
++#define HCI_MONITOR_REG2_MSK 0xffffffff
++#define HCI_MONITOR_REG2_I_MSK 0x00000000
++#define HCI_MONITOR_REG2_SFT 0
++#define HCI_MONITOR_REG2_HI 31
++#define HCI_MONITOR_REG2_SZ 32
++#define HCI_TX_ALLOC_TIME_31_0_MSK 0xffffffff
++#define HCI_TX_ALLOC_TIME_31_0_I_MSK 0x00000000
++#define HCI_TX_ALLOC_TIME_31_0_SFT 0
++#define HCI_TX_ALLOC_TIME_31_0_HI 31
++#define HCI_TX_ALLOC_TIME_31_0_SZ 32
++#define HCI_TX_ALLOC_TIME_47_32_MSK 0x0000ffff
++#define HCI_TX_ALLOC_TIME_47_32_I_MSK 0xffff0000
++#define HCI_TX_ALLOC_TIME_47_32_SFT 0
++#define HCI_TX_ALLOC_TIME_47_32_HI 15
++#define HCI_TX_ALLOC_TIME_47_32_SZ 16
++#define HCI_MB_MAX_CNT_MSK 0x00ff0000
++#define HCI_MB_MAX_CNT_I_MSK 0xff00ffff
++#define HCI_MB_MAX_CNT_SFT 16
++#define HCI_MB_MAX_CNT_HI 23
++#define HCI_MB_MAX_CNT_SZ 8
++#define HCI_TX_ALLOC_CNT_31_0_MSK 0xffffffff
++#define HCI_TX_ALLOC_CNT_31_0_I_MSK 0x00000000
++#define HCI_TX_ALLOC_CNT_31_0_SFT 0
++#define HCI_TX_ALLOC_CNT_31_0_HI 31
++#define HCI_TX_ALLOC_CNT_31_0_SZ 32
++#define HCI_TX_ALLOC_CNT_47_32_MSK 0x0000ffff
++#define HCI_TX_ALLOC_CNT_47_32_I_MSK 0xffff0000
++#define HCI_TX_ALLOC_CNT_47_32_SFT 0
++#define HCI_TX_ALLOC_CNT_47_32_HI 15
++#define HCI_TX_ALLOC_CNT_47_32_SZ 16
++#define HCI_PROC_CNT_MSK 0x00ff0000
++#define HCI_PROC_CNT_I_MSK 0xff00ffff
++#define HCI_PROC_CNT_SFT 16
++#define HCI_PROC_CNT_HI 23
++#define HCI_PROC_CNT_SZ 8
++#define SDIO_TRANS_CNT_MSK 0xff000000
++#define SDIO_TRANS_CNT_I_MSK 0x00ffffff
++#define SDIO_TRANS_CNT_SFT 24
++#define SDIO_TRANS_CNT_HI 31
++#define SDIO_TRANS_CNT_SZ 8
++#define SDIO_TX_INVALID_CNT_31_0_MSK 0xffffffff
++#define SDIO_TX_INVALID_CNT_31_0_I_MSK 0x00000000
++#define SDIO_TX_INVALID_CNT_31_0_SFT 0
++#define SDIO_TX_INVALID_CNT_31_0_HI 31
++#define SDIO_TX_INVALID_CNT_31_0_SZ 32
++#define SDIO_TX_INVALID_CNT_47_32_MSK 0x0000ffff
++#define SDIO_TX_INVALID_CNT_47_32_I_MSK 0xffff0000
++#define SDIO_TX_INVALID_CNT_47_32_SFT 0
++#define SDIO_TX_INVALID_CNT_47_32_HI 15
++#define SDIO_TX_INVALID_CNT_47_32_SZ 16
++#define CS_START_ADDR_MSK 0x0000ffff
++#define CS_START_ADDR_I_MSK 0xffff0000
++#define CS_START_ADDR_SFT 0
++#define CS_START_ADDR_HI 15
++#define CS_START_ADDR_SZ 16
++#define CS_PKT_ID_MSK 0x007f0000
++#define CS_PKT_ID_I_MSK 0xff80ffff
++#define CS_PKT_ID_SFT 16
++#define CS_PKT_ID_HI 22
++#define CS_PKT_ID_SZ 7
++#define ADD_LEN_MSK 0x0000ffff
++#define ADD_LEN_I_MSK 0xffff0000
++#define ADD_LEN_SFT 0
++#define ADD_LEN_HI 15
++#define ADD_LEN_SZ 16
++#define CS_ADDER_EN_MSK 0x00000001
++#define CS_ADDER_EN_I_MSK 0xfffffffe
++#define CS_ADDER_EN_SFT 0
++#define CS_ADDER_EN_HI 0
++#define CS_ADDER_EN_SZ 1
++#define PSEUDO_MSK 0x00000002
++#define PSEUDO_I_MSK 0xfffffffd
++#define PSEUDO_SFT 1
++#define PSEUDO_HI 1
++#define PSEUDO_SZ 1
++#define CALCULATE_MSK 0xffffffff
++#define CALCULATE_I_MSK 0x00000000
++#define CALCULATE_SFT 0
++#define CALCULATE_HI 31
++#define CALCULATE_SZ 32
++#define L4_LEN_MSK 0x0000ffff
++#define L4_LEN_I_MSK 0xffff0000
++#define L4_LEN_SFT 0
++#define L4_LEN_HI 15
++#define L4_LEN_SZ 16
++#define L4_PROTOL_MSK 0x00ff0000
++#define L4_PROTOL_I_MSK 0xff00ffff
++#define L4_PROTOL_SFT 16
++#define L4_PROTOL_HI 23
++#define L4_PROTOL_SZ 8
++#define CHECK_SUM_MSK 0x0000ffff
++#define CHECK_SUM_I_MSK 0xffff0000
++#define CHECK_SUM_SFT 0
++#define CHECK_SUM_HI 15
++#define CHECK_SUM_SZ 16
++#define RAND_EN_MSK 0x00000001
++#define RAND_EN_I_MSK 0xfffffffe
++#define RAND_EN_SFT 0
++#define RAND_EN_HI 0
++#define RAND_EN_SZ 1
++#define RAND_NUM_MSK 0xffffffff
++#define RAND_NUM_I_MSK 0x00000000
++#define RAND_NUM_SFT 0
++#define RAND_NUM_HI 31
++#define RAND_NUM_SZ 32
++#define MUL_OP1_MSK 0xffffffff
++#define MUL_OP1_I_MSK 0x00000000
++#define MUL_OP1_SFT 0
++#define MUL_OP1_HI 31
++#define MUL_OP1_SZ 32
++#define MUL_OP2_MSK 0xffffffff
++#define MUL_OP2_I_MSK 0x00000000
++#define MUL_OP2_SFT 0
++#define MUL_OP2_HI 31
++#define MUL_OP2_SZ 32
++#define MUL_ANS0_MSK 0xffffffff
++#define MUL_ANS0_I_MSK 0x00000000
++#define MUL_ANS0_SFT 0
++#define MUL_ANS0_HI 31
++#define MUL_ANS0_SZ 32
++#define MUL_ANS1_MSK 0xffffffff
++#define MUL_ANS1_I_MSK 0x00000000
++#define MUL_ANS1_SFT 0
++#define MUL_ANS1_HI 31
++#define MUL_ANS1_SZ 32
++#define RD_ADDR_MSK 0x0000ffff
++#define RD_ADDR_I_MSK 0xffff0000
++#define RD_ADDR_SFT 0
++#define RD_ADDR_HI 15
++#define RD_ADDR_SZ 16
++#define RD_ID_MSK 0x007f0000
++#define RD_ID_I_MSK 0xff80ffff
++#define RD_ID_SFT 16
++#define RD_ID_HI 22
++#define RD_ID_SZ 7
++#define WR_ADDR_MSK 0x0000ffff
++#define WR_ADDR_I_MSK 0xffff0000
++#define WR_ADDR_SFT 0
++#define WR_ADDR_HI 15
++#define WR_ADDR_SZ 16
++#define WR_ID_MSK 0x007f0000
++#define WR_ID_I_MSK 0xff80ffff
++#define WR_ID_SFT 16
++#define WR_ID_HI 22
++#define WR_ID_SZ 7
++#define LEN_MSK 0x0000ffff
++#define LEN_I_MSK 0xffff0000
++#define LEN_SFT 0
++#define LEN_HI 15
++#define LEN_SZ 16
++#define CLR_MSK 0x00000001
++#define CLR_I_MSK 0xfffffffe
++#define CLR_SFT 0
++#define CLR_HI 0
++#define CLR_SZ 1
++#define PHY_MODE_MSK 0x00000003
++#define PHY_MODE_I_MSK 0xfffffffc
++#define PHY_MODE_SFT 0
++#define PHY_MODE_HI 1
++#define PHY_MODE_SZ 2
++#define SHRT_PREAM_MSK 0x00000004
++#define SHRT_PREAM_I_MSK 0xfffffffb
++#define SHRT_PREAM_SFT 2
++#define SHRT_PREAM_HI 2
++#define SHRT_PREAM_SZ 1
++#define SHRT_GI_MSK 0x00000008
++#define SHRT_GI_I_MSK 0xfffffff7
++#define SHRT_GI_SFT 3
++#define SHRT_GI_HI 3
++#define SHRT_GI_SZ 1
++#define DATA_RATE_MSK 0x000007f0
++#define DATA_RATE_I_MSK 0xfffff80f
++#define DATA_RATE_SFT 4
++#define DATA_RATE_HI 10
++#define DATA_RATE_SZ 7
++#define MCS_MSK 0x00007000
++#define MCS_I_MSK 0xffff8fff
++#define MCS_SFT 12
++#define MCS_HI 14
++#define MCS_SZ 3
++#define FRAME_LEN_MSK 0xffff0000
++#define FRAME_LEN_I_MSK 0x0000ffff
++#define FRAME_LEN_SFT 16
++#define FRAME_LEN_HI 31
++#define FRAME_LEN_SZ 16
++#define DURATION_MSK 0x0000ffff
++#define DURATION_I_MSK 0xffff0000
++#define DURATION_SFT 0
++#define DURATION_HI 15
++#define DURATION_SZ 16
++#define SHA_DST_ADDR_MSK 0xffffffff
++#define SHA_DST_ADDR_I_MSK 0x00000000
++#define SHA_DST_ADDR_SFT 0
++#define SHA_DST_ADDR_HI 31
++#define SHA_DST_ADDR_SZ 32
++#define SHA_SRC_ADDR_MSK 0xffffffff
++#define SHA_SRC_ADDR_I_MSK 0x00000000
++#define SHA_SRC_ADDR_SFT 0
++#define SHA_SRC_ADDR_HI 31
++#define SHA_SRC_ADDR_SZ 32
++#define SHA_BUSY_MSK 0x00000001
++#define SHA_BUSY_I_MSK 0xfffffffe
++#define SHA_BUSY_SFT 0
++#define SHA_BUSY_HI 0
++#define SHA_BUSY_SZ 1
++#define SHA_ENDIAN_MSK 0x00000002
++#define SHA_ENDIAN_I_MSK 0xfffffffd
++#define SHA_ENDIAN_SFT 1
++#define SHA_ENDIAN_HI 1
++#define SHA_ENDIAN_SZ 1
++#define EFS_CLKFREQ_MSK 0x00000fff
++#define EFS_CLKFREQ_I_MSK 0xfffff000
++#define EFS_CLKFREQ_SFT 0
++#define EFS_CLKFREQ_HI 11
++#define EFS_CLKFREQ_SZ 12
++#define LOW_ACTIVE_MSK 0x00010000
++#define LOW_ACTIVE_I_MSK 0xfffeffff
++#define LOW_ACTIVE_SFT 16
++#define LOW_ACTIVE_HI 16
++#define LOW_ACTIVE_SZ 1
++#define EFS_CLKFREQ_RD_MSK 0x0ff00000
++#define EFS_CLKFREQ_RD_I_MSK 0xf00fffff
++#define EFS_CLKFREQ_RD_SFT 20
++#define EFS_CLKFREQ_RD_HI 27
++#define EFS_CLKFREQ_RD_SZ 8
++#define EFS_PRE_RD_MSK 0xf0000000
++#define EFS_PRE_RD_I_MSK 0x0fffffff
++#define EFS_PRE_RD_SFT 28
++#define EFS_PRE_RD_HI 31
++#define EFS_PRE_RD_SZ 4
++#define EFS_LDO_ON_MSK 0x0000ffff
++#define EFS_LDO_ON_I_MSK 0xffff0000
++#define EFS_LDO_ON_SFT 0
++#define EFS_LDO_ON_HI 15
++#define EFS_LDO_ON_SZ 16
++#define EFS_LDO_OFF_MSK 0xffff0000
++#define EFS_LDO_OFF_I_MSK 0x0000ffff
++#define EFS_LDO_OFF_SFT 16
++#define EFS_LDO_OFF_HI 31
++#define EFS_LDO_OFF_SZ 16
++#define EFS_RDATA_0_MSK 0xffffffff
++#define EFS_RDATA_0_I_MSK 0x00000000
++#define EFS_RDATA_0_SFT 0
++#define EFS_RDATA_0_HI 31
++#define EFS_RDATA_0_SZ 32
++#define EFS_WDATA_0_MSK 0xffffffff
++#define EFS_WDATA_0_I_MSK 0x00000000
++#define EFS_WDATA_0_SFT 0
++#define EFS_WDATA_0_HI 31
++#define EFS_WDATA_0_SZ 32
++#define EFS_RDATA_1_MSK 0xffffffff
++#define EFS_RDATA_1_I_MSK 0x00000000
++#define EFS_RDATA_1_SFT 0
++#define EFS_RDATA_1_HI 31
++#define EFS_RDATA_1_SZ 32
++#define EFS_WDATA_1_MSK 0xffffffff
++#define EFS_WDATA_1_I_MSK 0x00000000
++#define EFS_WDATA_1_SFT 0
++#define EFS_WDATA_1_HI 31
++#define EFS_WDATA_1_SZ 32
++#define EFS_RDATA_2_MSK 0xffffffff
++#define EFS_RDATA_2_I_MSK 0x00000000
++#define EFS_RDATA_2_SFT 0
++#define EFS_RDATA_2_HI 31
++#define EFS_RDATA_2_SZ 32
++#define EFS_WDATA_2_MSK 0xffffffff
++#define EFS_WDATA_2_I_MSK 0x00000000
++#define EFS_WDATA_2_SFT 0
++#define EFS_WDATA_2_HI 31
++#define EFS_WDATA_2_SZ 32
++#define EFS_RDATA_3_MSK 0xffffffff
++#define EFS_RDATA_3_I_MSK 0x00000000
++#define EFS_RDATA_3_SFT 0
++#define EFS_RDATA_3_HI 31
++#define EFS_RDATA_3_SZ 32
++#define EFS_WDATA_3_MSK 0xffffffff
++#define EFS_WDATA_3_I_MSK 0x00000000
++#define EFS_WDATA_3_SFT 0
++#define EFS_WDATA_3_HI 31
++#define EFS_WDATA_3_SZ 32
++#define EFS_RDATA_4_MSK 0xffffffff
++#define EFS_RDATA_4_I_MSK 0x00000000
++#define EFS_RDATA_4_SFT 0
++#define EFS_RDATA_4_HI 31
++#define EFS_RDATA_4_SZ 32
++#define EFS_WDATA_4_MSK 0xffffffff
++#define EFS_WDATA_4_I_MSK 0x00000000
++#define EFS_WDATA_4_SFT 0
++#define EFS_WDATA_4_HI 31
++#define EFS_WDATA_4_SZ 32
++#define EFS_RDATA_5_MSK 0xffffffff
++#define EFS_RDATA_5_I_MSK 0x00000000
++#define EFS_RDATA_5_SFT 0
++#define EFS_RDATA_5_HI 31
++#define EFS_RDATA_5_SZ 32
++#define EFS_WDATA_5_MSK 0xffffffff
++#define EFS_WDATA_5_I_MSK 0x00000000
++#define EFS_WDATA_5_SFT 0
++#define EFS_WDATA_5_HI 31
++#define EFS_WDATA_5_SZ 32
++#define EFS_RDATA_6_MSK 0xffffffff
++#define EFS_RDATA_6_I_MSK 0x00000000
++#define EFS_RDATA_6_SFT 0
++#define EFS_RDATA_6_HI 31
++#define EFS_RDATA_6_SZ 32
++#define EFS_WDATA_6_MSK 0xffffffff
++#define EFS_WDATA_6_I_MSK 0x00000000
++#define EFS_WDATA_6_SFT 0
++#define EFS_WDATA_6_HI 31
++#define EFS_WDATA_6_SZ 32
++#define EFS_RDATA_7_MSK 0xffffffff
++#define EFS_RDATA_7_I_MSK 0x00000000
++#define EFS_RDATA_7_SFT 0
++#define EFS_RDATA_7_HI 31
++#define EFS_RDATA_7_SZ 32
++#define EFS_WDATA_7_MSK 0xffffffff
++#define EFS_WDATA_7_I_MSK 0x00000000
++#define EFS_WDATA_7_SFT 0
++#define EFS_WDATA_7_HI 31
++#define EFS_WDATA_7_SZ 32
++#define EFS_SPI_RD0_EN_MSK 0x00000001
++#define EFS_SPI_RD0_EN_I_MSK 0xfffffffe
++#define EFS_SPI_RD0_EN_SFT 0
++#define EFS_SPI_RD0_EN_HI 0
++#define EFS_SPI_RD0_EN_SZ 1
++#define EFS_SPI_RD1_EN_MSK 0x00000001
++#define EFS_SPI_RD1_EN_I_MSK 0xfffffffe
++#define EFS_SPI_RD1_EN_SFT 0
++#define EFS_SPI_RD1_EN_HI 0
++#define EFS_SPI_RD1_EN_SZ 1
++#define EFS_SPI_RD2_EN_MSK 0x00000001
++#define EFS_SPI_RD2_EN_I_MSK 0xfffffffe
++#define EFS_SPI_RD2_EN_SFT 0
++#define EFS_SPI_RD2_EN_HI 0
++#define EFS_SPI_RD2_EN_SZ 1
++#define EFS_SPI_RD3_EN_MSK 0x00000001
++#define EFS_SPI_RD3_EN_I_MSK 0xfffffffe
++#define EFS_SPI_RD3_EN_SFT 0
++#define EFS_SPI_RD3_EN_HI 0
++#define EFS_SPI_RD3_EN_SZ 1
++#define EFS_SPI_RD4_EN_MSK 0x00000001
++#define EFS_SPI_RD4_EN_I_MSK 0xfffffffe
++#define EFS_SPI_RD4_EN_SFT 0
++#define EFS_SPI_RD4_EN_HI 0
++#define EFS_SPI_RD4_EN_SZ 1
++#define EFS_SPI_RD5_EN_MSK 0x00000001
++#define EFS_SPI_RD5_EN_I_MSK 0xfffffffe
++#define EFS_SPI_RD5_EN_SFT 0
++#define EFS_SPI_RD5_EN_HI 0
++#define EFS_SPI_RD5_EN_SZ 1
++#define EFS_SPI_RD6_EN_MSK 0x00000001
++#define EFS_SPI_RD6_EN_I_MSK 0xfffffffe
++#define EFS_SPI_RD6_EN_SFT 0
++#define EFS_SPI_RD6_EN_HI 0
++#define EFS_SPI_RD6_EN_SZ 1
++#define EFS_SPI_RD7_EN_MSK 0x00000001
++#define EFS_SPI_RD7_EN_I_MSK 0xfffffffe
++#define EFS_SPI_RD7_EN_SFT 0
++#define EFS_SPI_RD7_EN_HI 0
++#define EFS_SPI_RD7_EN_SZ 1
++#define EFS_SPI_RBUSY_MSK 0x00000001
++#define EFS_SPI_RBUSY_I_MSK 0xfffffffe
++#define EFS_SPI_RBUSY_SFT 0
++#define EFS_SPI_RBUSY_HI 0
++#define EFS_SPI_RBUSY_SZ 1
++#define EFS_SPI_RDATA_0_MSK 0xffffffff
++#define EFS_SPI_RDATA_0_I_MSK 0x00000000
++#define EFS_SPI_RDATA_0_SFT 0
++#define EFS_SPI_RDATA_0_HI 31
++#define EFS_SPI_RDATA_0_SZ 32
++#define EFS_SPI_RDATA_1_MSK 0xffffffff
++#define EFS_SPI_RDATA_1_I_MSK 0x00000000
++#define EFS_SPI_RDATA_1_SFT 0
++#define EFS_SPI_RDATA_1_HI 31
++#define EFS_SPI_RDATA_1_SZ 32
++#define EFS_SPI_RDATA_2_MSK 0xffffffff
++#define EFS_SPI_RDATA_2_I_MSK 0x00000000
++#define EFS_SPI_RDATA_2_SFT 0
++#define EFS_SPI_RDATA_2_HI 31
++#define EFS_SPI_RDATA_2_SZ 32
++#define EFS_SPI_RDATA_3_MSK 0xffffffff
++#define EFS_SPI_RDATA_3_I_MSK 0x00000000
++#define EFS_SPI_RDATA_3_SFT 0
++#define EFS_SPI_RDATA_3_HI 31
++#define EFS_SPI_RDATA_3_SZ 32
++#define EFS_SPI_RDATA_4_MSK 0xffffffff
++#define EFS_SPI_RDATA_4_I_MSK 0x00000000
++#define EFS_SPI_RDATA_4_SFT 0
++#define EFS_SPI_RDATA_4_HI 31
++#define EFS_SPI_RDATA_4_SZ 32
++#define EFS_SPI_RDATA_5_MSK 0xffffffff
++#define EFS_SPI_RDATA_5_I_MSK 0x00000000
++#define EFS_SPI_RDATA_5_SFT 0
++#define EFS_SPI_RDATA_5_HI 31
++#define EFS_SPI_RDATA_5_SZ 32
++#define EFS_SPI_RDATA_6_MSK 0xffffffff
++#define EFS_SPI_RDATA_6_I_MSK 0x00000000
++#define EFS_SPI_RDATA_6_SFT 0
++#define EFS_SPI_RDATA_6_HI 31
++#define EFS_SPI_RDATA_6_SZ 32
++#define EFS_SPI_RDATA_7_MSK 0xffffffff
++#define EFS_SPI_RDATA_7_I_MSK 0x00000000
++#define EFS_SPI_RDATA_7_SFT 0
++#define EFS_SPI_RDATA_7_HI 31
++#define EFS_SPI_RDATA_7_SZ 32
++#define GET_RK_MSK 0x00000001
++#define GET_RK_I_MSK 0xfffffffe
++#define GET_RK_SFT 0
++#define GET_RK_HI 0
++#define GET_RK_SZ 1
++#define FORCE_GET_RK_MSK 0x00000002
++#define FORCE_GET_RK_I_MSK 0xfffffffd
++#define FORCE_GET_RK_SFT 1
++#define FORCE_GET_RK_HI 1
++#define FORCE_GET_RK_SZ 1
++#define SMS4_DESCRY_EN_MSK 0x00000010
++#define SMS4_DESCRY_EN_I_MSK 0xffffffef
++#define SMS4_DESCRY_EN_SFT 4
++#define SMS4_DESCRY_EN_HI 4
++#define SMS4_DESCRY_EN_SZ 1
++#define DEC_DOUT_MSB_MSK 0x00000001
++#define DEC_DOUT_MSB_I_MSK 0xfffffffe
++#define DEC_DOUT_MSB_SFT 0
++#define DEC_DOUT_MSB_HI 0
++#define DEC_DOUT_MSB_SZ 1
++#define DEC_DIN_MSB_MSK 0x00000002
++#define DEC_DIN_MSB_I_MSK 0xfffffffd
++#define DEC_DIN_MSB_SFT 1
++#define DEC_DIN_MSB_HI 1
++#define DEC_DIN_MSB_SZ 1
++#define ENC_DOUT_MSB_MSK 0x00000004
++#define ENC_DOUT_MSB_I_MSK 0xfffffffb
++#define ENC_DOUT_MSB_SFT 2
++#define ENC_DOUT_MSB_HI 2
++#define ENC_DOUT_MSB_SZ 1
++#define ENC_DIN_MSB_MSK 0x00000008
++#define ENC_DIN_MSB_I_MSK 0xfffffff7
++#define ENC_DIN_MSB_SFT 3
++#define ENC_DIN_MSB_HI 3
++#define ENC_DIN_MSB_SZ 1
++#define KEY_DIN_MSB_MSK 0x00000010
++#define KEY_DIN_MSB_I_MSK 0xffffffef
++#define KEY_DIN_MSB_SFT 4
++#define KEY_DIN_MSB_HI 4
++#define KEY_DIN_MSB_SZ 1
++#define SMS4_CBC_EN_MSK 0x00000001
++#define SMS4_CBC_EN_I_MSK 0xfffffffe
++#define SMS4_CBC_EN_SFT 0
++#define SMS4_CBC_EN_HI 0
++#define SMS4_CBC_EN_SZ 1
++#define SMS4_CFB_EN_MSK 0x00000002
++#define SMS4_CFB_EN_I_MSK 0xfffffffd
++#define SMS4_CFB_EN_SFT 1
++#define SMS4_CFB_EN_HI 1
++#define SMS4_CFB_EN_SZ 1
++#define SMS4_OFB_EN_MSK 0x00000004
++#define SMS4_OFB_EN_I_MSK 0xfffffffb
++#define SMS4_OFB_EN_SFT 2
++#define SMS4_OFB_EN_HI 2
++#define SMS4_OFB_EN_SZ 1
++#define SMS4_START_TRIG_MSK 0x00000001
++#define SMS4_START_TRIG_I_MSK 0xfffffffe
++#define SMS4_START_TRIG_SFT 0
++#define SMS4_START_TRIG_HI 0
++#define SMS4_START_TRIG_SZ 1
++#define SMS4_BUSY_MSK 0x00000001
++#define SMS4_BUSY_I_MSK 0xfffffffe
++#define SMS4_BUSY_SFT 0
++#define SMS4_BUSY_HI 0
++#define SMS4_BUSY_SZ 1
++#define SMS4_DONE_MSK 0x00000001
++#define SMS4_DONE_I_MSK 0xfffffffe
++#define SMS4_DONE_SFT 0
++#define SMS4_DONE_HI 0
++#define SMS4_DONE_SZ 1
++#define SMS4_DATAIN_0_MSK 0xffffffff
++#define SMS4_DATAIN_0_I_MSK 0x00000000
++#define SMS4_DATAIN_0_SFT 0
++#define SMS4_DATAIN_0_HI 31
++#define SMS4_DATAIN_0_SZ 32
++#define SMS4_DATAIN_1_MSK 0xffffffff
++#define SMS4_DATAIN_1_I_MSK 0x00000000
++#define SMS4_DATAIN_1_SFT 0
++#define SMS4_DATAIN_1_HI 31
++#define SMS4_DATAIN_1_SZ 32
++#define SMS4_DATAIN_2_MSK 0xffffffff
++#define SMS4_DATAIN_2_I_MSK 0x00000000
++#define SMS4_DATAIN_2_SFT 0
++#define SMS4_DATAIN_2_HI 31
++#define SMS4_DATAIN_2_SZ 32
++#define SMS4_DATAIN_3_MSK 0xffffffff
++#define SMS4_DATAIN_3_I_MSK 0x00000000
++#define SMS4_DATAIN_3_SFT 0
++#define SMS4_DATAIN_3_HI 31
++#define SMS4_DATAIN_3_SZ 32
++#define SMS4_DATAOUT_0_MSK 0xffffffff
++#define SMS4_DATAOUT_0_I_MSK 0x00000000
++#define SMS4_DATAOUT_0_SFT 0
++#define SMS4_DATAOUT_0_HI 31
++#define SMS4_DATAOUT_0_SZ 32
++#define SMS4_DATAOUT_1_MSK 0xffffffff
++#define SMS4_DATAOUT_1_I_MSK 0x00000000
++#define SMS4_DATAOUT_1_SFT 0
++#define SMS4_DATAOUT_1_HI 31
++#define SMS4_DATAOUT_1_SZ 32
++#define SMS4_DATAOUT_2_MSK 0xffffffff
++#define SMS4_DATAOUT_2_I_MSK 0x00000000
++#define SMS4_DATAOUT_2_SFT 0
++#define SMS4_DATAOUT_2_HI 31
++#define SMS4_DATAOUT_2_SZ 32
++#define SMS4_DATAOUT_3_MSK 0xffffffff
++#define SMS4_DATAOUT_3_I_MSK 0x00000000
++#define SMS4_DATAOUT_3_SFT 0
++#define SMS4_DATAOUT_3_HI 31
++#define SMS4_DATAOUT_3_SZ 32
++#define SMS4_KEY_0_MSK 0xffffffff
++#define SMS4_KEY_0_I_MSK 0x00000000
++#define SMS4_KEY_0_SFT 0
++#define SMS4_KEY_0_HI 31
++#define SMS4_KEY_0_SZ 32
++#define SMS4_KEY_1_MSK 0xffffffff
++#define SMS4_KEY_1_I_MSK 0x00000000
++#define SMS4_KEY_1_SFT 0
++#define SMS4_KEY_1_HI 31
++#define SMS4_KEY_1_SZ 32
++#define SMS4_KEY_2_MSK 0xffffffff
++#define SMS4_KEY_2_I_MSK 0x00000000
++#define SMS4_KEY_2_SFT 0
++#define SMS4_KEY_2_HI 31
++#define SMS4_KEY_2_SZ 32
++#define SMS4_KEY_3_MSK 0xffffffff
++#define SMS4_KEY_3_I_MSK 0x00000000
++#define SMS4_KEY_3_SFT 0
++#define SMS4_KEY_3_HI 31
++#define SMS4_KEY_3_SZ 32
++#define SMS4_MODE_IV0_MSK 0xffffffff
++#define SMS4_MODE_IV0_I_MSK 0x00000000
++#define SMS4_MODE_IV0_SFT 0
++#define SMS4_MODE_IV0_HI 31
++#define SMS4_MODE_IV0_SZ 32
++#define SMS4_MODE_IV1_MSK 0xffffffff
++#define SMS4_MODE_IV1_I_MSK 0x00000000
++#define SMS4_MODE_IV1_SFT 0
++#define SMS4_MODE_IV1_HI 31
++#define SMS4_MODE_IV1_SZ 32
++#define SMS4_MODE_IV2_MSK 0xffffffff
++#define SMS4_MODE_IV2_I_MSK 0x00000000
++#define SMS4_MODE_IV2_SFT 0
++#define SMS4_MODE_IV2_HI 31
++#define SMS4_MODE_IV2_SZ 32
++#define SMS4_MODE_IV3_MSK 0xffffffff
++#define SMS4_MODE_IV3_I_MSK 0x00000000
++#define SMS4_MODE_IV3_SFT 0
++#define SMS4_MODE_IV3_HI 31
++#define SMS4_MODE_IV3_SZ 32
++#define SMS4_OFB_ENC0_MSK 0xffffffff
++#define SMS4_OFB_ENC0_I_MSK 0x00000000
++#define SMS4_OFB_ENC0_SFT 0
++#define SMS4_OFB_ENC0_HI 31
++#define SMS4_OFB_ENC0_SZ 32
++#define SMS4_OFB_ENC1_MSK 0xffffffff
++#define SMS4_OFB_ENC1_I_MSK 0x00000000
++#define SMS4_OFB_ENC1_SFT 0
++#define SMS4_OFB_ENC1_HI 31
++#define SMS4_OFB_ENC1_SZ 32
++#define SMS4_OFB_ENC2_MSK 0xffffffff
++#define SMS4_OFB_ENC2_I_MSK 0x00000000
++#define SMS4_OFB_ENC2_SFT 0
++#define SMS4_OFB_ENC2_HI 31
++#define SMS4_OFB_ENC2_SZ 32
++#define SMS4_OFB_ENC3_MSK 0xffffffff
++#define SMS4_OFB_ENC3_I_MSK 0x00000000
++#define SMS4_OFB_ENC3_SFT 0
++#define SMS4_OFB_ENC3_HI 31
++#define SMS4_OFB_ENC3_SZ 32
++#define MRX_MCAST_TB0_31_0_MSK 0xffffffff
++#define MRX_MCAST_TB0_31_0_I_MSK 0x00000000
++#define MRX_MCAST_TB0_31_0_SFT 0
++#define MRX_MCAST_TB0_31_0_HI 31
++#define MRX_MCAST_TB0_31_0_SZ 32
++#define MRX_MCAST_TB0_47_32_MSK 0x0000ffff
++#define MRX_MCAST_TB0_47_32_I_MSK 0xffff0000
++#define MRX_MCAST_TB0_47_32_SFT 0
++#define MRX_MCAST_TB0_47_32_HI 15
++#define MRX_MCAST_TB0_47_32_SZ 16
++#define MRX_MCAST_MASK0_31_0_MSK 0xffffffff
++#define MRX_MCAST_MASK0_31_0_I_MSK 0x00000000
++#define MRX_MCAST_MASK0_31_0_SFT 0
++#define MRX_MCAST_MASK0_31_0_HI 31
++#define MRX_MCAST_MASK0_31_0_SZ 32
++#define MRX_MCAST_MASK0_47_32_MSK 0x0000ffff
++#define MRX_MCAST_MASK0_47_32_I_MSK 0xffff0000
++#define MRX_MCAST_MASK0_47_32_SFT 0
++#define MRX_MCAST_MASK0_47_32_HI 15
++#define MRX_MCAST_MASK0_47_32_SZ 16
++#define MRX_MCAST_CTRL_0_MSK 0x00000003
++#define MRX_MCAST_CTRL_0_I_MSK 0xfffffffc
++#define MRX_MCAST_CTRL_0_SFT 0
++#define MRX_MCAST_CTRL_0_HI 1
++#define MRX_MCAST_CTRL_0_SZ 2
++#define MRX_MCAST_TB1_31_0_MSK 0xffffffff
++#define MRX_MCAST_TB1_31_0_I_MSK 0x00000000
++#define MRX_MCAST_TB1_31_0_SFT 0
++#define MRX_MCAST_TB1_31_0_HI 31
++#define MRX_MCAST_TB1_31_0_SZ 32
++#define MRX_MCAST_TB1_47_32_MSK 0x0000ffff
++#define MRX_MCAST_TB1_47_32_I_MSK 0xffff0000
++#define MRX_MCAST_TB1_47_32_SFT 0
++#define MRX_MCAST_TB1_47_32_HI 15
++#define MRX_MCAST_TB1_47_32_SZ 16
++#define MRX_MCAST_MASK1_31_0_MSK 0xffffffff
++#define MRX_MCAST_MASK1_31_0_I_MSK 0x00000000
++#define MRX_MCAST_MASK1_31_0_SFT 0
++#define MRX_MCAST_MASK1_31_0_HI 31
++#define MRX_MCAST_MASK1_31_0_SZ 32
++#define MRX_MCAST_MASK1_47_32_MSK 0x0000ffff
++#define MRX_MCAST_MASK1_47_32_I_MSK 0xffff0000
++#define MRX_MCAST_MASK1_47_32_SFT 0
++#define MRX_MCAST_MASK1_47_32_HI 15
++#define MRX_MCAST_MASK1_47_32_SZ 16
++#define MRX_MCAST_CTRL_1_MSK 0x00000003
++#define MRX_MCAST_CTRL_1_I_MSK 0xfffffffc
++#define MRX_MCAST_CTRL_1_SFT 0
++#define MRX_MCAST_CTRL_1_HI 1
++#define MRX_MCAST_CTRL_1_SZ 2
++#define MRX_MCAST_TB2_31_0_MSK 0xffffffff
++#define MRX_MCAST_TB2_31_0_I_MSK 0x00000000
++#define MRX_MCAST_TB2_31_0_SFT 0
++#define MRX_MCAST_TB2_31_0_HI 31
++#define MRX_MCAST_TB2_31_0_SZ 32
++#define MRX_MCAST_TB2_47_32_MSK 0x0000ffff
++#define MRX_MCAST_TB2_47_32_I_MSK 0xffff0000
++#define MRX_MCAST_TB2_47_32_SFT 0
++#define MRX_MCAST_TB2_47_32_HI 15
++#define MRX_MCAST_TB2_47_32_SZ 16
++#define MRX_MCAST_MASK2_31_0_MSK 0xffffffff
++#define MRX_MCAST_MASK2_31_0_I_MSK 0x00000000
++#define MRX_MCAST_MASK2_31_0_SFT 0
++#define MRX_MCAST_MASK2_31_0_HI 31
++#define MRX_MCAST_MASK2_31_0_SZ 32
++#define MRX_MCAST_MASK2_47_32_MSK 0x0000ffff
++#define MRX_MCAST_MASK2_47_32_I_MSK 0xffff0000
++#define MRX_MCAST_MASK2_47_32_SFT 0
++#define MRX_MCAST_MASK2_47_32_HI 15
++#define MRX_MCAST_MASK2_47_32_SZ 16
++#define MRX_MCAST_CTRL_2_MSK 0x00000003
++#define MRX_MCAST_CTRL_2_I_MSK 0xfffffffc
++#define MRX_MCAST_CTRL_2_SFT 0
++#define MRX_MCAST_CTRL_2_HI 1
++#define MRX_MCAST_CTRL_2_SZ 2
++#define MRX_MCAST_TB3_31_0_MSK 0xffffffff
++#define MRX_MCAST_TB3_31_0_I_MSK 0x00000000
++#define MRX_MCAST_TB3_31_0_SFT 0
++#define MRX_MCAST_TB3_31_0_HI 31
++#define MRX_MCAST_TB3_31_0_SZ 32
++#define MRX_MCAST_TB3_47_32_MSK 0x0000ffff
++#define MRX_MCAST_TB3_47_32_I_MSK 0xffff0000
++#define MRX_MCAST_TB3_47_32_SFT 0
++#define MRX_MCAST_TB3_47_32_HI 15
++#define MRX_MCAST_TB3_47_32_SZ 16
++#define MRX_MCAST_MASK3_31_0_MSK 0xffffffff
++#define MRX_MCAST_MASK3_31_0_I_MSK 0x00000000
++#define MRX_MCAST_MASK3_31_0_SFT 0
++#define MRX_MCAST_MASK3_31_0_HI 31
++#define MRX_MCAST_MASK3_31_0_SZ 32
++#define MRX_MCAST_MASK3_47_32_MSK 0x0000ffff
++#define MRX_MCAST_MASK3_47_32_I_MSK 0xffff0000
++#define MRX_MCAST_MASK3_47_32_SFT 0
++#define MRX_MCAST_MASK3_47_32_HI 15
++#define MRX_MCAST_MASK3_47_32_SZ 16
++#define MRX_MCAST_CTRL_3_MSK 0x00000003
++#define MRX_MCAST_CTRL_3_I_MSK 0xfffffffc
++#define MRX_MCAST_CTRL_3_SFT 0
++#define MRX_MCAST_CTRL_3_HI 1
++#define MRX_MCAST_CTRL_3_SZ 2
++#define MRX_PHY_INFO_MSK 0xffffffff
++#define MRX_PHY_INFO_I_MSK 0x00000000
++#define MRX_PHY_INFO_SFT 0
++#define MRX_PHY_INFO_HI 31
++#define MRX_PHY_INFO_SZ 32
++#define DBG_BA_TYPE_MSK 0x0000003f
++#define DBG_BA_TYPE_I_MSK 0xffffffc0
++#define DBG_BA_TYPE_SFT 0
++#define DBG_BA_TYPE_HI 5
++#define DBG_BA_TYPE_SZ 6
++#define DBG_BA_SEQ_MSK 0x000fff00
++#define DBG_BA_SEQ_I_MSK 0xfff000ff
++#define DBG_BA_SEQ_SFT 8
++#define DBG_BA_SEQ_HI 19
++#define DBG_BA_SEQ_SZ 12
++#define MRX_FLT_TB0_MSK 0x00007fff
++#define MRX_FLT_TB0_I_MSK 0xffff8000
++#define MRX_FLT_TB0_SFT 0
++#define MRX_FLT_TB0_HI 14
++#define MRX_FLT_TB0_SZ 15
++#define MRX_FLT_TB1_MSK 0x00007fff
++#define MRX_FLT_TB1_I_MSK 0xffff8000
++#define MRX_FLT_TB1_SFT 0
++#define MRX_FLT_TB1_HI 14
++#define MRX_FLT_TB1_SZ 15
++#define MRX_FLT_TB2_MSK 0x00007fff
++#define MRX_FLT_TB2_I_MSK 0xffff8000
++#define MRX_FLT_TB2_SFT 0
++#define MRX_FLT_TB2_HI 14
++#define MRX_FLT_TB2_SZ 15
++#define MRX_FLT_TB3_MSK 0x00007fff
++#define MRX_FLT_TB3_I_MSK 0xffff8000
++#define MRX_FLT_TB3_SFT 0
++#define MRX_FLT_TB3_HI 14
++#define MRX_FLT_TB3_SZ 15
++#define MRX_FLT_TB4_MSK 0x00007fff
++#define MRX_FLT_TB4_I_MSK 0xffff8000
++#define MRX_FLT_TB4_SFT 0
++#define MRX_FLT_TB4_HI 14
++#define MRX_FLT_TB4_SZ 15
++#define MRX_FLT_TB5_MSK 0x00007fff
++#define MRX_FLT_TB5_I_MSK 0xffff8000
++#define MRX_FLT_TB5_SFT 0
++#define MRX_FLT_TB5_HI 14
++#define MRX_FLT_TB5_SZ 15
++#define MRX_FLT_TB6_MSK 0x00007fff
++#define MRX_FLT_TB6_I_MSK 0xffff8000
++#define MRX_FLT_TB6_SFT 0
++#define MRX_FLT_TB6_HI 14
++#define MRX_FLT_TB6_SZ 15
++#define MRX_FLT_TB7_MSK 0x00007fff
++#define MRX_FLT_TB7_I_MSK 0xffff8000
++#define MRX_FLT_TB7_SFT 0
++#define MRX_FLT_TB7_HI 14
++#define MRX_FLT_TB7_SZ 15
++#define MRX_FLT_TB8_MSK 0x00007fff
++#define MRX_FLT_TB8_I_MSK 0xffff8000
++#define MRX_FLT_TB8_SFT 0
++#define MRX_FLT_TB8_HI 14
++#define MRX_FLT_TB8_SZ 15
++#define MRX_FLT_TB9_MSK 0x00007fff
++#define MRX_FLT_TB9_I_MSK 0xffff8000
++#define MRX_FLT_TB9_SFT 0
++#define MRX_FLT_TB9_HI 14
++#define MRX_FLT_TB9_SZ 15
++#define MRX_FLT_TB10_MSK 0x00007fff
++#define MRX_FLT_TB10_I_MSK 0xffff8000
++#define MRX_FLT_TB10_SFT 0
++#define MRX_FLT_TB10_HI 14
++#define MRX_FLT_TB10_SZ 15
++#define MRX_FLT_TB11_MSK 0x00007fff
++#define MRX_FLT_TB11_I_MSK 0xffff8000
++#define MRX_FLT_TB11_SFT 0
++#define MRX_FLT_TB11_HI 14
++#define MRX_FLT_TB11_SZ 15
++#define MRX_FLT_TB12_MSK 0x00007fff
++#define MRX_FLT_TB12_I_MSK 0xffff8000
++#define MRX_FLT_TB12_SFT 0
++#define MRX_FLT_TB12_HI 14
++#define MRX_FLT_TB12_SZ 15
++#define MRX_FLT_TB13_MSK 0x00007fff
++#define MRX_FLT_TB13_I_MSK 0xffff8000
++#define MRX_FLT_TB13_SFT 0
++#define MRX_FLT_TB13_HI 14
++#define MRX_FLT_TB13_SZ 15
++#define MRX_FLT_TB14_MSK 0x00007fff
++#define MRX_FLT_TB14_I_MSK 0xffff8000
++#define MRX_FLT_TB14_SFT 0
++#define MRX_FLT_TB14_HI 14
++#define MRX_FLT_TB14_SZ 15
++#define MRX_FLT_TB15_MSK 0x00007fff
++#define MRX_FLT_TB15_I_MSK 0xffff8000
++#define MRX_FLT_TB15_SFT 0
++#define MRX_FLT_TB15_HI 14
++#define MRX_FLT_TB15_SZ 15
++#define MRX_FLT_EN0_MSK 0x0000ffff
++#define MRX_FLT_EN0_I_MSK 0xffff0000
++#define MRX_FLT_EN0_SFT 0
++#define MRX_FLT_EN0_HI 15
++#define MRX_FLT_EN0_SZ 16
++#define MRX_FLT_EN1_MSK 0x0000ffff
++#define MRX_FLT_EN1_I_MSK 0xffff0000
++#define MRX_FLT_EN1_SFT 0
++#define MRX_FLT_EN1_HI 15
++#define MRX_FLT_EN1_SZ 16
++#define MRX_FLT_EN2_MSK 0x0000ffff
++#define MRX_FLT_EN2_I_MSK 0xffff0000
++#define MRX_FLT_EN2_SFT 0
++#define MRX_FLT_EN2_HI 15
++#define MRX_FLT_EN2_SZ 16
++#define MRX_FLT_EN3_MSK 0x0000ffff
++#define MRX_FLT_EN3_I_MSK 0xffff0000
++#define MRX_FLT_EN3_SFT 0
++#define MRX_FLT_EN3_HI 15
++#define MRX_FLT_EN3_SZ 16
++#define MRX_FLT_EN4_MSK 0x0000ffff
++#define MRX_FLT_EN4_I_MSK 0xffff0000
++#define MRX_FLT_EN4_SFT 0
++#define MRX_FLT_EN4_HI 15
++#define MRX_FLT_EN4_SZ 16
++#define MRX_FLT_EN5_MSK 0x0000ffff
++#define MRX_FLT_EN5_I_MSK 0xffff0000
++#define MRX_FLT_EN5_SFT 0
++#define MRX_FLT_EN5_HI 15
++#define MRX_FLT_EN5_SZ 16
++#define MRX_FLT_EN6_MSK 0x0000ffff
++#define MRX_FLT_EN6_I_MSK 0xffff0000
++#define MRX_FLT_EN6_SFT 0
++#define MRX_FLT_EN6_HI 15
++#define MRX_FLT_EN6_SZ 16
++#define MRX_FLT_EN7_MSK 0x0000ffff
++#define MRX_FLT_EN7_I_MSK 0xffff0000
++#define MRX_FLT_EN7_SFT 0
++#define MRX_FLT_EN7_HI 15
++#define MRX_FLT_EN7_SZ 16
++#define MRX_FLT_EN8_MSK 0x0000ffff
++#define MRX_FLT_EN8_I_MSK 0xffff0000
++#define MRX_FLT_EN8_SFT 0
++#define MRX_FLT_EN8_HI 15
++#define MRX_FLT_EN8_SZ 16
++#define MRX_LEN_FLT_MSK 0x0000ffff
++#define MRX_LEN_FLT_I_MSK 0xffff0000
++#define MRX_LEN_FLT_SFT 0
++#define MRX_LEN_FLT_HI 15
++#define MRX_LEN_FLT_SZ 16
++#define RX_FLOW_DATA_MSK 0xffffffff
++#define RX_FLOW_DATA_I_MSK 0x00000000
++#define RX_FLOW_DATA_SFT 0
++#define RX_FLOW_DATA_HI 31
++#define RX_FLOW_DATA_SZ 32
++#define RX_FLOW_MNG_MSK 0x0000ffff
++#define RX_FLOW_MNG_I_MSK 0xffff0000
++#define RX_FLOW_MNG_SFT 0
++#define RX_FLOW_MNG_HI 15
++#define RX_FLOW_MNG_SZ 16
++#define RX_FLOW_CTRL_MSK 0x0000ffff
++#define RX_FLOW_CTRL_I_MSK 0xffff0000
++#define RX_FLOW_CTRL_SFT 0
++#define RX_FLOW_CTRL_HI 15
++#define RX_FLOW_CTRL_SZ 16
++#define MRX_STP_EN_MSK 0x00000001
++#define MRX_STP_EN_I_MSK 0xfffffffe
++#define MRX_STP_EN_SFT 0
++#define MRX_STP_EN_HI 0
++#define MRX_STP_EN_SZ 1
++#define MRX_STP_OFST_MSK 0x0000ff00
++#define MRX_STP_OFST_I_MSK 0xffff00ff
++#define MRX_STP_OFST_SFT 8
++#define MRX_STP_OFST_HI 15
++#define MRX_STP_OFST_SZ 8
++#define DBG_FF_FULL_MSK 0x0000ffff
++#define DBG_FF_FULL_I_MSK 0xffff0000
++#define DBG_FF_FULL_SFT 0
++#define DBG_FF_FULL_HI 15
++#define DBG_FF_FULL_SZ 16
++#define DBG_FF_FULL_CLR_MSK 0x80000000
++#define DBG_FF_FULL_CLR_I_MSK 0x7fffffff
++#define DBG_FF_FULL_CLR_SFT 31
++#define DBG_FF_FULL_CLR_HI 31
++#define DBG_FF_FULL_CLR_SZ 1
++#define DBG_WFF_FULL_MSK 0x0000ffff
++#define DBG_WFF_FULL_I_MSK 0xffff0000
++#define DBG_WFF_FULL_SFT 0
++#define DBG_WFF_FULL_HI 15
++#define DBG_WFF_FULL_SZ 16
++#define DBG_WFF_FULL_CLR_MSK 0x80000000
++#define DBG_WFF_FULL_CLR_I_MSK 0x7fffffff
++#define DBG_WFF_FULL_CLR_SFT 31
++#define DBG_WFF_FULL_CLR_HI 31
++#define DBG_WFF_FULL_CLR_SZ 1
++#define DBG_MB_FULL_MSK 0x0000ffff
++#define DBG_MB_FULL_I_MSK 0xffff0000
++#define DBG_MB_FULL_SFT 0
++#define DBG_MB_FULL_HI 15
++#define DBG_MB_FULL_SZ 16
++#define DBG_MB_FULL_CLR_MSK 0x80000000
++#define DBG_MB_FULL_CLR_I_MSK 0x7fffffff
++#define DBG_MB_FULL_CLR_SFT 31
++#define DBG_MB_FULL_CLR_HI 31
++#define DBG_MB_FULL_CLR_SZ 1
++#define BA_CTRL_MSK 0x00000003
++#define BA_CTRL_I_MSK 0xfffffffc
++#define BA_CTRL_SFT 0
++#define BA_CTRL_HI 1
++#define BA_CTRL_SZ 2
++#define BA_DBG_EN_MSK 0x00000004
++#define BA_DBG_EN_I_MSK 0xfffffffb
++#define BA_DBG_EN_SFT 2
++#define BA_DBG_EN_HI 2
++#define BA_DBG_EN_SZ 1
++#define BA_AGRE_EN_MSK 0x00000008
++#define BA_AGRE_EN_I_MSK 0xfffffff7
++#define BA_AGRE_EN_SFT 3
++#define BA_AGRE_EN_HI 3
++#define BA_AGRE_EN_SZ 1
++#define BA_TA_31_0_MSK 0xffffffff
++#define BA_TA_31_0_I_MSK 0x00000000
++#define BA_TA_31_0_SFT 0
++#define BA_TA_31_0_HI 31
++#define BA_TA_31_0_SZ 32
++#define BA_TA_47_32_MSK 0x0000ffff
++#define BA_TA_47_32_I_MSK 0xffff0000
++#define BA_TA_47_32_SFT 0
++#define BA_TA_47_32_HI 15
++#define BA_TA_47_32_SZ 16
++#define BA_TID_MSK 0x0000000f
++#define BA_TID_I_MSK 0xfffffff0
++#define BA_TID_SFT 0
++#define BA_TID_HI 3
++#define BA_TID_SZ 4
++#define BA_ST_SEQ_MSK 0x00000fff
++#define BA_ST_SEQ_I_MSK 0xfffff000
++#define BA_ST_SEQ_SFT 0
++#define BA_ST_SEQ_HI 11
++#define BA_ST_SEQ_SZ 12
++#define BA_SB0_MSK 0xffffffff
++#define BA_SB0_I_MSK 0x00000000
++#define BA_SB0_SFT 0
++#define BA_SB0_HI 31
++#define BA_SB0_SZ 32
++#define BA_SB1_MSK 0xffffffff
++#define BA_SB1_I_MSK 0x00000000
++#define BA_SB1_SFT 0
++#define BA_SB1_HI 31
++#define BA_SB1_SZ 32
++#define MRX_WD_MSK 0x0001ffff
++#define MRX_WD_I_MSK 0xfffe0000
++#define MRX_WD_SFT 0
++#define MRX_WD_HI 16
++#define MRX_WD_SZ 17
++#define ACK_GEN_EN_MSK 0x00000001
++#define ACK_GEN_EN_I_MSK 0xfffffffe
++#define ACK_GEN_EN_SFT 0
++#define ACK_GEN_EN_HI 0
++#define ACK_GEN_EN_SZ 1
++#define BA_GEN_EN_MSK 0x00000002
++#define BA_GEN_EN_I_MSK 0xfffffffd
++#define BA_GEN_EN_SFT 1
++#define BA_GEN_EN_HI 1
++#define BA_GEN_EN_SZ 1
++#define ACK_GEN_DUR_MSK 0x0000ffff
++#define ACK_GEN_DUR_I_MSK 0xffff0000
++#define ACK_GEN_DUR_SFT 0
++#define ACK_GEN_DUR_HI 15
++#define ACK_GEN_DUR_SZ 16
++#define ACK_GEN_INFO_MSK 0x003f0000
++#define ACK_GEN_INFO_I_MSK 0xffc0ffff
++#define ACK_GEN_INFO_SFT 16
++#define ACK_GEN_INFO_HI 21
++#define ACK_GEN_INFO_SZ 6
++#define ACK_GEN_RA_31_0_MSK 0xffffffff
++#define ACK_GEN_RA_31_0_I_MSK 0x00000000
++#define ACK_GEN_RA_31_0_SFT 0
++#define ACK_GEN_RA_31_0_HI 31
++#define ACK_GEN_RA_31_0_SZ 32
++#define ACK_GEN_RA_47_32_MSK 0x0000ffff
++#define ACK_GEN_RA_47_32_I_MSK 0xffff0000
++#define ACK_GEN_RA_47_32_SFT 0
++#define ACK_GEN_RA_47_32_HI 15
++#define ACK_GEN_RA_47_32_SZ 16
++#define MIB_LEN_FAIL_MSK 0x0000ffff
++#define MIB_LEN_FAIL_I_MSK 0xffff0000
++#define MIB_LEN_FAIL_SFT 0
++#define MIB_LEN_FAIL_HI 15
++#define MIB_LEN_FAIL_SZ 16
++#define TRAP_HW_ID_MSK 0x0000000f
++#define TRAP_HW_ID_I_MSK 0xfffffff0
++#define TRAP_HW_ID_SFT 0
++#define TRAP_HW_ID_HI 3
++#define TRAP_HW_ID_SZ 4
++#define ID_IN_USE_MSK 0x000000ff
++#define ID_IN_USE_I_MSK 0xffffff00
++#define ID_IN_USE_SFT 0
++#define ID_IN_USE_HI 7
++#define ID_IN_USE_SZ 8
++#define MRX_ERR_MSK 0xffffffff
++#define MRX_ERR_I_MSK 0x00000000
++#define MRX_ERR_SFT 0
++#define MRX_ERR_HI 31
++#define MRX_ERR_SZ 32
++#define W0_T0_SEQ_MSK 0x0000ffff
++#define W0_T0_SEQ_I_MSK 0xffff0000
++#define W0_T0_SEQ_SFT 0
++#define W0_T0_SEQ_HI 15
++#define W0_T0_SEQ_SZ 16
++#define W0_T1_SEQ_MSK 0x0000ffff
++#define W0_T1_SEQ_I_MSK 0xffff0000
++#define W0_T1_SEQ_SFT 0
++#define W0_T1_SEQ_HI 15
++#define W0_T1_SEQ_SZ 16
++#define W0_T2_SEQ_MSK 0x0000ffff
++#define W0_T2_SEQ_I_MSK 0xffff0000
++#define W0_T2_SEQ_SFT 0
++#define W0_T2_SEQ_HI 15
++#define W0_T2_SEQ_SZ 16
++#define W0_T3_SEQ_MSK 0x0000ffff
++#define W0_T3_SEQ_I_MSK 0xffff0000
++#define W0_T3_SEQ_SFT 0
++#define W0_T3_SEQ_HI 15
++#define W0_T3_SEQ_SZ 16
++#define W0_T4_SEQ_MSK 0x0000ffff
++#define W0_T4_SEQ_I_MSK 0xffff0000
++#define W0_T4_SEQ_SFT 0
++#define W0_T4_SEQ_HI 15
++#define W0_T4_SEQ_SZ 16
++#define W0_T5_SEQ_MSK 0x0000ffff
++#define W0_T5_SEQ_I_MSK 0xffff0000
++#define W0_T5_SEQ_SFT 0
++#define W0_T5_SEQ_HI 15
++#define W0_T5_SEQ_SZ 16
++#define W0_T6_SEQ_MSK 0x0000ffff
++#define W0_T6_SEQ_I_MSK 0xffff0000
++#define W0_T6_SEQ_SFT 0
++#define W0_T6_SEQ_HI 15
++#define W0_T6_SEQ_SZ 16
++#define W0_T7_SEQ_MSK 0x0000ffff
++#define W0_T7_SEQ_I_MSK 0xffff0000
++#define W0_T7_SEQ_SFT 0
++#define W0_T7_SEQ_HI 15
++#define W0_T7_SEQ_SZ 16
++#define W1_T0_SEQ_MSK 0x0000ffff
++#define W1_T0_SEQ_I_MSK 0xffff0000
++#define W1_T0_SEQ_SFT 0
++#define W1_T0_SEQ_HI 15
++#define W1_T0_SEQ_SZ 16
++#define W1_T1_SEQ_MSK 0x0000ffff
++#define W1_T1_SEQ_I_MSK 0xffff0000
++#define W1_T1_SEQ_SFT 0
++#define W1_T1_SEQ_HI 15
++#define W1_T1_SEQ_SZ 16
++#define W1_T2_SEQ_MSK 0x0000ffff
++#define W1_T2_SEQ_I_MSK 0xffff0000
++#define W1_T2_SEQ_SFT 0
++#define W1_T2_SEQ_HI 15
++#define W1_T2_SEQ_SZ 16
++#define W1_T3_SEQ_MSK 0x0000ffff
++#define W1_T3_SEQ_I_MSK 0xffff0000
++#define W1_T3_SEQ_SFT 0
++#define W1_T3_SEQ_HI 15
++#define W1_T3_SEQ_SZ 16
++#define W1_T4_SEQ_MSK 0x0000ffff
++#define W1_T4_SEQ_I_MSK 0xffff0000
++#define W1_T4_SEQ_SFT 0
++#define W1_T4_SEQ_HI 15
++#define W1_T4_SEQ_SZ 16
++#define W1_T5_SEQ_MSK 0x0000ffff
++#define W1_T5_SEQ_I_MSK 0xffff0000
++#define W1_T5_SEQ_SFT 0
++#define W1_T5_SEQ_HI 15
++#define W1_T5_SEQ_SZ 16
++#define W1_T6_SEQ_MSK 0x0000ffff
++#define W1_T6_SEQ_I_MSK 0xffff0000
++#define W1_T6_SEQ_SFT 0
++#define W1_T6_SEQ_HI 15
++#define W1_T6_SEQ_SZ 16
++#define W1_T7_SEQ_MSK 0x0000ffff
++#define W1_T7_SEQ_I_MSK 0xffff0000
++#define W1_T7_SEQ_SFT 0
++#define W1_T7_SEQ_HI 15
++#define W1_T7_SEQ_SZ 16
++#define ADDR1A_SEL_MSK 0x00000003
++#define ADDR1A_SEL_I_MSK 0xfffffffc
++#define ADDR1A_SEL_SFT 0
++#define ADDR1A_SEL_HI 1
++#define ADDR1A_SEL_SZ 2
++#define ADDR2A_SEL_MSK 0x0000000c
++#define ADDR2A_SEL_I_MSK 0xfffffff3
++#define ADDR2A_SEL_SFT 2
++#define ADDR2A_SEL_HI 3
++#define ADDR2A_SEL_SZ 2
++#define ADDR3A_SEL_MSK 0x00000030
++#define ADDR3A_SEL_I_MSK 0xffffffcf
++#define ADDR3A_SEL_SFT 4
++#define ADDR3A_SEL_HI 5
++#define ADDR3A_SEL_SZ 2
++#define ADDR1B_SEL_MSK 0x000000c0
++#define ADDR1B_SEL_I_MSK 0xffffff3f
++#define ADDR1B_SEL_SFT 6
++#define ADDR1B_SEL_HI 7
++#define ADDR1B_SEL_SZ 2
++#define ADDR2B_SEL_MSK 0x00000300
++#define ADDR2B_SEL_I_MSK 0xfffffcff
++#define ADDR2B_SEL_SFT 8
++#define ADDR2B_SEL_HI 9
++#define ADDR2B_SEL_SZ 2
++#define ADDR3B_SEL_MSK 0x00000c00
++#define ADDR3B_SEL_I_MSK 0xfffff3ff
++#define ADDR3B_SEL_SFT 10
++#define ADDR3B_SEL_HI 11
++#define ADDR3B_SEL_SZ 2
++#define ADDR3C_SEL_MSK 0x00003000
++#define ADDR3C_SEL_I_MSK 0xffffcfff
++#define ADDR3C_SEL_SFT 12
++#define ADDR3C_SEL_HI 13
++#define ADDR3C_SEL_SZ 2
++#define FRM_CTRL_MSK 0x0000003f
++#define FRM_CTRL_I_MSK 0xffffffc0
++#define FRM_CTRL_SFT 0
++#define FRM_CTRL_HI 5
++#define FRM_CTRL_SZ 6
++#define CSR_PHY_INFO_MSK 0x00007fff
++#define CSR_PHY_INFO_I_MSK 0xffff8000
++#define CSR_PHY_INFO_SFT 0
++#define CSR_PHY_INFO_HI 14
++#define CSR_PHY_INFO_SZ 15
++#define AMPDU_SIG_MSK 0x000000ff
++#define AMPDU_SIG_I_MSK 0xffffff00
++#define AMPDU_SIG_SFT 0
++#define AMPDU_SIG_HI 7
++#define AMPDU_SIG_SZ 8
++#define MIB_AMPDU_MSK 0xffffffff
++#define MIB_AMPDU_I_MSK 0x00000000
++#define MIB_AMPDU_SFT 0
++#define MIB_AMPDU_HI 31
++#define MIB_AMPDU_SZ 32
++#define LEN_FLT_MSK 0x0000ffff
++#define LEN_FLT_I_MSK 0xffff0000
++#define LEN_FLT_SFT 0
++#define LEN_FLT_HI 15
++#define LEN_FLT_SZ 16
++#define MIB_DELIMITER_MSK 0x0000ffff
++#define MIB_DELIMITER_I_MSK 0xffff0000
++#define MIB_DELIMITER_SFT 0
++#define MIB_DELIMITER_HI 15
++#define MIB_DELIMITER_SZ 16
++#define MTX_INT_Q0_Q_EMPTY_MSK 0x00010000
++#define MTX_INT_Q0_Q_EMPTY_I_MSK 0xfffeffff
++#define MTX_INT_Q0_Q_EMPTY_SFT 16
++#define MTX_INT_Q0_Q_EMPTY_HI 16
++#define MTX_INT_Q0_Q_EMPTY_SZ 1
++#define MTX_INT_Q0_TXOP_RUNOUT_MSK 0x00020000
++#define MTX_INT_Q0_TXOP_RUNOUT_I_MSK 0xfffdffff
++#define MTX_INT_Q0_TXOP_RUNOUT_SFT 17
++#define MTX_INT_Q0_TXOP_RUNOUT_HI 17
++#define MTX_INT_Q0_TXOP_RUNOUT_SZ 1
++#define MTX_INT_Q1_Q_EMPTY_MSK 0x00040000
++#define MTX_INT_Q1_Q_EMPTY_I_MSK 0xfffbffff
++#define MTX_INT_Q1_Q_EMPTY_SFT 18
++#define MTX_INT_Q1_Q_EMPTY_HI 18
++#define MTX_INT_Q1_Q_EMPTY_SZ 1
++#define MTX_INT_Q1_TXOP_RUNOUT_MSK 0x00080000
++#define MTX_INT_Q1_TXOP_RUNOUT_I_MSK 0xfff7ffff
++#define MTX_INT_Q1_TXOP_RUNOUT_SFT 19
++#define MTX_INT_Q1_TXOP_RUNOUT_HI 19
++#define MTX_INT_Q1_TXOP_RUNOUT_SZ 1
++#define MTX_INT_Q2_Q_EMPTY_MSK 0x00100000
++#define MTX_INT_Q2_Q_EMPTY_I_MSK 0xffefffff
++#define MTX_INT_Q2_Q_EMPTY_SFT 20
++#define MTX_INT_Q2_Q_EMPTY_HI 20
++#define MTX_INT_Q2_Q_EMPTY_SZ 1
++#define MTX_INT_Q2_TXOP_RUNOUT_MSK 0x00200000
++#define MTX_INT_Q2_TXOP_RUNOUT_I_MSK 0xffdfffff
++#define MTX_INT_Q2_TXOP_RUNOUT_SFT 21
++#define MTX_INT_Q2_TXOP_RUNOUT_HI 21
++#define MTX_INT_Q2_TXOP_RUNOUT_SZ 1
++#define MTX_INT_Q3_Q_EMPTY_MSK 0x00400000
++#define MTX_INT_Q3_Q_EMPTY_I_MSK 0xffbfffff
++#define MTX_INT_Q3_Q_EMPTY_SFT 22
++#define MTX_INT_Q3_Q_EMPTY_HI 22
++#define MTX_INT_Q3_Q_EMPTY_SZ 1
++#define MTX_INT_Q3_TXOP_RUNOUT_MSK 0x00800000
++#define MTX_INT_Q3_TXOP_RUNOUT_I_MSK 0xff7fffff
++#define MTX_INT_Q3_TXOP_RUNOUT_SFT 23
++#define MTX_INT_Q3_TXOP_RUNOUT_HI 23
++#define MTX_INT_Q3_TXOP_RUNOUT_SZ 1
++#define MTX_INT_Q4_Q_EMPTY_MSK 0x01000000
++#define MTX_INT_Q4_Q_EMPTY_I_MSK 0xfeffffff
++#define MTX_INT_Q4_Q_EMPTY_SFT 24
++#define MTX_INT_Q4_Q_EMPTY_HI 24
++#define MTX_INT_Q4_Q_EMPTY_SZ 1
++#define MTX_INT_Q4_TXOP_RUNOUT_MSK 0x02000000
++#define MTX_INT_Q4_TXOP_RUNOUT_I_MSK 0xfdffffff
++#define MTX_INT_Q4_TXOP_RUNOUT_SFT 25
++#define MTX_INT_Q4_TXOP_RUNOUT_HI 25
++#define MTX_INT_Q4_TXOP_RUNOUT_SZ 1
++#define MTX_EN_INT_Q0_Q_EMPTY_MSK 0x00010000
++#define MTX_EN_INT_Q0_Q_EMPTY_I_MSK 0xfffeffff
++#define MTX_EN_INT_Q0_Q_EMPTY_SFT 16
++#define MTX_EN_INT_Q0_Q_EMPTY_HI 16
++#define MTX_EN_INT_Q0_Q_EMPTY_SZ 1
++#define MTX_EN_INT_Q0_TXOP_RUNOUT_MSK 0x00020000
++#define MTX_EN_INT_Q0_TXOP_RUNOUT_I_MSK 0xfffdffff
++#define MTX_EN_INT_Q0_TXOP_RUNOUT_SFT 17
++#define MTX_EN_INT_Q0_TXOP_RUNOUT_HI 17
++#define MTX_EN_INT_Q0_TXOP_RUNOUT_SZ 1
++#define MTX_EN_INT_Q1_Q_EMPTY_MSK 0x00040000
++#define MTX_EN_INT_Q1_Q_EMPTY_I_MSK 0xfffbffff
++#define MTX_EN_INT_Q1_Q_EMPTY_SFT 18
++#define MTX_EN_INT_Q1_Q_EMPTY_HI 18
++#define MTX_EN_INT_Q1_Q_EMPTY_SZ 1
++#define MTX_EN_INT_Q1_TXOP_RUNOUT_MSK 0x00080000
++#define MTX_EN_INT_Q1_TXOP_RUNOUT_I_MSK 0xfff7ffff
++#define MTX_EN_INT_Q1_TXOP_RUNOUT_SFT 19
++#define MTX_EN_INT_Q1_TXOP_RUNOUT_HI 19
++#define MTX_EN_INT_Q1_TXOP_RUNOUT_SZ 1
++#define MTX_EN_INT_Q2_Q_EMPTY_MSK 0x00100000
++#define MTX_EN_INT_Q2_Q_EMPTY_I_MSK 0xffefffff
++#define MTX_EN_INT_Q2_Q_EMPTY_SFT 20
++#define MTX_EN_INT_Q2_Q_EMPTY_HI 20
++#define MTX_EN_INT_Q2_Q_EMPTY_SZ 1
++#define MTX_EN_INT_Q2_TXOP_RUNOUT_MSK 0x00200000
++#define MTX_EN_INT_Q2_TXOP_RUNOUT_I_MSK 0xffdfffff
++#define MTX_EN_INT_Q2_TXOP_RUNOUT_SFT 21
++#define MTX_EN_INT_Q2_TXOP_RUNOUT_HI 21
++#define MTX_EN_INT_Q2_TXOP_RUNOUT_SZ 1
++#define MTX_EN_INT_Q3_Q_EMPTY_MSK 0x00400000
++#define MTX_EN_INT_Q3_Q_EMPTY_I_MSK 0xffbfffff
++#define MTX_EN_INT_Q3_Q_EMPTY_SFT 22
++#define MTX_EN_INT_Q3_Q_EMPTY_HI 22
++#define MTX_EN_INT_Q3_Q_EMPTY_SZ 1
++#define MTX_EN_INT_Q3_TXOP_RUNOUT_MSK 0x00800000
++#define MTX_EN_INT_Q3_TXOP_RUNOUT_I_MSK 0xff7fffff
++#define MTX_EN_INT_Q3_TXOP_RUNOUT_SFT 23
++#define MTX_EN_INT_Q3_TXOP_RUNOUT_HI 23
++#define MTX_EN_INT_Q3_TXOP_RUNOUT_SZ 1
++#define MTX_EN_INT_Q4_Q_EMPTY_MSK 0x01000000
++#define MTX_EN_INT_Q4_Q_EMPTY_I_MSK 0xfeffffff
++#define MTX_EN_INT_Q4_Q_EMPTY_SFT 24
++#define MTX_EN_INT_Q4_Q_EMPTY_HI 24
++#define MTX_EN_INT_Q4_Q_EMPTY_SZ 1
++#define MTX_EN_INT_Q4_TXOP_RUNOUT_MSK 0x02000000
++#define MTX_EN_INT_Q4_TXOP_RUNOUT_I_MSK 0xfdffffff
++#define MTX_EN_INT_Q4_TXOP_RUNOUT_SFT 25
++#define MTX_EN_INT_Q4_TXOP_RUNOUT_HI 25
++#define MTX_EN_INT_Q4_TXOP_RUNOUT_SZ 1
++#define MTX_MTX2PHY_SLOW_MSK 0x00000001
++#define MTX_MTX2PHY_SLOW_I_MSK 0xfffffffe
++#define MTX_MTX2PHY_SLOW_SFT 0
++#define MTX_MTX2PHY_SLOW_HI 0
++#define MTX_MTX2PHY_SLOW_SZ 1
++#define MTX_M2M_SLOW_PRD_MSK 0x0000000e
++#define MTX_M2M_SLOW_PRD_I_MSK 0xfffffff1
++#define MTX_M2M_SLOW_PRD_SFT 1
++#define MTX_M2M_SLOW_PRD_HI 3
++#define MTX_M2M_SLOW_PRD_SZ 3
++#define MTX_AMPDU_CRC_AUTO_MSK 0x00000020
++#define MTX_AMPDU_CRC_AUTO_I_MSK 0xffffffdf
++#define MTX_AMPDU_CRC_AUTO_SFT 5
++#define MTX_AMPDU_CRC_AUTO_HI 5
++#define MTX_AMPDU_CRC_AUTO_SZ 1
++#define MTX_FAST_RSP_MODE_MSK 0x00000040
++#define MTX_FAST_RSP_MODE_I_MSK 0xffffffbf
++#define MTX_FAST_RSP_MODE_SFT 6
++#define MTX_FAST_RSP_MODE_HI 6
++#define MTX_FAST_RSP_MODE_SZ 1
++#define MTX_RAW_DATA_MODE_MSK 0x00000080
++#define MTX_RAW_DATA_MODE_I_MSK 0xffffff7f
++#define MTX_RAW_DATA_MODE_SFT 7
++#define MTX_RAW_DATA_MODE_HI 7
++#define MTX_RAW_DATA_MODE_SZ 1
++#define MTX_ACK_DUR0_MSK 0x00000100
++#define MTX_ACK_DUR0_I_MSK 0xfffffeff
++#define MTX_ACK_DUR0_SFT 8
++#define MTX_ACK_DUR0_HI 8
++#define MTX_ACK_DUR0_SZ 1
++#define MTX_TSF_AUTO_BCN_MSK 0x00000400
++#define MTX_TSF_AUTO_BCN_I_MSK 0xfffffbff
++#define MTX_TSF_AUTO_BCN_SFT 10
++#define MTX_TSF_AUTO_BCN_HI 10
++#define MTX_TSF_AUTO_BCN_SZ 1
++#define MTX_TSF_AUTO_MISC_MSK 0x00000800
++#define MTX_TSF_AUTO_MISC_I_MSK 0xfffff7ff
++#define MTX_TSF_AUTO_MISC_SFT 11
++#define MTX_TSF_AUTO_MISC_HI 11
++#define MTX_TSF_AUTO_MISC_SZ 1
++#define MTX_FORCE_CS_IDLE_MSK 0x00001000
++#define MTX_FORCE_CS_IDLE_I_MSK 0xffffefff
++#define MTX_FORCE_CS_IDLE_SFT 12
++#define MTX_FORCE_CS_IDLE_HI 12
++#define MTX_FORCE_CS_IDLE_SZ 1
++#define MTX_FORCE_BKF_RXEN0_MSK 0x00002000
++#define MTX_FORCE_BKF_RXEN0_I_MSK 0xffffdfff
++#define MTX_FORCE_BKF_RXEN0_SFT 13
++#define MTX_FORCE_BKF_RXEN0_HI 13
++#define MTX_FORCE_BKF_RXEN0_SZ 1
++#define MTX_FORCE_DMA_RXEN0_MSK 0x00004000
++#define MTX_FORCE_DMA_RXEN0_I_MSK 0xffffbfff
++#define MTX_FORCE_DMA_RXEN0_SFT 14
++#define MTX_FORCE_DMA_RXEN0_HI 14
++#define MTX_FORCE_DMA_RXEN0_SZ 1
++#define MTX_FORCE_RXEN0_MSK 0x00008000
++#define MTX_FORCE_RXEN0_I_MSK 0xffff7fff
++#define MTX_FORCE_RXEN0_SFT 15
++#define MTX_FORCE_RXEN0_HI 15
++#define MTX_FORCE_RXEN0_SZ 1
++#define MTX_HALT_Q_MB_MSK 0x003f0000
++#define MTX_HALT_Q_MB_I_MSK 0xffc0ffff
++#define MTX_HALT_Q_MB_SFT 16
++#define MTX_HALT_Q_MB_HI 21
++#define MTX_HALT_Q_MB_SZ 6
++#define MTX_CTS_SET_DIF_MSK 0x00400000
++#define MTX_CTS_SET_DIF_I_MSK 0xffbfffff
++#define MTX_CTS_SET_DIF_SFT 22
++#define MTX_CTS_SET_DIF_HI 22
++#define MTX_CTS_SET_DIF_SZ 1
++#define MTX_AMPDU_SET_DIF_MSK 0x00800000
++#define MTX_AMPDU_SET_DIF_I_MSK 0xff7fffff
++#define MTX_AMPDU_SET_DIF_SFT 23
++#define MTX_AMPDU_SET_DIF_HI 23
++#define MTX_AMPDU_SET_DIF_SZ 1
++#define MTX_EDCCA_TOUT_MSK 0x000003ff
++#define MTX_EDCCA_TOUT_I_MSK 0xfffffc00
++#define MTX_EDCCA_TOUT_SFT 0
++#define MTX_EDCCA_TOUT_HI 9
++#define MTX_EDCCA_TOUT_SZ 10
++#define MTX_INT_BCN_MSK 0x00000002
++#define MTX_INT_BCN_I_MSK 0xfffffffd
++#define MTX_INT_BCN_SFT 1
++#define MTX_INT_BCN_HI 1
++#define MTX_INT_BCN_SZ 1
++#define MTX_INT_DTIM_MSK 0x00000008
++#define MTX_INT_DTIM_I_MSK 0xfffffff7
++#define MTX_INT_DTIM_SFT 3
++#define MTX_INT_DTIM_HI 3
++#define MTX_INT_DTIM_SZ 1
++#define MTX_EN_INT_BCN_MSK 0x00000002
++#define MTX_EN_INT_BCN_I_MSK 0xfffffffd
++#define MTX_EN_INT_BCN_SFT 1
++#define MTX_EN_INT_BCN_HI 1
++#define MTX_EN_INT_BCN_SZ 1
++#define MTX_EN_INT_DTIM_MSK 0x00000008
++#define MTX_EN_INT_DTIM_I_MSK 0xfffffff7
++#define MTX_EN_INT_DTIM_SFT 3
++#define MTX_EN_INT_DTIM_HI 3
++#define MTX_EN_INT_DTIM_SZ 1
++#define MTX_BCN_TIMER_EN_MSK 0x00000001
++#define MTX_BCN_TIMER_EN_I_MSK 0xfffffffe
++#define MTX_BCN_TIMER_EN_SFT 0
++#define MTX_BCN_TIMER_EN_HI 0
++#define MTX_BCN_TIMER_EN_SZ 1
++#define MTX_TIME_STAMP_AUTO_FILL_MSK 0x00000002
++#define MTX_TIME_STAMP_AUTO_FILL_I_MSK 0xfffffffd
++#define MTX_TIME_STAMP_AUTO_FILL_SFT 1
++#define MTX_TIME_STAMP_AUTO_FILL_HI 1
++#define MTX_TIME_STAMP_AUTO_FILL_SZ 1
++#define MTX_TSF_TIMER_EN_MSK 0x00000020
++#define MTX_TSF_TIMER_EN_I_MSK 0xffffffdf
++#define MTX_TSF_TIMER_EN_SFT 5
++#define MTX_TSF_TIMER_EN_HI 5
++#define MTX_TSF_TIMER_EN_SZ 1
++#define MTX_HALT_MNG_UNTIL_DTIM_MSK 0x00000040
++#define MTX_HALT_MNG_UNTIL_DTIM_I_MSK 0xffffffbf
++#define MTX_HALT_MNG_UNTIL_DTIM_SFT 6
++#define MTX_HALT_MNG_UNTIL_DTIM_HI 6
++#define MTX_HALT_MNG_UNTIL_DTIM_SZ 1
++#define MTX_INT_DTIM_NUM_MSK 0x0000ff00
++#define MTX_INT_DTIM_NUM_I_MSK 0xffff00ff
++#define MTX_INT_DTIM_NUM_SFT 8
++#define MTX_INT_DTIM_NUM_HI 15
++#define MTX_INT_DTIM_NUM_SZ 8
++#define MTX_AUTO_FLUSH_Q4_MSK 0x00010000
++#define MTX_AUTO_FLUSH_Q4_I_MSK 0xfffeffff
++#define MTX_AUTO_FLUSH_Q4_SFT 16
++#define MTX_AUTO_FLUSH_Q4_HI 16
++#define MTX_AUTO_FLUSH_Q4_SZ 1
++#define MTX_BCN_PKTID_CH_LOCK_MSK 0x00000001
++#define MTX_BCN_PKTID_CH_LOCK_I_MSK 0xfffffffe
++#define MTX_BCN_PKTID_CH_LOCK_SFT 0
++#define MTX_BCN_PKTID_CH_LOCK_HI 0
++#define MTX_BCN_PKTID_CH_LOCK_SZ 1
++#define MTX_BCN_CFG_VLD_MSK 0x00000006
++#define MTX_BCN_CFG_VLD_I_MSK 0xfffffff9
++#define MTX_BCN_CFG_VLD_SFT 1
++#define MTX_BCN_CFG_VLD_HI 2
++#define MTX_BCN_CFG_VLD_SZ 2
++#define MTX_AUTO_BCN_ONGOING_MSK 0x00000008
++#define MTX_AUTO_BCN_ONGOING_I_MSK 0xfffffff7
++#define MTX_AUTO_BCN_ONGOING_SFT 3
++#define MTX_AUTO_BCN_ONGOING_HI 3
++#define MTX_AUTO_BCN_ONGOING_SZ 1
++#define MTX_BCN_TIMER_MSK 0xffff0000
++#define MTX_BCN_TIMER_I_MSK 0x0000ffff
++#define MTX_BCN_TIMER_SFT 16
++#define MTX_BCN_TIMER_HI 31
++#define MTX_BCN_TIMER_SZ 16
++#define MTX_BCN_PERIOD_MSK 0x0000ffff
++#define MTX_BCN_PERIOD_I_MSK 0xffff0000
++#define MTX_BCN_PERIOD_SFT 0
++#define MTX_BCN_PERIOD_HI 15
++#define MTX_BCN_PERIOD_SZ 16
++#define MTX_DTIM_NUM_MSK 0xff000000
++#define MTX_DTIM_NUM_I_MSK 0x00ffffff
++#define MTX_DTIM_NUM_SFT 24
++#define MTX_DTIM_NUM_HI 31
++#define MTX_DTIM_NUM_SZ 8
++#define MTX_BCN_TSF_L_MSK 0xffffffff
++#define MTX_BCN_TSF_L_I_MSK 0x00000000
++#define MTX_BCN_TSF_L_SFT 0
++#define MTX_BCN_TSF_L_HI 31
++#define MTX_BCN_TSF_L_SZ 32
++#define MTX_BCN_TSF_U_MSK 0xffffffff
++#define MTX_BCN_TSF_U_I_MSK 0x00000000
++#define MTX_BCN_TSF_U_SFT 0
++#define MTX_BCN_TSF_U_HI 31
++#define MTX_BCN_TSF_U_SZ 32
++#define MTX_BCN_PKT_ID0_MSK 0x0000007f
++#define MTX_BCN_PKT_ID0_I_MSK 0xffffff80
++#define MTX_BCN_PKT_ID0_SFT 0
++#define MTX_BCN_PKT_ID0_HI 6
++#define MTX_BCN_PKT_ID0_SZ 7
++#define MTX_DTIM_OFST0_MSK 0x03ff0000
++#define MTX_DTIM_OFST0_I_MSK 0xfc00ffff
++#define MTX_DTIM_OFST0_SFT 16
++#define MTX_DTIM_OFST0_HI 25
++#define MTX_DTIM_OFST0_SZ 10
++#define MTX_BCN_PKT_ID1_MSK 0x0000007f
++#define MTX_BCN_PKT_ID1_I_MSK 0xffffff80
++#define MTX_BCN_PKT_ID1_SFT 0
++#define MTX_BCN_PKT_ID1_HI 6
++#define MTX_BCN_PKT_ID1_SZ 7
++#define MTX_DTIM_OFST1_MSK 0x03ff0000
++#define MTX_DTIM_OFST1_I_MSK 0xfc00ffff
++#define MTX_DTIM_OFST1_SFT 16
++#define MTX_DTIM_OFST1_HI 25
++#define MTX_DTIM_OFST1_SZ 10
++#define MTX_CCA_MSK 0x00000001
++#define MTX_CCA_I_MSK 0xfffffffe
++#define MTX_CCA_SFT 0
++#define MTX_CCA_HI 0
++#define MTX_CCA_SZ 1
++#define MRX_CCA_MSK 0x00000002
++#define MRX_CCA_I_MSK 0xfffffffd
++#define MRX_CCA_SFT 1
++#define MRX_CCA_HI 1
++#define MRX_CCA_SZ 1
++#define MTX_DMA_FSM_MSK 0x0000001c
++#define MTX_DMA_FSM_I_MSK 0xffffffe3
++#define MTX_DMA_FSM_SFT 2
++#define MTX_DMA_FSM_HI 4
++#define MTX_DMA_FSM_SZ 3
++#define CH_ST_FSM_MSK 0x000000e0
++#define CH_ST_FSM_I_MSK 0xffffff1f
++#define CH_ST_FSM_SFT 5
++#define CH_ST_FSM_HI 7
++#define CH_ST_FSM_SZ 3
++#define MTX_GNT_LOCK_MSK 0x00000100
++#define MTX_GNT_LOCK_I_MSK 0xfffffeff
++#define MTX_GNT_LOCK_SFT 8
++#define MTX_GNT_LOCK_HI 8
++#define MTX_GNT_LOCK_SZ 1
++#define MTX_DMA_REQ_MSK 0x00000200
++#define MTX_DMA_REQ_I_MSK 0xfffffdff
++#define MTX_DMA_REQ_SFT 9
++#define MTX_DMA_REQ_HI 9
++#define MTX_DMA_REQ_SZ 1
++#define MTX_Q_REQ_MSK 0x00000400
++#define MTX_Q_REQ_I_MSK 0xfffffbff
++#define MTX_Q_REQ_SFT 10
++#define MTX_Q_REQ_HI 10
++#define MTX_Q_REQ_SZ 1
++#define MTX_TX_EN_MSK 0x00000800
++#define MTX_TX_EN_I_MSK 0xfffff7ff
++#define MTX_TX_EN_SFT 11
++#define MTX_TX_EN_HI 11
++#define MTX_TX_EN_SZ 1
++#define MRX_RX_EN_MSK 0x00001000
++#define MRX_RX_EN_I_MSK 0xffffefff
++#define MRX_RX_EN_SFT 12
++#define MRX_RX_EN_HI 12
++#define MRX_RX_EN_SZ 1
++#define DBG_PRTC_PRD_MSK 0x00002000
++#define DBG_PRTC_PRD_I_MSK 0xffffdfff
++#define DBG_PRTC_PRD_SFT 13
++#define DBG_PRTC_PRD_HI 13
++#define DBG_PRTC_PRD_SZ 1
++#define DBG_DMA_RDY_MSK 0x00004000
++#define DBG_DMA_RDY_I_MSK 0xffffbfff
++#define DBG_DMA_RDY_SFT 14
++#define DBG_DMA_RDY_HI 14
++#define DBG_DMA_RDY_SZ 1
++#define DBG_WAIT_RSP_MSK 0x00008000
++#define DBG_WAIT_RSP_I_MSK 0xffff7fff
++#define DBG_WAIT_RSP_SFT 15
++#define DBG_WAIT_RSP_HI 15
++#define DBG_WAIT_RSP_SZ 1
++#define DBG_CFRM_BUSY_MSK 0x00010000
++#define DBG_CFRM_BUSY_I_MSK 0xfffeffff
++#define DBG_CFRM_BUSY_SFT 16
++#define DBG_CFRM_BUSY_HI 16
++#define DBG_CFRM_BUSY_SZ 1
++#define DBG_RST_MSK 0x00000001
++#define DBG_RST_I_MSK 0xfffffffe
++#define DBG_RST_SFT 0
++#define DBG_RST_HI 0
++#define DBG_RST_SZ 1
++#define DBG_MODE_MSK 0x00000002
++#define DBG_MODE_I_MSK 0xfffffffd
++#define DBG_MODE_SFT 1
++#define DBG_MODE_HI 1
++#define DBG_MODE_SZ 1
++#define MB_REQ_DUR_MSK 0x0000ffff
++#define MB_REQ_DUR_I_MSK 0xffff0000
++#define MB_REQ_DUR_SFT 0
++#define MB_REQ_DUR_HI 15
++#define MB_REQ_DUR_SZ 16
++#define RX_EN_DUR_MSK 0xffff0000
++#define RX_EN_DUR_I_MSK 0x0000ffff
++#define RX_EN_DUR_SFT 16
++#define RX_EN_DUR_HI 31
++#define RX_EN_DUR_SZ 16
++#define RX_CS_DUR_MSK 0x0000ffff
++#define RX_CS_DUR_I_MSK 0xffff0000
++#define RX_CS_DUR_SFT 0
++#define RX_CS_DUR_HI 15
++#define RX_CS_DUR_SZ 16
++#define TX_CCA_DUR_MSK 0xffff0000
++#define TX_CCA_DUR_I_MSK 0x0000ffff
++#define TX_CCA_DUR_SFT 16
++#define TX_CCA_DUR_HI 31
++#define TX_CCA_DUR_SZ 16
++#define Q_REQ_DUR_MSK 0x0000ffff
++#define Q_REQ_DUR_I_MSK 0xffff0000
++#define Q_REQ_DUR_SFT 0
++#define Q_REQ_DUR_HI 15
++#define Q_REQ_DUR_SZ 16
++#define CH_STA0_DUR_MSK 0xffff0000
++#define CH_STA0_DUR_I_MSK 0x0000ffff
++#define CH_STA0_DUR_SFT 16
++#define CH_STA0_DUR_HI 31
++#define CH_STA0_DUR_SZ 16
++#define MTX_DUR_RSP_TOUT_B_MSK 0x000000ff
++#define MTX_DUR_RSP_TOUT_B_I_MSK 0xffffff00
++#define MTX_DUR_RSP_TOUT_B_SFT 0
++#define MTX_DUR_RSP_TOUT_B_HI 7
++#define MTX_DUR_RSP_TOUT_B_SZ 8
++#define MTX_DUR_RSP_TOUT_G_MSK 0x0000ff00
++#define MTX_DUR_RSP_TOUT_G_I_MSK 0xffff00ff
++#define MTX_DUR_RSP_TOUT_G_SFT 8
++#define MTX_DUR_RSP_TOUT_G_HI 15
++#define MTX_DUR_RSP_TOUT_G_SZ 8
++#define MTX_DUR_RSP_SIFS_MSK 0x000000ff
++#define MTX_DUR_RSP_SIFS_I_MSK 0xffffff00
++#define MTX_DUR_RSP_SIFS_SFT 0
++#define MTX_DUR_RSP_SIFS_HI 7
++#define MTX_DUR_RSP_SIFS_SZ 8
++#define MTX_DUR_BURST_SIFS_MSK 0x0000ff00
++#define MTX_DUR_BURST_SIFS_I_MSK 0xffff00ff
++#define MTX_DUR_BURST_SIFS_SFT 8
++#define MTX_DUR_BURST_SIFS_HI 15
++#define MTX_DUR_BURST_SIFS_SZ 8
++#define MTX_DUR_SLOT_MSK 0x003f0000
++#define MTX_DUR_SLOT_I_MSK 0xffc0ffff
++#define MTX_DUR_SLOT_SFT 16
++#define MTX_DUR_SLOT_HI 21
++#define MTX_DUR_SLOT_SZ 6
++#define MTX_DUR_RSP_EIFS_MSK 0xffc00000
++#define MTX_DUR_RSP_EIFS_I_MSK 0x003fffff
++#define MTX_DUR_RSP_EIFS_SFT 22
++#define MTX_DUR_RSP_EIFS_HI 31
++#define MTX_DUR_RSP_EIFS_SZ 10
++#define MTX_DUR_RSP_SIFS_G_MSK 0x000000ff
++#define MTX_DUR_RSP_SIFS_G_I_MSK 0xffffff00
++#define MTX_DUR_RSP_SIFS_G_SFT 0
++#define MTX_DUR_RSP_SIFS_G_HI 7
++#define MTX_DUR_RSP_SIFS_G_SZ 8
++#define MTX_DUR_BURST_SIFS_G_MSK 0x0000ff00
++#define MTX_DUR_BURST_SIFS_G_I_MSK 0xffff00ff
++#define MTX_DUR_BURST_SIFS_G_SFT 8
++#define MTX_DUR_BURST_SIFS_G_HI 15
++#define MTX_DUR_BURST_SIFS_G_SZ 8
++#define MTX_DUR_SLOT_G_MSK 0x003f0000
++#define MTX_DUR_SLOT_G_I_MSK 0xffc0ffff
++#define MTX_DUR_SLOT_G_SFT 16
++#define MTX_DUR_SLOT_G_HI 21
++#define MTX_DUR_SLOT_G_SZ 6
++#define MTX_DUR_RSP_EIFS_G_MSK 0xffc00000
++#define MTX_DUR_RSP_EIFS_G_I_MSK 0x003fffff
++#define MTX_DUR_RSP_EIFS_G_SFT 22
++#define MTX_DUR_RSP_EIFS_G_HI 31
++#define MTX_DUR_RSP_EIFS_G_SZ 10
++#define CH_STA1_DUR_MSK 0x0000ffff
++#define CH_STA1_DUR_I_MSK 0xffff0000
++#define CH_STA1_DUR_SFT 0
++#define CH_STA1_DUR_HI 15
++#define CH_STA1_DUR_SZ 16
++#define CH_STA2_DUR_MSK 0xffff0000
++#define CH_STA2_DUR_I_MSK 0x0000ffff
++#define CH_STA2_DUR_SFT 16
++#define CH_STA2_DUR_HI 31
++#define CH_STA2_DUR_SZ 16
++#define MTX_NAV_MSK 0x0000ffff
++#define MTX_NAV_I_MSK 0xffff0000
++#define MTX_NAV_SFT 0
++#define MTX_NAV_HI 15
++#define MTX_NAV_SZ 16
++#define MTX_MIB_CNT0_MSK 0x3fffffff
++#define MTX_MIB_CNT0_I_MSK 0xc0000000
++#define MTX_MIB_CNT0_SFT 0
++#define MTX_MIB_CNT0_HI 29
++#define MTX_MIB_CNT0_SZ 30
++#define MTX_MIB_EN0_MSK 0x40000000
++#define MTX_MIB_EN0_I_MSK 0xbfffffff
++#define MTX_MIB_EN0_SFT 30
++#define MTX_MIB_EN0_HI 30
++#define MTX_MIB_EN0_SZ 1
++#define MTX_MIB_CNT1_MSK 0x3fffffff
++#define MTX_MIB_CNT1_I_MSK 0xc0000000
++#define MTX_MIB_CNT1_SFT 0
++#define MTX_MIB_CNT1_HI 29
++#define MTX_MIB_CNT1_SZ 30
++#define MTX_MIB_EN1_MSK 0x40000000
++#define MTX_MIB_EN1_I_MSK 0xbfffffff
++#define MTX_MIB_EN1_SFT 30
++#define MTX_MIB_EN1_HI 30
++#define MTX_MIB_EN1_SZ 1
++#define CH_STA3_DUR_MSK 0x0000ffff
++#define CH_STA3_DUR_I_MSK 0xffff0000
++#define CH_STA3_DUR_SFT 0
++#define CH_STA3_DUR_HI 15
++#define CH_STA3_DUR_SZ 16
++#define CH_STA4_DUR_MSK 0xffff0000
++#define CH_STA4_DUR_I_MSK 0x0000ffff
++#define CH_STA4_DUR_SFT 16
++#define CH_STA4_DUR_HI 31
++#define CH_STA4_DUR_SZ 16
++#define TXQ0_MTX_Q_PRE_LD_MSK 0x00000002
++#define TXQ0_MTX_Q_PRE_LD_I_MSK 0xfffffffd
++#define TXQ0_MTX_Q_PRE_LD_SFT 1
++#define TXQ0_MTX_Q_PRE_LD_HI 1
++#define TXQ0_MTX_Q_PRE_LD_SZ 1
++#define TXQ0_MTX_Q_BKF_CNT_FIXED_MSK 0x00000004
++#define TXQ0_MTX_Q_BKF_CNT_FIXED_I_MSK 0xfffffffb
++#define TXQ0_MTX_Q_BKF_CNT_FIXED_SFT 2
++#define TXQ0_MTX_Q_BKF_CNT_FIXED_HI 2
++#define TXQ0_MTX_Q_BKF_CNT_FIXED_SZ 1
++#define TXQ0_MTX_Q_TXOP_SUB_FRM_TIME_MSK 0x00000008
++#define TXQ0_MTX_Q_TXOP_SUB_FRM_TIME_I_MSK 0xfffffff7
++#define TXQ0_MTX_Q_TXOP_SUB_FRM_TIME_SFT 3
++#define TXQ0_MTX_Q_TXOP_SUB_FRM_TIME_HI 3
++#define TXQ0_MTX_Q_TXOP_SUB_FRM_TIME_SZ 1
++#define TXQ0_MTX_Q_MB_NO_RLS_MSK 0x00000010
++#define TXQ0_MTX_Q_MB_NO_RLS_I_MSK 0xffffffef
++#define TXQ0_MTX_Q_MB_NO_RLS_SFT 4
++#define TXQ0_MTX_Q_MB_NO_RLS_HI 4
++#define TXQ0_MTX_Q_MB_NO_RLS_SZ 1
++#define TXQ0_MTX_Q_TXOP_FRC_BUR_MSK 0x00000020
++#define TXQ0_MTX_Q_TXOP_FRC_BUR_I_MSK 0xffffffdf
++#define TXQ0_MTX_Q_TXOP_FRC_BUR_SFT 5
++#define TXQ0_MTX_Q_TXOP_FRC_BUR_HI 5
++#define TXQ0_MTX_Q_TXOP_FRC_BUR_SZ 1
++#define TXQ0_MTX_Q_RND_MODE_MSK 0x000000c0
++#define TXQ0_MTX_Q_RND_MODE_I_MSK 0xffffff3f
++#define TXQ0_MTX_Q_RND_MODE_SFT 6
++#define TXQ0_MTX_Q_RND_MODE_HI 7
++#define TXQ0_MTX_Q_RND_MODE_SZ 2
++#define TXQ0_MTX_Q_AIFSN_MSK 0x0000000f
++#define TXQ0_MTX_Q_AIFSN_I_MSK 0xfffffff0
++#define TXQ0_MTX_Q_AIFSN_SFT 0
++#define TXQ0_MTX_Q_AIFSN_HI 3
++#define TXQ0_MTX_Q_AIFSN_SZ 4
++#define TXQ0_MTX_Q_ECWMIN_MSK 0x00000f00
++#define TXQ0_MTX_Q_ECWMIN_I_MSK 0xfffff0ff
++#define TXQ0_MTX_Q_ECWMIN_SFT 8
++#define TXQ0_MTX_Q_ECWMIN_HI 11
++#define TXQ0_MTX_Q_ECWMIN_SZ 4
++#define TXQ0_MTX_Q_ECWMAX_MSK 0x0000f000
++#define TXQ0_MTX_Q_ECWMAX_I_MSK 0xffff0fff
++#define TXQ0_MTX_Q_ECWMAX_SFT 12
++#define TXQ0_MTX_Q_ECWMAX_HI 15
++#define TXQ0_MTX_Q_ECWMAX_SZ 4
++#define TXQ0_MTX_Q_TXOP_LIMIT_MSK 0xffff0000
++#define TXQ0_MTX_Q_TXOP_LIMIT_I_MSK 0x0000ffff
++#define TXQ0_MTX_Q_TXOP_LIMIT_SFT 16
++#define TXQ0_MTX_Q_TXOP_LIMIT_HI 31
++#define TXQ0_MTX_Q_TXOP_LIMIT_SZ 16
++#define TXQ0_MTX_Q_BKF_CNT_MSK 0x0000ffff
++#define TXQ0_MTX_Q_BKF_CNT_I_MSK 0xffff0000
++#define TXQ0_MTX_Q_BKF_CNT_SFT 0
++#define TXQ0_MTX_Q_BKF_CNT_HI 15
++#define TXQ0_MTX_Q_BKF_CNT_SZ 16
++#define TXQ0_MTX_Q_SRC_LIMIT_MSK 0x000000ff
++#define TXQ0_MTX_Q_SRC_LIMIT_I_MSK 0xffffff00
++#define TXQ0_MTX_Q_SRC_LIMIT_SFT 0
++#define TXQ0_MTX_Q_SRC_LIMIT_HI 7
++#define TXQ0_MTX_Q_SRC_LIMIT_SZ 8
++#define TXQ0_MTX_Q_LRC_LIMIT_MSK 0x0000ff00
++#define TXQ0_MTX_Q_LRC_LIMIT_I_MSK 0xffff00ff
++#define TXQ0_MTX_Q_LRC_LIMIT_SFT 8
++#define TXQ0_MTX_Q_LRC_LIMIT_HI 15
++#define TXQ0_MTX_Q_LRC_LIMIT_SZ 8
++#define TXQ0_MTX_Q_ID_MAP_L_MSK 0xffffffff
++#define TXQ0_MTX_Q_ID_MAP_L_I_MSK 0x00000000
++#define TXQ0_MTX_Q_ID_MAP_L_SFT 0
++#define TXQ0_MTX_Q_ID_MAP_L_HI 31
++#define TXQ0_MTX_Q_ID_MAP_L_SZ 32
++#define TXQ0_MTX_Q_TXOP_CH_THD_MSK 0x0000ffff
++#define TXQ0_MTX_Q_TXOP_CH_THD_I_MSK 0xffff0000
++#define TXQ0_MTX_Q_TXOP_CH_THD_SFT 0
++#define TXQ0_MTX_Q_TXOP_CH_THD_HI 15
++#define TXQ0_MTX_Q_TXOP_CH_THD_SZ 16
++#define TXQ0_MTX_Q_TXOP_OV_THD_MSK 0x0000ffff
++#define TXQ0_MTX_Q_TXOP_OV_THD_I_MSK 0xffff0000
++#define TXQ0_MTX_Q_TXOP_OV_THD_SFT 0
++#define TXQ0_MTX_Q_TXOP_OV_THD_HI 15
++#define TXQ0_MTX_Q_TXOP_OV_THD_SZ 16
++#define TXQ1_MTX_Q_PRE_LD_MSK 0x00000002
++#define TXQ1_MTX_Q_PRE_LD_I_MSK 0xfffffffd
++#define TXQ1_MTX_Q_PRE_LD_SFT 1
++#define TXQ1_MTX_Q_PRE_LD_HI 1
++#define TXQ1_MTX_Q_PRE_LD_SZ 1
++#define TXQ1_MTX_Q_BKF_CNT_FIXED_MSK 0x00000004
++#define TXQ1_MTX_Q_BKF_CNT_FIXED_I_MSK 0xfffffffb
++#define TXQ1_MTX_Q_BKF_CNT_FIXED_SFT 2
++#define TXQ1_MTX_Q_BKF_CNT_FIXED_HI 2
++#define TXQ1_MTX_Q_BKF_CNT_FIXED_SZ 1
++#define TXQ1_MTX_Q_TXOP_SUB_FRM_TIME_MSK 0x00000008
++#define TXQ1_MTX_Q_TXOP_SUB_FRM_TIME_I_MSK 0xfffffff7
++#define TXQ1_MTX_Q_TXOP_SUB_FRM_TIME_SFT 3
++#define TXQ1_MTX_Q_TXOP_SUB_FRM_TIME_HI 3
++#define TXQ1_MTX_Q_TXOP_SUB_FRM_TIME_SZ 1
++#define TXQ1_MTX_Q_MB_NO_RLS_MSK 0x00000010
++#define TXQ1_MTX_Q_MB_NO_RLS_I_MSK 0xffffffef
++#define TXQ1_MTX_Q_MB_NO_RLS_SFT 4
++#define TXQ1_MTX_Q_MB_NO_RLS_HI 4
++#define TXQ1_MTX_Q_MB_NO_RLS_SZ 1
++#define TXQ1_MTX_Q_TXOP_FRC_BUR_MSK 0x00000020
++#define TXQ1_MTX_Q_TXOP_FRC_BUR_I_MSK 0xffffffdf
++#define TXQ1_MTX_Q_TXOP_FRC_BUR_SFT 5
++#define TXQ1_MTX_Q_TXOP_FRC_BUR_HI 5
++#define TXQ1_MTX_Q_TXOP_FRC_BUR_SZ 1
++#define TXQ1_MTX_Q_RND_MODE_MSK 0x000000c0
++#define TXQ1_MTX_Q_RND_MODE_I_MSK 0xffffff3f
++#define TXQ1_MTX_Q_RND_MODE_SFT 6
++#define TXQ1_MTX_Q_RND_MODE_HI 7
++#define TXQ1_MTX_Q_RND_MODE_SZ 2
++#define TXQ1_MTX_Q_AIFSN_MSK 0x0000000f
++#define TXQ1_MTX_Q_AIFSN_I_MSK 0xfffffff0
++#define TXQ1_MTX_Q_AIFSN_SFT 0
++#define TXQ1_MTX_Q_AIFSN_HI 3
++#define TXQ1_MTX_Q_AIFSN_SZ 4
++#define TXQ1_MTX_Q_ECWMIN_MSK 0x00000f00
++#define TXQ1_MTX_Q_ECWMIN_I_MSK 0xfffff0ff
++#define TXQ1_MTX_Q_ECWMIN_SFT 8
++#define TXQ1_MTX_Q_ECWMIN_HI 11
++#define TXQ1_MTX_Q_ECWMIN_SZ 4
++#define TXQ1_MTX_Q_ECWMAX_MSK 0x0000f000
++#define TXQ1_MTX_Q_ECWMAX_I_MSK 0xffff0fff
++#define TXQ1_MTX_Q_ECWMAX_SFT 12
++#define TXQ1_MTX_Q_ECWMAX_HI 15
++#define TXQ1_MTX_Q_ECWMAX_SZ 4
++#define TXQ1_MTX_Q_TXOP_LIMIT_MSK 0xffff0000
++#define TXQ1_MTX_Q_TXOP_LIMIT_I_MSK 0x0000ffff
++#define TXQ1_MTX_Q_TXOP_LIMIT_SFT 16
++#define TXQ1_MTX_Q_TXOP_LIMIT_HI 31
++#define TXQ1_MTX_Q_TXOP_LIMIT_SZ 16
++#define TXQ1_MTX_Q_BKF_CNT_MSK 0x0000ffff
++#define TXQ1_MTX_Q_BKF_CNT_I_MSK 0xffff0000
++#define TXQ1_MTX_Q_BKF_CNT_SFT 0
++#define TXQ1_MTX_Q_BKF_CNT_HI 15
++#define TXQ1_MTX_Q_BKF_CNT_SZ 16
++#define TXQ1_MTX_Q_SRC_LIMIT_MSK 0x000000ff
++#define TXQ1_MTX_Q_SRC_LIMIT_I_MSK 0xffffff00
++#define TXQ1_MTX_Q_SRC_LIMIT_SFT 0
++#define TXQ1_MTX_Q_SRC_LIMIT_HI 7
++#define TXQ1_MTX_Q_SRC_LIMIT_SZ 8
++#define TXQ1_MTX_Q_LRC_LIMIT_MSK 0x0000ff00
++#define TXQ1_MTX_Q_LRC_LIMIT_I_MSK 0xffff00ff
++#define TXQ1_MTX_Q_LRC_LIMIT_SFT 8
++#define TXQ1_MTX_Q_LRC_LIMIT_HI 15
++#define TXQ1_MTX_Q_LRC_LIMIT_SZ 8
++#define TXQ1_MTX_Q_ID_MAP_L_MSK 0xffffffff
++#define TXQ1_MTX_Q_ID_MAP_L_I_MSK 0x00000000
++#define TXQ1_MTX_Q_ID_MAP_L_SFT 0
++#define TXQ1_MTX_Q_ID_MAP_L_HI 31
++#define TXQ1_MTX_Q_ID_MAP_L_SZ 32
++#define TXQ1_MTX_Q_TXOP_CH_THD_MSK 0x0000ffff
++#define TXQ1_MTX_Q_TXOP_CH_THD_I_MSK 0xffff0000
++#define TXQ1_MTX_Q_TXOP_CH_THD_SFT 0
++#define TXQ1_MTX_Q_TXOP_CH_THD_HI 15
++#define TXQ1_MTX_Q_TXOP_CH_THD_SZ 16
++#define TXQ1_MTX_Q_TXOP_OV_THD_MSK 0x0000ffff
++#define TXQ1_MTX_Q_TXOP_OV_THD_I_MSK 0xffff0000
++#define TXQ1_MTX_Q_TXOP_OV_THD_SFT 0
++#define TXQ1_MTX_Q_TXOP_OV_THD_HI 15
++#define TXQ1_MTX_Q_TXOP_OV_THD_SZ 16
++#define TXQ2_MTX_Q_PRE_LD_MSK 0x00000002
++#define TXQ2_MTX_Q_PRE_LD_I_MSK 0xfffffffd
++#define TXQ2_MTX_Q_PRE_LD_SFT 1
++#define TXQ2_MTX_Q_PRE_LD_HI 1
++#define TXQ2_MTX_Q_PRE_LD_SZ 1
++#define TXQ2_MTX_Q_BKF_CNT_FIXED_MSK 0x00000004
++#define TXQ2_MTX_Q_BKF_CNT_FIXED_I_MSK 0xfffffffb
++#define TXQ2_MTX_Q_BKF_CNT_FIXED_SFT 2
++#define TXQ2_MTX_Q_BKF_CNT_FIXED_HI 2
++#define TXQ2_MTX_Q_BKF_CNT_FIXED_SZ 1
++#define TXQ2_MTX_Q_TXOP_SUB_FRM_TIME_MSK 0x00000008
++#define TXQ2_MTX_Q_TXOP_SUB_FRM_TIME_I_MSK 0xfffffff7
++#define TXQ2_MTX_Q_TXOP_SUB_FRM_TIME_SFT 3
++#define TXQ2_MTX_Q_TXOP_SUB_FRM_TIME_HI 3
++#define TXQ2_MTX_Q_TXOP_SUB_FRM_TIME_SZ 1
++#define TXQ2_MTX_Q_MB_NO_RLS_MSK 0x00000010
++#define TXQ2_MTX_Q_MB_NO_RLS_I_MSK 0xffffffef
++#define TXQ2_MTX_Q_MB_NO_RLS_SFT 4
++#define TXQ2_MTX_Q_MB_NO_RLS_HI 4
++#define TXQ2_MTX_Q_MB_NO_RLS_SZ 1
++#define TXQ2_MTX_Q_TXOP_FRC_BUR_MSK 0x00000020
++#define TXQ2_MTX_Q_TXOP_FRC_BUR_I_MSK 0xffffffdf
++#define TXQ2_MTX_Q_TXOP_FRC_BUR_SFT 5
++#define TXQ2_MTX_Q_TXOP_FRC_BUR_HI 5
++#define TXQ2_MTX_Q_TXOP_FRC_BUR_SZ 1
++#define TXQ2_MTX_Q_RND_MODE_MSK 0x000000c0
++#define TXQ2_MTX_Q_RND_MODE_I_MSK 0xffffff3f
++#define TXQ2_MTX_Q_RND_MODE_SFT 6
++#define TXQ2_MTX_Q_RND_MODE_HI 7
++#define TXQ2_MTX_Q_RND_MODE_SZ 2
++#define TXQ2_MTX_Q_AIFSN_MSK 0x0000000f
++#define TXQ2_MTX_Q_AIFSN_I_MSK 0xfffffff0
++#define TXQ2_MTX_Q_AIFSN_SFT 0
++#define TXQ2_MTX_Q_AIFSN_HI 3
++#define TXQ2_MTX_Q_AIFSN_SZ 4
++#define TXQ2_MTX_Q_ECWMIN_MSK 0x00000f00
++#define TXQ2_MTX_Q_ECWMIN_I_MSK 0xfffff0ff
++#define TXQ2_MTX_Q_ECWMIN_SFT 8
++#define TXQ2_MTX_Q_ECWMIN_HI 11
++#define TXQ2_MTX_Q_ECWMIN_SZ 4
++#define TXQ2_MTX_Q_ECWMAX_MSK 0x0000f000
++#define TXQ2_MTX_Q_ECWMAX_I_MSK 0xffff0fff
++#define TXQ2_MTX_Q_ECWMAX_SFT 12
++#define TXQ2_MTX_Q_ECWMAX_HI 15
++#define TXQ2_MTX_Q_ECWMAX_SZ 4
++#define TXQ2_MTX_Q_TXOP_LIMIT_MSK 0xffff0000
++#define TXQ2_MTX_Q_TXOP_LIMIT_I_MSK 0x0000ffff
++#define TXQ2_MTX_Q_TXOP_LIMIT_SFT 16
++#define TXQ2_MTX_Q_TXOP_LIMIT_HI 31
++#define TXQ2_MTX_Q_TXOP_LIMIT_SZ 16
++#define TXQ2_MTX_Q_BKF_CNT_MSK 0x0000ffff
++#define TXQ2_MTX_Q_BKF_CNT_I_MSK 0xffff0000
++#define TXQ2_MTX_Q_BKF_CNT_SFT 0
++#define TXQ2_MTX_Q_BKF_CNT_HI 15
++#define TXQ2_MTX_Q_BKF_CNT_SZ 16
++#define TXQ2_MTX_Q_SRC_LIMIT_MSK 0x000000ff
++#define TXQ2_MTX_Q_SRC_LIMIT_I_MSK 0xffffff00
++#define TXQ2_MTX_Q_SRC_LIMIT_SFT 0
++#define TXQ2_MTX_Q_SRC_LIMIT_HI 7
++#define TXQ2_MTX_Q_SRC_LIMIT_SZ 8
++#define TXQ2_MTX_Q_LRC_LIMIT_MSK 0x0000ff00
++#define TXQ2_MTX_Q_LRC_LIMIT_I_MSK 0xffff00ff
++#define TXQ2_MTX_Q_LRC_LIMIT_SFT 8
++#define TXQ2_MTX_Q_LRC_LIMIT_HI 15
++#define TXQ2_MTX_Q_LRC_LIMIT_SZ 8
++#define TXQ2_MTX_Q_ID_MAP_L_MSK 0xffffffff
++#define TXQ2_MTX_Q_ID_MAP_L_I_MSK 0x00000000
++#define TXQ2_MTX_Q_ID_MAP_L_SFT 0
++#define TXQ2_MTX_Q_ID_MAP_L_HI 31
++#define TXQ2_MTX_Q_ID_MAP_L_SZ 32
++#define TXQ2_MTX_Q_TXOP_CH_THD_MSK 0x0000ffff
++#define TXQ2_MTX_Q_TXOP_CH_THD_I_MSK 0xffff0000
++#define TXQ2_MTX_Q_TXOP_CH_THD_SFT 0
++#define TXQ2_MTX_Q_TXOP_CH_THD_HI 15
++#define TXQ2_MTX_Q_TXOP_CH_THD_SZ 16
++#define TXQ2_MTX_Q_TXOP_OV_THD_MSK 0x0000ffff
++#define TXQ2_MTX_Q_TXOP_OV_THD_I_MSK 0xffff0000
++#define TXQ2_MTX_Q_TXOP_OV_THD_SFT 0
++#define TXQ2_MTX_Q_TXOP_OV_THD_HI 15
++#define TXQ2_MTX_Q_TXOP_OV_THD_SZ 16
++#define TXQ3_MTX_Q_PRE_LD_MSK 0x00000002
++#define TXQ3_MTX_Q_PRE_LD_I_MSK 0xfffffffd
++#define TXQ3_MTX_Q_PRE_LD_SFT 1
++#define TXQ3_MTX_Q_PRE_LD_HI 1
++#define TXQ3_MTX_Q_PRE_LD_SZ 1
++#define TXQ3_MTX_Q_BKF_CNT_FIXED_MSK 0x00000004
++#define TXQ3_MTX_Q_BKF_CNT_FIXED_I_MSK 0xfffffffb
++#define TXQ3_MTX_Q_BKF_CNT_FIXED_SFT 2
++#define TXQ3_MTX_Q_BKF_CNT_FIXED_HI 2
++#define TXQ3_MTX_Q_BKF_CNT_FIXED_SZ 1
++#define TXQ3_MTX_Q_TXOP_SUB_FRM_TIME_MSK 0x00000008
++#define TXQ3_MTX_Q_TXOP_SUB_FRM_TIME_I_MSK 0xfffffff7
++#define TXQ3_MTX_Q_TXOP_SUB_FRM_TIME_SFT 3
++#define TXQ3_MTX_Q_TXOP_SUB_FRM_TIME_HI 3
++#define TXQ3_MTX_Q_TXOP_SUB_FRM_TIME_SZ 1
++#define TXQ3_MTX_Q_MB_NO_RLS_MSK 0x00000010
++#define TXQ3_MTX_Q_MB_NO_RLS_I_MSK 0xffffffef
++#define TXQ3_MTX_Q_MB_NO_RLS_SFT 4
++#define TXQ3_MTX_Q_MB_NO_RLS_HI 4
++#define TXQ3_MTX_Q_MB_NO_RLS_SZ 1
++#define TXQ3_MTX_Q_TXOP_FRC_BUR_MSK 0x00000020
++#define TXQ3_MTX_Q_TXOP_FRC_BUR_I_MSK 0xffffffdf
++#define TXQ3_MTX_Q_TXOP_FRC_BUR_SFT 5
++#define TXQ3_MTX_Q_TXOP_FRC_BUR_HI 5
++#define TXQ3_MTX_Q_TXOP_FRC_BUR_SZ 1
++#define TXQ3_MTX_Q_RND_MODE_MSK 0x000000c0
++#define TXQ3_MTX_Q_RND_MODE_I_MSK 0xffffff3f
++#define TXQ3_MTX_Q_RND_MODE_SFT 6
++#define TXQ3_MTX_Q_RND_MODE_HI 7
++#define TXQ3_MTX_Q_RND_MODE_SZ 2
++#define TXQ3_MTX_Q_AIFSN_MSK 0x0000000f
++#define TXQ3_MTX_Q_AIFSN_I_MSK 0xfffffff0
++#define TXQ3_MTX_Q_AIFSN_SFT 0
++#define TXQ3_MTX_Q_AIFSN_HI 3
++#define TXQ3_MTX_Q_AIFSN_SZ 4
++#define TXQ3_MTX_Q_ECWMIN_MSK 0x00000f00
++#define TXQ3_MTX_Q_ECWMIN_I_MSK 0xfffff0ff
++#define TXQ3_MTX_Q_ECWMIN_SFT 8
++#define TXQ3_MTX_Q_ECWMIN_HI 11
++#define TXQ3_MTX_Q_ECWMIN_SZ 4
++#define TXQ3_MTX_Q_ECWMAX_MSK 0x0000f000
++#define TXQ3_MTX_Q_ECWMAX_I_MSK 0xffff0fff
++#define TXQ3_MTX_Q_ECWMAX_SFT 12
++#define TXQ3_MTX_Q_ECWMAX_HI 15
++#define TXQ3_MTX_Q_ECWMAX_SZ 4
++#define TXQ3_MTX_Q_TXOP_LIMIT_MSK 0xffff0000
++#define TXQ3_MTX_Q_TXOP_LIMIT_I_MSK 0x0000ffff
++#define TXQ3_MTX_Q_TXOP_LIMIT_SFT 16
++#define TXQ3_MTX_Q_TXOP_LIMIT_HI 31
++#define TXQ3_MTX_Q_TXOP_LIMIT_SZ 16
++#define TXQ3_MTX_Q_BKF_CNT_MSK 0x0000ffff
++#define TXQ3_MTX_Q_BKF_CNT_I_MSK 0xffff0000
++#define TXQ3_MTX_Q_BKF_CNT_SFT 0
++#define TXQ3_MTX_Q_BKF_CNT_HI 15
++#define TXQ3_MTX_Q_BKF_CNT_SZ 16
++#define TXQ3_MTX_Q_SRC_LIMIT_MSK 0x000000ff
++#define TXQ3_MTX_Q_SRC_LIMIT_I_MSK 0xffffff00
++#define TXQ3_MTX_Q_SRC_LIMIT_SFT 0
++#define TXQ3_MTX_Q_SRC_LIMIT_HI 7
++#define TXQ3_MTX_Q_SRC_LIMIT_SZ 8
++#define TXQ3_MTX_Q_LRC_LIMIT_MSK 0x0000ff00
++#define TXQ3_MTX_Q_LRC_LIMIT_I_MSK 0xffff00ff
++#define TXQ3_MTX_Q_LRC_LIMIT_SFT 8
++#define TXQ3_MTX_Q_LRC_LIMIT_HI 15
++#define TXQ3_MTX_Q_LRC_LIMIT_SZ 8
++#define TXQ3_MTX_Q_ID_MAP_L_MSK 0xffffffff
++#define TXQ3_MTX_Q_ID_MAP_L_I_MSK 0x00000000
++#define TXQ3_MTX_Q_ID_MAP_L_SFT 0
++#define TXQ3_MTX_Q_ID_MAP_L_HI 31
++#define TXQ3_MTX_Q_ID_MAP_L_SZ 32
++#define TXQ3_MTX_Q_TXOP_CH_THD_MSK 0x0000ffff
++#define TXQ3_MTX_Q_TXOP_CH_THD_I_MSK 0xffff0000
++#define TXQ3_MTX_Q_TXOP_CH_THD_SFT 0
++#define TXQ3_MTX_Q_TXOP_CH_THD_HI 15
++#define TXQ3_MTX_Q_TXOP_CH_THD_SZ 16
++#define TXQ3_MTX_Q_TXOP_OV_THD_MSK 0x0000ffff
++#define TXQ3_MTX_Q_TXOP_OV_THD_I_MSK 0xffff0000
++#define TXQ3_MTX_Q_TXOP_OV_THD_SFT 0
++#define TXQ3_MTX_Q_TXOP_OV_THD_HI 15
++#define TXQ3_MTX_Q_TXOP_OV_THD_SZ 16
++#define TXQ4_MTX_Q_PRE_LD_MSK 0x00000002
++#define TXQ4_MTX_Q_PRE_LD_I_MSK 0xfffffffd
++#define TXQ4_MTX_Q_PRE_LD_SFT 1
++#define TXQ4_MTX_Q_PRE_LD_HI 1
++#define TXQ4_MTX_Q_PRE_LD_SZ 1
++#define TXQ4_MTX_Q_BKF_CNT_FIXED_MSK 0x00000004
++#define TXQ4_MTX_Q_BKF_CNT_FIXED_I_MSK 0xfffffffb
++#define TXQ4_MTX_Q_BKF_CNT_FIXED_SFT 2
++#define TXQ4_MTX_Q_BKF_CNT_FIXED_HI 2
++#define TXQ4_MTX_Q_BKF_CNT_FIXED_SZ 1
++#define TXQ4_MTX_Q_TXOP_SUB_FRM_TIME_MSK 0x00000008
++#define TXQ4_MTX_Q_TXOP_SUB_FRM_TIME_I_MSK 0xfffffff7
++#define TXQ4_MTX_Q_TXOP_SUB_FRM_TIME_SFT 3
++#define TXQ4_MTX_Q_TXOP_SUB_FRM_TIME_HI 3
++#define TXQ4_MTX_Q_TXOP_SUB_FRM_TIME_SZ 1
++#define TXQ4_MTX_Q_MB_NO_RLS_MSK 0x00000010
++#define TXQ4_MTX_Q_MB_NO_RLS_I_MSK 0xffffffef
++#define TXQ4_MTX_Q_MB_NO_RLS_SFT 4
++#define TXQ4_MTX_Q_MB_NO_RLS_HI 4
++#define TXQ4_MTX_Q_MB_NO_RLS_SZ 1
++#define TXQ4_MTX_Q_TXOP_FRC_BUR_MSK 0x00000020
++#define TXQ4_MTX_Q_TXOP_FRC_BUR_I_MSK 0xffffffdf
++#define TXQ4_MTX_Q_TXOP_FRC_BUR_SFT 5
++#define TXQ4_MTX_Q_TXOP_FRC_BUR_HI 5
++#define TXQ4_MTX_Q_TXOP_FRC_BUR_SZ 1
++#define TXQ4_MTX_Q_RND_MODE_MSK 0x000000c0
++#define TXQ4_MTX_Q_RND_MODE_I_MSK 0xffffff3f
++#define TXQ4_MTX_Q_RND_MODE_SFT 6
++#define TXQ4_MTX_Q_RND_MODE_HI 7
++#define TXQ4_MTX_Q_RND_MODE_SZ 2
++#define TXQ4_MTX_Q_AIFSN_MSK 0x0000000f
++#define TXQ4_MTX_Q_AIFSN_I_MSK 0xfffffff0
++#define TXQ4_MTX_Q_AIFSN_SFT 0
++#define TXQ4_MTX_Q_AIFSN_HI 3
++#define TXQ4_MTX_Q_AIFSN_SZ 4
++#define TXQ4_MTX_Q_ECWMIN_MSK 0x00000f00
++#define TXQ4_MTX_Q_ECWMIN_I_MSK 0xfffff0ff
++#define TXQ4_MTX_Q_ECWMIN_SFT 8
++#define TXQ4_MTX_Q_ECWMIN_HI 11
++#define TXQ4_MTX_Q_ECWMIN_SZ 4
++#define TXQ4_MTX_Q_ECWMAX_MSK 0x0000f000
++#define TXQ4_MTX_Q_ECWMAX_I_MSK 0xffff0fff
++#define TXQ4_MTX_Q_ECWMAX_SFT 12
++#define TXQ4_MTX_Q_ECWMAX_HI 15
++#define TXQ4_MTX_Q_ECWMAX_SZ 4
++#define TXQ4_MTX_Q_TXOP_LIMIT_MSK 0xffff0000
++#define TXQ4_MTX_Q_TXOP_LIMIT_I_MSK 0x0000ffff
++#define TXQ4_MTX_Q_TXOP_LIMIT_SFT 16
++#define TXQ4_MTX_Q_TXOP_LIMIT_HI 31
++#define TXQ4_MTX_Q_TXOP_LIMIT_SZ 16
++#define TXQ4_MTX_Q_BKF_CNT_MSK 0x0000ffff
++#define TXQ4_MTX_Q_BKF_CNT_I_MSK 0xffff0000
++#define TXQ4_MTX_Q_BKF_CNT_SFT 0
++#define TXQ4_MTX_Q_BKF_CNT_HI 15
++#define TXQ4_MTX_Q_BKF_CNT_SZ 16
++#define TXQ4_MTX_Q_SRC_LIMIT_MSK 0x000000ff
++#define TXQ4_MTX_Q_SRC_LIMIT_I_MSK 0xffffff00
++#define TXQ4_MTX_Q_SRC_LIMIT_SFT 0
++#define TXQ4_MTX_Q_SRC_LIMIT_HI 7
++#define TXQ4_MTX_Q_SRC_LIMIT_SZ 8
++#define TXQ4_MTX_Q_LRC_LIMIT_MSK 0x0000ff00
++#define TXQ4_MTX_Q_LRC_LIMIT_I_MSK 0xffff00ff
++#define TXQ4_MTX_Q_LRC_LIMIT_SFT 8
++#define TXQ4_MTX_Q_LRC_LIMIT_HI 15
++#define TXQ4_MTX_Q_LRC_LIMIT_SZ 8
++#define TXQ4_MTX_Q_ID_MAP_L_MSK 0xffffffff
++#define TXQ4_MTX_Q_ID_MAP_L_I_MSK 0x00000000
++#define TXQ4_MTX_Q_ID_MAP_L_SFT 0
++#define TXQ4_MTX_Q_ID_MAP_L_HI 31
++#define TXQ4_MTX_Q_ID_MAP_L_SZ 32
++#define TXQ4_MTX_Q_TXOP_CH_THD_MSK 0x0000ffff
++#define TXQ4_MTX_Q_TXOP_CH_THD_I_MSK 0xffff0000
++#define TXQ4_MTX_Q_TXOP_CH_THD_SFT 0
++#define TXQ4_MTX_Q_TXOP_CH_THD_HI 15
++#define TXQ4_MTX_Q_TXOP_CH_THD_SZ 16
++#define TXQ4_MTX_Q_TXOP_OV_THD_MSK 0x0000ffff
++#define TXQ4_MTX_Q_TXOP_OV_THD_I_MSK 0xffff0000
++#define TXQ4_MTX_Q_TXOP_OV_THD_SFT 0
++#define TXQ4_MTX_Q_TXOP_OV_THD_HI 15
++#define TXQ4_MTX_Q_TXOP_OV_THD_SZ 16
++#define VALID0_MSK 0x00000001
++#define VALID0_I_MSK 0xfffffffe
++#define VALID0_SFT 0
++#define VALID0_HI 0
++#define VALID0_SZ 1
++#define PEER_QOS_EN0_MSK 0x00000002
++#define PEER_QOS_EN0_I_MSK 0xfffffffd
++#define PEER_QOS_EN0_SFT 1
++#define PEER_QOS_EN0_HI 1
++#define PEER_QOS_EN0_SZ 1
++#define PEER_OP_MODE0_MSK 0x0000000c
++#define PEER_OP_MODE0_I_MSK 0xfffffff3
++#define PEER_OP_MODE0_SFT 2
++#define PEER_OP_MODE0_HI 3
++#define PEER_OP_MODE0_SZ 2
++#define PEER_HT_MODE0_MSK 0x00000030
++#define PEER_HT_MODE0_I_MSK 0xffffffcf
++#define PEER_HT_MODE0_SFT 4
++#define PEER_HT_MODE0_HI 5
++#define PEER_HT_MODE0_SZ 2
++#define PEER_MAC0_31_0_MSK 0xffffffff
++#define PEER_MAC0_31_0_I_MSK 0x00000000
++#define PEER_MAC0_31_0_SFT 0
++#define PEER_MAC0_31_0_HI 31
++#define PEER_MAC0_31_0_SZ 32
++#define PEER_MAC0_47_32_MSK 0x0000ffff
++#define PEER_MAC0_47_32_I_MSK 0xffff0000
++#define PEER_MAC0_47_32_SFT 0
++#define PEER_MAC0_47_32_HI 15
++#define PEER_MAC0_47_32_SZ 16
++#define TX_ACK_POLICY_0_0_MSK 0x00000003
++#define TX_ACK_POLICY_0_0_I_MSK 0xfffffffc
++#define TX_ACK_POLICY_0_0_SFT 0
++#define TX_ACK_POLICY_0_0_HI 1
++#define TX_ACK_POLICY_0_0_SZ 2
++#define TX_SEQ_CTRL_0_0_MSK 0x00000fff
++#define TX_SEQ_CTRL_0_0_I_MSK 0xfffff000
++#define TX_SEQ_CTRL_0_0_SFT 0
++#define TX_SEQ_CTRL_0_0_HI 11
++#define TX_SEQ_CTRL_0_0_SZ 12
++#define TX_ACK_POLICY_0_1_MSK 0x00000003
++#define TX_ACK_POLICY_0_1_I_MSK 0xfffffffc
++#define TX_ACK_POLICY_0_1_SFT 0
++#define TX_ACK_POLICY_0_1_HI 1
++#define TX_ACK_POLICY_0_1_SZ 2
++#define TX_SEQ_CTRL_0_1_MSK 0x00000fff
++#define TX_SEQ_CTRL_0_1_I_MSK 0xfffff000
++#define TX_SEQ_CTRL_0_1_SFT 0
++#define TX_SEQ_CTRL_0_1_HI 11
++#define TX_SEQ_CTRL_0_1_SZ 12
++#define TX_ACK_POLICY_0_2_MSK 0x00000003
++#define TX_ACK_POLICY_0_2_I_MSK 0xfffffffc
++#define TX_ACK_POLICY_0_2_SFT 0
++#define TX_ACK_POLICY_0_2_HI 1
++#define TX_ACK_POLICY_0_2_SZ 2
++#define TX_SEQ_CTRL_0_2_MSK 0x00000fff
++#define TX_SEQ_CTRL_0_2_I_MSK 0xfffff000
++#define TX_SEQ_CTRL_0_2_SFT 0
++#define TX_SEQ_CTRL_0_2_HI 11
++#define TX_SEQ_CTRL_0_2_SZ 12
++#define TX_ACK_POLICY_0_3_MSK 0x00000003
++#define TX_ACK_POLICY_0_3_I_MSK 0xfffffffc
++#define TX_ACK_POLICY_0_3_SFT 0
++#define TX_ACK_POLICY_0_3_HI 1
++#define TX_ACK_POLICY_0_3_SZ 2
++#define TX_SEQ_CTRL_0_3_MSK 0x00000fff
++#define TX_SEQ_CTRL_0_3_I_MSK 0xfffff000
++#define TX_SEQ_CTRL_0_3_SFT 0
++#define TX_SEQ_CTRL_0_3_HI 11
++#define TX_SEQ_CTRL_0_3_SZ 12
++#define TX_ACK_POLICY_0_4_MSK 0x00000003
++#define TX_ACK_POLICY_0_4_I_MSK 0xfffffffc
++#define TX_ACK_POLICY_0_4_SFT 0
++#define TX_ACK_POLICY_0_4_HI 1
++#define TX_ACK_POLICY_0_4_SZ 2
++#define TX_SEQ_CTRL_0_4_MSK 0x00000fff
++#define TX_SEQ_CTRL_0_4_I_MSK 0xfffff000
++#define TX_SEQ_CTRL_0_4_SFT 0
++#define TX_SEQ_CTRL_0_4_HI 11
++#define TX_SEQ_CTRL_0_4_SZ 12
++#define TX_ACK_POLICY_0_5_MSK 0x00000003
++#define TX_ACK_POLICY_0_5_I_MSK 0xfffffffc
++#define TX_ACK_POLICY_0_5_SFT 0
++#define TX_ACK_POLICY_0_5_HI 1
++#define TX_ACK_POLICY_0_5_SZ 2
++#define TX_SEQ_CTRL_0_5_MSK 0x00000fff
++#define TX_SEQ_CTRL_0_5_I_MSK 0xfffff000
++#define TX_SEQ_CTRL_0_5_SFT 0
++#define TX_SEQ_CTRL_0_5_HI 11
++#define TX_SEQ_CTRL_0_5_SZ 12
++#define TX_ACK_POLICY_0_6_MSK 0x00000003
++#define TX_ACK_POLICY_0_6_I_MSK 0xfffffffc
++#define TX_ACK_POLICY_0_6_SFT 0
++#define TX_ACK_POLICY_0_6_HI 1
++#define TX_ACK_POLICY_0_6_SZ 2
++#define TX_SEQ_CTRL_0_6_MSK 0x00000fff
++#define TX_SEQ_CTRL_0_6_I_MSK 0xfffff000
++#define TX_SEQ_CTRL_0_6_SFT 0
++#define TX_SEQ_CTRL_0_6_HI 11
++#define TX_SEQ_CTRL_0_6_SZ 12
++#define TX_ACK_POLICY_0_7_MSK 0x00000003
++#define TX_ACK_POLICY_0_7_I_MSK 0xfffffffc
++#define TX_ACK_POLICY_0_7_SFT 0
++#define TX_ACK_POLICY_0_7_HI 1
++#define TX_ACK_POLICY_0_7_SZ 2
++#define TX_SEQ_CTRL_0_7_MSK 0x00000fff
++#define TX_SEQ_CTRL_0_7_I_MSK 0xfffff000
++#define TX_SEQ_CTRL_0_7_SFT 0
++#define TX_SEQ_CTRL_0_7_HI 11
++#define TX_SEQ_CTRL_0_7_SZ 12
++#define VALID1_MSK 0x00000001
++#define VALID1_I_MSK 0xfffffffe
++#define VALID1_SFT 0
++#define VALID1_HI 0
++#define VALID1_SZ 1
++#define PEER_QOS_EN1_MSK 0x00000002
++#define PEER_QOS_EN1_I_MSK 0xfffffffd
++#define PEER_QOS_EN1_SFT 1
++#define PEER_QOS_EN1_HI 1
++#define PEER_QOS_EN1_SZ 1
++#define PEER_OP_MODE1_MSK 0x0000000c
++#define PEER_OP_MODE1_I_MSK 0xfffffff3
++#define PEER_OP_MODE1_SFT 2
++#define PEER_OP_MODE1_HI 3
++#define PEER_OP_MODE1_SZ 2
++#define PEER_HT_MODE1_MSK 0x00000030
++#define PEER_HT_MODE1_I_MSK 0xffffffcf
++#define PEER_HT_MODE1_SFT 4
++#define PEER_HT_MODE1_HI 5
++#define PEER_HT_MODE1_SZ 2
++#define PEER_MAC1_31_0_MSK 0xffffffff
++#define PEER_MAC1_31_0_I_MSK 0x00000000
++#define PEER_MAC1_31_0_SFT 0
++#define PEER_MAC1_31_0_HI 31
++#define PEER_MAC1_31_0_SZ 32
++#define PEER_MAC1_47_32_MSK 0x0000ffff
++#define PEER_MAC1_47_32_I_MSK 0xffff0000
++#define PEER_MAC1_47_32_SFT 0
++#define PEER_MAC1_47_32_HI 15
++#define PEER_MAC1_47_32_SZ 16
++#define TX_ACK_POLICY_1_0_MSK 0x00000003
++#define TX_ACK_POLICY_1_0_I_MSK 0xfffffffc
++#define TX_ACK_POLICY_1_0_SFT 0
++#define TX_ACK_POLICY_1_0_HI 1
++#define TX_ACK_POLICY_1_0_SZ 2
++#define TX_SEQ_CTRL_1_0_MSK 0x00000fff
++#define TX_SEQ_CTRL_1_0_I_MSK 0xfffff000
++#define TX_SEQ_CTRL_1_0_SFT 0
++#define TX_SEQ_CTRL_1_0_HI 11
++#define TX_SEQ_CTRL_1_0_SZ 12
++#define TX_ACK_POLICY_1_1_MSK 0x00000003
++#define TX_ACK_POLICY_1_1_I_MSK 0xfffffffc
++#define TX_ACK_POLICY_1_1_SFT 0
++#define TX_ACK_POLICY_1_1_HI 1
++#define TX_ACK_POLICY_1_1_SZ 2
++#define TX_SEQ_CTRL_1_1_MSK 0x00000fff
++#define TX_SEQ_CTRL_1_1_I_MSK 0xfffff000
++#define TX_SEQ_CTRL_1_1_SFT 0
++#define TX_SEQ_CTRL_1_1_HI 11
++#define TX_SEQ_CTRL_1_1_SZ 12
++#define TX_ACK_POLICY_1_2_MSK 0x00000003
++#define TX_ACK_POLICY_1_2_I_MSK 0xfffffffc
++#define TX_ACK_POLICY_1_2_SFT 0
++#define TX_ACK_POLICY_1_2_HI 1
++#define TX_ACK_POLICY_1_2_SZ 2
++#define TX_SEQ_CTRL_1_2_MSK 0x00000fff
++#define TX_SEQ_CTRL_1_2_I_MSK 0xfffff000
++#define TX_SEQ_CTRL_1_2_SFT 0
++#define TX_SEQ_CTRL_1_2_HI 11
++#define TX_SEQ_CTRL_1_2_SZ 12
++#define TX_ACK_POLICY_1_3_MSK 0x00000003
++#define TX_ACK_POLICY_1_3_I_MSK 0xfffffffc
++#define TX_ACK_POLICY_1_3_SFT 0
++#define TX_ACK_POLICY_1_3_HI 1
++#define TX_ACK_POLICY_1_3_SZ 2
++#define TX_SEQ_CTRL_1_3_MSK 0x00000fff
++#define TX_SEQ_CTRL_1_3_I_MSK 0xfffff000
++#define TX_SEQ_CTRL_1_3_SFT 0
++#define TX_SEQ_CTRL_1_3_HI 11
++#define TX_SEQ_CTRL_1_3_SZ 12
++#define TX_ACK_POLICY_1_4_MSK 0x00000003
++#define TX_ACK_POLICY_1_4_I_MSK 0xfffffffc
++#define TX_ACK_POLICY_1_4_SFT 0
++#define TX_ACK_POLICY_1_4_HI 1
++#define TX_ACK_POLICY_1_4_SZ 2
++#define TX_SEQ_CTRL_1_4_MSK 0x00000fff
++#define TX_SEQ_CTRL_1_4_I_MSK 0xfffff000
++#define TX_SEQ_CTRL_1_4_SFT 0
++#define TX_SEQ_CTRL_1_4_HI 11
++#define TX_SEQ_CTRL_1_4_SZ 12
++#define TX_ACK_POLICY_1_5_MSK 0x00000003
++#define TX_ACK_POLICY_1_5_I_MSK 0xfffffffc
++#define TX_ACK_POLICY_1_5_SFT 0
++#define TX_ACK_POLICY_1_5_HI 1
++#define TX_ACK_POLICY_1_5_SZ 2
++#define TX_SEQ_CTRL_1_5_MSK 0x00000fff
++#define TX_SEQ_CTRL_1_5_I_MSK 0xfffff000
++#define TX_SEQ_CTRL_1_5_SFT 0
++#define TX_SEQ_CTRL_1_5_HI 11
++#define TX_SEQ_CTRL_1_5_SZ 12
++#define TX_ACK_POLICY_1_6_MSK 0x00000003
++#define TX_ACK_POLICY_1_6_I_MSK 0xfffffffc
++#define TX_ACK_POLICY_1_6_SFT 0
++#define TX_ACK_POLICY_1_6_HI 1
++#define TX_ACK_POLICY_1_6_SZ 2
++#define TX_SEQ_CTRL_1_6_MSK 0x00000fff
++#define TX_SEQ_CTRL_1_6_I_MSK 0xfffff000
++#define TX_SEQ_CTRL_1_6_SFT 0
++#define TX_SEQ_CTRL_1_6_HI 11
++#define TX_SEQ_CTRL_1_6_SZ 12
++#define TX_ACK_POLICY_1_7_MSK 0x00000003
++#define TX_ACK_POLICY_1_7_I_MSK 0xfffffffc
++#define TX_ACK_POLICY_1_7_SFT 0
++#define TX_ACK_POLICY_1_7_HI 1
++#define TX_ACK_POLICY_1_7_SZ 2
++#define TX_SEQ_CTRL_1_7_MSK 0x00000fff
++#define TX_SEQ_CTRL_1_7_I_MSK 0xfffff000
++#define TX_SEQ_CTRL_1_7_SFT 0
++#define TX_SEQ_CTRL_1_7_HI 11
++#define TX_SEQ_CTRL_1_7_SZ 12
++#define INFO0_MSK 0xffffffff
++#define INFO0_I_MSK 0x00000000
++#define INFO0_SFT 0
++#define INFO0_HI 31
++#define INFO0_SZ 32
++#define INFO1_MSK 0xffffffff
++#define INFO1_I_MSK 0x00000000
++#define INFO1_SFT 0
++#define INFO1_HI 31
++#define INFO1_SZ 32
++#define INFO2_MSK 0xffffffff
++#define INFO2_I_MSK 0x00000000
++#define INFO2_SFT 0
++#define INFO2_HI 31
++#define INFO2_SZ 32
++#define INFO3_MSK 0xffffffff
++#define INFO3_I_MSK 0x00000000
++#define INFO3_SFT 0
++#define INFO3_HI 31
++#define INFO3_SZ 32
++#define INFO4_MSK 0xffffffff
++#define INFO4_I_MSK 0x00000000
++#define INFO4_SFT 0
++#define INFO4_HI 31
++#define INFO4_SZ 32
++#define INFO5_MSK 0xffffffff
++#define INFO5_I_MSK 0x00000000
++#define INFO5_SFT 0
++#define INFO5_HI 31
++#define INFO5_SZ 32
++#define INFO6_MSK 0xffffffff
++#define INFO6_I_MSK 0x00000000
++#define INFO6_SFT 0
++#define INFO6_HI 31
++#define INFO6_SZ 32
++#define INFO7_MSK 0xffffffff
++#define INFO7_I_MSK 0x00000000
++#define INFO7_SFT 0
++#define INFO7_HI 31
++#define INFO7_SZ 32
++#define INFO8_MSK 0xffffffff
++#define INFO8_I_MSK 0x00000000
++#define INFO8_SFT 0
++#define INFO8_HI 31
++#define INFO8_SZ 32
++#define INFO9_MSK 0xffffffff
++#define INFO9_I_MSK 0x00000000
++#define INFO9_SFT 0
++#define INFO9_HI 31
++#define INFO9_SZ 32
++#define INFO10_MSK 0xffffffff
++#define INFO10_I_MSK 0x00000000
++#define INFO10_SFT 0
++#define INFO10_HI 31
++#define INFO10_SZ 32
++#define INFO11_MSK 0xffffffff
++#define INFO11_I_MSK 0x00000000
++#define INFO11_SFT 0
++#define INFO11_HI 31
++#define INFO11_SZ 32
++#define INFO12_MSK 0xffffffff
++#define INFO12_I_MSK 0x00000000
++#define INFO12_SFT 0
++#define INFO12_HI 31
++#define INFO12_SZ 32
++#define INFO13_MSK 0xffffffff
++#define INFO13_I_MSK 0x00000000
++#define INFO13_SFT 0
++#define INFO13_HI 31
++#define INFO13_SZ 32
++#define INFO14_MSK 0xffffffff
++#define INFO14_I_MSK 0x00000000
++#define INFO14_SFT 0
++#define INFO14_HI 31
++#define INFO14_SZ 32
++#define INFO15_MSK 0xffffffff
++#define INFO15_I_MSK 0x00000000
++#define INFO15_SFT 0
++#define INFO15_HI 31
++#define INFO15_SZ 32
++#define INFO16_MSK 0xffffffff
++#define INFO16_I_MSK 0x00000000
++#define INFO16_SFT 0
++#define INFO16_HI 31
++#define INFO16_SZ 32
++#define INFO17_MSK 0xffffffff
++#define INFO17_I_MSK 0x00000000
++#define INFO17_SFT 0
++#define INFO17_HI 31
++#define INFO17_SZ 32
++#define INFO18_MSK 0xffffffff
++#define INFO18_I_MSK 0x00000000
++#define INFO18_SFT 0
++#define INFO18_HI 31
++#define INFO18_SZ 32
++#define INFO19_MSK 0xffffffff
++#define INFO19_I_MSK 0x00000000
++#define INFO19_SFT 0
++#define INFO19_HI 31
++#define INFO19_SZ 32
++#define INFO20_MSK 0xffffffff
++#define INFO20_I_MSK 0x00000000
++#define INFO20_SFT 0
++#define INFO20_HI 31
++#define INFO20_SZ 32
++#define INFO21_MSK 0xffffffff
++#define INFO21_I_MSK 0x00000000
++#define INFO21_SFT 0
++#define INFO21_HI 31
++#define INFO21_SZ 32
++#define INFO22_MSK 0xffffffff
++#define INFO22_I_MSK 0x00000000
++#define INFO22_SFT 0
++#define INFO22_HI 31
++#define INFO22_SZ 32
++#define INFO23_MSK 0xffffffff
++#define INFO23_I_MSK 0x00000000
++#define INFO23_SFT 0
++#define INFO23_HI 31
++#define INFO23_SZ 32
++#define INFO24_MSK 0xffffffff
++#define INFO24_I_MSK 0x00000000
++#define INFO24_SFT 0
++#define INFO24_HI 31
++#define INFO24_SZ 32
++#define INFO25_MSK 0xffffffff
++#define INFO25_I_MSK 0x00000000
++#define INFO25_SFT 0
++#define INFO25_HI 31
++#define INFO25_SZ 32
++#define INFO26_MSK 0xffffffff
++#define INFO26_I_MSK 0x00000000
++#define INFO26_SFT 0
++#define INFO26_HI 31
++#define INFO26_SZ 32
++#define INFO27_MSK 0xffffffff
++#define INFO27_I_MSK 0x00000000
++#define INFO27_SFT 0
++#define INFO27_HI 31
++#define INFO27_SZ 32
++#define INFO28_MSK 0xffffffff
++#define INFO28_I_MSK 0x00000000
++#define INFO28_SFT 0
++#define INFO28_HI 31
++#define INFO28_SZ 32
++#define INFO29_MSK 0xffffffff
++#define INFO29_I_MSK 0x00000000
++#define INFO29_SFT 0
++#define INFO29_HI 31
++#define INFO29_SZ 32
++#define INFO30_MSK 0xffffffff
++#define INFO30_I_MSK 0x00000000
++#define INFO30_SFT 0
++#define INFO30_HI 31
++#define INFO30_SZ 32
++#define INFO31_MSK 0xffffffff
++#define INFO31_I_MSK 0x00000000
++#define INFO31_SFT 0
++#define INFO31_HI 31
++#define INFO31_SZ 32
++#define INFO32_MSK 0xffffffff
++#define INFO32_I_MSK 0x00000000
++#define INFO32_SFT 0
++#define INFO32_HI 31
++#define INFO32_SZ 32
++#define INFO33_MSK 0xffffffff
++#define INFO33_I_MSK 0x00000000
++#define INFO33_SFT 0
++#define INFO33_HI 31
++#define INFO33_SZ 32
++#define INFO34_MSK 0xffffffff
++#define INFO34_I_MSK 0x00000000
++#define INFO34_SFT 0
++#define INFO34_HI 31
++#define INFO34_SZ 32
++#define INFO35_MSK 0xffffffff
++#define INFO35_I_MSK 0x00000000
++#define INFO35_SFT 0
++#define INFO35_HI 31
++#define INFO35_SZ 32
++#define INFO36_MSK 0xffffffff
++#define INFO36_I_MSK 0x00000000
++#define INFO36_SFT 0
++#define INFO36_HI 31
++#define INFO36_SZ 32
++#define INFO37_MSK 0xffffffff
++#define INFO37_I_MSK 0x00000000
++#define INFO37_SFT 0
++#define INFO37_HI 31
++#define INFO37_SZ 32
++#define INFO38_MSK 0xffffffff
++#define INFO38_I_MSK 0x00000000
++#define INFO38_SFT 0
++#define INFO38_HI 31
++#define INFO38_SZ 32
++#define INFO_MASK_MSK 0xffffffff
++#define INFO_MASK_I_MSK 0x00000000
++#define INFO_MASK_SFT 0
++#define INFO_MASK_HI 31
++#define INFO_MASK_SZ 32
++#define INFO_DEF_RATE_MSK 0x0000003f
++#define INFO_DEF_RATE_I_MSK 0xffffffc0
++#define INFO_DEF_RATE_SFT 0
++#define INFO_DEF_RATE_HI 5
++#define INFO_DEF_RATE_SZ 6
++#define INFO_MRX_OFFSET_MSK 0x000f0000
++#define INFO_MRX_OFFSET_I_MSK 0xfff0ffff
++#define INFO_MRX_OFFSET_SFT 16
++#define INFO_MRX_OFFSET_HI 19
++#define INFO_MRX_OFFSET_SZ 4
++#define BCAST_RATEUNKNOW_MSK 0x3f000000
++#define BCAST_RATEUNKNOW_I_MSK 0xc0ffffff
++#define BCAST_RATEUNKNOW_SFT 24
++#define BCAST_RATEUNKNOW_HI 29
++#define BCAST_RATEUNKNOW_SZ 6
++#define INFO_IDX_TBL_ADDR_MSK 0xffffffff
++#define INFO_IDX_TBL_ADDR_I_MSK 0x00000000
++#define INFO_IDX_TBL_ADDR_SFT 0
++#define INFO_IDX_TBL_ADDR_HI 31
++#define INFO_IDX_TBL_ADDR_SZ 32
++#define INFO_LEN_TBL_ADDR_MSK 0xffffffff
++#define INFO_LEN_TBL_ADDR_I_MSK 0x00000000
++#define INFO_LEN_TBL_ADDR_SFT 0
++#define INFO_LEN_TBL_ADDR_HI 31
++#define INFO_LEN_TBL_ADDR_SZ 32
++#define IC_TAG_31_0_MSK 0xffffffff
++#define IC_TAG_31_0_I_MSK 0x00000000
++#define IC_TAG_31_0_SFT 0
++#define IC_TAG_31_0_HI 31
++#define IC_TAG_31_0_SZ 32
++#define IC_TAG_63_32_MSK 0xffffffff
++#define IC_TAG_63_32_I_MSK 0x00000000
++#define IC_TAG_63_32_SFT 0
++#define IC_TAG_63_32_HI 31
++#define IC_TAG_63_32_SZ 32
++#define CH1_PRI_MSK 0x00000003
++#define CH1_PRI_I_MSK 0xfffffffc
++#define CH1_PRI_SFT 0
++#define CH1_PRI_HI 1
++#define CH1_PRI_SZ 2
++#define CH2_PRI_MSK 0x00000300
++#define CH2_PRI_I_MSK 0xfffffcff
++#define CH2_PRI_SFT 8
++#define CH2_PRI_HI 9
++#define CH2_PRI_SZ 2
++#define CH3_PRI_MSK 0x00030000
++#define CH3_PRI_I_MSK 0xfffcffff
++#define CH3_PRI_SFT 16
++#define CH3_PRI_HI 17
++#define CH3_PRI_SZ 2
++#define RG_MAC_LPBK_MSK 0x00000001
++#define RG_MAC_LPBK_I_MSK 0xfffffffe
++#define RG_MAC_LPBK_SFT 0
++#define RG_MAC_LPBK_HI 0
++#define RG_MAC_LPBK_SZ 1
++#define RG_MAC_M2M_MSK 0x00000002
++#define RG_MAC_M2M_I_MSK 0xfffffffd
++#define RG_MAC_M2M_SFT 1
++#define RG_MAC_M2M_HI 1
++#define RG_MAC_M2M_SZ 1
++#define RG_PHY_LPBK_MSK 0x00000004
++#define RG_PHY_LPBK_I_MSK 0xfffffffb
++#define RG_PHY_LPBK_SFT 2
++#define RG_PHY_LPBK_HI 2
++#define RG_PHY_LPBK_SZ 1
++#define RG_LPBK_RX_EN_MSK 0x00000008
++#define RG_LPBK_RX_EN_I_MSK 0xfffffff7
++#define RG_LPBK_RX_EN_SFT 3
++#define RG_LPBK_RX_EN_HI 3
++#define RG_LPBK_RX_EN_SZ 1
++#define EXT_MAC_MODE_MSK 0x00000010
++#define EXT_MAC_MODE_I_MSK 0xffffffef
++#define EXT_MAC_MODE_SFT 4
++#define EXT_MAC_MODE_HI 4
++#define EXT_MAC_MODE_SZ 1
++#define EXT_PHY_MODE_MSK 0x00000020
++#define EXT_PHY_MODE_I_MSK 0xffffffdf
++#define EXT_PHY_MODE_SFT 5
++#define EXT_PHY_MODE_HI 5
++#define EXT_PHY_MODE_SZ 1
++#define ASIC_TAG_MSK 0xff000000
++#define ASIC_TAG_I_MSK 0x00ffffff
++#define ASIC_TAG_SFT 24
++#define ASIC_TAG_HI 31
++#define ASIC_TAG_SZ 8
++#define HCI_SW_RST_MSK 0x00000001
++#define HCI_SW_RST_I_MSK 0xfffffffe
++#define HCI_SW_RST_SFT 0
++#define HCI_SW_RST_HI 0
++#define HCI_SW_RST_SZ 1
++#define CO_PROC_SW_RST_MSK 0x00000002
++#define CO_PROC_SW_RST_I_MSK 0xfffffffd
++#define CO_PROC_SW_RST_SFT 1
++#define CO_PROC_SW_RST_HI 1
++#define CO_PROC_SW_RST_SZ 1
++#define MTX_MISC_SW_RST_MSK 0x00000008
++#define MTX_MISC_SW_RST_I_MSK 0xfffffff7
++#define MTX_MISC_SW_RST_SFT 3
++#define MTX_MISC_SW_RST_HI 3
++#define MTX_MISC_SW_RST_SZ 1
++#define MTX_QUE_SW_RST_MSK 0x00000010
++#define MTX_QUE_SW_RST_I_MSK 0xffffffef
++#define MTX_QUE_SW_RST_SFT 4
++#define MTX_QUE_SW_RST_HI 4
++#define MTX_QUE_SW_RST_SZ 1
++#define MTX_CHST_SW_RST_MSK 0x00000020
++#define MTX_CHST_SW_RST_I_MSK 0xffffffdf
++#define MTX_CHST_SW_RST_SFT 5
++#define MTX_CHST_SW_RST_HI 5
++#define MTX_CHST_SW_RST_SZ 1
++#define MTX_BCN_SW_RST_MSK 0x00000040
++#define MTX_BCN_SW_RST_I_MSK 0xffffffbf
++#define MTX_BCN_SW_RST_SFT 6
++#define MTX_BCN_SW_RST_HI 6
++#define MTX_BCN_SW_RST_SZ 1
++#define MRX_SW_RST_MSK 0x00000080
++#define MRX_SW_RST_I_MSK 0xffffff7f
++#define MRX_SW_RST_SFT 7
++#define MRX_SW_RST_HI 7
++#define MRX_SW_RST_SZ 1
++#define AMPDU_SW_RST_MSK 0x00000100
++#define AMPDU_SW_RST_I_MSK 0xfffffeff
++#define AMPDU_SW_RST_SFT 8
++#define AMPDU_SW_RST_HI 8
++#define AMPDU_SW_RST_SZ 1
++#define MMU_SW_RST_MSK 0x00000200
++#define MMU_SW_RST_I_MSK 0xfffffdff
++#define MMU_SW_RST_SFT 9
++#define MMU_SW_RST_HI 9
++#define MMU_SW_RST_SZ 1
++#define ID_MNG_SW_RST_MSK 0x00000800
++#define ID_MNG_SW_RST_I_MSK 0xfffff7ff
++#define ID_MNG_SW_RST_SFT 11
++#define ID_MNG_SW_RST_HI 11
++#define ID_MNG_SW_RST_SZ 1
++#define MBOX_SW_RST_MSK 0x00001000
++#define MBOX_SW_RST_I_MSK 0xffffefff
++#define MBOX_SW_RST_SFT 12
++#define MBOX_SW_RST_HI 12
++#define MBOX_SW_RST_SZ 1
++#define SCRT_SW_RST_MSK 0x00002000
++#define SCRT_SW_RST_I_MSK 0xffffdfff
++#define SCRT_SW_RST_SFT 13
++#define SCRT_SW_RST_HI 13
++#define SCRT_SW_RST_SZ 1
++#define MIC_SW_RST_MSK 0x00004000
++#define MIC_SW_RST_I_MSK 0xffffbfff
++#define MIC_SW_RST_SFT 14
++#define MIC_SW_RST_HI 14
++#define MIC_SW_RST_SZ 1
++#define CO_PROC_ENG_RST_MSK 0x00000002
++#define CO_PROC_ENG_RST_I_MSK 0xfffffffd
++#define CO_PROC_ENG_RST_SFT 1
++#define CO_PROC_ENG_RST_HI 1
++#define CO_PROC_ENG_RST_SZ 1
++#define MTX_MISC_ENG_RST_MSK 0x00000008
++#define MTX_MISC_ENG_RST_I_MSK 0xfffffff7
++#define MTX_MISC_ENG_RST_SFT 3
++#define MTX_MISC_ENG_RST_HI 3
++#define MTX_MISC_ENG_RST_SZ 1
++#define MTX_QUE_ENG_RST_MSK 0x00000010
++#define MTX_QUE_ENG_RST_I_MSK 0xffffffef
++#define MTX_QUE_ENG_RST_SFT 4
++#define MTX_QUE_ENG_RST_HI 4
++#define MTX_QUE_ENG_RST_SZ 1
++#define MTX_CHST_ENG_RST_MSK 0x00000020
++#define MTX_CHST_ENG_RST_I_MSK 0xffffffdf
++#define MTX_CHST_ENG_RST_SFT 5
++#define MTX_CHST_ENG_RST_HI 5
++#define MTX_CHST_ENG_RST_SZ 1
++#define MTX_BCN_ENG_RST_MSK 0x00000040
++#define MTX_BCN_ENG_RST_I_MSK 0xffffffbf
++#define MTX_BCN_ENG_RST_SFT 6
++#define MTX_BCN_ENG_RST_HI 6
++#define MTX_BCN_ENG_RST_SZ 1
++#define MRX_ENG_RST_MSK 0x00000080
++#define MRX_ENG_RST_I_MSK 0xffffff7f
++#define MRX_ENG_RST_SFT 7
++#define MRX_ENG_RST_HI 7
++#define MRX_ENG_RST_SZ 1
++#define AMPDU_ENG_RST_MSK 0x00000100
++#define AMPDU_ENG_RST_I_MSK 0xfffffeff
++#define AMPDU_ENG_RST_SFT 8
++#define AMPDU_ENG_RST_HI 8
++#define AMPDU_ENG_RST_SZ 1
++#define ID_MNG_ENG_RST_MSK 0x00004000
++#define ID_MNG_ENG_RST_I_MSK 0xffffbfff
++#define ID_MNG_ENG_RST_SFT 14
++#define ID_MNG_ENG_RST_HI 14
++#define ID_MNG_ENG_RST_SZ 1
++#define MBOX_ENG_RST_MSK 0x00008000
++#define MBOX_ENG_RST_I_MSK 0xffff7fff
++#define MBOX_ENG_RST_SFT 15
++#define MBOX_ENG_RST_HI 15
++#define MBOX_ENG_RST_SZ 1
++#define SCRT_ENG_RST_MSK 0x00010000
++#define SCRT_ENG_RST_I_MSK 0xfffeffff
++#define SCRT_ENG_RST_SFT 16
++#define SCRT_ENG_RST_HI 16
++#define SCRT_ENG_RST_SZ 1
++#define MIC_ENG_RST_MSK 0x00020000
++#define MIC_ENG_RST_I_MSK 0xfffdffff
++#define MIC_ENG_RST_SFT 17
++#define MIC_ENG_RST_HI 17
++#define MIC_ENG_RST_SZ 1
++#define CO_PROC_CSR_RST_MSK 0x00000002
++#define CO_PROC_CSR_RST_I_MSK 0xfffffffd
++#define CO_PROC_CSR_RST_SFT 1
++#define CO_PROC_CSR_RST_HI 1
++#define CO_PROC_CSR_RST_SZ 1
++#define MTX_MISC_CSR_RST_MSK 0x00000008
++#define MTX_MISC_CSR_RST_I_MSK 0xfffffff7
++#define MTX_MISC_CSR_RST_SFT 3
++#define MTX_MISC_CSR_RST_HI 3
++#define MTX_MISC_CSR_RST_SZ 1
++#define MTX_QUE0_CSR_RST_MSK 0x00000010
++#define MTX_QUE0_CSR_RST_I_MSK 0xffffffef
++#define MTX_QUE0_CSR_RST_SFT 4
++#define MTX_QUE0_CSR_RST_HI 4
++#define MTX_QUE0_CSR_RST_SZ 1
++#define MTX_QUE1_CSR_RST_MSK 0x00000020
++#define MTX_QUE1_CSR_RST_I_MSK 0xffffffdf
++#define MTX_QUE1_CSR_RST_SFT 5
++#define MTX_QUE1_CSR_RST_HI 5
++#define MTX_QUE1_CSR_RST_SZ 1
++#define MTX_QUE2_CSR_RST_MSK 0x00000040
++#define MTX_QUE2_CSR_RST_I_MSK 0xffffffbf
++#define MTX_QUE2_CSR_RST_SFT 6
++#define MTX_QUE2_CSR_RST_HI 6
++#define MTX_QUE2_CSR_RST_SZ 1
++#define MTX_QUE3_CSR_RST_MSK 0x00000080
++#define MTX_QUE3_CSR_RST_I_MSK 0xffffff7f
++#define MTX_QUE3_CSR_RST_SFT 7
++#define MTX_QUE3_CSR_RST_HI 7
++#define MTX_QUE3_CSR_RST_SZ 1
++#define MTX_QUE4_CSR_RST_MSK 0x00000100
++#define MTX_QUE4_CSR_RST_I_MSK 0xfffffeff
++#define MTX_QUE4_CSR_RST_SFT 8
++#define MTX_QUE4_CSR_RST_HI 8
++#define MTX_QUE4_CSR_RST_SZ 1
++#define MTX_QUE5_CSR_RST_MSK 0x00000200
++#define MTX_QUE5_CSR_RST_I_MSK 0xfffffdff
++#define MTX_QUE5_CSR_RST_SFT 9
++#define MTX_QUE5_CSR_RST_HI 9
++#define MTX_QUE5_CSR_RST_SZ 1
++#define MRX_CSR_RST_MSK 0x00000400
++#define MRX_CSR_RST_I_MSK 0xfffffbff
++#define MRX_CSR_RST_SFT 10
++#define MRX_CSR_RST_HI 10
++#define MRX_CSR_RST_SZ 1
++#define AMPDU_CSR_RST_MSK 0x00000800
++#define AMPDU_CSR_RST_I_MSK 0xfffff7ff
++#define AMPDU_CSR_RST_SFT 11
++#define AMPDU_CSR_RST_HI 11
++#define AMPDU_CSR_RST_SZ 1
++#define SCRT_CSR_RST_MSK 0x00002000
++#define SCRT_CSR_RST_I_MSK 0xffffdfff
++#define SCRT_CSR_RST_SFT 13
++#define SCRT_CSR_RST_HI 13
++#define SCRT_CSR_RST_SZ 1
++#define ID_MNG_CSR_RST_MSK 0x00004000
++#define ID_MNG_CSR_RST_I_MSK 0xffffbfff
++#define ID_MNG_CSR_RST_SFT 14
++#define ID_MNG_CSR_RST_HI 14
++#define ID_MNG_CSR_RST_SZ 1
++#define MBOX_CSR_RST_MSK 0x00008000
++#define MBOX_CSR_RST_I_MSK 0xffff7fff
++#define MBOX_CSR_RST_SFT 15
++#define MBOX_CSR_RST_HI 15
++#define MBOX_CSR_RST_SZ 1
++#define HCI_CLK_EN_MSK 0x00000001
++#define HCI_CLK_EN_I_MSK 0xfffffffe
++#define HCI_CLK_EN_SFT 0
++#define HCI_CLK_EN_HI 0
++#define HCI_CLK_EN_SZ 1
++#define CO_PROC_CLK_EN_MSK 0x00000002
++#define CO_PROC_CLK_EN_I_MSK 0xfffffffd
++#define CO_PROC_CLK_EN_SFT 1
++#define CO_PROC_CLK_EN_HI 1
++#define CO_PROC_CLK_EN_SZ 1
++#define MTX_MISC_CLK_EN_MSK 0x00000008
++#define MTX_MISC_CLK_EN_I_MSK 0xfffffff7
++#define MTX_MISC_CLK_EN_SFT 3
++#define MTX_MISC_CLK_EN_HI 3
++#define MTX_MISC_CLK_EN_SZ 1
++#define MTX_QUE_CLK_EN_MSK 0x00000010
++#define MTX_QUE_CLK_EN_I_MSK 0xffffffef
++#define MTX_QUE_CLK_EN_SFT 4
++#define MTX_QUE_CLK_EN_HI 4
++#define MTX_QUE_CLK_EN_SZ 1
++#define MRX_CLK_EN_MSK 0x00000020
++#define MRX_CLK_EN_I_MSK 0xffffffdf
++#define MRX_CLK_EN_SFT 5
++#define MRX_CLK_EN_HI 5
++#define MRX_CLK_EN_SZ 1
++#define AMPDU_CLK_EN_MSK 0x00000040
++#define AMPDU_CLK_EN_I_MSK 0xffffffbf
++#define AMPDU_CLK_EN_SFT 6
++#define AMPDU_CLK_EN_HI 6
++#define AMPDU_CLK_EN_SZ 1
++#define MMU_CLK_EN_MSK 0x00000080
++#define MMU_CLK_EN_I_MSK 0xffffff7f
++#define MMU_CLK_EN_SFT 7
++#define MMU_CLK_EN_HI 7
++#define MMU_CLK_EN_SZ 1
++#define ID_MNG_CLK_EN_MSK 0x00000200
++#define ID_MNG_CLK_EN_I_MSK 0xfffffdff
++#define ID_MNG_CLK_EN_SFT 9
++#define ID_MNG_CLK_EN_HI 9
++#define ID_MNG_CLK_EN_SZ 1
++#define MBOX_CLK_EN_MSK 0x00000400
++#define MBOX_CLK_EN_I_MSK 0xfffffbff
++#define MBOX_CLK_EN_SFT 10
++#define MBOX_CLK_EN_HI 10
++#define MBOX_CLK_EN_SZ 1
++#define SCRT_CLK_EN_MSK 0x00000800
++#define SCRT_CLK_EN_I_MSK 0xfffff7ff
++#define SCRT_CLK_EN_SFT 11
++#define SCRT_CLK_EN_HI 11
++#define SCRT_CLK_EN_SZ 1
++#define MIC_CLK_EN_MSK 0x00001000
++#define MIC_CLK_EN_I_MSK 0xffffefff
++#define MIC_CLK_EN_SFT 12
++#define MIC_CLK_EN_HI 12
++#define MIC_CLK_EN_SZ 1
++#define MIB_CLK_EN_MSK 0x00002000
++#define MIB_CLK_EN_I_MSK 0xffffdfff
++#define MIB_CLK_EN_SFT 13
++#define MIB_CLK_EN_HI 13
++#define MIB_CLK_EN_SZ 1
++#define HCI_ENG_CLK_EN_MSK 0x00000001
++#define HCI_ENG_CLK_EN_I_MSK 0xfffffffe
++#define HCI_ENG_CLK_EN_SFT 0
++#define HCI_ENG_CLK_EN_HI 0
++#define HCI_ENG_CLK_EN_SZ 1
++#define CO_PROC_ENG_CLK_EN_MSK 0x00000002
++#define CO_PROC_ENG_CLK_EN_I_MSK 0xfffffffd
++#define CO_PROC_ENG_CLK_EN_SFT 1
++#define CO_PROC_ENG_CLK_EN_HI 1
++#define CO_PROC_ENG_CLK_EN_SZ 1
++#define MTX_MISC_ENG_CLK_EN_MSK 0x00000008
++#define MTX_MISC_ENG_CLK_EN_I_MSK 0xfffffff7
++#define MTX_MISC_ENG_CLK_EN_SFT 3
++#define MTX_MISC_ENG_CLK_EN_HI 3
++#define MTX_MISC_ENG_CLK_EN_SZ 1
++#define MTX_QUE_ENG_CLK_EN_MSK 0x00000010
++#define MTX_QUE_ENG_CLK_EN_I_MSK 0xffffffef
++#define MTX_QUE_ENG_CLK_EN_SFT 4
++#define MTX_QUE_ENG_CLK_EN_HI 4
++#define MTX_QUE_ENG_CLK_EN_SZ 1
++#define MRX_ENG_CLK_EN_MSK 0x00000020
++#define MRX_ENG_CLK_EN_I_MSK 0xffffffdf
++#define MRX_ENG_CLK_EN_SFT 5
++#define MRX_ENG_CLK_EN_HI 5
++#define MRX_ENG_CLK_EN_SZ 1
++#define AMPDU_ENG_CLK_EN_MSK 0x00000040
++#define AMPDU_ENG_CLK_EN_I_MSK 0xffffffbf
++#define AMPDU_ENG_CLK_EN_SFT 6
++#define AMPDU_ENG_CLK_EN_HI 6
++#define AMPDU_ENG_CLK_EN_SZ 1
++#define ID_MNG_ENG_CLK_EN_MSK 0x00001000
++#define ID_MNG_ENG_CLK_EN_I_MSK 0xffffefff
++#define ID_MNG_ENG_CLK_EN_SFT 12
++#define ID_MNG_ENG_CLK_EN_HI 12
++#define ID_MNG_ENG_CLK_EN_SZ 1
++#define MBOX_ENG_CLK_EN_MSK 0x00002000
++#define MBOX_ENG_CLK_EN_I_MSK 0xffffdfff
++#define MBOX_ENG_CLK_EN_SFT 13
++#define MBOX_ENG_CLK_EN_HI 13
++#define MBOX_ENG_CLK_EN_SZ 1
++#define SCRT_ENG_CLK_EN_MSK 0x00004000
++#define SCRT_ENG_CLK_EN_I_MSK 0xffffbfff
++#define SCRT_ENG_CLK_EN_SFT 14
++#define SCRT_ENG_CLK_EN_HI 14
++#define SCRT_ENG_CLK_EN_SZ 1
++#define MIC_ENG_CLK_EN_MSK 0x00008000
++#define MIC_ENG_CLK_EN_I_MSK 0xffff7fff
++#define MIC_ENG_CLK_EN_SFT 15
++#define MIC_ENG_CLK_EN_HI 15
++#define MIC_ENG_CLK_EN_SZ 1
++#define CO_PROC_CSR_CLK_EN_MSK 0x00000002
++#define CO_PROC_CSR_CLK_EN_I_MSK 0xfffffffd
++#define CO_PROC_CSR_CLK_EN_SFT 1
++#define CO_PROC_CSR_CLK_EN_HI 1
++#define CO_PROC_CSR_CLK_EN_SZ 1
++#define MRX_CSR_CLK_EN_MSK 0x00000400
++#define MRX_CSR_CLK_EN_I_MSK 0xfffffbff
++#define MRX_CSR_CLK_EN_SFT 10
++#define MRX_CSR_CLK_EN_HI 10
++#define MRX_CSR_CLK_EN_SZ 1
++#define AMPDU_CSR_CLK_EN_MSK 0x00000800
++#define AMPDU_CSR_CLK_EN_I_MSK 0xfffff7ff
++#define AMPDU_CSR_CLK_EN_SFT 11
++#define AMPDU_CSR_CLK_EN_HI 11
++#define AMPDU_CSR_CLK_EN_SZ 1
++#define SCRT_CSR_CLK_EN_MSK 0x00002000
++#define SCRT_CSR_CLK_EN_I_MSK 0xffffdfff
++#define SCRT_CSR_CLK_EN_SFT 13
++#define SCRT_CSR_CLK_EN_HI 13
++#define SCRT_CSR_CLK_EN_SZ 1
++#define ID_MNG_CSR_CLK_EN_MSK 0x00004000
++#define ID_MNG_CSR_CLK_EN_I_MSK 0xffffbfff
++#define ID_MNG_CSR_CLK_EN_SFT 14
++#define ID_MNG_CSR_CLK_EN_HI 14
++#define ID_MNG_CSR_CLK_EN_SZ 1
++#define MBOX_CSR_CLK_EN_MSK 0x00008000
++#define MBOX_CSR_CLK_EN_I_MSK 0xffff7fff
++#define MBOX_CSR_CLK_EN_SFT 15
++#define MBOX_CSR_CLK_EN_HI 15
++#define MBOX_CSR_CLK_EN_SZ 1
++#define OP_MODE_MSK 0x00000003
++#define OP_MODE_I_MSK 0xfffffffc
++#define OP_MODE_SFT 0
++#define OP_MODE_HI 1
++#define OP_MODE_SZ 2
++#define HT_MODE_MSK 0x0000000c
++#define HT_MODE_I_MSK 0xfffffff3
++#define HT_MODE_SFT 2
++#define HT_MODE_HI 3
++#define HT_MODE_SZ 2
++#define QOS_EN_MSK 0x00000010
++#define QOS_EN_I_MSK 0xffffffef
++#define QOS_EN_SFT 4
++#define QOS_EN_HI 4
++#define QOS_EN_SZ 1
++#define PB_OFFSET_MSK 0x0000ff00
++#define PB_OFFSET_I_MSK 0xffff00ff
++#define PB_OFFSET_SFT 8
++#define PB_OFFSET_HI 15
++#define PB_OFFSET_SZ 8
++#define SNIFFER_MODE_MSK 0x00010000
++#define SNIFFER_MODE_I_MSK 0xfffeffff
++#define SNIFFER_MODE_SFT 16
++#define SNIFFER_MODE_HI 16
++#define SNIFFER_MODE_SZ 1
++#define DUP_FLT_MSK 0x00020000
++#define DUP_FLT_I_MSK 0xfffdffff
++#define DUP_FLT_SFT 17
++#define DUP_FLT_HI 17
++#define DUP_FLT_SZ 1
++#define TX_PKT_RSVD_MSK 0x001c0000
++#define TX_PKT_RSVD_I_MSK 0xffe3ffff
++#define TX_PKT_RSVD_SFT 18
++#define TX_PKT_RSVD_HI 20
++#define TX_PKT_RSVD_SZ 3
++#define AMPDU_SNIFFER_MSK 0x00200000
++#define AMPDU_SNIFFER_I_MSK 0xffdfffff
++#define AMPDU_SNIFFER_SFT 21
++#define AMPDU_SNIFFER_HI 21
++#define AMPDU_SNIFFER_SZ 1
++#define REASON_TRAP0_MSK 0xffffffff
++#define REASON_TRAP0_I_MSK 0x00000000
++#define REASON_TRAP0_SFT 0
++#define REASON_TRAP0_HI 31
++#define REASON_TRAP0_SZ 32
++#define REASON_TRAP1_MSK 0xffffffff
++#define REASON_TRAP1_I_MSK 0x00000000
++#define REASON_TRAP1_SFT 0
++#define REASON_TRAP1_HI 31
++#define REASON_TRAP1_SZ 32
++#define BSSID_31_0_MSK 0xffffffff
++#define BSSID_31_0_I_MSK 0x00000000
++#define BSSID_31_0_SFT 0
++#define BSSID_31_0_HI 31
++#define BSSID_31_0_SZ 32
++#define BSSID_47_32_MSK 0x0000ffff
++#define BSSID_47_32_I_MSK 0xffff0000
++#define BSSID_47_32_SFT 0
++#define BSSID_47_32_HI 15
++#define BSSID_47_32_SZ 16
++#define SCRT_STATE_MSK 0x0000000f
++#define SCRT_STATE_I_MSK 0xfffffff0
++#define SCRT_STATE_SFT 0
++#define SCRT_STATE_HI 3
++#define SCRT_STATE_SZ 4
++#define STA_MAC_31_0_MSK 0xffffffff
++#define STA_MAC_31_0_I_MSK 0x00000000
++#define STA_MAC_31_0_SFT 0
++#define STA_MAC_31_0_HI 31
++#define STA_MAC_31_0_SZ 32
++#define STA_MAC_47_32_MSK 0x0000ffff
++#define STA_MAC_47_32_I_MSK 0xffff0000
++#define STA_MAC_47_32_SFT 0
++#define STA_MAC_47_32_HI 15
++#define STA_MAC_47_32_SZ 16
++#define PAIR_SCRT_MSK 0x00000007
++#define PAIR_SCRT_I_MSK 0xfffffff8
++#define PAIR_SCRT_SFT 0
++#define PAIR_SCRT_HI 2
++#define PAIR_SCRT_SZ 3
++#define GRP_SCRT_MSK 0x00000038
++#define GRP_SCRT_I_MSK 0xffffffc7
++#define GRP_SCRT_SFT 3
++#define GRP_SCRT_HI 5
++#define GRP_SCRT_SZ 3
++#define SCRT_PKT_ID_MSK 0x00001fc0
++#define SCRT_PKT_ID_I_MSK 0xffffe03f
++#define SCRT_PKT_ID_SFT 6
++#define SCRT_PKT_ID_HI 12
++#define SCRT_PKT_ID_SZ 7
++#define SCRT_RPLY_IGNORE_MSK 0x00010000
++#define SCRT_RPLY_IGNORE_I_MSK 0xfffeffff
++#define SCRT_RPLY_IGNORE_SFT 16
++#define SCRT_RPLY_IGNORE_HI 16
++#define SCRT_RPLY_IGNORE_SZ 1
++#define COEXIST_EN_MSK 0x00000001
++#define COEXIST_EN_I_MSK 0xfffffffe
++#define COEXIST_EN_SFT 0
++#define COEXIST_EN_HI 0
++#define COEXIST_EN_SZ 1
++#define WIRE_MODE_MSK 0x0000000e
++#define WIRE_MODE_I_MSK 0xfffffff1
++#define WIRE_MODE_SFT 1
++#define WIRE_MODE_HI 3
++#define WIRE_MODE_SZ 3
++#define WL_RX_PRI_MSK 0x00000010
++#define WL_RX_PRI_I_MSK 0xffffffef
++#define WL_RX_PRI_SFT 4
++#define WL_RX_PRI_HI 4
++#define WL_RX_PRI_SZ 1
++#define WL_TX_PRI_MSK 0x00000020
++#define WL_TX_PRI_I_MSK 0xffffffdf
++#define WL_TX_PRI_SFT 5
++#define WL_TX_PRI_HI 5
++#define WL_TX_PRI_SZ 1
++#define GURAN_USE_EN_MSK 0x00000100
++#define GURAN_USE_EN_I_MSK 0xfffffeff
++#define GURAN_USE_EN_SFT 8
++#define GURAN_USE_EN_HI 8
++#define GURAN_USE_EN_SZ 1
++#define GURAN_USE_CTRL_MSK 0x00000200
++#define GURAN_USE_CTRL_I_MSK 0xfffffdff
++#define GURAN_USE_CTRL_SFT 9
++#define GURAN_USE_CTRL_HI 9
++#define GURAN_USE_CTRL_SZ 1
++#define BEACON_TIMEOUT_EN_MSK 0x00000400
++#define BEACON_TIMEOUT_EN_I_MSK 0xfffffbff
++#define BEACON_TIMEOUT_EN_SFT 10
++#define BEACON_TIMEOUT_EN_HI 10
++#define BEACON_TIMEOUT_EN_SZ 1
++#define WLAN_ACT_POL_MSK 0x00000800
++#define WLAN_ACT_POL_I_MSK 0xfffff7ff
++#define WLAN_ACT_POL_SFT 11
++#define WLAN_ACT_POL_HI 11
++#define WLAN_ACT_POL_SZ 1
++#define DUAL_ANT_EN_MSK 0x00001000
++#define DUAL_ANT_EN_I_MSK 0xffffefff
++#define DUAL_ANT_EN_SFT 12
++#define DUAL_ANT_EN_HI 12
++#define DUAL_ANT_EN_SZ 1
++#define TRSW_PHY_POL_MSK 0x00010000
++#define TRSW_PHY_POL_I_MSK 0xfffeffff
++#define TRSW_PHY_POL_SFT 16
++#define TRSW_PHY_POL_HI 16
++#define TRSW_PHY_POL_SZ 1
++#define WIFI_TX_SW_POL_MSK 0x00020000
++#define WIFI_TX_SW_POL_I_MSK 0xfffdffff
++#define WIFI_TX_SW_POL_SFT 17
++#define WIFI_TX_SW_POL_HI 17
++#define WIFI_TX_SW_POL_SZ 1
++#define WIFI_RX_SW_POL_MSK 0x00040000
++#define WIFI_RX_SW_POL_I_MSK 0xfffbffff
++#define WIFI_RX_SW_POL_SFT 18
++#define WIFI_RX_SW_POL_HI 18
++#define WIFI_RX_SW_POL_SZ 1
++#define BT_SW_POL_MSK 0x00080000
++#define BT_SW_POL_I_MSK 0xfff7ffff
++#define BT_SW_POL_SFT 19
++#define BT_SW_POL_HI 19
++#define BT_SW_POL_SZ 1
++#define BT_PRI_SMP_TIME_MSK 0x000000ff
++#define BT_PRI_SMP_TIME_I_MSK 0xffffff00
++#define BT_PRI_SMP_TIME_SFT 0
++#define BT_PRI_SMP_TIME_HI 7
++#define BT_PRI_SMP_TIME_SZ 8
++#define BT_STA_SMP_TIME_MSK 0x0000ff00
++#define BT_STA_SMP_TIME_I_MSK 0xffff00ff
++#define BT_STA_SMP_TIME_SFT 8
++#define BT_STA_SMP_TIME_HI 15
++#define BT_STA_SMP_TIME_SZ 8
++#define BEACON_TIMEOUT_MSK 0x00ff0000
++#define BEACON_TIMEOUT_I_MSK 0xff00ffff
++#define BEACON_TIMEOUT_SFT 16
++#define BEACON_TIMEOUT_HI 23
++#define BEACON_TIMEOUT_SZ 8
++#define WLAN_REMAIN_TIME_MSK 0xff000000
++#define WLAN_REMAIN_TIME_I_MSK 0x00ffffff
++#define WLAN_REMAIN_TIME_SFT 24
++#define WLAN_REMAIN_TIME_HI 31
++#define WLAN_REMAIN_TIME_SZ 8
++#define SW_MANUAL_EN_MSK 0x00000001
++#define SW_MANUAL_EN_I_MSK 0xfffffffe
++#define SW_MANUAL_EN_SFT 0
++#define SW_MANUAL_EN_HI 0
++#define SW_MANUAL_EN_SZ 1
++#define SW_WL_TX_MSK 0x00000002
++#define SW_WL_TX_I_MSK 0xfffffffd
++#define SW_WL_TX_SFT 1
++#define SW_WL_TX_HI 1
++#define SW_WL_TX_SZ 1
++#define SW_WL_RX_MSK 0x00000004
++#define SW_WL_RX_I_MSK 0xfffffffb
++#define SW_WL_RX_SFT 2
++#define SW_WL_RX_HI 2
++#define SW_WL_RX_SZ 1
++#define SW_BT_TRX_MSK 0x00000008
++#define SW_BT_TRX_I_MSK 0xfffffff7
++#define SW_BT_TRX_SFT 3
++#define SW_BT_TRX_HI 3
++#define SW_BT_TRX_SZ 1
++#define BT_TXBAR_MANUAL_EN_MSK 0x00000010
++#define BT_TXBAR_MANUAL_EN_I_MSK 0xffffffef
++#define BT_TXBAR_MANUAL_EN_SFT 4
++#define BT_TXBAR_MANUAL_EN_HI 4
++#define BT_TXBAR_MANUAL_EN_SZ 1
++#define BT_TXBAR_SET_MSK 0x00000020
++#define BT_TXBAR_SET_I_MSK 0xffffffdf
++#define BT_TXBAR_SET_SFT 5
++#define BT_TXBAR_SET_HI 5
++#define BT_TXBAR_SET_SZ 1
++#define BT_BUSY_MANUAL_EN_MSK 0x00000100
++#define BT_BUSY_MANUAL_EN_I_MSK 0xfffffeff
++#define BT_BUSY_MANUAL_EN_SFT 8
++#define BT_BUSY_MANUAL_EN_HI 8
++#define BT_BUSY_MANUAL_EN_SZ 1
++#define BT_BUSY_SET_MSK 0x00000200
++#define BT_BUSY_SET_I_MSK 0xfffffdff
++#define BT_BUSY_SET_SFT 9
++#define BT_BUSY_SET_HI 9
++#define BT_BUSY_SET_SZ 1
++#define G0_PKT_CLS_MIB_EN_MSK 0x00000004
++#define G0_PKT_CLS_MIB_EN_I_MSK 0xfffffffb
++#define G0_PKT_CLS_MIB_EN_SFT 2
++#define G0_PKT_CLS_MIB_EN_HI 2
++#define G0_PKT_CLS_MIB_EN_SZ 1
++#define G0_PKT_CLS_ONGOING_MSK 0x00000008
++#define G0_PKT_CLS_ONGOING_I_MSK 0xfffffff7
++#define G0_PKT_CLS_ONGOING_SFT 3
++#define G0_PKT_CLS_ONGOING_HI 3
++#define G0_PKT_CLS_ONGOING_SZ 1
++#define G1_PKT_CLS_MIB_EN_MSK 0x00000010
++#define G1_PKT_CLS_MIB_EN_I_MSK 0xffffffef
++#define G1_PKT_CLS_MIB_EN_SFT 4
++#define G1_PKT_CLS_MIB_EN_HI 4
++#define G1_PKT_CLS_MIB_EN_SZ 1
++#define G1_PKT_CLS_ONGOING_MSK 0x00000020
++#define G1_PKT_CLS_ONGOING_I_MSK 0xffffffdf
++#define G1_PKT_CLS_ONGOING_SFT 5
++#define G1_PKT_CLS_ONGOING_HI 5
++#define G1_PKT_CLS_ONGOING_SZ 1
++#define Q0_PKT_CLS_MIB_EN_MSK 0x00000040
++#define Q0_PKT_CLS_MIB_EN_I_MSK 0xffffffbf
++#define Q0_PKT_CLS_MIB_EN_SFT 6
++#define Q0_PKT_CLS_MIB_EN_HI 6
++#define Q0_PKT_CLS_MIB_EN_SZ 1
++#define Q0_PKT_CLS_ONGOING_MSK 0x00000080
++#define Q0_PKT_CLS_ONGOING_I_MSK 0xffffff7f
++#define Q0_PKT_CLS_ONGOING_SFT 7
++#define Q0_PKT_CLS_ONGOING_HI 7
++#define Q0_PKT_CLS_ONGOING_SZ 1
++#define Q1_PKT_CLS_MIB_EN_MSK 0x00000100
++#define Q1_PKT_CLS_MIB_EN_I_MSK 0xfffffeff
++#define Q1_PKT_CLS_MIB_EN_SFT 8
++#define Q1_PKT_CLS_MIB_EN_HI 8
++#define Q1_PKT_CLS_MIB_EN_SZ 1
++#define Q1_PKT_CLS_ONGOING_MSK 0x00000200
++#define Q1_PKT_CLS_ONGOING_I_MSK 0xfffffdff
++#define Q1_PKT_CLS_ONGOING_SFT 9
++#define Q1_PKT_CLS_ONGOING_HI 9
++#define Q1_PKT_CLS_ONGOING_SZ 1
++#define Q2_PKT_CLS_MIB_EN_MSK 0x00000400
++#define Q2_PKT_CLS_MIB_EN_I_MSK 0xfffffbff
++#define Q2_PKT_CLS_MIB_EN_SFT 10
++#define Q2_PKT_CLS_MIB_EN_HI 10
++#define Q2_PKT_CLS_MIB_EN_SZ 1
++#define Q2_PKT_CLS_ONGOING_MSK 0x00000800
++#define Q2_PKT_CLS_ONGOING_I_MSK 0xfffff7ff
++#define Q2_PKT_CLS_ONGOING_SFT 11
++#define Q2_PKT_CLS_ONGOING_HI 11
++#define Q2_PKT_CLS_ONGOING_SZ 1
++#define Q3_PKT_CLS_MIB_EN_MSK 0x00001000
++#define Q3_PKT_CLS_MIB_EN_I_MSK 0xffffefff
++#define Q3_PKT_CLS_MIB_EN_SFT 12
++#define Q3_PKT_CLS_MIB_EN_HI 12
++#define Q3_PKT_CLS_MIB_EN_SZ 1
++#define Q3_PKT_CLS_ONGOING_MSK 0x00002000
++#define Q3_PKT_CLS_ONGOING_I_MSK 0xffffdfff
++#define Q3_PKT_CLS_ONGOING_SFT 13
++#define Q3_PKT_CLS_ONGOING_HI 13
++#define Q3_PKT_CLS_ONGOING_SZ 1
++#define SCRT_PKT_CLS_MIB_EN_MSK 0x00004000
++#define SCRT_PKT_CLS_MIB_EN_I_MSK 0xffffbfff
++#define SCRT_PKT_CLS_MIB_EN_SFT 14
++#define SCRT_PKT_CLS_MIB_EN_HI 14
++#define SCRT_PKT_CLS_MIB_EN_SZ 1
++#define SCRT_PKT_CLS_ONGOING_MSK 0x00008000
++#define SCRT_PKT_CLS_ONGOING_I_MSK 0xffff7fff
++#define SCRT_PKT_CLS_ONGOING_SFT 15
++#define SCRT_PKT_CLS_ONGOING_HI 15
++#define SCRT_PKT_CLS_ONGOING_SZ 1
++#define MISC_PKT_CLS_MIB_EN_MSK 0x00010000
++#define MISC_PKT_CLS_MIB_EN_I_MSK 0xfffeffff
++#define MISC_PKT_CLS_MIB_EN_SFT 16
++#define MISC_PKT_CLS_MIB_EN_HI 16
++#define MISC_PKT_CLS_MIB_EN_SZ 1
++#define MISC_PKT_CLS_ONGOING_MSK 0x00020000
++#define MISC_PKT_CLS_ONGOING_I_MSK 0xfffdffff
++#define MISC_PKT_CLS_ONGOING_SFT 17
++#define MISC_PKT_CLS_ONGOING_HI 17
++#define MISC_PKT_CLS_ONGOING_SZ 1
++#define MTX_WSID0_SUCC_MSK 0x0000ffff
++#define MTX_WSID0_SUCC_I_MSK 0xffff0000
++#define MTX_WSID0_SUCC_SFT 0
++#define MTX_WSID0_SUCC_HI 15
++#define MTX_WSID0_SUCC_SZ 16
++#define MTX_WSID0_FRM_MSK 0x0000ffff
++#define MTX_WSID0_FRM_I_MSK 0xffff0000
++#define MTX_WSID0_FRM_SFT 0
++#define MTX_WSID0_FRM_HI 15
++#define MTX_WSID0_FRM_SZ 16
++#define MTX_WSID0_RETRY_MSK 0x0000ffff
++#define MTX_WSID0_RETRY_I_MSK 0xffff0000
++#define MTX_WSID0_RETRY_SFT 0
++#define MTX_WSID0_RETRY_HI 15
++#define MTX_WSID0_RETRY_SZ 16
++#define MTX_WSID0_TOTAL_MSK 0x0000ffff
++#define MTX_WSID0_TOTAL_I_MSK 0xffff0000
++#define MTX_WSID0_TOTAL_SFT 0
++#define MTX_WSID0_TOTAL_HI 15
++#define MTX_WSID0_TOTAL_SZ 16
++#define MTX_GRP_MSK 0x000fffff
++#define MTX_GRP_I_MSK 0xfff00000
++#define MTX_GRP_SFT 0
++#define MTX_GRP_HI 19
++#define MTX_GRP_SZ 20
++#define MTX_FAIL_MSK 0x0000ffff
++#define MTX_FAIL_I_MSK 0xffff0000
++#define MTX_FAIL_SFT 0
++#define MTX_FAIL_HI 15
++#define MTX_FAIL_SZ 16
++#define MTX_RETRY_MSK 0x000fffff
++#define MTX_RETRY_I_MSK 0xfff00000
++#define MTX_RETRY_SFT 0
++#define MTX_RETRY_HI 19
++#define MTX_RETRY_SZ 20
++#define MTX_MULTI_RETRY_MSK 0x000fffff
++#define MTX_MULTI_RETRY_I_MSK 0xfff00000
++#define MTX_MULTI_RETRY_SFT 0
++#define MTX_MULTI_RETRY_HI 19
++#define MTX_MULTI_RETRY_SZ 20
++#define MTX_RTS_SUCC_MSK 0x0000ffff
++#define MTX_RTS_SUCC_I_MSK 0xffff0000
++#define MTX_RTS_SUCC_SFT 0
++#define MTX_RTS_SUCC_HI 15
++#define MTX_RTS_SUCC_SZ 16
++#define MTX_RTS_FAIL_MSK 0x0000ffff
++#define MTX_RTS_FAIL_I_MSK 0xffff0000
++#define MTX_RTS_FAIL_SFT 0
++#define MTX_RTS_FAIL_HI 15
++#define MTX_RTS_FAIL_SZ 16
++#define MTX_ACK_FAIL_MSK 0x0000ffff
++#define MTX_ACK_FAIL_I_MSK 0xffff0000
++#define MTX_ACK_FAIL_SFT 0
++#define MTX_ACK_FAIL_HI 15
++#define MTX_ACK_FAIL_SZ 16
++#define MTX_FRM_MSK 0x000fffff
++#define MTX_FRM_I_MSK 0xfff00000
++#define MTX_FRM_SFT 0
++#define MTX_FRM_HI 19
++#define MTX_FRM_SZ 20
++#define MTX_ACK_TX_MSK 0x0000ffff
++#define MTX_ACK_TX_I_MSK 0xffff0000
++#define MTX_ACK_TX_SFT 0
++#define MTX_ACK_TX_HI 15
++#define MTX_ACK_TX_SZ 16
++#define MTX_CTS_TX_MSK 0x0000ffff
++#define MTX_CTS_TX_I_MSK 0xffff0000
++#define MTX_CTS_TX_SFT 0
++#define MTX_CTS_TX_HI 15
++#define MTX_CTS_TX_SZ 16
++#define MRX_DUP_MSK 0x0000ffff
++#define MRX_DUP_I_MSK 0xffff0000
++#define MRX_DUP_SFT 0
++#define MRX_DUP_HI 15
++#define MRX_DUP_SZ 16
++#define MRX_FRG_MSK 0x000fffff
++#define MRX_FRG_I_MSK 0xfff00000
++#define MRX_FRG_SFT 0
++#define MRX_FRG_HI 19
++#define MRX_FRG_SZ 20
++#define MRX_GRP_MSK 0x000fffff
++#define MRX_GRP_I_MSK 0xfff00000
++#define MRX_GRP_SFT 0
++#define MRX_GRP_HI 19
++#define MRX_GRP_SZ 20
++#define MRX_FCS_ERR_MSK 0x0000ffff
++#define MRX_FCS_ERR_I_MSK 0xffff0000
++#define MRX_FCS_ERR_SFT 0
++#define MRX_FCS_ERR_HI 15
++#define MRX_FCS_ERR_SZ 16
++#define MRX_FCS_SUC_MSK 0x0000ffff
++#define MRX_FCS_SUC_I_MSK 0xffff0000
++#define MRX_FCS_SUC_SFT 0
++#define MRX_FCS_SUC_HI 15
++#define MRX_FCS_SUC_SZ 16
++#define MRX_MISS_MSK 0x0000ffff
++#define MRX_MISS_I_MSK 0xffff0000
++#define MRX_MISS_SFT 0
++#define MRX_MISS_HI 15
++#define MRX_MISS_SZ 16
++#define MRX_ALC_FAIL_MSK 0x0000ffff
++#define MRX_ALC_FAIL_I_MSK 0xffff0000
++#define MRX_ALC_FAIL_SFT 0
++#define MRX_ALC_FAIL_HI 15
++#define MRX_ALC_FAIL_SZ 16
++#define MRX_DAT_NTF_MSK 0x0000ffff
++#define MRX_DAT_NTF_I_MSK 0xffff0000
++#define MRX_DAT_NTF_SFT 0
++#define MRX_DAT_NTF_HI 15
++#define MRX_DAT_NTF_SZ 16
++#define MRX_RTS_NTF_MSK 0x0000ffff
++#define MRX_RTS_NTF_I_MSK 0xffff0000
++#define MRX_RTS_NTF_SFT 0
++#define MRX_RTS_NTF_HI 15
++#define MRX_RTS_NTF_SZ 16
++#define MRX_CTS_NTF_MSK 0x0000ffff
++#define MRX_CTS_NTF_I_MSK 0xffff0000
++#define MRX_CTS_NTF_SFT 0
++#define MRX_CTS_NTF_HI 15
++#define MRX_CTS_NTF_SZ 16
++#define MRX_ACK_NTF_MSK 0x0000ffff
++#define MRX_ACK_NTF_I_MSK 0xffff0000
++#define MRX_ACK_NTF_SFT 0
++#define MRX_ACK_NTF_HI 15
++#define MRX_ACK_NTF_SZ 16
++#define MRX_BA_NTF_MSK 0x0000ffff
++#define MRX_BA_NTF_I_MSK 0xffff0000
++#define MRX_BA_NTF_SFT 0
++#define MRX_BA_NTF_HI 15
++#define MRX_BA_NTF_SZ 16
++#define MRX_DATA_NTF_MSK 0x0000ffff
++#define MRX_DATA_NTF_I_MSK 0xffff0000
++#define MRX_DATA_NTF_SFT 0
++#define MRX_DATA_NTF_HI 15
++#define MRX_DATA_NTF_SZ 16
++#define MRX_MNG_NTF_MSK 0x0000ffff
++#define MRX_MNG_NTF_I_MSK 0xffff0000
++#define MRX_MNG_NTF_SFT 0
++#define MRX_MNG_NTF_HI 15
++#define MRX_MNG_NTF_SZ 16
++#define MRX_DAT_CRC_NTF_MSK 0x0000ffff
++#define MRX_DAT_CRC_NTF_I_MSK 0xffff0000
++#define MRX_DAT_CRC_NTF_SFT 0
++#define MRX_DAT_CRC_NTF_HI 15
++#define MRX_DAT_CRC_NTF_SZ 16
++#define MRX_BAR_NTF_MSK 0x0000ffff
++#define MRX_BAR_NTF_I_MSK 0xffff0000
++#define MRX_BAR_NTF_SFT 0
++#define MRX_BAR_NTF_HI 15
++#define MRX_BAR_NTF_SZ 16
++#define MRX_MB_MISS_MSK 0x0000ffff
++#define MRX_MB_MISS_I_MSK 0xffff0000
++#define MRX_MB_MISS_SFT 0
++#define MRX_MB_MISS_HI 15
++#define MRX_MB_MISS_SZ 16
++#define MRX_NIDLE_MISS_MSK 0x0000ffff
++#define MRX_NIDLE_MISS_I_MSK 0xffff0000
++#define MRX_NIDLE_MISS_SFT 0
++#define MRX_NIDLE_MISS_HI 15
++#define MRX_NIDLE_MISS_SZ 16
++#define MRX_CSR_NTF_MSK 0x0000ffff
++#define MRX_CSR_NTF_I_MSK 0xffff0000
++#define MRX_CSR_NTF_SFT 0
++#define MRX_CSR_NTF_HI 15
++#define MRX_CSR_NTF_SZ 16
++#define DBG_Q0_SUCC_MSK 0x0000ffff
++#define DBG_Q0_SUCC_I_MSK 0xffff0000
++#define DBG_Q0_SUCC_SFT 0
++#define DBG_Q0_SUCC_HI 15
++#define DBG_Q0_SUCC_SZ 16
++#define DBG_Q0_FAIL_MSK 0x0000ffff
++#define DBG_Q0_FAIL_I_MSK 0xffff0000
++#define DBG_Q0_FAIL_SFT 0
++#define DBG_Q0_FAIL_HI 15
++#define DBG_Q0_FAIL_SZ 16
++#define DBG_Q0_ACK_SUCC_MSK 0x0000ffff
++#define DBG_Q0_ACK_SUCC_I_MSK 0xffff0000
++#define DBG_Q0_ACK_SUCC_SFT 0
++#define DBG_Q0_ACK_SUCC_HI 15
++#define DBG_Q0_ACK_SUCC_SZ 16
++#define DBG_Q0_ACK_FAIL_MSK 0x0000ffff
++#define DBG_Q0_ACK_FAIL_I_MSK 0xffff0000
++#define DBG_Q0_ACK_FAIL_SFT 0
++#define DBG_Q0_ACK_FAIL_HI 15
++#define DBG_Q0_ACK_FAIL_SZ 16
++#define DBG_Q1_SUCC_MSK 0x0000ffff
++#define DBG_Q1_SUCC_I_MSK 0xffff0000
++#define DBG_Q1_SUCC_SFT 0
++#define DBG_Q1_SUCC_HI 15
++#define DBG_Q1_SUCC_SZ 16
++#define DBG_Q1_FAIL_MSK 0x0000ffff
++#define DBG_Q1_FAIL_I_MSK 0xffff0000
++#define DBG_Q1_FAIL_SFT 0
++#define DBG_Q1_FAIL_HI 15
++#define DBG_Q1_FAIL_SZ 16
++#define DBG_Q1_ACK_SUCC_MSK 0x0000ffff
++#define DBG_Q1_ACK_SUCC_I_MSK 0xffff0000
++#define DBG_Q1_ACK_SUCC_SFT 0
++#define DBG_Q1_ACK_SUCC_HI 15
++#define DBG_Q1_ACK_SUCC_SZ 16
++#define DBG_Q1_ACK_FAIL_MSK 0x0000ffff
++#define DBG_Q1_ACK_FAIL_I_MSK 0xffff0000
++#define DBG_Q1_ACK_FAIL_SFT 0
++#define DBG_Q1_ACK_FAIL_HI 15
++#define DBG_Q1_ACK_FAIL_SZ 16
++#define DBG_Q2_SUCC_MSK 0x0000ffff
++#define DBG_Q2_SUCC_I_MSK 0xffff0000
++#define DBG_Q2_SUCC_SFT 0
++#define DBG_Q2_SUCC_HI 15
++#define DBG_Q2_SUCC_SZ 16
++#define DBG_Q2_FAIL_MSK 0x0000ffff
++#define DBG_Q2_FAIL_I_MSK 0xffff0000
++#define DBG_Q2_FAIL_SFT 0
++#define DBG_Q2_FAIL_HI 15
++#define DBG_Q2_FAIL_SZ 16
++#define DBG_Q2_ACK_SUCC_MSK 0x0000ffff
++#define DBG_Q2_ACK_SUCC_I_MSK 0xffff0000
++#define DBG_Q2_ACK_SUCC_SFT 0
++#define DBG_Q2_ACK_SUCC_HI 15
++#define DBG_Q2_ACK_SUCC_SZ 16
++#define DBG_Q2_ACK_FAIL_MSK 0x0000ffff
++#define DBG_Q2_ACK_FAIL_I_MSK 0xffff0000
++#define DBG_Q2_ACK_FAIL_SFT 0
++#define DBG_Q2_ACK_FAIL_HI 15
++#define DBG_Q2_ACK_FAIL_SZ 16
++#define DBG_Q3_SUCC_MSK 0x0000ffff
++#define DBG_Q3_SUCC_I_MSK 0xffff0000
++#define DBG_Q3_SUCC_SFT 0
++#define DBG_Q3_SUCC_HI 15
++#define DBG_Q3_SUCC_SZ 16
++#define DBG_Q3_FAIL_MSK 0x0000ffff
++#define DBG_Q3_FAIL_I_MSK 0xffff0000
++#define DBG_Q3_FAIL_SFT 0
++#define DBG_Q3_FAIL_HI 15
++#define DBG_Q3_FAIL_SZ 16
++#define DBG_Q3_ACK_SUCC_MSK 0x0000ffff
++#define DBG_Q3_ACK_SUCC_I_MSK 0xffff0000
++#define DBG_Q3_ACK_SUCC_SFT 0
++#define DBG_Q3_ACK_SUCC_HI 15
++#define DBG_Q3_ACK_SUCC_SZ 16
++#define DBG_Q3_ACK_FAIL_MSK 0x0000ffff
++#define DBG_Q3_ACK_FAIL_I_MSK 0xffff0000
++#define DBG_Q3_ACK_FAIL_SFT 0
++#define DBG_Q3_ACK_FAIL_HI 15
++#define DBG_Q3_ACK_FAIL_SZ 16
++#define SCRT_TKIP_CERR_MSK 0x000fffff
++#define SCRT_TKIP_CERR_I_MSK 0xfff00000
++#define SCRT_TKIP_CERR_SFT 0
++#define SCRT_TKIP_CERR_HI 19
++#define SCRT_TKIP_CERR_SZ 20
++#define SCRT_TKIP_MIC_ERR_MSK 0x000fffff
++#define SCRT_TKIP_MIC_ERR_I_MSK 0xfff00000
++#define SCRT_TKIP_MIC_ERR_SFT 0
++#define SCRT_TKIP_MIC_ERR_HI 19
++#define SCRT_TKIP_MIC_ERR_SZ 20
++#define SCRT_TKIP_RPLY_MSK 0x000fffff
++#define SCRT_TKIP_RPLY_I_MSK 0xfff00000
++#define SCRT_TKIP_RPLY_SFT 0
++#define SCRT_TKIP_RPLY_HI 19
++#define SCRT_TKIP_RPLY_SZ 20
++#define SCRT_CCMP_RPLY_MSK 0x000fffff
++#define SCRT_CCMP_RPLY_I_MSK 0xfff00000
++#define SCRT_CCMP_RPLY_SFT 0
++#define SCRT_CCMP_RPLY_HI 19
++#define SCRT_CCMP_RPLY_SZ 20
++#define SCRT_CCMP_CERR_MSK 0x000fffff
++#define SCRT_CCMP_CERR_I_MSK 0xfff00000
++#define SCRT_CCMP_CERR_SFT 0
++#define SCRT_CCMP_CERR_HI 19
++#define SCRT_CCMP_CERR_SZ 20
++#define DBG_LEN_CRC_FAIL_MSK 0x0000ffff
++#define DBG_LEN_CRC_FAIL_I_MSK 0xffff0000
++#define DBG_LEN_CRC_FAIL_SFT 0
++#define DBG_LEN_CRC_FAIL_HI 15
++#define DBG_LEN_CRC_FAIL_SZ 16
++#define DBG_LEN_ALC_FAIL_MSK 0x0000ffff
++#define DBG_LEN_ALC_FAIL_I_MSK 0xffff0000
++#define DBG_LEN_ALC_FAIL_SFT 0
++#define DBG_LEN_ALC_FAIL_HI 15
++#define DBG_LEN_ALC_FAIL_SZ 16
++#define DBG_AMPDU_PASS_MSK 0x0000ffff
++#define DBG_AMPDU_PASS_I_MSK 0xffff0000
++#define DBG_AMPDU_PASS_SFT 0
++#define DBG_AMPDU_PASS_HI 15
++#define DBG_AMPDU_PASS_SZ 16
++#define DBG_AMPDU_FAIL_MSK 0x0000ffff
++#define DBG_AMPDU_FAIL_I_MSK 0xffff0000
++#define DBG_AMPDU_FAIL_SFT 0
++#define DBG_AMPDU_FAIL_HI 15
++#define DBG_AMPDU_FAIL_SZ 16
++#define RXID_ALC_CNT_FAIL_MSK 0x0000ffff
++#define RXID_ALC_CNT_FAIL_I_MSK 0xffff0000
++#define RXID_ALC_CNT_FAIL_SFT 0
++#define RXID_ALC_CNT_FAIL_HI 15
++#define RXID_ALC_CNT_FAIL_SZ 16
++#define RXID_ALC_LEN_FAIL_MSK 0x0000ffff
++#define RXID_ALC_LEN_FAIL_I_MSK 0xffff0000
++#define RXID_ALC_LEN_FAIL_SFT 0
++#define RXID_ALC_LEN_FAIL_HI 15
++#define RXID_ALC_LEN_FAIL_SZ 16
++#define CBR_RG_EN_MANUAL_MSK 0x00000001
++#define CBR_RG_EN_MANUAL_I_MSK 0xfffffffe
++#define CBR_RG_EN_MANUAL_SFT 0
++#define CBR_RG_EN_MANUAL_HI 0
++#define CBR_RG_EN_MANUAL_SZ 1
++#define CBR_RG_TX_EN_MSK 0x00000002
++#define CBR_RG_TX_EN_I_MSK 0xfffffffd
++#define CBR_RG_TX_EN_SFT 1
++#define CBR_RG_TX_EN_HI 1
++#define CBR_RG_TX_EN_SZ 1
++#define CBR_RG_TX_PA_EN_MSK 0x00000004
++#define CBR_RG_TX_PA_EN_I_MSK 0xfffffffb
++#define CBR_RG_TX_PA_EN_SFT 2
++#define CBR_RG_TX_PA_EN_HI 2
++#define CBR_RG_TX_PA_EN_SZ 1
++#define CBR_RG_TX_DAC_EN_MSK 0x00000008
++#define CBR_RG_TX_DAC_EN_I_MSK 0xfffffff7
++#define CBR_RG_TX_DAC_EN_SFT 3
++#define CBR_RG_TX_DAC_EN_HI 3
++#define CBR_RG_TX_DAC_EN_SZ 1
++#define CBR_RG_RX_AGC_MSK 0x00000010
++#define CBR_RG_RX_AGC_I_MSK 0xffffffef
++#define CBR_RG_RX_AGC_SFT 4
++#define CBR_RG_RX_AGC_HI 4
++#define CBR_RG_RX_AGC_SZ 1
++#define CBR_RG_RX_GAIN_MANUAL_MSK 0x00000020
++#define CBR_RG_RX_GAIN_MANUAL_I_MSK 0xffffffdf
++#define CBR_RG_RX_GAIN_MANUAL_SFT 5
++#define CBR_RG_RX_GAIN_MANUAL_HI 5
++#define CBR_RG_RX_GAIN_MANUAL_SZ 1
++#define CBR_RG_RFG_MSK 0x000000c0
++#define CBR_RG_RFG_I_MSK 0xffffff3f
++#define CBR_RG_RFG_SFT 6
++#define CBR_RG_RFG_HI 7
++#define CBR_RG_RFG_SZ 2
++#define CBR_RG_PGAG_MSK 0x00000f00
++#define CBR_RG_PGAG_I_MSK 0xfffff0ff
++#define CBR_RG_PGAG_SFT 8
++#define CBR_RG_PGAG_HI 11
++#define CBR_RG_PGAG_SZ 4
++#define CBR_RG_MODE_MSK 0x00003000
++#define CBR_RG_MODE_I_MSK 0xffffcfff
++#define CBR_RG_MODE_SFT 12
++#define CBR_RG_MODE_HI 13
++#define CBR_RG_MODE_SZ 2
++#define CBR_RG_EN_TX_TRSW_MSK 0x00004000
++#define CBR_RG_EN_TX_TRSW_I_MSK 0xffffbfff
++#define CBR_RG_EN_TX_TRSW_SFT 14
++#define CBR_RG_EN_TX_TRSW_HI 14
++#define CBR_RG_EN_TX_TRSW_SZ 1
++#define CBR_RG_EN_SX_MSK 0x00008000
++#define CBR_RG_EN_SX_I_MSK 0xffff7fff
++#define CBR_RG_EN_SX_SFT 15
++#define CBR_RG_EN_SX_HI 15
++#define CBR_RG_EN_SX_SZ 1
++#define CBR_RG_EN_RX_LNA_MSK 0x00010000
++#define CBR_RG_EN_RX_LNA_I_MSK 0xfffeffff
++#define CBR_RG_EN_RX_LNA_SFT 16
++#define CBR_RG_EN_RX_LNA_HI 16
++#define CBR_RG_EN_RX_LNA_SZ 1
++#define CBR_RG_EN_RX_MIXER_MSK 0x00020000
++#define CBR_RG_EN_RX_MIXER_I_MSK 0xfffdffff
++#define CBR_RG_EN_RX_MIXER_SFT 17
++#define CBR_RG_EN_RX_MIXER_HI 17
++#define CBR_RG_EN_RX_MIXER_SZ 1
++#define CBR_RG_EN_RX_DIV2_MSK 0x00040000
++#define CBR_RG_EN_RX_DIV2_I_MSK 0xfffbffff
++#define CBR_RG_EN_RX_DIV2_SFT 18
++#define CBR_RG_EN_RX_DIV2_HI 18
++#define CBR_RG_EN_RX_DIV2_SZ 1
++#define CBR_RG_EN_RX_LOBUF_MSK 0x00080000
++#define CBR_RG_EN_RX_LOBUF_I_MSK 0xfff7ffff
++#define CBR_RG_EN_RX_LOBUF_SFT 19
++#define CBR_RG_EN_RX_LOBUF_HI 19
++#define CBR_RG_EN_RX_LOBUF_SZ 1
++#define CBR_RG_EN_RX_TZ_MSK 0x00100000
++#define CBR_RG_EN_RX_TZ_I_MSK 0xffefffff
++#define CBR_RG_EN_RX_TZ_SFT 20
++#define CBR_RG_EN_RX_TZ_HI 20
++#define CBR_RG_EN_RX_TZ_SZ 1
++#define CBR_RG_EN_RX_FILTER_MSK 0x00200000
++#define CBR_RG_EN_RX_FILTER_I_MSK 0xffdfffff
++#define CBR_RG_EN_RX_FILTER_SFT 21
++#define CBR_RG_EN_RX_FILTER_HI 21
++#define CBR_RG_EN_RX_FILTER_SZ 1
++#define CBR_RG_EN_RX_HPF_MSK 0x00400000
++#define CBR_RG_EN_RX_HPF_I_MSK 0xffbfffff
++#define CBR_RG_EN_RX_HPF_SFT 22
++#define CBR_RG_EN_RX_HPF_HI 22
++#define CBR_RG_EN_RX_HPF_SZ 1
++#define CBR_RG_EN_RX_RSSI_MSK 0x00800000
++#define CBR_RG_EN_RX_RSSI_I_MSK 0xff7fffff
++#define CBR_RG_EN_RX_RSSI_SFT 23
++#define CBR_RG_EN_RX_RSSI_HI 23
++#define CBR_RG_EN_RX_RSSI_SZ 1
++#define CBR_RG_EN_ADC_MSK 0x01000000
++#define CBR_RG_EN_ADC_I_MSK 0xfeffffff
++#define CBR_RG_EN_ADC_SFT 24
++#define CBR_RG_EN_ADC_HI 24
++#define CBR_RG_EN_ADC_SZ 1
++#define CBR_RG_EN_TX_MOD_MSK 0x02000000
++#define CBR_RG_EN_TX_MOD_I_MSK 0xfdffffff
++#define CBR_RG_EN_TX_MOD_SFT 25
++#define CBR_RG_EN_TX_MOD_HI 25
++#define CBR_RG_EN_TX_MOD_SZ 1
++#define CBR_RG_EN_TX_DIV2_MSK 0x04000000
++#define CBR_RG_EN_TX_DIV2_I_MSK 0xfbffffff
++#define CBR_RG_EN_TX_DIV2_SFT 26
++#define CBR_RG_EN_TX_DIV2_HI 26
++#define CBR_RG_EN_TX_DIV2_SZ 1
++#define CBR_RG_EN_TX_DIV2_BUF_MSK 0x08000000
++#define CBR_RG_EN_TX_DIV2_BUF_I_MSK 0xf7ffffff
++#define CBR_RG_EN_TX_DIV2_BUF_SFT 27
++#define CBR_RG_EN_TX_DIV2_BUF_HI 27
++#define CBR_RG_EN_TX_DIV2_BUF_SZ 1
++#define CBR_RG_EN_TX_LOBF_MSK 0x10000000
++#define CBR_RG_EN_TX_LOBF_I_MSK 0xefffffff
++#define CBR_RG_EN_TX_LOBF_SFT 28
++#define CBR_RG_EN_TX_LOBF_HI 28
++#define CBR_RG_EN_TX_LOBF_SZ 1
++#define CBR_RG_EN_RX_LOBF_MSK 0x20000000
++#define CBR_RG_EN_RX_LOBF_I_MSK 0xdfffffff
++#define CBR_RG_EN_RX_LOBF_SFT 29
++#define CBR_RG_EN_RX_LOBF_HI 29
++#define CBR_RG_EN_RX_LOBF_SZ 1
++#define CBR_RG_SEL_DPLL_CLK_MSK 0x40000000
++#define CBR_RG_SEL_DPLL_CLK_I_MSK 0xbfffffff
++#define CBR_RG_SEL_DPLL_CLK_SFT 30
++#define CBR_RG_SEL_DPLL_CLK_HI 30
++#define CBR_RG_SEL_DPLL_CLK_SZ 1
++#define CBR_RG_EN_TX_DPD_MSK 0x00000001
++#define CBR_RG_EN_TX_DPD_I_MSK 0xfffffffe
++#define CBR_RG_EN_TX_DPD_SFT 0
++#define CBR_RG_EN_TX_DPD_HI 0
++#define CBR_RG_EN_TX_DPD_SZ 1
++#define CBR_RG_EN_TX_TSSI_MSK 0x00000002
++#define CBR_RG_EN_TX_TSSI_I_MSK 0xfffffffd
++#define CBR_RG_EN_TX_TSSI_SFT 1
++#define CBR_RG_EN_TX_TSSI_HI 1
++#define CBR_RG_EN_TX_TSSI_SZ 1
++#define CBR_RG_EN_RX_IQCAL_MSK 0x00000004
++#define CBR_RG_EN_RX_IQCAL_I_MSK 0xfffffffb
++#define CBR_RG_EN_RX_IQCAL_SFT 2
++#define CBR_RG_EN_RX_IQCAL_HI 2
++#define CBR_RG_EN_RX_IQCAL_SZ 1
++#define CBR_RG_EN_TX_DAC_CAL_MSK 0x00000008
++#define CBR_RG_EN_TX_DAC_CAL_I_MSK 0xfffffff7
++#define CBR_RG_EN_TX_DAC_CAL_SFT 3
++#define CBR_RG_EN_TX_DAC_CAL_HI 3
++#define CBR_RG_EN_TX_DAC_CAL_SZ 1
++#define CBR_RG_EN_TX_SELF_MIXER_MSK 0x00000010
++#define CBR_RG_EN_TX_SELF_MIXER_I_MSK 0xffffffef
++#define CBR_RG_EN_TX_SELF_MIXER_SFT 4
++#define CBR_RG_EN_TX_SELF_MIXER_HI 4
++#define CBR_RG_EN_TX_SELF_MIXER_SZ 1
++#define CBR_RG_EN_TX_DAC_OUT_MSK 0x00000020
++#define CBR_RG_EN_TX_DAC_OUT_I_MSK 0xffffffdf
++#define CBR_RG_EN_TX_DAC_OUT_SFT 5
++#define CBR_RG_EN_TX_DAC_OUT_HI 5
++#define CBR_RG_EN_TX_DAC_OUT_SZ 1
++#define CBR_RG_EN_LDO_RX_FE_MSK 0x00000040
++#define CBR_RG_EN_LDO_RX_FE_I_MSK 0xffffffbf
++#define CBR_RG_EN_LDO_RX_FE_SFT 6
++#define CBR_RG_EN_LDO_RX_FE_HI 6
++#define CBR_RG_EN_LDO_RX_FE_SZ 1
++#define CBR_RG_EN_LDO_ABB_MSK 0x00000080
++#define CBR_RG_EN_LDO_ABB_I_MSK 0xffffff7f
++#define CBR_RG_EN_LDO_ABB_SFT 7
++#define CBR_RG_EN_LDO_ABB_HI 7
++#define CBR_RG_EN_LDO_ABB_SZ 1
++#define CBR_RG_EN_LDO_AFE_MSK 0x00000100
++#define CBR_RG_EN_LDO_AFE_I_MSK 0xfffffeff
++#define CBR_RG_EN_LDO_AFE_SFT 8
++#define CBR_RG_EN_LDO_AFE_HI 8
++#define CBR_RG_EN_LDO_AFE_SZ 1
++#define CBR_RG_EN_SX_CHPLDO_MSK 0x00000200
++#define CBR_RG_EN_SX_CHPLDO_I_MSK 0xfffffdff
++#define CBR_RG_EN_SX_CHPLDO_SFT 9
++#define CBR_RG_EN_SX_CHPLDO_HI 9
++#define CBR_RG_EN_SX_CHPLDO_SZ 1
++#define CBR_RG_EN_SX_LOBFLDO_MSK 0x00000400
++#define CBR_RG_EN_SX_LOBFLDO_I_MSK 0xfffffbff
++#define CBR_RG_EN_SX_LOBFLDO_SFT 10
++#define CBR_RG_EN_SX_LOBFLDO_HI 10
++#define CBR_RG_EN_SX_LOBFLDO_SZ 1
++#define CBR_RG_EN_IREF_RX_MSK 0x00000800
++#define CBR_RG_EN_IREF_RX_I_MSK 0xfffff7ff
++#define CBR_RG_EN_IREF_RX_SFT 11
++#define CBR_RG_EN_IREF_RX_HI 11
++#define CBR_RG_EN_IREF_RX_SZ 1
++#define CBR_RG_DCDC_MODE_MSK 0x00001000
++#define CBR_RG_DCDC_MODE_I_MSK 0xffffefff
++#define CBR_RG_DCDC_MODE_SFT 12
++#define CBR_RG_DCDC_MODE_HI 12
++#define CBR_RG_DCDC_MODE_SZ 1
++#define CBR_RG_LDO_LEVEL_RX_FE_MSK 0x00000007
++#define CBR_RG_LDO_LEVEL_RX_FE_I_MSK 0xfffffff8
++#define CBR_RG_LDO_LEVEL_RX_FE_SFT 0
++#define CBR_RG_LDO_LEVEL_RX_FE_HI 2
++#define CBR_RG_LDO_LEVEL_RX_FE_SZ 3
++#define CBR_RG_LDO_LEVEL_ABB_MSK 0x00000038
++#define CBR_RG_LDO_LEVEL_ABB_I_MSK 0xffffffc7
++#define CBR_RG_LDO_LEVEL_ABB_SFT 3
++#define CBR_RG_LDO_LEVEL_ABB_HI 5
++#define CBR_RG_LDO_LEVEL_ABB_SZ 3
++#define CBR_RG_LDO_LEVEL_AFE_MSK 0x000001c0
++#define CBR_RG_LDO_LEVEL_AFE_I_MSK 0xfffffe3f
++#define CBR_RG_LDO_LEVEL_AFE_SFT 6
++#define CBR_RG_LDO_LEVEL_AFE_HI 8
++#define CBR_RG_LDO_LEVEL_AFE_SZ 3
++#define CBR_RG_SX_LDO_CHP_LEVEL_MSK 0x00000e00
++#define CBR_RG_SX_LDO_CHP_LEVEL_I_MSK 0xfffff1ff
++#define CBR_RG_SX_LDO_CHP_LEVEL_SFT 9
++#define CBR_RG_SX_LDO_CHP_LEVEL_HI 11
++#define CBR_RG_SX_LDO_CHP_LEVEL_SZ 3
++#define CBR_RG_SX_LDO_LOBF_LEVEL_MSK 0x00007000
++#define CBR_RG_SX_LDO_LOBF_LEVEL_I_MSK 0xffff8fff
++#define CBR_RG_SX_LDO_LOBF_LEVEL_SFT 12
++#define CBR_RG_SX_LDO_LOBF_LEVEL_HI 14
++#define CBR_RG_SX_LDO_LOBF_LEVEL_SZ 3
++#define CBR_RG_SX_LDO_XOSC_LEVEL_MSK 0x00038000
++#define CBR_RG_SX_LDO_XOSC_LEVEL_I_MSK 0xfffc7fff
++#define CBR_RG_SX_LDO_XOSC_LEVEL_SFT 15
++#define CBR_RG_SX_LDO_XOSC_LEVEL_HI 17
++#define CBR_RG_SX_LDO_XOSC_LEVEL_SZ 3
++#define CBR_RG_DP_LDO_LEVEL_MSK 0x001c0000
++#define CBR_RG_DP_LDO_LEVEL_I_MSK 0xffe3ffff
++#define CBR_RG_DP_LDO_LEVEL_SFT 18
++#define CBR_RG_DP_LDO_LEVEL_HI 20
++#define CBR_RG_DP_LDO_LEVEL_SZ 3
++#define CBR_RG_SX_LDO_VCO_LEVEL_MSK 0x00e00000
++#define CBR_RG_SX_LDO_VCO_LEVEL_I_MSK 0xff1fffff
++#define CBR_RG_SX_LDO_VCO_LEVEL_SFT 21
++#define CBR_RG_SX_LDO_VCO_LEVEL_HI 23
++#define CBR_RG_SX_LDO_VCO_LEVEL_SZ 3
++#define CBR_RG_TX_LDO_TX_LEVEL_MSK 0x07000000
++#define CBR_RG_TX_LDO_TX_LEVEL_I_MSK 0xf8ffffff
++#define CBR_RG_TX_LDO_TX_LEVEL_SFT 24
++#define CBR_RG_TX_LDO_TX_LEVEL_HI 26
++#define CBR_RG_TX_LDO_TX_LEVEL_SZ 3
++#define CBR_RG_BUCK_LEVEL_MSK 0x38000000
++#define CBR_RG_BUCK_LEVEL_I_MSK 0xc7ffffff
++#define CBR_RG_BUCK_LEVEL_SFT 27
++#define CBR_RG_BUCK_LEVEL_HI 29
++#define CBR_RG_BUCK_LEVEL_SZ 3
++#define CBR_RG_EN_RX_PADSW_MSK 0x00000001
++#define CBR_RG_EN_RX_PADSW_I_MSK 0xfffffffe
++#define CBR_RG_EN_RX_PADSW_SFT 0
++#define CBR_RG_EN_RX_PADSW_HI 0
++#define CBR_RG_EN_RX_PADSW_SZ 1
++#define CBR_RG_EN_RX_TESTNODE_MSK 0x00000002
++#define CBR_RG_EN_RX_TESTNODE_I_MSK 0xfffffffd
++#define CBR_RG_EN_RX_TESTNODE_SFT 1
++#define CBR_RG_EN_RX_TESTNODE_HI 1
++#define CBR_RG_EN_RX_TESTNODE_SZ 1
++#define CBR_RG_RX_ABBCFIX_MSK 0x00000004
++#define CBR_RG_RX_ABBCFIX_I_MSK 0xfffffffb
++#define CBR_RG_RX_ABBCFIX_SFT 2
++#define CBR_RG_RX_ABBCFIX_HI 2
++#define CBR_RG_RX_ABBCFIX_SZ 1
++#define CBR_RG_RX_ABBCTUNE_MSK 0x000001f8
++#define CBR_RG_RX_ABBCTUNE_I_MSK 0xfffffe07
++#define CBR_RG_RX_ABBCTUNE_SFT 3
++#define CBR_RG_RX_ABBCTUNE_HI 8
++#define CBR_RG_RX_ABBCTUNE_SZ 6
++#define CBR_RG_RX_ABBOUT_TRI_STATE_MSK 0x00000200
++#define CBR_RG_RX_ABBOUT_TRI_STATE_I_MSK 0xfffffdff
++#define CBR_RG_RX_ABBOUT_TRI_STATE_SFT 9
++#define CBR_RG_RX_ABBOUT_TRI_STATE_HI 9
++#define CBR_RG_RX_ABBOUT_TRI_STATE_SZ 1
++#define CBR_RG_RX_ABB_N_MODE_MSK 0x00000400
++#define CBR_RG_RX_ABB_N_MODE_I_MSK 0xfffffbff
++#define CBR_RG_RX_ABB_N_MODE_SFT 10
++#define CBR_RG_RX_ABB_N_MODE_HI 10
++#define CBR_RG_RX_ABB_N_MODE_SZ 1
++#define CBR_RG_RX_EN_LOOPA_MSK 0x00000800
++#define CBR_RG_RX_EN_LOOPA_I_MSK 0xfffff7ff
++#define CBR_RG_RX_EN_LOOPA_SFT 11
++#define CBR_RG_RX_EN_LOOPA_HI 11
++#define CBR_RG_RX_EN_LOOPA_SZ 1
++#define CBR_RG_RX_FILTERI1ST_MSK 0x00003000
++#define CBR_RG_RX_FILTERI1ST_I_MSK 0xffffcfff
++#define CBR_RG_RX_FILTERI1ST_SFT 12
++#define CBR_RG_RX_FILTERI1ST_HI 13
++#define CBR_RG_RX_FILTERI1ST_SZ 2
++#define CBR_RG_RX_FILTERI2ND_MSK 0x0000c000
++#define CBR_RG_RX_FILTERI2ND_I_MSK 0xffff3fff
++#define CBR_RG_RX_FILTERI2ND_SFT 14
++#define CBR_RG_RX_FILTERI2ND_HI 15
++#define CBR_RG_RX_FILTERI2ND_SZ 2
++#define CBR_RG_RX_FILTERI3RD_MSK 0x00030000
++#define CBR_RG_RX_FILTERI3RD_I_MSK 0xfffcffff
++#define CBR_RG_RX_FILTERI3RD_SFT 16
++#define CBR_RG_RX_FILTERI3RD_HI 17
++#define CBR_RG_RX_FILTERI3RD_SZ 2
++#define CBR_RG_RX_FILTERI_COURSE_MSK 0x000c0000
++#define CBR_RG_RX_FILTERI_COURSE_I_MSK 0xfff3ffff
++#define CBR_RG_RX_FILTERI_COURSE_SFT 18
++#define CBR_RG_RX_FILTERI_COURSE_HI 19
++#define CBR_RG_RX_FILTERI_COURSE_SZ 2
++#define CBR_RG_RX_FILTERVCM_MSK 0x00300000
++#define CBR_RG_RX_FILTERVCM_I_MSK 0xffcfffff
++#define CBR_RG_RX_FILTERVCM_SFT 20
++#define CBR_RG_RX_FILTERVCM_HI 21
++#define CBR_RG_RX_FILTERVCM_SZ 2
++#define CBR_RG_RX_HPF3M_MSK 0x00400000
++#define CBR_RG_RX_HPF3M_I_MSK 0xffbfffff
++#define CBR_RG_RX_HPF3M_SFT 22
++#define CBR_RG_RX_HPF3M_HI 22
++#define CBR_RG_RX_HPF3M_SZ 1
++#define CBR_RG_RX_HPF300K_MSK 0x00800000
++#define CBR_RG_RX_HPF300K_I_MSK 0xff7fffff
++#define CBR_RG_RX_HPF300K_SFT 23
++#define CBR_RG_RX_HPF300K_HI 23
++#define CBR_RG_RX_HPF300K_SZ 1
++#define CBR_RG_RX_HPFI_MSK 0x03000000
++#define CBR_RG_RX_HPFI_I_MSK 0xfcffffff
++#define CBR_RG_RX_HPFI_SFT 24
++#define CBR_RG_RX_HPFI_HI 25
++#define CBR_RG_RX_HPFI_SZ 2
++#define CBR_RG_RX_HPF_FINALCORNER_MSK 0x0c000000
++#define CBR_RG_RX_HPF_FINALCORNER_I_MSK 0xf3ffffff
++#define CBR_RG_RX_HPF_FINALCORNER_SFT 26
++#define CBR_RG_RX_HPF_FINALCORNER_HI 27
++#define CBR_RG_RX_HPF_FINALCORNER_SZ 2
++#define CBR_RG_RX_HPF_SETTLE1_C_MSK 0x30000000
++#define CBR_RG_RX_HPF_SETTLE1_C_I_MSK 0xcfffffff
++#define CBR_RG_RX_HPF_SETTLE1_C_SFT 28
++#define CBR_RG_RX_HPF_SETTLE1_C_HI 29
++#define CBR_RG_RX_HPF_SETTLE1_C_SZ 2
++#define CBR_RG_RX_HPF_SETTLE1_R_MSK 0x00000003
++#define CBR_RG_RX_HPF_SETTLE1_R_I_MSK 0xfffffffc
++#define CBR_RG_RX_HPF_SETTLE1_R_SFT 0
++#define CBR_RG_RX_HPF_SETTLE1_R_HI 1
++#define CBR_RG_RX_HPF_SETTLE1_R_SZ 2
++#define CBR_RG_RX_HPF_SETTLE2_C_MSK 0x0000000c
++#define CBR_RG_RX_HPF_SETTLE2_C_I_MSK 0xfffffff3
++#define CBR_RG_RX_HPF_SETTLE2_C_SFT 2
++#define CBR_RG_RX_HPF_SETTLE2_C_HI 3
++#define CBR_RG_RX_HPF_SETTLE2_C_SZ 2
++#define CBR_RG_RX_HPF_SETTLE2_R_MSK 0x00000030
++#define CBR_RG_RX_HPF_SETTLE2_R_I_MSK 0xffffffcf
++#define CBR_RG_RX_HPF_SETTLE2_R_SFT 4
++#define CBR_RG_RX_HPF_SETTLE2_R_HI 5
++#define CBR_RG_RX_HPF_SETTLE2_R_SZ 2
++#define CBR_RG_RX_HPF_VCMCON2_MSK 0x000000c0
++#define CBR_RG_RX_HPF_VCMCON2_I_MSK 0xffffff3f
++#define CBR_RG_RX_HPF_VCMCON2_SFT 6
++#define CBR_RG_RX_HPF_VCMCON2_HI 7
++#define CBR_RG_RX_HPF_VCMCON2_SZ 2
++#define CBR_RG_RX_HPF_VCMCON_MSK 0x00000300
++#define CBR_RG_RX_HPF_VCMCON_I_MSK 0xfffffcff
++#define CBR_RG_RX_HPF_VCMCON_SFT 8
++#define CBR_RG_RX_HPF_VCMCON_HI 9
++#define CBR_RG_RX_HPF_VCMCON_SZ 2
++#define CBR_RG_RX_OUTVCM_MSK 0x00000c00
++#define CBR_RG_RX_OUTVCM_I_MSK 0xfffff3ff
++#define CBR_RG_RX_OUTVCM_SFT 10
++#define CBR_RG_RX_OUTVCM_HI 11
++#define CBR_RG_RX_OUTVCM_SZ 2
++#define CBR_RG_RX_TZI_MSK 0x00003000
++#define CBR_RG_RX_TZI_I_MSK 0xffffcfff
++#define CBR_RG_RX_TZI_SFT 12
++#define CBR_RG_RX_TZI_HI 13
++#define CBR_RG_RX_TZI_SZ 2
++#define CBR_RG_RX_TZ_OUT_TRISTATE_MSK 0x00004000
++#define CBR_RG_RX_TZ_OUT_TRISTATE_I_MSK 0xffffbfff
++#define CBR_RG_RX_TZ_OUT_TRISTATE_SFT 14
++#define CBR_RG_RX_TZ_OUT_TRISTATE_HI 14
++#define CBR_RG_RX_TZ_OUT_TRISTATE_SZ 1
++#define CBR_RG_RX_TZ_VCM_MSK 0x00018000
++#define CBR_RG_RX_TZ_VCM_I_MSK 0xfffe7fff
++#define CBR_RG_RX_TZ_VCM_SFT 15
++#define CBR_RG_RX_TZ_VCM_HI 16
++#define CBR_RG_RX_TZ_VCM_SZ 2
++#define CBR_RG_EN_RX_RSSI_TESTNODE_MSK 0x000e0000
++#define CBR_RG_EN_RX_RSSI_TESTNODE_I_MSK 0xfff1ffff
++#define CBR_RG_EN_RX_RSSI_TESTNODE_SFT 17
++#define CBR_RG_EN_RX_RSSI_TESTNODE_HI 19
++#define CBR_RG_EN_RX_RSSI_TESTNODE_SZ 3
++#define CBR_RG_RX_ADCRSSI_CLKSEL_MSK 0x00100000
++#define CBR_RG_RX_ADCRSSI_CLKSEL_I_MSK 0xffefffff
++#define CBR_RG_RX_ADCRSSI_CLKSEL_SFT 20
++#define CBR_RG_RX_ADCRSSI_CLKSEL_HI 20
++#define CBR_RG_RX_ADCRSSI_CLKSEL_SZ 1
++#define CBR_RG_RX_ADCRSSI_VCM_MSK 0x00600000
++#define CBR_RG_RX_ADCRSSI_VCM_I_MSK 0xff9fffff
++#define CBR_RG_RX_ADCRSSI_VCM_SFT 21
++#define CBR_RG_RX_ADCRSSI_VCM_HI 22
++#define CBR_RG_RX_ADCRSSI_VCM_SZ 2
++#define CBR_RG_RX_REC_LPFCORNER_MSK 0x01800000
++#define CBR_RG_RX_REC_LPFCORNER_I_MSK 0xfe7fffff
++#define CBR_RG_RX_REC_LPFCORNER_SFT 23
++#define CBR_RG_RX_REC_LPFCORNER_HI 24
++#define CBR_RG_RX_REC_LPFCORNER_SZ 2
++#define CBR_RG_RSSI_CLOCK_GATING_MSK 0x02000000
++#define CBR_RG_RSSI_CLOCK_GATING_I_MSK 0xfdffffff
++#define CBR_RG_RSSI_CLOCK_GATING_SFT 25
++#define CBR_RG_RSSI_CLOCK_GATING_HI 25
++#define CBR_RG_RSSI_CLOCK_GATING_SZ 1
++#define CBR_RG_TXPGA_CAPSW_MSK 0x00000003
++#define CBR_RG_TXPGA_CAPSW_I_MSK 0xfffffffc
++#define CBR_RG_TXPGA_CAPSW_SFT 0
++#define CBR_RG_TXPGA_CAPSW_HI 1
++#define CBR_RG_TXPGA_CAPSW_SZ 2
++#define CBR_RG_TXPGA_MAIN_MSK 0x000000fc
++#define CBR_RG_TXPGA_MAIN_I_MSK 0xffffff03
++#define CBR_RG_TXPGA_MAIN_SFT 2
++#define CBR_RG_TXPGA_MAIN_HI 7
++#define CBR_RG_TXPGA_MAIN_SZ 6
++#define CBR_RG_TXPGA_STEER_MSK 0x00003f00
++#define CBR_RG_TXPGA_STEER_I_MSK 0xffffc0ff
++#define CBR_RG_TXPGA_STEER_SFT 8
++#define CBR_RG_TXPGA_STEER_HI 13
++#define CBR_RG_TXPGA_STEER_SZ 6
++#define CBR_RG_TXMOD_GMCELL_MSK 0x0000c000
++#define CBR_RG_TXMOD_GMCELL_I_MSK 0xffff3fff
++#define CBR_RG_TXMOD_GMCELL_SFT 14
++#define CBR_RG_TXMOD_GMCELL_HI 15
++#define CBR_RG_TXMOD_GMCELL_SZ 2
++#define CBR_RG_TXLPF_GMCELL_MSK 0x00030000
++#define CBR_RG_TXLPF_GMCELL_I_MSK 0xfffcffff
++#define CBR_RG_TXLPF_GMCELL_SFT 16
++#define CBR_RG_TXLPF_GMCELL_HI 17
++#define CBR_RG_TXLPF_GMCELL_SZ 2
++#define CBR_RG_PACELL_EN_MSK 0x001c0000
++#define CBR_RG_PACELL_EN_I_MSK 0xffe3ffff
++#define CBR_RG_PACELL_EN_SFT 18
++#define CBR_RG_PACELL_EN_HI 20
++#define CBR_RG_PACELL_EN_SZ 3
++#define CBR_RG_PABIAS_CTRL_MSK 0x01e00000
++#define CBR_RG_PABIAS_CTRL_I_MSK 0xfe1fffff
++#define CBR_RG_PABIAS_CTRL_SFT 21
++#define CBR_RG_PABIAS_CTRL_HI 24
++#define CBR_RG_PABIAS_CTRL_SZ 4
++#define CBR_RG_PABIAS_AB_MSK 0x02000000
++#define CBR_RG_PABIAS_AB_I_MSK 0xfdffffff
++#define CBR_RG_PABIAS_AB_SFT 25
++#define CBR_RG_PABIAS_AB_HI 25
++#define CBR_RG_PABIAS_AB_SZ 1
++#define CBR_RG_TX_DIV_VSET_MSK 0x0c000000
++#define CBR_RG_TX_DIV_VSET_I_MSK 0xf3ffffff
++#define CBR_RG_TX_DIV_VSET_SFT 26
++#define CBR_RG_TX_DIV_VSET_HI 27
++#define CBR_RG_TX_DIV_VSET_SZ 2
++#define CBR_RG_TX_LOBUF_VSET_MSK 0x30000000
++#define CBR_RG_TX_LOBUF_VSET_I_MSK 0xcfffffff
++#define CBR_RG_TX_LOBUF_VSET_SFT 28
++#define CBR_RG_TX_LOBUF_VSET_HI 29
++#define CBR_RG_TX_LOBUF_VSET_SZ 2
++#define CBR_RG_RX_SQDC_MSK 0x00000007
++#define CBR_RG_RX_SQDC_I_MSK 0xfffffff8
++#define CBR_RG_RX_SQDC_SFT 0
++#define CBR_RG_RX_SQDC_HI 2
++#define CBR_RG_RX_SQDC_SZ 3
++#define CBR_RG_RX_DIV2_CORE_MSK 0x00000018
++#define CBR_RG_RX_DIV2_CORE_I_MSK 0xffffffe7
++#define CBR_RG_RX_DIV2_CORE_SFT 3
++#define CBR_RG_RX_DIV2_CORE_HI 4
++#define CBR_RG_RX_DIV2_CORE_SZ 2
++#define CBR_RG_RX_LOBUF_MSK 0x00000060
++#define CBR_RG_RX_LOBUF_I_MSK 0xffffff9f
++#define CBR_RG_RX_LOBUF_SFT 5
++#define CBR_RG_RX_LOBUF_HI 6
++#define CBR_RG_RX_LOBUF_SZ 2
++#define CBR_RG_TX_DPDGM_BIAS_MSK 0x00000780
++#define CBR_RG_TX_DPDGM_BIAS_I_MSK 0xfffff87f
++#define CBR_RG_TX_DPDGM_BIAS_SFT 7
++#define CBR_RG_TX_DPDGM_BIAS_HI 10
++#define CBR_RG_TX_DPDGM_BIAS_SZ 4
++#define CBR_RG_TX_DPD_DIV_MSK 0x00007800
++#define CBR_RG_TX_DPD_DIV_I_MSK 0xffff87ff
++#define CBR_RG_TX_DPD_DIV_SFT 11
++#define CBR_RG_TX_DPD_DIV_HI 14
++#define CBR_RG_TX_DPD_DIV_SZ 4
++#define CBR_RG_TX_TSSI_BIAS_MSK 0x00038000
++#define CBR_RG_TX_TSSI_BIAS_I_MSK 0xfffc7fff
++#define CBR_RG_TX_TSSI_BIAS_SFT 15
++#define CBR_RG_TX_TSSI_BIAS_HI 17
++#define CBR_RG_TX_TSSI_BIAS_SZ 3
++#define CBR_RG_TX_TSSI_DIV_MSK 0x001c0000
++#define CBR_RG_TX_TSSI_DIV_I_MSK 0xffe3ffff
++#define CBR_RG_TX_TSSI_DIV_SFT 18
++#define CBR_RG_TX_TSSI_DIV_HI 20
++#define CBR_RG_TX_TSSI_DIV_SZ 3
++#define CBR_RG_TX_TSSI_TESTMODE_MSK 0x00200000
++#define CBR_RG_TX_TSSI_TESTMODE_I_MSK 0xffdfffff
++#define CBR_RG_TX_TSSI_TESTMODE_SFT 21
++#define CBR_RG_TX_TSSI_TESTMODE_HI 21
++#define CBR_RG_TX_TSSI_TESTMODE_SZ 1
++#define CBR_RG_TX_TSSI_TEST_MSK 0x00c00000
++#define CBR_RG_TX_TSSI_TEST_I_MSK 0xff3fffff
++#define CBR_RG_TX_TSSI_TEST_SFT 22
++#define CBR_RG_TX_TSSI_TEST_HI 23
++#define CBR_RG_TX_TSSI_TEST_SZ 2
++#define CBR_RG_RX_HG_LNA_GC_MSK 0x00000003
++#define CBR_RG_RX_HG_LNA_GC_I_MSK 0xfffffffc
++#define CBR_RG_RX_HG_LNA_GC_SFT 0
++#define CBR_RG_RX_HG_LNA_GC_HI 1
++#define CBR_RG_RX_HG_LNA_GC_SZ 2
++#define CBR_RG_RX_HG_LNAHGN_BIAS_MSK 0x0000003c
++#define CBR_RG_RX_HG_LNAHGN_BIAS_I_MSK 0xffffffc3
++#define CBR_RG_RX_HG_LNAHGN_BIAS_SFT 2
++#define CBR_RG_RX_HG_LNAHGN_BIAS_HI 5
++#define CBR_RG_RX_HG_LNAHGN_BIAS_SZ 4
++#define CBR_RG_RX_HG_LNAHGP_BIAS_MSK 0x000003c0
++#define CBR_RG_RX_HG_LNAHGP_BIAS_I_MSK 0xfffffc3f
++#define CBR_RG_RX_HG_LNAHGP_BIAS_SFT 6
++#define CBR_RG_RX_HG_LNAHGP_BIAS_HI 9
++#define CBR_RG_RX_HG_LNAHGP_BIAS_SZ 4
++#define CBR_RG_RX_HG_LNALG_BIAS_MSK 0x00003c00
++#define CBR_RG_RX_HG_LNALG_BIAS_I_MSK 0xffffc3ff
++#define CBR_RG_RX_HG_LNALG_BIAS_SFT 10
++#define CBR_RG_RX_HG_LNALG_BIAS_HI 13
++#define CBR_RG_RX_HG_LNALG_BIAS_SZ 4
++#define CBR_RG_RX_HG_TZ_GC_MSK 0x0000c000
++#define CBR_RG_RX_HG_TZ_GC_I_MSK 0xffff3fff
++#define CBR_RG_RX_HG_TZ_GC_SFT 14
++#define CBR_RG_RX_HG_TZ_GC_HI 15
++#define CBR_RG_RX_HG_TZ_GC_SZ 2
++#define CBR_RG_RX_HG_TZ_CAP_MSK 0x00070000
++#define CBR_RG_RX_HG_TZ_CAP_I_MSK 0xfff8ffff
++#define CBR_RG_RX_HG_TZ_CAP_SFT 16
++#define CBR_RG_RX_HG_TZ_CAP_HI 18
++#define CBR_RG_RX_HG_TZ_CAP_SZ 3
++#define CBR_RG_RX_MG_LNA_GC_MSK 0x00000003
++#define CBR_RG_RX_MG_LNA_GC_I_MSK 0xfffffffc
++#define CBR_RG_RX_MG_LNA_GC_SFT 0
++#define CBR_RG_RX_MG_LNA_GC_HI 1
++#define CBR_RG_RX_MG_LNA_GC_SZ 2
++#define CBR_RG_RX_MG_LNAHGN_BIAS_MSK 0x0000003c
++#define CBR_RG_RX_MG_LNAHGN_BIAS_I_MSK 0xffffffc3
++#define CBR_RG_RX_MG_LNAHGN_BIAS_SFT 2
++#define CBR_RG_RX_MG_LNAHGN_BIAS_HI 5
++#define CBR_RG_RX_MG_LNAHGN_BIAS_SZ 4
++#define CBR_RG_RX_MG_LNAHGP_BIAS_MSK 0x000003c0
++#define CBR_RG_RX_MG_LNAHGP_BIAS_I_MSK 0xfffffc3f
++#define CBR_RG_RX_MG_LNAHGP_BIAS_SFT 6
++#define CBR_RG_RX_MG_LNAHGP_BIAS_HI 9
++#define CBR_RG_RX_MG_LNAHGP_BIAS_SZ 4
++#define CBR_RG_RX_MG_LNALG_BIAS_MSK 0x00003c00
++#define CBR_RG_RX_MG_LNALG_BIAS_I_MSK 0xffffc3ff
++#define CBR_RG_RX_MG_LNALG_BIAS_SFT 10
++#define CBR_RG_RX_MG_LNALG_BIAS_HI 13
++#define CBR_RG_RX_MG_LNALG_BIAS_SZ 4
++#define CBR_RG_RX_MG_TZ_GC_MSK 0x0000c000
++#define CBR_RG_RX_MG_TZ_GC_I_MSK 0xffff3fff
++#define CBR_RG_RX_MG_TZ_GC_SFT 14
++#define CBR_RG_RX_MG_TZ_GC_HI 15
++#define CBR_RG_RX_MG_TZ_GC_SZ 2
++#define CBR_RG_RX_MG_TZ_CAP_MSK 0x00070000
++#define CBR_RG_RX_MG_TZ_CAP_I_MSK 0xfff8ffff
++#define CBR_RG_RX_MG_TZ_CAP_SFT 16
++#define CBR_RG_RX_MG_TZ_CAP_HI 18
++#define CBR_RG_RX_MG_TZ_CAP_SZ 3
++#define CBR_RG_RX_LG_LNA_GC_MSK 0x00000003
++#define CBR_RG_RX_LG_LNA_GC_I_MSK 0xfffffffc
++#define CBR_RG_RX_LG_LNA_GC_SFT 0
++#define CBR_RG_RX_LG_LNA_GC_HI 1
++#define CBR_RG_RX_LG_LNA_GC_SZ 2
++#define CBR_RG_RX_LG_LNAHGN_BIAS_MSK 0x0000003c
++#define CBR_RG_RX_LG_LNAHGN_BIAS_I_MSK 0xffffffc3
++#define CBR_RG_RX_LG_LNAHGN_BIAS_SFT 2
++#define CBR_RG_RX_LG_LNAHGN_BIAS_HI 5
++#define CBR_RG_RX_LG_LNAHGN_BIAS_SZ 4
++#define CBR_RG_RX_LG_LNAHGP_BIAS_MSK 0x000003c0
++#define CBR_RG_RX_LG_LNAHGP_BIAS_I_MSK 0xfffffc3f
++#define CBR_RG_RX_LG_LNAHGP_BIAS_SFT 6
++#define CBR_RG_RX_LG_LNAHGP_BIAS_HI 9
++#define CBR_RG_RX_LG_LNAHGP_BIAS_SZ 4
++#define CBR_RG_RX_LG_LNALG_BIAS_MSK 0x00003c00
++#define CBR_RG_RX_LG_LNALG_BIAS_I_MSK 0xffffc3ff
++#define CBR_RG_RX_LG_LNALG_BIAS_SFT 10
++#define CBR_RG_RX_LG_LNALG_BIAS_HI 13
++#define CBR_RG_RX_LG_LNALG_BIAS_SZ 4
++#define CBR_RG_RX_LG_TZ_GC_MSK 0x0000c000
++#define CBR_RG_RX_LG_TZ_GC_I_MSK 0xffff3fff
++#define CBR_RG_RX_LG_TZ_GC_SFT 14
++#define CBR_RG_RX_LG_TZ_GC_HI 15
++#define CBR_RG_RX_LG_TZ_GC_SZ 2
++#define CBR_RG_RX_LG_TZ_CAP_MSK 0x00070000
++#define CBR_RG_RX_LG_TZ_CAP_I_MSK 0xfff8ffff
++#define CBR_RG_RX_LG_TZ_CAP_SFT 16
++#define CBR_RG_RX_LG_TZ_CAP_HI 18
++#define CBR_RG_RX_LG_TZ_CAP_SZ 3
++#define CBR_RG_RX_ULG_LNA_GC_MSK 0x00000003
++#define CBR_RG_RX_ULG_LNA_GC_I_MSK 0xfffffffc
++#define CBR_RG_RX_ULG_LNA_GC_SFT 0
++#define CBR_RG_RX_ULG_LNA_GC_HI 1
++#define CBR_RG_RX_ULG_LNA_GC_SZ 2
++#define CBR_RG_RX_ULG_LNAHGN_BIAS_MSK 0x0000003c
++#define CBR_RG_RX_ULG_LNAHGN_BIAS_I_MSK 0xffffffc3
++#define CBR_RG_RX_ULG_LNAHGN_BIAS_SFT 2
++#define CBR_RG_RX_ULG_LNAHGN_BIAS_HI 5
++#define CBR_RG_RX_ULG_LNAHGN_BIAS_SZ 4
++#define CBR_RG_RX_ULG_LNAHGP_BIAS_MSK 0x000003c0
++#define CBR_RG_RX_ULG_LNAHGP_BIAS_I_MSK 0xfffffc3f
++#define CBR_RG_RX_ULG_LNAHGP_BIAS_SFT 6
++#define CBR_RG_RX_ULG_LNAHGP_BIAS_HI 9
++#define CBR_RG_RX_ULG_LNAHGP_BIAS_SZ 4
++#define CBR_RG_RX_ULG_LNALG_BIAS_MSK 0x00003c00
++#define CBR_RG_RX_ULG_LNALG_BIAS_I_MSK 0xffffc3ff
++#define CBR_RG_RX_ULG_LNALG_BIAS_SFT 10
++#define CBR_RG_RX_ULG_LNALG_BIAS_HI 13
++#define CBR_RG_RX_ULG_LNALG_BIAS_SZ 4
++#define CBR_RG_RX_ULG_TZ_GC_MSK 0x0000c000
++#define CBR_RG_RX_ULG_TZ_GC_I_MSK 0xffff3fff
++#define CBR_RG_RX_ULG_TZ_GC_SFT 14
++#define CBR_RG_RX_ULG_TZ_GC_HI 15
++#define CBR_RG_RX_ULG_TZ_GC_SZ 2
++#define CBR_RG_RX_ULG_TZ_CAP_MSK 0x00070000
++#define CBR_RG_RX_ULG_TZ_CAP_I_MSK 0xfff8ffff
++#define CBR_RG_RX_ULG_TZ_CAP_SFT 16
++#define CBR_RG_RX_ULG_TZ_CAP_HI 18
++#define CBR_RG_RX_ULG_TZ_CAP_SZ 3
++#define CBR_RG_HPF1_FAST_SET_X_MSK 0x00000001
++#define CBR_RG_HPF1_FAST_SET_X_I_MSK 0xfffffffe
++#define CBR_RG_HPF1_FAST_SET_X_SFT 0
++#define CBR_RG_HPF1_FAST_SET_X_HI 0
++#define CBR_RG_HPF1_FAST_SET_X_SZ 1
++#define CBR_RG_HPF1_FAST_SET_Y_MSK 0x00000002
++#define CBR_RG_HPF1_FAST_SET_Y_I_MSK 0xfffffffd
++#define CBR_RG_HPF1_FAST_SET_Y_SFT 1
++#define CBR_RG_HPF1_FAST_SET_Y_HI 1
++#define CBR_RG_HPF1_FAST_SET_Y_SZ 1
++#define CBR_RG_HPF1_FAST_SET_Z_MSK 0x00000004
++#define CBR_RG_HPF1_FAST_SET_Z_I_MSK 0xfffffffb
++#define CBR_RG_HPF1_FAST_SET_Z_SFT 2
++#define CBR_RG_HPF1_FAST_SET_Z_HI 2
++#define CBR_RG_HPF1_FAST_SET_Z_SZ 1
++#define CBR_RG_HPF_T1A_MSK 0x00000018
++#define CBR_RG_HPF_T1A_I_MSK 0xffffffe7
++#define CBR_RG_HPF_T1A_SFT 3
++#define CBR_RG_HPF_T1A_HI 4
++#define CBR_RG_HPF_T1A_SZ 2
++#define CBR_RG_HPF_T1B_MSK 0x00000060
++#define CBR_RG_HPF_T1B_I_MSK 0xffffff9f
++#define CBR_RG_HPF_T1B_SFT 5
++#define CBR_RG_HPF_T1B_HI 6
++#define CBR_RG_HPF_T1B_SZ 2
++#define CBR_RG_HPF_T1C_MSK 0x00000180
++#define CBR_RG_HPF_T1C_I_MSK 0xfffffe7f
++#define CBR_RG_HPF_T1C_SFT 7
++#define CBR_RG_HPF_T1C_HI 8
++#define CBR_RG_HPF_T1C_SZ 2
++#define CBR_RG_RX_LNA_TRI_SEL_MSK 0x00000600
++#define CBR_RG_RX_LNA_TRI_SEL_I_MSK 0xfffff9ff
++#define CBR_RG_RX_LNA_TRI_SEL_SFT 9
++#define CBR_RG_RX_LNA_TRI_SEL_HI 10
++#define CBR_RG_RX_LNA_TRI_SEL_SZ 2
++#define CBR_RG_RX_LNA_SETTLE_MSK 0x00001800
++#define CBR_RG_RX_LNA_SETTLE_I_MSK 0xffffe7ff
++#define CBR_RG_RX_LNA_SETTLE_SFT 11
++#define CBR_RG_RX_LNA_SETTLE_HI 12
++#define CBR_RG_RX_LNA_SETTLE_SZ 2
++#define CBR_RG_ADC_CLKSEL_MSK 0x00000001
++#define CBR_RG_ADC_CLKSEL_I_MSK 0xfffffffe
++#define CBR_RG_ADC_CLKSEL_SFT 0
++#define CBR_RG_ADC_CLKSEL_HI 0
++#define CBR_RG_ADC_CLKSEL_SZ 1
++#define CBR_RG_ADC_DIBIAS_MSK 0x00000006
++#define CBR_RG_ADC_DIBIAS_I_MSK 0xfffffff9
++#define CBR_RG_ADC_DIBIAS_SFT 1
++#define CBR_RG_ADC_DIBIAS_HI 2
++#define CBR_RG_ADC_DIBIAS_SZ 2
++#define CBR_RG_ADC_DIVR_MSK 0x00000008
++#define CBR_RG_ADC_DIVR_I_MSK 0xfffffff7
++#define CBR_RG_ADC_DIVR_SFT 3
++#define CBR_RG_ADC_DIVR_HI 3
++#define CBR_RG_ADC_DIVR_SZ 1
++#define CBR_RG_ADC_DVCMI_MSK 0x00000030
++#define CBR_RG_ADC_DVCMI_I_MSK 0xffffffcf
++#define CBR_RG_ADC_DVCMI_SFT 4
++#define CBR_RG_ADC_DVCMI_HI 5
++#define CBR_RG_ADC_DVCMI_SZ 2
++#define CBR_RG_ADC_SAMSEL_MSK 0x000003c0
++#define CBR_RG_ADC_SAMSEL_I_MSK 0xfffffc3f
++#define CBR_RG_ADC_SAMSEL_SFT 6
++#define CBR_RG_ADC_SAMSEL_HI 9
++#define CBR_RG_ADC_SAMSEL_SZ 4
++#define CBR_RG_ADC_STNBY_MSK 0x00000400
++#define CBR_RG_ADC_STNBY_I_MSK 0xfffffbff
++#define CBR_RG_ADC_STNBY_SFT 10
++#define CBR_RG_ADC_STNBY_HI 10
++#define CBR_RG_ADC_STNBY_SZ 1
++#define CBR_RG_ADC_TESTMODE_MSK 0x00000800
++#define CBR_RG_ADC_TESTMODE_I_MSK 0xfffff7ff
++#define CBR_RG_ADC_TESTMODE_SFT 11
++#define CBR_RG_ADC_TESTMODE_HI 11
++#define CBR_RG_ADC_TESTMODE_SZ 1
++#define CBR_RG_ADC_TSEL_MSK 0x0000f000
++#define CBR_RG_ADC_TSEL_I_MSK 0xffff0fff
++#define CBR_RG_ADC_TSEL_SFT 12
++#define CBR_RG_ADC_TSEL_HI 15
++#define CBR_RG_ADC_TSEL_SZ 4
++#define CBR_RG_ADC_VRSEL_MSK 0x00030000
++#define CBR_RG_ADC_VRSEL_I_MSK 0xfffcffff
++#define CBR_RG_ADC_VRSEL_SFT 16
++#define CBR_RG_ADC_VRSEL_HI 17
++#define CBR_RG_ADC_VRSEL_SZ 2
++#define CBR_RG_DICMP_MSK 0x000c0000
++#define CBR_RG_DICMP_I_MSK 0xfff3ffff
++#define CBR_RG_DICMP_SFT 18
++#define CBR_RG_DICMP_HI 19
++#define CBR_RG_DICMP_SZ 2
++#define CBR_RG_DIOP_MSK 0x00300000
++#define CBR_RG_DIOP_I_MSK 0xffcfffff
++#define CBR_RG_DIOP_SFT 20
++#define CBR_RG_DIOP_HI 21
++#define CBR_RG_DIOP_SZ 2
++#define CBR_RG_DACI1ST_MSK 0x00000003
++#define CBR_RG_DACI1ST_I_MSK 0xfffffffc
++#define CBR_RG_DACI1ST_SFT 0
++#define CBR_RG_DACI1ST_HI 1
++#define CBR_RG_DACI1ST_SZ 2
++#define CBR_RG_TX_DACLPF_ICOURSE_MSK 0x0000000c
++#define CBR_RG_TX_DACLPF_ICOURSE_I_MSK 0xfffffff3
++#define CBR_RG_TX_DACLPF_ICOURSE_SFT 2
++#define CBR_RG_TX_DACLPF_ICOURSE_HI 3
++#define CBR_RG_TX_DACLPF_ICOURSE_SZ 2
++#define CBR_RG_TX_DACLPF_IFINE_MSK 0x00000030
++#define CBR_RG_TX_DACLPF_IFINE_I_MSK 0xffffffcf
++#define CBR_RG_TX_DACLPF_IFINE_SFT 4
++#define CBR_RG_TX_DACLPF_IFINE_HI 5
++#define CBR_RG_TX_DACLPF_IFINE_SZ 2
++#define CBR_RG_TX_DACLPF_VCM_MSK 0x000000c0
++#define CBR_RG_TX_DACLPF_VCM_I_MSK 0xffffff3f
++#define CBR_RG_TX_DACLPF_VCM_SFT 6
++#define CBR_RG_TX_DACLPF_VCM_HI 7
++#define CBR_RG_TX_DACLPF_VCM_SZ 2
++#define CBR_RG_TX_DAC_CKEDGE_SEL_MSK 0x00000100
++#define CBR_RG_TX_DAC_CKEDGE_SEL_I_MSK 0xfffffeff
++#define CBR_RG_TX_DAC_CKEDGE_SEL_SFT 8
++#define CBR_RG_TX_DAC_CKEDGE_SEL_HI 8
++#define CBR_RG_TX_DAC_CKEDGE_SEL_SZ 1
++#define CBR_RG_TX_DAC_IBIAS_MSK 0x00000600
++#define CBR_RG_TX_DAC_IBIAS_I_MSK 0xfffff9ff
++#define CBR_RG_TX_DAC_IBIAS_SFT 9
++#define CBR_RG_TX_DAC_IBIAS_HI 10
++#define CBR_RG_TX_DAC_IBIAS_SZ 2
++#define CBR_RG_TX_DAC_OS_MSK 0x00003800
++#define CBR_RG_TX_DAC_OS_I_MSK 0xffffc7ff
++#define CBR_RG_TX_DAC_OS_SFT 11
++#define CBR_RG_TX_DAC_OS_HI 13
++#define CBR_RG_TX_DAC_OS_SZ 3
++#define CBR_RG_TX_DAC_RCAL_MSK 0x0000c000
++#define CBR_RG_TX_DAC_RCAL_I_MSK 0xffff3fff
++#define CBR_RG_TX_DAC_RCAL_SFT 14
++#define CBR_RG_TX_DAC_RCAL_HI 15
++#define CBR_RG_TX_DAC_RCAL_SZ 2
++#define CBR_RG_TX_DAC_TSEL_MSK 0x000f0000
++#define CBR_RG_TX_DAC_TSEL_I_MSK 0xfff0ffff
++#define CBR_RG_TX_DAC_TSEL_SFT 16
++#define CBR_RG_TX_DAC_TSEL_HI 19
++#define CBR_RG_TX_DAC_TSEL_SZ 4
++#define CBR_RG_TX_EN_VOLTAGE_IN_MSK 0x00100000
++#define CBR_RG_TX_EN_VOLTAGE_IN_I_MSK 0xffefffff
++#define CBR_RG_TX_EN_VOLTAGE_IN_SFT 20
++#define CBR_RG_TX_EN_VOLTAGE_IN_HI 20
++#define CBR_RG_TX_EN_VOLTAGE_IN_SZ 1
++#define CBR_RG_TXLPF_BYPASS_MSK 0x00200000
++#define CBR_RG_TXLPF_BYPASS_I_MSK 0xffdfffff
++#define CBR_RG_TXLPF_BYPASS_SFT 21
++#define CBR_RG_TXLPF_BYPASS_HI 21
++#define CBR_RG_TXLPF_BYPASS_SZ 1
++#define CBR_RG_TXLPF_BOOSTI_MSK 0x00400000
++#define CBR_RG_TXLPF_BOOSTI_I_MSK 0xffbfffff
++#define CBR_RG_TXLPF_BOOSTI_SFT 22
++#define CBR_RG_TXLPF_BOOSTI_HI 22
++#define CBR_RG_TXLPF_BOOSTI_SZ 1
++#define CBR_RG_EN_SX_R3_MSK 0x00000001
++#define CBR_RG_EN_SX_R3_I_MSK 0xfffffffe
++#define CBR_RG_EN_SX_R3_SFT 0
++#define CBR_RG_EN_SX_R3_HI 0
++#define CBR_RG_EN_SX_R3_SZ 1
++#define CBR_RG_EN_SX_CH_MSK 0x00000002
++#define CBR_RG_EN_SX_CH_I_MSK 0xfffffffd
++#define CBR_RG_EN_SX_CH_SFT 1
++#define CBR_RG_EN_SX_CH_HI 1
++#define CBR_RG_EN_SX_CH_SZ 1
++#define CBR_RG_EN_SX_CHP_MSK 0x00000004
++#define CBR_RG_EN_SX_CHP_I_MSK 0xfffffffb
++#define CBR_RG_EN_SX_CHP_SFT 2
++#define CBR_RG_EN_SX_CHP_HI 2
++#define CBR_RG_EN_SX_CHP_SZ 1
++#define CBR_RG_EN_SX_DIVCK_MSK 0x00000008
++#define CBR_RG_EN_SX_DIVCK_I_MSK 0xfffffff7
++#define CBR_RG_EN_SX_DIVCK_SFT 3
++#define CBR_RG_EN_SX_DIVCK_HI 3
++#define CBR_RG_EN_SX_DIVCK_SZ 1
++#define CBR_RG_EN_SX_VCOBF_MSK 0x00000010
++#define CBR_RG_EN_SX_VCOBF_I_MSK 0xffffffef
++#define CBR_RG_EN_SX_VCOBF_SFT 4
++#define CBR_RG_EN_SX_VCOBF_HI 4
++#define CBR_RG_EN_SX_VCOBF_SZ 1
++#define CBR_RG_EN_SX_VCO_MSK 0x00000020
++#define CBR_RG_EN_SX_VCO_I_MSK 0xffffffdf
++#define CBR_RG_EN_SX_VCO_SFT 5
++#define CBR_RG_EN_SX_VCO_HI 5
++#define CBR_RG_EN_SX_VCO_SZ 1
++#define CBR_RG_EN_SX_MOD_MSK 0x00000040
++#define CBR_RG_EN_SX_MOD_I_MSK 0xffffffbf
++#define CBR_RG_EN_SX_MOD_SFT 6
++#define CBR_RG_EN_SX_MOD_HI 6
++#define CBR_RG_EN_SX_MOD_SZ 1
++#define CBR_RG_EN_SX_LCK_MSK 0x00000080
++#define CBR_RG_EN_SX_LCK_I_MSK 0xffffff7f
++#define CBR_RG_EN_SX_LCK_SFT 7
++#define CBR_RG_EN_SX_LCK_HI 7
++#define CBR_RG_EN_SX_LCK_SZ 1
++#define CBR_RG_EN_SX_DITHER_MSK 0x00000100
++#define CBR_RG_EN_SX_DITHER_I_MSK 0xfffffeff
++#define CBR_RG_EN_SX_DITHER_SFT 8
++#define CBR_RG_EN_SX_DITHER_HI 8
++#define CBR_RG_EN_SX_DITHER_SZ 1
++#define CBR_RG_EN_SX_DELCAL_MSK 0x00000200
++#define CBR_RG_EN_SX_DELCAL_I_MSK 0xfffffdff
++#define CBR_RG_EN_SX_DELCAL_SFT 9
++#define CBR_RG_EN_SX_DELCAL_HI 9
++#define CBR_RG_EN_SX_DELCAL_SZ 1
++#define CBR_RG_EN_SX_PC_BYPASS_MSK 0x00000400
++#define CBR_RG_EN_SX_PC_BYPASS_I_MSK 0xfffffbff
++#define CBR_RG_EN_SX_PC_BYPASS_SFT 10
++#define CBR_RG_EN_SX_PC_BYPASS_HI 10
++#define CBR_RG_EN_SX_PC_BYPASS_SZ 1
++#define CBR_RG_EN_SX_VT_MON_MSK 0x00000800
++#define CBR_RG_EN_SX_VT_MON_I_MSK 0xfffff7ff
++#define CBR_RG_EN_SX_VT_MON_SFT 11
++#define CBR_RG_EN_SX_VT_MON_HI 11
++#define CBR_RG_EN_SX_VT_MON_SZ 1
++#define CBR_RG_EN_SX_VT_MON_DG_MSK 0x00001000
++#define CBR_RG_EN_SX_VT_MON_DG_I_MSK 0xffffefff
++#define CBR_RG_EN_SX_VT_MON_DG_SFT 12
++#define CBR_RG_EN_SX_VT_MON_DG_HI 12
++#define CBR_RG_EN_SX_VT_MON_DG_SZ 1
++#define CBR_RG_EN_SX_DIV_MSK 0x00002000
++#define CBR_RG_EN_SX_DIV_I_MSK 0xffffdfff
++#define CBR_RG_EN_SX_DIV_SFT 13
++#define CBR_RG_EN_SX_DIV_HI 13
++#define CBR_RG_EN_SX_DIV_SZ 1
++#define CBR_RG_EN_SX_LPF_MSK 0x00004000
++#define CBR_RG_EN_SX_LPF_I_MSK 0xffffbfff
++#define CBR_RG_EN_SX_LPF_SFT 14
++#define CBR_RG_EN_SX_LPF_HI 14
++#define CBR_RG_EN_SX_LPF_SZ 1
++#define CBR_RG_SX_RFCTRL_F_MSK 0x00ffffff
++#define CBR_RG_SX_RFCTRL_F_I_MSK 0xff000000
++#define CBR_RG_SX_RFCTRL_F_SFT 0
++#define CBR_RG_SX_RFCTRL_F_HI 23
++#define CBR_RG_SX_RFCTRL_F_SZ 24
++#define CBR_RG_SX_SEL_CP_MSK 0x0f000000
++#define CBR_RG_SX_SEL_CP_I_MSK 0xf0ffffff
++#define CBR_RG_SX_SEL_CP_SFT 24
++#define CBR_RG_SX_SEL_CP_HI 27
++#define CBR_RG_SX_SEL_CP_SZ 4
++#define CBR_RG_SX_SEL_CS_MSK 0xf0000000
++#define CBR_RG_SX_SEL_CS_I_MSK 0x0fffffff
++#define CBR_RG_SX_SEL_CS_SFT 28
++#define CBR_RG_SX_SEL_CS_HI 31
++#define CBR_RG_SX_SEL_CS_SZ 4
++#define CBR_RG_SX_RFCTRL_CH_MSK 0x000007ff
++#define CBR_RG_SX_RFCTRL_CH_I_MSK 0xfffff800
++#define CBR_RG_SX_RFCTRL_CH_SFT 0
++#define CBR_RG_SX_RFCTRL_CH_HI 10
++#define CBR_RG_SX_RFCTRL_CH_SZ 11
++#define CBR_RG_SX_SEL_C3_MSK 0x00007800
++#define CBR_RG_SX_SEL_C3_I_MSK 0xffff87ff
++#define CBR_RG_SX_SEL_C3_SFT 11
++#define CBR_RG_SX_SEL_C3_HI 14
++#define CBR_RG_SX_SEL_C3_SZ 4
++#define CBR_RG_SX_SEL_RS_MSK 0x000f8000
++#define CBR_RG_SX_SEL_RS_I_MSK 0xfff07fff
++#define CBR_RG_SX_SEL_RS_SFT 15
++#define CBR_RG_SX_SEL_RS_HI 19
++#define CBR_RG_SX_SEL_RS_SZ 5
++#define CBR_RG_SX_SEL_R3_MSK 0x01f00000
++#define CBR_RG_SX_SEL_R3_I_MSK 0xfe0fffff
++#define CBR_RG_SX_SEL_R3_SFT 20
++#define CBR_RG_SX_SEL_R3_HI 24
++#define CBR_RG_SX_SEL_R3_SZ 5
++#define CBR_RG_SX_SEL_ICHP_MSK 0x0000001f
++#define CBR_RG_SX_SEL_ICHP_I_MSK 0xffffffe0
++#define CBR_RG_SX_SEL_ICHP_SFT 0
++#define CBR_RG_SX_SEL_ICHP_HI 4
++#define CBR_RG_SX_SEL_ICHP_SZ 5
++#define CBR_RG_SX_SEL_PCHP_MSK 0x000003e0
++#define CBR_RG_SX_SEL_PCHP_I_MSK 0xfffffc1f
++#define CBR_RG_SX_SEL_PCHP_SFT 5
++#define CBR_RG_SX_SEL_PCHP_HI 9
++#define CBR_RG_SX_SEL_PCHP_SZ 5
++#define CBR_RG_SX_SEL_CHP_REGOP_MSK 0x00003c00
++#define CBR_RG_SX_SEL_CHP_REGOP_I_MSK 0xffffc3ff
++#define CBR_RG_SX_SEL_CHP_REGOP_SFT 10
++#define CBR_RG_SX_SEL_CHP_REGOP_HI 13
++#define CBR_RG_SX_SEL_CHP_REGOP_SZ 4
++#define CBR_RG_SX_SEL_CHP_UNIOP_MSK 0x0003c000
++#define CBR_RG_SX_SEL_CHP_UNIOP_I_MSK 0xfffc3fff
++#define CBR_RG_SX_SEL_CHP_UNIOP_SFT 14
++#define CBR_RG_SX_SEL_CHP_UNIOP_HI 17
++#define CBR_RG_SX_SEL_CHP_UNIOP_SZ 4
++#define CBR_RG_SX_CHP_IOST_POL_MSK 0x00040000
++#define CBR_RG_SX_CHP_IOST_POL_I_MSK 0xfffbffff
++#define CBR_RG_SX_CHP_IOST_POL_SFT 18
++#define CBR_RG_SX_CHP_IOST_POL_HI 18
++#define CBR_RG_SX_CHP_IOST_POL_SZ 1
++#define CBR_RG_SX_CHP_IOST_MSK 0x00380000
++#define CBR_RG_SX_CHP_IOST_I_MSK 0xffc7ffff
++#define CBR_RG_SX_CHP_IOST_SFT 19
++#define CBR_RG_SX_CHP_IOST_HI 21
++#define CBR_RG_SX_CHP_IOST_SZ 3
++#define CBR_RG_SX_PFDSEL_MSK 0x00400000
++#define CBR_RG_SX_PFDSEL_I_MSK 0xffbfffff
++#define CBR_RG_SX_PFDSEL_SFT 22
++#define CBR_RG_SX_PFDSEL_HI 22
++#define CBR_RG_SX_PFDSEL_SZ 1
++#define CBR_RG_SX_PFD_SET_MSK 0x00800000
++#define CBR_RG_SX_PFD_SET_I_MSK 0xff7fffff
++#define CBR_RG_SX_PFD_SET_SFT 23
++#define CBR_RG_SX_PFD_SET_HI 23
++#define CBR_RG_SX_PFD_SET_SZ 1
++#define CBR_RG_SX_PFD_SET1_MSK 0x01000000
++#define CBR_RG_SX_PFD_SET1_I_MSK 0xfeffffff
++#define CBR_RG_SX_PFD_SET1_SFT 24
++#define CBR_RG_SX_PFD_SET1_HI 24
++#define CBR_RG_SX_PFD_SET1_SZ 1
++#define CBR_RG_SX_PFD_SET2_MSK 0x02000000
++#define CBR_RG_SX_PFD_SET2_I_MSK 0xfdffffff
++#define CBR_RG_SX_PFD_SET2_SFT 25
++#define CBR_RG_SX_PFD_SET2_HI 25
++#define CBR_RG_SX_PFD_SET2_SZ 1
++#define CBR_RG_SX_VBNCAS_SEL_MSK 0x04000000
++#define CBR_RG_SX_VBNCAS_SEL_I_MSK 0xfbffffff
++#define CBR_RG_SX_VBNCAS_SEL_SFT 26
++#define CBR_RG_SX_VBNCAS_SEL_HI 26
++#define CBR_RG_SX_VBNCAS_SEL_SZ 1
++#define CBR_RG_SX_PFD_RST_H_MSK 0x08000000
++#define CBR_RG_SX_PFD_RST_H_I_MSK 0xf7ffffff
++#define CBR_RG_SX_PFD_RST_H_SFT 27
++#define CBR_RG_SX_PFD_RST_H_HI 27
++#define CBR_RG_SX_PFD_RST_H_SZ 1
++#define CBR_RG_SX_PFD_TRUP_MSK 0x10000000
++#define CBR_RG_SX_PFD_TRUP_I_MSK 0xefffffff
++#define CBR_RG_SX_PFD_TRUP_SFT 28
++#define CBR_RG_SX_PFD_TRUP_HI 28
++#define CBR_RG_SX_PFD_TRUP_SZ 1
++#define CBR_RG_SX_PFD_TRDN_MSK 0x20000000
++#define CBR_RG_SX_PFD_TRDN_I_MSK 0xdfffffff
++#define CBR_RG_SX_PFD_TRDN_SFT 29
++#define CBR_RG_SX_PFD_TRDN_HI 29
++#define CBR_RG_SX_PFD_TRDN_SZ 1
++#define CBR_RG_SX_PFD_TRSEL_MSK 0x40000000
++#define CBR_RG_SX_PFD_TRSEL_I_MSK 0xbfffffff
++#define CBR_RG_SX_PFD_TRSEL_SFT 30
++#define CBR_RG_SX_PFD_TRSEL_HI 30
++#define CBR_RG_SX_PFD_TRSEL_SZ 1
++#define CBR_RG_SX_VCOBA_R_MSK 0x00000007
++#define CBR_RG_SX_VCOBA_R_I_MSK 0xfffffff8
++#define CBR_RG_SX_VCOBA_R_SFT 0
++#define CBR_RG_SX_VCOBA_R_HI 2
++#define CBR_RG_SX_VCOBA_R_SZ 3
++#define CBR_RG_SX_VCORSEL_MSK 0x000000f8
++#define CBR_RG_SX_VCORSEL_I_MSK 0xffffff07
++#define CBR_RG_SX_VCORSEL_SFT 3
++#define CBR_RG_SX_VCORSEL_HI 7
++#define CBR_RG_SX_VCORSEL_SZ 5
++#define CBR_RG_SX_VCOCUSEL_MSK 0x00000f00
++#define CBR_RG_SX_VCOCUSEL_I_MSK 0xfffff0ff
++#define CBR_RG_SX_VCOCUSEL_SFT 8
++#define CBR_RG_SX_VCOCUSEL_HI 11
++#define CBR_RG_SX_VCOCUSEL_SZ 4
++#define CBR_RG_SX_RXBFSEL_MSK 0x0000f000
++#define CBR_RG_SX_RXBFSEL_I_MSK 0xffff0fff
++#define CBR_RG_SX_RXBFSEL_SFT 12
++#define CBR_RG_SX_RXBFSEL_HI 15
++#define CBR_RG_SX_RXBFSEL_SZ 4
++#define CBR_RG_SX_TXBFSEL_MSK 0x000f0000
++#define CBR_RG_SX_TXBFSEL_I_MSK 0xfff0ffff
++#define CBR_RG_SX_TXBFSEL_SFT 16
++#define CBR_RG_SX_TXBFSEL_HI 19
++#define CBR_RG_SX_TXBFSEL_SZ 4
++#define CBR_RG_SX_VCOBFSEL_MSK 0x00f00000
++#define CBR_RG_SX_VCOBFSEL_I_MSK 0xff0fffff
++#define CBR_RG_SX_VCOBFSEL_SFT 20
++#define CBR_RG_SX_VCOBFSEL_HI 23
++#define CBR_RG_SX_VCOBFSEL_SZ 4
++#define CBR_RG_SX_DIVBFSEL_MSK 0x0f000000
++#define CBR_RG_SX_DIVBFSEL_I_MSK 0xf0ffffff
++#define CBR_RG_SX_DIVBFSEL_SFT 24
++#define CBR_RG_SX_DIVBFSEL_HI 27
++#define CBR_RG_SX_DIVBFSEL_SZ 4
++#define CBR_RG_SX_GNDR_SEL_MSK 0xf0000000
++#define CBR_RG_SX_GNDR_SEL_I_MSK 0x0fffffff
++#define CBR_RG_SX_GNDR_SEL_SFT 28
++#define CBR_RG_SX_GNDR_SEL_HI 31
++#define CBR_RG_SX_GNDR_SEL_SZ 4
++#define CBR_RG_SX_DITHER_WEIGHT_MSK 0x00000003
++#define CBR_RG_SX_DITHER_WEIGHT_I_MSK 0xfffffffc
++#define CBR_RG_SX_DITHER_WEIGHT_SFT 0
++#define CBR_RG_SX_DITHER_WEIGHT_HI 1
++#define CBR_RG_SX_DITHER_WEIGHT_SZ 2
++#define CBR_RG_SX_MOD_ERRCMP_MSK 0x0000000c
++#define CBR_RG_SX_MOD_ERRCMP_I_MSK 0xfffffff3
++#define CBR_RG_SX_MOD_ERRCMP_SFT 2
++#define CBR_RG_SX_MOD_ERRCMP_HI 3
++#define CBR_RG_SX_MOD_ERRCMP_SZ 2
++#define CBR_RG_SX_MOD_ORDER_MSK 0x00000030
++#define CBR_RG_SX_MOD_ORDER_I_MSK 0xffffffcf
++#define CBR_RG_SX_MOD_ORDER_SFT 4
++#define CBR_RG_SX_MOD_ORDER_HI 5
++#define CBR_RG_SX_MOD_ORDER_SZ 2
++#define CBR_RG_SX_SDM_D1_MSK 0x00000040
++#define CBR_RG_SX_SDM_D1_I_MSK 0xffffffbf
++#define CBR_RG_SX_SDM_D1_SFT 6
++#define CBR_RG_SX_SDM_D1_HI 6
++#define CBR_RG_SX_SDM_D1_SZ 1
++#define CBR_RG_SX_SDM_D2_MSK 0x00000080
++#define CBR_RG_SX_SDM_D2_I_MSK 0xffffff7f
++#define CBR_RG_SX_SDM_D2_SFT 7
++#define CBR_RG_SX_SDM_D2_HI 7
++#define CBR_RG_SX_SDM_D2_SZ 1
++#define CBR_RG_SDM_PASS_MSK 0x00000100
++#define CBR_RG_SDM_PASS_I_MSK 0xfffffeff
++#define CBR_RG_SDM_PASS_SFT 8
++#define CBR_RG_SDM_PASS_HI 8
++#define CBR_RG_SDM_PASS_SZ 1
++#define CBR_RG_SX_RST_H_DIV_MSK 0x00000200
++#define CBR_RG_SX_RST_H_DIV_I_MSK 0xfffffdff
++#define CBR_RG_SX_RST_H_DIV_SFT 9
++#define CBR_RG_SX_RST_H_DIV_HI 9
++#define CBR_RG_SX_RST_H_DIV_SZ 1
++#define CBR_RG_SX_SDM_EDGE_MSK 0x00000400
++#define CBR_RG_SX_SDM_EDGE_I_MSK 0xfffffbff
++#define CBR_RG_SX_SDM_EDGE_SFT 10
++#define CBR_RG_SX_SDM_EDGE_HI 10
++#define CBR_RG_SX_SDM_EDGE_SZ 1
++#define CBR_RG_SX_XO_GM_MSK 0x00001800
++#define CBR_RG_SX_XO_GM_I_MSK 0xffffe7ff
++#define CBR_RG_SX_XO_GM_SFT 11
++#define CBR_RG_SX_XO_GM_HI 12
++#define CBR_RG_SX_XO_GM_SZ 2
++#define CBR_RG_SX_REFBYTWO_MSK 0x00002000
++#define CBR_RG_SX_REFBYTWO_I_MSK 0xffffdfff
++#define CBR_RG_SX_REFBYTWO_SFT 13
++#define CBR_RG_SX_REFBYTWO_HI 13
++#define CBR_RG_SX_REFBYTWO_SZ 1
++#define CBR_RG_SX_XO_SWCAP_MSK 0x0003c000
++#define CBR_RG_SX_XO_SWCAP_I_MSK 0xfffc3fff
++#define CBR_RG_SX_XO_SWCAP_SFT 14
++#define CBR_RG_SX_XO_SWCAP_HI 17
++#define CBR_RG_SX_XO_SWCAP_SZ 4
++#define CBR_RG_SX_SDMLUT_INV_MSK 0x00040000
++#define CBR_RG_SX_SDMLUT_INV_I_MSK 0xfffbffff
++#define CBR_RG_SX_SDMLUT_INV_SFT 18
++#define CBR_RG_SX_SDMLUT_INV_HI 18
++#define CBR_RG_SX_SDMLUT_INV_SZ 1
++#define CBR_RG_SX_LCKEN_MSK 0x00080000
++#define CBR_RG_SX_LCKEN_I_MSK 0xfff7ffff
++#define CBR_RG_SX_LCKEN_SFT 19
++#define CBR_RG_SX_LCKEN_HI 19
++#define CBR_RG_SX_LCKEN_SZ 1
++#define CBR_RG_SX_PREVDD_MSK 0x00f00000
++#define CBR_RG_SX_PREVDD_I_MSK 0xff0fffff
++#define CBR_RG_SX_PREVDD_SFT 20
++#define CBR_RG_SX_PREVDD_HI 23
++#define CBR_RG_SX_PREVDD_SZ 4
++#define CBR_RG_SX_PSCONTERVDD_MSK 0x0f000000
++#define CBR_RG_SX_PSCONTERVDD_I_MSK 0xf0ffffff
++#define CBR_RG_SX_PSCONTERVDD_SFT 24
++#define CBR_RG_SX_PSCONTERVDD_HI 27
++#define CBR_RG_SX_PSCONTERVDD_SZ 4
++#define CBR_RG_SX_MOD_ERR_DELAY_MSK 0x30000000
++#define CBR_RG_SX_MOD_ERR_DELAY_I_MSK 0xcfffffff
++#define CBR_RG_SX_MOD_ERR_DELAY_SFT 28
++#define CBR_RG_SX_MOD_ERR_DELAY_HI 29
++#define CBR_RG_SX_MOD_ERR_DELAY_SZ 2
++#define CBR_RG_SX_MODDB_MSK 0x40000000
++#define CBR_RG_SX_MODDB_I_MSK 0xbfffffff
++#define CBR_RG_SX_MODDB_SFT 30
++#define CBR_RG_SX_MODDB_HI 30
++#define CBR_RG_SX_MODDB_SZ 1
++#define CBR_RG_SX_CV_CURVE_SEL_MSK 0x00000003
++#define CBR_RG_SX_CV_CURVE_SEL_I_MSK 0xfffffffc
++#define CBR_RG_SX_CV_CURVE_SEL_SFT 0
++#define CBR_RG_SX_CV_CURVE_SEL_HI 1
++#define CBR_RG_SX_CV_CURVE_SEL_SZ 2
++#define CBR_RG_SX_SEL_DELAY_MSK 0x0000007c
++#define CBR_RG_SX_SEL_DELAY_I_MSK 0xffffff83
++#define CBR_RG_SX_SEL_DELAY_SFT 2
++#define CBR_RG_SX_SEL_DELAY_HI 6
++#define CBR_RG_SX_SEL_DELAY_SZ 5
++#define CBR_RG_SX_REF_CYCLE_MSK 0x00000780
++#define CBR_RG_SX_REF_CYCLE_I_MSK 0xfffff87f
++#define CBR_RG_SX_REF_CYCLE_SFT 7
++#define CBR_RG_SX_REF_CYCLE_HI 10
++#define CBR_RG_SX_REF_CYCLE_SZ 4
++#define CBR_RG_SX_VCOBY16_MSK 0x00000800
++#define CBR_RG_SX_VCOBY16_I_MSK 0xfffff7ff
++#define CBR_RG_SX_VCOBY16_SFT 11
++#define CBR_RG_SX_VCOBY16_HI 11
++#define CBR_RG_SX_VCOBY16_SZ 1
++#define CBR_RG_SX_VCOBY32_MSK 0x00001000
++#define CBR_RG_SX_VCOBY32_I_MSK 0xffffefff
++#define CBR_RG_SX_VCOBY32_SFT 12
++#define CBR_RG_SX_VCOBY32_HI 12
++#define CBR_RG_SX_VCOBY32_SZ 1
++#define CBR_RG_SX_PH_MSK 0x00002000
++#define CBR_RG_SX_PH_I_MSK 0xffffdfff
++#define CBR_RG_SX_PH_SFT 13
++#define CBR_RG_SX_PH_HI 13
++#define CBR_RG_SX_PH_SZ 1
++#define CBR_RG_SX_PL_MSK 0x00004000
++#define CBR_RG_SX_PL_I_MSK 0xffffbfff
++#define CBR_RG_SX_PL_SFT 14
++#define CBR_RG_SX_PL_HI 14
++#define CBR_RG_SX_PL_SZ 1
++#define CBR_RG_SX_VT_MON_MODE_MSK 0x00000001
++#define CBR_RG_SX_VT_MON_MODE_I_MSK 0xfffffffe
++#define CBR_RG_SX_VT_MON_MODE_SFT 0
++#define CBR_RG_SX_VT_MON_MODE_HI 0
++#define CBR_RG_SX_VT_MON_MODE_SZ 1
++#define CBR_RG_SX_VT_TH_HI_MSK 0x00000006
++#define CBR_RG_SX_VT_TH_HI_I_MSK 0xfffffff9
++#define CBR_RG_SX_VT_TH_HI_SFT 1
++#define CBR_RG_SX_VT_TH_HI_HI 2
++#define CBR_RG_SX_VT_TH_HI_SZ 2
++#define CBR_RG_SX_VT_TH_LO_MSK 0x00000018
++#define CBR_RG_SX_VT_TH_LO_I_MSK 0xffffffe7
++#define CBR_RG_SX_VT_TH_LO_SFT 3
++#define CBR_RG_SX_VT_TH_LO_HI 4
++#define CBR_RG_SX_VT_TH_LO_SZ 2
++#define CBR_RG_SX_VT_SET_MSK 0x00000020
++#define CBR_RG_SX_VT_SET_I_MSK 0xffffffdf
++#define CBR_RG_SX_VT_SET_SFT 5
++#define CBR_RG_SX_VT_SET_HI 5
++#define CBR_RG_SX_VT_SET_SZ 1
++#define CBR_RG_SX_VT_MON_TMR_MSK 0x00007fc0
++#define CBR_RG_SX_VT_MON_TMR_I_MSK 0xffff803f
++#define CBR_RG_SX_VT_MON_TMR_SFT 6
++#define CBR_RG_SX_VT_MON_TMR_HI 14
++#define CBR_RG_SX_VT_MON_TMR_SZ 9
++#define CBR_RG_IDEAL_CYCLE_MSK 0x0fff8000
++#define CBR_RG_IDEAL_CYCLE_I_MSK 0xf0007fff
++#define CBR_RG_IDEAL_CYCLE_SFT 15
++#define CBR_RG_IDEAL_CYCLE_HI 27
++#define CBR_RG_IDEAL_CYCLE_SZ 13
++#define CBR_RG_EN_DP_VT_MON_MSK 0x00000001
++#define CBR_RG_EN_DP_VT_MON_I_MSK 0xfffffffe
++#define CBR_RG_EN_DP_VT_MON_SFT 0
++#define CBR_RG_EN_DP_VT_MON_HI 0
++#define CBR_RG_EN_DP_VT_MON_SZ 1
++#define CBR_RG_DP_VT_TH_HI_MSK 0x00000006
++#define CBR_RG_DP_VT_TH_HI_I_MSK 0xfffffff9
++#define CBR_RG_DP_VT_TH_HI_SFT 1
++#define CBR_RG_DP_VT_TH_HI_HI 2
++#define CBR_RG_DP_VT_TH_HI_SZ 2
++#define CBR_RG_DP_VT_TH_LO_MSK 0x00000018
++#define CBR_RG_DP_VT_TH_LO_I_MSK 0xffffffe7
++#define CBR_RG_DP_VT_TH_LO_SFT 3
++#define CBR_RG_DP_VT_TH_LO_HI 4
++#define CBR_RG_DP_VT_TH_LO_SZ 2
++#define CBR_RG_DP_VT_MON_TMR_MSK 0x00003fe0
++#define CBR_RG_DP_VT_MON_TMR_I_MSK 0xffffc01f
++#define CBR_RG_DP_VT_MON_TMR_SFT 5
++#define CBR_RG_DP_VT_MON_TMR_HI 13
++#define CBR_RG_DP_VT_MON_TMR_SZ 9
++#define CBR_RG_DP_CK320BY2_MSK 0x00004000
++#define CBR_RG_DP_CK320BY2_I_MSK 0xffffbfff
++#define CBR_RG_DP_CK320BY2_SFT 14
++#define CBR_RG_DP_CK320BY2_HI 14
++#define CBR_RG_DP_CK320BY2_SZ 1
++#define CBR_RG_SX_DELCTRL_MSK 0x001f8000
++#define CBR_RG_SX_DELCTRL_I_MSK 0xffe07fff
++#define CBR_RG_SX_DELCTRL_SFT 15
++#define CBR_RG_SX_DELCTRL_HI 20
++#define CBR_RG_SX_DELCTRL_SZ 6
++#define CBR_RG_DP_OD_TEST_MSK 0x00200000
++#define CBR_RG_DP_OD_TEST_I_MSK 0xffdfffff
++#define CBR_RG_DP_OD_TEST_SFT 21
++#define CBR_RG_DP_OD_TEST_HI 21
++#define CBR_RG_DP_OD_TEST_SZ 1
++#define CBR_RG_DP_BBPLL_BP_MSK 0x00000001
++#define CBR_RG_DP_BBPLL_BP_I_MSK 0xfffffffe
++#define CBR_RG_DP_BBPLL_BP_SFT 0
++#define CBR_RG_DP_BBPLL_BP_HI 0
++#define CBR_RG_DP_BBPLL_BP_SZ 1
++#define CBR_RG_DP_BBPLL_ICP_MSK 0x00000006
++#define CBR_RG_DP_BBPLL_ICP_I_MSK 0xfffffff9
++#define CBR_RG_DP_BBPLL_ICP_SFT 1
++#define CBR_RG_DP_BBPLL_ICP_HI 2
++#define CBR_RG_DP_BBPLL_ICP_SZ 2
++#define CBR_RG_DP_BBPLL_IDUAL_MSK 0x00000018
++#define CBR_RG_DP_BBPLL_IDUAL_I_MSK 0xffffffe7
++#define CBR_RG_DP_BBPLL_IDUAL_SFT 3
++#define CBR_RG_DP_BBPLL_IDUAL_HI 4
++#define CBR_RG_DP_BBPLL_IDUAL_SZ 2
++#define CBR_RG_DP_BBPLL_OD_TEST_MSK 0x000001e0
++#define CBR_RG_DP_BBPLL_OD_TEST_I_MSK 0xfffffe1f
++#define CBR_RG_DP_BBPLL_OD_TEST_SFT 5
++#define CBR_RG_DP_BBPLL_OD_TEST_HI 8
++#define CBR_RG_DP_BBPLL_OD_TEST_SZ 4
++#define CBR_RG_DP_BBPLL_PD_MSK 0x00000200
++#define CBR_RG_DP_BBPLL_PD_I_MSK 0xfffffdff
++#define CBR_RG_DP_BBPLL_PD_SFT 9
++#define CBR_RG_DP_BBPLL_PD_HI 9
++#define CBR_RG_DP_BBPLL_PD_SZ 1
++#define CBR_RG_DP_BBPLL_TESTSEL_MSK 0x00001c00
++#define CBR_RG_DP_BBPLL_TESTSEL_I_MSK 0xffffe3ff
++#define CBR_RG_DP_BBPLL_TESTSEL_SFT 10
++#define CBR_RG_DP_BBPLL_TESTSEL_HI 12
++#define CBR_RG_DP_BBPLL_TESTSEL_SZ 3
++#define CBR_RG_DP_BBPLL_PFD_DLY_MSK 0x00006000
++#define CBR_RG_DP_BBPLL_PFD_DLY_I_MSK 0xffff9fff
++#define CBR_RG_DP_BBPLL_PFD_DLY_SFT 13
++#define CBR_RG_DP_BBPLL_PFD_DLY_HI 14
++#define CBR_RG_DP_BBPLL_PFD_DLY_SZ 2
++#define CBR_RG_DP_RP_MSK 0x00038000
++#define CBR_RG_DP_RP_I_MSK 0xfffc7fff
++#define CBR_RG_DP_RP_SFT 15
++#define CBR_RG_DP_RP_HI 17
++#define CBR_RG_DP_RP_SZ 3
++#define CBR_RG_DP_RHP_MSK 0x000c0000
++#define CBR_RG_DP_RHP_I_MSK 0xfff3ffff
++#define CBR_RG_DP_RHP_SFT 18
++#define CBR_RG_DP_RHP_HI 19
++#define CBR_RG_DP_RHP_SZ 2
++#define CBR_RG_DP_DR3_MSK 0x00700000
++#define CBR_RG_DP_DR3_I_MSK 0xff8fffff
++#define CBR_RG_DP_DR3_SFT 20
++#define CBR_RG_DP_DR3_HI 22
++#define CBR_RG_DP_DR3_SZ 3
++#define CBR_RG_DP_DCP_MSK 0x07800000
++#define CBR_RG_DP_DCP_I_MSK 0xf87fffff
++#define CBR_RG_DP_DCP_SFT 23
++#define CBR_RG_DP_DCP_HI 26
++#define CBR_RG_DP_DCP_SZ 4
++#define CBR_RG_DP_DCS_MSK 0x78000000
++#define CBR_RG_DP_DCS_I_MSK 0x87ffffff
++#define CBR_RG_DP_DCS_SFT 27
++#define CBR_RG_DP_DCS_HI 30
++#define CBR_RG_DP_DCS_SZ 4
++#define CBR_RG_DP_FBDIV_MSK 0x00000fff
++#define CBR_RG_DP_FBDIV_I_MSK 0xfffff000
++#define CBR_RG_DP_FBDIV_SFT 0
++#define CBR_RG_DP_FBDIV_HI 11
++#define CBR_RG_DP_FBDIV_SZ 12
++#define CBR_RG_DP_FODIV_MSK 0x003ff000
++#define CBR_RG_DP_FODIV_I_MSK 0xffc00fff
++#define CBR_RG_DP_FODIV_SFT 12
++#define CBR_RG_DP_FODIV_HI 21
++#define CBR_RG_DP_FODIV_SZ 10
++#define CBR_RG_DP_REFDIV_MSK 0xffc00000
++#define CBR_RG_DP_REFDIV_I_MSK 0x003fffff
++#define CBR_RG_DP_REFDIV_SFT 22
++#define CBR_RG_DP_REFDIV_HI 31
++#define CBR_RG_DP_REFDIV_SZ 10
++#define CBR_RG_IDACAI_PGAG15_MSK 0x0000003f
++#define CBR_RG_IDACAI_PGAG15_I_MSK 0xffffffc0
++#define CBR_RG_IDACAI_PGAG15_SFT 0
++#define CBR_RG_IDACAI_PGAG15_HI 5
++#define CBR_RG_IDACAI_PGAG15_SZ 6
++#define CBR_RG_IDACAQ_PGAG15_MSK 0x00000fc0
++#define CBR_RG_IDACAQ_PGAG15_I_MSK 0xfffff03f
++#define CBR_RG_IDACAQ_PGAG15_SFT 6
++#define CBR_RG_IDACAQ_PGAG15_HI 11
++#define CBR_RG_IDACAQ_PGAG15_SZ 6
++#define CBR_RG_IDACAI_PGAG14_MSK 0x0003f000
++#define CBR_RG_IDACAI_PGAG14_I_MSK 0xfffc0fff
++#define CBR_RG_IDACAI_PGAG14_SFT 12
++#define CBR_RG_IDACAI_PGAG14_HI 17
++#define CBR_RG_IDACAI_PGAG14_SZ 6
++#define CBR_RG_IDACAQ_PGAG14_MSK 0x00fc0000
++#define CBR_RG_IDACAQ_PGAG14_I_MSK 0xff03ffff
++#define CBR_RG_IDACAQ_PGAG14_SFT 18
++#define CBR_RG_IDACAQ_PGAG14_HI 23
++#define CBR_RG_IDACAQ_PGAG14_SZ 6
++#define CBR_RG_IDACAI_PGAG13_MSK 0x0000003f
++#define CBR_RG_IDACAI_PGAG13_I_MSK 0xffffffc0
++#define CBR_RG_IDACAI_PGAG13_SFT 0
++#define CBR_RG_IDACAI_PGAG13_HI 5
++#define CBR_RG_IDACAI_PGAG13_SZ 6
++#define CBR_RG_IDACAQ_PGAG13_MSK 0x00000fc0
++#define CBR_RG_IDACAQ_PGAG13_I_MSK 0xfffff03f
++#define CBR_RG_IDACAQ_PGAG13_SFT 6
++#define CBR_RG_IDACAQ_PGAG13_HI 11
++#define CBR_RG_IDACAQ_PGAG13_SZ 6
++#define CBR_RG_IDACAI_PGAG12_MSK 0x0003f000
++#define CBR_RG_IDACAI_PGAG12_I_MSK 0xfffc0fff
++#define CBR_RG_IDACAI_PGAG12_SFT 12
++#define CBR_RG_IDACAI_PGAG12_HI 17
++#define CBR_RG_IDACAI_PGAG12_SZ 6
++#define CBR_RG_IDACAQ_PGAG12_MSK 0x00fc0000
++#define CBR_RG_IDACAQ_PGAG12_I_MSK 0xff03ffff
++#define CBR_RG_IDACAQ_PGAG12_SFT 18
++#define CBR_RG_IDACAQ_PGAG12_HI 23
++#define CBR_RG_IDACAQ_PGAG12_SZ 6
++#define CBR_RG_IDACAI_PGAG11_MSK 0x0000003f
++#define CBR_RG_IDACAI_PGAG11_I_MSK 0xffffffc0
++#define CBR_RG_IDACAI_PGAG11_SFT 0
++#define CBR_RG_IDACAI_PGAG11_HI 5
++#define CBR_RG_IDACAI_PGAG11_SZ 6
++#define CBR_RG_IDACAQ_PGAG11_MSK 0x00000fc0
++#define CBR_RG_IDACAQ_PGAG11_I_MSK 0xfffff03f
++#define CBR_RG_IDACAQ_PGAG11_SFT 6
++#define CBR_RG_IDACAQ_PGAG11_HI 11
++#define CBR_RG_IDACAQ_PGAG11_SZ 6
++#define CBR_RG_IDACAI_PGAG10_MSK 0x0003f000
++#define CBR_RG_IDACAI_PGAG10_I_MSK 0xfffc0fff
++#define CBR_RG_IDACAI_PGAG10_SFT 12
++#define CBR_RG_IDACAI_PGAG10_HI 17
++#define CBR_RG_IDACAI_PGAG10_SZ 6
++#define CBR_RG_IDACAQ_PGAG10_MSK 0x00fc0000
++#define CBR_RG_IDACAQ_PGAG10_I_MSK 0xff03ffff
++#define CBR_RG_IDACAQ_PGAG10_SFT 18
++#define CBR_RG_IDACAQ_PGAG10_HI 23
++#define CBR_RG_IDACAQ_PGAG10_SZ 6
++#define CBR_RG_IDACAI_PGAG9_MSK 0x0000003f
++#define CBR_RG_IDACAI_PGAG9_I_MSK 0xffffffc0
++#define CBR_RG_IDACAI_PGAG9_SFT 0
++#define CBR_RG_IDACAI_PGAG9_HI 5
++#define CBR_RG_IDACAI_PGAG9_SZ 6
++#define CBR_RG_IDACAQ_PGAG9_MSK 0x00000fc0
++#define CBR_RG_IDACAQ_PGAG9_I_MSK 0xfffff03f
++#define CBR_RG_IDACAQ_PGAG9_SFT 6
++#define CBR_RG_IDACAQ_PGAG9_HI 11
++#define CBR_RG_IDACAQ_PGAG9_SZ 6
++#define CBR_RG_IDACAI_PGAG8_MSK 0x0003f000
++#define CBR_RG_IDACAI_PGAG8_I_MSK 0xfffc0fff
++#define CBR_RG_IDACAI_PGAG8_SFT 12
++#define CBR_RG_IDACAI_PGAG8_HI 17
++#define CBR_RG_IDACAI_PGAG8_SZ 6
++#define CBR_RG_IDACAQ_PGAG8_MSK 0x00fc0000
++#define CBR_RG_IDACAQ_PGAG8_I_MSK 0xff03ffff
++#define CBR_RG_IDACAQ_PGAG8_SFT 18
++#define CBR_RG_IDACAQ_PGAG8_HI 23
++#define CBR_RG_IDACAQ_PGAG8_SZ 6
++#define CBR_RG_IDACAI_PGAG7_MSK 0x0000003f
++#define CBR_RG_IDACAI_PGAG7_I_MSK 0xffffffc0
++#define CBR_RG_IDACAI_PGAG7_SFT 0
++#define CBR_RG_IDACAI_PGAG7_HI 5
++#define CBR_RG_IDACAI_PGAG7_SZ 6
++#define CBR_RG_IDACAQ_PGAG7_MSK 0x00000fc0
++#define CBR_RG_IDACAQ_PGAG7_I_MSK 0xfffff03f
++#define CBR_RG_IDACAQ_PGAG7_SFT 6
++#define CBR_RG_IDACAQ_PGAG7_HI 11
++#define CBR_RG_IDACAQ_PGAG7_SZ 6
++#define CBR_RG_IDACAI_PGAG6_MSK 0x0003f000
++#define CBR_RG_IDACAI_PGAG6_I_MSK 0xfffc0fff
++#define CBR_RG_IDACAI_PGAG6_SFT 12
++#define CBR_RG_IDACAI_PGAG6_HI 17
++#define CBR_RG_IDACAI_PGAG6_SZ 6
++#define CBR_RG_IDACAQ_PGAG6_MSK 0x00fc0000
++#define CBR_RG_IDACAQ_PGAG6_I_MSK 0xff03ffff
++#define CBR_RG_IDACAQ_PGAG6_SFT 18
++#define CBR_RG_IDACAQ_PGAG6_HI 23
++#define CBR_RG_IDACAQ_PGAG6_SZ 6
++#define CBR_RG_IDACAI_PGAG5_MSK 0x0000003f
++#define CBR_RG_IDACAI_PGAG5_I_MSK 0xffffffc0
++#define CBR_RG_IDACAI_PGAG5_SFT 0
++#define CBR_RG_IDACAI_PGAG5_HI 5
++#define CBR_RG_IDACAI_PGAG5_SZ 6
++#define CBR_RG_IDACAQ_PGAG5_MSK 0x00000fc0
++#define CBR_RG_IDACAQ_PGAG5_I_MSK 0xfffff03f
++#define CBR_RG_IDACAQ_PGAG5_SFT 6
++#define CBR_RG_IDACAQ_PGAG5_HI 11
++#define CBR_RG_IDACAQ_PGAG5_SZ 6
++#define CBR_RG_IDACAI_PGAG4_MSK 0x0003f000
++#define CBR_RG_IDACAI_PGAG4_I_MSK 0xfffc0fff
++#define CBR_RG_IDACAI_PGAG4_SFT 12
++#define CBR_RG_IDACAI_PGAG4_HI 17
++#define CBR_RG_IDACAI_PGAG4_SZ 6
++#define CBR_RG_IDACAQ_PGAG4_MSK 0x00fc0000
++#define CBR_RG_IDACAQ_PGAG4_I_MSK 0xff03ffff
++#define CBR_RG_IDACAQ_PGAG4_SFT 18
++#define CBR_RG_IDACAQ_PGAG4_HI 23
++#define CBR_RG_IDACAQ_PGAG4_SZ 6
++#define CBR_RG_IDACAI_PGAG3_MSK 0x0000003f
++#define CBR_RG_IDACAI_PGAG3_I_MSK 0xffffffc0
++#define CBR_RG_IDACAI_PGAG3_SFT 0
++#define CBR_RG_IDACAI_PGAG3_HI 5
++#define CBR_RG_IDACAI_PGAG3_SZ 6
++#define CBR_RG_IDACAQ_PGAG3_MSK 0x00000fc0
++#define CBR_RG_IDACAQ_PGAG3_I_MSK 0xfffff03f
++#define CBR_RG_IDACAQ_PGAG3_SFT 6
++#define CBR_RG_IDACAQ_PGAG3_HI 11
++#define CBR_RG_IDACAQ_PGAG3_SZ 6
++#define CBR_RG_IDACAI_PGAG2_MSK 0x0003f000
++#define CBR_RG_IDACAI_PGAG2_I_MSK 0xfffc0fff
++#define CBR_RG_IDACAI_PGAG2_SFT 12
++#define CBR_RG_IDACAI_PGAG2_HI 17
++#define CBR_RG_IDACAI_PGAG2_SZ 6
++#define CBR_RG_IDACAQ_PGAG2_MSK 0x00fc0000
++#define CBR_RG_IDACAQ_PGAG2_I_MSK 0xff03ffff
++#define CBR_RG_IDACAQ_PGAG2_SFT 18
++#define CBR_RG_IDACAQ_PGAG2_HI 23
++#define CBR_RG_IDACAQ_PGAG2_SZ 6
++#define CBR_RG_IDACAI_PGAG1_MSK 0x0000003f
++#define CBR_RG_IDACAI_PGAG1_I_MSK 0xffffffc0
++#define CBR_RG_IDACAI_PGAG1_SFT 0
++#define CBR_RG_IDACAI_PGAG1_HI 5
++#define CBR_RG_IDACAI_PGAG1_SZ 6
++#define CBR_RG_IDACAQ_PGAG1_MSK 0x00000fc0
++#define CBR_RG_IDACAQ_PGAG1_I_MSK 0xfffff03f
++#define CBR_RG_IDACAQ_PGAG1_SFT 6
++#define CBR_RG_IDACAQ_PGAG1_HI 11
++#define CBR_RG_IDACAQ_PGAG1_SZ 6
++#define CBR_RG_IDACAI_PGAG0_MSK 0x0003f000
++#define CBR_RG_IDACAI_PGAG0_I_MSK 0xfffc0fff
++#define CBR_RG_IDACAI_PGAG0_SFT 12
++#define CBR_RG_IDACAI_PGAG0_HI 17
++#define CBR_RG_IDACAI_PGAG0_SZ 6
++#define CBR_RG_IDACAQ_PGAG0_MSK 0x00fc0000
++#define CBR_RG_IDACAQ_PGAG0_I_MSK 0xff03ffff
++#define CBR_RG_IDACAQ_PGAG0_SFT 18
++#define CBR_RG_IDACAQ_PGAG0_HI 23
++#define CBR_RG_IDACAQ_PGAG0_SZ 6
++#define CBR_RG_EN_RCAL_MSK 0x00000001
++#define CBR_RG_EN_RCAL_I_MSK 0xfffffffe
++#define CBR_RG_EN_RCAL_SFT 0
++#define CBR_RG_EN_RCAL_HI 0
++#define CBR_RG_EN_RCAL_SZ 1
++#define CBR_RG_RCAL_SPD_MSK 0x00000002
++#define CBR_RG_RCAL_SPD_I_MSK 0xfffffffd
++#define CBR_RG_RCAL_SPD_SFT 1
++#define CBR_RG_RCAL_SPD_HI 1
++#define CBR_RG_RCAL_SPD_SZ 1
++#define CBR_RG_RCAL_TMR_MSK 0x000001fc
++#define CBR_RG_RCAL_TMR_I_MSK 0xfffffe03
++#define CBR_RG_RCAL_TMR_SFT 2
++#define CBR_RG_RCAL_TMR_HI 8
++#define CBR_RG_RCAL_TMR_SZ 7
++#define CBR_RG_RCAL_CODE_CWR_MSK 0x00000200
++#define CBR_RG_RCAL_CODE_CWR_I_MSK 0xfffffdff
++#define CBR_RG_RCAL_CODE_CWR_SFT 9
++#define CBR_RG_RCAL_CODE_CWR_HI 9
++#define CBR_RG_RCAL_CODE_CWR_SZ 1
++#define CBR_RG_RCAL_CODE_CWD_MSK 0x00007c00
++#define CBR_RG_RCAL_CODE_CWD_I_MSK 0xffff83ff
++#define CBR_RG_RCAL_CODE_CWD_SFT 10
++#define CBR_RG_RCAL_CODE_CWD_HI 14
++#define CBR_RG_RCAL_CODE_CWD_SZ 5
++#define CBR_RG_SX_SUB_SEL_CWR_MSK 0x00000001
++#define CBR_RG_SX_SUB_SEL_CWR_I_MSK 0xfffffffe
++#define CBR_RG_SX_SUB_SEL_CWR_SFT 0
++#define CBR_RG_SX_SUB_SEL_CWR_HI 0
++#define CBR_RG_SX_SUB_SEL_CWR_SZ 1
++#define CBR_RG_SX_SUB_SEL_CWD_MSK 0x000000fe
++#define CBR_RG_SX_SUB_SEL_CWD_I_MSK 0xffffff01
++#define CBR_RG_SX_SUB_SEL_CWD_SFT 1
++#define CBR_RG_SX_SUB_SEL_CWD_HI 7
++#define CBR_RG_SX_SUB_SEL_CWD_SZ 7
++#define CBR_RG_DP_BBPLL_BS_CWR_MSK 0x00000100
++#define CBR_RG_DP_BBPLL_BS_CWR_I_MSK 0xfffffeff
++#define CBR_RG_DP_BBPLL_BS_CWR_SFT 8
++#define CBR_RG_DP_BBPLL_BS_CWR_HI 8
++#define CBR_RG_DP_BBPLL_BS_CWR_SZ 1
++#define CBR_RG_DP_BBPLL_BS_CWD_MSK 0x00007e00
++#define CBR_RG_DP_BBPLL_BS_CWD_I_MSK 0xffff81ff
++#define CBR_RG_DP_BBPLL_BS_CWD_SFT 9
++#define CBR_RG_DP_BBPLL_BS_CWD_HI 14
++#define CBR_RG_DP_BBPLL_BS_CWD_SZ 6
++#define CBR_RCAL_RDY_MSK 0x00000001
++#define CBR_RCAL_RDY_I_MSK 0xfffffffe
++#define CBR_RCAL_RDY_SFT 0
++#define CBR_RCAL_RDY_HI 0
++#define CBR_RCAL_RDY_SZ 1
++#define CBR_DA_LCK_RDY_MSK 0x00000002
++#define CBR_DA_LCK_RDY_I_MSK 0xfffffffd
++#define CBR_DA_LCK_RDY_SFT 1
++#define CBR_DA_LCK_RDY_HI 1
++#define CBR_DA_LCK_RDY_SZ 1
++#define CBR_VT_MON_RDY_MSK 0x00000004
++#define CBR_VT_MON_RDY_I_MSK 0xfffffffb
++#define CBR_VT_MON_RDY_SFT 2
++#define CBR_VT_MON_RDY_HI 2
++#define CBR_VT_MON_RDY_SZ 1
++#define CBR_DP_VT_MON_RDY_MSK 0x00000008
++#define CBR_DP_VT_MON_RDY_I_MSK 0xfffffff7
++#define CBR_DP_VT_MON_RDY_SFT 3
++#define CBR_DP_VT_MON_RDY_HI 3
++#define CBR_DP_VT_MON_RDY_SZ 1
++#define CBR_CH_RDY_MSK 0x00000010
++#define CBR_CH_RDY_I_MSK 0xffffffef
++#define CBR_CH_RDY_SFT 4
++#define CBR_CH_RDY_HI 4
++#define CBR_CH_RDY_SZ 1
++#define CBR_DA_R_CODE_LUT_MSK 0x000007c0
++#define CBR_DA_R_CODE_LUT_I_MSK 0xfffff83f
++#define CBR_DA_R_CODE_LUT_SFT 6
++#define CBR_DA_R_CODE_LUT_HI 10
++#define CBR_DA_R_CODE_LUT_SZ 5
++#define CBR_AD_SX_VT_MON_Q_MSK 0x00001800
++#define CBR_AD_SX_VT_MON_Q_I_MSK 0xffffe7ff
++#define CBR_AD_SX_VT_MON_Q_SFT 11
++#define CBR_AD_SX_VT_MON_Q_HI 12
++#define CBR_AD_SX_VT_MON_Q_SZ 2
++#define CBR_AD_DP_VT_MON_Q_MSK 0x00006000
++#define CBR_AD_DP_VT_MON_Q_I_MSK 0xffff9fff
++#define CBR_AD_DP_VT_MON_Q_SFT 13
++#define CBR_AD_DP_VT_MON_Q_HI 14
++#define CBR_AD_DP_VT_MON_Q_SZ 2
++#define CBR_DA_R_CAL_CODE_MSK 0x0000001f
++#define CBR_DA_R_CAL_CODE_I_MSK 0xffffffe0
++#define CBR_DA_R_CAL_CODE_SFT 0
++#define CBR_DA_R_CAL_CODE_HI 4
++#define CBR_DA_R_CAL_CODE_SZ 5
++#define CBR_DA_SX_SUB_SEL_MSK 0x00000fe0
++#define CBR_DA_SX_SUB_SEL_I_MSK 0xfffff01f
++#define CBR_DA_SX_SUB_SEL_SFT 5
++#define CBR_DA_SX_SUB_SEL_HI 11
++#define CBR_DA_SX_SUB_SEL_SZ 7
++#define CBR_DA_DP_BBPLL_BS_MSK 0x0003f000
++#define CBR_DA_DP_BBPLL_BS_I_MSK 0xfffc0fff
++#define CBR_DA_DP_BBPLL_BS_SFT 12
++#define CBR_DA_DP_BBPLL_BS_HI 17
++#define CBR_DA_DP_BBPLL_BS_SZ 6
++#define CBR_TX_EN_MSK 0x00000001
++#define CBR_TX_EN_I_MSK 0xfffffffe
++#define CBR_TX_EN_SFT 0
++#define CBR_TX_EN_HI 0
++#define CBR_TX_EN_SZ 1
++#define CBR_TX_CNT_RST_MSK 0x00000002
++#define CBR_TX_CNT_RST_I_MSK 0xfffffffd
++#define CBR_TX_CNT_RST_SFT 1
++#define CBR_TX_CNT_RST_HI 1
++#define CBR_TX_CNT_RST_SZ 1
++#define CBR_IFS_TIME_MSK 0x000000fc
++#define CBR_IFS_TIME_I_MSK 0xffffff03
++#define CBR_IFS_TIME_SFT 2
++#define CBR_IFS_TIME_HI 7
++#define CBR_IFS_TIME_SZ 6
++#define CBR_LENGTH_TARGET_MSK 0x000fff00
++#define CBR_LENGTH_TARGET_I_MSK 0xfff000ff
++#define CBR_LENGTH_TARGET_SFT 8
++#define CBR_LENGTH_TARGET_HI 19
++#define CBR_LENGTH_TARGET_SZ 12
++#define CBR_TX_CNT_TARGET_MSK 0xff000000
++#define CBR_TX_CNT_TARGET_I_MSK 0x00ffffff
++#define CBR_TX_CNT_TARGET_SFT 24
++#define CBR_TX_CNT_TARGET_HI 31
++#define CBR_TX_CNT_TARGET_SZ 8
++#define CBR_TC_CNT_TARGET_MSK 0x00ffffff
++#define CBR_TC_CNT_TARGET_I_MSK 0xff000000
++#define CBR_TC_CNT_TARGET_SFT 0
++#define CBR_TC_CNT_TARGET_HI 23
++#define CBR_TC_CNT_TARGET_SZ 24
++#define CBR_PLCP_PSDU_DATA_MEM_MSK 0x000000ff
++#define CBR_PLCP_PSDU_DATA_MEM_I_MSK 0xffffff00
++#define CBR_PLCP_PSDU_DATA_MEM_SFT 0
++#define CBR_PLCP_PSDU_DATA_MEM_HI 7
++#define CBR_PLCP_PSDU_DATA_MEM_SZ 8
++#define CBR_PLCP_PSDU_PREAMBLE_SHORT_MSK 0x00000100
++#define CBR_PLCP_PSDU_PREAMBLE_SHORT_I_MSK 0xfffffeff
++#define CBR_PLCP_PSDU_PREAMBLE_SHORT_SFT 8
++#define CBR_PLCP_PSDU_PREAMBLE_SHORT_HI 8
++#define CBR_PLCP_PSDU_PREAMBLE_SHORT_SZ 1
++#define CBR_PLCP_BYTE_LENGTH_MSK 0x001ffe00
++#define CBR_PLCP_BYTE_LENGTH_I_MSK 0xffe001ff
++#define CBR_PLCP_BYTE_LENGTH_SFT 9
++#define CBR_PLCP_BYTE_LENGTH_HI 20
++#define CBR_PLCP_BYTE_LENGTH_SZ 12
++#define CBR_PLCP_PSDU_RATE_MSK 0x00600000
++#define CBR_PLCP_PSDU_RATE_I_MSK 0xff9fffff
++#define CBR_PLCP_PSDU_RATE_SFT 21
++#define CBR_PLCP_PSDU_RATE_HI 22
++#define CBR_PLCP_PSDU_RATE_SZ 2
++#define CBR_TAIL_TIME_MSK 0x1f800000
++#define CBR_TAIL_TIME_I_MSK 0xe07fffff
++#define CBR_TAIL_TIME_SFT 23
++#define CBR_TAIL_TIME_HI 28
++#define CBR_TAIL_TIME_SZ 6
++#define CBR_RG_O_PAD_PD_MSK 0x00000001
++#define CBR_RG_O_PAD_PD_I_MSK 0xfffffffe
++#define CBR_RG_O_PAD_PD_SFT 0
++#define CBR_RG_O_PAD_PD_HI 0
++#define CBR_RG_O_PAD_PD_SZ 1
++#define CBR_RG_I_PAD_PD_MSK 0x00000002
++#define CBR_RG_I_PAD_PD_I_MSK 0xfffffffd
++#define CBR_RG_I_PAD_PD_SFT 1
++#define CBR_RG_I_PAD_PD_HI 1
++#define CBR_RG_I_PAD_PD_SZ 1
++#define CBR_SEL_ADCKP_INV_MSK 0x00000004
++#define CBR_SEL_ADCKP_INV_I_MSK 0xfffffffb
++#define CBR_SEL_ADCKP_INV_SFT 2
++#define CBR_SEL_ADCKP_INV_HI 2
++#define CBR_SEL_ADCKP_INV_SZ 1
++#define CBR_RG_PAD_DS_MSK 0x00000008
++#define CBR_RG_PAD_DS_I_MSK 0xfffffff7
++#define CBR_RG_PAD_DS_SFT 3
++#define CBR_RG_PAD_DS_HI 3
++#define CBR_RG_PAD_DS_SZ 1
++#define CBR_SEL_ADCKP_MUX_MSK 0x00000010
++#define CBR_SEL_ADCKP_MUX_I_MSK 0xffffffef
++#define CBR_SEL_ADCKP_MUX_SFT 4
++#define CBR_SEL_ADCKP_MUX_HI 4
++#define CBR_SEL_ADCKP_MUX_SZ 1
++#define CBR_RG_PAD_DS_CLK_MSK 0x00000020
++#define CBR_RG_PAD_DS_CLK_I_MSK 0xffffffdf
++#define CBR_RG_PAD_DS_CLK_SFT 5
++#define CBR_RG_PAD_DS_CLK_HI 5
++#define CBR_RG_PAD_DS_CLK_SZ 1
++#define CBR_INTP_SEL_MSK 0x00000200
++#define CBR_INTP_SEL_I_MSK 0xfffffdff
++#define CBR_INTP_SEL_SFT 9
++#define CBR_INTP_SEL_HI 9
++#define CBR_INTP_SEL_SZ 1
++#define CBR_IQ_SWP_MSK 0x00000400
++#define CBR_IQ_SWP_I_MSK 0xfffffbff
++#define CBR_IQ_SWP_SFT 10
++#define CBR_IQ_SWP_HI 10
++#define CBR_IQ_SWP_SZ 1
++#define CBR_RG_EN_EXT_DA_MSK 0x00000800
++#define CBR_RG_EN_EXT_DA_I_MSK 0xfffff7ff
++#define CBR_RG_EN_EXT_DA_SFT 11
++#define CBR_RG_EN_EXT_DA_HI 11
++#define CBR_RG_EN_EXT_DA_SZ 1
++#define CBR_RG_DIS_DA_OFFSET_MSK 0x00001000
++#define CBR_RG_DIS_DA_OFFSET_I_MSK 0xffffefff
++#define CBR_RG_DIS_DA_OFFSET_SFT 12
++#define CBR_RG_DIS_DA_OFFSET_HI 12
++#define CBR_RG_DIS_DA_OFFSET_SZ 1
++#define CBR_DBG_SEL_MSK 0x000f0000
++#define CBR_DBG_SEL_I_MSK 0xfff0ffff
++#define CBR_DBG_SEL_SFT 16
++#define CBR_DBG_SEL_HI 19
++#define CBR_DBG_SEL_SZ 4
++#define CBR_DBG_EN_MSK 0x00100000
++#define CBR_DBG_EN_I_MSK 0xffefffff
++#define CBR_DBG_EN_SFT 20
++#define CBR_DBG_EN_HI 20
++#define CBR_DBG_EN_SZ 1
++#define CBR_RG_PKT_GEN_TX_CNT_MSK 0xffffffff
++#define CBR_RG_PKT_GEN_TX_CNT_I_MSK 0x00000000
++#define CBR_RG_PKT_GEN_TX_CNT_SFT 0
++#define CBR_RG_PKT_GEN_TX_CNT_HI 31
++#define CBR_RG_PKT_GEN_TX_CNT_SZ 32
++#define CBR_TP_SEL_MSK 0x0000001f
++#define CBR_TP_SEL_I_MSK 0xffffffe0
++#define CBR_TP_SEL_SFT 0
++#define CBR_TP_SEL_HI 4
++#define CBR_TP_SEL_SZ 5
++#define CBR_IDEAL_IQ_EN_MSK 0x00000020
++#define CBR_IDEAL_IQ_EN_I_MSK 0xffffffdf
++#define CBR_IDEAL_IQ_EN_SFT 5
++#define CBR_IDEAL_IQ_EN_HI 5
++#define CBR_IDEAL_IQ_EN_SZ 1
++#define CBR_DATA_OUT_SEL_MSK 0x000001c0
++#define CBR_DATA_OUT_SEL_I_MSK 0xfffffe3f
++#define CBR_DATA_OUT_SEL_SFT 6
++#define CBR_DATA_OUT_SEL_HI 8
++#define CBR_DATA_OUT_SEL_SZ 3
++#define CBR_TWO_TONE_EN_MSK 0x00000200
++#define CBR_TWO_TONE_EN_I_MSK 0xfffffdff
++#define CBR_TWO_TONE_EN_SFT 9
++#define CBR_TWO_TONE_EN_HI 9
++#define CBR_TWO_TONE_EN_SZ 1
++#define CBR_FREQ_SEL_MSK 0x00ff0000
++#define CBR_FREQ_SEL_I_MSK 0xff00ffff
++#define CBR_FREQ_SEL_SFT 16
++#define CBR_FREQ_SEL_HI 23
++#define CBR_FREQ_SEL_SZ 8
++#define CBR_IQ_SCALE_MSK 0xff000000
++#define CBR_IQ_SCALE_I_MSK 0x00ffffff
++#define CBR_IQ_SCALE_SFT 24
++#define CBR_IQ_SCALE_HI 31
++#define CBR_IQ_SCALE_SZ 8
++#define CPU_QUE_POP_MSK 0x00000001
++#define CPU_QUE_POP_I_MSK 0xfffffffe
++#define CPU_QUE_POP_SFT 0
++#define CPU_QUE_POP_HI 0
++#define CPU_QUE_POP_SZ 1
++#define CPU_INT_MSK 0x00000004
++#define CPU_INT_I_MSK 0xfffffffb
++#define CPU_INT_SFT 2
++#define CPU_INT_HI 2
++#define CPU_INT_SZ 1
++#define CPU_ID_TB0_MSK 0xffffffff
++#define CPU_ID_TB0_I_MSK 0x00000000
++#define CPU_ID_TB0_SFT 0
++#define CPU_ID_TB0_HI 31
++#define CPU_ID_TB0_SZ 32
++#define CPU_ID_TB1_MSK 0xffffffff
++#define CPU_ID_TB1_I_MSK 0x00000000
++#define CPU_ID_TB1_SFT 0
++#define CPU_ID_TB1_HI 31
++#define CPU_ID_TB1_SZ 32
++#define HW_PKTID_MSK 0x000007ff
++#define HW_PKTID_I_MSK 0xfffff800
++#define HW_PKTID_SFT 0
++#define HW_PKTID_HI 10
++#define HW_PKTID_SZ 11
++#define CH0_INT_ADDR_MSK 0xffffffff
++#define CH0_INT_ADDR_I_MSK 0x00000000
++#define CH0_INT_ADDR_SFT 0
++#define CH0_INT_ADDR_HI 31
++#define CH0_INT_ADDR_SZ 32
++#define PRI_HW_PKTID_MSK 0x000007ff
++#define PRI_HW_PKTID_I_MSK 0xfffff800
++#define PRI_HW_PKTID_SFT 0
++#define PRI_HW_PKTID_HI 10
++#define PRI_HW_PKTID_SZ 11
++#define CH0_FULL_MSK 0x00000001
++#define CH0_FULL_I_MSK 0xfffffffe
++#define CH0_FULL_SFT 0
++#define CH0_FULL_HI 0
++#define CH0_FULL_SZ 1
++#define FF0_EMPTY_MSK 0x00000002
++#define FF0_EMPTY_I_MSK 0xfffffffd
++#define FF0_EMPTY_SFT 1
++#define FF0_EMPTY_HI 1
++#define FF0_EMPTY_SZ 1
++#define RLS_BUSY_MSK 0x00000200
++#define RLS_BUSY_I_MSK 0xfffffdff
++#define RLS_BUSY_SFT 9
++#define RLS_BUSY_HI 9
++#define RLS_BUSY_SZ 1
++#define RLS_COUNT_CLR_MSK 0x00000400
++#define RLS_COUNT_CLR_I_MSK 0xfffffbff
++#define RLS_COUNT_CLR_SFT 10
++#define RLS_COUNT_CLR_HI 10
++#define RLS_COUNT_CLR_SZ 1
++#define RTN_COUNT_CLR_MSK 0x00000800
++#define RTN_COUNT_CLR_I_MSK 0xfffff7ff
++#define RTN_COUNT_CLR_SFT 11
++#define RTN_COUNT_CLR_HI 11
++#define RTN_COUNT_CLR_SZ 1
++#define RLS_COUNT_MSK 0x00ff0000
++#define RLS_COUNT_I_MSK 0xff00ffff
++#define RLS_COUNT_SFT 16
++#define RLS_COUNT_HI 23
++#define RLS_COUNT_SZ 8
++#define RTN_COUNT_MSK 0xff000000
++#define RTN_COUNT_I_MSK 0x00ffffff
++#define RTN_COUNT_SFT 24
++#define RTN_COUNT_HI 31
++#define RTN_COUNT_SZ 8
++#define FF0_CNT_MSK 0x0000001f
++#define FF0_CNT_I_MSK 0xffffffe0
++#define FF0_CNT_SFT 0
++#define FF0_CNT_HI 4
++#define FF0_CNT_SZ 5
++#define FF1_CNT_MSK 0x000001e0
++#define FF1_CNT_I_MSK 0xfffffe1f
++#define FF1_CNT_SFT 5
++#define FF1_CNT_HI 8
++#define FF1_CNT_SZ 4
++#define FF3_CNT_MSK 0x00003800
++#define FF3_CNT_I_MSK 0xffffc7ff
++#define FF3_CNT_SFT 11
++#define FF3_CNT_HI 13
++#define FF3_CNT_SZ 3
++#define FF5_CNT_MSK 0x000e0000
++#define FF5_CNT_I_MSK 0xfff1ffff
++#define FF5_CNT_SFT 17
++#define FF5_CNT_HI 19
++#define FF5_CNT_SZ 3
++#define FF6_CNT_MSK 0x00700000
++#define FF6_CNT_I_MSK 0xff8fffff
++#define FF6_CNT_SFT 20
++#define FF6_CNT_HI 22
++#define FF6_CNT_SZ 3
++#define FF7_CNT_MSK 0x03800000
++#define FF7_CNT_I_MSK 0xfc7fffff
++#define FF7_CNT_SFT 23
++#define FF7_CNT_HI 25
++#define FF7_CNT_SZ 3
++#define FF8_CNT_MSK 0x1c000000
++#define FF8_CNT_I_MSK 0xe3ffffff
++#define FF8_CNT_SFT 26
++#define FF8_CNT_HI 28
++#define FF8_CNT_SZ 3
++#define FF9_CNT_MSK 0xe0000000
++#define FF9_CNT_I_MSK 0x1fffffff
++#define FF9_CNT_SFT 29
++#define FF9_CNT_HI 31
++#define FF9_CNT_SZ 3
++#define FF10_CNT_MSK 0x00000007
++#define FF10_CNT_I_MSK 0xfffffff8
++#define FF10_CNT_SFT 0
++#define FF10_CNT_HI 2
++#define FF10_CNT_SZ 3
++#define FF11_CNT_MSK 0x00000038
++#define FF11_CNT_I_MSK 0xffffffc7
++#define FF11_CNT_SFT 3
++#define FF11_CNT_HI 5
++#define FF11_CNT_SZ 3
++#define FF12_CNT_MSK 0x000001c0
++#define FF12_CNT_I_MSK 0xfffffe3f
++#define FF12_CNT_SFT 6
++#define FF12_CNT_HI 8
++#define FF12_CNT_SZ 3
++#define FF13_CNT_MSK 0x00000600
++#define FF13_CNT_I_MSK 0xfffff9ff
++#define FF13_CNT_SFT 9
++#define FF13_CNT_HI 10
++#define FF13_CNT_SZ 2
++#define FF14_CNT_MSK 0x00001800
++#define FF14_CNT_I_MSK 0xffffe7ff
++#define FF14_CNT_SFT 11
++#define FF14_CNT_HI 12
++#define FF14_CNT_SZ 2
++#define FF15_CNT_MSK 0x00006000
++#define FF15_CNT_I_MSK 0xffff9fff
++#define FF15_CNT_SFT 13
++#define FF15_CNT_HI 14
++#define FF15_CNT_SZ 2
++#define FF4_CNT_MSK 0x000f8000
++#define FF4_CNT_I_MSK 0xfff07fff
++#define FF4_CNT_SFT 15
++#define FF4_CNT_HI 19
++#define FF4_CNT_SZ 5
++#define FF2_CNT_MSK 0x00700000
++#define FF2_CNT_I_MSK 0xff8fffff
++#define FF2_CNT_SFT 20
++#define FF2_CNT_HI 22
++#define FF2_CNT_SZ 3
++#define CH1_FULL_MSK 0x00000002
++#define CH1_FULL_I_MSK 0xfffffffd
++#define CH1_FULL_SFT 1
++#define CH1_FULL_HI 1
++#define CH1_FULL_SZ 1
++#define CH2_FULL_MSK 0x00000004
++#define CH2_FULL_I_MSK 0xfffffffb
++#define CH2_FULL_SFT 2
++#define CH2_FULL_HI 2
++#define CH2_FULL_SZ 1
++#define CH3_FULL_MSK 0x00000008
++#define CH3_FULL_I_MSK 0xfffffff7
++#define CH3_FULL_SFT 3
++#define CH3_FULL_HI 3
++#define CH3_FULL_SZ 1
++#define CH4_FULL_MSK 0x00000010
++#define CH4_FULL_I_MSK 0xffffffef
++#define CH4_FULL_SFT 4
++#define CH4_FULL_HI 4
++#define CH4_FULL_SZ 1
++#define CH5_FULL_MSK 0x00000020
++#define CH5_FULL_I_MSK 0xffffffdf
++#define CH5_FULL_SFT 5
++#define CH5_FULL_HI 5
++#define CH5_FULL_SZ 1
++#define CH6_FULL_MSK 0x00000040
++#define CH6_FULL_I_MSK 0xffffffbf
++#define CH6_FULL_SFT 6
++#define CH6_FULL_HI 6
++#define CH6_FULL_SZ 1
++#define CH7_FULL_MSK 0x00000080
++#define CH7_FULL_I_MSK 0xffffff7f
++#define CH7_FULL_SFT 7
++#define CH7_FULL_HI 7
++#define CH7_FULL_SZ 1
++#define CH8_FULL_MSK 0x00000100
++#define CH8_FULL_I_MSK 0xfffffeff
++#define CH8_FULL_SFT 8
++#define CH8_FULL_HI 8
++#define CH8_FULL_SZ 1
++#define CH9_FULL_MSK 0x00000200
++#define CH9_FULL_I_MSK 0xfffffdff
++#define CH9_FULL_SFT 9
++#define CH9_FULL_HI 9
++#define CH9_FULL_SZ 1
++#define CH10_FULL_MSK 0x00000400
++#define CH10_FULL_I_MSK 0xfffffbff
++#define CH10_FULL_SFT 10
++#define CH10_FULL_HI 10
++#define CH10_FULL_SZ 1
++#define CH11_FULL_MSK 0x00000800
++#define CH11_FULL_I_MSK 0xfffff7ff
++#define CH11_FULL_SFT 11
++#define CH11_FULL_HI 11
++#define CH11_FULL_SZ 1
++#define CH12_FULL_MSK 0x00001000
++#define CH12_FULL_I_MSK 0xffffefff
++#define CH12_FULL_SFT 12
++#define CH12_FULL_HI 12
++#define CH12_FULL_SZ 1
++#define CH13_FULL_MSK 0x00002000
++#define CH13_FULL_I_MSK 0xffffdfff
++#define CH13_FULL_SFT 13
++#define CH13_FULL_HI 13
++#define CH13_FULL_SZ 1
++#define CH14_FULL_MSK 0x00004000
++#define CH14_FULL_I_MSK 0xffffbfff
++#define CH14_FULL_SFT 14
++#define CH14_FULL_HI 14
++#define CH14_FULL_SZ 1
++#define CH15_FULL_MSK 0x00008000
++#define CH15_FULL_I_MSK 0xffff7fff
++#define CH15_FULL_SFT 15
++#define CH15_FULL_HI 15
++#define CH15_FULL_SZ 1
++#define HALT_CH0_MSK 0x00000001
++#define HALT_CH0_I_MSK 0xfffffffe
++#define HALT_CH0_SFT 0
++#define HALT_CH0_HI 0
++#define HALT_CH0_SZ 1
++#define HALT_CH1_MSK 0x00000002
++#define HALT_CH1_I_MSK 0xfffffffd
++#define HALT_CH1_SFT 1
++#define HALT_CH1_HI 1
++#define HALT_CH1_SZ 1
++#define HALT_CH2_MSK 0x00000004
++#define HALT_CH2_I_MSK 0xfffffffb
++#define HALT_CH2_SFT 2
++#define HALT_CH2_HI 2
++#define HALT_CH2_SZ 1
++#define HALT_CH3_MSK 0x00000008
++#define HALT_CH3_I_MSK 0xfffffff7
++#define HALT_CH3_SFT 3
++#define HALT_CH3_HI 3
++#define HALT_CH3_SZ 1
++#define HALT_CH4_MSK 0x00000010
++#define HALT_CH4_I_MSK 0xffffffef
++#define HALT_CH4_SFT 4
++#define HALT_CH4_HI 4
++#define HALT_CH4_SZ 1
++#define HALT_CH5_MSK 0x00000020
++#define HALT_CH5_I_MSK 0xffffffdf
++#define HALT_CH5_SFT 5
++#define HALT_CH5_HI 5
++#define HALT_CH5_SZ 1
++#define HALT_CH6_MSK 0x00000040
++#define HALT_CH6_I_MSK 0xffffffbf
++#define HALT_CH6_SFT 6
++#define HALT_CH6_HI 6
++#define HALT_CH6_SZ 1
++#define HALT_CH7_MSK 0x00000080
++#define HALT_CH7_I_MSK 0xffffff7f
++#define HALT_CH7_SFT 7
++#define HALT_CH7_HI 7
++#define HALT_CH7_SZ 1
++#define HALT_CH8_MSK 0x00000100
++#define HALT_CH8_I_MSK 0xfffffeff
++#define HALT_CH8_SFT 8
++#define HALT_CH8_HI 8
++#define HALT_CH8_SZ 1
++#define HALT_CH9_MSK 0x00000200
++#define HALT_CH9_I_MSK 0xfffffdff
++#define HALT_CH9_SFT 9
++#define HALT_CH9_HI 9
++#define HALT_CH9_SZ 1
++#define HALT_CH10_MSK 0x00000400
++#define HALT_CH10_I_MSK 0xfffffbff
++#define HALT_CH10_SFT 10
++#define HALT_CH10_HI 10
++#define HALT_CH10_SZ 1
++#define HALT_CH11_MSK 0x00000800
++#define HALT_CH11_I_MSK 0xfffff7ff
++#define HALT_CH11_SFT 11
++#define HALT_CH11_HI 11
++#define HALT_CH11_SZ 1
++#define HALT_CH12_MSK 0x00001000
++#define HALT_CH12_I_MSK 0xffffefff
++#define HALT_CH12_SFT 12
++#define HALT_CH12_HI 12
++#define HALT_CH12_SZ 1
++#define HALT_CH13_MSK 0x00002000
++#define HALT_CH13_I_MSK 0xffffdfff
++#define HALT_CH13_SFT 13
++#define HALT_CH13_HI 13
++#define HALT_CH13_SZ 1
++#define HALT_CH14_MSK 0x00004000
++#define HALT_CH14_I_MSK 0xffffbfff
++#define HALT_CH14_SFT 14
++#define HALT_CH14_HI 14
++#define HALT_CH14_SZ 1
++#define HALT_CH15_MSK 0x00008000
++#define HALT_CH15_I_MSK 0xffff7fff
++#define HALT_CH15_SFT 15
++#define HALT_CH15_HI 15
++#define HALT_CH15_SZ 1
++#define STOP_MBOX_MSK 0x00010000
++#define STOP_MBOX_I_MSK 0xfffeffff
++#define STOP_MBOX_SFT 16
++#define STOP_MBOX_HI 16
++#define STOP_MBOX_SZ 1
++#define MB_ERR_AUTO_HALT_EN_MSK 0x00100000
++#define MB_ERR_AUTO_HALT_EN_I_MSK 0xffefffff
++#define MB_ERR_AUTO_HALT_EN_SFT 20
++#define MB_ERR_AUTO_HALT_EN_HI 20
++#define MB_ERR_AUTO_HALT_EN_SZ 1
++#define MB_EXCEPT_CLR_MSK 0x00200000
++#define MB_EXCEPT_CLR_I_MSK 0xffdfffff
++#define MB_EXCEPT_CLR_SFT 21
++#define MB_EXCEPT_CLR_HI 21
++#define MB_EXCEPT_CLR_SZ 1
++#define MB_EXCEPT_CASE_MSK 0xff000000
++#define MB_EXCEPT_CASE_I_MSK 0x00ffffff
++#define MB_EXCEPT_CASE_SFT 24
++#define MB_EXCEPT_CASE_HI 31
++#define MB_EXCEPT_CASE_SZ 8
++#define MB_DBG_TIME_STEP_MSK 0x0000ffff
++#define MB_DBG_TIME_STEP_I_MSK 0xffff0000
++#define MB_DBG_TIME_STEP_SFT 0
++#define MB_DBG_TIME_STEP_HI 15
++#define MB_DBG_TIME_STEP_SZ 16
++#define DBG_TYPE_MSK 0x00030000
++#define DBG_TYPE_I_MSK 0xfffcffff
++#define DBG_TYPE_SFT 16
++#define DBG_TYPE_HI 17
++#define DBG_TYPE_SZ 2
++#define MB_DBG_CLR_MSK 0x00040000
++#define MB_DBG_CLR_I_MSK 0xfffbffff
++#define MB_DBG_CLR_SFT 18
++#define MB_DBG_CLR_HI 18
++#define MB_DBG_CLR_SZ 1
++#define DBG_ALC_LOG_EN_MSK 0x00080000
++#define DBG_ALC_LOG_EN_I_MSK 0xfff7ffff
++#define DBG_ALC_LOG_EN_SFT 19
++#define DBG_ALC_LOG_EN_HI 19
++#define DBG_ALC_LOG_EN_SZ 1
++#define MB_DBG_COUNTER_EN_MSK 0x01000000
++#define MB_DBG_COUNTER_EN_I_MSK 0xfeffffff
++#define MB_DBG_COUNTER_EN_SFT 24
++#define MB_DBG_COUNTER_EN_HI 24
++#define MB_DBG_COUNTER_EN_SZ 1
++#define MB_DBG_EN_MSK 0x80000000
++#define MB_DBG_EN_I_MSK 0x7fffffff
++#define MB_DBG_EN_SFT 31
++#define MB_DBG_EN_HI 31
++#define MB_DBG_EN_SZ 1
++#define MB_DBG_RECORD_CNT_MSK 0x0000ffff
++#define MB_DBG_RECORD_CNT_I_MSK 0xffff0000
++#define MB_DBG_RECORD_CNT_SFT 0
++#define MB_DBG_RECORD_CNT_HI 15
++#define MB_DBG_RECORD_CNT_SZ 16
++#define MB_DBG_LENGTH_MSK 0xffff0000
++#define MB_DBG_LENGTH_I_MSK 0x0000ffff
++#define MB_DBG_LENGTH_SFT 16
++#define MB_DBG_LENGTH_HI 31
++#define MB_DBG_LENGTH_SZ 16
++#define MB_DBG_CFG_ADDR_MSK 0xffffffff
++#define MB_DBG_CFG_ADDR_I_MSK 0x00000000
++#define MB_DBG_CFG_ADDR_SFT 0
++#define MB_DBG_CFG_ADDR_HI 31
++#define MB_DBG_CFG_ADDR_SZ 32
++#define DBG_HWID0_WR_EN_MSK 0x00000001
++#define DBG_HWID0_WR_EN_I_MSK 0xfffffffe
++#define DBG_HWID0_WR_EN_SFT 0
++#define DBG_HWID0_WR_EN_HI 0
++#define DBG_HWID0_WR_EN_SZ 1
++#define DBG_HWID1_WR_EN_MSK 0x00000002
++#define DBG_HWID1_WR_EN_I_MSK 0xfffffffd
++#define DBG_HWID1_WR_EN_SFT 1
++#define DBG_HWID1_WR_EN_HI 1
++#define DBG_HWID1_WR_EN_SZ 1
++#define DBG_HWID2_WR_EN_MSK 0x00000004
++#define DBG_HWID2_WR_EN_I_MSK 0xfffffffb
++#define DBG_HWID2_WR_EN_SFT 2
++#define DBG_HWID2_WR_EN_HI 2
++#define DBG_HWID2_WR_EN_SZ 1
++#define DBG_HWID3_WR_EN_MSK 0x00000008
++#define DBG_HWID3_WR_EN_I_MSK 0xfffffff7
++#define DBG_HWID3_WR_EN_SFT 3
++#define DBG_HWID3_WR_EN_HI 3
++#define DBG_HWID3_WR_EN_SZ 1
++#define DBG_HWID4_WR_EN_MSK 0x00000010
++#define DBG_HWID4_WR_EN_I_MSK 0xffffffef
++#define DBG_HWID4_WR_EN_SFT 4
++#define DBG_HWID4_WR_EN_HI 4
++#define DBG_HWID4_WR_EN_SZ 1
++#define DBG_HWID5_WR_EN_MSK 0x00000020
++#define DBG_HWID5_WR_EN_I_MSK 0xffffffdf
++#define DBG_HWID5_WR_EN_SFT 5
++#define DBG_HWID5_WR_EN_HI 5
++#define DBG_HWID5_WR_EN_SZ 1
++#define DBG_HWID6_WR_EN_MSK 0x00000040
++#define DBG_HWID6_WR_EN_I_MSK 0xffffffbf
++#define DBG_HWID6_WR_EN_SFT 6
++#define DBG_HWID6_WR_EN_HI 6
++#define DBG_HWID6_WR_EN_SZ 1
++#define DBG_HWID7_WR_EN_MSK 0x00000080
++#define DBG_HWID7_WR_EN_I_MSK 0xffffff7f
++#define DBG_HWID7_WR_EN_SFT 7
++#define DBG_HWID7_WR_EN_HI 7
++#define DBG_HWID7_WR_EN_SZ 1
++#define DBG_HWID8_WR_EN_MSK 0x00000100
++#define DBG_HWID8_WR_EN_I_MSK 0xfffffeff
++#define DBG_HWID8_WR_EN_SFT 8
++#define DBG_HWID8_WR_EN_HI 8
++#define DBG_HWID8_WR_EN_SZ 1
++#define DBG_HWID9_WR_EN_MSK 0x00000200
++#define DBG_HWID9_WR_EN_I_MSK 0xfffffdff
++#define DBG_HWID9_WR_EN_SFT 9
++#define DBG_HWID9_WR_EN_HI 9
++#define DBG_HWID9_WR_EN_SZ 1
++#define DBG_HWID10_WR_EN_MSK 0x00000400
++#define DBG_HWID10_WR_EN_I_MSK 0xfffffbff
++#define DBG_HWID10_WR_EN_SFT 10
++#define DBG_HWID10_WR_EN_HI 10
++#define DBG_HWID10_WR_EN_SZ 1
++#define DBG_HWID11_WR_EN_MSK 0x00000800
++#define DBG_HWID11_WR_EN_I_MSK 0xfffff7ff
++#define DBG_HWID11_WR_EN_SFT 11
++#define DBG_HWID11_WR_EN_HI 11
++#define DBG_HWID11_WR_EN_SZ 1
++#define DBG_HWID12_WR_EN_MSK 0x00001000
++#define DBG_HWID12_WR_EN_I_MSK 0xffffefff
++#define DBG_HWID12_WR_EN_SFT 12
++#define DBG_HWID12_WR_EN_HI 12
++#define DBG_HWID12_WR_EN_SZ 1
++#define DBG_HWID13_WR_EN_MSK 0x00002000
++#define DBG_HWID13_WR_EN_I_MSK 0xffffdfff
++#define DBG_HWID13_WR_EN_SFT 13
++#define DBG_HWID13_WR_EN_HI 13
++#define DBG_HWID13_WR_EN_SZ 1
++#define DBG_HWID14_WR_EN_MSK 0x00004000
++#define DBG_HWID14_WR_EN_I_MSK 0xffffbfff
++#define DBG_HWID14_WR_EN_SFT 14
++#define DBG_HWID14_WR_EN_HI 14
++#define DBG_HWID14_WR_EN_SZ 1
++#define DBG_HWID15_WR_EN_MSK 0x00008000
++#define DBG_HWID15_WR_EN_I_MSK 0xffff7fff
++#define DBG_HWID15_WR_EN_SFT 15
++#define DBG_HWID15_WR_EN_HI 15
++#define DBG_HWID15_WR_EN_SZ 1
++#define DBG_HWID0_RD_EN_MSK 0x00010000
++#define DBG_HWID0_RD_EN_I_MSK 0xfffeffff
++#define DBG_HWID0_RD_EN_SFT 16
++#define DBG_HWID0_RD_EN_HI 16
++#define DBG_HWID0_RD_EN_SZ 1
++#define DBG_HWID1_RD_EN_MSK 0x00020000
++#define DBG_HWID1_RD_EN_I_MSK 0xfffdffff
++#define DBG_HWID1_RD_EN_SFT 17
++#define DBG_HWID1_RD_EN_HI 17
++#define DBG_HWID1_RD_EN_SZ 1
++#define DBG_HWID2_RD_EN_MSK 0x00040000
++#define DBG_HWID2_RD_EN_I_MSK 0xfffbffff
++#define DBG_HWID2_RD_EN_SFT 18
++#define DBG_HWID2_RD_EN_HI 18
++#define DBG_HWID2_RD_EN_SZ 1
++#define DBG_HWID3_RD_EN_MSK 0x00080000
++#define DBG_HWID3_RD_EN_I_MSK 0xfff7ffff
++#define DBG_HWID3_RD_EN_SFT 19
++#define DBG_HWID3_RD_EN_HI 19
++#define DBG_HWID3_RD_EN_SZ 1
++#define DBG_HWID4_RD_EN_MSK 0x00100000
++#define DBG_HWID4_RD_EN_I_MSK 0xffefffff
++#define DBG_HWID4_RD_EN_SFT 20
++#define DBG_HWID4_RD_EN_HI 20
++#define DBG_HWID4_RD_EN_SZ 1
++#define DBG_HWID5_RD_EN_MSK 0x00200000
++#define DBG_HWID5_RD_EN_I_MSK 0xffdfffff
++#define DBG_HWID5_RD_EN_SFT 21
++#define DBG_HWID5_RD_EN_HI 21
++#define DBG_HWID5_RD_EN_SZ 1
++#define DBG_HWID6_RD_EN_MSK 0x00400000
++#define DBG_HWID6_RD_EN_I_MSK 0xffbfffff
++#define DBG_HWID6_RD_EN_SFT 22
++#define DBG_HWID6_RD_EN_HI 22
++#define DBG_HWID6_RD_EN_SZ 1
++#define DBG_HWID7_RD_EN_MSK 0x00800000
++#define DBG_HWID7_RD_EN_I_MSK 0xff7fffff
++#define DBG_HWID7_RD_EN_SFT 23
++#define DBG_HWID7_RD_EN_HI 23
++#define DBG_HWID7_RD_EN_SZ 1
++#define DBG_HWID8_RD_EN_MSK 0x01000000
++#define DBG_HWID8_RD_EN_I_MSK 0xfeffffff
++#define DBG_HWID8_RD_EN_SFT 24
++#define DBG_HWID8_RD_EN_HI 24
++#define DBG_HWID8_RD_EN_SZ 1
++#define DBG_HWID9_RD_EN_MSK 0x02000000
++#define DBG_HWID9_RD_EN_I_MSK 0xfdffffff
++#define DBG_HWID9_RD_EN_SFT 25
++#define DBG_HWID9_RD_EN_HI 25
++#define DBG_HWID9_RD_EN_SZ 1
++#define DBG_HWID10_RD_EN_MSK 0x04000000
++#define DBG_HWID10_RD_EN_I_MSK 0xfbffffff
++#define DBG_HWID10_RD_EN_SFT 26
++#define DBG_HWID10_RD_EN_HI 26
++#define DBG_HWID10_RD_EN_SZ 1
++#define DBG_HWID11_RD_EN_MSK 0x08000000
++#define DBG_HWID11_RD_EN_I_MSK 0xf7ffffff
++#define DBG_HWID11_RD_EN_SFT 27
++#define DBG_HWID11_RD_EN_HI 27
++#define DBG_HWID11_RD_EN_SZ 1
++#define DBG_HWID12_RD_EN_MSK 0x10000000
++#define DBG_HWID12_RD_EN_I_MSK 0xefffffff
++#define DBG_HWID12_RD_EN_SFT 28
++#define DBG_HWID12_RD_EN_HI 28
++#define DBG_HWID12_RD_EN_SZ 1
++#define DBG_HWID13_RD_EN_MSK 0x20000000
++#define DBG_HWID13_RD_EN_I_MSK 0xdfffffff
++#define DBG_HWID13_RD_EN_SFT 29
++#define DBG_HWID13_RD_EN_HI 29
++#define DBG_HWID13_RD_EN_SZ 1
++#define DBG_HWID14_RD_EN_MSK 0x40000000
++#define DBG_HWID14_RD_EN_I_MSK 0xbfffffff
++#define DBG_HWID14_RD_EN_SFT 30
++#define DBG_HWID14_RD_EN_HI 30
++#define DBG_HWID14_RD_EN_SZ 1
++#define DBG_HWID15_RD_EN_MSK 0x80000000
++#define DBG_HWID15_RD_EN_I_MSK 0x7fffffff
++#define DBG_HWID15_RD_EN_SFT 31
++#define DBG_HWID15_RD_EN_HI 31
++#define DBG_HWID15_RD_EN_SZ 1
++#define MB_OUT_QUEUE_EN_MSK 0x00000002
++#define MB_OUT_QUEUE_EN_I_MSK 0xfffffffd
++#define MB_OUT_QUEUE_EN_SFT 1
++#define MB_OUT_QUEUE_EN_HI 1
++#define MB_OUT_QUEUE_EN_SZ 1
++#define CH0_QUEUE_FLUSH_MSK 0x00000001
++#define CH0_QUEUE_FLUSH_I_MSK 0xfffffffe
++#define CH0_QUEUE_FLUSH_SFT 0
++#define CH0_QUEUE_FLUSH_HI 0
++#define CH0_QUEUE_FLUSH_SZ 1
++#define CH1_QUEUE_FLUSH_MSK 0x00000002
++#define CH1_QUEUE_FLUSH_I_MSK 0xfffffffd
++#define CH1_QUEUE_FLUSH_SFT 1
++#define CH1_QUEUE_FLUSH_HI 1
++#define CH1_QUEUE_FLUSH_SZ 1
++#define CH2_QUEUE_FLUSH_MSK 0x00000004
++#define CH2_QUEUE_FLUSH_I_MSK 0xfffffffb
++#define CH2_QUEUE_FLUSH_SFT 2
++#define CH2_QUEUE_FLUSH_HI 2
++#define CH2_QUEUE_FLUSH_SZ 1
++#define CH3_QUEUE_FLUSH_MSK 0x00000008
++#define CH3_QUEUE_FLUSH_I_MSK 0xfffffff7
++#define CH3_QUEUE_FLUSH_SFT 3
++#define CH3_QUEUE_FLUSH_HI 3
++#define CH3_QUEUE_FLUSH_SZ 1
++#define CH4_QUEUE_FLUSH_MSK 0x00000010
++#define CH4_QUEUE_FLUSH_I_MSK 0xffffffef
++#define CH4_QUEUE_FLUSH_SFT 4
++#define CH4_QUEUE_FLUSH_HI 4
++#define CH4_QUEUE_FLUSH_SZ 1
++#define CH5_QUEUE_FLUSH_MSK 0x00000020
++#define CH5_QUEUE_FLUSH_I_MSK 0xffffffdf
++#define CH5_QUEUE_FLUSH_SFT 5
++#define CH5_QUEUE_FLUSH_HI 5
++#define CH5_QUEUE_FLUSH_SZ 1
++#define CH6_QUEUE_FLUSH_MSK 0x00000040
++#define CH6_QUEUE_FLUSH_I_MSK 0xffffffbf
++#define CH6_QUEUE_FLUSH_SFT 6
++#define CH6_QUEUE_FLUSH_HI 6
++#define CH6_QUEUE_FLUSH_SZ 1
++#define CH7_QUEUE_FLUSH_MSK 0x00000080
++#define CH7_QUEUE_FLUSH_I_MSK 0xffffff7f
++#define CH7_QUEUE_FLUSH_SFT 7
++#define CH7_QUEUE_FLUSH_HI 7
++#define CH7_QUEUE_FLUSH_SZ 1
++#define CH8_QUEUE_FLUSH_MSK 0x00000100
++#define CH8_QUEUE_FLUSH_I_MSK 0xfffffeff
++#define CH8_QUEUE_FLUSH_SFT 8
++#define CH8_QUEUE_FLUSH_HI 8
++#define CH8_QUEUE_FLUSH_SZ 1
++#define CH9_QUEUE_FLUSH_MSK 0x00000200
++#define CH9_QUEUE_FLUSH_I_MSK 0xfffffdff
++#define CH9_QUEUE_FLUSH_SFT 9
++#define CH9_QUEUE_FLUSH_HI 9
++#define CH9_QUEUE_FLUSH_SZ 1
++#define CH10_QUEUE_FLUSH_MSK 0x00000400
++#define CH10_QUEUE_FLUSH_I_MSK 0xfffffbff
++#define CH10_QUEUE_FLUSH_SFT 10
++#define CH10_QUEUE_FLUSH_HI 10
++#define CH10_QUEUE_FLUSH_SZ 1
++#define CH11_QUEUE_FLUSH_MSK 0x00000800
++#define CH11_QUEUE_FLUSH_I_MSK 0xfffff7ff
++#define CH11_QUEUE_FLUSH_SFT 11
++#define CH11_QUEUE_FLUSH_HI 11
++#define CH11_QUEUE_FLUSH_SZ 1
++#define CH12_QUEUE_FLUSH_MSK 0x00001000
++#define CH12_QUEUE_FLUSH_I_MSK 0xffffefff
++#define CH12_QUEUE_FLUSH_SFT 12
++#define CH12_QUEUE_FLUSH_HI 12
++#define CH12_QUEUE_FLUSH_SZ 1
++#define CH13_QUEUE_FLUSH_MSK 0x00002000
++#define CH13_QUEUE_FLUSH_I_MSK 0xffffdfff
++#define CH13_QUEUE_FLUSH_SFT 13
++#define CH13_QUEUE_FLUSH_HI 13
++#define CH13_QUEUE_FLUSH_SZ 1
++#define CH14_QUEUE_FLUSH_MSK 0x00004000
++#define CH14_QUEUE_FLUSH_I_MSK 0xffffbfff
++#define CH14_QUEUE_FLUSH_SFT 14
++#define CH14_QUEUE_FLUSH_HI 14
++#define CH14_QUEUE_FLUSH_SZ 1
++#define CH15_QUEUE_FLUSH_MSK 0x00008000
++#define CH15_QUEUE_FLUSH_I_MSK 0xffff7fff
++#define CH15_QUEUE_FLUSH_SFT 15
++#define CH15_QUEUE_FLUSH_HI 15
++#define CH15_QUEUE_FLUSH_SZ 1
++#define FFO0_CNT_MSK 0x0000001f
++#define FFO0_CNT_I_MSK 0xffffffe0
++#define FFO0_CNT_SFT 0
++#define FFO0_CNT_HI 4
++#define FFO0_CNT_SZ 5
++#define FFO1_CNT_MSK 0x000003e0
++#define FFO1_CNT_I_MSK 0xfffffc1f
++#define FFO1_CNT_SFT 5
++#define FFO1_CNT_HI 9
++#define FFO1_CNT_SZ 5
++#define FFO2_CNT_MSK 0x00000c00
++#define FFO2_CNT_I_MSK 0xfffff3ff
++#define FFO2_CNT_SFT 10
++#define FFO2_CNT_HI 11
++#define FFO2_CNT_SZ 2
++#define FFO3_CNT_MSK 0x000f8000
++#define FFO3_CNT_I_MSK 0xfff07fff
++#define FFO3_CNT_SFT 15
++#define FFO3_CNT_HI 19
++#define FFO3_CNT_SZ 5
++#define FFO4_CNT_MSK 0x00300000
++#define FFO4_CNT_I_MSK 0xffcfffff
++#define FFO4_CNT_SFT 20
++#define FFO4_CNT_HI 21
++#define FFO4_CNT_SZ 2
++#define FFO5_CNT_MSK 0x0e000000
++#define FFO5_CNT_I_MSK 0xf1ffffff
++#define FFO5_CNT_SFT 25
++#define FFO5_CNT_HI 27
++#define FFO5_CNT_SZ 3
++#define FFO6_CNT_MSK 0x0000000f
++#define FFO6_CNT_I_MSK 0xfffffff0
++#define FFO6_CNT_SFT 0
++#define FFO6_CNT_HI 3
++#define FFO6_CNT_SZ 4
++#define FFO7_CNT_MSK 0x000003e0
++#define FFO7_CNT_I_MSK 0xfffffc1f
++#define FFO7_CNT_SFT 5
++#define FFO7_CNT_HI 9
++#define FFO7_CNT_SZ 5
++#define FFO8_CNT_MSK 0x00007c00
++#define FFO8_CNT_I_MSK 0xffff83ff
++#define FFO8_CNT_SFT 10
++#define FFO8_CNT_HI 14
++#define FFO8_CNT_SZ 5
++#define FFO9_CNT_MSK 0x000f8000
++#define FFO9_CNT_I_MSK 0xfff07fff
++#define FFO9_CNT_SFT 15
++#define FFO9_CNT_HI 19
++#define FFO9_CNT_SZ 5
++#define FFO10_CNT_MSK 0x00f00000
++#define FFO10_CNT_I_MSK 0xff0fffff
++#define FFO10_CNT_SFT 20
++#define FFO10_CNT_HI 23
++#define FFO10_CNT_SZ 4
++#define FFO11_CNT_MSK 0x3e000000
++#define FFO11_CNT_I_MSK 0xc1ffffff
++#define FFO11_CNT_SFT 25
++#define FFO11_CNT_HI 29
++#define FFO11_CNT_SZ 5
++#define FFO12_CNT_MSK 0x00000007
++#define FFO12_CNT_I_MSK 0xfffffff8
++#define FFO12_CNT_SFT 0
++#define FFO12_CNT_HI 2
++#define FFO12_CNT_SZ 3
++#define FFO13_CNT_MSK 0x00000060
++#define FFO13_CNT_I_MSK 0xffffff9f
++#define FFO13_CNT_SFT 5
++#define FFO13_CNT_HI 6
++#define FFO13_CNT_SZ 2
++#define FFO14_CNT_MSK 0x00000c00
++#define FFO14_CNT_I_MSK 0xfffff3ff
++#define FFO14_CNT_SFT 10
++#define FFO14_CNT_HI 11
++#define FFO14_CNT_SZ 2
++#define FFO15_CNT_MSK 0x001f8000
++#define FFO15_CNT_I_MSK 0xffe07fff
++#define FFO15_CNT_SFT 15
++#define FFO15_CNT_HI 20
++#define FFO15_CNT_SZ 6
++#define CH0_FFO_FULL_MSK 0x00000001
++#define CH0_FFO_FULL_I_MSK 0xfffffffe
++#define CH0_FFO_FULL_SFT 0
++#define CH0_FFO_FULL_HI 0
++#define CH0_FFO_FULL_SZ 1
++#define CH1_FFO_FULL_MSK 0x00000002
++#define CH1_FFO_FULL_I_MSK 0xfffffffd
++#define CH1_FFO_FULL_SFT 1
++#define CH1_FFO_FULL_HI 1
++#define CH1_FFO_FULL_SZ 1
++#define CH2_FFO_FULL_MSK 0x00000004
++#define CH2_FFO_FULL_I_MSK 0xfffffffb
++#define CH2_FFO_FULL_SFT 2
++#define CH2_FFO_FULL_HI 2
++#define CH2_FFO_FULL_SZ 1
++#define CH3_FFO_FULL_MSK 0x00000008
++#define CH3_FFO_FULL_I_MSK 0xfffffff7
++#define CH3_FFO_FULL_SFT 3
++#define CH3_FFO_FULL_HI 3
++#define CH3_FFO_FULL_SZ 1
++#define CH4_FFO_FULL_MSK 0x00000010
++#define CH4_FFO_FULL_I_MSK 0xffffffef
++#define CH4_FFO_FULL_SFT 4
++#define CH4_FFO_FULL_HI 4
++#define CH4_FFO_FULL_SZ 1
++#define CH5_FFO_FULL_MSK 0x00000020
++#define CH5_FFO_FULL_I_MSK 0xffffffdf
++#define CH5_FFO_FULL_SFT 5
++#define CH5_FFO_FULL_HI 5
++#define CH5_FFO_FULL_SZ 1
++#define CH6_FFO_FULL_MSK 0x00000040
++#define CH6_FFO_FULL_I_MSK 0xffffffbf
++#define CH6_FFO_FULL_SFT 6
++#define CH6_FFO_FULL_HI 6
++#define CH6_FFO_FULL_SZ 1
++#define CH7_FFO_FULL_MSK 0x00000080
++#define CH7_FFO_FULL_I_MSK 0xffffff7f
++#define CH7_FFO_FULL_SFT 7
++#define CH7_FFO_FULL_HI 7
++#define CH7_FFO_FULL_SZ 1
++#define CH8_FFO_FULL_MSK 0x00000100
++#define CH8_FFO_FULL_I_MSK 0xfffffeff
++#define CH8_FFO_FULL_SFT 8
++#define CH8_FFO_FULL_HI 8
++#define CH8_FFO_FULL_SZ 1
++#define CH9_FFO_FULL_MSK 0x00000200
++#define CH9_FFO_FULL_I_MSK 0xfffffdff
++#define CH9_FFO_FULL_SFT 9
++#define CH9_FFO_FULL_HI 9
++#define CH9_FFO_FULL_SZ 1
++#define CH10_FFO_FULL_MSK 0x00000400
++#define CH10_FFO_FULL_I_MSK 0xfffffbff
++#define CH10_FFO_FULL_SFT 10
++#define CH10_FFO_FULL_HI 10
++#define CH10_FFO_FULL_SZ 1
++#define CH11_FFO_FULL_MSK 0x00000800
++#define CH11_FFO_FULL_I_MSK 0xfffff7ff
++#define CH11_FFO_FULL_SFT 11
++#define CH11_FFO_FULL_HI 11
++#define CH11_FFO_FULL_SZ 1
++#define CH12_FFO_FULL_MSK 0x00001000
++#define CH12_FFO_FULL_I_MSK 0xffffefff
++#define CH12_FFO_FULL_SFT 12
++#define CH12_FFO_FULL_HI 12
++#define CH12_FFO_FULL_SZ 1
++#define CH13_FFO_FULL_MSK 0x00002000
++#define CH13_FFO_FULL_I_MSK 0xffffdfff
++#define CH13_FFO_FULL_SFT 13
++#define CH13_FFO_FULL_HI 13
++#define CH13_FFO_FULL_SZ 1
++#define CH14_FFO_FULL_MSK 0x00004000
++#define CH14_FFO_FULL_I_MSK 0xffffbfff
++#define CH14_FFO_FULL_SFT 14
++#define CH14_FFO_FULL_HI 14
++#define CH14_FFO_FULL_SZ 1
++#define CH15_FFO_FULL_MSK 0x00008000
++#define CH15_FFO_FULL_I_MSK 0xffff7fff
++#define CH15_FFO_FULL_SFT 15
++#define CH15_FFO_FULL_HI 15
++#define CH15_FFO_FULL_SZ 1
++#define CH0_LOWTHOLD_INT_MSK 0x00000001
++#define CH0_LOWTHOLD_INT_I_MSK 0xfffffffe
++#define CH0_LOWTHOLD_INT_SFT 0
++#define CH0_LOWTHOLD_INT_HI 0
++#define CH0_LOWTHOLD_INT_SZ 1
++#define CH1_LOWTHOLD_INT_MSK 0x00000002
++#define CH1_LOWTHOLD_INT_I_MSK 0xfffffffd
++#define CH1_LOWTHOLD_INT_SFT 1
++#define CH1_LOWTHOLD_INT_HI 1
++#define CH1_LOWTHOLD_INT_SZ 1
++#define CH2_LOWTHOLD_INT_MSK 0x00000004
++#define CH2_LOWTHOLD_INT_I_MSK 0xfffffffb
++#define CH2_LOWTHOLD_INT_SFT 2
++#define CH2_LOWTHOLD_INT_HI 2
++#define CH2_LOWTHOLD_INT_SZ 1
++#define CH3_LOWTHOLD_INT_MSK 0x00000008
++#define CH3_LOWTHOLD_INT_I_MSK 0xfffffff7
++#define CH3_LOWTHOLD_INT_SFT 3
++#define CH3_LOWTHOLD_INT_HI 3
++#define CH3_LOWTHOLD_INT_SZ 1
++#define CH4_LOWTHOLD_INT_MSK 0x00000010
++#define CH4_LOWTHOLD_INT_I_MSK 0xffffffef
++#define CH4_LOWTHOLD_INT_SFT 4
++#define CH4_LOWTHOLD_INT_HI 4
++#define CH4_LOWTHOLD_INT_SZ 1
++#define CH5_LOWTHOLD_INT_MSK 0x00000020
++#define CH5_LOWTHOLD_INT_I_MSK 0xffffffdf
++#define CH5_LOWTHOLD_INT_SFT 5
++#define CH5_LOWTHOLD_INT_HI 5
++#define CH5_LOWTHOLD_INT_SZ 1
++#define CH6_LOWTHOLD_INT_MSK 0x00000040
++#define CH6_LOWTHOLD_INT_I_MSK 0xffffffbf
++#define CH6_LOWTHOLD_INT_SFT 6
++#define CH6_LOWTHOLD_INT_HI 6
++#define CH6_LOWTHOLD_INT_SZ 1
++#define CH7_LOWTHOLD_INT_MSK 0x00000080
++#define CH7_LOWTHOLD_INT_I_MSK 0xffffff7f
++#define CH7_LOWTHOLD_INT_SFT 7
++#define CH7_LOWTHOLD_INT_HI 7
++#define CH7_LOWTHOLD_INT_SZ 1
++#define CH8_LOWTHOLD_INT_MSK 0x00000100
++#define CH8_LOWTHOLD_INT_I_MSK 0xfffffeff
++#define CH8_LOWTHOLD_INT_SFT 8
++#define CH8_LOWTHOLD_INT_HI 8
++#define CH8_LOWTHOLD_INT_SZ 1
++#define CH9_LOWTHOLD_INT_MSK 0x00000200
++#define CH9_LOWTHOLD_INT_I_MSK 0xfffffdff
++#define CH9_LOWTHOLD_INT_SFT 9
++#define CH9_LOWTHOLD_INT_HI 9
++#define CH9_LOWTHOLD_INT_SZ 1
++#define CH10_LOWTHOLD_INT_MSK 0x00000400
++#define CH10_LOWTHOLD_INT_I_MSK 0xfffffbff
++#define CH10_LOWTHOLD_INT_SFT 10
++#define CH10_LOWTHOLD_INT_HI 10
++#define CH10_LOWTHOLD_INT_SZ 1
++#define CH11_LOWTHOLD_INT_MSK 0x00000800
++#define CH11_LOWTHOLD_INT_I_MSK 0xfffff7ff
++#define CH11_LOWTHOLD_INT_SFT 11
++#define CH11_LOWTHOLD_INT_HI 11
++#define CH11_LOWTHOLD_INT_SZ 1
++#define CH12_LOWTHOLD_INT_MSK 0x00001000
++#define CH12_LOWTHOLD_INT_I_MSK 0xffffefff
++#define CH12_LOWTHOLD_INT_SFT 12
++#define CH12_LOWTHOLD_INT_HI 12
++#define CH12_LOWTHOLD_INT_SZ 1
++#define CH13_LOWTHOLD_INT_MSK 0x00002000
++#define CH13_LOWTHOLD_INT_I_MSK 0xffffdfff
++#define CH13_LOWTHOLD_INT_SFT 13
++#define CH13_LOWTHOLD_INT_HI 13
++#define CH13_LOWTHOLD_INT_SZ 1
++#define CH14_LOWTHOLD_INT_MSK 0x00004000
++#define CH14_LOWTHOLD_INT_I_MSK 0xffffbfff
++#define CH14_LOWTHOLD_INT_SFT 14
++#define CH14_LOWTHOLD_INT_HI 14
++#define CH14_LOWTHOLD_INT_SZ 1
++#define CH15_LOWTHOLD_INT_MSK 0x00008000
++#define CH15_LOWTHOLD_INT_I_MSK 0xffff7fff
++#define CH15_LOWTHOLD_INT_SFT 15
++#define CH15_LOWTHOLD_INT_HI 15
++#define CH15_LOWTHOLD_INT_SZ 1
++#define MB_LOW_THOLD_EN_MSK 0x80000000
++#define MB_LOW_THOLD_EN_I_MSK 0x7fffffff
++#define MB_LOW_THOLD_EN_SFT 31
++#define MB_LOW_THOLD_EN_HI 31
++#define MB_LOW_THOLD_EN_SZ 1
++#define CH0_LOWTHOLD_MSK 0x0000001f
++#define CH0_LOWTHOLD_I_MSK 0xffffffe0
++#define CH0_LOWTHOLD_SFT 0
++#define CH0_LOWTHOLD_HI 4
++#define CH0_LOWTHOLD_SZ 5
++#define CH1_LOWTHOLD_MSK 0x00001f00
++#define CH1_LOWTHOLD_I_MSK 0xffffe0ff
++#define CH1_LOWTHOLD_SFT 8
++#define CH1_LOWTHOLD_HI 12
++#define CH1_LOWTHOLD_SZ 5
++#define CH2_LOWTHOLD_MSK 0x001f0000
++#define CH2_LOWTHOLD_I_MSK 0xffe0ffff
++#define CH2_LOWTHOLD_SFT 16
++#define CH2_LOWTHOLD_HI 20
++#define CH2_LOWTHOLD_SZ 5
++#define CH3_LOWTHOLD_MSK 0x1f000000
++#define CH3_LOWTHOLD_I_MSK 0xe0ffffff
++#define CH3_LOWTHOLD_SFT 24
++#define CH3_LOWTHOLD_HI 28
++#define CH3_LOWTHOLD_SZ 5
++#define CH4_LOWTHOLD_MSK 0x0000001f
++#define CH4_LOWTHOLD_I_MSK 0xffffffe0
++#define CH4_LOWTHOLD_SFT 0
++#define CH4_LOWTHOLD_HI 4
++#define CH4_LOWTHOLD_SZ 5
++#define CH5_LOWTHOLD_MSK 0x00001f00
++#define CH5_LOWTHOLD_I_MSK 0xffffe0ff
++#define CH5_LOWTHOLD_SFT 8
++#define CH5_LOWTHOLD_HI 12
++#define CH5_LOWTHOLD_SZ 5
++#define CH6_LOWTHOLD_MSK 0x001f0000
++#define CH6_LOWTHOLD_I_MSK 0xffe0ffff
++#define CH6_LOWTHOLD_SFT 16
++#define CH6_LOWTHOLD_HI 20
++#define CH6_LOWTHOLD_SZ 5
++#define CH7_LOWTHOLD_MSK 0x1f000000
++#define CH7_LOWTHOLD_I_MSK 0xe0ffffff
++#define CH7_LOWTHOLD_SFT 24
++#define CH7_LOWTHOLD_HI 28
++#define CH7_LOWTHOLD_SZ 5
++#define CH8_LOWTHOLD_MSK 0x0000001f
++#define CH8_LOWTHOLD_I_MSK 0xffffffe0
++#define CH8_LOWTHOLD_SFT 0
++#define CH8_LOWTHOLD_HI 4
++#define CH8_LOWTHOLD_SZ 5
++#define CH9_LOWTHOLD_MSK 0x00001f00
++#define CH9_LOWTHOLD_I_MSK 0xffffe0ff
++#define CH9_LOWTHOLD_SFT 8
++#define CH9_LOWTHOLD_HI 12
++#define CH9_LOWTHOLD_SZ 5
++#define CH10_LOWTHOLD_MSK 0x001f0000
++#define CH10_LOWTHOLD_I_MSK 0xffe0ffff
++#define CH10_LOWTHOLD_SFT 16
++#define CH10_LOWTHOLD_HI 20
++#define CH10_LOWTHOLD_SZ 5
++#define CH11_LOWTHOLD_MSK 0x1f000000
++#define CH11_LOWTHOLD_I_MSK 0xe0ffffff
++#define CH11_LOWTHOLD_SFT 24
++#define CH11_LOWTHOLD_HI 28
++#define CH11_LOWTHOLD_SZ 5
++#define CH12_LOWTHOLD_MSK 0x0000001f
++#define CH12_LOWTHOLD_I_MSK 0xffffffe0
++#define CH12_LOWTHOLD_SFT 0
++#define CH12_LOWTHOLD_HI 4
++#define CH12_LOWTHOLD_SZ 5
++#define CH13_LOWTHOLD_MSK 0x00001f00
++#define CH13_LOWTHOLD_I_MSK 0xffffe0ff
++#define CH13_LOWTHOLD_SFT 8
++#define CH13_LOWTHOLD_HI 12
++#define CH13_LOWTHOLD_SZ 5
++#define CH14_LOWTHOLD_MSK 0x001f0000
++#define CH14_LOWTHOLD_I_MSK 0xffe0ffff
++#define CH14_LOWTHOLD_SFT 16
++#define CH14_LOWTHOLD_HI 20
++#define CH14_LOWTHOLD_SZ 5
++#define CH15_LOWTHOLD_MSK 0x1f000000
++#define CH15_LOWTHOLD_I_MSK 0xe0ffffff
++#define CH15_LOWTHOLD_SFT 24
++#define CH15_LOWTHOLD_HI 28
++#define CH15_LOWTHOLD_SZ 5
++#define TRASH_TIMEOUT_EN_MSK 0x00000001
++#define TRASH_TIMEOUT_EN_I_MSK 0xfffffffe
++#define TRASH_TIMEOUT_EN_SFT 0
++#define TRASH_TIMEOUT_EN_HI 0
++#define TRASH_TIMEOUT_EN_SZ 1
++#define TRASH_CAN_INT_MSK 0x00000002
++#define TRASH_CAN_INT_I_MSK 0xfffffffd
++#define TRASH_CAN_INT_SFT 1
++#define TRASH_CAN_INT_HI 1
++#define TRASH_CAN_INT_SZ 1
++#define TRASH_INT_ID_MSK 0x000007f0
++#define TRASH_INT_ID_I_MSK 0xfffff80f
++#define TRASH_INT_ID_SFT 4
++#define TRASH_INT_ID_HI 10
++#define TRASH_INT_ID_SZ 7
++#define TRASH_TIMEOUT_MSK 0x03ff0000
++#define TRASH_TIMEOUT_I_MSK 0xfc00ffff
++#define TRASH_TIMEOUT_SFT 16
++#define TRASH_TIMEOUT_HI 25
++#define TRASH_TIMEOUT_SZ 10
++#define CH0_WRFF_FLUSH_MSK 0x00000001
++#define CH0_WRFF_FLUSH_I_MSK 0xfffffffe
++#define CH0_WRFF_FLUSH_SFT 0
++#define CH0_WRFF_FLUSH_HI 0
++#define CH0_WRFF_FLUSH_SZ 1
++#define CH1_WRFF_FLUSH_MSK 0x00000002
++#define CH1_WRFF_FLUSH_I_MSK 0xfffffffd
++#define CH1_WRFF_FLUSH_SFT 1
++#define CH1_WRFF_FLUSH_HI 1
++#define CH1_WRFF_FLUSH_SZ 1
++#define CH2_WRFF_FLUSH_MSK 0x00000004
++#define CH2_WRFF_FLUSH_I_MSK 0xfffffffb
++#define CH2_WRFF_FLUSH_SFT 2
++#define CH2_WRFF_FLUSH_HI 2
++#define CH2_WRFF_FLUSH_SZ 1
++#define CH3_WRFF_FLUSH_MSK 0x00000008
++#define CH3_WRFF_FLUSH_I_MSK 0xfffffff7
++#define CH3_WRFF_FLUSH_SFT 3
++#define CH3_WRFF_FLUSH_HI 3
++#define CH3_WRFF_FLUSH_SZ 1
++#define CH4_WRFF_FLUSH_MSK 0x00000010
++#define CH4_WRFF_FLUSH_I_MSK 0xffffffef
++#define CH4_WRFF_FLUSH_SFT 4
++#define CH4_WRFF_FLUSH_HI 4
++#define CH4_WRFF_FLUSH_SZ 1
++#define CH5_WRFF_FLUSH_MSK 0x00000020
++#define CH5_WRFF_FLUSH_I_MSK 0xffffffdf
++#define CH5_WRFF_FLUSH_SFT 5
++#define CH5_WRFF_FLUSH_HI 5
++#define CH5_WRFF_FLUSH_SZ 1
++#define CH6_WRFF_FLUSH_MSK 0x00000040
++#define CH6_WRFF_FLUSH_I_MSK 0xffffffbf
++#define CH6_WRFF_FLUSH_SFT 6
++#define CH6_WRFF_FLUSH_HI 6
++#define CH6_WRFF_FLUSH_SZ 1
++#define CH7_WRFF_FLUSH_MSK 0x00000080
++#define CH7_WRFF_FLUSH_I_MSK 0xffffff7f
++#define CH7_WRFF_FLUSH_SFT 7
++#define CH7_WRFF_FLUSH_HI 7
++#define CH7_WRFF_FLUSH_SZ 1
++#define CH8_WRFF_FLUSH_MSK 0x00000100
++#define CH8_WRFF_FLUSH_I_MSK 0xfffffeff
++#define CH8_WRFF_FLUSH_SFT 8
++#define CH8_WRFF_FLUSH_HI 8
++#define CH8_WRFF_FLUSH_SZ 1
++#define CH9_WRFF_FLUSH_MSK 0x00000200
++#define CH9_WRFF_FLUSH_I_MSK 0xfffffdff
++#define CH9_WRFF_FLUSH_SFT 9
++#define CH9_WRFF_FLUSH_HI 9
++#define CH9_WRFF_FLUSH_SZ 1
++#define CH10_WRFF_FLUSH_MSK 0x00000400
++#define CH10_WRFF_FLUSH_I_MSK 0xfffffbff
++#define CH10_WRFF_FLUSH_SFT 10
++#define CH10_WRFF_FLUSH_HI 10
++#define CH10_WRFF_FLUSH_SZ 1
++#define CH11_WRFF_FLUSH_MSK 0x00000800
++#define CH11_WRFF_FLUSH_I_MSK 0xfffff7ff
++#define CH11_WRFF_FLUSH_SFT 11
++#define CH11_WRFF_FLUSH_HI 11
++#define CH11_WRFF_FLUSH_SZ 1
++#define CH12_WRFF_FLUSH_MSK 0x00001000
++#define CH12_WRFF_FLUSH_I_MSK 0xffffefff
++#define CH12_WRFF_FLUSH_SFT 12
++#define CH12_WRFF_FLUSH_HI 12
++#define CH12_WRFF_FLUSH_SZ 1
++#define CH13_WRFF_FLUSH_MSK 0x00002000
++#define CH13_WRFF_FLUSH_I_MSK 0xffffdfff
++#define CH13_WRFF_FLUSH_SFT 13
++#define CH13_WRFF_FLUSH_HI 13
++#define CH13_WRFF_FLUSH_SZ 1
++#define CH14_WRFF_FLUSH_MSK 0x00004000
++#define CH14_WRFF_FLUSH_I_MSK 0xffffbfff
++#define CH14_WRFF_FLUSH_SFT 14
++#define CH14_WRFF_FLUSH_HI 14
++#define CH14_WRFF_FLUSH_SZ 1
++#define CPU_ID_TB2_MSK 0xffffffff
++#define CPU_ID_TB2_I_MSK 0x00000000
++#define CPU_ID_TB2_SFT 0
++#define CPU_ID_TB2_HI 31
++#define CPU_ID_TB2_SZ 32
++#define CPU_ID_TB3_MSK 0xffffffff
++#define CPU_ID_TB3_I_MSK 0x00000000
++#define CPU_ID_TB3_SFT 0
++#define CPU_ID_TB3_HI 31
++#define CPU_ID_TB3_SZ 32
++#define IQ_LOG_EN_MSK 0x00000001
++#define IQ_LOG_EN_I_MSK 0xfffffffe
++#define IQ_LOG_EN_SFT 0
++#define IQ_LOG_EN_HI 0
++#define IQ_LOG_EN_SZ 1
++#define IQ_LOG_STOP_MODE_MSK 0x00000001
++#define IQ_LOG_STOP_MODE_I_MSK 0xfffffffe
++#define IQ_LOG_STOP_MODE_SFT 0
++#define IQ_LOG_STOP_MODE_HI 0
++#define IQ_LOG_STOP_MODE_SZ 1
++#define GPIO_STOP_EN_MSK 0x00000010
++#define GPIO_STOP_EN_I_MSK 0xffffffef
++#define GPIO_STOP_EN_SFT 4
++#define GPIO_STOP_EN_HI 4
++#define GPIO_STOP_EN_SZ 1
++#define GPIO_STOP_POL_MSK 0x00000020
++#define GPIO_STOP_POL_I_MSK 0xffffffdf
++#define GPIO_STOP_POL_SFT 5
++#define GPIO_STOP_POL_HI 5
++#define GPIO_STOP_POL_SZ 1
++#define IQ_LOG_TIMER_MSK 0xffff0000
++#define IQ_LOG_TIMER_I_MSK 0x0000ffff
++#define IQ_LOG_TIMER_SFT 16
++#define IQ_LOG_TIMER_HI 31
++#define IQ_LOG_TIMER_SZ 16
++#define IQ_LOG_LEN_MSK 0x0000ffff
++#define IQ_LOG_LEN_I_MSK 0xffff0000
++#define IQ_LOG_LEN_SFT 0
++#define IQ_LOG_LEN_HI 15
++#define IQ_LOG_LEN_SZ 16
++#define IQ_LOG_TAIL_ADR_MSK 0x0000ffff
++#define IQ_LOG_TAIL_ADR_I_MSK 0xffff0000
++#define IQ_LOG_TAIL_ADR_SFT 0
++#define IQ_LOG_TAIL_ADR_HI 15
++#define IQ_LOG_TAIL_ADR_SZ 16
++#define ALC_LENG_MSK 0x0003ffff
++#define ALC_LENG_I_MSK 0xfffc0000
++#define ALC_LENG_SFT 0
++#define ALC_LENG_HI 17
++#define ALC_LENG_SZ 18
++#define CH0_DYN_PRI_MSK 0x00300000
++#define CH0_DYN_PRI_I_MSK 0xffcfffff
++#define CH0_DYN_PRI_SFT 20
++#define CH0_DYN_PRI_HI 21
++#define CH0_DYN_PRI_SZ 2
++#define MCU_PKTID_MSK 0xffffffff
++#define MCU_PKTID_I_MSK 0x00000000
++#define MCU_PKTID_SFT 0
++#define MCU_PKTID_HI 31
++#define MCU_PKTID_SZ 32
++#define CH0_STA_PRI_MSK 0x00000003
++#define CH0_STA_PRI_I_MSK 0xfffffffc
++#define CH0_STA_PRI_SFT 0
++#define CH0_STA_PRI_HI 1
++#define CH0_STA_PRI_SZ 2
++#define CH1_STA_PRI_MSK 0x00000030
++#define CH1_STA_PRI_I_MSK 0xffffffcf
++#define CH1_STA_PRI_SFT 4
++#define CH1_STA_PRI_HI 5
++#define CH1_STA_PRI_SZ 2
++#define CH2_STA_PRI_MSK 0x00000300
++#define CH2_STA_PRI_I_MSK 0xfffffcff
++#define CH2_STA_PRI_SFT 8
++#define CH2_STA_PRI_HI 9
++#define CH2_STA_PRI_SZ 2
++#define CH3_STA_PRI_MSK 0x00003000
++#define CH3_STA_PRI_I_MSK 0xffffcfff
++#define CH3_STA_PRI_SFT 12
++#define CH3_STA_PRI_HI 13
++#define CH3_STA_PRI_SZ 2
++#define ID_TB0_MSK 0xffffffff
++#define ID_TB0_I_MSK 0x00000000
++#define ID_TB0_SFT 0
++#define ID_TB0_HI 31
++#define ID_TB0_SZ 32
++#define ID_TB1_MSK 0xffffffff
++#define ID_TB1_I_MSK 0x00000000
++#define ID_TB1_SFT 0
++#define ID_TB1_HI 31
++#define ID_TB1_SZ 32
++#define ID_MNG_HALT_MSK 0x00000010
++#define ID_MNG_HALT_I_MSK 0xffffffef
++#define ID_MNG_HALT_SFT 4
++#define ID_MNG_HALT_HI 4
++#define ID_MNG_HALT_SZ 1
++#define ID_MNG_ERR_HALT_EN_MSK 0x00000020
++#define ID_MNG_ERR_HALT_EN_I_MSK 0xffffffdf
++#define ID_MNG_ERR_HALT_EN_SFT 5
++#define ID_MNG_ERR_HALT_EN_HI 5
++#define ID_MNG_ERR_HALT_EN_SZ 1
++#define ID_EXCEPT_FLG_CLR_MSK 0x00000040
++#define ID_EXCEPT_FLG_CLR_I_MSK 0xffffffbf
++#define ID_EXCEPT_FLG_CLR_SFT 6
++#define ID_EXCEPT_FLG_CLR_HI 6
++#define ID_EXCEPT_FLG_CLR_SZ 1
++#define ID_EXCEPT_FLG_MSK 0x00000080
++#define ID_EXCEPT_FLG_I_MSK 0xffffff7f
++#define ID_EXCEPT_FLG_SFT 7
++#define ID_EXCEPT_FLG_HI 7
++#define ID_EXCEPT_FLG_SZ 1
++#define ID_FULL_MSK 0x00000001
++#define ID_FULL_I_MSK 0xfffffffe
++#define ID_FULL_SFT 0
++#define ID_FULL_HI 0
++#define ID_FULL_SZ 1
++#define ID_MNG_BUSY_MSK 0x00000002
++#define ID_MNG_BUSY_I_MSK 0xfffffffd
++#define ID_MNG_BUSY_SFT 1
++#define ID_MNG_BUSY_HI 1
++#define ID_MNG_BUSY_SZ 1
++#define REQ_LOCK_MSK 0x00000004
++#define REQ_LOCK_I_MSK 0xfffffffb
++#define REQ_LOCK_SFT 2
++#define REQ_LOCK_HI 2
++#define REQ_LOCK_SZ 1
++#define CH0_REQ_LOCK_MSK 0x00000010
++#define CH0_REQ_LOCK_I_MSK 0xffffffef
++#define CH0_REQ_LOCK_SFT 4
++#define CH0_REQ_LOCK_HI 4
++#define CH0_REQ_LOCK_SZ 1
++#define CH1_REQ_LOCK_MSK 0x00000020
++#define CH1_REQ_LOCK_I_MSK 0xffffffdf
++#define CH1_REQ_LOCK_SFT 5
++#define CH1_REQ_LOCK_HI 5
++#define CH1_REQ_LOCK_SZ 1
++#define CH2_REQ_LOCK_MSK 0x00000040
++#define CH2_REQ_LOCK_I_MSK 0xffffffbf
++#define CH2_REQ_LOCK_SFT 6
++#define CH2_REQ_LOCK_HI 6
++#define CH2_REQ_LOCK_SZ 1
++#define CH3_REQ_LOCK_MSK 0x00000080
++#define CH3_REQ_LOCK_I_MSK 0xffffff7f
++#define CH3_REQ_LOCK_SFT 7
++#define CH3_REQ_LOCK_HI 7
++#define CH3_REQ_LOCK_SZ 1
++#define REQ_LOCK_INT_EN_MSK 0x00000100
++#define REQ_LOCK_INT_EN_I_MSK 0xfffffeff
++#define REQ_LOCK_INT_EN_SFT 8
++#define REQ_LOCK_INT_EN_HI 8
++#define REQ_LOCK_INT_EN_SZ 1
++#define REQ_LOCK_INT_MSK 0x00000200
++#define REQ_LOCK_INT_I_MSK 0xfffffdff
++#define REQ_LOCK_INT_SFT 9
++#define REQ_LOCK_INT_HI 9
++#define REQ_LOCK_INT_SZ 1
++#define MCU_ALC_READY_MSK 0x00000001
++#define MCU_ALC_READY_I_MSK 0xfffffffe
++#define MCU_ALC_READY_SFT 0
++#define MCU_ALC_READY_HI 0
++#define MCU_ALC_READY_SZ 1
++#define ALC_FAIL_MSK 0x00000002
++#define ALC_FAIL_I_MSK 0xfffffffd
++#define ALC_FAIL_SFT 1
++#define ALC_FAIL_HI 1
++#define ALC_FAIL_SZ 1
++#define ALC_BUSY_MSK 0x00000004
++#define ALC_BUSY_I_MSK 0xfffffffb
++#define ALC_BUSY_SFT 2
++#define ALC_BUSY_HI 2
++#define ALC_BUSY_SZ 1
++#define CH0_NVLD_MSK 0x00000010
++#define CH0_NVLD_I_MSK 0xffffffef
++#define CH0_NVLD_SFT 4
++#define CH0_NVLD_HI 4
++#define CH0_NVLD_SZ 1
++#define CH1_NVLD_MSK 0x00000020
++#define CH1_NVLD_I_MSK 0xffffffdf
++#define CH1_NVLD_SFT 5
++#define CH1_NVLD_HI 5
++#define CH1_NVLD_SZ 1
++#define CH2_NVLD_MSK 0x00000040
++#define CH2_NVLD_I_MSK 0xffffffbf
++#define CH2_NVLD_SFT 6
++#define CH2_NVLD_HI 6
++#define CH2_NVLD_SZ 1
++#define CH3_NVLD_MSK 0x00000080
++#define CH3_NVLD_I_MSK 0xffffff7f
++#define CH3_NVLD_SFT 7
++#define CH3_NVLD_HI 7
++#define CH3_NVLD_SZ 1
++#define ALC_INT_ID_MSK 0x00007f00
++#define ALC_INT_ID_I_MSK 0xffff80ff
++#define ALC_INT_ID_SFT 8
++#define ALC_INT_ID_HI 14
++#define ALC_INT_ID_SZ 7
++#define ALC_TIMEOUT_MSK 0x03ff0000
++#define ALC_TIMEOUT_I_MSK 0xfc00ffff
++#define ALC_TIMEOUT_SFT 16
++#define ALC_TIMEOUT_HI 25
++#define ALC_TIMEOUT_SZ 10
++#define ALC_TIMEOUT_INT_EN_MSK 0x40000000
++#define ALC_TIMEOUT_INT_EN_I_MSK 0xbfffffff
++#define ALC_TIMEOUT_INT_EN_SFT 30
++#define ALC_TIMEOUT_INT_EN_HI 30
++#define ALC_TIMEOUT_INT_EN_SZ 1
++#define ALC_TIMEOUT_INT_MSK 0x80000000
++#define ALC_TIMEOUT_INT_I_MSK 0x7fffffff
++#define ALC_TIMEOUT_INT_SFT 31
++#define ALC_TIMEOUT_INT_HI 31
++#define ALC_TIMEOUT_INT_SZ 1
++#define TX_ID_COUNT_MSK 0x000000ff
++#define TX_ID_COUNT_I_MSK 0xffffff00
++#define TX_ID_COUNT_SFT 0
++#define TX_ID_COUNT_HI 7
++#define TX_ID_COUNT_SZ 8
++#define RX_ID_COUNT_MSK 0x0000ff00
++#define RX_ID_COUNT_I_MSK 0xffff00ff
++#define RX_ID_COUNT_SFT 8
++#define RX_ID_COUNT_HI 15
++#define RX_ID_COUNT_SZ 8
++#define TX_ID_THOLD_MSK 0x000000ff
++#define TX_ID_THOLD_I_MSK 0xffffff00
++#define TX_ID_THOLD_SFT 0
++#define TX_ID_THOLD_HI 7
++#define TX_ID_THOLD_SZ 8
++#define RX_ID_THOLD_MSK 0x0000ff00
++#define RX_ID_THOLD_I_MSK 0xffff00ff
++#define RX_ID_THOLD_SFT 8
++#define RX_ID_THOLD_HI 15
++#define RX_ID_THOLD_SZ 8
++#define ID_THOLD_RX_INT_MSK 0x00010000
++#define ID_THOLD_RX_INT_I_MSK 0xfffeffff
++#define ID_THOLD_RX_INT_SFT 16
++#define ID_THOLD_RX_INT_HI 16
++#define ID_THOLD_RX_INT_SZ 1
++#define RX_INT_CH_MSK 0x000e0000
++#define RX_INT_CH_I_MSK 0xfff1ffff
++#define RX_INT_CH_SFT 17
++#define RX_INT_CH_HI 19
++#define RX_INT_CH_SZ 3
++#define ID_THOLD_TX_INT_MSK 0x00100000
++#define ID_THOLD_TX_INT_I_MSK 0xffefffff
++#define ID_THOLD_TX_INT_SFT 20
++#define ID_THOLD_TX_INT_HI 20
++#define ID_THOLD_TX_INT_SZ 1
++#define TX_INT_CH_MSK 0x00e00000
++#define TX_INT_CH_I_MSK 0xff1fffff
++#define TX_INT_CH_SFT 21
++#define TX_INT_CH_HI 23
++#define TX_INT_CH_SZ 3
++#define ID_THOLD_INT_EN_MSK 0x01000000
++#define ID_THOLD_INT_EN_I_MSK 0xfeffffff
++#define ID_THOLD_INT_EN_SFT 24
++#define ID_THOLD_INT_EN_HI 24
++#define ID_THOLD_INT_EN_SZ 1
++#define TX_ID_TB0_MSK 0xffffffff
++#define TX_ID_TB0_I_MSK 0x00000000
++#define TX_ID_TB0_SFT 0
++#define TX_ID_TB0_HI 31
++#define TX_ID_TB0_SZ 32
++#define TX_ID_TB1_MSK 0xffffffff
++#define TX_ID_TB1_I_MSK 0x00000000
++#define TX_ID_TB1_SFT 0
++#define TX_ID_TB1_HI 31
++#define TX_ID_TB1_SZ 32
++#define RX_ID_TB0_MSK 0xffffffff
++#define RX_ID_TB0_I_MSK 0x00000000
++#define RX_ID_TB0_SFT 0
++#define RX_ID_TB0_HI 31
++#define RX_ID_TB0_SZ 32
++#define RX_ID_TB1_MSK 0xffffffff
++#define RX_ID_TB1_I_MSK 0x00000000
++#define RX_ID_TB1_SFT 0
++#define RX_ID_TB1_HI 31
++#define RX_ID_TB1_SZ 32
++#define DOUBLE_RLS_INT_EN_MSK 0x00000001
++#define DOUBLE_RLS_INT_EN_I_MSK 0xfffffffe
++#define DOUBLE_RLS_INT_EN_SFT 0
++#define DOUBLE_RLS_INT_EN_HI 0
++#define DOUBLE_RLS_INT_EN_SZ 1
++#define ID_DOUBLE_RLS_INT_MSK 0x00000002
++#define ID_DOUBLE_RLS_INT_I_MSK 0xfffffffd
++#define ID_DOUBLE_RLS_INT_SFT 1
++#define ID_DOUBLE_RLS_INT_HI 1
++#define ID_DOUBLE_RLS_INT_SZ 1
++#define DOUBLE_RLS_ID_MSK 0x00007f00
++#define DOUBLE_RLS_ID_I_MSK 0xffff80ff
++#define DOUBLE_RLS_ID_SFT 8
++#define DOUBLE_RLS_ID_HI 14
++#define DOUBLE_RLS_ID_SZ 7
++#define ID_LEN_THOLD_INT_EN_MSK 0x00000001
++#define ID_LEN_THOLD_INT_EN_I_MSK 0xfffffffe
++#define ID_LEN_THOLD_INT_EN_SFT 0
++#define ID_LEN_THOLD_INT_EN_HI 0
++#define ID_LEN_THOLD_INT_EN_SZ 1
++#define ALL_ID_LEN_THOLD_INT_MSK 0x00000002
++#define ALL_ID_LEN_THOLD_INT_I_MSK 0xfffffffd
++#define ALL_ID_LEN_THOLD_INT_SFT 1
++#define ALL_ID_LEN_THOLD_INT_HI 1
++#define ALL_ID_LEN_THOLD_INT_SZ 1
++#define TX_ID_LEN_THOLD_INT_MSK 0x00000004
++#define TX_ID_LEN_THOLD_INT_I_MSK 0xfffffffb
++#define TX_ID_LEN_THOLD_INT_SFT 2
++#define TX_ID_LEN_THOLD_INT_HI 2
++#define TX_ID_LEN_THOLD_INT_SZ 1
++#define RX_ID_LEN_THOLD_INT_MSK 0x00000008
++#define RX_ID_LEN_THOLD_INT_I_MSK 0xfffffff7
++#define RX_ID_LEN_THOLD_INT_SFT 3
++#define RX_ID_LEN_THOLD_INT_HI 3
++#define RX_ID_LEN_THOLD_INT_SZ 1
++#define ID_TX_LEN_THOLD_MSK 0x00001ff0
++#define ID_TX_LEN_THOLD_I_MSK 0xffffe00f
++#define ID_TX_LEN_THOLD_SFT 4
++#define ID_TX_LEN_THOLD_HI 12
++#define ID_TX_LEN_THOLD_SZ 9
++#define ID_RX_LEN_THOLD_MSK 0x003fe000
++#define ID_RX_LEN_THOLD_I_MSK 0xffc01fff
++#define ID_RX_LEN_THOLD_SFT 13
++#define ID_RX_LEN_THOLD_HI 21
++#define ID_RX_LEN_THOLD_SZ 9
++#define ID_LEN_THOLD_MSK 0x7fc00000
++#define ID_LEN_THOLD_I_MSK 0x803fffff
++#define ID_LEN_THOLD_SFT 22
++#define ID_LEN_THOLD_HI 30
++#define ID_LEN_THOLD_SZ 9
++#define ALL_ID_ALC_LEN_MSK 0x000001ff
++#define ALL_ID_ALC_LEN_I_MSK 0xfffffe00
++#define ALL_ID_ALC_LEN_SFT 0
++#define ALL_ID_ALC_LEN_HI 8
++#define ALL_ID_ALC_LEN_SZ 9
++#define TX_ID_ALC_LEN_MSK 0x0003fe00
++#define TX_ID_ALC_LEN_I_MSK 0xfffc01ff
++#define TX_ID_ALC_LEN_SFT 9
++#define TX_ID_ALC_LEN_HI 17
++#define TX_ID_ALC_LEN_SZ 9
++#define RX_ID_ALC_LEN_MSK 0x07fc0000
++#define RX_ID_ALC_LEN_I_MSK 0xf803ffff
++#define RX_ID_ALC_LEN_SFT 18
++#define RX_ID_ALC_LEN_HI 26
++#define RX_ID_ALC_LEN_SZ 9
++#define CH_ARB_EN_MSK 0x00000001
++#define CH_ARB_EN_I_MSK 0xfffffffe
++#define CH_ARB_EN_SFT 0
++#define CH_ARB_EN_HI 0
++#define CH_ARB_EN_SZ 1
++#define CH_PRI1_MSK 0x00000030
++#define CH_PRI1_I_MSK 0xffffffcf
++#define CH_PRI1_SFT 4
++#define CH_PRI1_HI 5
++#define CH_PRI1_SZ 2
++#define CH_PRI2_MSK 0x00000300
++#define CH_PRI2_I_MSK 0xfffffcff
++#define CH_PRI2_SFT 8
++#define CH_PRI2_HI 9
++#define CH_PRI2_SZ 2
++#define CH_PRI3_MSK 0x00003000
++#define CH_PRI3_I_MSK 0xffffcfff
++#define CH_PRI3_SFT 12
++#define CH_PRI3_HI 13
++#define CH_PRI3_SZ 2
++#define CH_PRI4_MSK 0x00030000
++#define CH_PRI4_I_MSK 0xfffcffff
++#define CH_PRI4_SFT 16
++#define CH_PRI4_HI 17
++#define CH_PRI4_SZ 2
++#define TX_ID_REMAIN_MSK 0x0000007f
++#define TX_ID_REMAIN_I_MSK 0xffffff80
++#define TX_ID_REMAIN_SFT 0
++#define TX_ID_REMAIN_HI 6
++#define TX_ID_REMAIN_SZ 7
++#define TX_PAGE_REMAIN_MSK 0x0001ff00
++#define TX_PAGE_REMAIN_I_MSK 0xfffe00ff
++#define TX_PAGE_REMAIN_SFT 8
++#define TX_PAGE_REMAIN_HI 16
++#define TX_PAGE_REMAIN_SZ 9
++#define ID_PAGE_MAX_SIZE_MSK 0x000001ff
++#define ID_PAGE_MAX_SIZE_I_MSK 0xfffffe00
++#define ID_PAGE_MAX_SIZE_SFT 0
++#define ID_PAGE_MAX_SIZE_HI 8
++#define ID_PAGE_MAX_SIZE_SZ 9
++#define TX_PAGE_LIMIT_MSK 0x000001ff
++#define TX_PAGE_LIMIT_I_MSK 0xfffffe00
++#define TX_PAGE_LIMIT_SFT 0
++#define TX_PAGE_LIMIT_HI 8
++#define TX_PAGE_LIMIT_SZ 9
++#define TX_COUNT_LIMIT_MSK 0x00ff0000
++#define TX_COUNT_LIMIT_I_MSK 0xff00ffff
++#define TX_COUNT_LIMIT_SFT 16
++#define TX_COUNT_LIMIT_HI 23
++#define TX_COUNT_LIMIT_SZ 8
++#define TX_LIMIT_INT_MSK 0x40000000
++#define TX_LIMIT_INT_I_MSK 0xbfffffff
++#define TX_LIMIT_INT_SFT 30
++#define TX_LIMIT_INT_HI 30
++#define TX_LIMIT_INT_SZ 1
++#define TX_LIMIT_INT_EN_MSK 0x80000000
++#define TX_LIMIT_INT_EN_I_MSK 0x7fffffff
++#define TX_LIMIT_INT_EN_SFT 31
++#define TX_LIMIT_INT_EN_HI 31
++#define TX_LIMIT_INT_EN_SZ 1
++#define TX_PAGE_USE_7_0_MSK 0x000000ff
++#define TX_PAGE_USE_7_0_I_MSK 0xffffff00
++#define TX_PAGE_USE_7_0_SFT 0
++#define TX_PAGE_USE_7_0_HI 7
++#define TX_PAGE_USE_7_0_SZ 8
++#define TX_ID_USE_5_0_MSK 0x00003f00
++#define TX_ID_USE_5_0_I_MSK 0xffffc0ff
++#define TX_ID_USE_5_0_SFT 8
++#define TX_ID_USE_5_0_HI 13
++#define TX_ID_USE_5_0_SZ 6
++#define EDCA0_FFO_CNT_MSK 0x0003c000
++#define EDCA0_FFO_CNT_I_MSK 0xfffc3fff
++#define EDCA0_FFO_CNT_SFT 14
++#define EDCA0_FFO_CNT_HI 17
++#define EDCA0_FFO_CNT_SZ 4
++#define EDCA1_FFO_CNT_3_0_MSK 0x003c0000
++#define EDCA1_FFO_CNT_3_0_I_MSK 0xffc3ffff
++#define EDCA1_FFO_CNT_3_0_SFT 18
++#define EDCA1_FFO_CNT_3_0_HI 21
++#define EDCA1_FFO_CNT_3_0_SZ 4
++#define EDCA2_FFO_CNT_MSK 0x07c00000
++#define EDCA2_FFO_CNT_I_MSK 0xf83fffff
++#define EDCA2_FFO_CNT_SFT 22
++#define EDCA2_FFO_CNT_HI 26
++#define EDCA2_FFO_CNT_SZ 5
++#define EDCA3_FFO_CNT_MSK 0xf8000000
++#define EDCA3_FFO_CNT_I_MSK 0x07ffffff
++#define EDCA3_FFO_CNT_SFT 27
++#define EDCA3_FFO_CNT_HI 31
++#define EDCA3_FFO_CNT_SZ 5
++#define ID_TB2_MSK 0xffffffff
++#define ID_TB2_I_MSK 0x00000000
++#define ID_TB2_SFT 0
++#define ID_TB2_HI 31
++#define ID_TB2_SZ 32
++#define ID_TB3_MSK 0xffffffff
++#define ID_TB3_I_MSK 0x00000000
++#define ID_TB3_SFT 0
++#define ID_TB3_HI 31
++#define ID_TB3_SZ 32
++#define TX_ID_TB2_MSK 0xffffffff
++#define TX_ID_TB2_I_MSK 0x00000000
++#define TX_ID_TB2_SFT 0
++#define TX_ID_TB2_HI 31
++#define TX_ID_TB2_SZ 32
++#define TX_ID_TB3_MSK 0xffffffff
++#define TX_ID_TB3_I_MSK 0x00000000
++#define TX_ID_TB3_SFT 0
++#define TX_ID_TB3_HI 31
++#define TX_ID_TB3_SZ 32
++#define RX_ID_TB2_MSK 0xffffffff
++#define RX_ID_TB2_I_MSK 0x00000000
++#define RX_ID_TB2_SFT 0
++#define RX_ID_TB2_HI 31
++#define RX_ID_TB2_SZ 32
++#define RX_ID_TB3_MSK 0xffffffff
++#define RX_ID_TB3_I_MSK 0x00000000
++#define RX_ID_TB3_SFT 0
++#define RX_ID_TB3_HI 31
++#define RX_ID_TB3_SZ 32
++#define TX_PAGE_USE2_MSK 0x000001ff
++#define TX_PAGE_USE2_I_MSK 0xfffffe00
++#define TX_PAGE_USE2_SFT 0
++#define TX_PAGE_USE2_HI 8
++#define TX_PAGE_USE2_SZ 9
++#define TX_ID_USE2_MSK 0x0001fe00
++#define TX_ID_USE2_I_MSK 0xfffe01ff
++#define TX_ID_USE2_SFT 9
++#define TX_ID_USE2_HI 16
++#define TX_ID_USE2_SZ 8
++#define EDCA4_FFO_CNT_MSK 0x001e0000
++#define EDCA4_FFO_CNT_I_MSK 0xffe1ffff
++#define EDCA4_FFO_CNT_SFT 17
++#define EDCA4_FFO_CNT_HI 20
++#define EDCA4_FFO_CNT_SZ 4
++#define TX_PAGE_USE3_MSK 0x000001ff
++#define TX_PAGE_USE3_I_MSK 0xfffffe00
++#define TX_PAGE_USE3_SFT 0
++#define TX_PAGE_USE3_HI 8
++#define TX_PAGE_USE3_SZ 9
++#define TX_ID_USE3_MSK 0x0001fe00
++#define TX_ID_USE3_I_MSK 0xfffe01ff
++#define TX_ID_USE3_SFT 9
++#define TX_ID_USE3_HI 16
++#define TX_ID_USE3_SZ 8
++#define EDCA1_FFO_CNT2_MSK 0x03e00000
++#define EDCA1_FFO_CNT2_I_MSK 0xfc1fffff
++#define EDCA1_FFO_CNT2_SFT 21
++#define EDCA1_FFO_CNT2_HI 25
++#define EDCA1_FFO_CNT2_SZ 5
++#define EDCA4_FFO_CNT2_MSK 0x3c000000
++#define EDCA4_FFO_CNT2_I_MSK 0xc3ffffff
++#define EDCA4_FFO_CNT2_SFT 26
++#define EDCA4_FFO_CNT2_HI 29
++#define EDCA4_FFO_CNT2_SZ 4
++#define TX_PAGE_USE4_MSK 0x000001ff
++#define TX_PAGE_USE4_I_MSK 0xfffffe00
++#define TX_PAGE_USE4_SFT 0
++#define TX_PAGE_USE4_HI 8
++#define TX_PAGE_USE4_SZ 9
++#define TX_ID_USE4_MSK 0x0001fe00
++#define TX_ID_USE4_I_MSK 0xfffe01ff
++#define TX_ID_USE4_SFT 9
++#define TX_ID_USE4_HI 16
++#define TX_ID_USE4_SZ 8
++#define EDCA2_FFO_CNT2_MSK 0x003e0000
++#define EDCA2_FFO_CNT2_I_MSK 0xffc1ffff
++#define EDCA2_FFO_CNT2_SFT 17
++#define EDCA2_FFO_CNT2_HI 21
++#define EDCA2_FFO_CNT2_SZ 5
++#define EDCA3_FFO_CNT2_MSK 0x07c00000
++#define EDCA3_FFO_CNT2_I_MSK 0xf83fffff
++#define EDCA3_FFO_CNT2_SFT 22
++#define EDCA3_FFO_CNT2_HI 26
++#define EDCA3_FFO_CNT2_SZ 5
++#define TX_ID_IFO_LEN_MSK 0x000001ff
++#define TX_ID_IFO_LEN_I_MSK 0xfffffe00
++#define TX_ID_IFO_LEN_SFT 0
++#define TX_ID_IFO_LEN_HI 8
++#define TX_ID_IFO_LEN_SZ 9
++#define RX_ID_IFO_LEN_MSK 0x01ff0000
++#define RX_ID_IFO_LEN_I_MSK 0xfe00ffff
++#define RX_ID_IFO_LEN_SFT 16
++#define RX_ID_IFO_LEN_HI 24
++#define RX_ID_IFO_LEN_SZ 9
++#define MAX_ALL_ALC_ID_CNT_MSK 0x000000ff
++#define MAX_ALL_ALC_ID_CNT_I_MSK 0xffffff00
++#define MAX_ALL_ALC_ID_CNT_SFT 0
++#define MAX_ALL_ALC_ID_CNT_HI 7
++#define MAX_ALL_ALC_ID_CNT_SZ 8
++#define MAX_TX_ALC_ID_CNT_MSK 0x0000ff00
++#define MAX_TX_ALC_ID_CNT_I_MSK 0xffff00ff
++#define MAX_TX_ALC_ID_CNT_SFT 8
++#define MAX_TX_ALC_ID_CNT_HI 15
++#define MAX_TX_ALC_ID_CNT_SZ 8
++#define MAX_RX_ALC_ID_CNT_MSK 0x00ff0000
++#define MAX_RX_ALC_ID_CNT_I_MSK 0xff00ffff
++#define MAX_RX_ALC_ID_CNT_SFT 16
++#define MAX_RX_ALC_ID_CNT_HI 23
++#define MAX_RX_ALC_ID_CNT_SZ 8
++#define MAX_ALL_ID_ALC_LEN_MSK 0x000001ff
++#define MAX_ALL_ID_ALC_LEN_I_MSK 0xfffffe00
++#define MAX_ALL_ID_ALC_LEN_SFT 0
++#define MAX_ALL_ID_ALC_LEN_HI 8
++#define MAX_ALL_ID_ALC_LEN_SZ 9
++#define MAX_TX_ID_ALC_LEN_MSK 0x0003fe00
++#define MAX_TX_ID_ALC_LEN_I_MSK 0xfffc01ff
++#define MAX_TX_ID_ALC_LEN_SFT 9
++#define MAX_TX_ID_ALC_LEN_HI 17
++#define MAX_TX_ID_ALC_LEN_SZ 9
++#define MAX_RX_ID_ALC_LEN_MSK 0x07fc0000
++#define MAX_RX_ID_ALC_LEN_I_MSK 0xf803ffff
++#define MAX_RX_ID_ALC_LEN_SFT 18
++#define MAX_RX_ID_ALC_LEN_HI 26
++#define MAX_RX_ID_ALC_LEN_SZ 9
++#define RG_PMDLBK_MSK 0x00000001
++#define RG_PMDLBK_I_MSK 0xfffffffe
++#define RG_PMDLBK_SFT 0
++#define RG_PMDLBK_HI 0
++#define RG_PMDLBK_SZ 1
++#define RG_RDYACK_SEL_MSK 0x00000006
++#define RG_RDYACK_SEL_I_MSK 0xfffffff9
++#define RG_RDYACK_SEL_SFT 1
++#define RG_RDYACK_SEL_HI 2
++#define RG_RDYACK_SEL_SZ 2
++#define RG_ADEDGE_SEL_MSK 0x00000008
++#define RG_ADEDGE_SEL_I_MSK 0xfffffff7
++#define RG_ADEDGE_SEL_SFT 3
++#define RG_ADEDGE_SEL_HI 3
++#define RG_ADEDGE_SEL_SZ 1
++#define RG_SIGN_SWAP_MSK 0x00000010
++#define RG_SIGN_SWAP_I_MSK 0xffffffef
++#define RG_SIGN_SWAP_SFT 4
++#define RG_SIGN_SWAP_HI 4
++#define RG_SIGN_SWAP_SZ 1
++#define RG_IQ_SWAP_MSK 0x00000020
++#define RG_IQ_SWAP_I_MSK 0xffffffdf
++#define RG_IQ_SWAP_SFT 5
++#define RG_IQ_SWAP_HI 5
++#define RG_IQ_SWAP_SZ 1
++#define RG_Q_INV_MSK 0x00000040
++#define RG_Q_INV_I_MSK 0xffffffbf
++#define RG_Q_INV_SFT 6
++#define RG_Q_INV_HI 6
++#define RG_Q_INV_SZ 1
++#define RG_I_INV_MSK 0x00000080
++#define RG_I_INV_I_MSK 0xffffff7f
++#define RG_I_INV_SFT 7
++#define RG_I_INV_HI 7
++#define RG_I_INV_SZ 1
++#define RG_BYPASS_ACI_MSK 0x00000100
++#define RG_BYPASS_ACI_I_MSK 0xfffffeff
++#define RG_BYPASS_ACI_SFT 8
++#define RG_BYPASS_ACI_HI 8
++#define RG_BYPASS_ACI_SZ 1
++#define RG_LBK_ANA_PATH_MSK 0x00000200
++#define RG_LBK_ANA_PATH_I_MSK 0xfffffdff
++#define RG_LBK_ANA_PATH_SFT 9
++#define RG_LBK_ANA_PATH_HI 9
++#define RG_LBK_ANA_PATH_SZ 1
++#define RG_SPECTRUM_LEAKY_FACTOR_MSK 0x00000c00
++#define RG_SPECTRUM_LEAKY_FACTOR_I_MSK 0xfffff3ff
++#define RG_SPECTRUM_LEAKY_FACTOR_SFT 10
++#define RG_SPECTRUM_LEAKY_FACTOR_HI 11
++#define RG_SPECTRUM_LEAKY_FACTOR_SZ 2
++#define RG_SPECTRUM_BW_MSK 0x00003000
++#define RG_SPECTRUM_BW_I_MSK 0xffffcfff
++#define RG_SPECTRUM_BW_SFT 12
++#define RG_SPECTRUM_BW_HI 13
++#define RG_SPECTRUM_BW_SZ 2
++#define RG_SPECTRUM_FREQ_MANUAL_MSK 0x00004000
++#define RG_SPECTRUM_FREQ_MANUAL_I_MSK 0xffffbfff
++#define RG_SPECTRUM_FREQ_MANUAL_SFT 14
++#define RG_SPECTRUM_FREQ_MANUAL_HI 14
++#define RG_SPECTRUM_FREQ_MANUAL_SZ 1
++#define RG_SPECTRUM_EN_MSK 0x00008000
++#define RG_SPECTRUM_EN_I_MSK 0xffff7fff
++#define RG_SPECTRUM_EN_SFT 15
++#define RG_SPECTRUM_EN_HI 15
++#define RG_SPECTRUM_EN_SZ 1
++#define RG_TXPWRLVL_SET_MSK 0x00ff0000
++#define RG_TXPWRLVL_SET_I_MSK 0xff00ffff
++#define RG_TXPWRLVL_SET_SFT 16
++#define RG_TXPWRLVL_SET_HI 23
++#define RG_TXPWRLVL_SET_SZ 8
++#define RG_TXPWRLVL_SEL_MSK 0x01000000
++#define RG_TXPWRLVL_SEL_I_MSK 0xfeffffff
++#define RG_TXPWRLVL_SEL_SFT 24
++#define RG_TXPWRLVL_SEL_HI 24
++#define RG_TXPWRLVL_SEL_SZ 1
++#define RG_RF_BB_CLK_SEL_MSK 0x80000000
++#define RG_RF_BB_CLK_SEL_I_MSK 0x7fffffff
++#define RG_RF_BB_CLK_SEL_SFT 31
++#define RG_RF_BB_CLK_SEL_HI 31
++#define RG_RF_BB_CLK_SEL_SZ 1
++#define RG_PHY_MD_EN_MSK 0x00000001
++#define RG_PHY_MD_EN_I_MSK 0xfffffffe
++#define RG_PHY_MD_EN_SFT 0
++#define RG_PHY_MD_EN_HI 0
++#define RG_PHY_MD_EN_SZ 1
++#define RG_PHYRX_MD_EN_MSK 0x00000002
++#define RG_PHYRX_MD_EN_I_MSK 0xfffffffd
++#define RG_PHYRX_MD_EN_SFT 1
++#define RG_PHYRX_MD_EN_HI 1
++#define RG_PHYRX_MD_EN_SZ 1
++#define RG_PHYTX_MD_EN_MSK 0x00000004
++#define RG_PHYTX_MD_EN_I_MSK 0xfffffffb
++#define RG_PHYTX_MD_EN_SFT 2
++#define RG_PHYTX_MD_EN_HI 2
++#define RG_PHYTX_MD_EN_SZ 1
++#define RG_PHY11GN_MD_EN_MSK 0x00000008
++#define RG_PHY11GN_MD_EN_I_MSK 0xfffffff7
++#define RG_PHY11GN_MD_EN_SFT 3
++#define RG_PHY11GN_MD_EN_HI 3
++#define RG_PHY11GN_MD_EN_SZ 1
++#define RG_PHY11B_MD_EN_MSK 0x00000010
++#define RG_PHY11B_MD_EN_I_MSK 0xffffffef
++#define RG_PHY11B_MD_EN_SFT 4
++#define RG_PHY11B_MD_EN_HI 4
++#define RG_PHY11B_MD_EN_SZ 1
++#define RG_PHYRXFIFO_MD_EN_MSK 0x00000020
++#define RG_PHYRXFIFO_MD_EN_I_MSK 0xffffffdf
++#define RG_PHYRXFIFO_MD_EN_SFT 5
++#define RG_PHYRXFIFO_MD_EN_HI 5
++#define RG_PHYRXFIFO_MD_EN_SZ 1
++#define RG_PHYTXFIFO_MD_EN_MSK 0x00000040
++#define RG_PHYTXFIFO_MD_EN_I_MSK 0xffffffbf
++#define RG_PHYTXFIFO_MD_EN_SFT 6
++#define RG_PHYTXFIFO_MD_EN_HI 6
++#define RG_PHYTXFIFO_MD_EN_SZ 1
++#define RG_PHY11BGN_MD_EN_MSK 0x00000100
++#define RG_PHY11BGN_MD_EN_I_MSK 0xfffffeff
++#define RG_PHY11BGN_MD_EN_SFT 8
++#define RG_PHY11BGN_MD_EN_HI 8
++#define RG_PHY11BGN_MD_EN_SZ 1
++#define RG_FORCE_11GN_EN_MSK 0x00001000
++#define RG_FORCE_11GN_EN_I_MSK 0xffffefff
++#define RG_FORCE_11GN_EN_SFT 12
++#define RG_FORCE_11GN_EN_HI 12
++#define RG_FORCE_11GN_EN_SZ 1
++#define RG_FORCE_11B_EN_MSK 0x00002000
++#define RG_FORCE_11B_EN_I_MSK 0xffffdfff
++#define RG_FORCE_11B_EN_SFT 13
++#define RG_FORCE_11B_EN_HI 13
++#define RG_FORCE_11B_EN_SZ 1
++#define RG_FFT_MEM_CLK_EN_RX_MSK 0x00004000
++#define RG_FFT_MEM_CLK_EN_RX_I_MSK 0xffffbfff
++#define RG_FFT_MEM_CLK_EN_RX_SFT 14
++#define RG_FFT_MEM_CLK_EN_RX_HI 14
++#define RG_FFT_MEM_CLK_EN_RX_SZ 1
++#define RG_FFT_MEM_CLK_EN_TX_MSK 0x00008000
++#define RG_FFT_MEM_CLK_EN_TX_I_MSK 0xffff7fff
++#define RG_FFT_MEM_CLK_EN_TX_SFT 15
++#define RG_FFT_MEM_CLK_EN_TX_HI 15
++#define RG_FFT_MEM_CLK_EN_TX_SZ 1
++#define RG_PHY_IQ_TRIG_SEL_MSK 0x000f0000
++#define RG_PHY_IQ_TRIG_SEL_I_MSK 0xfff0ffff
++#define RG_PHY_IQ_TRIG_SEL_SFT 16
++#define RG_PHY_IQ_TRIG_SEL_HI 19
++#define RG_PHY_IQ_TRIG_SEL_SZ 4
++#define RG_SPECTRUM_FREQ_MSK 0x3ff00000
++#define RG_SPECTRUM_FREQ_I_MSK 0xc00fffff
++#define RG_SPECTRUM_FREQ_SFT 20
++#define RG_SPECTRUM_FREQ_HI 29
++#define RG_SPECTRUM_FREQ_SZ 10
++#define SVN_VERSION_MSK 0xffffffff
++#define SVN_VERSION_I_MSK 0x00000000
++#define SVN_VERSION_SFT 0
++#define SVN_VERSION_HI 31
++#define SVN_VERSION_SZ 32
++#define RG_LENGTH_MSK 0x0000ffff
++#define RG_LENGTH_I_MSK 0xffff0000
++#define RG_LENGTH_SFT 0
++#define RG_LENGTH_HI 15
++#define RG_LENGTH_SZ 16
++#define RG_PKT_MODE_MSK 0x00070000
++#define RG_PKT_MODE_I_MSK 0xfff8ffff
++#define RG_PKT_MODE_SFT 16
++#define RG_PKT_MODE_HI 18
++#define RG_PKT_MODE_SZ 3
++#define RG_CH_BW_MSK 0x00380000
++#define RG_CH_BW_I_MSK 0xffc7ffff
++#define RG_CH_BW_SFT 19
++#define RG_CH_BW_HI 21
++#define RG_CH_BW_SZ 3
++#define RG_PRM_MSK 0x00400000
++#define RG_PRM_I_MSK 0xffbfffff
++#define RG_PRM_SFT 22
++#define RG_PRM_HI 22
++#define RG_PRM_SZ 1
++#define RG_SHORTGI_MSK 0x00800000
++#define RG_SHORTGI_I_MSK 0xff7fffff
++#define RG_SHORTGI_SFT 23
++#define RG_SHORTGI_HI 23
++#define RG_SHORTGI_SZ 1
++#define RG_RATE_MSK 0x7f000000
++#define RG_RATE_I_MSK 0x80ffffff
++#define RG_RATE_SFT 24
++#define RG_RATE_HI 30
++#define RG_RATE_SZ 7
++#define RG_L_LENGTH_MSK 0x00000fff
++#define RG_L_LENGTH_I_MSK 0xfffff000
++#define RG_L_LENGTH_SFT 0
++#define RG_L_LENGTH_HI 11
++#define RG_L_LENGTH_SZ 12
++#define RG_L_RATE_MSK 0x00007000
++#define RG_L_RATE_I_MSK 0xffff8fff
++#define RG_L_RATE_SFT 12
++#define RG_L_RATE_HI 14
++#define RG_L_RATE_SZ 3
++#define RG_SERVICE_MSK 0xffff0000
++#define RG_SERVICE_I_MSK 0x0000ffff
++#define RG_SERVICE_SFT 16
++#define RG_SERVICE_HI 31
++#define RG_SERVICE_SZ 16
++#define RG_SMOOTHING_MSK 0x00000001
++#define RG_SMOOTHING_I_MSK 0xfffffffe
++#define RG_SMOOTHING_SFT 0
++#define RG_SMOOTHING_HI 0
++#define RG_SMOOTHING_SZ 1
++#define RG_NO_SOUND_MSK 0x00000002
++#define RG_NO_SOUND_I_MSK 0xfffffffd
++#define RG_NO_SOUND_SFT 1
++#define RG_NO_SOUND_HI 1
++#define RG_NO_SOUND_SZ 1
++#define RG_AGGREGATE_MSK 0x00000004
++#define RG_AGGREGATE_I_MSK 0xfffffffb
++#define RG_AGGREGATE_SFT 2
++#define RG_AGGREGATE_HI 2
++#define RG_AGGREGATE_SZ 1
++#define RG_STBC_MSK 0x00000018
++#define RG_STBC_I_MSK 0xffffffe7
++#define RG_STBC_SFT 3
++#define RG_STBC_HI 4
++#define RG_STBC_SZ 2
++#define RG_FEC_MSK 0x00000020
++#define RG_FEC_I_MSK 0xffffffdf
++#define RG_FEC_SFT 5
++#define RG_FEC_HI 5
++#define RG_FEC_SZ 1
++#define RG_N_ESS_MSK 0x000000c0
++#define RG_N_ESS_I_MSK 0xffffff3f
++#define RG_N_ESS_SFT 6
++#define RG_N_ESS_HI 7
++#define RG_N_ESS_SZ 2
++#define RG_TXPWRLVL_MSK 0x0000ff00
++#define RG_TXPWRLVL_I_MSK 0xffff00ff
++#define RG_TXPWRLVL_SFT 8
++#define RG_TXPWRLVL_HI 15
++#define RG_TXPWRLVL_SZ 8
++#define RG_TX_START_MSK 0x00000001
++#define RG_TX_START_I_MSK 0xfffffffe
++#define RG_TX_START_SFT 0
++#define RG_TX_START_HI 0
++#define RG_TX_START_SZ 1
++#define RG_IFS_TIME_MSK 0x000000fc
++#define RG_IFS_TIME_I_MSK 0xffffff03
++#define RG_IFS_TIME_SFT 2
++#define RG_IFS_TIME_HI 7
++#define RG_IFS_TIME_SZ 6
++#define RG_CONTINUOUS_DATA_MSK 0x00000100
++#define RG_CONTINUOUS_DATA_I_MSK 0xfffffeff
++#define RG_CONTINUOUS_DATA_SFT 8
++#define RG_CONTINUOUS_DATA_HI 8
++#define RG_CONTINUOUS_DATA_SZ 1
++#define RG_DATA_SEL_MSK 0x00000600
++#define RG_DATA_SEL_I_MSK 0xfffff9ff
++#define RG_DATA_SEL_SFT 9
++#define RG_DATA_SEL_HI 10
++#define RG_DATA_SEL_SZ 2
++#define RG_TX_D_MSK 0x00ff0000
++#define RG_TX_D_I_MSK 0xff00ffff
++#define RG_TX_D_SFT 16
++#define RG_TX_D_HI 23
++#define RG_TX_D_SZ 8
++#define RG_TX_CNT_TARGET_MSK 0xffffffff
++#define RG_TX_CNT_TARGET_I_MSK 0x00000000
++#define RG_TX_CNT_TARGET_SFT 0
++#define RG_TX_CNT_TARGET_HI 31
++#define RG_TX_CNT_TARGET_SZ 32
++#define RG_FFT_IFFT_MODE_MSK 0x000000c0
++#define RG_FFT_IFFT_MODE_I_MSK 0xffffff3f
++#define RG_FFT_IFFT_MODE_SFT 6
++#define RG_FFT_IFFT_MODE_HI 7
++#define RG_FFT_IFFT_MODE_SZ 2
++#define RG_DAC_DBG_MODE_MSK 0x00000100
++#define RG_DAC_DBG_MODE_I_MSK 0xfffffeff
++#define RG_DAC_DBG_MODE_SFT 8
++#define RG_DAC_DBG_MODE_HI 8
++#define RG_DAC_DBG_MODE_SZ 1
++#define RG_DAC_SGN_SWAP_MSK 0x00000200
++#define RG_DAC_SGN_SWAP_I_MSK 0xfffffdff
++#define RG_DAC_SGN_SWAP_SFT 9
++#define RG_DAC_SGN_SWAP_HI 9
++#define RG_DAC_SGN_SWAP_SZ 1
++#define RG_TXD_SEL_MSK 0x00000c00
++#define RG_TXD_SEL_I_MSK 0xfffff3ff
++#define RG_TXD_SEL_SFT 10
++#define RG_TXD_SEL_HI 11
++#define RG_TXD_SEL_SZ 2
++#define RG_UP8X_MSK 0x00ff0000
++#define RG_UP8X_I_MSK 0xff00ffff
++#define RG_UP8X_SFT 16
++#define RG_UP8X_HI 23
++#define RG_UP8X_SZ 8
++#define RG_IQ_DC_BYP_MSK 0x01000000
++#define RG_IQ_DC_BYP_I_MSK 0xfeffffff
++#define RG_IQ_DC_BYP_SFT 24
++#define RG_IQ_DC_BYP_HI 24
++#define RG_IQ_DC_BYP_SZ 1
++#define RG_IQ_DC_LEAKY_FACTOR_MSK 0x30000000
++#define RG_IQ_DC_LEAKY_FACTOR_I_MSK 0xcfffffff
++#define RG_IQ_DC_LEAKY_FACTOR_SFT 28
++#define RG_IQ_DC_LEAKY_FACTOR_HI 29
++#define RG_IQ_DC_LEAKY_FACTOR_SZ 2
++#define RG_DAC_DCEN_MSK 0x00000001
++#define RG_DAC_DCEN_I_MSK 0xfffffffe
++#define RG_DAC_DCEN_SFT 0
++#define RG_DAC_DCEN_HI 0
++#define RG_DAC_DCEN_SZ 1
++#define RG_DAC_DCQ_MSK 0x00003ff0
++#define RG_DAC_DCQ_I_MSK 0xffffc00f
++#define RG_DAC_DCQ_SFT 4
++#define RG_DAC_DCQ_HI 13
++#define RG_DAC_DCQ_SZ 10
++#define RG_DAC_DCI_MSK 0x03ff0000
++#define RG_DAC_DCI_I_MSK 0xfc00ffff
++#define RG_DAC_DCI_SFT 16
++#define RG_DAC_DCI_HI 25
++#define RG_DAC_DCI_SZ 10
++#define RG_PGA_REFDB_SAT_MSK 0x0000007f
++#define RG_PGA_REFDB_SAT_I_MSK 0xffffff80
++#define RG_PGA_REFDB_SAT_SFT 0
++#define RG_PGA_REFDB_SAT_HI 6
++#define RG_PGA_REFDB_SAT_SZ 7
++#define RG_PGA_REFDB_TOP_MSK 0x00007f00
++#define RG_PGA_REFDB_TOP_I_MSK 0xffff80ff
++#define RG_PGA_REFDB_TOP_SFT 8
++#define RG_PGA_REFDB_TOP_HI 14
++#define RG_PGA_REFDB_TOP_SZ 7
++#define RG_PGA_REF_UND_MSK 0x03ff0000
++#define RG_PGA_REF_UND_I_MSK 0xfc00ffff
++#define RG_PGA_REF_UND_SFT 16
++#define RG_PGA_REF_UND_HI 25
++#define RG_PGA_REF_UND_SZ 10
++#define RG_RF_REF_SAT_MSK 0xf0000000
++#define RG_RF_REF_SAT_I_MSK 0x0fffffff
++#define RG_RF_REF_SAT_SFT 28
++#define RG_RF_REF_SAT_HI 31
++#define RG_RF_REF_SAT_SZ 4
++#define RG_PGAGC_SET_MSK 0x0000000f
++#define RG_PGAGC_SET_I_MSK 0xfffffff0
++#define RG_PGAGC_SET_SFT 0
++#define RG_PGAGC_SET_HI 3
++#define RG_PGAGC_SET_SZ 4
++#define RG_PGAGC_OW_MSK 0x00000010
++#define RG_PGAGC_OW_I_MSK 0xffffffef
++#define RG_PGAGC_OW_SFT 4
++#define RG_PGAGC_OW_HI 4
++#define RG_PGAGC_OW_SZ 1
++#define RG_RFGC_SET_MSK 0x00000060
++#define RG_RFGC_SET_I_MSK 0xffffff9f
++#define RG_RFGC_SET_SFT 5
++#define RG_RFGC_SET_HI 6
++#define RG_RFGC_SET_SZ 2
++#define RG_RFGC_OW_MSK 0x00000080
++#define RG_RFGC_OW_I_MSK 0xffffff7f
++#define RG_RFGC_OW_SFT 7
++#define RG_RFGC_OW_HI 7
++#define RG_RFGC_OW_SZ 1
++#define RG_WAIT_T_RXAGC_MSK 0x00003f00
++#define RG_WAIT_T_RXAGC_I_MSK 0xffffc0ff
++#define RG_WAIT_T_RXAGC_SFT 8
++#define RG_WAIT_T_RXAGC_HI 13
++#define RG_WAIT_T_RXAGC_SZ 6
++#define RG_RXAGC_SET_MSK 0x00004000
++#define RG_RXAGC_SET_I_MSK 0xffffbfff
++#define RG_RXAGC_SET_SFT 14
++#define RG_RXAGC_SET_HI 14
++#define RG_RXAGC_SET_SZ 1
++#define RG_RXAGC_OW_MSK 0x00008000
++#define RG_RXAGC_OW_I_MSK 0xffff7fff
++#define RG_RXAGC_OW_SFT 15
++#define RG_RXAGC_OW_HI 15
++#define RG_RXAGC_OW_SZ 1
++#define RG_WAIT_T_FINAL_MSK 0x003f0000
++#define RG_WAIT_T_FINAL_I_MSK 0xffc0ffff
++#define RG_WAIT_T_FINAL_SFT 16
++#define RG_WAIT_T_FINAL_HI 21
++#define RG_WAIT_T_FINAL_SZ 6
++#define RG_WAIT_T_MSK 0x3f000000
++#define RG_WAIT_T_I_MSK 0xc0ffffff
++#define RG_WAIT_T_SFT 24
++#define RG_WAIT_T_HI 29
++#define RG_WAIT_T_SZ 6
++#define RG_ULG_PGA_SAT_PGA_GAIN_MSK 0x0000000f
++#define RG_ULG_PGA_SAT_PGA_GAIN_I_MSK 0xfffffff0
++#define RG_ULG_PGA_SAT_PGA_GAIN_SFT 0
++#define RG_ULG_PGA_SAT_PGA_GAIN_HI 3
++#define RG_ULG_PGA_SAT_PGA_GAIN_SZ 4
++#define RG_LG_PGA_UND_PGA_GAIN_MSK 0x000000f0
++#define RG_LG_PGA_UND_PGA_GAIN_I_MSK 0xffffff0f
++#define RG_LG_PGA_UND_PGA_GAIN_SFT 4
++#define RG_LG_PGA_UND_PGA_GAIN_HI 7
++#define RG_LG_PGA_UND_PGA_GAIN_SZ 4
++#define RG_LG_PGA_SAT_PGA_GAIN_MSK 0x00000f00
++#define RG_LG_PGA_SAT_PGA_GAIN_I_MSK 0xfffff0ff
++#define RG_LG_PGA_SAT_PGA_GAIN_SFT 8
++#define RG_LG_PGA_SAT_PGA_GAIN_HI 11
++#define RG_LG_PGA_SAT_PGA_GAIN_SZ 4
++#define RG_LG_RF_SAT_PGA_GAIN_MSK 0x0000f000
++#define RG_LG_RF_SAT_PGA_GAIN_I_MSK 0xffff0fff
++#define RG_LG_RF_SAT_PGA_GAIN_SFT 12
++#define RG_LG_RF_SAT_PGA_GAIN_HI 15
++#define RG_LG_RF_SAT_PGA_GAIN_SZ 4
++#define RG_MG_RF_SAT_PGANOREF_PGA_GAIN_MSK 0x000f0000
++#define RG_MG_RF_SAT_PGANOREF_PGA_GAIN_I_MSK 0xfff0ffff
++#define RG_MG_RF_SAT_PGANOREF_PGA_GAIN_SFT 16
++#define RG_MG_RF_SAT_PGANOREF_PGA_GAIN_HI 19
++#define RG_MG_RF_SAT_PGANOREF_PGA_GAIN_SZ 4
++#define RG_HG_PGA_SAT2_PGA_GAIN_MSK 0x00f00000
++#define RG_HG_PGA_SAT2_PGA_GAIN_I_MSK 0xff0fffff
++#define RG_HG_PGA_SAT2_PGA_GAIN_SFT 20
++#define RG_HG_PGA_SAT2_PGA_GAIN_HI 23
++#define RG_HG_PGA_SAT2_PGA_GAIN_SZ 4
++#define RG_HG_PGA_SAT1_PGA_GAIN_MSK 0x0f000000
++#define RG_HG_PGA_SAT1_PGA_GAIN_I_MSK 0xf0ffffff
++#define RG_HG_PGA_SAT1_PGA_GAIN_SFT 24
++#define RG_HG_PGA_SAT1_PGA_GAIN_HI 27
++#define RG_HG_PGA_SAT1_PGA_GAIN_SZ 4
++#define RG_HG_RF_SAT_PGA_GAIN_MSK 0xf0000000
++#define RG_HG_RF_SAT_PGA_GAIN_I_MSK 0x0fffffff
++#define RG_HG_RF_SAT_PGA_GAIN_SFT 28
++#define RG_HG_RF_SAT_PGA_GAIN_HI 31
++#define RG_HG_RF_SAT_PGA_GAIN_SZ 4
++#define RG_MG_PGA_JB_TH_MSK 0x0000000f
++#define RG_MG_PGA_JB_TH_I_MSK 0xfffffff0
++#define RG_MG_PGA_JB_TH_SFT 0
++#define RG_MG_PGA_JB_TH_HI 3
++#define RG_MG_PGA_JB_TH_SZ 4
++#define RG_MA_PGA_LOW_TH_CNT_LMT_MSK 0x001f0000
++#define RG_MA_PGA_LOW_TH_CNT_LMT_I_MSK 0xffe0ffff
++#define RG_MA_PGA_LOW_TH_CNT_LMT_SFT 16
++#define RG_MA_PGA_LOW_TH_CNT_LMT_HI 20
++#define RG_MA_PGA_LOW_TH_CNT_LMT_SZ 5
++#define RG_WR_RFGC_INIT_SET_MSK 0x00600000
++#define RG_WR_RFGC_INIT_SET_I_MSK 0xff9fffff
++#define RG_WR_RFGC_INIT_SET_SFT 21
++#define RG_WR_RFGC_INIT_SET_HI 22
++#define RG_WR_RFGC_INIT_SET_SZ 2
++#define RG_WR_RFGC_INIT_EN_MSK 0x00800000
++#define RG_WR_RFGC_INIT_EN_I_MSK 0xff7fffff
++#define RG_WR_RFGC_INIT_EN_SFT 23
++#define RG_WR_RFGC_INIT_EN_HI 23
++#define RG_WR_RFGC_INIT_EN_SZ 1
++#define RG_MA_PGA_HIGH_TH_CNT_LMT_MSK 0x1f000000
++#define RG_MA_PGA_HIGH_TH_CNT_LMT_I_MSK 0xe0ffffff
++#define RG_MA_PGA_HIGH_TH_CNT_LMT_SFT 24
++#define RG_MA_PGA_HIGH_TH_CNT_LMT_HI 28
++#define RG_MA_PGA_HIGH_TH_CNT_LMT_SZ 5
++#define RG_AGC_THRESHOLD_MSK 0x00003fff
++#define RG_AGC_THRESHOLD_I_MSK 0xffffc000
++#define RG_AGC_THRESHOLD_SFT 0
++#define RG_AGC_THRESHOLD_HI 13
++#define RG_AGC_THRESHOLD_SZ 14
++#define RG_ACI_POINT_CNT_LMT_11B_MSK 0x007f0000
++#define RG_ACI_POINT_CNT_LMT_11B_I_MSK 0xff80ffff
++#define RG_ACI_POINT_CNT_LMT_11B_SFT 16
++#define RG_ACI_POINT_CNT_LMT_11B_HI 22
++#define RG_ACI_POINT_CNT_LMT_11B_SZ 7
++#define RG_ACI_DAGC_LEAKY_FACTOR_11B_MSK 0x03000000
++#define RG_ACI_DAGC_LEAKY_FACTOR_11B_I_MSK 0xfcffffff
++#define RG_ACI_DAGC_LEAKY_FACTOR_11B_SFT 24
++#define RG_ACI_DAGC_LEAKY_FACTOR_11B_HI 25
++#define RG_ACI_DAGC_LEAKY_FACTOR_11B_SZ 2
++#define RG_WR_ACI_GAIN_INI_SEL_11B_MSK 0x000000ff
++#define RG_WR_ACI_GAIN_INI_SEL_11B_I_MSK 0xffffff00
++#define RG_WR_ACI_GAIN_INI_SEL_11B_SFT 0
++#define RG_WR_ACI_GAIN_INI_SEL_11B_HI 7
++#define RG_WR_ACI_GAIN_INI_SEL_11B_SZ 8
++#define RG_WR_ACI_GAIN_SEL_11B_MSK 0x0000ff00
++#define RG_WR_ACI_GAIN_SEL_11B_I_MSK 0xffff00ff
++#define RG_WR_ACI_GAIN_SEL_11B_SFT 8
++#define RG_WR_ACI_GAIN_SEL_11B_HI 15
++#define RG_WR_ACI_GAIN_SEL_11B_SZ 8
++#define RG_ACI_DAGC_SET_VALUE_11B_MSK 0x007f0000
++#define RG_ACI_DAGC_SET_VALUE_11B_I_MSK 0xff80ffff
++#define RG_ACI_DAGC_SET_VALUE_11B_SFT 16
++#define RG_ACI_DAGC_SET_VALUE_11B_HI 22
++#define RG_ACI_DAGC_SET_VALUE_11B_SZ 7
++#define RG_WR_ACI_GAIN_OW_11B_MSK 0x80000000
++#define RG_WR_ACI_GAIN_OW_11B_I_MSK 0x7fffffff
++#define RG_WR_ACI_GAIN_OW_11B_SFT 31
++#define RG_WR_ACI_GAIN_OW_11B_HI 31
++#define RG_WR_ACI_GAIN_OW_11B_SZ 1
++#define RG_ACI_POINT_CNT_LMT_11GN_MSK 0x000000ff
++#define RG_ACI_POINT_CNT_LMT_11GN_I_MSK 0xffffff00
++#define RG_ACI_POINT_CNT_LMT_11GN_SFT 0
++#define RG_ACI_POINT_CNT_LMT_11GN_HI 7
++#define RG_ACI_POINT_CNT_LMT_11GN_SZ 8
++#define RG_ACI_DAGC_LEAKY_FACTOR_11GN_MSK 0x00000300
++#define RG_ACI_DAGC_LEAKY_FACTOR_11GN_I_MSK 0xfffffcff
++#define RG_ACI_DAGC_LEAKY_FACTOR_11GN_SFT 8
++#define RG_ACI_DAGC_LEAKY_FACTOR_11GN_HI 9
++#define RG_ACI_DAGC_LEAKY_FACTOR_11GN_SZ 2
++#define RG_ACI_DAGC_DONE_CNT_LMT_11GN_MSK 0xff000000
++#define RG_ACI_DAGC_DONE_CNT_LMT_11GN_I_MSK 0x00ffffff
++#define RG_ACI_DAGC_DONE_CNT_LMT_11GN_SFT 24
++#define RG_ACI_DAGC_DONE_CNT_LMT_11GN_HI 31
++#define RG_ACI_DAGC_DONE_CNT_LMT_11GN_SZ 8
++#define RG_ACI_DAGC_SET_VALUE_11GN_MSK 0x0000007f
++#define RG_ACI_DAGC_SET_VALUE_11GN_I_MSK 0xffffff80
++#define RG_ACI_DAGC_SET_VALUE_11GN_SFT 0
++#define RG_ACI_DAGC_SET_VALUE_11GN_HI 6
++#define RG_ACI_DAGC_SET_VALUE_11GN_SZ 7
++#define RG_ACI_GAIN_INI_VAL_11GN_MSK 0x0000ff00
++#define RG_ACI_GAIN_INI_VAL_11GN_I_MSK 0xffff00ff
++#define RG_ACI_GAIN_INI_VAL_11GN_SFT 8
++#define RG_ACI_GAIN_INI_VAL_11GN_HI 15
++#define RG_ACI_GAIN_INI_VAL_11GN_SZ 8
++#define RG_ACI_GAIN_OW_VAL_11GN_MSK 0x00ff0000
++#define RG_ACI_GAIN_OW_VAL_11GN_I_MSK 0xff00ffff
++#define RG_ACI_GAIN_OW_VAL_11GN_SFT 16
++#define RG_ACI_GAIN_OW_VAL_11GN_HI 23
++#define RG_ACI_GAIN_OW_VAL_11GN_SZ 8
++#define RG_ACI_GAIN_OW_11GN_MSK 0x80000000
++#define RG_ACI_GAIN_OW_11GN_I_MSK 0x7fffffff
++#define RG_ACI_GAIN_OW_11GN_SFT 31
++#define RG_ACI_GAIN_OW_11GN_HI 31
++#define RG_ACI_GAIN_OW_11GN_SZ 1
++#define RO_CCA_PWR_MA_11GN_MSK 0x0000007f
++#define RO_CCA_PWR_MA_11GN_I_MSK 0xffffff80
++#define RO_CCA_PWR_MA_11GN_SFT 0
++#define RO_CCA_PWR_MA_11GN_HI 6
++#define RO_CCA_PWR_MA_11GN_SZ 7
++#define RO_ED_STATE_MSK 0x00008000
++#define RO_ED_STATE_I_MSK 0xffff7fff
++#define RO_ED_STATE_SFT 15
++#define RO_ED_STATE_HI 15
++#define RO_ED_STATE_SZ 1
++#define RO_CCA_PWR_MA_11B_MSK 0x007f0000
++#define RO_CCA_PWR_MA_11B_I_MSK 0xff80ffff
++#define RO_CCA_PWR_MA_11B_SFT 16
++#define RO_CCA_PWR_MA_11B_HI 22
++#define RO_CCA_PWR_MA_11B_SZ 7
++#define RO_PGA_PWR_FF1_MSK 0x00003fff
++#define RO_PGA_PWR_FF1_I_MSK 0xffffc000
++#define RO_PGA_PWR_FF1_SFT 0
++#define RO_PGA_PWR_FF1_HI 13
++#define RO_PGA_PWR_FF1_SZ 14
++#define RO_RF_PWR_FF1_MSK 0x000f0000
++#define RO_RF_PWR_FF1_I_MSK 0xfff0ffff
++#define RO_RF_PWR_FF1_SFT 16
++#define RO_RF_PWR_FF1_HI 19
++#define RO_RF_PWR_FF1_SZ 4
++#define RO_PGAGC_FF1_MSK 0x0f000000
++#define RO_PGAGC_FF1_I_MSK 0xf0ffffff
++#define RO_PGAGC_FF1_SFT 24
++#define RO_PGAGC_FF1_HI 27
++#define RO_PGAGC_FF1_SZ 4
++#define RO_RFGC_FF1_MSK 0x30000000
++#define RO_RFGC_FF1_I_MSK 0xcfffffff
++#define RO_RFGC_FF1_SFT 28
++#define RO_RFGC_FF1_HI 29
++#define RO_RFGC_FF1_SZ 2
++#define RO_PGA_PWR_FF2_MSK 0x00003fff
++#define RO_PGA_PWR_FF2_I_MSK 0xffffc000
++#define RO_PGA_PWR_FF2_SFT 0
++#define RO_PGA_PWR_FF2_HI 13
++#define RO_PGA_PWR_FF2_SZ 14
++#define RO_RF_PWR_FF2_MSK 0x000f0000
++#define RO_RF_PWR_FF2_I_MSK 0xfff0ffff
++#define RO_RF_PWR_FF2_SFT 16
++#define RO_RF_PWR_FF2_HI 19
++#define RO_RF_PWR_FF2_SZ 4
++#define RO_PGAGC_FF2_MSK 0x0f000000
++#define RO_PGAGC_FF2_I_MSK 0xf0ffffff
++#define RO_PGAGC_FF2_SFT 24
++#define RO_PGAGC_FF2_HI 27
++#define RO_PGAGC_FF2_SZ 4
++#define RO_RFGC_FF2_MSK 0x30000000
++#define RO_RFGC_FF2_I_MSK 0xcfffffff
++#define RO_RFGC_FF2_SFT 28
++#define RO_RFGC_FF2_HI 29
++#define RO_RFGC_FF2_SZ 2
++#define RO_PGA_PWR_FF3_MSK 0x00003fff
++#define RO_PGA_PWR_FF3_I_MSK 0xffffc000
++#define RO_PGA_PWR_FF3_SFT 0
++#define RO_PGA_PWR_FF3_HI 13
++#define RO_PGA_PWR_FF3_SZ 14
++#define RO_RF_PWR_FF3_MSK 0x000f0000
++#define RO_RF_PWR_FF3_I_MSK 0xfff0ffff
++#define RO_RF_PWR_FF3_SFT 16
++#define RO_RF_PWR_FF3_HI 19
++#define RO_RF_PWR_FF3_SZ 4
++#define RO_PGAGC_FF3_MSK 0x0f000000
++#define RO_PGAGC_FF3_I_MSK 0xf0ffffff
++#define RO_PGAGC_FF3_SFT 24
++#define RO_PGAGC_FF3_HI 27
++#define RO_PGAGC_FF3_SZ 4
++#define RO_RFGC_FF3_MSK 0x30000000
++#define RO_RFGC_FF3_I_MSK 0xcfffffff
++#define RO_RFGC_FF3_SFT 28
++#define RO_RFGC_FF3_HI 29
++#define RO_RFGC_FF3_SZ 2
++#define RG_TX_DES_RATE_MSK 0x0000001f
++#define RG_TX_DES_RATE_I_MSK 0xffffffe0
++#define RG_TX_DES_RATE_SFT 0
++#define RG_TX_DES_RATE_HI 4
++#define RG_TX_DES_RATE_SZ 5
++#define RG_TX_DES_MODE_MSK 0x00001f00
++#define RG_TX_DES_MODE_I_MSK 0xffffe0ff
++#define RG_TX_DES_MODE_SFT 8
++#define RG_TX_DES_MODE_HI 12
++#define RG_TX_DES_MODE_SZ 5
++#define RG_TX_DES_LEN_LO_MSK 0x001f0000
++#define RG_TX_DES_LEN_LO_I_MSK 0xffe0ffff
++#define RG_TX_DES_LEN_LO_SFT 16
++#define RG_TX_DES_LEN_LO_HI 20
++#define RG_TX_DES_LEN_LO_SZ 5
++#define RG_TX_DES_LEN_UP_MSK 0x1f000000
++#define RG_TX_DES_LEN_UP_I_MSK 0xe0ffffff
++#define RG_TX_DES_LEN_UP_SFT 24
++#define RG_TX_DES_LEN_UP_HI 28
++#define RG_TX_DES_LEN_UP_SZ 5
++#define RG_TX_DES_SRVC_UP_MSK 0x0000001f
++#define RG_TX_DES_SRVC_UP_I_MSK 0xffffffe0
++#define RG_TX_DES_SRVC_UP_SFT 0
++#define RG_TX_DES_SRVC_UP_HI 4
++#define RG_TX_DES_SRVC_UP_SZ 5
++#define RG_TX_DES_L_LEN_LO_MSK 0x00001f00
++#define RG_TX_DES_L_LEN_LO_I_MSK 0xffffe0ff
++#define RG_TX_DES_L_LEN_LO_SFT 8
++#define RG_TX_DES_L_LEN_LO_HI 12
++#define RG_TX_DES_L_LEN_LO_SZ 5
++#define RG_TX_DES_L_LEN_UP_MSK 0x001f0000
++#define RG_TX_DES_L_LEN_UP_I_MSK 0xffe0ffff
++#define RG_TX_DES_L_LEN_UP_SFT 16
++#define RG_TX_DES_L_LEN_UP_HI 20
++#define RG_TX_DES_L_LEN_UP_SZ 5
++#define RG_TX_DES_TYPE_MSK 0x1f000000
++#define RG_TX_DES_TYPE_I_MSK 0xe0ffffff
++#define RG_TX_DES_TYPE_SFT 24
++#define RG_TX_DES_TYPE_HI 28
++#define RG_TX_DES_TYPE_SZ 5
++#define RG_TX_DES_L_LEN_UP_COMB_MSK 0x00000001
++#define RG_TX_DES_L_LEN_UP_COMB_I_MSK 0xfffffffe
++#define RG_TX_DES_L_LEN_UP_COMB_SFT 0
++#define RG_TX_DES_L_LEN_UP_COMB_HI 0
++#define RG_TX_DES_L_LEN_UP_COMB_SZ 1
++#define RG_TX_DES_TYPE_COMB_MSK 0x00000010
++#define RG_TX_DES_TYPE_COMB_I_MSK 0xffffffef
++#define RG_TX_DES_TYPE_COMB_SFT 4
++#define RG_TX_DES_TYPE_COMB_HI 4
++#define RG_TX_DES_TYPE_COMB_SZ 1
++#define RG_TX_DES_RATE_COMB_MSK 0x00000100
++#define RG_TX_DES_RATE_COMB_I_MSK 0xfffffeff
++#define RG_TX_DES_RATE_COMB_SFT 8
++#define RG_TX_DES_RATE_COMB_HI 8
++#define RG_TX_DES_RATE_COMB_SZ 1
++#define RG_TX_DES_MODE_COMB_MSK 0x00001000
++#define RG_TX_DES_MODE_COMB_I_MSK 0xffffefff
++#define RG_TX_DES_MODE_COMB_SFT 12
++#define RG_TX_DES_MODE_COMB_HI 12
++#define RG_TX_DES_MODE_COMB_SZ 1
++#define RG_TX_DES_PWRLVL_MSK 0x001f0000
++#define RG_TX_DES_PWRLVL_I_MSK 0xffe0ffff
++#define RG_TX_DES_PWRLVL_SFT 16
++#define RG_TX_DES_PWRLVL_HI 20
++#define RG_TX_DES_PWRLVL_SZ 5
++#define RG_TX_DES_SRVC_LO_MSK 0x1f000000
++#define RG_TX_DES_SRVC_LO_I_MSK 0xe0ffffff
++#define RG_TX_DES_SRVC_LO_SFT 24
++#define RG_TX_DES_SRVC_LO_HI 28
++#define RG_TX_DES_SRVC_LO_SZ 5
++#define RG_RX_DES_RATE_MSK 0x0000003f
++#define RG_RX_DES_RATE_I_MSK 0xffffffc0
++#define RG_RX_DES_RATE_SFT 0
++#define RG_RX_DES_RATE_HI 5
++#define RG_RX_DES_RATE_SZ 6
++#define RG_RX_DES_MODE_MSK 0x00003f00
++#define RG_RX_DES_MODE_I_MSK 0xffffc0ff
++#define RG_RX_DES_MODE_SFT 8
++#define RG_RX_DES_MODE_HI 13
++#define RG_RX_DES_MODE_SZ 6
++#define RG_RX_DES_LEN_LO_MSK 0x003f0000
++#define RG_RX_DES_LEN_LO_I_MSK 0xffc0ffff
++#define RG_RX_DES_LEN_LO_SFT 16
++#define RG_RX_DES_LEN_LO_HI 21
++#define RG_RX_DES_LEN_LO_SZ 6
++#define RG_RX_DES_LEN_UP_MSK 0x3f000000
++#define RG_RX_DES_LEN_UP_I_MSK 0xc0ffffff
++#define RG_RX_DES_LEN_UP_SFT 24
++#define RG_RX_DES_LEN_UP_HI 29
++#define RG_RX_DES_LEN_UP_SZ 6
++#define RG_RX_DES_SRVC_UP_MSK 0x0000003f
++#define RG_RX_DES_SRVC_UP_I_MSK 0xffffffc0
++#define RG_RX_DES_SRVC_UP_SFT 0
++#define RG_RX_DES_SRVC_UP_HI 5
++#define RG_RX_DES_SRVC_UP_SZ 6
++#define RG_RX_DES_L_LEN_LO_MSK 0x00003f00
++#define RG_RX_DES_L_LEN_LO_I_MSK 0xffffc0ff
++#define RG_RX_DES_L_LEN_LO_SFT 8
++#define RG_RX_DES_L_LEN_LO_HI 13
++#define RG_RX_DES_L_LEN_LO_SZ 6
++#define RG_RX_DES_L_LEN_UP_MSK 0x003f0000
++#define RG_RX_DES_L_LEN_UP_I_MSK 0xffc0ffff
++#define RG_RX_DES_L_LEN_UP_SFT 16
++#define RG_RX_DES_L_LEN_UP_HI 21
++#define RG_RX_DES_L_LEN_UP_SZ 6
++#define RG_RX_DES_TYPE_MSK 0x3f000000
++#define RG_RX_DES_TYPE_I_MSK 0xc0ffffff
++#define RG_RX_DES_TYPE_SFT 24
++#define RG_RX_DES_TYPE_HI 29
++#define RG_RX_DES_TYPE_SZ 6
++#define RG_RX_DES_L_LEN_UP_COMB_MSK 0x00000001
++#define RG_RX_DES_L_LEN_UP_COMB_I_MSK 0xfffffffe
++#define RG_RX_DES_L_LEN_UP_COMB_SFT 0
++#define RG_RX_DES_L_LEN_UP_COMB_HI 0
++#define RG_RX_DES_L_LEN_UP_COMB_SZ 1
++#define RG_RX_DES_TYPE_COMB_MSK 0x00000010
++#define RG_RX_DES_TYPE_COMB_I_MSK 0xffffffef
++#define RG_RX_DES_TYPE_COMB_SFT 4
++#define RG_RX_DES_TYPE_COMB_HI 4
++#define RG_RX_DES_TYPE_COMB_SZ 1
++#define RG_RX_DES_RATE_COMB_MSK 0x00000100
++#define RG_RX_DES_RATE_COMB_I_MSK 0xfffffeff
++#define RG_RX_DES_RATE_COMB_SFT 8
++#define RG_RX_DES_RATE_COMB_HI 8
++#define RG_RX_DES_RATE_COMB_SZ 1
++#define RG_RX_DES_MODE_COMB_MSK 0x00001000
++#define RG_RX_DES_MODE_COMB_I_MSK 0xffffefff
++#define RG_RX_DES_MODE_COMB_SFT 12
++#define RG_RX_DES_MODE_COMB_HI 12
++#define RG_RX_DES_MODE_COMB_SZ 1
++#define RG_RX_DES_SNR_MSK 0x000f0000
++#define RG_RX_DES_SNR_I_MSK 0xfff0ffff
++#define RG_RX_DES_SNR_SFT 16
++#define RG_RX_DES_SNR_HI 19
++#define RG_RX_DES_SNR_SZ 4
++#define RG_RX_DES_RCPI_MSK 0x00f00000
++#define RG_RX_DES_RCPI_I_MSK 0xff0fffff
++#define RG_RX_DES_RCPI_SFT 20
++#define RG_RX_DES_RCPI_HI 23
++#define RG_RX_DES_RCPI_SZ 4
++#define RG_RX_DES_SRVC_LO_MSK 0x3f000000
++#define RG_RX_DES_SRVC_LO_I_MSK 0xc0ffffff
++#define RG_RX_DES_SRVC_LO_SFT 24
++#define RG_RX_DES_SRVC_LO_HI 29
++#define RG_RX_DES_SRVC_LO_SZ 6
++#define RO_TX_DES_EXCP_RATE_CNT_MSK 0x000000ff
++#define RO_TX_DES_EXCP_RATE_CNT_I_MSK 0xffffff00
++#define RO_TX_DES_EXCP_RATE_CNT_SFT 0
++#define RO_TX_DES_EXCP_RATE_CNT_HI 7
++#define RO_TX_DES_EXCP_RATE_CNT_SZ 8
++#define RO_TX_DES_EXCP_CH_BW_CNT_MSK 0x0000ff00
++#define RO_TX_DES_EXCP_CH_BW_CNT_I_MSK 0xffff00ff
++#define RO_TX_DES_EXCP_CH_BW_CNT_SFT 8
++#define RO_TX_DES_EXCP_CH_BW_CNT_HI 15
++#define RO_TX_DES_EXCP_CH_BW_CNT_SZ 8
++#define RO_TX_DES_EXCP_MODE_CNT_MSK 0x00ff0000
++#define RO_TX_DES_EXCP_MODE_CNT_I_MSK 0xff00ffff
++#define RO_TX_DES_EXCP_MODE_CNT_SFT 16
++#define RO_TX_DES_EXCP_MODE_CNT_HI 23
++#define RO_TX_DES_EXCP_MODE_CNT_SZ 8
++#define RG_TX_DES_EXCP_RATE_DEFAULT_MSK 0x07000000
++#define RG_TX_DES_EXCP_RATE_DEFAULT_I_MSK 0xf8ffffff
++#define RG_TX_DES_EXCP_RATE_DEFAULT_SFT 24
++#define RG_TX_DES_EXCP_RATE_DEFAULT_HI 26
++#define RG_TX_DES_EXCP_RATE_DEFAULT_SZ 3
++#define RG_TX_DES_EXCP_MODE_DEFAULT_MSK 0x70000000
++#define RG_TX_DES_EXCP_MODE_DEFAULT_I_MSK 0x8fffffff
++#define RG_TX_DES_EXCP_MODE_DEFAULT_SFT 28
++#define RG_TX_DES_EXCP_MODE_DEFAULT_HI 30
++#define RG_TX_DES_EXCP_MODE_DEFAULT_SZ 3
++#define RG_TX_DES_EXCP_CLR_MSK 0x80000000
++#define RG_TX_DES_EXCP_CLR_I_MSK 0x7fffffff
++#define RG_TX_DES_EXCP_CLR_SFT 31
++#define RG_TX_DES_EXCP_CLR_HI 31
++#define RG_TX_DES_EXCP_CLR_SZ 1
++#define RG_TX_DES_ACK_WIDTH_MSK 0x00000001
++#define RG_TX_DES_ACK_WIDTH_I_MSK 0xfffffffe
++#define RG_TX_DES_ACK_WIDTH_SFT 0
++#define RG_TX_DES_ACK_WIDTH_HI 0
++#define RG_TX_DES_ACK_WIDTH_SZ 1
++#define RG_TX_DES_ACK_PRD_MSK 0x0000000e
++#define RG_TX_DES_ACK_PRD_I_MSK 0xfffffff1
++#define RG_TX_DES_ACK_PRD_SFT 1
++#define RG_TX_DES_ACK_PRD_HI 3
++#define RG_TX_DES_ACK_PRD_SZ 3
++#define RG_RX_DES_SNR_GN_MSK 0x003f0000
++#define RG_RX_DES_SNR_GN_I_MSK 0xffc0ffff
++#define RG_RX_DES_SNR_GN_SFT 16
++#define RG_RX_DES_SNR_GN_HI 21
++#define RG_RX_DES_SNR_GN_SZ 6
++#define RG_RX_DES_RCPI_GN_MSK 0x3f000000
++#define RG_RX_DES_RCPI_GN_I_MSK 0xc0ffffff
++#define RG_RX_DES_RCPI_GN_SFT 24
++#define RG_RX_DES_RCPI_GN_HI 29
++#define RG_RX_DES_RCPI_GN_SZ 6
++#define RG_TST_TBUS_SEL_MSK 0x0000000f
++#define RG_TST_TBUS_SEL_I_MSK 0xfffffff0
++#define RG_TST_TBUS_SEL_SFT 0
++#define RG_TST_TBUS_SEL_HI 3
++#define RG_TST_TBUS_SEL_SZ 4
++#define RG_RSSI_OFFSET_MSK 0x00ff0000
++#define RG_RSSI_OFFSET_I_MSK 0xff00ffff
++#define RG_RSSI_OFFSET_SFT 16
++#define RG_RSSI_OFFSET_HI 23
++#define RG_RSSI_OFFSET_SZ 8
++#define RG_RSSI_INV_MSK 0x01000000
++#define RG_RSSI_INV_I_MSK 0xfeffffff
++#define RG_RSSI_INV_SFT 24
++#define RG_RSSI_INV_HI 24
++#define RG_RSSI_INV_SZ 1
++#define RG_TST_ADC_ON_MSK 0x40000000
++#define RG_TST_ADC_ON_I_MSK 0xbfffffff
++#define RG_TST_ADC_ON_SFT 30
++#define RG_TST_ADC_ON_HI 30
++#define RG_TST_ADC_ON_SZ 1
++#define RG_TST_EXT_GAIN_MSK 0x80000000
++#define RG_TST_EXT_GAIN_I_MSK 0x7fffffff
++#define RG_TST_EXT_GAIN_SFT 31
++#define RG_TST_EXT_GAIN_HI 31
++#define RG_TST_EXT_GAIN_SZ 1
++#define RG_DAC_Q_SET_MSK 0x000003ff
++#define RG_DAC_Q_SET_I_MSK 0xfffffc00
++#define RG_DAC_Q_SET_SFT 0
++#define RG_DAC_Q_SET_HI 9
++#define RG_DAC_Q_SET_SZ 10
++#define RG_DAC_I_SET_MSK 0x003ff000
++#define RG_DAC_I_SET_I_MSK 0xffc00fff
++#define RG_DAC_I_SET_SFT 12
++#define RG_DAC_I_SET_HI 21
++#define RG_DAC_I_SET_SZ 10
++#define RG_DAC_EN_MAN_MSK 0x10000000
++#define RG_DAC_EN_MAN_I_MSK 0xefffffff
++#define RG_DAC_EN_MAN_SFT 28
++#define RG_DAC_EN_MAN_HI 28
++#define RG_DAC_EN_MAN_SZ 1
++#define RG_IQC_FFT_EN_MSK 0x20000000
++#define RG_IQC_FFT_EN_I_MSK 0xdfffffff
++#define RG_IQC_FFT_EN_SFT 29
++#define RG_IQC_FFT_EN_HI 29
++#define RG_IQC_FFT_EN_SZ 1
++#define RG_DAC_MAN_Q_EN_MSK 0x40000000
++#define RG_DAC_MAN_Q_EN_I_MSK 0xbfffffff
++#define RG_DAC_MAN_Q_EN_SFT 30
++#define RG_DAC_MAN_Q_EN_HI 30
++#define RG_DAC_MAN_Q_EN_SZ 1
++#define RG_DAC_MAN_I_EN_MSK 0x80000000
++#define RG_DAC_MAN_I_EN_I_MSK 0x7fffffff
++#define RG_DAC_MAN_I_EN_SFT 31
++#define RG_DAC_MAN_I_EN_HI 31
++#define RG_DAC_MAN_I_EN_SZ 1
++#define RO_MRX_EN_CNT_MSK 0x0000ffff
++#define RO_MRX_EN_CNT_I_MSK 0xffff0000
++#define RO_MRX_EN_CNT_SFT 0
++#define RO_MRX_EN_CNT_HI 15
++#define RO_MRX_EN_CNT_SZ 16
++#define RG_MRX_EN_CNT_RST_N_MSK 0x80000000
++#define RG_MRX_EN_CNT_RST_N_I_MSK 0x7fffffff
++#define RG_MRX_EN_CNT_RST_N_SFT 31
++#define RG_MRX_EN_CNT_RST_N_HI 31
++#define RG_MRX_EN_CNT_RST_N_SZ 1
++#define RG_PA_RISE_TIME_MSK 0x000000ff
++#define RG_PA_RISE_TIME_I_MSK 0xffffff00
++#define RG_PA_RISE_TIME_SFT 0
++#define RG_PA_RISE_TIME_HI 7
++#define RG_PA_RISE_TIME_SZ 8
++#define RG_RFTX_RISE_TIME_MSK 0x0000ff00
++#define RG_RFTX_RISE_TIME_I_MSK 0xffff00ff
++#define RG_RFTX_RISE_TIME_SFT 8
++#define RG_RFTX_RISE_TIME_HI 15
++#define RG_RFTX_RISE_TIME_SZ 8
++#define RG_DAC_RISE_TIME_MSK 0x00ff0000
++#define RG_DAC_RISE_TIME_I_MSK 0xff00ffff
++#define RG_DAC_RISE_TIME_SFT 16
++#define RG_DAC_RISE_TIME_HI 23
++#define RG_DAC_RISE_TIME_SZ 8
++#define RG_SW_RISE_TIME_MSK 0xff000000
++#define RG_SW_RISE_TIME_I_MSK 0x00ffffff
++#define RG_SW_RISE_TIME_SFT 24
++#define RG_SW_RISE_TIME_HI 31
++#define RG_SW_RISE_TIME_SZ 8
++#define RG_PA_FALL_TIME_MSK 0x000000ff
++#define RG_PA_FALL_TIME_I_MSK 0xffffff00
++#define RG_PA_FALL_TIME_SFT 0
++#define RG_PA_FALL_TIME_HI 7
++#define RG_PA_FALL_TIME_SZ 8
++#define RG_RFTX_FALL_TIME_MSK 0x0000ff00
++#define RG_RFTX_FALL_TIME_I_MSK 0xffff00ff
++#define RG_RFTX_FALL_TIME_SFT 8
++#define RG_RFTX_FALL_TIME_HI 15
++#define RG_RFTX_FALL_TIME_SZ 8
++#define RG_DAC_FALL_TIME_MSK 0x00ff0000
++#define RG_DAC_FALL_TIME_I_MSK 0xff00ffff
++#define RG_DAC_FALL_TIME_SFT 16
++#define RG_DAC_FALL_TIME_HI 23
++#define RG_DAC_FALL_TIME_SZ 8
++#define RG_SW_FALL_TIME_MSK 0xff000000
++#define RG_SW_FALL_TIME_I_MSK 0x00ffffff
++#define RG_SW_FALL_TIME_SFT 24
++#define RG_SW_FALL_TIME_HI 31
++#define RG_SW_FALL_TIME_SZ 8
++#define RG_ANT_SW_0_MSK 0x00000007
++#define RG_ANT_SW_0_I_MSK 0xfffffff8
++#define RG_ANT_SW_0_SFT 0
++#define RG_ANT_SW_0_HI 2
++#define RG_ANT_SW_0_SZ 3
++#define RG_ANT_SW_1_MSK 0x00000038
++#define RG_ANT_SW_1_I_MSK 0xffffffc7
++#define RG_ANT_SW_1_SFT 3
++#define RG_ANT_SW_1_HI 5
++#define RG_ANT_SW_1_SZ 3
++#define RG_MTX_LEN_LOWER_TH_0_MSK 0x00001fff
++#define RG_MTX_LEN_LOWER_TH_0_I_MSK 0xffffe000
++#define RG_MTX_LEN_LOWER_TH_0_SFT 0
++#define RG_MTX_LEN_LOWER_TH_0_HI 12
++#define RG_MTX_LEN_LOWER_TH_0_SZ 13
++#define RG_MTX_LEN_UPPER_TH_0_MSK 0x1fff0000
++#define RG_MTX_LEN_UPPER_TH_0_I_MSK 0xe000ffff
++#define RG_MTX_LEN_UPPER_TH_0_SFT 16
++#define RG_MTX_LEN_UPPER_TH_0_HI 28
++#define RG_MTX_LEN_UPPER_TH_0_SZ 13
++#define RG_MTX_LEN_CNT_EN_0_MSK 0x80000000
++#define RG_MTX_LEN_CNT_EN_0_I_MSK 0x7fffffff
++#define RG_MTX_LEN_CNT_EN_0_SFT 31
++#define RG_MTX_LEN_CNT_EN_0_HI 31
++#define RG_MTX_LEN_CNT_EN_0_SZ 1
++#define RG_MTX_LEN_LOWER_TH_1_MSK 0x00001fff
++#define RG_MTX_LEN_LOWER_TH_1_I_MSK 0xffffe000
++#define RG_MTX_LEN_LOWER_TH_1_SFT 0
++#define RG_MTX_LEN_LOWER_TH_1_HI 12
++#define RG_MTX_LEN_LOWER_TH_1_SZ 13
++#define RG_MTX_LEN_UPPER_TH_1_MSK 0x1fff0000
++#define RG_MTX_LEN_UPPER_TH_1_I_MSK 0xe000ffff
++#define RG_MTX_LEN_UPPER_TH_1_SFT 16
++#define RG_MTX_LEN_UPPER_TH_1_HI 28
++#define RG_MTX_LEN_UPPER_TH_1_SZ 13
++#define RG_MTX_LEN_CNT_EN_1_MSK 0x80000000
++#define RG_MTX_LEN_CNT_EN_1_I_MSK 0x7fffffff
++#define RG_MTX_LEN_CNT_EN_1_SFT 31
++#define RG_MTX_LEN_CNT_EN_1_HI 31
++#define RG_MTX_LEN_CNT_EN_1_SZ 1
++#define RG_MRX_LEN_LOWER_TH_0_MSK 0x00001fff
++#define RG_MRX_LEN_LOWER_TH_0_I_MSK 0xffffe000
++#define RG_MRX_LEN_LOWER_TH_0_SFT 0
++#define RG_MRX_LEN_LOWER_TH_0_HI 12
++#define RG_MRX_LEN_LOWER_TH_0_SZ 13
++#define RG_MRX_LEN_UPPER_TH_0_MSK 0x1fff0000
++#define RG_MRX_LEN_UPPER_TH_0_I_MSK 0xe000ffff
++#define RG_MRX_LEN_UPPER_TH_0_SFT 16
++#define RG_MRX_LEN_UPPER_TH_0_HI 28
++#define RG_MRX_LEN_UPPER_TH_0_SZ 13
++#define RG_MRX_LEN_CNT_EN_0_MSK 0x80000000
++#define RG_MRX_LEN_CNT_EN_0_I_MSK 0x7fffffff
++#define RG_MRX_LEN_CNT_EN_0_SFT 31
++#define RG_MRX_LEN_CNT_EN_0_HI 31
++#define RG_MRX_LEN_CNT_EN_0_SZ 1
++#define RG_MRX_LEN_LOWER_TH_1_MSK 0x00001fff
++#define RG_MRX_LEN_LOWER_TH_1_I_MSK 0xffffe000
++#define RG_MRX_LEN_LOWER_TH_1_SFT 0
++#define RG_MRX_LEN_LOWER_TH_1_HI 12
++#define RG_MRX_LEN_LOWER_TH_1_SZ 13
++#define RG_MRX_LEN_UPPER_TH_1_MSK 0x1fff0000
++#define RG_MRX_LEN_UPPER_TH_1_I_MSK 0xe000ffff
++#define RG_MRX_LEN_UPPER_TH_1_SFT 16
++#define RG_MRX_LEN_UPPER_TH_1_HI 28
++#define RG_MRX_LEN_UPPER_TH_1_SZ 13
++#define RG_MRX_LEN_CNT_EN_1_MSK 0x80000000
++#define RG_MRX_LEN_CNT_EN_1_I_MSK 0x7fffffff
++#define RG_MRX_LEN_CNT_EN_1_SFT 31
++#define RG_MRX_LEN_CNT_EN_1_HI 31
++#define RG_MRX_LEN_CNT_EN_1_SZ 1
++#define RO_MTX_LEN_CNT_1_MSK 0x0000ffff
++#define RO_MTX_LEN_CNT_1_I_MSK 0xffff0000
++#define RO_MTX_LEN_CNT_1_SFT 0
++#define RO_MTX_LEN_CNT_1_HI 15
++#define RO_MTX_LEN_CNT_1_SZ 16
++#define RO_MTX_LEN_CNT_0_MSK 0xffff0000
++#define RO_MTX_LEN_CNT_0_I_MSK 0x0000ffff
++#define RO_MTX_LEN_CNT_0_SFT 16
++#define RO_MTX_LEN_CNT_0_HI 31
++#define RO_MTX_LEN_CNT_0_SZ 16
++#define RO_MRX_LEN_CNT_1_MSK 0x0000ffff
++#define RO_MRX_LEN_CNT_1_I_MSK 0xffff0000
++#define RO_MRX_LEN_CNT_1_SFT 0
++#define RO_MRX_LEN_CNT_1_HI 15
++#define RO_MRX_LEN_CNT_1_SZ 16
++#define RO_MRX_LEN_CNT_0_MSK 0xffff0000
++#define RO_MRX_LEN_CNT_0_I_MSK 0x0000ffff
++#define RO_MRX_LEN_CNT_0_SFT 16
++#define RO_MRX_LEN_CNT_0_HI 31
++#define RO_MRX_LEN_CNT_0_SZ 16
++#define RG_MODE_REG_IN_16_MSK 0x0000ffff
++#define RG_MODE_REG_IN_16_I_MSK 0xffff0000
++#define RG_MODE_REG_IN_16_SFT 0
++#define RG_MODE_REG_IN_16_HI 15
++#define RG_MODE_REG_IN_16_SZ 16
++#define RG_PARALLEL_DR_16_MSK 0x00100000
++#define RG_PARALLEL_DR_16_I_MSK 0xffefffff
++#define RG_PARALLEL_DR_16_SFT 20
++#define RG_PARALLEL_DR_16_HI 20
++#define RG_PARALLEL_DR_16_SZ 1
++#define RG_MBRUN_16_MSK 0x01000000
++#define RG_MBRUN_16_I_MSK 0xfeffffff
++#define RG_MBRUN_16_SFT 24
++#define RG_MBRUN_16_HI 24
++#define RG_MBRUN_16_SZ 1
++#define RG_SHIFT_DR_16_MSK 0x10000000
++#define RG_SHIFT_DR_16_I_MSK 0xefffffff
++#define RG_SHIFT_DR_16_SFT 28
++#define RG_SHIFT_DR_16_HI 28
++#define RG_SHIFT_DR_16_SZ 1
++#define RG_MODE_REG_SI_16_MSK 0x20000000
++#define RG_MODE_REG_SI_16_I_MSK 0xdfffffff
++#define RG_MODE_REG_SI_16_SFT 29
++#define RG_MODE_REG_SI_16_HI 29
++#define RG_MODE_REG_SI_16_SZ 1
++#define RG_SIMULATION_MODE_16_MSK 0x40000000
++#define RG_SIMULATION_MODE_16_I_MSK 0xbfffffff
++#define RG_SIMULATION_MODE_16_SFT 30
++#define RG_SIMULATION_MODE_16_HI 30
++#define RG_SIMULATION_MODE_16_SZ 1
++#define RG_DBIST_MODE_16_MSK 0x80000000
++#define RG_DBIST_MODE_16_I_MSK 0x7fffffff
++#define RG_DBIST_MODE_16_SFT 31
++#define RG_DBIST_MODE_16_HI 31
++#define RG_DBIST_MODE_16_SZ 1
++#define RO_MODE_REG_OUT_16_MSK 0x0000ffff
++#define RO_MODE_REG_OUT_16_I_MSK 0xffff0000
++#define RO_MODE_REG_OUT_16_SFT 0
++#define RO_MODE_REG_OUT_16_HI 15
++#define RO_MODE_REG_OUT_16_SZ 16
++#define RO_MODE_REG_SO_16_MSK 0x01000000
++#define RO_MODE_REG_SO_16_I_MSK 0xfeffffff
++#define RO_MODE_REG_SO_16_SFT 24
++#define RO_MODE_REG_SO_16_HI 24
++#define RO_MODE_REG_SO_16_SZ 1
++#define RO_MONITOR_BUS_16_MSK 0x0007ffff
++#define RO_MONITOR_BUS_16_I_MSK 0xfff80000
++#define RO_MONITOR_BUS_16_SFT 0
++#define RO_MONITOR_BUS_16_HI 18
++#define RO_MONITOR_BUS_16_SZ 19
++#define RG_MRX_TYPE_1_MSK 0x000000ff
++#define RG_MRX_TYPE_1_I_MSK 0xffffff00
++#define RG_MRX_TYPE_1_SFT 0
++#define RG_MRX_TYPE_1_HI 7
++#define RG_MRX_TYPE_1_SZ 8
++#define RG_MRX_TYPE_0_MSK 0x0000ff00
++#define RG_MRX_TYPE_0_I_MSK 0xffff00ff
++#define RG_MRX_TYPE_0_SFT 8
++#define RG_MRX_TYPE_0_HI 15
++#define RG_MRX_TYPE_0_SZ 8
++#define RG_MTX_TYPE_1_MSK 0x00ff0000
++#define RG_MTX_TYPE_1_I_MSK 0xff00ffff
++#define RG_MTX_TYPE_1_SFT 16
++#define RG_MTX_TYPE_1_HI 23
++#define RG_MTX_TYPE_1_SZ 8
++#define RG_MTX_TYPE_0_MSK 0xff000000
++#define RG_MTX_TYPE_0_I_MSK 0x00ffffff
++#define RG_MTX_TYPE_0_SFT 24
++#define RG_MTX_TYPE_0_HI 31
++#define RG_MTX_TYPE_0_SZ 8
++#define RO_MTX_TYPE_CNT_1_MSK 0x0000ffff
++#define RO_MTX_TYPE_CNT_1_I_MSK 0xffff0000
++#define RO_MTX_TYPE_CNT_1_SFT 0
++#define RO_MTX_TYPE_CNT_1_HI 15
++#define RO_MTX_TYPE_CNT_1_SZ 16
++#define RO_MTX_TYPE_CNT_0_MSK 0xffff0000
++#define RO_MTX_TYPE_CNT_0_I_MSK 0x0000ffff
++#define RO_MTX_TYPE_CNT_0_SFT 16
++#define RO_MTX_TYPE_CNT_0_HI 31
++#define RO_MTX_TYPE_CNT_0_SZ 16
++#define RO_MRX_TYPE_CNT_1_MSK 0x0000ffff
++#define RO_MRX_TYPE_CNT_1_I_MSK 0xffff0000
++#define RO_MRX_TYPE_CNT_1_SFT 0
++#define RO_MRX_TYPE_CNT_1_HI 15
++#define RO_MRX_TYPE_CNT_1_SZ 16
++#define RO_MRX_TYPE_CNT_0_MSK 0xffff0000
++#define RO_MRX_TYPE_CNT_0_I_MSK 0x0000ffff
++#define RO_MRX_TYPE_CNT_0_SFT 16
++#define RO_MRX_TYPE_CNT_0_HI 31
++#define RO_MRX_TYPE_CNT_0_SZ 16
++#define RG_HB_COEF0_MSK 0x00000fff
++#define RG_HB_COEF0_I_MSK 0xfffff000
++#define RG_HB_COEF0_SFT 0
++#define RG_HB_COEF0_HI 11
++#define RG_HB_COEF0_SZ 12
++#define RG_HB_COEF1_MSK 0x0fff0000
++#define RG_HB_COEF1_I_MSK 0xf000ffff
++#define RG_HB_COEF1_SFT 16
++#define RG_HB_COEF1_HI 27
++#define RG_HB_COEF1_SZ 12
++#define RG_HB_COEF2_MSK 0x00000fff
++#define RG_HB_COEF2_I_MSK 0xfffff000
++#define RG_HB_COEF2_SFT 0
++#define RG_HB_COEF2_HI 11
++#define RG_HB_COEF2_SZ 12
++#define RG_HB_COEF3_MSK 0x0fff0000
++#define RG_HB_COEF3_I_MSK 0xf000ffff
++#define RG_HB_COEF3_SFT 16
++#define RG_HB_COEF3_HI 27
++#define RG_HB_COEF3_SZ 12
++#define RG_HB_COEF4_MSK 0x00000fff
++#define RG_HB_COEF4_I_MSK 0xfffff000
++#define RG_HB_COEF4_SFT 0
++#define RG_HB_COEF4_HI 11
++#define RG_HB_COEF4_SZ 12
++#define RO_TBUS_O_MSK 0x000fffff
++#define RO_TBUS_O_I_MSK 0xfff00000
++#define RO_TBUS_O_SFT 0
++#define RO_TBUS_O_HI 19
++#define RO_TBUS_O_SZ 20
++#define RG_LPF4_00_MSK 0x00001fff
++#define RG_LPF4_00_I_MSK 0xffffe000
++#define RG_LPF4_00_SFT 0
++#define RG_LPF4_00_HI 12
++#define RG_LPF4_00_SZ 13
++#define RG_LPF4_01_MSK 0x00001fff
++#define RG_LPF4_01_I_MSK 0xffffe000
++#define RG_LPF4_01_SFT 0
++#define RG_LPF4_01_HI 12
++#define RG_LPF4_01_SZ 13
++#define RG_LPF4_02_MSK 0x00001fff
++#define RG_LPF4_02_I_MSK 0xffffe000
++#define RG_LPF4_02_SFT 0
++#define RG_LPF4_02_HI 12
++#define RG_LPF4_02_SZ 13
++#define RG_LPF4_03_MSK 0x00001fff
++#define RG_LPF4_03_I_MSK 0xffffe000
++#define RG_LPF4_03_SFT 0
++#define RG_LPF4_03_HI 12
++#define RG_LPF4_03_SZ 13
++#define RG_LPF4_04_MSK 0x00001fff
++#define RG_LPF4_04_I_MSK 0xffffe000
++#define RG_LPF4_04_SFT 0
++#define RG_LPF4_04_HI 12
++#define RG_LPF4_04_SZ 13
++#define RG_LPF4_05_MSK 0x00001fff
++#define RG_LPF4_05_I_MSK 0xffffe000
++#define RG_LPF4_05_SFT 0
++#define RG_LPF4_05_HI 12
++#define RG_LPF4_05_SZ 13
++#define RG_LPF4_06_MSK 0x00001fff
++#define RG_LPF4_06_I_MSK 0xffffe000
++#define RG_LPF4_06_SFT 0
++#define RG_LPF4_06_HI 12
++#define RG_LPF4_06_SZ 13
++#define RG_LPF4_07_MSK 0x00001fff
++#define RG_LPF4_07_I_MSK 0xffffe000
++#define RG_LPF4_07_SFT 0
++#define RG_LPF4_07_HI 12
++#define RG_LPF4_07_SZ 13
++#define RG_LPF4_08_MSK 0x00001fff
++#define RG_LPF4_08_I_MSK 0xffffe000
++#define RG_LPF4_08_SFT 0
++#define RG_LPF4_08_HI 12
++#define RG_LPF4_08_SZ 13
++#define RG_LPF4_09_MSK 0x00001fff
++#define RG_LPF4_09_I_MSK 0xffffe000
++#define RG_LPF4_09_SFT 0
++#define RG_LPF4_09_HI 12
++#define RG_LPF4_09_SZ 13
++#define RG_LPF4_10_MSK 0x00001fff
++#define RG_LPF4_10_I_MSK 0xffffe000
++#define RG_LPF4_10_SFT 0
++#define RG_LPF4_10_HI 12
++#define RG_LPF4_10_SZ 13
++#define RG_LPF4_11_MSK 0x00001fff
++#define RG_LPF4_11_I_MSK 0xffffe000
++#define RG_LPF4_11_SFT 0
++#define RG_LPF4_11_HI 12
++#define RG_LPF4_11_SZ 13
++#define RG_LPF4_12_MSK 0x00001fff
++#define RG_LPF4_12_I_MSK 0xffffe000
++#define RG_LPF4_12_SFT 0
++#define RG_LPF4_12_HI 12
++#define RG_LPF4_12_SZ 13
++#define RG_LPF4_13_MSK 0x00001fff
++#define RG_LPF4_13_I_MSK 0xffffe000
++#define RG_LPF4_13_SFT 0
++#define RG_LPF4_13_HI 12
++#define RG_LPF4_13_SZ 13
++#define RG_LPF4_14_MSK 0x00001fff
++#define RG_LPF4_14_I_MSK 0xffffe000
++#define RG_LPF4_14_SFT 0
++#define RG_LPF4_14_HI 12
++#define RG_LPF4_14_SZ 13
++#define RG_LPF4_15_MSK 0x00001fff
++#define RG_LPF4_15_I_MSK 0xffffe000
++#define RG_LPF4_15_SFT 0
++#define RG_LPF4_15_HI 12
++#define RG_LPF4_15_SZ 13
++#define RG_LPF4_16_MSK 0x00001fff
++#define RG_LPF4_16_I_MSK 0xffffe000
++#define RG_LPF4_16_SFT 0
++#define RG_LPF4_16_HI 12
++#define RG_LPF4_16_SZ 13
++#define RG_LPF4_17_MSK 0x00001fff
++#define RG_LPF4_17_I_MSK 0xffffe000
++#define RG_LPF4_17_SFT 0
++#define RG_LPF4_17_HI 12
++#define RG_LPF4_17_SZ 13
++#define RG_LPF4_18_MSK 0x00001fff
++#define RG_LPF4_18_I_MSK 0xffffe000
++#define RG_LPF4_18_SFT 0
++#define RG_LPF4_18_HI 12
++#define RG_LPF4_18_SZ 13
++#define RG_LPF4_19_MSK 0x00001fff
++#define RG_LPF4_19_I_MSK 0xffffe000
++#define RG_LPF4_19_SFT 0
++#define RG_LPF4_19_HI 12
++#define RG_LPF4_19_SZ 13
++#define RG_LPF4_20_MSK 0x00001fff
++#define RG_LPF4_20_I_MSK 0xffffe000
++#define RG_LPF4_20_SFT 0
++#define RG_LPF4_20_HI 12
++#define RG_LPF4_20_SZ 13
++#define RG_LPF4_21_MSK 0x00001fff
++#define RG_LPF4_21_I_MSK 0xffffe000
++#define RG_LPF4_21_SFT 0
++#define RG_LPF4_21_HI 12
++#define RG_LPF4_21_SZ 13
++#define RG_LPF4_22_MSK 0x00001fff
++#define RG_LPF4_22_I_MSK 0xffffe000
++#define RG_LPF4_22_SFT 0
++#define RG_LPF4_22_HI 12
++#define RG_LPF4_22_SZ 13
++#define RG_LPF4_23_MSK 0x00001fff
++#define RG_LPF4_23_I_MSK 0xffffe000
++#define RG_LPF4_23_SFT 0
++#define RG_LPF4_23_HI 12
++#define RG_LPF4_23_SZ 13
++#define RG_LPF4_24_MSK 0x00001fff
++#define RG_LPF4_24_I_MSK 0xffffe000
++#define RG_LPF4_24_SFT 0
++#define RG_LPF4_24_HI 12
++#define RG_LPF4_24_SZ 13
++#define RG_LPF4_25_MSK 0x00001fff
++#define RG_LPF4_25_I_MSK 0xffffe000
++#define RG_LPF4_25_SFT 0
++#define RG_LPF4_25_HI 12
++#define RG_LPF4_25_SZ 13
++#define RG_LPF4_26_MSK 0x00001fff
++#define RG_LPF4_26_I_MSK 0xffffe000
++#define RG_LPF4_26_SFT 0
++#define RG_LPF4_26_HI 12
++#define RG_LPF4_26_SZ 13
++#define RG_LPF4_27_MSK 0x00001fff
++#define RG_LPF4_27_I_MSK 0xffffe000
++#define RG_LPF4_27_SFT 0
++#define RG_LPF4_27_HI 12
++#define RG_LPF4_27_SZ 13
++#define RG_LPF4_28_MSK 0x00001fff
++#define RG_LPF4_28_I_MSK 0xffffe000
++#define RG_LPF4_28_SFT 0
++#define RG_LPF4_28_HI 12
++#define RG_LPF4_28_SZ 13
++#define RG_LPF4_29_MSK 0x00001fff
++#define RG_LPF4_29_I_MSK 0xffffe000
++#define RG_LPF4_29_SFT 0
++#define RG_LPF4_29_HI 12
++#define RG_LPF4_29_SZ 13
++#define RG_LPF4_30_MSK 0x00001fff
++#define RG_LPF4_30_I_MSK 0xffffe000
++#define RG_LPF4_30_SFT 0
++#define RG_LPF4_30_HI 12
++#define RG_LPF4_30_SZ 13
++#define RG_LPF4_31_MSK 0x00001fff
++#define RG_LPF4_31_I_MSK 0xffffe000
++#define RG_LPF4_31_SFT 0
++#define RG_LPF4_31_HI 12
++#define RG_LPF4_31_SZ 13
++#define RG_LPF4_32_MSK 0x00001fff
++#define RG_LPF4_32_I_MSK 0xffffe000
++#define RG_LPF4_32_SFT 0
++#define RG_LPF4_32_HI 12
++#define RG_LPF4_32_SZ 13
++#define RG_LPF4_33_MSK 0x00001fff
++#define RG_LPF4_33_I_MSK 0xffffe000
++#define RG_LPF4_33_SFT 0
++#define RG_LPF4_33_HI 12
++#define RG_LPF4_33_SZ 13
++#define RG_LPF4_34_MSK 0x00001fff
++#define RG_LPF4_34_I_MSK 0xffffe000
++#define RG_LPF4_34_SFT 0
++#define RG_LPF4_34_HI 12
++#define RG_LPF4_34_SZ 13
++#define RG_LPF4_35_MSK 0x00001fff
++#define RG_LPF4_35_I_MSK 0xffffe000
++#define RG_LPF4_35_SFT 0
++#define RG_LPF4_35_HI 12
++#define RG_LPF4_35_SZ 13
++#define RG_LPF4_36_MSK 0x00001fff
++#define RG_LPF4_36_I_MSK 0xffffe000
++#define RG_LPF4_36_SFT 0
++#define RG_LPF4_36_HI 12
++#define RG_LPF4_36_SZ 13
++#define RG_LPF4_37_MSK 0x00001fff
++#define RG_LPF4_37_I_MSK 0xffffe000
++#define RG_LPF4_37_SFT 0
++#define RG_LPF4_37_HI 12
++#define RG_LPF4_37_SZ 13
++#define RG_LPF4_38_MSK 0x00001fff
++#define RG_LPF4_38_I_MSK 0xffffe000
++#define RG_LPF4_38_SFT 0
++#define RG_LPF4_38_HI 12
++#define RG_LPF4_38_SZ 13
++#define RG_LPF4_39_MSK 0x00001fff
++#define RG_LPF4_39_I_MSK 0xffffe000
++#define RG_LPF4_39_SFT 0
++#define RG_LPF4_39_HI 12
++#define RG_LPF4_39_SZ 13
++#define RG_LPF4_40_MSK 0x00001fff
++#define RG_LPF4_40_I_MSK 0xffffe000
++#define RG_LPF4_40_SFT 0
++#define RG_LPF4_40_HI 12
++#define RG_LPF4_40_SZ 13
++#define RG_BP_SMB_MSK 0x00002000
++#define RG_BP_SMB_I_MSK 0xffffdfff
++#define RG_BP_SMB_SFT 13
++#define RG_BP_SMB_HI 13
++#define RG_BP_SMB_SZ 1
++#define RG_EN_SRVC_MSK 0x00004000
++#define RG_EN_SRVC_I_MSK 0xffffbfff
++#define RG_EN_SRVC_SFT 14
++#define RG_EN_SRVC_HI 14
++#define RG_EN_SRVC_SZ 1
++#define RG_DES_SPD_MSK 0x00030000
++#define RG_DES_SPD_I_MSK 0xfffcffff
++#define RG_DES_SPD_SFT 16
++#define RG_DES_SPD_HI 17
++#define RG_DES_SPD_SZ 2
++#define RG_BB_11B_RISE_TIME_MSK 0x000000ff
++#define RG_BB_11B_RISE_TIME_I_MSK 0xffffff00
++#define RG_BB_11B_RISE_TIME_SFT 0
++#define RG_BB_11B_RISE_TIME_HI 7
++#define RG_BB_11B_RISE_TIME_SZ 8
++#define RG_BB_11B_FALL_TIME_MSK 0x0000ff00
++#define RG_BB_11B_FALL_TIME_I_MSK 0xffff00ff
++#define RG_BB_11B_FALL_TIME_SFT 8
++#define RG_BB_11B_FALL_TIME_HI 15
++#define RG_BB_11B_FALL_TIME_SZ 8
++#define RG_WR_TX_EN_CNT_RST_N_MSK 0x00000001
++#define RG_WR_TX_EN_CNT_RST_N_I_MSK 0xfffffffe
++#define RG_WR_TX_EN_CNT_RST_N_SFT 0
++#define RG_WR_TX_EN_CNT_RST_N_HI 0
++#define RG_WR_TX_EN_CNT_RST_N_SZ 1
++#define RO_TX_EN_CNT_MSK 0x0000ffff
++#define RO_TX_EN_CNT_I_MSK 0xffff0000
++#define RO_TX_EN_CNT_SFT 0
++#define RO_TX_EN_CNT_HI 15
++#define RO_TX_EN_CNT_SZ 16
++#define RO_TX_CNT_MSK 0xffffffff
++#define RO_TX_CNT_I_MSK 0x00000000
++#define RO_TX_CNT_SFT 0
++#define RO_TX_CNT_HI 31
++#define RO_TX_CNT_SZ 32
++#define RG_POS_DES_11B_L_EXT_MSK 0x0000000f
++#define RG_POS_DES_11B_L_EXT_I_MSK 0xfffffff0
++#define RG_POS_DES_11B_L_EXT_SFT 0
++#define RG_POS_DES_11B_L_EXT_HI 3
++#define RG_POS_DES_11B_L_EXT_SZ 4
++#define RG_PRE_DES_11B_DLY_MSK 0x000000f0
++#define RG_PRE_DES_11B_DLY_I_MSK 0xffffff0f
++#define RG_PRE_DES_11B_DLY_SFT 4
++#define RG_PRE_DES_11B_DLY_HI 7
++#define RG_PRE_DES_11B_DLY_SZ 4
++#define RG_CNT_CCA_LMT_MSK 0x000f0000
++#define RG_CNT_CCA_LMT_I_MSK 0xfff0ffff
++#define RG_CNT_CCA_LMT_SFT 16
++#define RG_CNT_CCA_LMT_HI 19
++#define RG_CNT_CCA_LMT_SZ 4
++#define RG_BYPASS_DESCRAMBLER_MSK 0x20000000
++#define RG_BYPASS_DESCRAMBLER_I_MSK 0xdfffffff
++#define RG_BYPASS_DESCRAMBLER_SFT 29
++#define RG_BYPASS_DESCRAMBLER_HI 29
++#define RG_BYPASS_DESCRAMBLER_SZ 1
++#define RG_BYPASS_AGC_MSK 0x80000000
++#define RG_BYPASS_AGC_I_MSK 0x7fffffff
++#define RG_BYPASS_AGC_SFT 31
++#define RG_BYPASS_AGC_HI 31
++#define RG_BYPASS_AGC_SZ 1
++#define RG_CCA_BIT_CNT_LMT_RX_MSK 0x000000f0
++#define RG_CCA_BIT_CNT_LMT_RX_I_MSK 0xffffff0f
++#define RG_CCA_BIT_CNT_LMT_RX_SFT 4
++#define RG_CCA_BIT_CNT_LMT_RX_HI 7
++#define RG_CCA_BIT_CNT_LMT_RX_SZ 4
++#define RG_CCA_SCALE_BF_MSK 0x007f0000
++#define RG_CCA_SCALE_BF_I_MSK 0xff80ffff
++#define RG_CCA_SCALE_BF_SFT 16
++#define RG_CCA_SCALE_BF_HI 22
++#define RG_CCA_SCALE_BF_SZ 7
++#define RG_PEAK_IDX_CNT_SEL_MSK 0x30000000
++#define RG_PEAK_IDX_CNT_SEL_I_MSK 0xcfffffff
++#define RG_PEAK_IDX_CNT_SEL_SFT 28
++#define RG_PEAK_IDX_CNT_SEL_HI 29
++#define RG_PEAK_IDX_CNT_SEL_SZ 2
++#define RG_TR_KI_T2_MSK 0x00000007
++#define RG_TR_KI_T2_I_MSK 0xfffffff8
++#define RG_TR_KI_T2_SFT 0
++#define RG_TR_KI_T2_HI 2
++#define RG_TR_KI_T2_SZ 3
++#define RG_TR_KP_T2_MSK 0x00000070
++#define RG_TR_KP_T2_I_MSK 0xffffff8f
++#define RG_TR_KP_T2_SFT 4
++#define RG_TR_KP_T2_HI 6
++#define RG_TR_KP_T2_SZ 3
++#define RG_TR_KI_T1_MSK 0x00000700
++#define RG_TR_KI_T1_I_MSK 0xfffff8ff
++#define RG_TR_KI_T1_SFT 8
++#define RG_TR_KI_T1_HI 10
++#define RG_TR_KI_T1_SZ 3
++#define RG_TR_KP_T1_MSK 0x00007000
++#define RG_TR_KP_T1_I_MSK 0xffff8fff
++#define RG_TR_KP_T1_SFT 12
++#define RG_TR_KP_T1_HI 14
++#define RG_TR_KP_T1_SZ 3
++#define RG_CR_KI_T1_MSK 0x00070000
++#define RG_CR_KI_T1_I_MSK 0xfff8ffff
++#define RG_CR_KI_T1_SFT 16
++#define RG_CR_KI_T1_HI 18
++#define RG_CR_KI_T1_SZ 3
++#define RG_CR_KP_T1_MSK 0x00700000
++#define RG_CR_KP_T1_I_MSK 0xff8fffff
++#define RG_CR_KP_T1_SFT 20
++#define RG_CR_KP_T1_HI 22
++#define RG_CR_KP_T1_SZ 3
++#define RG_CHIP_CNT_SLICER_MSK 0x0000001f
++#define RG_CHIP_CNT_SLICER_I_MSK 0xffffffe0
++#define RG_CHIP_CNT_SLICER_SFT 0
++#define RG_CHIP_CNT_SLICER_HI 4
++#define RG_CHIP_CNT_SLICER_SZ 5
++#define RG_CE_T4_CNT_LMT_MSK 0x0000ff00
++#define RG_CE_T4_CNT_LMT_I_MSK 0xffff00ff
++#define RG_CE_T4_CNT_LMT_SFT 8
++#define RG_CE_T4_CNT_LMT_HI 15
++#define RG_CE_T4_CNT_LMT_SZ 8
++#define RG_CE_T3_CNT_LMT_MSK 0x00ff0000
++#define RG_CE_T3_CNT_LMT_I_MSK 0xff00ffff
++#define RG_CE_T3_CNT_LMT_SFT 16
++#define RG_CE_T3_CNT_LMT_HI 23
++#define RG_CE_T3_CNT_LMT_SZ 8
++#define RG_CE_T2_CNT_LMT_MSK 0xff000000
++#define RG_CE_T2_CNT_LMT_I_MSK 0x00ffffff
++#define RG_CE_T2_CNT_LMT_SFT 24
++#define RG_CE_T2_CNT_LMT_HI 31
++#define RG_CE_T2_CNT_LMT_SZ 8
++#define RG_CE_MU_T1_MSK 0x00000007
++#define RG_CE_MU_T1_I_MSK 0xfffffff8
++#define RG_CE_MU_T1_SFT 0
++#define RG_CE_MU_T1_HI 2
++#define RG_CE_MU_T1_SZ 3
++#define RG_CE_DLY_SEL_MSK 0x003f0000
++#define RG_CE_DLY_SEL_I_MSK 0xffc0ffff
++#define RG_CE_DLY_SEL_SFT 16
++#define RG_CE_DLY_SEL_HI 21
++#define RG_CE_DLY_SEL_SZ 6
++#define RG_CE_MU_T8_MSK 0x00000007
++#define RG_CE_MU_T8_I_MSK 0xfffffff8
++#define RG_CE_MU_T8_SFT 0
++#define RG_CE_MU_T8_HI 2
++#define RG_CE_MU_T8_SZ 3
++#define RG_CE_MU_T7_MSK 0x00000070
++#define RG_CE_MU_T7_I_MSK 0xffffff8f
++#define RG_CE_MU_T7_SFT 4
++#define RG_CE_MU_T7_HI 6
++#define RG_CE_MU_T7_SZ 3
++#define RG_CE_MU_T6_MSK 0x00000700
++#define RG_CE_MU_T6_I_MSK 0xfffff8ff
++#define RG_CE_MU_T6_SFT 8
++#define RG_CE_MU_T6_HI 10
++#define RG_CE_MU_T6_SZ 3
++#define RG_CE_MU_T5_MSK 0x00007000
++#define RG_CE_MU_T5_I_MSK 0xffff8fff
++#define RG_CE_MU_T5_SFT 12
++#define RG_CE_MU_T5_HI 14
++#define RG_CE_MU_T5_SZ 3
++#define RG_CE_MU_T4_MSK 0x00070000
++#define RG_CE_MU_T4_I_MSK 0xfff8ffff
++#define RG_CE_MU_T4_SFT 16
++#define RG_CE_MU_T4_HI 18
++#define RG_CE_MU_T4_SZ 3
++#define RG_CE_MU_T3_MSK 0x00700000
++#define RG_CE_MU_T3_I_MSK 0xff8fffff
++#define RG_CE_MU_T3_SFT 20
++#define RG_CE_MU_T3_HI 22
++#define RG_CE_MU_T3_SZ 3
++#define RG_CE_MU_T2_MSK 0x07000000
++#define RG_CE_MU_T2_I_MSK 0xf8ffffff
++#define RG_CE_MU_T2_SFT 24
++#define RG_CE_MU_T2_HI 26
++#define RG_CE_MU_T2_SZ 3
++#define RG_EQ_MU_FB_T2_MSK 0x0000000f
++#define RG_EQ_MU_FB_T2_I_MSK 0xfffffff0
++#define RG_EQ_MU_FB_T2_SFT 0
++#define RG_EQ_MU_FB_T2_HI 3
++#define RG_EQ_MU_FB_T2_SZ 4
++#define RG_EQ_MU_FF_T2_MSK 0x000000f0
++#define RG_EQ_MU_FF_T2_I_MSK 0xffffff0f
++#define RG_EQ_MU_FF_T2_SFT 4
++#define RG_EQ_MU_FF_T2_HI 7
++#define RG_EQ_MU_FF_T2_SZ 4
++#define RG_EQ_MU_FB_T1_MSK 0x000f0000
++#define RG_EQ_MU_FB_T1_I_MSK 0xfff0ffff
++#define RG_EQ_MU_FB_T1_SFT 16
++#define RG_EQ_MU_FB_T1_HI 19
++#define RG_EQ_MU_FB_T1_SZ 4
++#define RG_EQ_MU_FF_T1_MSK 0x00f00000
++#define RG_EQ_MU_FF_T1_I_MSK 0xff0fffff
++#define RG_EQ_MU_FF_T1_SFT 20
++#define RG_EQ_MU_FF_T1_HI 23
++#define RG_EQ_MU_FF_T1_SZ 4
++#define RG_EQ_MU_FB_T4_MSK 0x0000000f
++#define RG_EQ_MU_FB_T4_I_MSK 0xfffffff0
++#define RG_EQ_MU_FB_T4_SFT 0
++#define RG_EQ_MU_FB_T4_HI 3
++#define RG_EQ_MU_FB_T4_SZ 4
++#define RG_EQ_MU_FF_T4_MSK 0x000000f0
++#define RG_EQ_MU_FF_T4_I_MSK 0xffffff0f
++#define RG_EQ_MU_FF_T4_SFT 4
++#define RG_EQ_MU_FF_T4_HI 7
++#define RG_EQ_MU_FF_T4_SZ 4
++#define RG_EQ_MU_FB_T3_MSK 0x000f0000
++#define RG_EQ_MU_FB_T3_I_MSK 0xfff0ffff
++#define RG_EQ_MU_FB_T3_SFT 16
++#define RG_EQ_MU_FB_T3_HI 19
++#define RG_EQ_MU_FB_T3_SZ 4
++#define RG_EQ_MU_FF_T3_MSK 0x00f00000
++#define RG_EQ_MU_FF_T3_I_MSK 0xff0fffff
++#define RG_EQ_MU_FF_T3_SFT 20
++#define RG_EQ_MU_FF_T3_HI 23
++#define RG_EQ_MU_FF_T3_SZ 4
++#define RG_EQ_KI_T2_MSK 0x00000700
++#define RG_EQ_KI_T2_I_MSK 0xfffff8ff
++#define RG_EQ_KI_T2_SFT 8
++#define RG_EQ_KI_T2_HI 10
++#define RG_EQ_KI_T2_SZ 3
++#define RG_EQ_KP_T2_MSK 0x00007000
++#define RG_EQ_KP_T2_I_MSK 0xffff8fff
++#define RG_EQ_KP_T2_SFT 12
++#define RG_EQ_KP_T2_HI 14
++#define RG_EQ_KP_T2_SZ 3
++#define RG_EQ_KI_T1_MSK 0x00070000
++#define RG_EQ_KI_T1_I_MSK 0xfff8ffff
++#define RG_EQ_KI_T1_SFT 16
++#define RG_EQ_KI_T1_HI 18
++#define RG_EQ_KI_T1_SZ 3
++#define RG_EQ_KP_T1_MSK 0x00700000
++#define RG_EQ_KP_T1_I_MSK 0xff8fffff
++#define RG_EQ_KP_T1_SFT 20
++#define RG_EQ_KP_T1_HI 22
++#define RG_EQ_KP_T1_SZ 3
++#define RG_TR_LPF_RATE_MSK 0x003fffff
++#define RG_TR_LPF_RATE_I_MSK 0xffc00000
++#define RG_TR_LPF_RATE_SFT 0
++#define RG_TR_LPF_RATE_HI 21
++#define RG_TR_LPF_RATE_SZ 22
++#define RG_CE_BIT_CNT_LMT_MSK 0x0000007f
++#define RG_CE_BIT_CNT_LMT_I_MSK 0xffffff80
++#define RG_CE_BIT_CNT_LMT_SFT 0
++#define RG_CE_BIT_CNT_LMT_HI 6
++#define RG_CE_BIT_CNT_LMT_SZ 7
++#define RG_CE_CH_MAIN_SET_MSK 0x00000080
++#define RG_CE_CH_MAIN_SET_I_MSK 0xffffff7f
++#define RG_CE_CH_MAIN_SET_SFT 7
++#define RG_CE_CH_MAIN_SET_HI 7
++#define RG_CE_CH_MAIN_SET_SZ 1
++#define RG_TC_BIT_CNT_LMT_MSK 0x00007f00
++#define RG_TC_BIT_CNT_LMT_I_MSK 0xffff80ff
++#define RG_TC_BIT_CNT_LMT_SFT 8
++#define RG_TC_BIT_CNT_LMT_HI 14
++#define RG_TC_BIT_CNT_LMT_SZ 7
++#define RG_CR_BIT_CNT_LMT_MSK 0x007f0000
++#define RG_CR_BIT_CNT_LMT_I_MSK 0xff80ffff
++#define RG_CR_BIT_CNT_LMT_SFT 16
++#define RG_CR_BIT_CNT_LMT_HI 22
++#define RG_CR_BIT_CNT_LMT_SZ 7
++#define RG_TR_BIT_CNT_LMT_MSK 0x7f000000
++#define RG_TR_BIT_CNT_LMT_I_MSK 0x80ffffff
++#define RG_TR_BIT_CNT_LMT_SFT 24
++#define RG_TR_BIT_CNT_LMT_HI 30
++#define RG_TR_BIT_CNT_LMT_SZ 7
++#define RG_EQ_MAIN_TAP_MAN_MSK 0x00000001
++#define RG_EQ_MAIN_TAP_MAN_I_MSK 0xfffffffe
++#define RG_EQ_MAIN_TAP_MAN_SFT 0
++#define RG_EQ_MAIN_TAP_MAN_HI 0
++#define RG_EQ_MAIN_TAP_MAN_SZ 1
++#define RG_EQ_MAIN_TAP_COEF_MSK 0x07ff0000
++#define RG_EQ_MAIN_TAP_COEF_I_MSK 0xf800ffff
++#define RG_EQ_MAIN_TAP_COEF_SFT 16
++#define RG_EQ_MAIN_TAP_COEF_HI 26
++#define RG_EQ_MAIN_TAP_COEF_SZ 11
++#define RG_PWRON_DLY_TH_11B_MSK 0x000000ff
++#define RG_PWRON_DLY_TH_11B_I_MSK 0xffffff00
++#define RG_PWRON_DLY_TH_11B_SFT 0
++#define RG_PWRON_DLY_TH_11B_HI 7
++#define RG_PWRON_DLY_TH_11B_SZ 8
++#define RG_SFD_BIT_CNT_LMT_MSK 0x00ff0000
++#define RG_SFD_BIT_CNT_LMT_I_MSK 0xff00ffff
++#define RG_SFD_BIT_CNT_LMT_SFT 16
++#define RG_SFD_BIT_CNT_LMT_HI 23
++#define RG_SFD_BIT_CNT_LMT_SZ 8
++#define RG_CCA_PWR_TH_RX_MSK 0x00007fff
++#define RG_CCA_PWR_TH_RX_I_MSK 0xffff8000
++#define RG_CCA_PWR_TH_RX_SFT 0
++#define RG_CCA_PWR_TH_RX_HI 14
++#define RG_CCA_PWR_TH_RX_SZ 15
++#define RG_CCA_PWR_CNT_TH_MSK 0x001f0000
++#define RG_CCA_PWR_CNT_TH_I_MSK 0xffe0ffff
++#define RG_CCA_PWR_CNT_TH_SFT 16
++#define RG_CCA_PWR_CNT_TH_HI 20
++#define RG_CCA_PWR_CNT_TH_SZ 5
++#define B_FREQ_OS_MSK 0x000007ff
++#define B_FREQ_OS_I_MSK 0xfffff800
++#define B_FREQ_OS_SFT 0
++#define B_FREQ_OS_HI 10
++#define B_FREQ_OS_SZ 11
++#define B_SNR_MSK 0x0000007f
++#define B_SNR_I_MSK 0xffffff80
++#define B_SNR_SFT 0
++#define B_SNR_HI 6
++#define B_SNR_SZ 7
++#define B_RCPI_MSK 0x007f0000
++#define B_RCPI_I_MSK 0xff80ffff
++#define B_RCPI_SFT 16
++#define B_RCPI_HI 22
++#define B_RCPI_SZ 7
++#define CRC_CNT_MSK 0x0000ffff
++#define CRC_CNT_I_MSK 0xffff0000
++#define CRC_CNT_SFT 0
++#define CRC_CNT_HI 15
++#define CRC_CNT_SZ 16
++#define SFD_CNT_MSK 0xffff0000
++#define SFD_CNT_I_MSK 0x0000ffff
++#define SFD_CNT_SFT 16
++#define SFD_CNT_HI 31
++#define SFD_CNT_SZ 16
++#define B_PACKET_ERR_CNT_MSK 0x0000ffff
++#define B_PACKET_ERR_CNT_I_MSK 0xffff0000
++#define B_PACKET_ERR_CNT_SFT 0
++#define B_PACKET_ERR_CNT_HI 15
++#define B_PACKET_ERR_CNT_SZ 16
++#define PACKET_ERR_MSK 0x00010000
++#define PACKET_ERR_I_MSK 0xfffeffff
++#define PACKET_ERR_SFT 16
++#define PACKET_ERR_HI 16
++#define PACKET_ERR_SZ 1
++#define B_PACKET_CNT_MSK 0x0000ffff
++#define B_PACKET_CNT_I_MSK 0xffff0000
++#define B_PACKET_CNT_SFT 0
++#define B_PACKET_CNT_HI 15
++#define B_PACKET_CNT_SZ 16
++#define B_CCA_CNT_MSK 0xffff0000
++#define B_CCA_CNT_I_MSK 0x0000ffff
++#define B_CCA_CNT_SFT 16
++#define B_CCA_CNT_HI 31
++#define B_CCA_CNT_SZ 16
++#define B_LENGTH_FIELD_MSK 0x0000ffff
++#define B_LENGTH_FIELD_I_MSK 0xffff0000
++#define B_LENGTH_FIELD_SFT 0
++#define B_LENGTH_FIELD_HI 15
++#define B_LENGTH_FIELD_SZ 16
++#define SFD_FIELD_MSK 0xffff0000
++#define SFD_FIELD_I_MSK 0x0000ffff
++#define SFD_FIELD_SFT 16
++#define SFD_FIELD_HI 31
++#define SFD_FIELD_SZ 16
++#define SIGNAL_FIELD_MSK 0x000000ff
++#define SIGNAL_FIELD_I_MSK 0xffffff00
++#define SIGNAL_FIELD_SFT 0
++#define SIGNAL_FIELD_HI 7
++#define SIGNAL_FIELD_SZ 8
++#define B_SERVICE_FIELD_MSK 0x0000ff00
++#define B_SERVICE_FIELD_I_MSK 0xffff00ff
++#define B_SERVICE_FIELD_SFT 8
++#define B_SERVICE_FIELD_HI 15
++#define B_SERVICE_FIELD_SZ 8
++#define CRC_CORRECT_MSK 0x00010000
++#define CRC_CORRECT_I_MSK 0xfffeffff
++#define CRC_CORRECT_SFT 16
++#define CRC_CORRECT_HI 16
++#define CRC_CORRECT_SZ 1
++#define DEBUG_SEL_MSK 0x0000000f
++#define DEBUG_SEL_I_MSK 0xfffffff0
++#define DEBUG_SEL_SFT 0
++#define DEBUG_SEL_HI 3
++#define DEBUG_SEL_SZ 4
++#define RG_PACKET_STAT_EN_11B_MSK 0x00100000
++#define RG_PACKET_STAT_EN_11B_I_MSK 0xffefffff
++#define RG_PACKET_STAT_EN_11B_SFT 20
++#define RG_PACKET_STAT_EN_11B_HI 20
++#define RG_PACKET_STAT_EN_11B_SZ 1
++#define RG_BIT_REVERSE_MSK 0x00200000
++#define RG_BIT_REVERSE_I_MSK 0xffdfffff
++#define RG_BIT_REVERSE_SFT 21
++#define RG_BIT_REVERSE_HI 21
++#define RG_BIT_REVERSE_SZ 1
++#define RX_PHY_11B_SOFT_RST_N_MSK 0x00000001
++#define RX_PHY_11B_SOFT_RST_N_I_MSK 0xfffffffe
++#define RX_PHY_11B_SOFT_RST_N_SFT 0
++#define RX_PHY_11B_SOFT_RST_N_HI 0
++#define RX_PHY_11B_SOFT_RST_N_SZ 1
++#define RG_CE_BYPASS_TAP_MSK 0x000000f0
++#define RG_CE_BYPASS_TAP_I_MSK 0xffffff0f
++#define RG_CE_BYPASS_TAP_SFT 4
++#define RG_CE_BYPASS_TAP_HI 7
++#define RG_CE_BYPASS_TAP_SZ 4
++#define RG_EQ_BYPASS_FBW_TAP_MSK 0x00000f00
++#define RG_EQ_BYPASS_FBW_TAP_I_MSK 0xfffff0ff
++#define RG_EQ_BYPASS_FBW_TAP_SFT 8
++#define RG_EQ_BYPASS_FBW_TAP_HI 11
++#define RG_EQ_BYPASS_FBW_TAP_SZ 4
++#define RG_BB_11GN_RISE_TIME_MSK 0x000000ff
++#define RG_BB_11GN_RISE_TIME_I_MSK 0xffffff00
++#define RG_BB_11GN_RISE_TIME_SFT 0
++#define RG_BB_11GN_RISE_TIME_HI 7
++#define RG_BB_11GN_RISE_TIME_SZ 8
++#define RG_BB_11GN_FALL_TIME_MSK 0x0000ff00
++#define RG_BB_11GN_FALL_TIME_I_MSK 0xffff00ff
++#define RG_BB_11GN_FALL_TIME_SFT 8
++#define RG_BB_11GN_FALL_TIME_HI 15
++#define RG_BB_11GN_FALL_TIME_SZ 8
++#define RG_HTCARR52_FFT_SCALE_MSK 0x000003ff
++#define RG_HTCARR52_FFT_SCALE_I_MSK 0xfffffc00
++#define RG_HTCARR52_FFT_SCALE_SFT 0
++#define RG_HTCARR52_FFT_SCALE_HI 9
++#define RG_HTCARR52_FFT_SCALE_SZ 10
++#define RG_HTCARR56_FFT_SCALE_MSK 0x003ff000
++#define RG_HTCARR56_FFT_SCALE_I_MSK 0xffc00fff
++#define RG_HTCARR56_FFT_SCALE_SFT 12
++#define RG_HTCARR56_FFT_SCALE_HI 21
++#define RG_HTCARR56_FFT_SCALE_SZ 10
++#define RG_PACKET_STAT_EN_MSK 0x00800000
++#define RG_PACKET_STAT_EN_I_MSK 0xff7fffff
++#define RG_PACKET_STAT_EN_SFT 23
++#define RG_PACKET_STAT_EN_HI 23
++#define RG_PACKET_STAT_EN_SZ 1
++#define RG_SMB_DEF_MSK 0x7f000000
++#define RG_SMB_DEF_I_MSK 0x80ffffff
++#define RG_SMB_DEF_SFT 24
++#define RG_SMB_DEF_HI 30
++#define RG_SMB_DEF_SZ 7
++#define RG_CONTINUOUS_DATA_11GN_MSK 0x80000000
++#define RG_CONTINUOUS_DATA_11GN_I_MSK 0x7fffffff
++#define RG_CONTINUOUS_DATA_11GN_SFT 31
++#define RG_CONTINUOUS_DATA_11GN_HI 31
++#define RG_CONTINUOUS_DATA_11GN_SZ 1
++#define RO_TX_CNT_R_MSK 0xffffffff
++#define RO_TX_CNT_R_I_MSK 0x00000000
++#define RO_TX_CNT_R_SFT 0
++#define RO_TX_CNT_R_HI 31
++#define RO_TX_CNT_R_SZ 32
++#define RO_PACKET_ERR_CNT_MSK 0x0000ffff
++#define RO_PACKET_ERR_CNT_I_MSK 0xffff0000
++#define RO_PACKET_ERR_CNT_SFT 0
++#define RO_PACKET_ERR_CNT_HI 15
++#define RO_PACKET_ERR_CNT_SZ 16
++#define RG_POS_DES_11GN_L_EXT_MSK 0x0000000f
++#define RG_POS_DES_11GN_L_EXT_I_MSK 0xfffffff0
++#define RG_POS_DES_11GN_L_EXT_SFT 0
++#define RG_POS_DES_11GN_L_EXT_HI 3
++#define RG_POS_DES_11GN_L_EXT_SZ 4
++#define RG_PRE_DES_11GN_DLY_MSK 0x000000f0
++#define RG_PRE_DES_11GN_DLY_I_MSK 0xffffff0f
++#define RG_PRE_DES_11GN_DLY_SFT 4
++#define RG_PRE_DES_11GN_DLY_HI 7
++#define RG_PRE_DES_11GN_DLY_SZ 4
++#define RG_TR_LPF_KI_G_T1_MSK 0x0000000f
++#define RG_TR_LPF_KI_G_T1_I_MSK 0xfffffff0
++#define RG_TR_LPF_KI_G_T1_SFT 0
++#define RG_TR_LPF_KI_G_T1_HI 3
++#define RG_TR_LPF_KI_G_T1_SZ 4
++#define RG_TR_LPF_KP_G_T1_MSK 0x000000f0
++#define RG_TR_LPF_KP_G_T1_I_MSK 0xffffff0f
++#define RG_TR_LPF_KP_G_T1_SFT 4
++#define RG_TR_LPF_KP_G_T1_HI 7
++#define RG_TR_LPF_KP_G_T1_SZ 4
++#define RG_TR_CNT_T1_MSK 0x0000ff00
++#define RG_TR_CNT_T1_I_MSK 0xffff00ff
++#define RG_TR_CNT_T1_SFT 8
++#define RG_TR_CNT_T1_HI 15
++#define RG_TR_CNT_T1_SZ 8
++#define RG_TR_LPF_KI_G_T0_MSK 0x000f0000
++#define RG_TR_LPF_KI_G_T0_I_MSK 0xfff0ffff
++#define RG_TR_LPF_KI_G_T0_SFT 16
++#define RG_TR_LPF_KI_G_T0_HI 19
++#define RG_TR_LPF_KI_G_T0_SZ 4
++#define RG_TR_LPF_KP_G_T0_MSK 0x00f00000
++#define RG_TR_LPF_KP_G_T0_I_MSK 0xff0fffff
++#define RG_TR_LPF_KP_G_T0_SFT 20
++#define RG_TR_LPF_KP_G_T0_HI 23
++#define RG_TR_LPF_KP_G_T0_SZ 4
++#define RG_TR_CNT_T0_MSK 0xff000000
++#define RG_TR_CNT_T0_I_MSK 0x00ffffff
++#define RG_TR_CNT_T0_SFT 24
++#define RG_TR_CNT_T0_HI 31
++#define RG_TR_CNT_T0_SZ 8
++#define RG_TR_LPF_KI_G_T2_MSK 0x0000000f
++#define RG_TR_LPF_KI_G_T2_I_MSK 0xfffffff0
++#define RG_TR_LPF_KI_G_T2_SFT 0
++#define RG_TR_LPF_KI_G_T2_HI 3
++#define RG_TR_LPF_KI_G_T2_SZ 4
++#define RG_TR_LPF_KP_G_T2_MSK 0x000000f0
++#define RG_TR_LPF_KP_G_T2_I_MSK 0xffffff0f
++#define RG_TR_LPF_KP_G_T2_SFT 4
++#define RG_TR_LPF_KP_G_T2_HI 7
++#define RG_TR_LPF_KP_G_T2_SZ 4
++#define RG_TR_CNT_T2_MSK 0x0000ff00
++#define RG_TR_CNT_T2_I_MSK 0xffff00ff
++#define RG_TR_CNT_T2_SFT 8
++#define RG_TR_CNT_T2_HI 15
++#define RG_TR_CNT_T2_SZ 8
++#define RG_TR_LPF_KI_G_MSK 0x0000000f
++#define RG_TR_LPF_KI_G_I_MSK 0xfffffff0
++#define RG_TR_LPF_KI_G_SFT 0
++#define RG_TR_LPF_KI_G_HI 3
++#define RG_TR_LPF_KI_G_SZ 4
++#define RG_TR_LPF_KP_G_MSK 0x000000f0
++#define RG_TR_LPF_KP_G_I_MSK 0xffffff0f
++#define RG_TR_LPF_KP_G_SFT 4
++#define RG_TR_LPF_KP_G_HI 7
++#define RG_TR_LPF_KP_G_SZ 4
++#define RG_TR_LPF_RATE_G_MSK 0x3fffff00
++#define RG_TR_LPF_RATE_G_I_MSK 0xc00000ff
++#define RG_TR_LPF_RATE_G_SFT 8
++#define RG_TR_LPF_RATE_G_HI 29
++#define RG_TR_LPF_RATE_G_SZ 22
++#define RG_CR_LPF_KI_G_MSK 0x00000007
++#define RG_CR_LPF_KI_G_I_MSK 0xfffffff8
++#define RG_CR_LPF_KI_G_SFT 0
++#define RG_CR_LPF_KI_G_HI 2
++#define RG_CR_LPF_KI_G_SZ 3
++#define RG_SYM_BOUND_CNT_MSK 0x00007f00
++#define RG_SYM_BOUND_CNT_I_MSK 0xffff80ff
++#define RG_SYM_BOUND_CNT_SFT 8
++#define RG_SYM_BOUND_CNT_HI 14
++#define RG_SYM_BOUND_CNT_SZ 7
++#define RG_XSCOR32_RATIO_MSK 0x007f0000
++#define RG_XSCOR32_RATIO_I_MSK 0xff80ffff
++#define RG_XSCOR32_RATIO_SFT 16
++#define RG_XSCOR32_RATIO_HI 22
++#define RG_XSCOR32_RATIO_SZ 7
++#define RG_ATCOR64_CNT_LMT_MSK 0x7f000000
++#define RG_ATCOR64_CNT_LMT_I_MSK 0x80ffffff
++#define RG_ATCOR64_CNT_LMT_SFT 24
++#define RG_ATCOR64_CNT_LMT_HI 30
++#define RG_ATCOR64_CNT_LMT_SZ 7
++#define RG_ATCOR16_CNT_LMT2_MSK 0x00007f00
++#define RG_ATCOR16_CNT_LMT2_I_MSK 0xffff80ff
++#define RG_ATCOR16_CNT_LMT2_SFT 8
++#define RG_ATCOR16_CNT_LMT2_HI 14
++#define RG_ATCOR16_CNT_LMT2_SZ 7
++#define RG_ATCOR16_CNT_LMT1_MSK 0x007f0000
++#define RG_ATCOR16_CNT_LMT1_I_MSK 0xff80ffff
++#define RG_ATCOR16_CNT_LMT1_SFT 16
++#define RG_ATCOR16_CNT_LMT1_HI 22
++#define RG_ATCOR16_CNT_LMT1_SZ 7
++#define RG_ATCOR16_RATIO_SB_MSK 0x7f000000
++#define RG_ATCOR16_RATIO_SB_I_MSK 0x80ffffff
++#define RG_ATCOR16_RATIO_SB_SFT 24
++#define RG_ATCOR16_RATIO_SB_HI 30
++#define RG_ATCOR16_RATIO_SB_SZ 7
++#define RG_XSCOR64_CNT_LMT2_MSK 0x007f0000
++#define RG_XSCOR64_CNT_LMT2_I_MSK 0xff80ffff
++#define RG_XSCOR64_CNT_LMT2_SFT 16
++#define RG_XSCOR64_CNT_LMT2_HI 22
++#define RG_XSCOR64_CNT_LMT2_SZ 7
++#define RG_XSCOR64_CNT_LMT1_MSK 0x7f000000
++#define RG_XSCOR64_CNT_LMT1_I_MSK 0x80ffffff
++#define RG_XSCOR64_CNT_LMT1_SFT 24
++#define RG_XSCOR64_CNT_LMT1_HI 30
++#define RG_XSCOR64_CNT_LMT1_SZ 7
++#define RG_RX_FFT_SCALE_MSK 0x000003ff
++#define RG_RX_FFT_SCALE_I_MSK 0xfffffc00
++#define RG_RX_FFT_SCALE_SFT 0
++#define RG_RX_FFT_SCALE_HI 9
++#define RG_RX_FFT_SCALE_SZ 10
++#define RG_VITERBI_AB_SWAP_MSK 0x00010000
++#define RG_VITERBI_AB_SWAP_I_MSK 0xfffeffff
++#define RG_VITERBI_AB_SWAP_SFT 16
++#define RG_VITERBI_AB_SWAP_HI 16
++#define RG_VITERBI_AB_SWAP_SZ 1
++#define RG_ATCOR16_CNT_TH_MSK 0x0f000000
++#define RG_ATCOR16_CNT_TH_I_MSK 0xf0ffffff
++#define RG_ATCOR16_CNT_TH_SFT 24
++#define RG_ATCOR16_CNT_TH_HI 27
++#define RG_ATCOR16_CNT_TH_SZ 4
++#define RG_NORMSQUARE_LOW_SNR_7_MSK 0x000000ff
++#define RG_NORMSQUARE_LOW_SNR_7_I_MSK 0xffffff00
++#define RG_NORMSQUARE_LOW_SNR_7_SFT 0
++#define RG_NORMSQUARE_LOW_SNR_7_HI 7
++#define RG_NORMSQUARE_LOW_SNR_7_SZ 8
++#define RG_NORMSQUARE_LOW_SNR_6_MSK 0x0000ff00
++#define RG_NORMSQUARE_LOW_SNR_6_I_MSK 0xffff00ff
++#define RG_NORMSQUARE_LOW_SNR_6_SFT 8
++#define RG_NORMSQUARE_LOW_SNR_6_HI 15
++#define RG_NORMSQUARE_LOW_SNR_6_SZ 8
++#define RG_NORMSQUARE_LOW_SNR_5_MSK 0x00ff0000
++#define RG_NORMSQUARE_LOW_SNR_5_I_MSK 0xff00ffff
++#define RG_NORMSQUARE_LOW_SNR_5_SFT 16
++#define RG_NORMSQUARE_LOW_SNR_5_HI 23
++#define RG_NORMSQUARE_LOW_SNR_5_SZ 8
++#define RG_NORMSQUARE_LOW_SNR_4_MSK 0xff000000
++#define RG_NORMSQUARE_LOW_SNR_4_I_MSK 0x00ffffff
++#define RG_NORMSQUARE_LOW_SNR_4_SFT 24
++#define RG_NORMSQUARE_LOW_SNR_4_HI 31
++#define RG_NORMSQUARE_LOW_SNR_4_SZ 8
++#define RG_NORMSQUARE_LOW_SNR_8_MSK 0xff000000
++#define RG_NORMSQUARE_LOW_SNR_8_I_MSK 0x00ffffff
++#define RG_NORMSQUARE_LOW_SNR_8_SFT 24
++#define RG_NORMSQUARE_LOW_SNR_8_HI 31
++#define RG_NORMSQUARE_LOW_SNR_8_SZ 8
++#define RG_NORMSQUARE_SNR_3_MSK 0x000000ff
++#define RG_NORMSQUARE_SNR_3_I_MSK 0xffffff00
++#define RG_NORMSQUARE_SNR_3_SFT 0
++#define RG_NORMSQUARE_SNR_3_HI 7
++#define RG_NORMSQUARE_SNR_3_SZ 8
++#define RG_NORMSQUARE_SNR_2_MSK 0x0000ff00
++#define RG_NORMSQUARE_SNR_2_I_MSK 0xffff00ff
++#define RG_NORMSQUARE_SNR_2_SFT 8
++#define RG_NORMSQUARE_SNR_2_HI 15
++#define RG_NORMSQUARE_SNR_2_SZ 8
++#define RG_NORMSQUARE_SNR_1_MSK 0x00ff0000
++#define RG_NORMSQUARE_SNR_1_I_MSK 0xff00ffff
++#define RG_NORMSQUARE_SNR_1_SFT 16
++#define RG_NORMSQUARE_SNR_1_HI 23
++#define RG_NORMSQUARE_SNR_1_SZ 8
++#define RG_NORMSQUARE_SNR_0_MSK 0xff000000
++#define RG_NORMSQUARE_SNR_0_I_MSK 0x00ffffff
++#define RG_NORMSQUARE_SNR_0_SFT 24
++#define RG_NORMSQUARE_SNR_0_HI 31
++#define RG_NORMSQUARE_SNR_0_SZ 8
++#define RG_NORMSQUARE_SNR_7_MSK 0x000000ff
++#define RG_NORMSQUARE_SNR_7_I_MSK 0xffffff00
++#define RG_NORMSQUARE_SNR_7_SFT 0
++#define RG_NORMSQUARE_SNR_7_HI 7
++#define RG_NORMSQUARE_SNR_7_SZ 8
++#define RG_NORMSQUARE_SNR_6_MSK 0x0000ff00
++#define RG_NORMSQUARE_SNR_6_I_MSK 0xffff00ff
++#define RG_NORMSQUARE_SNR_6_SFT 8
++#define RG_NORMSQUARE_SNR_6_HI 15
++#define RG_NORMSQUARE_SNR_6_SZ 8
++#define RG_NORMSQUARE_SNR_5_MSK 0x00ff0000
++#define RG_NORMSQUARE_SNR_5_I_MSK 0xff00ffff
++#define RG_NORMSQUARE_SNR_5_SFT 16
++#define RG_NORMSQUARE_SNR_5_HI 23
++#define RG_NORMSQUARE_SNR_5_SZ 8
++#define RG_NORMSQUARE_SNR_4_MSK 0xff000000
++#define RG_NORMSQUARE_SNR_4_I_MSK 0x00ffffff
++#define RG_NORMSQUARE_SNR_4_SFT 24
++#define RG_NORMSQUARE_SNR_4_HI 31
++#define RG_NORMSQUARE_SNR_4_SZ 8
++#define RG_NORMSQUARE_SNR_8_MSK 0xff000000
++#define RG_NORMSQUARE_SNR_8_I_MSK 0x00ffffff
++#define RG_NORMSQUARE_SNR_8_SFT 24
++#define RG_NORMSQUARE_SNR_8_HI 31
++#define RG_NORMSQUARE_SNR_8_SZ 8
++#define RG_SNR_TH_64QAM_MSK 0x0000007f
++#define RG_SNR_TH_64QAM_I_MSK 0xffffff80
++#define RG_SNR_TH_64QAM_SFT 0
++#define RG_SNR_TH_64QAM_HI 6
++#define RG_SNR_TH_64QAM_SZ 7
++#define RG_SNR_TH_16QAM_MSK 0x00007f00
++#define RG_SNR_TH_16QAM_I_MSK 0xffff80ff
++#define RG_SNR_TH_16QAM_SFT 8
++#define RG_SNR_TH_16QAM_HI 14
++#define RG_SNR_TH_16QAM_SZ 7
++#define RG_ATCOR16_CNT_PLUS_LMT2_MSK 0x0000007f
++#define RG_ATCOR16_CNT_PLUS_LMT2_I_MSK 0xffffff80
++#define RG_ATCOR16_CNT_PLUS_LMT2_SFT 0
++#define RG_ATCOR16_CNT_PLUS_LMT2_HI 6
++#define RG_ATCOR16_CNT_PLUS_LMT2_SZ 7
++#define RG_ATCOR16_CNT_PLUS_LMT1_MSK 0x00007f00
++#define RG_ATCOR16_CNT_PLUS_LMT1_I_MSK 0xffff80ff
++#define RG_ATCOR16_CNT_PLUS_LMT1_SFT 8
++#define RG_ATCOR16_CNT_PLUS_LMT1_HI 14
++#define RG_ATCOR16_CNT_PLUS_LMT1_SZ 7
++#define RG_SYM_BOUND_METHOD_MSK 0x00030000
++#define RG_SYM_BOUND_METHOD_I_MSK 0xfffcffff
++#define RG_SYM_BOUND_METHOD_SFT 16
++#define RG_SYM_BOUND_METHOD_HI 17
++#define RG_SYM_BOUND_METHOD_SZ 2
++#define RG_PWRON_DLY_TH_11GN_MSK 0x000000ff
++#define RG_PWRON_DLY_TH_11GN_I_MSK 0xffffff00
++#define RG_PWRON_DLY_TH_11GN_SFT 0
++#define RG_PWRON_DLY_TH_11GN_HI 7
++#define RG_PWRON_DLY_TH_11GN_SZ 8
++#define RG_SB_START_CNT_MSK 0x00007f00
++#define RG_SB_START_CNT_I_MSK 0xffff80ff
++#define RG_SB_START_CNT_SFT 8
++#define RG_SB_START_CNT_HI 14
++#define RG_SB_START_CNT_SZ 7
++#define RG_POW16_CNT_TH_MSK 0x000000f0
++#define RG_POW16_CNT_TH_I_MSK 0xffffff0f
++#define RG_POW16_CNT_TH_SFT 4
++#define RG_POW16_CNT_TH_HI 7
++#define RG_POW16_CNT_TH_SZ 4
++#define RG_POW16_SHORT_CNT_LMT_MSK 0x00000700
++#define RG_POW16_SHORT_CNT_LMT_I_MSK 0xfffff8ff
++#define RG_POW16_SHORT_CNT_LMT_SFT 8
++#define RG_POW16_SHORT_CNT_LMT_HI 10
++#define RG_POW16_SHORT_CNT_LMT_SZ 3
++#define RG_POW16_TH_L_MSK 0x7f000000
++#define RG_POW16_TH_L_I_MSK 0x80ffffff
++#define RG_POW16_TH_L_SFT 24
++#define RG_POW16_TH_L_HI 30
++#define RG_POW16_TH_L_SZ 7
++#define RG_XSCOR16_SHORT_CNT_LMT_MSK 0x00000007
++#define RG_XSCOR16_SHORT_CNT_LMT_I_MSK 0xfffffff8
++#define RG_XSCOR16_SHORT_CNT_LMT_SFT 0
++#define RG_XSCOR16_SHORT_CNT_LMT_HI 2
++#define RG_XSCOR16_SHORT_CNT_LMT_SZ 3
++#define RG_XSCOR16_RATIO_MSK 0x00007f00
++#define RG_XSCOR16_RATIO_I_MSK 0xffff80ff
++#define RG_XSCOR16_RATIO_SFT 8
++#define RG_XSCOR16_RATIO_HI 14
++#define RG_XSCOR16_RATIO_SZ 7
++#define RG_ATCOR16_SHORT_CNT_LMT_MSK 0x00070000
++#define RG_ATCOR16_SHORT_CNT_LMT_I_MSK 0xfff8ffff
++#define RG_ATCOR16_SHORT_CNT_LMT_SFT 16
++#define RG_ATCOR16_SHORT_CNT_LMT_HI 18
++#define RG_ATCOR16_SHORT_CNT_LMT_SZ 3
++#define RG_ATCOR16_RATIO_CCD_MSK 0x7f000000
++#define RG_ATCOR16_RATIO_CCD_I_MSK 0x80ffffff
++#define RG_ATCOR16_RATIO_CCD_SFT 24
++#define RG_ATCOR16_RATIO_CCD_HI 30
++#define RG_ATCOR16_RATIO_CCD_SZ 7
++#define RG_ATCOR64_ACC_LMT_MSK 0x0000007f
++#define RG_ATCOR64_ACC_LMT_I_MSK 0xffffff80
++#define RG_ATCOR64_ACC_LMT_SFT 0
++#define RG_ATCOR64_ACC_LMT_HI 6
++#define RG_ATCOR64_ACC_LMT_SZ 7
++#define RG_ATCOR16_SHORT_CNT_LMT2_MSK 0x00070000
++#define RG_ATCOR16_SHORT_CNT_LMT2_I_MSK 0xfff8ffff
++#define RG_ATCOR16_SHORT_CNT_LMT2_SFT 16
++#define RG_ATCOR16_SHORT_CNT_LMT2_HI 18
++#define RG_ATCOR16_SHORT_CNT_LMT2_SZ 3
++#define RG_VITERBI_TB_BITS_MSK 0xff000000
++#define RG_VITERBI_TB_BITS_I_MSK 0x00ffffff
++#define RG_VITERBI_TB_BITS_SFT 24
++#define RG_VITERBI_TB_BITS_HI 31
++#define RG_VITERBI_TB_BITS_SZ 8
++#define RG_CR_CNT_UPDATE_MSK 0x000000ff
++#define RG_CR_CNT_UPDATE_I_MSK 0xffffff00
++#define RG_CR_CNT_UPDATE_SFT 0
++#define RG_CR_CNT_UPDATE_HI 7
++#define RG_CR_CNT_UPDATE_SZ 8
++#define RG_TR_CNT_UPDATE_MSK 0x00ff0000
++#define RG_TR_CNT_UPDATE_I_MSK 0xff00ffff
++#define RG_TR_CNT_UPDATE_SFT 16
++#define RG_TR_CNT_UPDATE_HI 23
++#define RG_TR_CNT_UPDATE_SZ 8
++#define RG_BYPASS_CPE_MA_MSK 0x00000010
++#define RG_BYPASS_CPE_MA_I_MSK 0xffffffef
++#define RG_BYPASS_CPE_MA_SFT 4
++#define RG_BYPASS_CPE_MA_HI 4
++#define RG_BYPASS_CPE_MA_SZ 1
++#define RG_PILOT_BNDRY_SHIFT_MSK 0x00000700
++#define RG_PILOT_BNDRY_SHIFT_I_MSK 0xfffff8ff
++#define RG_PILOT_BNDRY_SHIFT_SFT 8
++#define RG_PILOT_BNDRY_SHIFT_HI 10
++#define RG_PILOT_BNDRY_SHIFT_SZ 3
++#define RG_EQ_SHORT_GI_SHIFT_MSK 0x00007000
++#define RG_EQ_SHORT_GI_SHIFT_I_MSK 0xffff8fff
++#define RG_EQ_SHORT_GI_SHIFT_SFT 12
++#define RG_EQ_SHORT_GI_SHIFT_HI 14
++#define RG_EQ_SHORT_GI_SHIFT_SZ 3
++#define RG_FFT_WDW_SHORT_SHIFT_MSK 0x00070000
++#define RG_FFT_WDW_SHORT_SHIFT_I_MSK 0xfff8ffff
++#define RG_FFT_WDW_SHORT_SHIFT_SFT 16
++#define RG_FFT_WDW_SHORT_SHIFT_HI 18
++#define RG_FFT_WDW_SHORT_SHIFT_SZ 3
++#define RG_CHSMTH_COEF_MSK 0x00030000
++#define RG_CHSMTH_COEF_I_MSK 0xfffcffff
++#define RG_CHSMTH_COEF_SFT 16
++#define RG_CHSMTH_COEF_HI 17
++#define RG_CHSMTH_COEF_SZ 2
++#define RG_CHSMTH_EN_MSK 0x00040000
++#define RG_CHSMTH_EN_I_MSK 0xfffbffff
++#define RG_CHSMTH_EN_SFT 18
++#define RG_CHSMTH_EN_HI 18
++#define RG_CHSMTH_EN_SZ 1
++#define RG_CHEST_DD_FACTOR_MSK 0x07000000
++#define RG_CHEST_DD_FACTOR_I_MSK 0xf8ffffff
++#define RG_CHEST_DD_FACTOR_SFT 24
++#define RG_CHEST_DD_FACTOR_HI 26
++#define RG_CHEST_DD_FACTOR_SZ 3
++#define RG_CH_UPDATE_MSK 0x80000000
++#define RG_CH_UPDATE_I_MSK 0x7fffffff
++#define RG_CH_UPDATE_SFT 31
++#define RG_CH_UPDATE_HI 31
++#define RG_CH_UPDATE_SZ 1
++#define RG_FMT_DET_MM_TH_MSK 0x000000ff
++#define RG_FMT_DET_MM_TH_I_MSK 0xffffff00
++#define RG_FMT_DET_MM_TH_SFT 0
++#define RG_FMT_DET_MM_TH_HI 7
++#define RG_FMT_DET_MM_TH_SZ 8
++#define RG_FMT_DET_GF_TH_MSK 0x0000ff00
++#define RG_FMT_DET_GF_TH_I_MSK 0xffff00ff
++#define RG_FMT_DET_GF_TH_SFT 8
++#define RG_FMT_DET_GF_TH_HI 15
++#define RG_FMT_DET_GF_TH_SZ 8
++#define RG_DO_NOT_CHECK_L_RATE_MSK 0x02000000
++#define RG_DO_NOT_CHECK_L_RATE_I_MSK 0xfdffffff
++#define RG_DO_NOT_CHECK_L_RATE_SFT 25
++#define RG_DO_NOT_CHECK_L_RATE_HI 25
++#define RG_DO_NOT_CHECK_L_RATE_SZ 1
++#define RG_FMT_DET_LENGTH_TH_MSK 0x0000ffff
++#define RG_FMT_DET_LENGTH_TH_I_MSK 0xffff0000
++#define RG_FMT_DET_LENGTH_TH_SFT 0
++#define RG_FMT_DET_LENGTH_TH_HI 15
++#define RG_FMT_DET_LENGTH_TH_SZ 16
++#define RG_L_LENGTH_MAX_MSK 0xffff0000
++#define RG_L_LENGTH_MAX_I_MSK 0x0000ffff
++#define RG_L_LENGTH_MAX_SFT 16
++#define RG_L_LENGTH_MAX_HI 31
++#define RG_L_LENGTH_MAX_SZ 16
++#define RG_TX_TIME_EXT_MSK 0x000000ff
++#define RG_TX_TIME_EXT_I_MSK 0xffffff00
++#define RG_TX_TIME_EXT_SFT 0
++#define RG_TX_TIME_EXT_HI 7
++#define RG_TX_TIME_EXT_SZ 8
++#define RG_MAC_DES_SPACE_MSK 0x00f00000
++#define RG_MAC_DES_SPACE_I_MSK 0xff0fffff
++#define RG_MAC_DES_SPACE_SFT 20
++#define RG_MAC_DES_SPACE_HI 23
++#define RG_MAC_DES_SPACE_SZ 4
++#define RG_TR_LPF_STBC_GF_KI_G_MSK 0x0000000f
++#define RG_TR_LPF_STBC_GF_KI_G_I_MSK 0xfffffff0
++#define RG_TR_LPF_STBC_GF_KI_G_SFT 0
++#define RG_TR_LPF_STBC_GF_KI_G_HI 3
++#define RG_TR_LPF_STBC_GF_KI_G_SZ 4
++#define RG_TR_LPF_STBC_GF_KP_G_MSK 0x000000f0
++#define RG_TR_LPF_STBC_GF_KP_G_I_MSK 0xffffff0f
++#define RG_TR_LPF_STBC_GF_KP_G_SFT 4
++#define RG_TR_LPF_STBC_GF_KP_G_HI 7
++#define RG_TR_LPF_STBC_GF_KP_G_SZ 4
++#define RG_TR_LPF_STBC_MF_KI_G_MSK 0x00000f00
++#define RG_TR_LPF_STBC_MF_KI_G_I_MSK 0xfffff0ff
++#define RG_TR_LPF_STBC_MF_KI_G_SFT 8
++#define RG_TR_LPF_STBC_MF_KI_G_HI 11
++#define RG_TR_LPF_STBC_MF_KI_G_SZ 4
++#define RG_TR_LPF_STBC_MF_KP_G_MSK 0x0000f000
++#define RG_TR_LPF_STBC_MF_KP_G_I_MSK 0xffff0fff
++#define RG_TR_LPF_STBC_MF_KP_G_SFT 12
++#define RG_TR_LPF_STBC_MF_KP_G_HI 15
++#define RG_TR_LPF_STBC_MF_KP_G_SZ 4
++#define RG_MODE_REG_IN_80_MSK 0x0001ffff
++#define RG_MODE_REG_IN_80_I_MSK 0xfffe0000
++#define RG_MODE_REG_IN_80_SFT 0
++#define RG_MODE_REG_IN_80_HI 16
++#define RG_MODE_REG_IN_80_SZ 17
++#define RG_PARALLEL_DR_80_MSK 0x00100000
++#define RG_PARALLEL_DR_80_I_MSK 0xffefffff
++#define RG_PARALLEL_DR_80_SFT 20
++#define RG_PARALLEL_DR_80_HI 20
++#define RG_PARALLEL_DR_80_SZ 1
++#define RG_MBRUN_80_MSK 0x01000000
++#define RG_MBRUN_80_I_MSK 0xfeffffff
++#define RG_MBRUN_80_SFT 24
++#define RG_MBRUN_80_HI 24
++#define RG_MBRUN_80_SZ 1
++#define RG_SHIFT_DR_80_MSK 0x10000000
++#define RG_SHIFT_DR_80_I_MSK 0xefffffff
++#define RG_SHIFT_DR_80_SFT 28
++#define RG_SHIFT_DR_80_HI 28
++#define RG_SHIFT_DR_80_SZ 1
++#define RG_MODE_REG_SI_80_MSK 0x20000000
++#define RG_MODE_REG_SI_80_I_MSK 0xdfffffff
++#define RG_MODE_REG_SI_80_SFT 29
++#define RG_MODE_REG_SI_80_HI 29
++#define RG_MODE_REG_SI_80_SZ 1
++#define RG_SIMULATION_MODE_80_MSK 0x40000000
++#define RG_SIMULATION_MODE_80_I_MSK 0xbfffffff
++#define RG_SIMULATION_MODE_80_SFT 30
++#define RG_SIMULATION_MODE_80_HI 30
++#define RG_SIMULATION_MODE_80_SZ 1
++#define RG_DBIST_MODE_80_MSK 0x80000000
++#define RG_DBIST_MODE_80_I_MSK 0x7fffffff
++#define RG_DBIST_MODE_80_SFT 31
++#define RG_DBIST_MODE_80_HI 31
++#define RG_DBIST_MODE_80_SZ 1
++#define RG_MODE_REG_IN_64_MSK 0x0000ffff
++#define RG_MODE_REG_IN_64_I_MSK 0xffff0000
++#define RG_MODE_REG_IN_64_SFT 0
++#define RG_MODE_REG_IN_64_HI 15
++#define RG_MODE_REG_IN_64_SZ 16
++#define RG_PARALLEL_DR_64_MSK 0x00100000
++#define RG_PARALLEL_DR_64_I_MSK 0xffefffff
++#define RG_PARALLEL_DR_64_SFT 20
++#define RG_PARALLEL_DR_64_HI 20
++#define RG_PARALLEL_DR_64_SZ 1
++#define RG_MBRUN_64_MSK 0x01000000
++#define RG_MBRUN_64_I_MSK 0xfeffffff
++#define RG_MBRUN_64_SFT 24
++#define RG_MBRUN_64_HI 24
++#define RG_MBRUN_64_SZ 1
++#define RG_SHIFT_DR_64_MSK 0x10000000
++#define RG_SHIFT_DR_64_I_MSK 0xefffffff
++#define RG_SHIFT_DR_64_SFT 28
++#define RG_SHIFT_DR_64_HI 28
++#define RG_SHIFT_DR_64_SZ 1
++#define RG_MODE_REG_SI_64_MSK 0x20000000
++#define RG_MODE_REG_SI_64_I_MSK 0xdfffffff
++#define RG_MODE_REG_SI_64_SFT 29
++#define RG_MODE_REG_SI_64_HI 29
++#define RG_MODE_REG_SI_64_SZ 1
++#define RG_SIMULATION_MODE_64_MSK 0x40000000
++#define RG_SIMULATION_MODE_64_I_MSK 0xbfffffff
++#define RG_SIMULATION_MODE_64_SFT 30
++#define RG_SIMULATION_MODE_64_HI 30
++#define RG_SIMULATION_MODE_64_SZ 1
++#define RG_DBIST_MODE_64_MSK 0x80000000
++#define RG_DBIST_MODE_64_I_MSK 0x7fffffff
++#define RG_DBIST_MODE_64_SFT 31
++#define RG_DBIST_MODE_64_HI 31
++#define RG_DBIST_MODE_64_SZ 1
++#define RO_MODE_REG_OUT_80_MSK 0x0001ffff
++#define RO_MODE_REG_OUT_80_I_MSK 0xfffe0000
++#define RO_MODE_REG_OUT_80_SFT 0
++#define RO_MODE_REG_OUT_80_HI 16
++#define RO_MODE_REG_OUT_80_SZ 17
++#define RO_MODE_REG_SO_80_MSK 0x01000000
++#define RO_MODE_REG_SO_80_I_MSK 0xfeffffff
++#define RO_MODE_REG_SO_80_SFT 24
++#define RO_MODE_REG_SO_80_HI 24
++#define RO_MODE_REG_SO_80_SZ 1
++#define RO_MONITOR_BUS_80_MSK 0x003fffff
++#define RO_MONITOR_BUS_80_I_MSK 0xffc00000
++#define RO_MONITOR_BUS_80_SFT 0
++#define RO_MONITOR_BUS_80_HI 21
++#define RO_MONITOR_BUS_80_SZ 22
++#define RO_MODE_REG_OUT_64_MSK 0x0000ffff
++#define RO_MODE_REG_OUT_64_I_MSK 0xffff0000
++#define RO_MODE_REG_OUT_64_SFT 0
++#define RO_MODE_REG_OUT_64_HI 15
++#define RO_MODE_REG_OUT_64_SZ 16
++#define RO_MODE_REG_SO_64_MSK 0x01000000
++#define RO_MODE_REG_SO_64_I_MSK 0xfeffffff
++#define RO_MODE_REG_SO_64_SFT 24
++#define RO_MODE_REG_SO_64_HI 24
++#define RO_MODE_REG_SO_64_SZ 1
++#define RO_MONITOR_BUS_64_MSK 0x0007ffff
++#define RO_MONITOR_BUS_64_I_MSK 0xfff80000
++#define RO_MONITOR_BUS_64_SFT 0
++#define RO_MONITOR_BUS_64_HI 18
++#define RO_MONITOR_BUS_64_SZ 19
++#define RO_SPECTRUM_DATA_MSK 0xffffffff
++#define RO_SPECTRUM_DATA_I_MSK 0x00000000
++#define RO_SPECTRUM_DATA_SFT 0
++#define RO_SPECTRUM_DATA_HI 31
++#define RO_SPECTRUM_DATA_SZ 32
++#define GN_SNR_MSK 0x0000007f
++#define GN_SNR_I_MSK 0xffffff80
++#define GN_SNR_SFT 0
++#define GN_SNR_HI 6
++#define GN_SNR_SZ 7
++#define GN_NOISE_PWR_MSK 0x00007f00
++#define GN_NOISE_PWR_I_MSK 0xffff80ff
++#define GN_NOISE_PWR_SFT 8
++#define GN_NOISE_PWR_HI 14
++#define GN_NOISE_PWR_SZ 7
++#define GN_RCPI_MSK 0x007f0000
++#define GN_RCPI_I_MSK 0xff80ffff
++#define GN_RCPI_SFT 16
++#define GN_RCPI_HI 22
++#define GN_RCPI_SZ 7
++#define GN_SIGNAL_PWR_MSK 0x7f000000
++#define GN_SIGNAL_PWR_I_MSK 0x80ffffff
++#define GN_SIGNAL_PWR_SFT 24
++#define GN_SIGNAL_PWR_HI 30
++#define GN_SIGNAL_PWR_SZ 7
++#define RO_FREQ_OS_LTS_MSK 0x00007fff
++#define RO_FREQ_OS_LTS_I_MSK 0xffff8000
++#define RO_FREQ_OS_LTS_SFT 0
++#define RO_FREQ_OS_LTS_HI 14
++#define RO_FREQ_OS_LTS_SZ 15
++#define CSTATE_MSK 0x000f0000
++#define CSTATE_I_MSK 0xfff0ffff
++#define CSTATE_SFT 16
++#define CSTATE_HI 19
++#define CSTATE_SZ 4
++#define SIGNAL_FIELD0_MSK 0x00ffffff
++#define SIGNAL_FIELD0_I_MSK 0xff000000
++#define SIGNAL_FIELD0_SFT 0
++#define SIGNAL_FIELD0_HI 23
++#define SIGNAL_FIELD0_SZ 24
++#define SIGNAL_FIELD1_MSK 0x00ffffff
++#define SIGNAL_FIELD1_I_MSK 0xff000000
++#define SIGNAL_FIELD1_SFT 0
++#define SIGNAL_FIELD1_HI 23
++#define SIGNAL_FIELD1_SZ 24
++#define GN_PACKET_ERR_CNT_MSK 0x0000ffff
++#define GN_PACKET_ERR_CNT_I_MSK 0xffff0000
++#define GN_PACKET_ERR_CNT_SFT 0
++#define GN_PACKET_ERR_CNT_HI 15
++#define GN_PACKET_ERR_CNT_SZ 16
++#define GN_PACKET_CNT_MSK 0x0000ffff
++#define GN_PACKET_CNT_I_MSK 0xffff0000
++#define GN_PACKET_CNT_SFT 0
++#define GN_PACKET_CNT_HI 15
++#define GN_PACKET_CNT_SZ 16
++#define GN_CCA_CNT_MSK 0xffff0000
++#define GN_CCA_CNT_I_MSK 0x0000ffff
++#define GN_CCA_CNT_SFT 16
++#define GN_CCA_CNT_HI 31
++#define GN_CCA_CNT_SZ 16
++#define GN_LENGTH_FIELD_MSK 0x0000ffff
++#define GN_LENGTH_FIELD_I_MSK 0xffff0000
++#define GN_LENGTH_FIELD_SFT 0
++#define GN_LENGTH_FIELD_HI 15
++#define GN_LENGTH_FIELD_SZ 16
++#define GN_SERVICE_FIELD_MSK 0xffff0000
++#define GN_SERVICE_FIELD_I_MSK 0x0000ffff
++#define GN_SERVICE_FIELD_SFT 16
++#define GN_SERVICE_FIELD_HI 31
++#define GN_SERVICE_FIELD_SZ 16
++#define RO_HT_MCS_40M_MSK 0x0000007f
++#define RO_HT_MCS_40M_I_MSK 0xffffff80
++#define RO_HT_MCS_40M_SFT 0
++#define RO_HT_MCS_40M_HI 6
++#define RO_HT_MCS_40M_SZ 7
++#define RO_L_RATE_40M_MSK 0x00003f00
++#define RO_L_RATE_40M_I_MSK 0xffffc0ff
++#define RO_L_RATE_40M_SFT 8
++#define RO_L_RATE_40M_HI 13
++#define RO_L_RATE_40M_SZ 6
++#define RG_DAGC_CNT_TH_MSK 0x00000003
++#define RG_DAGC_CNT_TH_I_MSK 0xfffffffc
++#define RG_DAGC_CNT_TH_SFT 0
++#define RG_DAGC_CNT_TH_HI 1
++#define RG_DAGC_CNT_TH_SZ 2
++#define RG_PACKET_STAT_EN_11GN_MSK 0x00100000
++#define RG_PACKET_STAT_EN_11GN_I_MSK 0xffefffff
++#define RG_PACKET_STAT_EN_11GN_SFT 20
++#define RG_PACKET_STAT_EN_11GN_HI 20
++#define RG_PACKET_STAT_EN_11GN_SZ 1
++#define RX_PHY_11GN_SOFT_RST_N_MSK 0x00000001
++#define RX_PHY_11GN_SOFT_RST_N_I_MSK 0xfffffffe
++#define RX_PHY_11GN_SOFT_RST_N_SFT 0
++#define RX_PHY_11GN_SOFT_RST_N_HI 0
++#define RX_PHY_11GN_SOFT_RST_N_SZ 1
++#define RG_RIFS_EN_MSK 0x00000002
++#define RG_RIFS_EN_I_MSK 0xfffffffd
++#define RG_RIFS_EN_SFT 1
++#define RG_RIFS_EN_HI 1
++#define RG_RIFS_EN_SZ 1
++#define RG_STBC_EN_MSK 0x00000004
++#define RG_STBC_EN_I_MSK 0xfffffffb
++#define RG_STBC_EN_SFT 2
++#define RG_STBC_EN_HI 2
++#define RG_STBC_EN_SZ 1
++#define RG_COR_SEL_MSK 0x00000008
++#define RG_COR_SEL_I_MSK 0xfffffff7
++#define RG_COR_SEL_SFT 3
++#define RG_COR_SEL_HI 3
++#define RG_COR_SEL_SZ 1
++#define RG_INI_PHASE_MSK 0x00000030
++#define RG_INI_PHASE_I_MSK 0xffffffcf
++#define RG_INI_PHASE_SFT 4
++#define RG_INI_PHASE_HI 5
++#define RG_INI_PHASE_SZ 2
++#define RG_HT_LTF_SEL_EQ_MSK 0x00000040
++#define RG_HT_LTF_SEL_EQ_I_MSK 0xffffffbf
++#define RG_HT_LTF_SEL_EQ_SFT 6
++#define RG_HT_LTF_SEL_EQ_HI 6
++#define RG_HT_LTF_SEL_EQ_SZ 1
++#define RG_HT_LTF_SEL_PILOT_MSK 0x00000080
++#define RG_HT_LTF_SEL_PILOT_I_MSK 0xffffff7f
++#define RG_HT_LTF_SEL_PILOT_SFT 7
++#define RG_HT_LTF_SEL_PILOT_HI 7
++#define RG_HT_LTF_SEL_PILOT_SZ 1
++#define RG_CCA_PWR_SEL_MSK 0x00000200
++#define RG_CCA_PWR_SEL_I_MSK 0xfffffdff
++#define RG_CCA_PWR_SEL_SFT 9
++#define RG_CCA_PWR_SEL_HI 9
++#define RG_CCA_PWR_SEL_SZ 1
++#define RG_CCA_XSCOR_PWR_SEL_MSK 0x00000400
++#define RG_CCA_XSCOR_PWR_SEL_I_MSK 0xfffffbff
++#define RG_CCA_XSCOR_PWR_SEL_SFT 10
++#define RG_CCA_XSCOR_PWR_SEL_HI 10
++#define RG_CCA_XSCOR_PWR_SEL_SZ 1
++#define RG_CCA_XSCOR_AVGPWR_SEL_MSK 0x00000800
++#define RG_CCA_XSCOR_AVGPWR_SEL_I_MSK 0xfffff7ff
++#define RG_CCA_XSCOR_AVGPWR_SEL_SFT 11
++#define RG_CCA_XSCOR_AVGPWR_SEL_HI 11
++#define RG_CCA_XSCOR_AVGPWR_SEL_SZ 1
++#define RG_DEBUG_SEL_MSK 0x0000f000
++#define RG_DEBUG_SEL_I_MSK 0xffff0fff
++#define RG_DEBUG_SEL_SFT 12
++#define RG_DEBUG_SEL_HI 15
++#define RG_DEBUG_SEL_SZ 4
++#define RG_POST_CLK_EN_MSK 0x00010000
++#define RG_POST_CLK_EN_I_MSK 0xfffeffff
++#define RG_POST_CLK_EN_SFT 16
++#define RG_POST_CLK_EN_HI 16
++#define RG_POST_CLK_EN_SZ 1
++#define IQCAL_RF_TX_EN_MSK 0x00000001
++#define IQCAL_RF_TX_EN_I_MSK 0xfffffffe
++#define IQCAL_RF_TX_EN_SFT 0
++#define IQCAL_RF_TX_EN_HI 0
++#define IQCAL_RF_TX_EN_SZ 1
++#define IQCAL_RF_TX_PA_EN_MSK 0x00000002
++#define IQCAL_RF_TX_PA_EN_I_MSK 0xfffffffd
++#define IQCAL_RF_TX_PA_EN_SFT 1
++#define IQCAL_RF_TX_PA_EN_HI 1
++#define IQCAL_RF_TX_PA_EN_SZ 1
++#define IQCAL_RF_TX_DAC_EN_MSK 0x00000004
++#define IQCAL_RF_TX_DAC_EN_I_MSK 0xfffffffb
++#define IQCAL_RF_TX_DAC_EN_SFT 2
++#define IQCAL_RF_TX_DAC_EN_HI 2
++#define IQCAL_RF_TX_DAC_EN_SZ 1
++#define IQCAL_RF_RX_AGC_MSK 0x00000008
++#define IQCAL_RF_RX_AGC_I_MSK 0xfffffff7
++#define IQCAL_RF_RX_AGC_SFT 3
++#define IQCAL_RF_RX_AGC_HI 3
++#define IQCAL_RF_RX_AGC_SZ 1
++#define IQCAL_RF_PGAG_MSK 0x00000f00
++#define IQCAL_RF_PGAG_I_MSK 0xfffff0ff
++#define IQCAL_RF_PGAG_SFT 8
++#define IQCAL_RF_PGAG_HI 11
++#define IQCAL_RF_PGAG_SZ 4
++#define IQCAL_RF_RFG_MSK 0x00003000
++#define IQCAL_RF_RFG_I_MSK 0xffffcfff
++#define IQCAL_RF_RFG_SFT 12
++#define IQCAL_RF_RFG_HI 13
++#define IQCAL_RF_RFG_SZ 2
++#define RG_TONEGEN_FREQ_MSK 0x007f0000
++#define RG_TONEGEN_FREQ_I_MSK 0xff80ffff
++#define RG_TONEGEN_FREQ_SFT 16
++#define RG_TONEGEN_FREQ_HI 22
++#define RG_TONEGEN_FREQ_SZ 7
++#define RG_TONEGEN_EN_MSK 0x00800000
++#define RG_TONEGEN_EN_I_MSK 0xff7fffff
++#define RG_TONEGEN_EN_SFT 23
++#define RG_TONEGEN_EN_HI 23
++#define RG_TONEGEN_EN_SZ 1
++#define RG_TONEGEN_INIT_PH_MSK 0x7f000000
++#define RG_TONEGEN_INIT_PH_I_MSK 0x80ffffff
++#define RG_TONEGEN_INIT_PH_SFT 24
++#define RG_TONEGEN_INIT_PH_HI 30
++#define RG_TONEGEN_INIT_PH_SZ 7
++#define RG_TONEGEN2_FREQ_MSK 0x0000007f
++#define RG_TONEGEN2_FREQ_I_MSK 0xffffff80
++#define RG_TONEGEN2_FREQ_SFT 0
++#define RG_TONEGEN2_FREQ_HI 6
++#define RG_TONEGEN2_FREQ_SZ 7
++#define RG_TONEGEN2_EN_MSK 0x00000080
++#define RG_TONEGEN2_EN_I_MSK 0xffffff7f
++#define RG_TONEGEN2_EN_SFT 7
++#define RG_TONEGEN2_EN_HI 7
++#define RG_TONEGEN2_EN_SZ 1
++#define RG_TONEGEN2_SCALE_MSK 0x0000ff00
++#define RG_TONEGEN2_SCALE_I_MSK 0xffff00ff
++#define RG_TONEGEN2_SCALE_SFT 8
++#define RG_TONEGEN2_SCALE_HI 15
++#define RG_TONEGEN2_SCALE_SZ 8
++#define RG_TXIQ_CLP_THD_I_MSK 0x000003ff
++#define RG_TXIQ_CLP_THD_I_I_MSK 0xfffffc00
++#define RG_TXIQ_CLP_THD_I_SFT 0
++#define RG_TXIQ_CLP_THD_I_HI 9
++#define RG_TXIQ_CLP_THD_I_SZ 10
++#define RG_TXIQ_CLP_THD_Q_MSK 0x03ff0000
++#define RG_TXIQ_CLP_THD_Q_I_MSK 0xfc00ffff
++#define RG_TXIQ_CLP_THD_Q_SFT 16
++#define RG_TXIQ_CLP_THD_Q_HI 25
++#define RG_TXIQ_CLP_THD_Q_SZ 10
++#define RG_TX_I_SCALE_MSK 0x000000ff
++#define RG_TX_I_SCALE_I_MSK 0xffffff00
++#define RG_TX_I_SCALE_SFT 0
++#define RG_TX_I_SCALE_HI 7
++#define RG_TX_I_SCALE_SZ 8
++#define RG_TX_Q_SCALE_MSK 0x0000ff00
++#define RG_TX_Q_SCALE_I_MSK 0xffff00ff
++#define RG_TX_Q_SCALE_SFT 8
++#define RG_TX_Q_SCALE_HI 15
++#define RG_TX_Q_SCALE_SZ 8
++#define RG_TX_IQ_SWP_MSK 0x00010000
++#define RG_TX_IQ_SWP_I_MSK 0xfffeffff
++#define RG_TX_IQ_SWP_SFT 16
++#define RG_TX_IQ_SWP_HI 16
++#define RG_TX_IQ_SWP_SZ 1
++#define RG_TX_SGN_OUT_MSK 0x00020000
++#define RG_TX_SGN_OUT_I_MSK 0xfffdffff
++#define RG_TX_SGN_OUT_SFT 17
++#define RG_TX_SGN_OUT_HI 17
++#define RG_TX_SGN_OUT_SZ 1
++#define RG_TXIQ_EMU_IDX_MSK 0x003c0000
++#define RG_TXIQ_EMU_IDX_I_MSK 0xffc3ffff
++#define RG_TXIQ_EMU_IDX_SFT 18
++#define RG_TXIQ_EMU_IDX_HI 21
++#define RG_TXIQ_EMU_IDX_SZ 4
++#define RG_TX_IQ_SRC_MSK 0x03000000
++#define RG_TX_IQ_SRC_I_MSK 0xfcffffff
++#define RG_TX_IQ_SRC_SFT 24
++#define RG_TX_IQ_SRC_HI 25
++#define RG_TX_IQ_SRC_SZ 2
++#define RG_TX_I_DC_MSK 0x000003ff
++#define RG_TX_I_DC_I_MSK 0xfffffc00
++#define RG_TX_I_DC_SFT 0
++#define RG_TX_I_DC_HI 9
++#define RG_TX_I_DC_SZ 10
++#define RG_TX_Q_DC_MSK 0x03ff0000
++#define RG_TX_Q_DC_I_MSK 0xfc00ffff
++#define RG_TX_Q_DC_SFT 16
++#define RG_TX_Q_DC_HI 25
++#define RG_TX_Q_DC_SZ 10
++#define RG_TX_IQ_THETA_MSK 0x0000001f
++#define RG_TX_IQ_THETA_I_MSK 0xffffffe0
++#define RG_TX_IQ_THETA_SFT 0
++#define RG_TX_IQ_THETA_HI 4
++#define RG_TX_IQ_THETA_SZ 5
++#define RG_TX_IQ_ALPHA_MSK 0x00001f00
++#define RG_TX_IQ_ALPHA_I_MSK 0xffffe0ff
++#define RG_TX_IQ_ALPHA_SFT 8
++#define RG_TX_IQ_ALPHA_HI 12
++#define RG_TX_IQ_ALPHA_SZ 5
++#define RG_TXIQ_NOSHRINK_MSK 0x00002000
++#define RG_TXIQ_NOSHRINK_I_MSK 0xffffdfff
++#define RG_TXIQ_NOSHRINK_SFT 13
++#define RG_TXIQ_NOSHRINK_HI 13
++#define RG_TXIQ_NOSHRINK_SZ 1
++#define RG_TX_I_OFFSET_MSK 0x00ff0000
++#define RG_TX_I_OFFSET_I_MSK 0xff00ffff
++#define RG_TX_I_OFFSET_SFT 16
++#define RG_TX_I_OFFSET_HI 23
++#define RG_TX_I_OFFSET_SZ 8
++#define RG_TX_Q_OFFSET_MSK 0xff000000
++#define RG_TX_Q_OFFSET_I_MSK 0x00ffffff
++#define RG_TX_Q_OFFSET_SFT 24
++#define RG_TX_Q_OFFSET_HI 31
++#define RG_TX_Q_OFFSET_SZ 8
++#define RG_RX_IQ_THETA_MSK 0x0000001f
++#define RG_RX_IQ_THETA_I_MSK 0xffffffe0
++#define RG_RX_IQ_THETA_SFT 0
++#define RG_RX_IQ_THETA_HI 4
++#define RG_RX_IQ_THETA_SZ 5
++#define RG_RX_IQ_ALPHA_MSK 0x00001f00
++#define RG_RX_IQ_ALPHA_I_MSK 0xffffe0ff
++#define RG_RX_IQ_ALPHA_SFT 8
++#define RG_RX_IQ_ALPHA_HI 12
++#define RG_RX_IQ_ALPHA_SZ 5
++#define RG_RXIQ_NOSHRINK_MSK 0x00002000
++#define RG_RXIQ_NOSHRINK_I_MSK 0xffffdfff
++#define RG_RXIQ_NOSHRINK_SFT 13
++#define RG_RXIQ_NOSHRINK_HI 13
++#define RG_RXIQ_NOSHRINK_SZ 1
++#define RG_MA_DPTH_MSK 0x0000000f
++#define RG_MA_DPTH_I_MSK 0xfffffff0
++#define RG_MA_DPTH_SFT 0
++#define RG_MA_DPTH_HI 3
++#define RG_MA_DPTH_SZ 4
++#define RG_INTG_PH_MSK 0x000003f0
++#define RG_INTG_PH_I_MSK 0xfffffc0f
++#define RG_INTG_PH_SFT 4
++#define RG_INTG_PH_HI 9
++#define RG_INTG_PH_SZ 6
++#define RG_INTG_PRD_MSK 0x00001c00
++#define RG_INTG_PRD_I_MSK 0xffffe3ff
++#define RG_INTG_PRD_SFT 10
++#define RG_INTG_PRD_HI 12
++#define RG_INTG_PRD_SZ 3
++#define RG_INTG_MU_MSK 0x00006000
++#define RG_INTG_MU_I_MSK 0xffff9fff
++#define RG_INTG_MU_SFT 13
++#define RG_INTG_MU_HI 14
++#define RG_INTG_MU_SZ 2
++#define RG_IQCAL_SPRM_SELQ_MSK 0x00010000
++#define RG_IQCAL_SPRM_SELQ_I_MSK 0xfffeffff
++#define RG_IQCAL_SPRM_SELQ_SFT 16
++#define RG_IQCAL_SPRM_SELQ_HI 16
++#define RG_IQCAL_SPRM_SELQ_SZ 1
++#define RG_IQCAL_SPRM_EN_MSK 0x00020000
++#define RG_IQCAL_SPRM_EN_I_MSK 0xfffdffff
++#define RG_IQCAL_SPRM_EN_SFT 17
++#define RG_IQCAL_SPRM_EN_HI 17
++#define RG_IQCAL_SPRM_EN_SZ 1
++#define RG_IQCAL_SPRM_FREQ_MSK 0x00fc0000
++#define RG_IQCAL_SPRM_FREQ_I_MSK 0xff03ffff
++#define RG_IQCAL_SPRM_FREQ_SFT 18
++#define RG_IQCAL_SPRM_FREQ_HI 23
++#define RG_IQCAL_SPRM_FREQ_SZ 6
++#define RG_IQCAL_IQCOL_EN_MSK 0x01000000
++#define RG_IQCAL_IQCOL_EN_I_MSK 0xfeffffff
++#define RG_IQCAL_IQCOL_EN_SFT 24
++#define RG_IQCAL_IQCOL_EN_HI 24
++#define RG_IQCAL_IQCOL_EN_SZ 1
++#define RG_IQCAL_ALPHA_ESTM_EN_MSK 0x02000000
++#define RG_IQCAL_ALPHA_ESTM_EN_I_MSK 0xfdffffff
++#define RG_IQCAL_ALPHA_ESTM_EN_SFT 25
++#define RG_IQCAL_ALPHA_ESTM_EN_HI 25
++#define RG_IQCAL_ALPHA_ESTM_EN_SZ 1
++#define RG_IQCAL_DC_EN_MSK 0x04000000
++#define RG_IQCAL_DC_EN_I_MSK 0xfbffffff
++#define RG_IQCAL_DC_EN_SFT 26
++#define RG_IQCAL_DC_EN_HI 26
++#define RG_IQCAL_DC_EN_SZ 1
++#define RG_PHEST_STBY_MSK 0x08000000
++#define RG_PHEST_STBY_I_MSK 0xf7ffffff
++#define RG_PHEST_STBY_SFT 27
++#define RG_PHEST_STBY_HI 27
++#define RG_PHEST_STBY_SZ 1
++#define RG_PHEST_EN_MSK 0x10000000
++#define RG_PHEST_EN_I_MSK 0xefffffff
++#define RG_PHEST_EN_SFT 28
++#define RG_PHEST_EN_HI 28
++#define RG_PHEST_EN_SZ 1
++#define RG_GP_DIV_EN_MSK 0x20000000
++#define RG_GP_DIV_EN_I_MSK 0xdfffffff
++#define RG_GP_DIV_EN_SFT 29
++#define RG_GP_DIV_EN_HI 29
++#define RG_GP_DIV_EN_SZ 1
++#define RG_DPD_GAIN_EST_EN_MSK 0x40000000
++#define RG_DPD_GAIN_EST_EN_I_MSK 0xbfffffff
++#define RG_DPD_GAIN_EST_EN_SFT 30
++#define RG_DPD_GAIN_EST_EN_HI 30
++#define RG_DPD_GAIN_EST_EN_SZ 1
++#define RG_IQCAL_MULT_OP0_MSK 0x000003ff
++#define RG_IQCAL_MULT_OP0_I_MSK 0xfffffc00
++#define RG_IQCAL_MULT_OP0_SFT 0
++#define RG_IQCAL_MULT_OP0_HI 9
++#define RG_IQCAL_MULT_OP0_SZ 10
++#define RG_IQCAL_MULT_OP1_MSK 0x03ff0000
++#define RG_IQCAL_MULT_OP1_I_MSK 0xfc00ffff
++#define RG_IQCAL_MULT_OP1_SFT 16
++#define RG_IQCAL_MULT_OP1_HI 25
++#define RG_IQCAL_MULT_OP1_SZ 10
++#define RO_IQCAL_O_MSK 0x000fffff
++#define RO_IQCAL_O_I_MSK 0xfff00000
++#define RO_IQCAL_O_SFT 0
++#define RO_IQCAL_O_HI 19
++#define RO_IQCAL_O_SZ 20
++#define RO_IQCAL_SPRM_RDY_MSK 0x00100000
++#define RO_IQCAL_SPRM_RDY_I_MSK 0xffefffff
++#define RO_IQCAL_SPRM_RDY_SFT 20
++#define RO_IQCAL_SPRM_RDY_HI 20
++#define RO_IQCAL_SPRM_RDY_SZ 1
++#define RO_IQCAL_IQCOL_RDY_MSK 0x00200000
++#define RO_IQCAL_IQCOL_RDY_I_MSK 0xffdfffff
++#define RO_IQCAL_IQCOL_RDY_SFT 21
++#define RO_IQCAL_IQCOL_RDY_HI 21
++#define RO_IQCAL_IQCOL_RDY_SZ 1
++#define RO_IQCAL_ALPHA_ESTM_RDY_MSK 0x00400000
++#define RO_IQCAL_ALPHA_ESTM_RDY_I_MSK 0xffbfffff
++#define RO_IQCAL_ALPHA_ESTM_RDY_SFT 22
++#define RO_IQCAL_ALPHA_ESTM_RDY_HI 22
++#define RO_IQCAL_ALPHA_ESTM_RDY_SZ 1
++#define RO_IQCAL_DC_RDY_MSK 0x00800000
++#define RO_IQCAL_DC_RDY_I_MSK 0xff7fffff
++#define RO_IQCAL_DC_RDY_SFT 23
++#define RO_IQCAL_DC_RDY_HI 23
++#define RO_IQCAL_DC_RDY_SZ 1
++#define RO_IQCAL_MULT_RDY_MSK 0x01000000
++#define RO_IQCAL_MULT_RDY_I_MSK 0xfeffffff
++#define RO_IQCAL_MULT_RDY_SFT 24
++#define RO_IQCAL_MULT_RDY_HI 24
++#define RO_IQCAL_MULT_RDY_SZ 1
++#define RO_FFT_ENRG_RDY_MSK 0x02000000
++#define RO_FFT_ENRG_RDY_I_MSK 0xfdffffff
++#define RO_FFT_ENRG_RDY_SFT 25
++#define RO_FFT_ENRG_RDY_HI 25
++#define RO_FFT_ENRG_RDY_SZ 1
++#define RO_PHEST_RDY_MSK 0x04000000
++#define RO_PHEST_RDY_I_MSK 0xfbffffff
++#define RO_PHEST_RDY_SFT 26
++#define RO_PHEST_RDY_HI 26
++#define RO_PHEST_RDY_SZ 1
++#define RO_GP_DIV_RDY_MSK 0x08000000
++#define RO_GP_DIV_RDY_I_MSK 0xf7ffffff
++#define RO_GP_DIV_RDY_SFT 27
++#define RO_GP_DIV_RDY_HI 27
++#define RO_GP_DIV_RDY_SZ 1
++#define RO_GAIN_EST_RDY_MSK 0x10000000
++#define RO_GAIN_EST_RDY_I_MSK 0xefffffff
++#define RO_GAIN_EST_RDY_SFT 28
++#define RO_GAIN_EST_RDY_HI 28
++#define RO_GAIN_EST_RDY_SZ 1
++#define RO_AMP_O_MSK 0x000001ff
++#define RO_AMP_O_I_MSK 0xfffffe00
++#define RO_AMP_O_SFT 0
++#define RO_AMP_O_HI 8
++#define RO_AMP_O_SZ 9
++#define RG_RX_I_SCALE_MSK 0x000000ff
++#define RG_RX_I_SCALE_I_MSK 0xffffff00
++#define RG_RX_I_SCALE_SFT 0
++#define RG_RX_I_SCALE_HI 7
++#define RG_RX_I_SCALE_SZ 8
++#define RG_RX_Q_SCALE_MSK 0x0000ff00
++#define RG_RX_Q_SCALE_I_MSK 0xffff00ff
++#define RG_RX_Q_SCALE_SFT 8
++#define RG_RX_Q_SCALE_HI 15
++#define RG_RX_Q_SCALE_SZ 8
++#define RG_RX_I_OFFSET_MSK 0x00ff0000
++#define RG_RX_I_OFFSET_I_MSK 0xff00ffff
++#define RG_RX_I_OFFSET_SFT 16
++#define RG_RX_I_OFFSET_HI 23
++#define RG_RX_I_OFFSET_SZ 8
++#define RG_RX_Q_OFFSET_MSK 0xff000000
++#define RG_RX_Q_OFFSET_I_MSK 0x00ffffff
++#define RG_RX_Q_OFFSET_SFT 24
++#define RG_RX_Q_OFFSET_HI 31
++#define RG_RX_Q_OFFSET_SZ 8
++#define RG_RX_IQ_SWP_MSK 0x00000001
++#define RG_RX_IQ_SWP_I_MSK 0xfffffffe
++#define RG_RX_IQ_SWP_SFT 0
++#define RG_RX_IQ_SWP_HI 0
++#define RG_RX_IQ_SWP_SZ 1
++#define RG_RX_SGN_IN_MSK 0x00000002
++#define RG_RX_SGN_IN_I_MSK 0xfffffffd
++#define RG_RX_SGN_IN_SFT 1
++#define RG_RX_SGN_IN_HI 1
++#define RG_RX_SGN_IN_SZ 1
++#define RG_RX_IQ_SRC_MSK 0x0000000c
++#define RG_RX_IQ_SRC_I_MSK 0xfffffff3
++#define RG_RX_IQ_SRC_SFT 2
++#define RG_RX_IQ_SRC_HI 3
++#define RG_RX_IQ_SRC_SZ 2
++#define RG_ACI_GAIN_MSK 0x00000ff0
++#define RG_ACI_GAIN_I_MSK 0xfffff00f
++#define RG_ACI_GAIN_SFT 4
++#define RG_ACI_GAIN_HI 11
++#define RG_ACI_GAIN_SZ 8
++#define RG_FFT_EN_MSK 0x00001000
++#define RG_FFT_EN_I_MSK 0xffffefff
++#define RG_FFT_EN_SFT 12
++#define RG_FFT_EN_HI 12
++#define RG_FFT_EN_SZ 1
++#define RG_FFT_MOD_MSK 0x00002000
++#define RG_FFT_MOD_I_MSK 0xffffdfff
++#define RG_FFT_MOD_SFT 13
++#define RG_FFT_MOD_HI 13
++#define RG_FFT_MOD_SZ 1
++#define RG_FFT_SCALE_MSK 0x00ffc000
++#define RG_FFT_SCALE_I_MSK 0xff003fff
++#define RG_FFT_SCALE_SFT 14
++#define RG_FFT_SCALE_HI 23
++#define RG_FFT_SCALE_SZ 10
++#define RG_FFT_ENRG_FREQ_MSK 0x3f000000
++#define RG_FFT_ENRG_FREQ_I_MSK 0xc0ffffff
++#define RG_FFT_ENRG_FREQ_SFT 24
++#define RG_FFT_ENRG_FREQ_HI 29
++#define RG_FFT_ENRG_FREQ_SZ 6
++#define RG_FPGA_80M_PH_UP_MSK 0x40000000
++#define RG_FPGA_80M_PH_UP_I_MSK 0xbfffffff
++#define RG_FPGA_80M_PH_UP_SFT 30
++#define RG_FPGA_80M_PH_UP_HI 30
++#define RG_FPGA_80M_PH_UP_SZ 1
++#define RG_FPGA_80M_PH_STP_MSK 0x80000000
++#define RG_FPGA_80M_PH_STP_I_MSK 0x7fffffff
++#define RG_FPGA_80M_PH_STP_SFT 31
++#define RG_FPGA_80M_PH_STP_HI 31
++#define RG_FPGA_80M_PH_STP_SZ 1
++#define RG_ADC2LA_SEL_MSK 0x00000001
++#define RG_ADC2LA_SEL_I_MSK 0xfffffffe
++#define RG_ADC2LA_SEL_SFT 0
++#define RG_ADC2LA_SEL_HI 0
++#define RG_ADC2LA_SEL_SZ 1
++#define RG_ADC2LA_CLKPH_MSK 0x00000002
++#define RG_ADC2LA_CLKPH_I_MSK 0xfffffffd
++#define RG_ADC2LA_CLKPH_SFT 1
++#define RG_ADC2LA_CLKPH_HI 1
++#define RG_ADC2LA_CLKPH_SZ 1
++#define RG_RXIQ_EMU_IDX_MSK 0x0000000f
++#define RG_RXIQ_EMU_IDX_I_MSK 0xfffffff0
++#define RG_RXIQ_EMU_IDX_SFT 0
++#define RG_RXIQ_EMU_IDX_HI 3
++#define RG_RXIQ_EMU_IDX_SZ 4
++#define RG_IQCAL_BP_ACI_MSK 0x00000010
++#define RG_IQCAL_BP_ACI_I_MSK 0xffffffef
++#define RG_IQCAL_BP_ACI_SFT 4
++#define RG_IQCAL_BP_ACI_HI 4
++#define RG_IQCAL_BP_ACI_SZ 1
++#define RG_DPD_AM_EN_MSK 0x00000001
++#define RG_DPD_AM_EN_I_MSK 0xfffffffe
++#define RG_DPD_AM_EN_SFT 0
++#define RG_DPD_AM_EN_HI 0
++#define RG_DPD_AM_EN_SZ 1
++#define RG_DPD_PM_EN_MSK 0x00000002
++#define RG_DPD_PM_EN_I_MSK 0xfffffffd
++#define RG_DPD_PM_EN_SFT 1
++#define RG_DPD_PM_EN_HI 1
++#define RG_DPD_PM_EN_SZ 1
++#define RG_DPD_PM_AMSEL_MSK 0x00000004
++#define RG_DPD_PM_AMSEL_I_MSK 0xfffffffb
++#define RG_DPD_PM_AMSEL_SFT 2
++#define RG_DPD_PM_AMSEL_HI 2
++#define RG_DPD_PM_AMSEL_SZ 1
++#define RG_DPD_020_GAIN_MSK 0x000003ff
++#define RG_DPD_020_GAIN_I_MSK 0xfffffc00
++#define RG_DPD_020_GAIN_SFT 0
++#define RG_DPD_020_GAIN_HI 9
++#define RG_DPD_020_GAIN_SZ 10
++#define RG_DPD_040_GAIN_MSK 0x03ff0000
++#define RG_DPD_040_GAIN_I_MSK 0xfc00ffff
++#define RG_DPD_040_GAIN_SFT 16
++#define RG_DPD_040_GAIN_HI 25
++#define RG_DPD_040_GAIN_SZ 10
++#define RG_DPD_060_GAIN_MSK 0x000003ff
++#define RG_DPD_060_GAIN_I_MSK 0xfffffc00
++#define RG_DPD_060_GAIN_SFT 0
++#define RG_DPD_060_GAIN_HI 9
++#define RG_DPD_060_GAIN_SZ 10
++#define RG_DPD_080_GAIN_MSK 0x03ff0000
++#define RG_DPD_080_GAIN_I_MSK 0xfc00ffff
++#define RG_DPD_080_GAIN_SFT 16
++#define RG_DPD_080_GAIN_HI 25
++#define RG_DPD_080_GAIN_SZ 10
++#define RG_DPD_0A0_GAIN_MSK 0x000003ff
++#define RG_DPD_0A0_GAIN_I_MSK 0xfffffc00
++#define RG_DPD_0A0_GAIN_SFT 0
++#define RG_DPD_0A0_GAIN_HI 9
++#define RG_DPD_0A0_GAIN_SZ 10
++#define RG_DPD_0C0_GAIN_MSK 0x03ff0000
++#define RG_DPD_0C0_GAIN_I_MSK 0xfc00ffff
++#define RG_DPD_0C0_GAIN_SFT 16
++#define RG_DPD_0C0_GAIN_HI 25
++#define RG_DPD_0C0_GAIN_SZ 10
++#define RG_DPD_0D0_GAIN_MSK 0x000003ff
++#define RG_DPD_0D0_GAIN_I_MSK 0xfffffc00
++#define RG_DPD_0D0_GAIN_SFT 0
++#define RG_DPD_0D0_GAIN_HI 9
++#define RG_DPD_0D0_GAIN_SZ 10
++#define RG_DPD_0E0_GAIN_MSK 0x03ff0000
++#define RG_DPD_0E0_GAIN_I_MSK 0xfc00ffff
++#define RG_DPD_0E0_GAIN_SFT 16
++#define RG_DPD_0E0_GAIN_HI 25
++#define RG_DPD_0E0_GAIN_SZ 10
++#define RG_DPD_0F0_GAIN_MSK 0x000003ff
++#define RG_DPD_0F0_GAIN_I_MSK 0xfffffc00
++#define RG_DPD_0F0_GAIN_SFT 0
++#define RG_DPD_0F0_GAIN_HI 9
++#define RG_DPD_0F0_GAIN_SZ 10
++#define RG_DPD_100_GAIN_MSK 0x03ff0000
++#define RG_DPD_100_GAIN_I_MSK 0xfc00ffff
++#define RG_DPD_100_GAIN_SFT 16
++#define RG_DPD_100_GAIN_HI 25
++#define RG_DPD_100_GAIN_SZ 10
++#define RG_DPD_110_GAIN_MSK 0x000003ff
++#define RG_DPD_110_GAIN_I_MSK 0xfffffc00
++#define RG_DPD_110_GAIN_SFT 0
++#define RG_DPD_110_GAIN_HI 9
++#define RG_DPD_110_GAIN_SZ 10
++#define RG_DPD_120_GAIN_MSK 0x03ff0000
++#define RG_DPD_120_GAIN_I_MSK 0xfc00ffff
++#define RG_DPD_120_GAIN_SFT 16
++#define RG_DPD_120_GAIN_HI 25
++#define RG_DPD_120_GAIN_SZ 10
++#define RG_DPD_130_GAIN_MSK 0x000003ff
++#define RG_DPD_130_GAIN_I_MSK 0xfffffc00
++#define RG_DPD_130_GAIN_SFT 0
++#define RG_DPD_130_GAIN_HI 9
++#define RG_DPD_130_GAIN_SZ 10
++#define RG_DPD_140_GAIN_MSK 0x03ff0000
++#define RG_DPD_140_GAIN_I_MSK 0xfc00ffff
++#define RG_DPD_140_GAIN_SFT 16
++#define RG_DPD_140_GAIN_HI 25
++#define RG_DPD_140_GAIN_SZ 10
++#define RG_DPD_150_GAIN_MSK 0x000003ff
++#define RG_DPD_150_GAIN_I_MSK 0xfffffc00
++#define RG_DPD_150_GAIN_SFT 0
++#define RG_DPD_150_GAIN_HI 9
++#define RG_DPD_150_GAIN_SZ 10
++#define RG_DPD_160_GAIN_MSK 0x03ff0000
++#define RG_DPD_160_GAIN_I_MSK 0xfc00ffff
++#define RG_DPD_160_GAIN_SFT 16
++#define RG_DPD_160_GAIN_HI 25
++#define RG_DPD_160_GAIN_SZ 10
++#define RG_DPD_170_GAIN_MSK 0x000003ff
++#define RG_DPD_170_GAIN_I_MSK 0xfffffc00
++#define RG_DPD_170_GAIN_SFT 0
++#define RG_DPD_170_GAIN_HI 9
++#define RG_DPD_170_GAIN_SZ 10
++#define RG_DPD_180_GAIN_MSK 0x03ff0000
++#define RG_DPD_180_GAIN_I_MSK 0xfc00ffff
++#define RG_DPD_180_GAIN_SFT 16
++#define RG_DPD_180_GAIN_HI 25
++#define RG_DPD_180_GAIN_SZ 10
++#define RG_DPD_190_GAIN_MSK 0x000003ff
++#define RG_DPD_190_GAIN_I_MSK 0xfffffc00
++#define RG_DPD_190_GAIN_SFT 0
++#define RG_DPD_190_GAIN_HI 9
++#define RG_DPD_190_GAIN_SZ 10
++#define RG_DPD_1A0_GAIN_MSK 0x03ff0000
++#define RG_DPD_1A0_GAIN_I_MSK 0xfc00ffff
++#define RG_DPD_1A0_GAIN_SFT 16
++#define RG_DPD_1A0_GAIN_HI 25
++#define RG_DPD_1A0_GAIN_SZ 10
++#define RG_DPD_1B0_GAIN_MSK 0x000003ff
++#define RG_DPD_1B0_GAIN_I_MSK 0xfffffc00
++#define RG_DPD_1B0_GAIN_SFT 0
++#define RG_DPD_1B0_GAIN_HI 9
++#define RG_DPD_1B0_GAIN_SZ 10
++#define RG_DPD_1C0_GAIN_MSK 0x03ff0000
++#define RG_DPD_1C0_GAIN_I_MSK 0xfc00ffff
++#define RG_DPD_1C0_GAIN_SFT 16
++#define RG_DPD_1C0_GAIN_HI 25
++#define RG_DPD_1C0_GAIN_SZ 10
++#define RG_DPD_1D0_GAIN_MSK 0x000003ff
++#define RG_DPD_1D0_GAIN_I_MSK 0xfffffc00
++#define RG_DPD_1D0_GAIN_SFT 0
++#define RG_DPD_1D0_GAIN_HI 9
++#define RG_DPD_1D0_GAIN_SZ 10
++#define RG_DPD_1E0_GAIN_MSK 0x03ff0000
++#define RG_DPD_1E0_GAIN_I_MSK 0xfc00ffff
++#define RG_DPD_1E0_GAIN_SFT 16
++#define RG_DPD_1E0_GAIN_HI 25
++#define RG_DPD_1E0_GAIN_SZ 10
++#define RG_DPD_1F0_GAIN_MSK 0x000003ff
++#define RG_DPD_1F0_GAIN_I_MSK 0xfffffc00
++#define RG_DPD_1F0_GAIN_SFT 0
++#define RG_DPD_1F0_GAIN_HI 9
++#define RG_DPD_1F0_GAIN_SZ 10
++#define RG_DPD_200_GAIN_MSK 0x03ff0000
++#define RG_DPD_200_GAIN_I_MSK 0xfc00ffff
++#define RG_DPD_200_GAIN_SFT 16
++#define RG_DPD_200_GAIN_HI 25
++#define RG_DPD_200_GAIN_SZ 10
++#define RG_DPD_020_PH_MSK 0x00001fff
++#define RG_DPD_020_PH_I_MSK 0xffffe000
++#define RG_DPD_020_PH_SFT 0
++#define RG_DPD_020_PH_HI 12
++#define RG_DPD_020_PH_SZ 13
++#define RG_DPD_040_PH_MSK 0x1fff0000
++#define RG_DPD_040_PH_I_MSK 0xe000ffff
++#define RG_DPD_040_PH_SFT 16
++#define RG_DPD_040_PH_HI 28
++#define RG_DPD_040_PH_SZ 13
++#define RG_DPD_060_PH_MSK 0x00001fff
++#define RG_DPD_060_PH_I_MSK 0xffffe000
++#define RG_DPD_060_PH_SFT 0
++#define RG_DPD_060_PH_HI 12
++#define RG_DPD_060_PH_SZ 13
++#define RG_DPD_080_PH_MSK 0x1fff0000
++#define RG_DPD_080_PH_I_MSK 0xe000ffff
++#define RG_DPD_080_PH_SFT 16
++#define RG_DPD_080_PH_HI 28
++#define RG_DPD_080_PH_SZ 13
++#define RG_DPD_0A0_PH_MSK 0x00001fff
++#define RG_DPD_0A0_PH_I_MSK 0xffffe000
++#define RG_DPD_0A0_PH_SFT 0
++#define RG_DPD_0A0_PH_HI 12
++#define RG_DPD_0A0_PH_SZ 13
++#define RG_DPD_0C0_PH_MSK 0x1fff0000
++#define RG_DPD_0C0_PH_I_MSK 0xe000ffff
++#define RG_DPD_0C0_PH_SFT 16
++#define RG_DPD_0C0_PH_HI 28
++#define RG_DPD_0C0_PH_SZ 13
++#define RG_DPD_0D0_PH_MSK 0x00001fff
++#define RG_DPD_0D0_PH_I_MSK 0xffffe000
++#define RG_DPD_0D0_PH_SFT 0
++#define RG_DPD_0D0_PH_HI 12
++#define RG_DPD_0D0_PH_SZ 13
++#define RG_DPD_0E0_PH_MSK 0x1fff0000
++#define RG_DPD_0E0_PH_I_MSK 0xe000ffff
++#define RG_DPD_0E0_PH_SFT 16
++#define RG_DPD_0E0_PH_HI 28
++#define RG_DPD_0E0_PH_SZ 13
++#define RG_DPD_0F0_PH_MSK 0x00001fff
++#define RG_DPD_0F0_PH_I_MSK 0xffffe000
++#define RG_DPD_0F0_PH_SFT 0
++#define RG_DPD_0F0_PH_HI 12
++#define RG_DPD_0F0_PH_SZ 13
++#define RG_DPD_100_PH_MSK 0x1fff0000
++#define RG_DPD_100_PH_I_MSK 0xe000ffff
++#define RG_DPD_100_PH_SFT 16
++#define RG_DPD_100_PH_HI 28
++#define RG_DPD_100_PH_SZ 13
++#define RG_DPD_110_PH_MSK 0x00001fff
++#define RG_DPD_110_PH_I_MSK 0xffffe000
++#define RG_DPD_110_PH_SFT 0
++#define RG_DPD_110_PH_HI 12
++#define RG_DPD_110_PH_SZ 13
++#define RG_DPD_120_PH_MSK 0x1fff0000
++#define RG_DPD_120_PH_I_MSK 0xe000ffff
++#define RG_DPD_120_PH_SFT 16
++#define RG_DPD_120_PH_HI 28
++#define RG_DPD_120_PH_SZ 13
++#define RG_DPD_130_PH_MSK 0x00001fff
++#define RG_DPD_130_PH_I_MSK 0xffffe000
++#define RG_DPD_130_PH_SFT 0
++#define RG_DPD_130_PH_HI 12
++#define RG_DPD_130_PH_SZ 13
++#define RG_DPD_140_PH_MSK 0x1fff0000
++#define RG_DPD_140_PH_I_MSK 0xe000ffff
++#define RG_DPD_140_PH_SFT 16
++#define RG_DPD_140_PH_HI 28
++#define RG_DPD_140_PH_SZ 13
++#define RG_DPD_150_PH_MSK 0x00001fff
++#define RG_DPD_150_PH_I_MSK 0xffffe000
++#define RG_DPD_150_PH_SFT 0
++#define RG_DPD_150_PH_HI 12
++#define RG_DPD_150_PH_SZ 13
++#define RG_DPD_160_PH_MSK 0x1fff0000
++#define RG_DPD_160_PH_I_MSK 0xe000ffff
++#define RG_DPD_160_PH_SFT 16
++#define RG_DPD_160_PH_HI 28
++#define RG_DPD_160_PH_SZ 13
++#define RG_DPD_170_PH_MSK 0x00001fff
++#define RG_DPD_170_PH_I_MSK 0xffffe000
++#define RG_DPD_170_PH_SFT 0
++#define RG_DPD_170_PH_HI 12
++#define RG_DPD_170_PH_SZ 13
++#define RG_DPD_180_PH_MSK 0x1fff0000
++#define RG_DPD_180_PH_I_MSK 0xe000ffff
++#define RG_DPD_180_PH_SFT 16
++#define RG_DPD_180_PH_HI 28
++#define RG_DPD_180_PH_SZ 13
++#define RG_DPD_190_PH_MSK 0x00001fff
++#define RG_DPD_190_PH_I_MSK 0xffffe000
++#define RG_DPD_190_PH_SFT 0
++#define RG_DPD_190_PH_HI 12
++#define RG_DPD_190_PH_SZ 13
++#define RG_DPD_1A0_PH_MSK 0x1fff0000
++#define RG_DPD_1A0_PH_I_MSK 0xe000ffff
++#define RG_DPD_1A0_PH_SFT 16
++#define RG_DPD_1A0_PH_HI 28
++#define RG_DPD_1A0_PH_SZ 13
++#define RG_DPD_1B0_PH_MSK 0x00001fff
++#define RG_DPD_1B0_PH_I_MSK 0xffffe000
++#define RG_DPD_1B0_PH_SFT 0
++#define RG_DPD_1B0_PH_HI 12
++#define RG_DPD_1B0_PH_SZ 13
++#define RG_DPD_1C0_PH_MSK 0x1fff0000
++#define RG_DPD_1C0_PH_I_MSK 0xe000ffff
++#define RG_DPD_1C0_PH_SFT 16
++#define RG_DPD_1C0_PH_HI 28
++#define RG_DPD_1C0_PH_SZ 13
++#define RG_DPD_1D0_PH_MSK 0x00001fff
++#define RG_DPD_1D0_PH_I_MSK 0xffffe000
++#define RG_DPD_1D0_PH_SFT 0
++#define RG_DPD_1D0_PH_HI 12
++#define RG_DPD_1D0_PH_SZ 13
++#define RG_DPD_1E0_PH_MSK 0x1fff0000
++#define RG_DPD_1E0_PH_I_MSK 0xe000ffff
++#define RG_DPD_1E0_PH_SFT 16
++#define RG_DPD_1E0_PH_HI 28
++#define RG_DPD_1E0_PH_SZ 13
++#define RG_DPD_1F0_PH_MSK 0x00001fff
++#define RG_DPD_1F0_PH_I_MSK 0xffffe000
++#define RG_DPD_1F0_PH_SFT 0
++#define RG_DPD_1F0_PH_HI 12
++#define RG_DPD_1F0_PH_SZ 13
++#define RG_DPD_200_PH_MSK 0x1fff0000
++#define RG_DPD_200_PH_I_MSK 0xe000ffff
++#define RG_DPD_200_PH_SFT 16
++#define RG_DPD_200_PH_HI 28
++#define RG_DPD_200_PH_SZ 13
++#define RG_DPD_GAIN_EST_Y0_MSK 0x000001ff
++#define RG_DPD_GAIN_EST_Y0_I_MSK 0xfffffe00
++#define RG_DPD_GAIN_EST_Y0_SFT 0
++#define RG_DPD_GAIN_EST_Y0_HI 8
++#define RG_DPD_GAIN_EST_Y0_SZ 9
++#define RG_DPD_GAIN_EST_Y1_MSK 0x01ff0000
++#define RG_DPD_GAIN_EST_Y1_I_MSK 0xfe00ffff
++#define RG_DPD_GAIN_EST_Y1_SFT 16
++#define RG_DPD_GAIN_EST_Y1_HI 24
++#define RG_DPD_GAIN_EST_Y1_SZ 9
++#define RG_DPD_LOOP_GAIN_MSK 0x000003ff
++#define RG_DPD_LOOP_GAIN_I_MSK 0xfffffc00
++#define RG_DPD_LOOP_GAIN_SFT 0
++#define RG_DPD_LOOP_GAIN_HI 9
++#define RG_DPD_LOOP_GAIN_SZ 10
++#define RG_DPD_GAIN_EST_X0_MSK 0x000001ff
++#define RG_DPD_GAIN_EST_X0_I_MSK 0xfffffe00
++#define RG_DPD_GAIN_EST_X0_SFT 0
++#define RG_DPD_GAIN_EST_X0_HI 8
++#define RG_DPD_GAIN_EST_X0_SZ 9
++#define RO_DPD_GAIN_MSK 0x03ff0000
++#define RO_DPD_GAIN_I_MSK 0xfc00ffff
++#define RO_DPD_GAIN_SFT 16
++#define RO_DPD_GAIN_HI 25
++#define RO_DPD_GAIN_SZ 10
++#define TX_SCALE_11B_MSK 0x000000ff
++#define TX_SCALE_11B_I_MSK 0xffffff00
++#define TX_SCALE_11B_SFT 0
++#define TX_SCALE_11B_HI 7
++#define TX_SCALE_11B_SZ 8
++#define TX_SCALE_11B_P0D5_MSK 0x0000ff00
++#define TX_SCALE_11B_P0D5_I_MSK 0xffff00ff
++#define TX_SCALE_11B_P0D5_SFT 8
++#define TX_SCALE_11B_P0D5_HI 15
++#define TX_SCALE_11B_P0D5_SZ 8
++#define TX_SCALE_11G_MSK 0x00ff0000
++#define TX_SCALE_11G_I_MSK 0xff00ffff
++#define TX_SCALE_11G_SFT 16
++#define TX_SCALE_11G_HI 23
++#define TX_SCALE_11G_SZ 8
++#define TX_SCALE_11G_P0D5_MSK 0xff000000
++#define TX_SCALE_11G_P0D5_I_MSK 0x00ffffff
++#define TX_SCALE_11G_P0D5_SFT 24
++#define TX_SCALE_11G_P0D5_HI 31
++#define TX_SCALE_11G_P0D5_SZ 8
++#define RG_EN_MANUAL_MSK 0x00000001
++#define RG_EN_MANUAL_I_MSK 0xfffffffe
++#define RG_EN_MANUAL_SFT 0
++#define RG_EN_MANUAL_HI 0
++#define RG_EN_MANUAL_SZ 1
++#define RG_TX_EN_MSK 0x00000002
++#define RG_TX_EN_I_MSK 0xfffffffd
++#define RG_TX_EN_SFT 1
++#define RG_TX_EN_HI 1
++#define RG_TX_EN_SZ 1
++#define RG_TX_PA_EN_MSK 0x00000004
++#define RG_TX_PA_EN_I_MSK 0xfffffffb
++#define RG_TX_PA_EN_SFT 2
++#define RG_TX_PA_EN_HI 2
++#define RG_TX_PA_EN_SZ 1
++#define RG_TX_DAC_EN_MSK 0x00000008
++#define RG_TX_DAC_EN_I_MSK 0xfffffff7
++#define RG_TX_DAC_EN_SFT 3
++#define RG_TX_DAC_EN_HI 3
++#define RG_TX_DAC_EN_SZ 1
++#define RG_RX_AGC_MSK 0x00000010
++#define RG_RX_AGC_I_MSK 0xffffffef
++#define RG_RX_AGC_SFT 4
++#define RG_RX_AGC_HI 4
++#define RG_RX_AGC_SZ 1
++#define RG_RX_GAIN_MANUAL_MSK 0x00000020
++#define RG_RX_GAIN_MANUAL_I_MSK 0xffffffdf
++#define RG_RX_GAIN_MANUAL_SFT 5
++#define RG_RX_GAIN_MANUAL_HI 5
++#define RG_RX_GAIN_MANUAL_SZ 1
++#define RG_RFG_MSK 0x000000c0
++#define RG_RFG_I_MSK 0xffffff3f
++#define RG_RFG_SFT 6
++#define RG_RFG_HI 7
++#define RG_RFG_SZ 2
++#define RG_PGAG_MSK 0x00000f00
++#define RG_PGAG_I_MSK 0xfffff0ff
++#define RG_PGAG_SFT 8
++#define RG_PGAG_HI 11
++#define RG_PGAG_SZ 4
++#define RG_MODE_MSK 0x00003000
++#define RG_MODE_I_MSK 0xffffcfff
++#define RG_MODE_SFT 12
++#define RG_MODE_HI 13
++#define RG_MODE_SZ 2
++#define RG_EN_TX_TRSW_MSK 0x00004000
++#define RG_EN_TX_TRSW_I_MSK 0xffffbfff
++#define RG_EN_TX_TRSW_SFT 14
++#define RG_EN_TX_TRSW_HI 14
++#define RG_EN_TX_TRSW_SZ 1
++#define RG_EN_SX_MSK 0x00008000
++#define RG_EN_SX_I_MSK 0xffff7fff
++#define RG_EN_SX_SFT 15
++#define RG_EN_SX_HI 15
++#define RG_EN_SX_SZ 1
++#define RG_EN_RX_LNA_MSK 0x00010000
++#define RG_EN_RX_LNA_I_MSK 0xfffeffff
++#define RG_EN_RX_LNA_SFT 16
++#define RG_EN_RX_LNA_HI 16
++#define RG_EN_RX_LNA_SZ 1
++#define RG_EN_RX_MIXER_MSK 0x00020000
++#define RG_EN_RX_MIXER_I_MSK 0xfffdffff
++#define RG_EN_RX_MIXER_SFT 17
++#define RG_EN_RX_MIXER_HI 17
++#define RG_EN_RX_MIXER_SZ 1
++#define RG_EN_RX_DIV2_MSK 0x00040000
++#define RG_EN_RX_DIV2_I_MSK 0xfffbffff
++#define RG_EN_RX_DIV2_SFT 18
++#define RG_EN_RX_DIV2_HI 18
++#define RG_EN_RX_DIV2_SZ 1
++#define RG_EN_RX_LOBUF_MSK 0x00080000
++#define RG_EN_RX_LOBUF_I_MSK 0xfff7ffff
++#define RG_EN_RX_LOBUF_SFT 19
++#define RG_EN_RX_LOBUF_HI 19
++#define RG_EN_RX_LOBUF_SZ 1
++#define RG_EN_RX_TZ_MSK 0x00100000
++#define RG_EN_RX_TZ_I_MSK 0xffefffff
++#define RG_EN_RX_TZ_SFT 20
++#define RG_EN_RX_TZ_HI 20
++#define RG_EN_RX_TZ_SZ 1
++#define RG_EN_RX_FILTER_MSK 0x00200000
++#define RG_EN_RX_FILTER_I_MSK 0xffdfffff
++#define RG_EN_RX_FILTER_SFT 21
++#define RG_EN_RX_FILTER_HI 21
++#define RG_EN_RX_FILTER_SZ 1
++#define RG_EN_RX_HPF_MSK 0x00400000
++#define RG_EN_RX_HPF_I_MSK 0xffbfffff
++#define RG_EN_RX_HPF_SFT 22
++#define RG_EN_RX_HPF_HI 22
++#define RG_EN_RX_HPF_SZ 1
++#define RG_EN_RX_RSSI_MSK 0x00800000
++#define RG_EN_RX_RSSI_I_MSK 0xff7fffff
++#define RG_EN_RX_RSSI_SFT 23
++#define RG_EN_RX_RSSI_HI 23
++#define RG_EN_RX_RSSI_SZ 1
++#define RG_EN_ADC_MSK 0x01000000
++#define RG_EN_ADC_I_MSK 0xfeffffff
++#define RG_EN_ADC_SFT 24
++#define RG_EN_ADC_HI 24
++#define RG_EN_ADC_SZ 1
++#define RG_EN_TX_MOD_MSK 0x02000000
++#define RG_EN_TX_MOD_I_MSK 0xfdffffff
++#define RG_EN_TX_MOD_SFT 25
++#define RG_EN_TX_MOD_HI 25
++#define RG_EN_TX_MOD_SZ 1
++#define RG_EN_TX_DIV2_MSK 0x04000000
++#define RG_EN_TX_DIV2_I_MSK 0xfbffffff
++#define RG_EN_TX_DIV2_SFT 26
++#define RG_EN_TX_DIV2_HI 26
++#define RG_EN_TX_DIV2_SZ 1
++#define RG_EN_TX_DIV2_BUF_MSK 0x08000000
++#define RG_EN_TX_DIV2_BUF_I_MSK 0xf7ffffff
++#define RG_EN_TX_DIV2_BUF_SFT 27
++#define RG_EN_TX_DIV2_BUF_HI 27
++#define RG_EN_TX_DIV2_BUF_SZ 1
++#define RG_EN_TX_LOBF_MSK 0x10000000
++#define RG_EN_TX_LOBF_I_MSK 0xefffffff
++#define RG_EN_TX_LOBF_SFT 28
++#define RG_EN_TX_LOBF_HI 28
++#define RG_EN_TX_LOBF_SZ 1
++#define RG_EN_RX_LOBF_MSK 0x20000000
++#define RG_EN_RX_LOBF_I_MSK 0xdfffffff
++#define RG_EN_RX_LOBF_SFT 29
++#define RG_EN_RX_LOBF_HI 29
++#define RG_EN_RX_LOBF_SZ 1
++#define RG_SEL_DPLL_CLK_MSK 0x40000000
++#define RG_SEL_DPLL_CLK_I_MSK 0xbfffffff
++#define RG_SEL_DPLL_CLK_SFT 30
++#define RG_SEL_DPLL_CLK_HI 30
++#define RG_SEL_DPLL_CLK_SZ 1
++#define RG_EN_CLK_960MBY13_UART_MSK 0x80000000
++#define RG_EN_CLK_960MBY13_UART_I_MSK 0x7fffffff
++#define RG_EN_CLK_960MBY13_UART_SFT 31
++#define RG_EN_CLK_960MBY13_UART_HI 31
++#define RG_EN_CLK_960MBY13_UART_SZ 1
++#define RG_EN_TX_DPD_MSK 0x00000001
++#define RG_EN_TX_DPD_I_MSK 0xfffffffe
++#define RG_EN_TX_DPD_SFT 0
++#define RG_EN_TX_DPD_HI 0
++#define RG_EN_TX_DPD_SZ 1
++#define RG_EN_TX_TSSI_MSK 0x00000002
++#define RG_EN_TX_TSSI_I_MSK 0xfffffffd
++#define RG_EN_TX_TSSI_SFT 1
++#define RG_EN_TX_TSSI_HI 1
++#define RG_EN_TX_TSSI_SZ 1
++#define RG_EN_RX_IQCAL_MSK 0x00000004
++#define RG_EN_RX_IQCAL_I_MSK 0xfffffffb
++#define RG_EN_RX_IQCAL_SFT 2
++#define RG_EN_RX_IQCAL_HI 2
++#define RG_EN_RX_IQCAL_SZ 1
++#define RG_EN_TX_DAC_CAL_MSK 0x00000008
++#define RG_EN_TX_DAC_CAL_I_MSK 0xfffffff7
++#define RG_EN_TX_DAC_CAL_SFT 3
++#define RG_EN_TX_DAC_CAL_HI 3
++#define RG_EN_TX_DAC_CAL_SZ 1
++#define RG_EN_TX_SELF_MIXER_MSK 0x00000010
++#define RG_EN_TX_SELF_MIXER_I_MSK 0xffffffef
++#define RG_EN_TX_SELF_MIXER_SFT 4
++#define RG_EN_TX_SELF_MIXER_HI 4
++#define RG_EN_TX_SELF_MIXER_SZ 1
++#define RG_EN_TX_DAC_OUT_MSK 0x00000020
++#define RG_EN_TX_DAC_OUT_I_MSK 0xffffffdf
++#define RG_EN_TX_DAC_OUT_SFT 5
++#define RG_EN_TX_DAC_OUT_HI 5
++#define RG_EN_TX_DAC_OUT_SZ 1
++#define RG_EN_LDO_RX_FE_MSK 0x00000040
++#define RG_EN_LDO_RX_FE_I_MSK 0xffffffbf
++#define RG_EN_LDO_RX_FE_SFT 6
++#define RG_EN_LDO_RX_FE_HI 6
++#define RG_EN_LDO_RX_FE_SZ 1
++#define RG_EN_LDO_ABB_MSK 0x00000080
++#define RG_EN_LDO_ABB_I_MSK 0xffffff7f
++#define RG_EN_LDO_ABB_SFT 7
++#define RG_EN_LDO_ABB_HI 7
++#define RG_EN_LDO_ABB_SZ 1
++#define RG_EN_LDO_AFE_MSK 0x00000100
++#define RG_EN_LDO_AFE_I_MSK 0xfffffeff
++#define RG_EN_LDO_AFE_SFT 8
++#define RG_EN_LDO_AFE_HI 8
++#define RG_EN_LDO_AFE_SZ 1
++#define RG_EN_SX_CHPLDO_MSK 0x00000200
++#define RG_EN_SX_CHPLDO_I_MSK 0xfffffdff
++#define RG_EN_SX_CHPLDO_SFT 9
++#define RG_EN_SX_CHPLDO_HI 9
++#define RG_EN_SX_CHPLDO_SZ 1
++#define RG_EN_SX_LOBFLDO_MSK 0x00000400
++#define RG_EN_SX_LOBFLDO_I_MSK 0xfffffbff
++#define RG_EN_SX_LOBFLDO_SFT 10
++#define RG_EN_SX_LOBFLDO_HI 10
++#define RG_EN_SX_LOBFLDO_SZ 1
++#define RG_EN_IREF_RX_MSK 0x00000800
++#define RG_EN_IREF_RX_I_MSK 0xfffff7ff
++#define RG_EN_IREF_RX_SFT 11
++#define RG_EN_IREF_RX_HI 11
++#define RG_EN_IREF_RX_SZ 1
++#define RG_EN_TX_DAC_VOUT_MSK 0x00002000
++#define RG_EN_TX_DAC_VOUT_I_MSK 0xffffdfff
++#define RG_EN_TX_DAC_VOUT_SFT 13
++#define RG_EN_TX_DAC_VOUT_HI 13
++#define RG_EN_TX_DAC_VOUT_SZ 1
++#define RG_EN_SX_LCK_BIN_MSK 0x00004000
++#define RG_EN_SX_LCK_BIN_I_MSK 0xffffbfff
++#define RG_EN_SX_LCK_BIN_SFT 14
++#define RG_EN_SX_LCK_BIN_HI 14
++#define RG_EN_SX_LCK_BIN_SZ 1
++#define RG_RTC_CAL_MODE_MSK 0x00010000
++#define RG_RTC_CAL_MODE_I_MSK 0xfffeffff
++#define RG_RTC_CAL_MODE_SFT 16
++#define RG_RTC_CAL_MODE_HI 16
++#define RG_RTC_CAL_MODE_SZ 1
++#define RG_EN_IQPAD_IOSW_MSK 0x00020000
++#define RG_EN_IQPAD_IOSW_I_MSK 0xfffdffff
++#define RG_EN_IQPAD_IOSW_SFT 17
++#define RG_EN_IQPAD_IOSW_HI 17
++#define RG_EN_IQPAD_IOSW_SZ 1
++#define RG_EN_TESTPAD_IOSW_MSK 0x00040000
++#define RG_EN_TESTPAD_IOSW_I_MSK 0xfffbffff
++#define RG_EN_TESTPAD_IOSW_SFT 18
++#define RG_EN_TESTPAD_IOSW_HI 18
++#define RG_EN_TESTPAD_IOSW_SZ 1
++#define RG_EN_TRXBF_BYPASS_MSK 0x00080000
++#define RG_EN_TRXBF_BYPASS_I_MSK 0xfff7ffff
++#define RG_EN_TRXBF_BYPASS_SFT 19
++#define RG_EN_TRXBF_BYPASS_HI 19
++#define RG_EN_TRXBF_BYPASS_SZ 1
++#define RG_LDO_LEVEL_RX_FE_MSK 0x00000007
++#define RG_LDO_LEVEL_RX_FE_I_MSK 0xfffffff8
++#define RG_LDO_LEVEL_RX_FE_SFT 0
++#define RG_LDO_LEVEL_RX_FE_HI 2
++#define RG_LDO_LEVEL_RX_FE_SZ 3
++#define RG_LDO_LEVEL_ABB_MSK 0x00000038
++#define RG_LDO_LEVEL_ABB_I_MSK 0xffffffc7
++#define RG_LDO_LEVEL_ABB_SFT 3
++#define RG_LDO_LEVEL_ABB_HI 5
++#define RG_LDO_LEVEL_ABB_SZ 3
++#define RG_LDO_LEVEL_AFE_MSK 0x000001c0
++#define RG_LDO_LEVEL_AFE_I_MSK 0xfffffe3f
++#define RG_LDO_LEVEL_AFE_SFT 6
++#define RG_LDO_LEVEL_AFE_HI 8
++#define RG_LDO_LEVEL_AFE_SZ 3
++#define RG_SX_LDO_CHP_LEVEL_MSK 0x00000e00
++#define RG_SX_LDO_CHP_LEVEL_I_MSK 0xfffff1ff
++#define RG_SX_LDO_CHP_LEVEL_SFT 9
++#define RG_SX_LDO_CHP_LEVEL_HI 11
++#define RG_SX_LDO_CHP_LEVEL_SZ 3
++#define RG_SX_LDO_LOBF_LEVEL_MSK 0x00007000
++#define RG_SX_LDO_LOBF_LEVEL_I_MSK 0xffff8fff
++#define RG_SX_LDO_LOBF_LEVEL_SFT 12
++#define RG_SX_LDO_LOBF_LEVEL_HI 14
++#define RG_SX_LDO_LOBF_LEVEL_SZ 3
++#define RG_SX_LDO_XOSC_LEVEL_MSK 0x00038000
++#define RG_SX_LDO_XOSC_LEVEL_I_MSK 0xfffc7fff
++#define RG_SX_LDO_XOSC_LEVEL_SFT 15
++#define RG_SX_LDO_XOSC_LEVEL_HI 17
++#define RG_SX_LDO_XOSC_LEVEL_SZ 3
++#define RG_DP_LDO_LEVEL_MSK 0x001c0000
++#define RG_DP_LDO_LEVEL_I_MSK 0xffe3ffff
++#define RG_DP_LDO_LEVEL_SFT 18
++#define RG_DP_LDO_LEVEL_HI 20
++#define RG_DP_LDO_LEVEL_SZ 3
++#define RG_SX_LDO_VCO_LEVEL_MSK 0x00e00000
++#define RG_SX_LDO_VCO_LEVEL_I_MSK 0xff1fffff
++#define RG_SX_LDO_VCO_LEVEL_SFT 21
++#define RG_SX_LDO_VCO_LEVEL_HI 23
++#define RG_SX_LDO_VCO_LEVEL_SZ 3
++#define RG_TX_LDO_TX_LEVEL_MSK 0x07000000
++#define RG_TX_LDO_TX_LEVEL_I_MSK 0xf8ffffff
++#define RG_TX_LDO_TX_LEVEL_SFT 24
++#define RG_TX_LDO_TX_LEVEL_HI 26
++#define RG_TX_LDO_TX_LEVEL_SZ 3
++#define RG_EN_RX_PADSW_MSK 0x00000001
++#define RG_EN_RX_PADSW_I_MSK 0xfffffffe
++#define RG_EN_RX_PADSW_SFT 0
++#define RG_EN_RX_PADSW_HI 0
++#define RG_EN_RX_PADSW_SZ 1
++#define RG_EN_RX_TESTNODE_MSK 0x00000002
++#define RG_EN_RX_TESTNODE_I_MSK 0xfffffffd
++#define RG_EN_RX_TESTNODE_SFT 1
++#define RG_EN_RX_TESTNODE_HI 1
++#define RG_EN_RX_TESTNODE_SZ 1
++#define RG_RX_ABBCFIX_MSK 0x00000004
++#define RG_RX_ABBCFIX_I_MSK 0xfffffffb
++#define RG_RX_ABBCFIX_SFT 2
++#define RG_RX_ABBCFIX_HI 2
++#define RG_RX_ABBCFIX_SZ 1
++#define RG_RX_ABBCTUNE_MSK 0x000001f8
++#define RG_RX_ABBCTUNE_I_MSK 0xfffffe07
++#define RG_RX_ABBCTUNE_SFT 3
++#define RG_RX_ABBCTUNE_HI 8
++#define RG_RX_ABBCTUNE_SZ 6
++#define RG_RX_ABBOUT_TRI_STATE_MSK 0x00000200
++#define RG_RX_ABBOUT_TRI_STATE_I_MSK 0xfffffdff
++#define RG_RX_ABBOUT_TRI_STATE_SFT 9
++#define RG_RX_ABBOUT_TRI_STATE_HI 9
++#define RG_RX_ABBOUT_TRI_STATE_SZ 1
++#define RG_RX_ABB_N_MODE_MSK 0x00000400
++#define RG_RX_ABB_N_MODE_I_MSK 0xfffffbff
++#define RG_RX_ABB_N_MODE_SFT 10
++#define RG_RX_ABB_N_MODE_HI 10
++#define RG_RX_ABB_N_MODE_SZ 1
++#define RG_RX_EN_LOOPA_MSK 0x00000800
++#define RG_RX_EN_LOOPA_I_MSK 0xfffff7ff
++#define RG_RX_EN_LOOPA_SFT 11
++#define RG_RX_EN_LOOPA_HI 11
++#define RG_RX_EN_LOOPA_SZ 1
++#define RG_RX_FILTERI1ST_MSK 0x00003000
++#define RG_RX_FILTERI1ST_I_MSK 0xffffcfff
++#define RG_RX_FILTERI1ST_SFT 12
++#define RG_RX_FILTERI1ST_HI 13
++#define RG_RX_FILTERI1ST_SZ 2
++#define RG_RX_FILTERI2ND_MSK 0x0000c000
++#define RG_RX_FILTERI2ND_I_MSK 0xffff3fff
++#define RG_RX_FILTERI2ND_SFT 14
++#define RG_RX_FILTERI2ND_HI 15
++#define RG_RX_FILTERI2ND_SZ 2
++#define RG_RX_FILTERI3RD_MSK 0x00030000
++#define RG_RX_FILTERI3RD_I_MSK 0xfffcffff
++#define RG_RX_FILTERI3RD_SFT 16
++#define RG_RX_FILTERI3RD_HI 17
++#define RG_RX_FILTERI3RD_SZ 2
++#define RG_RX_FILTERI_COURSE_MSK 0x000c0000
++#define RG_RX_FILTERI_COURSE_I_MSK 0xfff3ffff
++#define RG_RX_FILTERI_COURSE_SFT 18
++#define RG_RX_FILTERI_COURSE_HI 19
++#define RG_RX_FILTERI_COURSE_SZ 2
++#define RG_RX_FILTERVCM_MSK 0x00300000
++#define RG_RX_FILTERVCM_I_MSK 0xffcfffff
++#define RG_RX_FILTERVCM_SFT 20
++#define RG_RX_FILTERVCM_HI 21
++#define RG_RX_FILTERVCM_SZ 2
++#define RG_RX_HPF3M_MSK 0x00400000
++#define RG_RX_HPF3M_I_MSK 0xffbfffff
++#define RG_RX_HPF3M_SFT 22
++#define RG_RX_HPF3M_HI 22
++#define RG_RX_HPF3M_SZ 1
++#define RG_RX_HPF300K_MSK 0x00800000
++#define RG_RX_HPF300K_I_MSK 0xff7fffff
++#define RG_RX_HPF300K_SFT 23
++#define RG_RX_HPF300K_HI 23
++#define RG_RX_HPF300K_SZ 1
++#define RG_RX_HPFI_MSK 0x03000000
++#define RG_RX_HPFI_I_MSK 0xfcffffff
++#define RG_RX_HPFI_SFT 24
++#define RG_RX_HPFI_HI 25
++#define RG_RX_HPFI_SZ 2
++#define RG_RX_HPF_FINALCORNER_MSK 0x0c000000
++#define RG_RX_HPF_FINALCORNER_I_MSK 0xf3ffffff
++#define RG_RX_HPF_FINALCORNER_SFT 26
++#define RG_RX_HPF_FINALCORNER_HI 27
++#define RG_RX_HPF_FINALCORNER_SZ 2
++#define RG_RX_HPF_SETTLE1_C_MSK 0x30000000
++#define RG_RX_HPF_SETTLE1_C_I_MSK 0xcfffffff
++#define RG_RX_HPF_SETTLE1_C_SFT 28
++#define RG_RX_HPF_SETTLE1_C_HI 29
++#define RG_RX_HPF_SETTLE1_C_SZ 2
++#define RG_RX_HPF_SETTLE1_R_MSK 0x00000003
++#define RG_RX_HPF_SETTLE1_R_I_MSK 0xfffffffc
++#define RG_RX_HPF_SETTLE1_R_SFT 0
++#define RG_RX_HPF_SETTLE1_R_HI 1
++#define RG_RX_HPF_SETTLE1_R_SZ 2
++#define RG_RX_HPF_SETTLE2_C_MSK 0x0000000c
++#define RG_RX_HPF_SETTLE2_C_I_MSK 0xfffffff3
++#define RG_RX_HPF_SETTLE2_C_SFT 2
++#define RG_RX_HPF_SETTLE2_C_HI 3
++#define RG_RX_HPF_SETTLE2_C_SZ 2
++#define RG_RX_HPF_SETTLE2_R_MSK 0x00000030
++#define RG_RX_HPF_SETTLE2_R_I_MSK 0xffffffcf
++#define RG_RX_HPF_SETTLE2_R_SFT 4
++#define RG_RX_HPF_SETTLE2_R_HI 5
++#define RG_RX_HPF_SETTLE2_R_SZ 2
++#define RG_RX_HPF_VCMCON2_MSK 0x000000c0
++#define RG_RX_HPF_VCMCON2_I_MSK 0xffffff3f
++#define RG_RX_HPF_VCMCON2_SFT 6
++#define RG_RX_HPF_VCMCON2_HI 7
++#define RG_RX_HPF_VCMCON2_SZ 2
++#define RG_RX_HPF_VCMCON_MSK 0x00000300
++#define RG_RX_HPF_VCMCON_I_MSK 0xfffffcff
++#define RG_RX_HPF_VCMCON_SFT 8
++#define RG_RX_HPF_VCMCON_HI 9
++#define RG_RX_HPF_VCMCON_SZ 2
++#define RG_RX_OUTVCM_MSK 0x00000c00
++#define RG_RX_OUTVCM_I_MSK 0xfffff3ff
++#define RG_RX_OUTVCM_SFT 10
++#define RG_RX_OUTVCM_HI 11
++#define RG_RX_OUTVCM_SZ 2
++#define RG_RX_TZI_MSK 0x00003000
++#define RG_RX_TZI_I_MSK 0xffffcfff
++#define RG_RX_TZI_SFT 12
++#define RG_RX_TZI_HI 13
++#define RG_RX_TZI_SZ 2
++#define RG_RX_TZ_OUT_TRISTATE_MSK 0x00004000
++#define RG_RX_TZ_OUT_TRISTATE_I_MSK 0xffffbfff
++#define RG_RX_TZ_OUT_TRISTATE_SFT 14
++#define RG_RX_TZ_OUT_TRISTATE_HI 14
++#define RG_RX_TZ_OUT_TRISTATE_SZ 1
++#define RG_RX_TZ_VCM_MSK 0x00018000
++#define RG_RX_TZ_VCM_I_MSK 0xfffe7fff
++#define RG_RX_TZ_VCM_SFT 15
++#define RG_RX_TZ_VCM_HI 16
++#define RG_RX_TZ_VCM_SZ 2
++#define RG_EN_RX_RSSI_TESTNODE_MSK 0x000e0000
++#define RG_EN_RX_RSSI_TESTNODE_I_MSK 0xfff1ffff
++#define RG_EN_RX_RSSI_TESTNODE_SFT 17
++#define RG_EN_RX_RSSI_TESTNODE_HI 19
++#define RG_EN_RX_RSSI_TESTNODE_SZ 3
++#define RG_RX_ADCRSSI_CLKSEL_MSK 0x00100000
++#define RG_RX_ADCRSSI_CLKSEL_I_MSK 0xffefffff
++#define RG_RX_ADCRSSI_CLKSEL_SFT 20
++#define RG_RX_ADCRSSI_CLKSEL_HI 20
++#define RG_RX_ADCRSSI_CLKSEL_SZ 1
++#define RG_RX_ADCRSSI_VCM_MSK 0x00600000
++#define RG_RX_ADCRSSI_VCM_I_MSK 0xff9fffff
++#define RG_RX_ADCRSSI_VCM_SFT 21
++#define RG_RX_ADCRSSI_VCM_HI 22
++#define RG_RX_ADCRSSI_VCM_SZ 2
++#define RG_RX_REC_LPFCORNER_MSK 0x01800000
++#define RG_RX_REC_LPFCORNER_I_MSK 0xfe7fffff
++#define RG_RX_REC_LPFCORNER_SFT 23
++#define RG_RX_REC_LPFCORNER_HI 24
++#define RG_RX_REC_LPFCORNER_SZ 2
++#define RG_RSSI_CLOCK_GATING_MSK 0x02000000
++#define RG_RSSI_CLOCK_GATING_I_MSK 0xfdffffff
++#define RG_RSSI_CLOCK_GATING_SFT 25
++#define RG_RSSI_CLOCK_GATING_HI 25
++#define RG_RSSI_CLOCK_GATING_SZ 1
++#define RG_TXPGA_CAPSW_MSK 0x00000003
++#define RG_TXPGA_CAPSW_I_MSK 0xfffffffc
++#define RG_TXPGA_CAPSW_SFT 0
++#define RG_TXPGA_CAPSW_HI 1
++#define RG_TXPGA_CAPSW_SZ 2
++#define RG_TXPGA_MAIN_MSK 0x000000fc
++#define RG_TXPGA_MAIN_I_MSK 0xffffff03
++#define RG_TXPGA_MAIN_SFT 2
++#define RG_TXPGA_MAIN_HI 7
++#define RG_TXPGA_MAIN_SZ 6
++#define RG_TXPGA_STEER_MSK 0x00003f00
++#define RG_TXPGA_STEER_I_MSK 0xffffc0ff
++#define RG_TXPGA_STEER_SFT 8
++#define RG_TXPGA_STEER_HI 13
++#define RG_TXPGA_STEER_SZ 6
++#define RG_TXMOD_GMCELL_MSK 0x0000c000
++#define RG_TXMOD_GMCELL_I_MSK 0xffff3fff
++#define RG_TXMOD_GMCELL_SFT 14
++#define RG_TXMOD_GMCELL_HI 15
++#define RG_TXMOD_GMCELL_SZ 2
++#define RG_TXLPF_GMCELL_MSK 0x00030000
++#define RG_TXLPF_GMCELL_I_MSK 0xfffcffff
++#define RG_TXLPF_GMCELL_SFT 16
++#define RG_TXLPF_GMCELL_HI 17
++#define RG_TXLPF_GMCELL_SZ 2
++#define RG_PACELL_EN_MSK 0x001c0000
++#define RG_PACELL_EN_I_MSK 0xffe3ffff
++#define RG_PACELL_EN_SFT 18
++#define RG_PACELL_EN_HI 20
++#define RG_PACELL_EN_SZ 3
++#define RG_PABIAS_CTRL_MSK 0x01e00000
++#define RG_PABIAS_CTRL_I_MSK 0xfe1fffff
++#define RG_PABIAS_CTRL_SFT 21
++#define RG_PABIAS_CTRL_HI 24
++#define RG_PABIAS_CTRL_SZ 4
++#define RG_TX_DIV_VSET_MSK 0x0c000000
++#define RG_TX_DIV_VSET_I_MSK 0xf3ffffff
++#define RG_TX_DIV_VSET_SFT 26
++#define RG_TX_DIV_VSET_HI 27
++#define RG_TX_DIV_VSET_SZ 2
++#define RG_TX_LOBUF_VSET_MSK 0x30000000
++#define RG_TX_LOBUF_VSET_I_MSK 0xcfffffff
++#define RG_TX_LOBUF_VSET_SFT 28
++#define RG_TX_LOBUF_VSET_HI 29
++#define RG_TX_LOBUF_VSET_SZ 2
++#define RG_RX_SQDC_MSK 0x00000007
++#define RG_RX_SQDC_I_MSK 0xfffffff8
++#define RG_RX_SQDC_SFT 0
++#define RG_RX_SQDC_HI 2
++#define RG_RX_SQDC_SZ 3
++#define RG_RX_DIV2_CORE_MSK 0x00000018
++#define RG_RX_DIV2_CORE_I_MSK 0xffffffe7
++#define RG_RX_DIV2_CORE_SFT 3
++#define RG_RX_DIV2_CORE_HI 4
++#define RG_RX_DIV2_CORE_SZ 2
++#define RG_RX_LOBUF_MSK 0x00000060
++#define RG_RX_LOBUF_I_MSK 0xffffff9f
++#define RG_RX_LOBUF_SFT 5
++#define RG_RX_LOBUF_HI 6
++#define RG_RX_LOBUF_SZ 2
++#define RG_TX_DPDGM_BIAS_MSK 0x00000780
++#define RG_TX_DPDGM_BIAS_I_MSK 0xfffff87f
++#define RG_TX_DPDGM_BIAS_SFT 7
++#define RG_TX_DPDGM_BIAS_HI 10
++#define RG_TX_DPDGM_BIAS_SZ 4
++#define RG_TX_DPD_DIV_MSK 0x00007800
++#define RG_TX_DPD_DIV_I_MSK 0xffff87ff
++#define RG_TX_DPD_DIV_SFT 11
++#define RG_TX_DPD_DIV_HI 14
++#define RG_TX_DPD_DIV_SZ 4
++#define RG_TX_TSSI_BIAS_MSK 0x00038000
++#define RG_TX_TSSI_BIAS_I_MSK 0xfffc7fff
++#define RG_TX_TSSI_BIAS_SFT 15
++#define RG_TX_TSSI_BIAS_HI 17
++#define RG_TX_TSSI_BIAS_SZ 3
++#define RG_TX_TSSI_DIV_MSK 0x001c0000
++#define RG_TX_TSSI_DIV_I_MSK 0xffe3ffff
++#define RG_TX_TSSI_DIV_SFT 18
++#define RG_TX_TSSI_DIV_HI 20
++#define RG_TX_TSSI_DIV_SZ 3
++#define RG_TX_TSSI_TESTMODE_MSK 0x00200000
++#define RG_TX_TSSI_TESTMODE_I_MSK 0xffdfffff
++#define RG_TX_TSSI_TESTMODE_SFT 21
++#define RG_TX_TSSI_TESTMODE_HI 21
++#define RG_TX_TSSI_TESTMODE_SZ 1
++#define RG_TX_TSSI_TEST_MSK 0x00c00000
++#define RG_TX_TSSI_TEST_I_MSK 0xff3fffff
++#define RG_TX_TSSI_TEST_SFT 22
++#define RG_TX_TSSI_TEST_HI 23
++#define RG_TX_TSSI_TEST_SZ 2
++#define RG_PACASCODE_CTRL_MSK 0x07000000
++#define RG_PACASCODE_CTRL_I_MSK 0xf8ffffff
++#define RG_PACASCODE_CTRL_SFT 24
++#define RG_PACASCODE_CTRL_HI 26
++#define RG_PACASCODE_CTRL_SZ 3
++#define RG_RX_HG_LNA_GC_MSK 0x00000003
++#define RG_RX_HG_LNA_GC_I_MSK 0xfffffffc
++#define RG_RX_HG_LNA_GC_SFT 0
++#define RG_RX_HG_LNA_GC_HI 1
++#define RG_RX_HG_LNA_GC_SZ 2
++#define RG_RX_HG_LNAHGN_BIAS_MSK 0x0000003c
++#define RG_RX_HG_LNAHGN_BIAS_I_MSK 0xffffffc3
++#define RG_RX_HG_LNAHGN_BIAS_SFT 2
++#define RG_RX_HG_LNAHGN_BIAS_HI 5
++#define RG_RX_HG_LNAHGN_BIAS_SZ 4
++#define RG_RX_HG_LNAHGP_BIAS_MSK 0x000003c0
++#define RG_RX_HG_LNAHGP_BIAS_I_MSK 0xfffffc3f
++#define RG_RX_HG_LNAHGP_BIAS_SFT 6
++#define RG_RX_HG_LNAHGP_BIAS_HI 9
++#define RG_RX_HG_LNAHGP_BIAS_SZ 4
++#define RG_RX_HG_LNALG_BIAS_MSK 0x00003c00
++#define RG_RX_HG_LNALG_BIAS_I_MSK 0xffffc3ff
++#define RG_RX_HG_LNALG_BIAS_SFT 10
++#define RG_RX_HG_LNALG_BIAS_HI 13
++#define RG_RX_HG_LNALG_BIAS_SZ 4
++#define RG_RX_HG_TZ_GC_MSK 0x0000c000
++#define RG_RX_HG_TZ_GC_I_MSK 0xffff3fff
++#define RG_RX_HG_TZ_GC_SFT 14
++#define RG_RX_HG_TZ_GC_HI 15
++#define RG_RX_HG_TZ_GC_SZ 2
++#define RG_RX_HG_TZ_CAP_MSK 0x00070000
++#define RG_RX_HG_TZ_CAP_I_MSK 0xfff8ffff
++#define RG_RX_HG_TZ_CAP_SFT 16
++#define RG_RX_HG_TZ_CAP_HI 18
++#define RG_RX_HG_TZ_CAP_SZ 3
++#define RG_RX_MG_LNA_GC_MSK 0x00000003
++#define RG_RX_MG_LNA_GC_I_MSK 0xfffffffc
++#define RG_RX_MG_LNA_GC_SFT 0
++#define RG_RX_MG_LNA_GC_HI 1
++#define RG_RX_MG_LNA_GC_SZ 2
++#define RG_RX_MG_LNAHGN_BIAS_MSK 0x0000003c
++#define RG_RX_MG_LNAHGN_BIAS_I_MSK 0xffffffc3
++#define RG_RX_MG_LNAHGN_BIAS_SFT 2
++#define RG_RX_MG_LNAHGN_BIAS_HI 5
++#define RG_RX_MG_LNAHGN_BIAS_SZ 4
++#define RG_RX_MG_LNAHGP_BIAS_MSK 0x000003c0
++#define RG_RX_MG_LNAHGP_BIAS_I_MSK 0xfffffc3f
++#define RG_RX_MG_LNAHGP_BIAS_SFT 6
++#define RG_RX_MG_LNAHGP_BIAS_HI 9
++#define RG_RX_MG_LNAHGP_BIAS_SZ 4
++#define RG_RX_MG_LNALG_BIAS_MSK 0x00003c00
++#define RG_RX_MG_LNALG_BIAS_I_MSK 0xffffc3ff
++#define RG_RX_MG_LNALG_BIAS_SFT 10
++#define RG_RX_MG_LNALG_BIAS_HI 13
++#define RG_RX_MG_LNALG_BIAS_SZ 4
++#define RG_RX_MG_TZ_GC_MSK 0x0000c000
++#define RG_RX_MG_TZ_GC_I_MSK 0xffff3fff
++#define RG_RX_MG_TZ_GC_SFT 14
++#define RG_RX_MG_TZ_GC_HI 15
++#define RG_RX_MG_TZ_GC_SZ 2
++#define RG_RX_MG_TZ_CAP_MSK 0x00070000
++#define RG_RX_MG_TZ_CAP_I_MSK 0xfff8ffff
++#define RG_RX_MG_TZ_CAP_SFT 16
++#define RG_RX_MG_TZ_CAP_HI 18
++#define RG_RX_MG_TZ_CAP_SZ 3
++#define RG_RX_LG_LNA_GC_MSK 0x00000003
++#define RG_RX_LG_LNA_GC_I_MSK 0xfffffffc
++#define RG_RX_LG_LNA_GC_SFT 0
++#define RG_RX_LG_LNA_GC_HI 1
++#define RG_RX_LG_LNA_GC_SZ 2
++#define RG_RX_LG_LNAHGN_BIAS_MSK 0x0000003c
++#define RG_RX_LG_LNAHGN_BIAS_I_MSK 0xffffffc3
++#define RG_RX_LG_LNAHGN_BIAS_SFT 2
++#define RG_RX_LG_LNAHGN_BIAS_HI 5
++#define RG_RX_LG_LNAHGN_BIAS_SZ 4
++#define RG_RX_LG_LNAHGP_BIAS_MSK 0x000003c0
++#define RG_RX_LG_LNAHGP_BIAS_I_MSK 0xfffffc3f
++#define RG_RX_LG_LNAHGP_BIAS_SFT 6
++#define RG_RX_LG_LNAHGP_BIAS_HI 9
++#define RG_RX_LG_LNAHGP_BIAS_SZ 4
++#define RG_RX_LG_LNALG_BIAS_MSK 0x00003c00
++#define RG_RX_LG_LNALG_BIAS_I_MSK 0xffffc3ff
++#define RG_RX_LG_LNALG_BIAS_SFT 10
++#define RG_RX_LG_LNALG_BIAS_HI 13
++#define RG_RX_LG_LNALG_BIAS_SZ 4
++#define RG_RX_LG_TZ_GC_MSK 0x0000c000
++#define RG_RX_LG_TZ_GC_I_MSK 0xffff3fff
++#define RG_RX_LG_TZ_GC_SFT 14
++#define RG_RX_LG_TZ_GC_HI 15
++#define RG_RX_LG_TZ_GC_SZ 2
++#define RG_RX_LG_TZ_CAP_MSK 0x00070000
++#define RG_RX_LG_TZ_CAP_I_MSK 0xfff8ffff
++#define RG_RX_LG_TZ_CAP_SFT 16
++#define RG_RX_LG_TZ_CAP_HI 18
++#define RG_RX_LG_TZ_CAP_SZ 3
++#define RG_RX_ULG_LNA_GC_MSK 0x00000003
++#define RG_RX_ULG_LNA_GC_I_MSK 0xfffffffc
++#define RG_RX_ULG_LNA_GC_SFT 0
++#define RG_RX_ULG_LNA_GC_HI 1
++#define RG_RX_ULG_LNA_GC_SZ 2
++#define RG_RX_ULG_LNAHGN_BIAS_MSK 0x0000003c
++#define RG_RX_ULG_LNAHGN_BIAS_I_MSK 0xffffffc3
++#define RG_RX_ULG_LNAHGN_BIAS_SFT 2
++#define RG_RX_ULG_LNAHGN_BIAS_HI 5
++#define RG_RX_ULG_LNAHGN_BIAS_SZ 4
++#define RG_RX_ULG_LNAHGP_BIAS_MSK 0x000003c0
++#define RG_RX_ULG_LNAHGP_BIAS_I_MSK 0xfffffc3f
++#define RG_RX_ULG_LNAHGP_BIAS_SFT 6
++#define RG_RX_ULG_LNAHGP_BIAS_HI 9
++#define RG_RX_ULG_LNAHGP_BIAS_SZ 4
++#define RG_RX_ULG_LNALG_BIAS_MSK 0x00003c00
++#define RG_RX_ULG_LNALG_BIAS_I_MSK 0xffffc3ff
++#define RG_RX_ULG_LNALG_BIAS_SFT 10
++#define RG_RX_ULG_LNALG_BIAS_HI 13
++#define RG_RX_ULG_LNALG_BIAS_SZ 4
++#define RG_RX_ULG_TZ_GC_MSK 0x0000c000
++#define RG_RX_ULG_TZ_GC_I_MSK 0xffff3fff
++#define RG_RX_ULG_TZ_GC_SFT 14
++#define RG_RX_ULG_TZ_GC_HI 15
++#define RG_RX_ULG_TZ_GC_SZ 2
++#define RG_RX_ULG_TZ_CAP_MSK 0x00070000
++#define RG_RX_ULG_TZ_CAP_I_MSK 0xfff8ffff
++#define RG_RX_ULG_TZ_CAP_SFT 16
++#define RG_RX_ULG_TZ_CAP_HI 18
++#define RG_RX_ULG_TZ_CAP_SZ 3
++#define RG_HPF1_FAST_SET_X_MSK 0x00000001
++#define RG_HPF1_FAST_SET_X_I_MSK 0xfffffffe
++#define RG_HPF1_FAST_SET_X_SFT 0
++#define RG_HPF1_FAST_SET_X_HI 0
++#define RG_HPF1_FAST_SET_X_SZ 1
++#define RG_HPF1_FAST_SET_Y_MSK 0x00000002
++#define RG_HPF1_FAST_SET_Y_I_MSK 0xfffffffd
++#define RG_HPF1_FAST_SET_Y_SFT 1
++#define RG_HPF1_FAST_SET_Y_HI 1
++#define RG_HPF1_FAST_SET_Y_SZ 1
++#define RG_HPF1_FAST_SET_Z_MSK 0x00000004
++#define RG_HPF1_FAST_SET_Z_I_MSK 0xfffffffb
++#define RG_HPF1_FAST_SET_Z_SFT 2
++#define RG_HPF1_FAST_SET_Z_HI 2
++#define RG_HPF1_FAST_SET_Z_SZ 1
++#define RG_HPF_T1A_MSK 0x00000018
++#define RG_HPF_T1A_I_MSK 0xffffffe7
++#define RG_HPF_T1A_SFT 3
++#define RG_HPF_T1A_HI 4
++#define RG_HPF_T1A_SZ 2
++#define RG_HPF_T1B_MSK 0x00000060
++#define RG_HPF_T1B_I_MSK 0xffffff9f
++#define RG_HPF_T1B_SFT 5
++#define RG_HPF_T1B_HI 6
++#define RG_HPF_T1B_SZ 2
++#define RG_HPF_T1C_MSK 0x00000180
++#define RG_HPF_T1C_I_MSK 0xfffffe7f
++#define RG_HPF_T1C_SFT 7
++#define RG_HPF_T1C_HI 8
++#define RG_HPF_T1C_SZ 2
++#define RG_RX_LNA_TRI_SEL_MSK 0x00000600
++#define RG_RX_LNA_TRI_SEL_I_MSK 0xfffff9ff
++#define RG_RX_LNA_TRI_SEL_SFT 9
++#define RG_RX_LNA_TRI_SEL_HI 10
++#define RG_RX_LNA_TRI_SEL_SZ 2
++#define RG_RX_LNA_SETTLE_MSK 0x00001800
++#define RG_RX_LNA_SETTLE_I_MSK 0xffffe7ff
++#define RG_RX_LNA_SETTLE_SFT 11
++#define RG_RX_LNA_SETTLE_HI 12
++#define RG_RX_LNA_SETTLE_SZ 2
++#define RG_TXGAIN_PHYCTRL_MSK 0x00002000
++#define RG_TXGAIN_PHYCTRL_I_MSK 0xffffdfff
++#define RG_TXGAIN_PHYCTRL_SFT 13
++#define RG_TXGAIN_PHYCTRL_HI 13
++#define RG_TXGAIN_PHYCTRL_SZ 1
++#define RG_TX_GAIN_MSK 0x003fc000
++#define RG_TX_GAIN_I_MSK 0xffc03fff
++#define RG_TX_GAIN_SFT 14
++#define RG_TX_GAIN_HI 21
++#define RG_TX_GAIN_SZ 8
++#define RG_TXGAIN_MANUAL_MSK 0x00400000
++#define RG_TXGAIN_MANUAL_I_MSK 0xffbfffff
++#define RG_TXGAIN_MANUAL_SFT 22
++#define RG_TXGAIN_MANUAL_HI 22
++#define RG_TXGAIN_MANUAL_SZ 1
++#define RG_TX_GAIN_OFFSET_MSK 0x07800000
++#define RG_TX_GAIN_OFFSET_I_MSK 0xf87fffff
++#define RG_TX_GAIN_OFFSET_SFT 23
++#define RG_TX_GAIN_OFFSET_HI 26
++#define RG_TX_GAIN_OFFSET_SZ 4
++#define RG_ADC_CLKSEL_MSK 0x00000001
++#define RG_ADC_CLKSEL_I_MSK 0xfffffffe
++#define RG_ADC_CLKSEL_SFT 0
++#define RG_ADC_CLKSEL_HI 0
++#define RG_ADC_CLKSEL_SZ 1
++#define RG_ADC_DIBIAS_MSK 0x00000006
++#define RG_ADC_DIBIAS_I_MSK 0xfffffff9
++#define RG_ADC_DIBIAS_SFT 1
++#define RG_ADC_DIBIAS_HI 2
++#define RG_ADC_DIBIAS_SZ 2
++#define RG_ADC_DIVR_MSK 0x00000008
++#define RG_ADC_DIVR_I_MSK 0xfffffff7
++#define RG_ADC_DIVR_SFT 3
++#define RG_ADC_DIVR_HI 3
++#define RG_ADC_DIVR_SZ 1
++#define RG_ADC_DVCMI_MSK 0x00000030
++#define RG_ADC_DVCMI_I_MSK 0xffffffcf
++#define RG_ADC_DVCMI_SFT 4
++#define RG_ADC_DVCMI_HI 5
++#define RG_ADC_DVCMI_SZ 2
++#define RG_ADC_SAMSEL_MSK 0x000003c0
++#define RG_ADC_SAMSEL_I_MSK 0xfffffc3f
++#define RG_ADC_SAMSEL_SFT 6
++#define RG_ADC_SAMSEL_HI 9
++#define RG_ADC_SAMSEL_SZ 4
++#define RG_ADC_STNBY_MSK 0x00000400
++#define RG_ADC_STNBY_I_MSK 0xfffffbff
++#define RG_ADC_STNBY_SFT 10
++#define RG_ADC_STNBY_HI 10
++#define RG_ADC_STNBY_SZ 1
++#define RG_ADC_TESTMODE_MSK 0x00000800
++#define RG_ADC_TESTMODE_I_MSK 0xfffff7ff
++#define RG_ADC_TESTMODE_SFT 11
++#define RG_ADC_TESTMODE_HI 11
++#define RG_ADC_TESTMODE_SZ 1
++#define RG_ADC_TSEL_MSK 0x0000f000
++#define RG_ADC_TSEL_I_MSK 0xffff0fff
++#define RG_ADC_TSEL_SFT 12
++#define RG_ADC_TSEL_HI 15
++#define RG_ADC_TSEL_SZ 4
++#define RG_ADC_VRSEL_MSK 0x00030000
++#define RG_ADC_VRSEL_I_MSK 0xfffcffff
++#define RG_ADC_VRSEL_SFT 16
++#define RG_ADC_VRSEL_HI 17
++#define RG_ADC_VRSEL_SZ 2
++#define RG_DICMP_MSK 0x000c0000
++#define RG_DICMP_I_MSK 0xfff3ffff
++#define RG_DICMP_SFT 18
++#define RG_DICMP_HI 19
++#define RG_DICMP_SZ 2
++#define RG_DIOP_MSK 0x00300000
++#define RG_DIOP_I_MSK 0xffcfffff
++#define RG_DIOP_SFT 20
++#define RG_DIOP_HI 21
++#define RG_DIOP_SZ 2
++#define RG_SARADC_VRSEL_MSK 0x00c00000
++#define RG_SARADC_VRSEL_I_MSK 0xff3fffff
++#define RG_SARADC_VRSEL_SFT 22
++#define RG_SARADC_VRSEL_HI 23
++#define RG_SARADC_VRSEL_SZ 2
++#define RG_EN_SAR_TEST_MSK 0x03000000
++#define RG_EN_SAR_TEST_I_MSK 0xfcffffff
++#define RG_EN_SAR_TEST_SFT 24
++#define RG_EN_SAR_TEST_HI 25
++#define RG_EN_SAR_TEST_SZ 2
++#define RG_SARADC_THERMAL_MSK 0x04000000
++#define RG_SARADC_THERMAL_I_MSK 0xfbffffff
++#define RG_SARADC_THERMAL_SFT 26
++#define RG_SARADC_THERMAL_HI 26
++#define RG_SARADC_THERMAL_SZ 1
++#define RG_SARADC_TSSI_MSK 0x08000000
++#define RG_SARADC_TSSI_I_MSK 0xf7ffffff
++#define RG_SARADC_TSSI_SFT 27
++#define RG_SARADC_TSSI_HI 27
++#define RG_SARADC_TSSI_SZ 1
++#define RG_CLK_SAR_SEL_MSK 0x30000000
++#define RG_CLK_SAR_SEL_I_MSK 0xcfffffff
++#define RG_CLK_SAR_SEL_SFT 28
++#define RG_CLK_SAR_SEL_HI 29
++#define RG_CLK_SAR_SEL_SZ 2
++#define RG_EN_SARADC_MSK 0x40000000
++#define RG_EN_SARADC_I_MSK 0xbfffffff
++#define RG_EN_SARADC_SFT 30
++#define RG_EN_SARADC_HI 30
++#define RG_EN_SARADC_SZ 1
++#define RG_DACI1ST_MSK 0x00000003
++#define RG_DACI1ST_I_MSK 0xfffffffc
++#define RG_DACI1ST_SFT 0
++#define RG_DACI1ST_HI 1
++#define RG_DACI1ST_SZ 2
++#define RG_TX_DACLPF_ICOURSE_MSK 0x0000000c
++#define RG_TX_DACLPF_ICOURSE_I_MSK 0xfffffff3
++#define RG_TX_DACLPF_ICOURSE_SFT 2
++#define RG_TX_DACLPF_ICOURSE_HI 3
++#define RG_TX_DACLPF_ICOURSE_SZ 2
++#define RG_TX_DACLPF_IFINE_MSK 0x00000030
++#define RG_TX_DACLPF_IFINE_I_MSK 0xffffffcf
++#define RG_TX_DACLPF_IFINE_SFT 4
++#define RG_TX_DACLPF_IFINE_HI 5
++#define RG_TX_DACLPF_IFINE_SZ 2
++#define RG_TX_DACLPF_VCM_MSK 0x000000c0
++#define RG_TX_DACLPF_VCM_I_MSK 0xffffff3f
++#define RG_TX_DACLPF_VCM_SFT 6
++#define RG_TX_DACLPF_VCM_HI 7
++#define RG_TX_DACLPF_VCM_SZ 2
++#define RG_TX_DAC_CKEDGE_SEL_MSK 0x00000100
++#define RG_TX_DAC_CKEDGE_SEL_I_MSK 0xfffffeff
++#define RG_TX_DAC_CKEDGE_SEL_SFT 8
++#define RG_TX_DAC_CKEDGE_SEL_HI 8
++#define RG_TX_DAC_CKEDGE_SEL_SZ 1
++#define RG_TX_DAC_IBIAS_MSK 0x00000600
++#define RG_TX_DAC_IBIAS_I_MSK 0xfffff9ff
++#define RG_TX_DAC_IBIAS_SFT 9
++#define RG_TX_DAC_IBIAS_HI 10
++#define RG_TX_DAC_IBIAS_SZ 2
++#define RG_TX_DAC_OS_MSK 0x00003800
++#define RG_TX_DAC_OS_I_MSK 0xffffc7ff
++#define RG_TX_DAC_OS_SFT 11
++#define RG_TX_DAC_OS_HI 13
++#define RG_TX_DAC_OS_SZ 3
++#define RG_TX_DAC_RCAL_MSK 0x0000c000
++#define RG_TX_DAC_RCAL_I_MSK 0xffff3fff
++#define RG_TX_DAC_RCAL_SFT 14
++#define RG_TX_DAC_RCAL_HI 15
++#define RG_TX_DAC_RCAL_SZ 2
++#define RG_TX_DAC_TSEL_MSK 0x000f0000
++#define RG_TX_DAC_TSEL_I_MSK 0xfff0ffff
++#define RG_TX_DAC_TSEL_SFT 16
++#define RG_TX_DAC_TSEL_HI 19
++#define RG_TX_DAC_TSEL_SZ 4
++#define RG_TX_EN_VOLTAGE_IN_MSK 0x00100000
++#define RG_TX_EN_VOLTAGE_IN_I_MSK 0xffefffff
++#define RG_TX_EN_VOLTAGE_IN_SFT 20
++#define RG_TX_EN_VOLTAGE_IN_HI 20
++#define RG_TX_EN_VOLTAGE_IN_SZ 1
++#define RG_TXLPF_BYPASS_MSK 0x00200000
++#define RG_TXLPF_BYPASS_I_MSK 0xffdfffff
++#define RG_TXLPF_BYPASS_SFT 21
++#define RG_TXLPF_BYPASS_HI 21
++#define RG_TXLPF_BYPASS_SZ 1
++#define RG_TXLPF_BOOSTI_MSK 0x00400000
++#define RG_TXLPF_BOOSTI_I_MSK 0xffbfffff
++#define RG_TXLPF_BOOSTI_SFT 22
++#define RG_TXLPF_BOOSTI_HI 22
++#define RG_TXLPF_BOOSTI_SZ 1
++#define RG_TX_DAC_IOFFSET_MSK 0x07800000
++#define RG_TX_DAC_IOFFSET_I_MSK 0xf87fffff
++#define RG_TX_DAC_IOFFSET_SFT 23
++#define RG_TX_DAC_IOFFSET_HI 26
++#define RG_TX_DAC_IOFFSET_SZ 4
++#define RG_TX_DAC_QOFFSET_MSK 0x78000000
++#define RG_TX_DAC_QOFFSET_I_MSK 0x87ffffff
++#define RG_TX_DAC_QOFFSET_SFT 27
++#define RG_TX_DAC_QOFFSET_HI 30
++#define RG_TX_DAC_QOFFSET_SZ 4
++#define RG_EN_SX_R3_MSK 0x00000001
++#define RG_EN_SX_R3_I_MSK 0xfffffffe
++#define RG_EN_SX_R3_SFT 0
++#define RG_EN_SX_R3_HI 0
++#define RG_EN_SX_R3_SZ 1
++#define RG_EN_SX_CH_MSK 0x00000002
++#define RG_EN_SX_CH_I_MSK 0xfffffffd
++#define RG_EN_SX_CH_SFT 1
++#define RG_EN_SX_CH_HI 1
++#define RG_EN_SX_CH_SZ 1
++#define RG_EN_SX_CHP_MSK 0x00000004
++#define RG_EN_SX_CHP_I_MSK 0xfffffffb
++#define RG_EN_SX_CHP_SFT 2
++#define RG_EN_SX_CHP_HI 2
++#define RG_EN_SX_CHP_SZ 1
++#define RG_EN_SX_DIVCK_MSK 0x00000008
++#define RG_EN_SX_DIVCK_I_MSK 0xfffffff7
++#define RG_EN_SX_DIVCK_SFT 3
++#define RG_EN_SX_DIVCK_HI 3
++#define RG_EN_SX_DIVCK_SZ 1
++#define RG_EN_SX_VCOBF_MSK 0x00000010
++#define RG_EN_SX_VCOBF_I_MSK 0xffffffef
++#define RG_EN_SX_VCOBF_SFT 4
++#define RG_EN_SX_VCOBF_HI 4
++#define RG_EN_SX_VCOBF_SZ 1
++#define RG_EN_SX_VCO_MSK 0x00000020
++#define RG_EN_SX_VCO_I_MSK 0xffffffdf
++#define RG_EN_SX_VCO_SFT 5
++#define RG_EN_SX_VCO_HI 5
++#define RG_EN_SX_VCO_SZ 1
++#define RG_EN_SX_MOD_MSK 0x00000040
++#define RG_EN_SX_MOD_I_MSK 0xffffffbf
++#define RG_EN_SX_MOD_SFT 6
++#define RG_EN_SX_MOD_HI 6
++#define RG_EN_SX_MOD_SZ 1
++#define RG_EN_SX_DITHER_MSK 0x00000100
++#define RG_EN_SX_DITHER_I_MSK 0xfffffeff
++#define RG_EN_SX_DITHER_SFT 8
++#define RG_EN_SX_DITHER_HI 8
++#define RG_EN_SX_DITHER_SZ 1
++#define RG_EN_SX_VT_MON_MSK 0x00000800
++#define RG_EN_SX_VT_MON_I_MSK 0xfffff7ff
++#define RG_EN_SX_VT_MON_SFT 11
++#define RG_EN_SX_VT_MON_HI 11
++#define RG_EN_SX_VT_MON_SZ 1
++#define RG_EN_SX_VT_MON_DG_MSK 0x00001000
++#define RG_EN_SX_VT_MON_DG_I_MSK 0xffffefff
++#define RG_EN_SX_VT_MON_DG_SFT 12
++#define RG_EN_SX_VT_MON_DG_HI 12
++#define RG_EN_SX_VT_MON_DG_SZ 1
++#define RG_EN_SX_DIV_MSK 0x00002000
++#define RG_EN_SX_DIV_I_MSK 0xffffdfff
++#define RG_EN_SX_DIV_SFT 13
++#define RG_EN_SX_DIV_HI 13
++#define RG_EN_SX_DIV_SZ 1
++#define RG_EN_SX_LPF_MSK 0x00004000
++#define RG_EN_SX_LPF_I_MSK 0xffffbfff
++#define RG_EN_SX_LPF_SFT 14
++#define RG_EN_SX_LPF_HI 14
++#define RG_EN_SX_LPF_SZ 1
++#define RG_EN_DPL_MOD_MSK 0x00008000
++#define RG_EN_DPL_MOD_I_MSK 0xffff7fff
++#define RG_EN_DPL_MOD_SFT 15
++#define RG_EN_DPL_MOD_HI 15
++#define RG_EN_DPL_MOD_SZ 1
++#define RG_DPL_MOD_ORDER_MSK 0x00030000
++#define RG_DPL_MOD_ORDER_I_MSK 0xfffcffff
++#define RG_DPL_MOD_ORDER_SFT 16
++#define RG_DPL_MOD_ORDER_HI 17
++#define RG_DPL_MOD_ORDER_SZ 2
++#define RG_SX_RFCTRL_F_MSK 0x00ffffff
++#define RG_SX_RFCTRL_F_I_MSK 0xff000000
++#define RG_SX_RFCTRL_F_SFT 0
++#define RG_SX_RFCTRL_F_HI 23
++#define RG_SX_RFCTRL_F_SZ 24
++#define RG_SX_SEL_CP_MSK 0x0f000000
++#define RG_SX_SEL_CP_I_MSK 0xf0ffffff
++#define RG_SX_SEL_CP_SFT 24
++#define RG_SX_SEL_CP_HI 27
++#define RG_SX_SEL_CP_SZ 4
++#define RG_SX_SEL_CS_MSK 0xf0000000
++#define RG_SX_SEL_CS_I_MSK 0x0fffffff
++#define RG_SX_SEL_CS_SFT 28
++#define RG_SX_SEL_CS_HI 31
++#define RG_SX_SEL_CS_SZ 4
++#define RG_SX_RFCTRL_CH_MSK 0x000007ff
++#define RG_SX_RFCTRL_CH_I_MSK 0xfffff800
++#define RG_SX_RFCTRL_CH_SFT 0
++#define RG_SX_RFCTRL_CH_HI 10
++#define RG_SX_RFCTRL_CH_SZ 11
++#define RG_SX_SEL_C3_MSK 0x00007800
++#define RG_SX_SEL_C3_I_MSK 0xffff87ff
++#define RG_SX_SEL_C3_SFT 11
++#define RG_SX_SEL_C3_HI 14
++#define RG_SX_SEL_C3_SZ 4
++#define RG_SX_SEL_RS_MSK 0x000f8000
++#define RG_SX_SEL_RS_I_MSK 0xfff07fff
++#define RG_SX_SEL_RS_SFT 15
++#define RG_SX_SEL_RS_HI 19
++#define RG_SX_SEL_RS_SZ 5
++#define RG_SX_SEL_R3_MSK 0x01f00000
++#define RG_SX_SEL_R3_I_MSK 0xfe0fffff
++#define RG_SX_SEL_R3_SFT 20
++#define RG_SX_SEL_R3_HI 24
++#define RG_SX_SEL_R3_SZ 5
++#define RG_SX_SEL_ICHP_MSK 0x0000001f
++#define RG_SX_SEL_ICHP_I_MSK 0xffffffe0
++#define RG_SX_SEL_ICHP_SFT 0
++#define RG_SX_SEL_ICHP_HI 4
++#define RG_SX_SEL_ICHP_SZ 5
++#define RG_SX_SEL_PCHP_MSK 0x000003e0
++#define RG_SX_SEL_PCHP_I_MSK 0xfffffc1f
++#define RG_SX_SEL_PCHP_SFT 5
++#define RG_SX_SEL_PCHP_HI 9
++#define RG_SX_SEL_PCHP_SZ 5
++#define RG_SX_SEL_CHP_REGOP_MSK 0x00003c00
++#define RG_SX_SEL_CHP_REGOP_I_MSK 0xffffc3ff
++#define RG_SX_SEL_CHP_REGOP_SFT 10
++#define RG_SX_SEL_CHP_REGOP_HI 13
++#define RG_SX_SEL_CHP_REGOP_SZ 4
++#define RG_SX_SEL_CHP_UNIOP_MSK 0x0003c000
++#define RG_SX_SEL_CHP_UNIOP_I_MSK 0xfffc3fff
++#define RG_SX_SEL_CHP_UNIOP_SFT 14
++#define RG_SX_SEL_CHP_UNIOP_HI 17
++#define RG_SX_SEL_CHP_UNIOP_SZ 4
++#define RG_SX_CHP_IOST_POL_MSK 0x00040000
++#define RG_SX_CHP_IOST_POL_I_MSK 0xfffbffff
++#define RG_SX_CHP_IOST_POL_SFT 18
++#define RG_SX_CHP_IOST_POL_HI 18
++#define RG_SX_CHP_IOST_POL_SZ 1
++#define RG_SX_CHP_IOST_MSK 0x00380000
++#define RG_SX_CHP_IOST_I_MSK 0xffc7ffff
++#define RG_SX_CHP_IOST_SFT 19
++#define RG_SX_CHP_IOST_HI 21
++#define RG_SX_CHP_IOST_SZ 3
++#define RG_SX_PFDSEL_MSK 0x00400000
++#define RG_SX_PFDSEL_I_MSK 0xffbfffff
++#define RG_SX_PFDSEL_SFT 22
++#define RG_SX_PFDSEL_HI 22
++#define RG_SX_PFDSEL_SZ 1
++#define RG_SX_PFD_SET_MSK 0x00800000
++#define RG_SX_PFD_SET_I_MSK 0xff7fffff
++#define RG_SX_PFD_SET_SFT 23
++#define RG_SX_PFD_SET_HI 23
++#define RG_SX_PFD_SET_SZ 1
++#define RG_SX_PFD_SET1_MSK 0x01000000
++#define RG_SX_PFD_SET1_I_MSK 0xfeffffff
++#define RG_SX_PFD_SET1_SFT 24
++#define RG_SX_PFD_SET1_HI 24
++#define RG_SX_PFD_SET1_SZ 1
++#define RG_SX_PFD_SET2_MSK 0x02000000
++#define RG_SX_PFD_SET2_I_MSK 0xfdffffff
++#define RG_SX_PFD_SET2_SFT 25
++#define RG_SX_PFD_SET2_HI 25
++#define RG_SX_PFD_SET2_SZ 1
++#define RG_SX_VBNCAS_SEL_MSK 0x04000000
++#define RG_SX_VBNCAS_SEL_I_MSK 0xfbffffff
++#define RG_SX_VBNCAS_SEL_SFT 26
++#define RG_SX_VBNCAS_SEL_HI 26
++#define RG_SX_VBNCAS_SEL_SZ 1
++#define RG_SX_PFD_RST_H_MSK 0x08000000
++#define RG_SX_PFD_RST_H_I_MSK 0xf7ffffff
++#define RG_SX_PFD_RST_H_SFT 27
++#define RG_SX_PFD_RST_H_HI 27
++#define RG_SX_PFD_RST_H_SZ 1
++#define RG_SX_PFD_TRUP_MSK 0x10000000
++#define RG_SX_PFD_TRUP_I_MSK 0xefffffff
++#define RG_SX_PFD_TRUP_SFT 28
++#define RG_SX_PFD_TRUP_HI 28
++#define RG_SX_PFD_TRUP_SZ 1
++#define RG_SX_PFD_TRDN_MSK 0x20000000
++#define RG_SX_PFD_TRDN_I_MSK 0xdfffffff
++#define RG_SX_PFD_TRDN_SFT 29
++#define RG_SX_PFD_TRDN_HI 29
++#define RG_SX_PFD_TRDN_SZ 1
++#define RG_SX_PFD_TRSEL_MSK 0x40000000
++#define RG_SX_PFD_TRSEL_I_MSK 0xbfffffff
++#define RG_SX_PFD_TRSEL_SFT 30
++#define RG_SX_PFD_TRSEL_HI 30
++#define RG_SX_PFD_TRSEL_SZ 1
++#define RG_SX_VCOBA_R_MSK 0x00000007
++#define RG_SX_VCOBA_R_I_MSK 0xfffffff8
++#define RG_SX_VCOBA_R_SFT 0
++#define RG_SX_VCOBA_R_HI 2
++#define RG_SX_VCOBA_R_SZ 3
++#define RG_SX_VCORSEL_MSK 0x000000f8
++#define RG_SX_VCORSEL_I_MSK 0xffffff07
++#define RG_SX_VCORSEL_SFT 3
++#define RG_SX_VCORSEL_HI 7
++#define RG_SX_VCORSEL_SZ 5
++#define RG_SX_VCOCUSEL_MSK 0x00000f00
++#define RG_SX_VCOCUSEL_I_MSK 0xfffff0ff
++#define RG_SX_VCOCUSEL_SFT 8
++#define RG_SX_VCOCUSEL_HI 11
++#define RG_SX_VCOCUSEL_SZ 4
++#define RG_SX_RXBFSEL_MSK 0x0000f000
++#define RG_SX_RXBFSEL_I_MSK 0xffff0fff
++#define RG_SX_RXBFSEL_SFT 12
++#define RG_SX_RXBFSEL_HI 15
++#define RG_SX_RXBFSEL_SZ 4
++#define RG_SX_TXBFSEL_MSK 0x000f0000
++#define RG_SX_TXBFSEL_I_MSK 0xfff0ffff
++#define RG_SX_TXBFSEL_SFT 16
++#define RG_SX_TXBFSEL_HI 19
++#define RG_SX_TXBFSEL_SZ 4
++#define RG_SX_VCOBFSEL_MSK 0x00f00000
++#define RG_SX_VCOBFSEL_I_MSK 0xff0fffff
++#define RG_SX_VCOBFSEL_SFT 20
++#define RG_SX_VCOBFSEL_HI 23
++#define RG_SX_VCOBFSEL_SZ 4
++#define RG_SX_DIVBFSEL_MSK 0x0f000000
++#define RG_SX_DIVBFSEL_I_MSK 0xf0ffffff
++#define RG_SX_DIVBFSEL_SFT 24
++#define RG_SX_DIVBFSEL_HI 27
++#define RG_SX_DIVBFSEL_SZ 4
++#define RG_SX_GNDR_SEL_MSK 0xf0000000
++#define RG_SX_GNDR_SEL_I_MSK 0x0fffffff
++#define RG_SX_GNDR_SEL_SFT 28
++#define RG_SX_GNDR_SEL_HI 31
++#define RG_SX_GNDR_SEL_SZ 4
++#define RG_SX_DITHER_WEIGHT_MSK 0x00000003
++#define RG_SX_DITHER_WEIGHT_I_MSK 0xfffffffc
++#define RG_SX_DITHER_WEIGHT_SFT 0
++#define RG_SX_DITHER_WEIGHT_HI 1
++#define RG_SX_DITHER_WEIGHT_SZ 2
++#define RG_SX_MOD_ORDER_MSK 0x00000030
++#define RG_SX_MOD_ORDER_I_MSK 0xffffffcf
++#define RG_SX_MOD_ORDER_SFT 4
++#define RG_SX_MOD_ORDER_HI 5
++#define RG_SX_MOD_ORDER_SZ 2
++#define RG_SX_RST_H_DIV_MSK 0x00000200
++#define RG_SX_RST_H_DIV_I_MSK 0xfffffdff
++#define RG_SX_RST_H_DIV_SFT 9
++#define RG_SX_RST_H_DIV_HI 9
++#define RG_SX_RST_H_DIV_SZ 1
++#define RG_SX_SDM_EDGE_MSK 0x00000400
++#define RG_SX_SDM_EDGE_I_MSK 0xfffffbff
++#define RG_SX_SDM_EDGE_SFT 10
++#define RG_SX_SDM_EDGE_HI 10
++#define RG_SX_SDM_EDGE_SZ 1
++#define RG_SX_XO_GM_MSK 0x00001800
++#define RG_SX_XO_GM_I_MSK 0xffffe7ff
++#define RG_SX_XO_GM_SFT 11
++#define RG_SX_XO_GM_HI 12
++#define RG_SX_XO_GM_SZ 2
++#define RG_SX_REFBYTWO_MSK 0x00002000
++#define RG_SX_REFBYTWO_I_MSK 0xffffdfff
++#define RG_SX_REFBYTWO_SFT 13
++#define RG_SX_REFBYTWO_HI 13
++#define RG_SX_REFBYTWO_SZ 1
++#define RG_SX_LCKEN_MSK 0x00080000
++#define RG_SX_LCKEN_I_MSK 0xfff7ffff
++#define RG_SX_LCKEN_SFT 19
++#define RG_SX_LCKEN_HI 19
++#define RG_SX_LCKEN_SZ 1
++#define RG_SX_PREVDD_MSK 0x00f00000
++#define RG_SX_PREVDD_I_MSK 0xff0fffff
++#define RG_SX_PREVDD_SFT 20
++#define RG_SX_PREVDD_HI 23
++#define RG_SX_PREVDD_SZ 4
++#define RG_SX_PSCONTERVDD_MSK 0x0f000000
++#define RG_SX_PSCONTERVDD_I_MSK 0xf0ffffff
++#define RG_SX_PSCONTERVDD_SFT 24
++#define RG_SX_PSCONTERVDD_HI 27
++#define RG_SX_PSCONTERVDD_SZ 4
++#define RG_SX_PH_MSK 0x00002000
++#define RG_SX_PH_I_MSK 0xffffdfff
++#define RG_SX_PH_SFT 13
++#define RG_SX_PH_HI 13
++#define RG_SX_PH_SZ 1
++#define RG_SX_PL_MSK 0x00004000
++#define RG_SX_PL_I_MSK 0xffffbfff
++#define RG_SX_PL_SFT 14
++#define RG_SX_PL_HI 14
++#define RG_SX_PL_SZ 1
++#define RG_XOSC_CBANK_XO_MSK 0x00078000
++#define RG_XOSC_CBANK_XO_I_MSK 0xfff87fff
++#define RG_XOSC_CBANK_XO_SFT 15
++#define RG_XOSC_CBANK_XO_HI 18
++#define RG_XOSC_CBANK_XO_SZ 4
++#define RG_XOSC_CBANK_XI_MSK 0x00780000
++#define RG_XOSC_CBANK_XI_I_MSK 0xff87ffff
++#define RG_XOSC_CBANK_XI_SFT 19
++#define RG_XOSC_CBANK_XI_HI 22
++#define RG_XOSC_CBANK_XI_SZ 4
++#define RG_SX_VT_MON_MODE_MSK 0x00000001
++#define RG_SX_VT_MON_MODE_I_MSK 0xfffffffe
++#define RG_SX_VT_MON_MODE_SFT 0
++#define RG_SX_VT_MON_MODE_HI 0
++#define RG_SX_VT_MON_MODE_SZ 1
++#define RG_SX_VT_TH_HI_MSK 0x00000006
++#define RG_SX_VT_TH_HI_I_MSK 0xfffffff9
++#define RG_SX_VT_TH_HI_SFT 1
++#define RG_SX_VT_TH_HI_HI 2
++#define RG_SX_VT_TH_HI_SZ 2
++#define RG_SX_VT_TH_LO_MSK 0x00000018
++#define RG_SX_VT_TH_LO_I_MSK 0xffffffe7
++#define RG_SX_VT_TH_LO_SFT 3
++#define RG_SX_VT_TH_LO_HI 4
++#define RG_SX_VT_TH_LO_SZ 2
++#define RG_SX_VT_SET_MSK 0x00000020
++#define RG_SX_VT_SET_I_MSK 0xffffffdf
++#define RG_SX_VT_SET_SFT 5
++#define RG_SX_VT_SET_HI 5
++#define RG_SX_VT_SET_SZ 1
++#define RG_SX_VT_MON_TMR_MSK 0x00007fc0
++#define RG_SX_VT_MON_TMR_I_MSK 0xffff803f
++#define RG_SX_VT_MON_TMR_SFT 6
++#define RG_SX_VT_MON_TMR_HI 14
++#define RG_SX_VT_MON_TMR_SZ 9
++#define RG_EN_DP_VT_MON_MSK 0x00000001
++#define RG_EN_DP_VT_MON_I_MSK 0xfffffffe
++#define RG_EN_DP_VT_MON_SFT 0
++#define RG_EN_DP_VT_MON_HI 0
++#define RG_EN_DP_VT_MON_SZ 1
++#define RG_DP_VT_TH_HI_MSK 0x00000006
++#define RG_DP_VT_TH_HI_I_MSK 0xfffffff9
++#define RG_DP_VT_TH_HI_SFT 1
++#define RG_DP_VT_TH_HI_HI 2
++#define RG_DP_VT_TH_HI_SZ 2
++#define RG_DP_VT_TH_LO_MSK 0x00000018
++#define RG_DP_VT_TH_LO_I_MSK 0xffffffe7
++#define RG_DP_VT_TH_LO_SFT 3
++#define RG_DP_VT_TH_LO_HI 4
++#define RG_DP_VT_TH_LO_SZ 2
++#define RG_DP_CK320BY2_MSK 0x00004000
++#define RG_DP_CK320BY2_I_MSK 0xffffbfff
++#define RG_DP_CK320BY2_SFT 14
++#define RG_DP_CK320BY2_HI 14
++#define RG_DP_CK320BY2_SZ 1
++#define RG_DP_OD_TEST_MSK 0x00200000
++#define RG_DP_OD_TEST_I_MSK 0xffdfffff
++#define RG_DP_OD_TEST_SFT 21
++#define RG_DP_OD_TEST_HI 21
++#define RG_DP_OD_TEST_SZ 1
++#define RG_DP_BBPLL_BP_MSK 0x00000001
++#define RG_DP_BBPLL_BP_I_MSK 0xfffffffe
++#define RG_DP_BBPLL_BP_SFT 0
++#define RG_DP_BBPLL_BP_HI 0
++#define RG_DP_BBPLL_BP_SZ 1
++#define RG_DP_BBPLL_ICP_MSK 0x00000006
++#define RG_DP_BBPLL_ICP_I_MSK 0xfffffff9
++#define RG_DP_BBPLL_ICP_SFT 1
++#define RG_DP_BBPLL_ICP_HI 2
++#define RG_DP_BBPLL_ICP_SZ 2
++#define RG_DP_BBPLL_IDUAL_MSK 0x00000018
++#define RG_DP_BBPLL_IDUAL_I_MSK 0xffffffe7
++#define RG_DP_BBPLL_IDUAL_SFT 3
++#define RG_DP_BBPLL_IDUAL_HI 4
++#define RG_DP_BBPLL_IDUAL_SZ 2
++#define RG_DP_BBPLL_OD_TEST_MSK 0x000001e0
++#define RG_DP_BBPLL_OD_TEST_I_MSK 0xfffffe1f
++#define RG_DP_BBPLL_OD_TEST_SFT 5
++#define RG_DP_BBPLL_OD_TEST_HI 8
++#define RG_DP_BBPLL_OD_TEST_SZ 4
++#define RG_DP_BBPLL_PD_MSK 0x00000200
++#define RG_DP_BBPLL_PD_I_MSK 0xfffffdff
++#define RG_DP_BBPLL_PD_SFT 9
++#define RG_DP_BBPLL_PD_HI 9
++#define RG_DP_BBPLL_PD_SZ 1
++#define RG_DP_BBPLL_TESTSEL_MSK 0x00001c00
++#define RG_DP_BBPLL_TESTSEL_I_MSK 0xffffe3ff
++#define RG_DP_BBPLL_TESTSEL_SFT 10
++#define RG_DP_BBPLL_TESTSEL_HI 12
++#define RG_DP_BBPLL_TESTSEL_SZ 3
++#define RG_DP_BBPLL_PFD_DLY_MSK 0x00006000
++#define RG_DP_BBPLL_PFD_DLY_I_MSK 0xffff9fff
++#define RG_DP_BBPLL_PFD_DLY_SFT 13
++#define RG_DP_BBPLL_PFD_DLY_HI 14
++#define RG_DP_BBPLL_PFD_DLY_SZ 2
++#define RG_DP_RP_MSK 0x00038000
++#define RG_DP_RP_I_MSK 0xfffc7fff
++#define RG_DP_RP_SFT 15
++#define RG_DP_RP_HI 17
++#define RG_DP_RP_SZ 3
++#define RG_DP_RHP_MSK 0x000c0000
++#define RG_DP_RHP_I_MSK 0xfff3ffff
++#define RG_DP_RHP_SFT 18
++#define RG_DP_RHP_HI 19
++#define RG_DP_RHP_SZ 2
++#define RG_DP_BBPLL_SDM_EDGE_MSK 0x80000000
++#define RG_DP_BBPLL_SDM_EDGE_I_MSK 0x7fffffff
++#define RG_DP_BBPLL_SDM_EDGE_SFT 31
++#define RG_DP_BBPLL_SDM_EDGE_HI 31
++#define RG_DP_BBPLL_SDM_EDGE_SZ 1
++#define RG_DP_FODIV_MSK 0x0007f000
++#define RG_DP_FODIV_I_MSK 0xfff80fff
++#define RG_DP_FODIV_SFT 12
++#define RG_DP_FODIV_HI 18
++#define RG_DP_FODIV_SZ 7
++#define RG_DP_REFDIV_MSK 0x1fc00000
++#define RG_DP_REFDIV_I_MSK 0xe03fffff
++#define RG_DP_REFDIV_SFT 22
++#define RG_DP_REFDIV_HI 28
++#define RG_DP_REFDIV_SZ 7
++#define RG_IDACAI_PGAG15_MSK 0x0000003f
++#define RG_IDACAI_PGAG15_I_MSK 0xffffffc0
++#define RG_IDACAI_PGAG15_SFT 0
++#define RG_IDACAI_PGAG15_HI 5
++#define RG_IDACAI_PGAG15_SZ 6
++#define RG_IDACAQ_PGAG15_MSK 0x00000fc0
++#define RG_IDACAQ_PGAG15_I_MSK 0xfffff03f
++#define RG_IDACAQ_PGAG15_SFT 6
++#define RG_IDACAQ_PGAG15_HI 11
++#define RG_IDACAQ_PGAG15_SZ 6
++#define RG_IDACAI_PGAG14_MSK 0x0003f000
++#define RG_IDACAI_PGAG14_I_MSK 0xfffc0fff
++#define RG_IDACAI_PGAG14_SFT 12
++#define RG_IDACAI_PGAG14_HI 17
++#define RG_IDACAI_PGAG14_SZ 6
++#define RG_IDACAQ_PGAG14_MSK 0x00fc0000
++#define RG_IDACAQ_PGAG14_I_MSK 0xff03ffff
++#define RG_IDACAQ_PGAG14_SFT 18
++#define RG_IDACAQ_PGAG14_HI 23
++#define RG_IDACAQ_PGAG14_SZ 6
++#define RG_DP_BBPLL_BS_MSK 0x3f000000
++#define RG_DP_BBPLL_BS_I_MSK 0xc0ffffff
++#define RG_DP_BBPLL_BS_SFT 24
++#define RG_DP_BBPLL_BS_HI 29
++#define RG_DP_BBPLL_BS_SZ 6
++#define RG_IDACAI_PGAG13_MSK 0x0000003f
++#define RG_IDACAI_PGAG13_I_MSK 0xffffffc0
++#define RG_IDACAI_PGAG13_SFT 0
++#define RG_IDACAI_PGAG13_HI 5
++#define RG_IDACAI_PGAG13_SZ 6
++#define RG_IDACAQ_PGAG13_MSK 0x00000fc0
++#define RG_IDACAQ_PGAG13_I_MSK 0xfffff03f
++#define RG_IDACAQ_PGAG13_SFT 6
++#define RG_IDACAQ_PGAG13_HI 11
++#define RG_IDACAQ_PGAG13_SZ 6
++#define RG_IDACAI_PGAG12_MSK 0x0003f000
++#define RG_IDACAI_PGAG12_I_MSK 0xfffc0fff
++#define RG_IDACAI_PGAG12_SFT 12
++#define RG_IDACAI_PGAG12_HI 17
++#define RG_IDACAI_PGAG12_SZ 6
++#define RG_IDACAQ_PGAG12_MSK 0x00fc0000
++#define RG_IDACAQ_PGAG12_I_MSK 0xff03ffff
++#define RG_IDACAQ_PGAG12_SFT 18
++#define RG_IDACAQ_PGAG12_HI 23
++#define RG_IDACAQ_PGAG12_SZ 6
++#define RG_IDACAI_PGAG11_MSK 0x0000003f
++#define RG_IDACAI_PGAG11_I_MSK 0xffffffc0
++#define RG_IDACAI_PGAG11_SFT 0
++#define RG_IDACAI_PGAG11_HI 5
++#define RG_IDACAI_PGAG11_SZ 6
++#define RG_IDACAQ_PGAG11_MSK 0x00000fc0
++#define RG_IDACAQ_PGAG11_I_MSK 0xfffff03f
++#define RG_IDACAQ_PGAG11_SFT 6
++#define RG_IDACAQ_PGAG11_HI 11
++#define RG_IDACAQ_PGAG11_SZ 6
++#define RG_IDACAI_PGAG10_MSK 0x0003f000
++#define RG_IDACAI_PGAG10_I_MSK 0xfffc0fff
++#define RG_IDACAI_PGAG10_SFT 12
++#define RG_IDACAI_PGAG10_HI 17
++#define RG_IDACAI_PGAG10_SZ 6
++#define RG_IDACAQ_PGAG10_MSK 0x00fc0000
++#define RG_IDACAQ_PGAG10_I_MSK 0xff03ffff
++#define RG_IDACAQ_PGAG10_SFT 18
++#define RG_IDACAQ_PGAG10_HI 23
++#define RG_IDACAQ_PGAG10_SZ 6
++#define RG_IDACAI_PGAG9_MSK 0x0000003f
++#define RG_IDACAI_PGAG9_I_MSK 0xffffffc0
++#define RG_IDACAI_PGAG9_SFT 0
++#define RG_IDACAI_PGAG9_HI 5
++#define RG_IDACAI_PGAG9_SZ 6
++#define RG_IDACAQ_PGAG9_MSK 0x00000fc0
++#define RG_IDACAQ_PGAG9_I_MSK 0xfffff03f
++#define RG_IDACAQ_PGAG9_SFT 6
++#define RG_IDACAQ_PGAG9_HI 11
++#define RG_IDACAQ_PGAG9_SZ 6
++#define RG_IDACAI_PGAG8_MSK 0x0003f000
++#define RG_IDACAI_PGAG8_I_MSK 0xfffc0fff
++#define RG_IDACAI_PGAG8_SFT 12
++#define RG_IDACAI_PGAG8_HI 17
++#define RG_IDACAI_PGAG8_SZ 6
++#define RG_IDACAQ_PGAG8_MSK 0x00fc0000
++#define RG_IDACAQ_PGAG8_I_MSK 0xff03ffff
++#define RG_IDACAQ_PGAG8_SFT 18
++#define RG_IDACAQ_PGAG8_HI 23
++#define RG_IDACAQ_PGAG8_SZ 6
++#define RG_IDACAI_PGAG7_MSK 0x0000003f
++#define RG_IDACAI_PGAG7_I_MSK 0xffffffc0
++#define RG_IDACAI_PGAG7_SFT 0
++#define RG_IDACAI_PGAG7_HI 5
++#define RG_IDACAI_PGAG7_SZ 6
++#define RG_IDACAQ_PGAG7_MSK 0x00000fc0
++#define RG_IDACAQ_PGAG7_I_MSK 0xfffff03f
++#define RG_IDACAQ_PGAG7_SFT 6
++#define RG_IDACAQ_PGAG7_HI 11
++#define RG_IDACAQ_PGAG7_SZ 6
++#define RG_IDACAI_PGAG6_MSK 0x0003f000
++#define RG_IDACAI_PGAG6_I_MSK 0xfffc0fff
++#define RG_IDACAI_PGAG6_SFT 12
++#define RG_IDACAI_PGAG6_HI 17
++#define RG_IDACAI_PGAG6_SZ 6
++#define RG_IDACAQ_PGAG6_MSK 0x00fc0000
++#define RG_IDACAQ_PGAG6_I_MSK 0xff03ffff
++#define RG_IDACAQ_PGAG6_SFT 18
++#define RG_IDACAQ_PGAG6_HI 23
++#define RG_IDACAQ_PGAG6_SZ 6
++#define RG_IDACAI_PGAG5_MSK 0x0000003f
++#define RG_IDACAI_PGAG5_I_MSK 0xffffffc0
++#define RG_IDACAI_PGAG5_SFT 0
++#define RG_IDACAI_PGAG5_HI 5
++#define RG_IDACAI_PGAG5_SZ 6
++#define RG_IDACAQ_PGAG5_MSK 0x00000fc0
++#define RG_IDACAQ_PGAG5_I_MSK 0xfffff03f
++#define RG_IDACAQ_PGAG5_SFT 6
++#define RG_IDACAQ_PGAG5_HI 11
++#define RG_IDACAQ_PGAG5_SZ 6
++#define RG_IDACAI_PGAG4_MSK 0x0003f000
++#define RG_IDACAI_PGAG4_I_MSK 0xfffc0fff
++#define RG_IDACAI_PGAG4_SFT 12
++#define RG_IDACAI_PGAG4_HI 17
++#define RG_IDACAI_PGAG4_SZ 6
++#define RG_IDACAQ_PGAG4_MSK 0x00fc0000
++#define RG_IDACAQ_PGAG4_I_MSK 0xff03ffff
++#define RG_IDACAQ_PGAG4_SFT 18
++#define RG_IDACAQ_PGAG4_HI 23
++#define RG_IDACAQ_PGAG4_SZ 6
++#define RG_IDACAI_PGAG3_MSK 0x0000003f
++#define RG_IDACAI_PGAG3_I_MSK 0xffffffc0
++#define RG_IDACAI_PGAG3_SFT 0
++#define RG_IDACAI_PGAG3_HI 5
++#define RG_IDACAI_PGAG3_SZ 6
++#define RG_IDACAQ_PGAG3_MSK 0x00000fc0
++#define RG_IDACAQ_PGAG3_I_MSK 0xfffff03f
++#define RG_IDACAQ_PGAG3_SFT 6
++#define RG_IDACAQ_PGAG3_HI 11
++#define RG_IDACAQ_PGAG3_SZ 6
++#define RG_IDACAI_PGAG2_MSK 0x0003f000
++#define RG_IDACAI_PGAG2_I_MSK 0xfffc0fff
++#define RG_IDACAI_PGAG2_SFT 12
++#define RG_IDACAI_PGAG2_HI 17
++#define RG_IDACAI_PGAG2_SZ 6
++#define RG_IDACAQ_PGAG2_MSK 0x00fc0000
++#define RG_IDACAQ_PGAG2_I_MSK 0xff03ffff
++#define RG_IDACAQ_PGAG2_SFT 18
++#define RG_IDACAQ_PGAG2_HI 23
++#define RG_IDACAQ_PGAG2_SZ 6
++#define RG_IDACAI_PGAG1_MSK 0x0000003f
++#define RG_IDACAI_PGAG1_I_MSK 0xffffffc0
++#define RG_IDACAI_PGAG1_SFT 0
++#define RG_IDACAI_PGAG1_HI 5
++#define RG_IDACAI_PGAG1_SZ 6
++#define RG_IDACAQ_PGAG1_MSK 0x00000fc0
++#define RG_IDACAQ_PGAG1_I_MSK 0xfffff03f
++#define RG_IDACAQ_PGAG1_SFT 6
++#define RG_IDACAQ_PGAG1_HI 11
++#define RG_IDACAQ_PGAG1_SZ 6
++#define RG_IDACAI_PGAG0_MSK 0x0003f000
++#define RG_IDACAI_PGAG0_I_MSK 0xfffc0fff
++#define RG_IDACAI_PGAG0_SFT 12
++#define RG_IDACAI_PGAG0_HI 17
++#define RG_IDACAI_PGAG0_SZ 6
++#define RG_IDACAQ_PGAG0_MSK 0x00fc0000
++#define RG_IDACAQ_PGAG0_I_MSK 0xff03ffff
++#define RG_IDACAQ_PGAG0_SFT 18
++#define RG_IDACAQ_PGAG0_HI 23
++#define RG_IDACAQ_PGAG0_SZ 6
++#define RG_EN_RCAL_MSK 0x00000001
++#define RG_EN_RCAL_I_MSK 0xfffffffe
++#define RG_EN_RCAL_SFT 0
++#define RG_EN_RCAL_HI 0
++#define RG_EN_RCAL_SZ 1
++#define RG_RCAL_SPD_MSK 0x00000002
++#define RG_RCAL_SPD_I_MSK 0xfffffffd
++#define RG_RCAL_SPD_SFT 1
++#define RG_RCAL_SPD_HI 1
++#define RG_RCAL_SPD_SZ 1
++#define RG_RCAL_TMR_MSK 0x000001fc
++#define RG_RCAL_TMR_I_MSK 0xfffffe03
++#define RG_RCAL_TMR_SFT 2
++#define RG_RCAL_TMR_HI 8
++#define RG_RCAL_TMR_SZ 7
++#define RG_RCAL_CODE_CWR_MSK 0x00000200
++#define RG_RCAL_CODE_CWR_I_MSK 0xfffffdff
++#define RG_RCAL_CODE_CWR_SFT 9
++#define RG_RCAL_CODE_CWR_HI 9
++#define RG_RCAL_CODE_CWR_SZ 1
++#define RG_RCAL_CODE_CWD_MSK 0x00007c00
++#define RG_RCAL_CODE_CWD_I_MSK 0xffff83ff
++#define RG_RCAL_CODE_CWD_SFT 10
++#define RG_RCAL_CODE_CWD_HI 14
++#define RG_RCAL_CODE_CWD_SZ 5
++#define RG_SX_SUB_SEL_CWR_MSK 0x00000001
++#define RG_SX_SUB_SEL_CWR_I_MSK 0xfffffffe
++#define RG_SX_SUB_SEL_CWR_SFT 0
++#define RG_SX_SUB_SEL_CWR_HI 0
++#define RG_SX_SUB_SEL_CWR_SZ 1
++#define RG_SX_SUB_SEL_CWD_MSK 0x000000fe
++#define RG_SX_SUB_SEL_CWD_I_MSK 0xffffff01
++#define RG_SX_SUB_SEL_CWD_SFT 1
++#define RG_SX_SUB_SEL_CWD_HI 7
++#define RG_SX_SUB_SEL_CWD_SZ 7
++#define RG_SX_LCK_BIN_OFFSET_MSK 0x00078000
++#define RG_SX_LCK_BIN_OFFSET_I_MSK 0xfff87fff
++#define RG_SX_LCK_BIN_OFFSET_SFT 15
++#define RG_SX_LCK_BIN_OFFSET_HI 18
++#define RG_SX_LCK_BIN_OFFSET_SZ 4
++#define RG_SX_LCK_BIN_PRECISION_MSK 0x00080000
++#define RG_SX_LCK_BIN_PRECISION_I_MSK 0xfff7ffff
++#define RG_SX_LCK_BIN_PRECISION_SFT 19
++#define RG_SX_LCK_BIN_PRECISION_HI 19
++#define RG_SX_LCK_BIN_PRECISION_SZ 1
++#define RG_SX_LOCK_EN_N_MSK 0x00100000
++#define RG_SX_LOCK_EN_N_I_MSK 0xffefffff
++#define RG_SX_LOCK_EN_N_SFT 20
++#define RG_SX_LOCK_EN_N_HI 20
++#define RG_SX_LOCK_EN_N_SZ 1
++#define RG_SX_LOCK_MANUAL_MSK 0x00200000
++#define RG_SX_LOCK_MANUAL_I_MSK 0xffdfffff
++#define RG_SX_LOCK_MANUAL_SFT 21
++#define RG_SX_LOCK_MANUAL_HI 21
++#define RG_SX_LOCK_MANUAL_SZ 1
++#define RG_SX_SUB_MANUAL_MSK 0x00400000
++#define RG_SX_SUB_MANUAL_I_MSK 0xffbfffff
++#define RG_SX_SUB_MANUAL_SFT 22
++#define RG_SX_SUB_MANUAL_HI 22
++#define RG_SX_SUB_MANUAL_SZ 1
++#define RG_SX_SUB_SEL_MSK 0x3f800000
++#define RG_SX_SUB_SEL_I_MSK 0xc07fffff
++#define RG_SX_SUB_SEL_SFT 23
++#define RG_SX_SUB_SEL_HI 29
++#define RG_SX_SUB_SEL_SZ 7
++#define RG_SX_MUX_SEL_VTH_BINL_MSK 0x40000000
++#define RG_SX_MUX_SEL_VTH_BINL_I_MSK 0xbfffffff
++#define RG_SX_MUX_SEL_VTH_BINL_SFT 30
++#define RG_SX_MUX_SEL_VTH_BINL_HI 30
++#define RG_SX_MUX_SEL_VTH_BINL_SZ 1
++#define RG_TRX_DUMMMY_MSK 0xffffffff
++#define RG_TRX_DUMMMY_I_MSK 0x00000000
++#define RG_TRX_DUMMMY_SFT 0
++#define RG_TRX_DUMMMY_HI 31
++#define RG_TRX_DUMMMY_SZ 32
++#define RG_SX_DUMMMY_MSK 0xffffffff
++#define RG_SX_DUMMMY_I_MSK 0x00000000
++#define RG_SX_DUMMMY_SFT 0
++#define RG_SX_DUMMMY_HI 31
++#define RG_SX_DUMMMY_SZ 32
++#define RCAL_RDY_MSK 0x00000001
++#define RCAL_RDY_I_MSK 0xfffffffe
++#define RCAL_RDY_SFT 0
++#define RCAL_RDY_HI 0
++#define RCAL_RDY_SZ 1
++#define LCK_BIN_RDY_MSK 0x00000002
++#define LCK_BIN_RDY_I_MSK 0xfffffffd
++#define LCK_BIN_RDY_SFT 1
++#define LCK_BIN_RDY_HI 1
++#define LCK_BIN_RDY_SZ 1
++#define VT_MON_RDY_MSK 0x00000004
++#define VT_MON_RDY_I_MSK 0xfffffffb
++#define VT_MON_RDY_SFT 2
++#define VT_MON_RDY_HI 2
++#define VT_MON_RDY_SZ 1
++#define DA_R_CODE_LUT_MSK 0x000007c0
++#define DA_R_CODE_LUT_I_MSK 0xfffff83f
++#define DA_R_CODE_LUT_SFT 6
++#define DA_R_CODE_LUT_HI 10
++#define DA_R_CODE_LUT_SZ 5
++#define AD_SX_VT_MON_Q_MSK 0x00001800
++#define AD_SX_VT_MON_Q_I_MSK 0xffffe7ff
++#define AD_SX_VT_MON_Q_SFT 11
++#define AD_SX_VT_MON_Q_HI 12
++#define AD_SX_VT_MON_Q_SZ 2
++#define AD_DP_VT_MON_Q_MSK 0x00006000
++#define AD_DP_VT_MON_Q_I_MSK 0xffff9fff
++#define AD_DP_VT_MON_Q_SFT 13
++#define AD_DP_VT_MON_Q_HI 14
++#define AD_DP_VT_MON_Q_SZ 2
++#define RTC_CAL_RDY_MSK 0x00008000
++#define RTC_CAL_RDY_I_MSK 0xffff7fff
++#define RTC_CAL_RDY_SFT 15
++#define RTC_CAL_RDY_HI 15
++#define RTC_CAL_RDY_SZ 1
++#define RG_SARADC_BIT_MSK 0x003f0000
++#define RG_SARADC_BIT_I_MSK 0xffc0ffff
++#define RG_SARADC_BIT_SFT 16
++#define RG_SARADC_BIT_HI 21
++#define RG_SARADC_BIT_SZ 6
++#define SAR_ADC_FSM_RDY_MSK 0x00400000
++#define SAR_ADC_FSM_RDY_I_MSK 0xffbfffff
++#define SAR_ADC_FSM_RDY_SFT 22
++#define SAR_ADC_FSM_RDY_HI 22
++#define SAR_ADC_FSM_RDY_SZ 1
++#define AD_CIRCUIT_VERSION_MSK 0x07800000
++#define AD_CIRCUIT_VERSION_I_MSK 0xf87fffff
++#define AD_CIRCUIT_VERSION_SFT 23
++#define AD_CIRCUIT_VERSION_HI 26
++#define AD_CIRCUIT_VERSION_SZ 4
++#define DA_R_CAL_CODE_MSK 0x0000001f
++#define DA_R_CAL_CODE_I_MSK 0xffffffe0
++#define DA_R_CAL_CODE_SFT 0
++#define DA_R_CAL_CODE_HI 4
++#define DA_R_CAL_CODE_SZ 5
++#define DA_SX_SUB_SEL_MSK 0x00000fe0
++#define DA_SX_SUB_SEL_I_MSK 0xfffff01f
++#define DA_SX_SUB_SEL_SFT 5
++#define DA_SX_SUB_SEL_HI 11
++#define DA_SX_SUB_SEL_SZ 7
++#define RG_DPL_RFCTRL_CH_MSK 0x000007ff
++#define RG_DPL_RFCTRL_CH_I_MSK 0xfffff800
++#define RG_DPL_RFCTRL_CH_SFT 0
++#define RG_DPL_RFCTRL_CH_HI 10
++#define RG_DPL_RFCTRL_CH_SZ 11
++#define RG_RSSIADC_RO_BIT_MSK 0x00007800
++#define RG_RSSIADC_RO_BIT_I_MSK 0xffff87ff
++#define RG_RSSIADC_RO_BIT_SFT 11
++#define RG_RSSIADC_RO_BIT_HI 14
++#define RG_RSSIADC_RO_BIT_SZ 4
++#define RG_RX_ADC_I_RO_BIT_MSK 0x007f8000
++#define RG_RX_ADC_I_RO_BIT_I_MSK 0xff807fff
++#define RG_RX_ADC_I_RO_BIT_SFT 15
++#define RG_RX_ADC_I_RO_BIT_HI 22
++#define RG_RX_ADC_I_RO_BIT_SZ 8
++#define RG_RX_ADC_Q_RO_BIT_MSK 0x7f800000
++#define RG_RX_ADC_Q_RO_BIT_I_MSK 0x807fffff
++#define RG_RX_ADC_Q_RO_BIT_SFT 23
++#define RG_RX_ADC_Q_RO_BIT_HI 30
++#define RG_RX_ADC_Q_RO_BIT_SZ 8
++#define RG_DPL_RFCTRL_F_MSK 0x00ffffff
++#define RG_DPL_RFCTRL_F_I_MSK 0xff000000
++#define RG_DPL_RFCTRL_F_SFT 0
++#define RG_DPL_RFCTRL_F_HI 23
++#define RG_DPL_RFCTRL_F_SZ 24
++#define RG_SX_TARGET_CNT_MSK 0x00001fff
++#define RG_SX_TARGET_CNT_I_MSK 0xffffe000
++#define RG_SX_TARGET_CNT_SFT 0
++#define RG_SX_TARGET_CNT_HI 12
++#define RG_SX_TARGET_CNT_SZ 13
++#define RG_RTC_OFFSET_MSK 0x000000ff
++#define RG_RTC_OFFSET_I_MSK 0xffffff00
++#define RG_RTC_OFFSET_SFT 0
++#define RG_RTC_OFFSET_HI 7
++#define RG_RTC_OFFSET_SZ 8
++#define RG_RTC_CAL_TARGET_COUNT_MSK 0x000fff00
++#define RG_RTC_CAL_TARGET_COUNT_I_MSK 0xfff000ff
++#define RG_RTC_CAL_TARGET_COUNT_SFT 8
++#define RG_RTC_CAL_TARGET_COUNT_HI 19
++#define RG_RTC_CAL_TARGET_COUNT_SZ 12
++#define RG_RF_D_REG_MSK 0x0000ffff
++#define RG_RF_D_REG_I_MSK 0xffff0000
++#define RG_RF_D_REG_SFT 0
++#define RG_RF_D_REG_HI 15
++#define RG_RF_D_REG_SZ 16
++#define DIRECT_MODE_MSK 0x00000001
++#define DIRECT_MODE_I_MSK 0xfffffffe
++#define DIRECT_MODE_SFT 0
++#define DIRECT_MODE_HI 0
++#define DIRECT_MODE_SZ 1
++#define TAG_INTERLEAVE_MD_MSK 0x00000002
++#define TAG_INTERLEAVE_MD_I_MSK 0xfffffffd
++#define TAG_INTERLEAVE_MD_SFT 1
++#define TAG_INTERLEAVE_MD_HI 1
++#define TAG_INTERLEAVE_MD_SZ 1
++#define DIS_DEMAND_MSK 0x00000004
++#define DIS_DEMAND_I_MSK 0xfffffffb
++#define DIS_DEMAND_SFT 2
++#define DIS_DEMAND_HI 2
++#define DIS_DEMAND_SZ 1
++#define SAME_ID_ALLOC_MD_MSK 0x00000008
++#define SAME_ID_ALLOC_MD_I_MSK 0xfffffff7
++#define SAME_ID_ALLOC_MD_SFT 3
++#define SAME_ID_ALLOC_MD_HI 3
++#define SAME_ID_ALLOC_MD_SZ 1
++#define HS_ACCESS_MD_MSK 0x00000010
++#define HS_ACCESS_MD_I_MSK 0xffffffef
++#define HS_ACCESS_MD_SFT 4
++#define HS_ACCESS_MD_HI 4
++#define HS_ACCESS_MD_SZ 1
++#define SRAM_ACCESS_MD_MSK 0x00000020
++#define SRAM_ACCESS_MD_I_MSK 0xffffffdf
++#define SRAM_ACCESS_MD_SFT 5
++#define SRAM_ACCESS_MD_HI 5
++#define SRAM_ACCESS_MD_SZ 1
++#define NOHIT_RPASS_MD_MSK 0x00000040
++#define NOHIT_RPASS_MD_I_MSK 0xffffffbf
++#define NOHIT_RPASS_MD_SFT 6
++#define NOHIT_RPASS_MD_HI 6
++#define NOHIT_RPASS_MD_SZ 1
++#define DMN_FLAG_CLR_MSK 0x00000080
++#define DMN_FLAG_CLR_I_MSK 0xffffff7f
++#define DMN_FLAG_CLR_SFT 7
++#define DMN_FLAG_CLR_HI 7
++#define DMN_FLAG_CLR_SZ 1
++#define ERR_SW_RST_N_MSK 0x00000100
++#define ERR_SW_RST_N_I_MSK 0xfffffeff
++#define ERR_SW_RST_N_SFT 8
++#define ERR_SW_RST_N_HI 8
++#define ERR_SW_RST_N_SZ 1
++#define ALR_SW_RST_N_MSK 0x00000200
++#define ALR_SW_RST_N_I_MSK 0xfffffdff
++#define ALR_SW_RST_N_SFT 9
++#define ALR_SW_RST_N_HI 9
++#define ALR_SW_RST_N_SZ 1
++#define MCH_SW_RST_N_MSK 0x00000400
++#define MCH_SW_RST_N_I_MSK 0xfffffbff
++#define MCH_SW_RST_N_SFT 10
++#define MCH_SW_RST_N_HI 10
++#define MCH_SW_RST_N_SZ 1
++#define TAG_SW_RST_N_MSK 0x00000800
++#define TAG_SW_RST_N_I_MSK 0xfffff7ff
++#define TAG_SW_RST_N_SFT 11
++#define TAG_SW_RST_N_HI 11
++#define TAG_SW_RST_N_SZ 1
++#define ABT_SW_RST_N_MSK 0x00001000
++#define ABT_SW_RST_N_I_MSK 0xffffefff
++#define ABT_SW_RST_N_SFT 12
++#define ABT_SW_RST_N_HI 12
++#define ABT_SW_RST_N_SZ 1
++#define MMU_VER_MSK 0x0000e000
++#define MMU_VER_I_MSK 0xffff1fff
++#define MMU_VER_SFT 13
++#define MMU_VER_HI 15
++#define MMU_VER_SZ 3
++#define MMU_SHARE_MCU_MSK 0x00ff0000
++#define MMU_SHARE_MCU_I_MSK 0xff00ffff
++#define MMU_SHARE_MCU_SFT 16
++#define MMU_SHARE_MCU_HI 23
++#define MMU_SHARE_MCU_SZ 8
++#define HS_WR_MSK 0x00000001
++#define HS_WR_I_MSK 0xfffffffe
++#define HS_WR_SFT 0
++#define HS_WR_HI 0
++#define HS_WR_SZ 1
++#define HS_FLAG_MSK 0x00000010
++#define HS_FLAG_I_MSK 0xffffffef
++#define HS_FLAG_SFT 4
++#define HS_FLAG_HI 4
++#define HS_FLAG_SZ 1
++#define HS_ID_MSK 0x00007f00
++#define HS_ID_I_MSK 0xffff80ff
++#define HS_ID_SFT 8
++#define HS_ID_HI 14
++#define HS_ID_SZ 7
++#define HS_CHANNEL_MSK 0x000f0000
++#define HS_CHANNEL_I_MSK 0xfff0ffff
++#define HS_CHANNEL_SFT 16
++#define HS_CHANNEL_HI 19
++#define HS_CHANNEL_SZ 4
++#define HS_PAGE_MSK 0x00f00000
++#define HS_PAGE_I_MSK 0xff0fffff
++#define HS_PAGE_SFT 20
++#define HS_PAGE_HI 23
++#define HS_PAGE_SZ 4
++#define HS_DATA_MSK 0xff000000
++#define HS_DATA_I_MSK 0x00ffffff
++#define HS_DATA_SFT 24
++#define HS_DATA_HI 31
++#define HS_DATA_SZ 8
++#define CPU_POR0_MSK 0x0000000f
++#define CPU_POR0_I_MSK 0xfffffff0
++#define CPU_POR0_SFT 0
++#define CPU_POR0_HI 3
++#define CPU_POR0_SZ 4
++#define CPU_POR1_MSK 0x000000f0
++#define CPU_POR1_I_MSK 0xffffff0f
++#define CPU_POR1_SFT 4
++#define CPU_POR1_HI 7
++#define CPU_POR1_SZ 4
++#define CPU_POR2_MSK 0x00000f00
++#define CPU_POR2_I_MSK 0xfffff0ff
++#define CPU_POR2_SFT 8
++#define CPU_POR2_HI 11
++#define CPU_POR2_SZ 4
++#define CPU_POR3_MSK 0x0000f000
++#define CPU_POR3_I_MSK 0xffff0fff
++#define CPU_POR3_SFT 12
++#define CPU_POR3_HI 15
++#define CPU_POR3_SZ 4
++#define CPU_POR4_MSK 0x000f0000
++#define CPU_POR4_I_MSK 0xfff0ffff
++#define CPU_POR4_SFT 16
++#define CPU_POR4_HI 19
++#define CPU_POR4_SZ 4
++#define CPU_POR5_MSK 0x00f00000
++#define CPU_POR5_I_MSK 0xff0fffff
++#define CPU_POR5_SFT 20
++#define CPU_POR5_HI 23
++#define CPU_POR5_SZ 4
++#define CPU_POR6_MSK 0x0f000000
++#define CPU_POR6_I_MSK 0xf0ffffff
++#define CPU_POR6_SFT 24
++#define CPU_POR6_HI 27
++#define CPU_POR6_SZ 4
++#define CPU_POR7_MSK 0xf0000000
++#define CPU_POR7_I_MSK 0x0fffffff
++#define CPU_POR7_SFT 28
++#define CPU_POR7_HI 31
++#define CPU_POR7_SZ 4
++#define CPU_POR8_MSK 0x0000000f
++#define CPU_POR8_I_MSK 0xfffffff0
++#define CPU_POR8_SFT 0
++#define CPU_POR8_HI 3
++#define CPU_POR8_SZ 4
++#define CPU_POR9_MSK 0x000000f0
++#define CPU_POR9_I_MSK 0xffffff0f
++#define CPU_POR9_SFT 4
++#define CPU_POR9_HI 7
++#define CPU_POR9_SZ 4
++#define CPU_PORA_MSK 0x00000f00
++#define CPU_PORA_I_MSK 0xfffff0ff
++#define CPU_PORA_SFT 8
++#define CPU_PORA_HI 11
++#define CPU_PORA_SZ 4
++#define CPU_PORB_MSK 0x0000f000
++#define CPU_PORB_I_MSK 0xffff0fff
++#define CPU_PORB_SFT 12
++#define CPU_PORB_HI 15
++#define CPU_PORB_SZ 4
++#define CPU_PORC_MSK 0x000f0000
++#define CPU_PORC_I_MSK 0xfff0ffff
++#define CPU_PORC_SFT 16
++#define CPU_PORC_HI 19
++#define CPU_PORC_SZ 4
++#define CPU_PORD_MSK 0x00f00000
++#define CPU_PORD_I_MSK 0xff0fffff
++#define CPU_PORD_SFT 20
++#define CPU_PORD_HI 23
++#define CPU_PORD_SZ 4
++#define CPU_PORE_MSK 0x0f000000
++#define CPU_PORE_I_MSK 0xf0ffffff
++#define CPU_PORE_SFT 24
++#define CPU_PORE_HI 27
++#define CPU_PORE_SZ 4
++#define CPU_PORF_MSK 0xf0000000
++#define CPU_PORF_I_MSK 0x0fffffff
++#define CPU_PORF_SFT 28
++#define CPU_PORF_HI 31
++#define CPU_PORF_SZ 4
++#define ACC_WR_LEN_MSK 0x0000003f
++#define ACC_WR_LEN_I_MSK 0xffffffc0
++#define ACC_WR_LEN_SFT 0
++#define ACC_WR_LEN_HI 5
++#define ACC_WR_LEN_SZ 6
++#define ACC_RD_LEN_MSK 0x00003f00
++#define ACC_RD_LEN_I_MSK 0xffffc0ff
++#define ACC_RD_LEN_SFT 8
++#define ACC_RD_LEN_HI 13
++#define ACC_RD_LEN_SZ 6
++#define REQ_NACK_CLR_MSK 0x00008000
++#define REQ_NACK_CLR_I_MSK 0xffff7fff
++#define REQ_NACK_CLR_SFT 15
++#define REQ_NACK_CLR_HI 15
++#define REQ_NACK_CLR_SZ 1
++#define NACK_FLAG_BUS_MSK 0xffff0000
++#define NACK_FLAG_BUS_I_MSK 0x0000ffff
++#define NACK_FLAG_BUS_SFT 16
++#define NACK_FLAG_BUS_HI 31
++#define NACK_FLAG_BUS_SZ 16
++#define DMN_R_PASS_MSK 0x0000ffff
++#define DMN_R_PASS_I_MSK 0xffff0000
++#define DMN_R_PASS_SFT 0
++#define DMN_R_PASS_HI 15
++#define DMN_R_PASS_SZ 16
++#define PARA_ALC_RLS_MSK 0x00010000
++#define PARA_ALC_RLS_I_MSK 0xfffeffff
++#define PARA_ALC_RLS_SFT 16
++#define PARA_ALC_RLS_HI 16
++#define PARA_ALC_RLS_SZ 1
++#define REQ_PORNS_CHGEN_MSK 0x01000000
++#define REQ_PORNS_CHGEN_I_MSK 0xfeffffff
++#define REQ_PORNS_CHGEN_SFT 24
++#define REQ_PORNS_CHGEN_HI 24
++#define REQ_PORNS_CHGEN_SZ 1
++#define ALC_ABT_ID_MSK 0x0000007f
++#define ALC_ABT_ID_I_MSK 0xffffff80
++#define ALC_ABT_ID_SFT 0
++#define ALC_ABT_ID_HI 6
++#define ALC_ABT_ID_SZ 7
++#define ALC_ABT_INT_MSK 0x00008000
++#define ALC_ABT_INT_I_MSK 0xffff7fff
++#define ALC_ABT_INT_SFT 15
++#define ALC_ABT_INT_HI 15
++#define ALC_ABT_INT_SZ 1
++#define RLS_ABT_ID_MSK 0x007f0000
++#define RLS_ABT_ID_I_MSK 0xff80ffff
++#define RLS_ABT_ID_SFT 16
++#define RLS_ABT_ID_HI 22
++#define RLS_ABT_ID_SZ 7
++#define RLS_ABT_INT_MSK 0x80000000
++#define RLS_ABT_INT_I_MSK 0x7fffffff
++#define RLS_ABT_INT_SFT 31
++#define RLS_ABT_INT_HI 31
++#define RLS_ABT_INT_SZ 1
++#define DEBUG_CTL_MSK 0x000000ff
++#define DEBUG_CTL_I_MSK 0xffffff00
++#define DEBUG_CTL_SFT 0
++#define DEBUG_CTL_HI 7
++#define DEBUG_CTL_SZ 8
++#define DEBUG_H16_MSK 0x00000100
++#define DEBUG_H16_I_MSK 0xfffffeff
++#define DEBUG_H16_SFT 8
++#define DEBUG_H16_HI 8
++#define DEBUG_H16_SZ 1
++#define DEBUG_OUT_MSK 0xffffffff
++#define DEBUG_OUT_I_MSK 0x00000000
++#define DEBUG_OUT_SFT 0
++#define DEBUG_OUT_HI 31
++#define DEBUG_OUT_SZ 32
++#define ALC_ERR_MSK 0x00000001
++#define ALC_ERR_I_MSK 0xfffffffe
++#define ALC_ERR_SFT 0
++#define ALC_ERR_HI 0
++#define ALC_ERR_SZ 1
++#define RLS_ERR_MSK 0x00000002
++#define RLS_ERR_I_MSK 0xfffffffd
++#define RLS_ERR_SFT 1
++#define RLS_ERR_HI 1
++#define RLS_ERR_SZ 1
++#define AL_STATE_MSK 0x00000700
++#define AL_STATE_I_MSK 0xfffff8ff
++#define AL_STATE_SFT 8
++#define AL_STATE_HI 10
++#define AL_STATE_SZ 3
++#define RL_STATE_MSK 0x00007000
++#define RL_STATE_I_MSK 0xffff8fff
++#define RL_STATE_SFT 12
++#define RL_STATE_HI 14
++#define RL_STATE_SZ 3
++#define ALC_ERR_ID_MSK 0x007f0000
++#define ALC_ERR_ID_I_MSK 0xff80ffff
++#define ALC_ERR_ID_SFT 16
++#define ALC_ERR_ID_HI 22
++#define ALC_ERR_ID_SZ 7
++#define RLS_ERR_ID_MSK 0x7f000000
++#define RLS_ERR_ID_I_MSK 0x80ffffff
++#define RLS_ERR_ID_SFT 24
++#define RLS_ERR_ID_HI 30
++#define RLS_ERR_ID_SZ 7
++#define DMN_NOHIT_FLAG_MSK 0x00000001
++#define DMN_NOHIT_FLAG_I_MSK 0xfffffffe
++#define DMN_NOHIT_FLAG_SFT 0
++#define DMN_NOHIT_FLAG_HI 0
++#define DMN_NOHIT_FLAG_SZ 1
++#define DMN_FLAG_MSK 0x00000002
++#define DMN_FLAG_I_MSK 0xfffffffd
++#define DMN_FLAG_SFT 1
++#define DMN_FLAG_HI 1
++#define DMN_FLAG_SZ 1
++#define DMN_WR_MSK 0x00000008
++#define DMN_WR_I_MSK 0xfffffff7
++#define DMN_WR_SFT 3
++#define DMN_WR_HI 3
++#define DMN_WR_SZ 1
++#define DMN_PORT_MSK 0x000000f0
++#define DMN_PORT_I_MSK 0xffffff0f
++#define DMN_PORT_SFT 4
++#define DMN_PORT_HI 7
++#define DMN_PORT_SZ 4
++#define DMN_NHIT_ID_MSK 0x00007f00
++#define DMN_NHIT_ID_I_MSK 0xffff80ff
++#define DMN_NHIT_ID_SFT 8
++#define DMN_NHIT_ID_HI 14
++#define DMN_NHIT_ID_SZ 7
++#define DMN_NHIT_ADDR_MSK 0xffff0000
++#define DMN_NHIT_ADDR_I_MSK 0x0000ffff
++#define DMN_NHIT_ADDR_SFT 16
++#define DMN_NHIT_ADDR_HI 31
++#define DMN_NHIT_ADDR_SZ 16
++#define TX_MOUNT_MSK 0x000000ff
++#define TX_MOUNT_I_MSK 0xffffff00
++#define TX_MOUNT_SFT 0
++#define TX_MOUNT_HI 7
++#define TX_MOUNT_SZ 8
++#define RX_MOUNT_MSK 0x0000ff00
++#define RX_MOUNT_I_MSK 0xffff00ff
++#define RX_MOUNT_SFT 8
++#define RX_MOUNT_HI 15
++#define RX_MOUNT_SZ 8
++#define AVA_TAG_MSK 0x01ff0000
++#define AVA_TAG_I_MSK 0xfe00ffff
++#define AVA_TAG_SFT 16
++#define AVA_TAG_HI 24
++#define AVA_TAG_SZ 9
++#define PKTBUF_FULL_MSK 0x80000000
++#define PKTBUF_FULL_I_MSK 0x7fffffff
++#define PKTBUF_FULL_SFT 31
++#define PKTBUF_FULL_HI 31
++#define PKTBUF_FULL_SZ 1
++#define DMN_NOHIT_MCU_MSK 0x00000001
++#define DMN_NOHIT_MCU_I_MSK 0xfffffffe
++#define DMN_NOHIT_MCU_SFT 0
++#define DMN_NOHIT_MCU_HI 0
++#define DMN_NOHIT_MCU_SZ 1
++#define DMN_MCU_FLAG_MSK 0x00000002
++#define DMN_MCU_FLAG_I_MSK 0xfffffffd
++#define DMN_MCU_FLAG_SFT 1
++#define DMN_MCU_FLAG_HI 1
++#define DMN_MCU_FLAG_SZ 1
++#define DMN_MCU_WR_MSK 0x00000008
++#define DMN_MCU_WR_I_MSK 0xfffffff7
++#define DMN_MCU_WR_SFT 3
++#define DMN_MCU_WR_HI 3
++#define DMN_MCU_WR_SZ 1
++#define DMN_MCU_PORT_MSK 0x000000f0
++#define DMN_MCU_PORT_I_MSK 0xffffff0f
++#define DMN_MCU_PORT_SFT 4
++#define DMN_MCU_PORT_HI 7
++#define DMN_MCU_PORT_SZ 4
++#define DMN_MCU_ID_MSK 0x00007f00
++#define DMN_MCU_ID_I_MSK 0xffff80ff
++#define DMN_MCU_ID_SFT 8
++#define DMN_MCU_ID_HI 14
++#define DMN_MCU_ID_SZ 7
++#define DMN_MCU_ADDR_MSK 0xffff0000
++#define DMN_MCU_ADDR_I_MSK 0x0000ffff
++#define DMN_MCU_ADDR_SFT 16
++#define DMN_MCU_ADDR_HI 31
++#define DMN_MCU_ADDR_SZ 16
++#define MB_IDTBL_31_0_MSK 0xffffffff
++#define MB_IDTBL_31_0_I_MSK 0x00000000
++#define MB_IDTBL_31_0_SFT 0
++#define MB_IDTBL_31_0_HI 31
++#define MB_IDTBL_31_0_SZ 32
++#define MB_IDTBL_63_32_MSK 0xffffffff
++#define MB_IDTBL_63_32_I_MSK 0x00000000
++#define MB_IDTBL_63_32_SFT 0
++#define MB_IDTBL_63_32_HI 31
++#define MB_IDTBL_63_32_SZ 32
++#define MB_IDTBL_95_64_MSK 0xffffffff
++#define MB_IDTBL_95_64_I_MSK 0x00000000
++#define MB_IDTBL_95_64_SFT 0
++#define MB_IDTBL_95_64_HI 31
++#define MB_IDTBL_95_64_SZ 32
++#define MB_IDTBL_127_96_MSK 0xffffffff
++#define MB_IDTBL_127_96_I_MSK 0x00000000
++#define MB_IDTBL_127_96_SFT 0
++#define MB_IDTBL_127_96_HI 31
++#define MB_IDTBL_127_96_SZ 32
++#define PKT_IDTBL_31_0_MSK 0xffffffff
++#define PKT_IDTBL_31_0_I_MSK 0x00000000
++#define PKT_IDTBL_31_0_SFT 0
++#define PKT_IDTBL_31_0_HI 31
++#define PKT_IDTBL_31_0_SZ 32
++#define PKT_IDTBL_63_32_MSK 0xffffffff
++#define PKT_IDTBL_63_32_I_MSK 0x00000000
++#define PKT_IDTBL_63_32_SFT 0
++#define PKT_IDTBL_63_32_HI 31
++#define PKT_IDTBL_63_32_SZ 32
++#define PKT_IDTBL_95_64_MSK 0xffffffff
++#define PKT_IDTBL_95_64_I_MSK 0x00000000
++#define PKT_IDTBL_95_64_SFT 0
++#define PKT_IDTBL_95_64_HI 31
++#define PKT_IDTBL_95_64_SZ 32
++#define PKT_IDTBL_127_96_MSK 0xffffffff
++#define PKT_IDTBL_127_96_I_MSK 0x00000000
++#define PKT_IDTBL_127_96_SFT 0
++#define PKT_IDTBL_127_96_HI 31
++#define PKT_IDTBL_127_96_SZ 32
++#define DMN_IDTBL_31_0_MSK 0xffffffff
++#define DMN_IDTBL_31_0_I_MSK 0x00000000
++#define DMN_IDTBL_31_0_SFT 0
++#define DMN_IDTBL_31_0_HI 31
++#define DMN_IDTBL_31_0_SZ 32
++#define DMN_IDTBL_63_32_MSK 0xffffffff
++#define DMN_IDTBL_63_32_I_MSK 0x00000000
++#define DMN_IDTBL_63_32_SFT 0
++#define DMN_IDTBL_63_32_HI 31
++#define DMN_IDTBL_63_32_SZ 32
++#define DMN_IDTBL_95_64_MSK 0xffffffff
++#define DMN_IDTBL_95_64_I_MSK 0x00000000
++#define DMN_IDTBL_95_64_SFT 0
++#define DMN_IDTBL_95_64_HI 31
++#define DMN_IDTBL_95_64_SZ 32
++#define DMN_IDTBL_127_96_MSK 0xffffffff
++#define DMN_IDTBL_127_96_I_MSK 0x00000000
++#define DMN_IDTBL_127_96_SFT 0
++#define DMN_IDTBL_127_96_HI 31
++#define DMN_IDTBL_127_96_SZ 32
++#define NEQ_MB_ID_31_0_MSK 0xffffffff
++#define NEQ_MB_ID_31_0_I_MSK 0x00000000
++#define NEQ_MB_ID_31_0_SFT 0
++#define NEQ_MB_ID_31_0_HI 31
++#define NEQ_MB_ID_31_0_SZ 32
++#define NEQ_MB_ID_63_32_MSK 0xffffffff
++#define NEQ_MB_ID_63_32_I_MSK 0x00000000
++#define NEQ_MB_ID_63_32_SFT 0
++#define NEQ_MB_ID_63_32_HI 31
++#define NEQ_MB_ID_63_32_SZ 32
++#define NEQ_MB_ID_95_64_MSK 0xffffffff
++#define NEQ_MB_ID_95_64_I_MSK 0x00000000
++#define NEQ_MB_ID_95_64_SFT 0
++#define NEQ_MB_ID_95_64_HI 31
++#define NEQ_MB_ID_95_64_SZ 32
++#define NEQ_MB_ID_127_96_MSK 0xffffffff
++#define NEQ_MB_ID_127_96_I_MSK 0x00000000
++#define NEQ_MB_ID_127_96_SFT 0
++#define NEQ_MB_ID_127_96_HI 31
++#define NEQ_MB_ID_127_96_SZ 32
++#define NEQ_PKT_ID_31_0_MSK 0xffffffff
++#define NEQ_PKT_ID_31_0_I_MSK 0x00000000
++#define NEQ_PKT_ID_31_0_SFT 0
++#define NEQ_PKT_ID_31_0_HI 31
++#define NEQ_PKT_ID_31_0_SZ 32
++#define NEQ_PKT_ID_63_32_MSK 0xffffffff
++#define NEQ_PKT_ID_63_32_I_MSK 0x00000000
++#define NEQ_PKT_ID_63_32_SFT 0
++#define NEQ_PKT_ID_63_32_HI 31
++#define NEQ_PKT_ID_63_32_SZ 32
++#define NEQ_PKT_ID_95_64_MSK 0xffffffff
++#define NEQ_PKT_ID_95_64_I_MSK 0x00000000
++#define NEQ_PKT_ID_95_64_SFT 0
++#define NEQ_PKT_ID_95_64_HI 31
++#define NEQ_PKT_ID_95_64_SZ 32
++#define NEQ_PKT_ID_127_96_MSK 0xffffffff
++#define NEQ_PKT_ID_127_96_I_MSK 0x00000000
++#define NEQ_PKT_ID_127_96_SFT 0
++#define NEQ_PKT_ID_127_96_HI 31
++#define NEQ_PKT_ID_127_96_SZ 32
++#define ALC_NOCHG_ID_MSK 0x0000007f
++#define ALC_NOCHG_ID_I_MSK 0xffffff80
++#define ALC_NOCHG_ID_SFT 0
++#define ALC_NOCHG_ID_HI 6
++#define ALC_NOCHG_ID_SZ 7
++#define ALC_NOCHG_INT_MSK 0x00008000
++#define ALC_NOCHG_INT_I_MSK 0xffff7fff
++#define ALC_NOCHG_INT_SFT 15
++#define ALC_NOCHG_INT_HI 15
++#define ALC_NOCHG_INT_SZ 1
++#define NEQ_PKT_FLAG_MSK 0x00010000
++#define NEQ_PKT_FLAG_I_MSK 0xfffeffff
++#define NEQ_PKT_FLAG_SFT 16
++#define NEQ_PKT_FLAG_HI 16
++#define NEQ_PKT_FLAG_SZ 1
++#define NEQ_MB_FLAG_MSK 0x01000000
++#define NEQ_MB_FLAG_I_MSK 0xfeffffff
++#define NEQ_MB_FLAG_SFT 24
++#define NEQ_MB_FLAG_HI 24
++#define NEQ_MB_FLAG_SZ 1
++#define SRAM_TAG_0_MSK 0x0000ffff
++#define SRAM_TAG_0_I_MSK 0xffff0000
++#define SRAM_TAG_0_SFT 0
++#define SRAM_TAG_0_HI 15
++#define SRAM_TAG_0_SZ 16
++#define SRAM_TAG_1_MSK 0xffff0000
++#define SRAM_TAG_1_I_MSK 0x0000ffff
++#define SRAM_TAG_1_SFT 16
++#define SRAM_TAG_1_HI 31
++#define SRAM_TAG_1_SZ 16
++#define SRAM_TAG_2_MSK 0x0000ffff
++#define SRAM_TAG_2_I_MSK 0xffff0000
++#define SRAM_TAG_2_SFT 0
++#define SRAM_TAG_2_HI 15
++#define SRAM_TAG_2_SZ 16
++#define SRAM_TAG_3_MSK 0xffff0000
++#define SRAM_TAG_3_I_MSK 0x0000ffff
++#define SRAM_TAG_3_SFT 16
++#define SRAM_TAG_3_HI 31
++#define SRAM_TAG_3_SZ 16
++#define SRAM_TAG_4_MSK 0x0000ffff
++#define SRAM_TAG_4_I_MSK 0xffff0000
++#define SRAM_TAG_4_SFT 0
++#define SRAM_TAG_4_HI 15
++#define SRAM_TAG_4_SZ 16
++#define SRAM_TAG_5_MSK 0xffff0000
++#define SRAM_TAG_5_I_MSK 0x0000ffff
++#define SRAM_TAG_5_SFT 16
++#define SRAM_TAG_5_HI 31
++#define SRAM_TAG_5_SZ 16
++#define SRAM_TAG_6_MSK 0x0000ffff
++#define SRAM_TAG_6_I_MSK 0xffff0000
++#define SRAM_TAG_6_SFT 0
++#define SRAM_TAG_6_HI 15
++#define SRAM_TAG_6_SZ 16
++#define SRAM_TAG_7_MSK 0xffff0000
++#define SRAM_TAG_7_I_MSK 0x0000ffff
++#define SRAM_TAG_7_SFT 16
++#define SRAM_TAG_7_HI 31
++#define SRAM_TAG_7_SZ 16
++#define SRAM_TAG_8_MSK 0x0000ffff
++#define SRAM_TAG_8_I_MSK 0xffff0000
++#define SRAM_TAG_8_SFT 0
++#define SRAM_TAG_8_HI 15
++#define SRAM_TAG_8_SZ 16
++#define SRAM_TAG_9_MSK 0xffff0000
++#define SRAM_TAG_9_I_MSK 0x0000ffff
++#define SRAM_TAG_9_SFT 16
++#define SRAM_TAG_9_HI 31
++#define SRAM_TAG_9_SZ 16
++#define SRAM_TAG_10_MSK 0x0000ffff
++#define SRAM_TAG_10_I_MSK 0xffff0000
++#define SRAM_TAG_10_SFT 0
++#define SRAM_TAG_10_HI 15
++#define SRAM_TAG_10_SZ 16
++#define SRAM_TAG_11_MSK 0xffff0000
++#define SRAM_TAG_11_I_MSK 0x0000ffff
++#define SRAM_TAG_11_SFT 16
++#define SRAM_TAG_11_HI 31
++#define SRAM_TAG_11_SZ 16
++#define SRAM_TAG_12_MSK 0x0000ffff
++#define SRAM_TAG_12_I_MSK 0xffff0000
++#define SRAM_TAG_12_SFT 0
++#define SRAM_TAG_12_HI 15
++#define SRAM_TAG_12_SZ 16
++#define SRAM_TAG_13_MSK 0xffff0000
++#define SRAM_TAG_13_I_MSK 0x0000ffff
++#define SRAM_TAG_13_SFT 16
++#define SRAM_TAG_13_HI 31
++#define SRAM_TAG_13_SZ 16
++#define SRAM_TAG_14_MSK 0x0000ffff
++#define SRAM_TAG_14_I_MSK 0xffff0000
++#define SRAM_TAG_14_SFT 0
++#define SRAM_TAG_14_HI 15
++#define SRAM_TAG_14_SZ 16
++#define SRAM_TAG_15_MSK 0xffff0000
++#define SRAM_TAG_15_I_MSK 0x0000ffff
++#define SRAM_TAG_15_SFT 16
++#define SRAM_TAG_15_HI 31
++#define SRAM_TAG_15_SZ 16
+diff --git a/drivers/net/wireless/ssv6051/include/ssv6200_common.h b/drivers/net/wireless/ssv6051/include/ssv6200_common.h
+new file mode 100644
+index 000000000000..e6d30f3714f7
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/include/ssv6200_common.h
+@@ -0,0 +1,452 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation, either version 3 of the License, or
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _SSV6200_COMMON_H_
++#define _SSV6200_COMMON_H_
++#define FW_VERSION_REG ADR_TX_SEG
++#define M_ENG_CPU 0x00
++#define M_ENG_HWHCI 0x01
++#define M_ENG_EMPTY 0x02
++#define M_ENG_ENCRYPT 0x03
++#define M_ENG_MACRX 0x04
++#define M_ENG_MIC 0x05
++#define M_ENG_TX_EDCA0 0x06
++#define M_ENG_TX_EDCA1 0x07
++#define M_ENG_TX_EDCA2 0x08
++#define M_ENG_TX_EDCA3 0x09
++#define M_ENG_TX_MNG 0x0A
++#define M_ENG_ENCRYPT_SEC 0x0B
++#define M_ENG_MIC_SEC 0x0C
++#define M_ENG_RESERVED_1 0x0D
++#define M_ENG_RESERVED_2 0x0E
++#define M_ENG_TRASH_CAN 0x0F
++#define M_ENG_MAX (M_ENG_TRASH_CAN+1)
++#define M_CPU_HWENG 0x00
++#define M_CPU_TXL34CS 0x01
++#define M_CPU_RXL34CS 0x02
++#define M_CPU_DEFRAG 0x03
++#define M_CPU_EDCATX 0x04
++#define M_CPU_RXDATA 0x05
++#define M_CPU_RXMGMT 0x06
++#define M_CPU_RXCTRL 0x07
++#define M_CPU_FRAG 0x08
++#define M_CPU_TXTPUT 0x09
++#ifndef ID_TRAP_SW_TXTPUT
++#define ID_TRAP_SW_TXTPUT 50
++#endif
++#define M0_TXREQ 0
++#define M1_TXREQ 1
++#define M2_TXREQ 2
++#define M0_RXEVENT 3
++#define M2_RXEVENT 4
++#define HOST_CMD 5
++#define HOST_EVENT 6
++#define TEST_CMD 7
++#define SSV6XXX_RX_DESC_LEN \
++        (sizeof(struct ssv6200_rx_desc) + \
++         sizeof(struct ssv6200_rxphy_info))
++#define SSV6XXX_TX_DESC_LEN \
++        (sizeof(struct ssv6200_tx_desc) + 0)
++#define TXPB_OFFSET 80
++#define RXPB_OFFSET 80
++#define SSV6200_TX_PKT_RSVD_SETTING 0x3
++#define SSV6200_TX_PKT_RSVD SSV6200_TX_PKT_RSVD_SETTING*16
++#define SSV6200_ALLOC_RSVD TXPB_OFFSET+SSV6200_TX_PKT_RSVD
++#define SSV62XX_TX_MAX_RATES 3
++
++enum ssv6xxx_sr_bhvr {
++	SUSPEND_RESUME_0,
++	SUSPEND_RESUME_1,
++	SUSPEND_RESUME_MAX
++};
++
++enum ssv6xxx_reboot_bhvr {
++	SSV_SYS_REBOOT = 1,
++	SSV_SYS_HALF,
++	SSV_SYS_POWER_OFF
++};
++
++struct fw_rc_retry_params {
++	u32 count:4;
++	u32 drate:6;
++	u32 crate:6;
++	u32 rts_cts_nav:16;
++	u32 frame_consume_time:10;
++	u32 dl_length:12;
++	u32 RSVD:10;
++} __attribute__((packed));
++struct ssv6200_tx_desc {
++	u32 len:16;
++	u32 c_type:3;
++	u32 f80211:1;
++	u32 qos:1;
++	u32 ht:1;
++	u32 use_4addr:1;
++	u32 RSVD_0:3;
++	u32 bc_que:1;
++	u32 security:1;
++	u32 more_data:1;
++	u32 stype_b5b4:2;
++	u32 extra_info:1;
++	u32 fCmd;
++	u32 hdr_offset:8;
++	u32 frag:1;
++	u32 unicast:1;
++	u32 hdr_len:6;
++	u32 tx_report:1;
++	u32 tx_burst:1;
++	u32 ack_policy:2;
++	u32 aggregation:1;
++	u32 RSVD_1:3;
++	u32 do_rts_cts:2;
++	u32 reason:6;
++	u32 payload_offset:8;
++	u32 RSVD_4:7;
++	u32 RSVD_2:1;
++	u32 fCmdIdx:3;
++	u32 wsid:4;
++	u32 txq_idx:3;
++	u32 TxF_ID:6;
++	u32 rts_cts_nav:16;
++	u32 frame_consume_time:10;
++	u32 crate_idx:6;
++	u32 drate_idx:6;
++	u32 dl_length:12;
++	u32 RSVD_3:14;
++	u32 RESERVED[8];
++	struct fw_rc_retry_params rc_params[SSV62XX_TX_MAX_RATES];
++};
++struct ssv6200_rx_desc {
++	u32 len:16;
++	u32 c_type:3;
++	u32 f80211:1;
++	u32 qos:1;
++	u32 ht:1;
++	u32 use_4addr:1;
++	u32 l3cs_err:1;
++	u32 l4cs_err:1;
++	u32 align2:1;
++	u32 RSVD_0:2;
++	u32 psm:1;
++	u32 stype_b5b4:2;
++	u32 extra_info:1;
++	u32 edca0_used:4;
++	u32 edca1_used:5;
++	u32 edca2_used:5;
++	u32 edca3_used:5;
++	u32 mng_used:4;
++	u32 tx_page_used:9;
++	u32 hdr_offset:8;
++	u32 frag:1;
++	u32 unicast:1;
++	u32 hdr_len:6;
++	u32 RxResult:8;
++	u32 wildcard_bssid:1;
++	u32 RSVD_1:1;
++	u32 reason:6;
++	u32 payload_offset:8;
++	u32 tx_id_used:8;
++	u32 fCmdIdx:3;
++	u32 wsid:4;
++	u32 RSVD_3:3;
++	u32 rate_idx:6;
++};
++struct ssv6200_rxphy_info {
++	u32 len:16;
++	u32 rsvd0:16;
++	u32 mode:3;
++	u32 ch_bw:3;
++	u32 preamble:1;
++	u32 ht_short_gi:1;
++	u32 rate:7;
++	u32 rsvd1:1;
++	u32 smoothing:1;
++	u32 no_sounding:1;
++	u32 aggregate:1;
++	u32 stbc:2;
++	u32 fec:1;
++	u32 n_ess:2;
++	u32 rsvd2:8;
++	u32 l_length:12;
++	u32 l_rate:3;
++	u32 rsvd3:17;
++	u32 rsvd4;
++	u32 rpci:8;
++	u32 snr:8;
++	u32 service:16;
++};
++struct ssv6200_rxphy_info_padding {
++	u32 rpci:8;
++	u32 snr:8;
++	u32 RSVD:16;
++};
++struct ssv6200_txphy_info {
++	u32 rsvd[7];
++};
++#ifdef CONFIG_P2P_NOA
++struct ssv6xxx_p2p_noa_param {
++	u32 duration;
++	u32 interval;
++	u32 start_time;
++	u32 enable:8;
++	u32 count:8;
++	u8 addr[6];
++	u8 vif_id;
++} __attribute__((packed));
++#endif
++typedef struct cfg_host_cmd {
++	u32 len:16;
++	u32 c_type:3;
++	u32 RSVD0:5;
++	u32 h_cmd:8;
++	u32 cmd_seq_no;
++	union {
++		u32 dummy;
++		u8 dat8[0];
++		u16 dat16[0];
++		u32 dat32[0];
++	};
++} HDR_HostCmd;
++#define HOST_CMD_HDR_LEN ((size_t)(((HDR_HostCmd *)100)->dat8)-100U)
++struct sdio_rxtput_cfg {
++	u32 size_per_frame;
++	u32 total_frames;
++};
++typedef enum {
++	SSV6XXX_HOST_CMD_START = 0,
++	SSV6XXX_HOST_CMD_LOG,
++	SSV6XXX_HOST_CMD_PS,
++	SSV6XXX_HOST_CMD_INIT_CALI,
++	SSV6XXX_HOST_CMD_RX_TPUT,
++	SSV6XXX_HOST_CMD_TX_TPUT,
++	SSV6XXX_HOST_CMD_WATCHDOG_START,
++	SSV6XXX_HOST_CMD_WATCHDOG_STOP,
++	SSV6XXX_HOST_CMD_WSID_OP,
++#ifdef CONFIG_P2P_NOA
++	SSV6XXX_HOST_CMD_SET_NOA,
++#endif
++	SSV6XXX_HOST_SOC_CMD_MAXID,
++} ssv6xxx_host_cmd_id;
++#define SSV_NUM_HW_STA 2
++typedef struct cfg_host_event {
++	u32 len:16;
++	u32 c_type:3;
++	u32 RSVD0:5;
++	u32 h_event:8;
++	u32 evt_seq_no;
++	u8 dat[0];
++} HDR_HostEvent;
++typedef enum {
++#ifdef USE_CMD_RESP
++	SOC_EVT_CMD_RESP,
++	SOC_EVT_SCAN_RESULT,
++	SOC_EVT_DEAUTH,
++#else
++	SOC_EVT_GET_REG_RESP,
++#endif
++	SOC_EVT_NO_BA,
++	SOC_EVT_RC_MPDU_REPORT,
++	SOC_EVT_RC_AMPDU_REPORT,
++	SOC_EVT_LOG,
++#ifdef CONFIG_P2P_NOA
++	SOC_EVT_NOA,
++#endif
++	SOC_EVT_USER_END,
++	SOC_EVT_SDIO_TEST_COMMAND,
++	SOC_EVT_RESET_HOST,
++	SOC_EVT_SDIO_TXTPUT_RESULT,
++	SOC_EVT_WATCHDOG_TRIGGER,
++	SOC_EVT_TXLOOPBK_RESULT,
++	SOC_EVT_MAXID,
++} ssv6xxx_soc_event;
++#ifdef CONFIG_P2P_NOA
++typedef enum {
++	SSV6XXX_NOA_START = 0,
++	SSV6XXX_NOA_STOP,
++} ssv6xxx_host_noa_event;
++struct ssv62xx_noa_evt {
++	u8 evt_id;
++	u8 vif;
++} __attribute__((packed));
++#endif
++typedef enum {
++	SSV6XXX_RC_COUNTER_CLEAR = 1,
++	SSV6XXX_RC_REPORT,
++} ssv6xxx_host_rate_control_event;
++#define MAX_AGGR_NUM (24)
++struct ssv62xx_tx_rate {
++	s8 data_rate;
++	u8 count;
++} __attribute__((packed));
++struct ampdu_ba_notify_data {
++	u8 wsid;
++	struct ssv62xx_tx_rate tried_rates[SSV62XX_TX_MAX_RATES];
++	u16 seq_no[MAX_AGGR_NUM];
++} __attribute__((packed));
++struct firmware_rate_control_report_data {
++	u8 wsid;
++	struct ssv62xx_tx_rate rates[SSV62XX_TX_MAX_RATES];
++	u16 ampdu_len;
++	u16 ampdu_ack_len;
++	int ack_signal;
++} __attribute__((packed));
++#define RC_RETRY_PARAM_OFFSET ((sizeof(struct fw_rc_retry_params))*SSV62XX_TX_MAX_RATES)
++#define SSV_RC_RATE_MAX 39
++enum SSV6XXX_WSID_OPS {
++	SSV6XXX_WSID_OPS_ADD,
++	SSV6XXX_WSID_OPS_DEL,
++	SSV6XXX_WSID_OPS_RESETALL,
++	SSV6XXX_WSID_OPS_ENABLE_CAPS,
++	SSV6XXX_WSID_OPS_DISABLE_CAPS,
++	SSV6XXX_WSID_OPS_HWWSID_PAIRWISE_SET_TYPE,
++	SSV6XXX_WSID_OPS_HWWSID_GROUP_SET_TYPE,
++	SSV6XXX_WSID_OPS_MAX
++};
++enum SSV6XXX_WSID_SEC {
++	SSV6XXX_WSID_SEC_NONE = 0,
++	SSV6XXX_WSID_SEC_PAIRWISE = 1 << 0,
++	SSV6XXX_WSID_SEC_GROUP = 1 << 1,
++};
++enum SSV6XXX_WSID_SEC_TYPE {
++	SSV6XXX_WSID_SEC_SW,
++	SSV6XXX_WSID_SEC_HW,
++	SSV6XXX_WSID_SEC_TYPE_MAX
++};
++enum SSV6XXX_RETURN_STATE {
++	SSV6XXX_STATE_OK,
++	SSV6XXX_STATE_NG,
++	SSV6XXX_STATE_MAX
++};
++struct ssv6xxx_wsid_params {
++	u8 cmd;
++	u8 wsid_idx;
++	u8 target_wsid[6];
++	u8 hw_security;
++};
++struct ssv6xxx_iqk_cfg {
++	u32 cfg_xtal:8;
++	u32 cfg_pa:8;
++	u32 cfg_pabias_ctrl:8;
++	u32 cfg_pacascode_ctrl:8;
++	u32 cfg_tssi_trgt:8;
++	u32 cfg_tssi_div:8;
++	u32 cfg_def_tx_scale_11b:8;
++	u32 cfg_def_tx_scale_11b_p0d5:8;
++	u32 cfg_def_tx_scale_11g:8;
++	u32 cfg_def_tx_scale_11g_p0d5:8;
++	u32 cmd_sel;
++	union {
++		u32 fx_sel;
++		u32 argv;
++	};
++	u32 phy_tbl_size;
++	u32 rf_tbl_size;
++};
++#define PHY_SETTING_SIZE sizeof(phy_setting)
++struct ssv6xxx_ch_cfg {
++	u32 reg_addr;
++	u32 ch1_12_value;
++	u32 ch13_14_value;
++};
++#define IQK_CFG_LEN (sizeof(struct ssv6xxx_iqk_cfg))
++#define RF_SETTING_SIZE (sizeof(asic_rf_setting))
++#define MAX_PHY_SETTING_TABLE_SIZE 1920
++#define MAX_RF_SETTING_TABLE_SIZE 512
++typedef enum {
++	SSV6XXX_VOLT_DCDC_CONVERT = 0,
++	SSV6XXX_VOLT_LDO_CONVERT,
++} ssv6xxx_cfg_volt;
++typedef enum {
++	SSV6XXX_VOLT_33V = 0,
++	SSV6XXX_VOLT_42V,
++} ssv6xxx_cfg_volt_value;
++typedef enum {
++	SSV6XXX_IQK_CFG_XTAL_26M = 0,
++	SSV6XXX_IQK_CFG_XTAL_40M,
++	SSV6XXX_IQK_CFG_XTAL_24M,
++	SSV6XXX_IQK_CFG_XTAL_MAX,
++} ssv6xxx_iqk_cfg_xtal;
++typedef enum {
++	SSV6XXX_IQK_CFG_PA_DEF = 0,
++	SSV6XXX_IQK_CFG_PA_LI_MPB,
++	SSV6XXX_IQK_CFG_PA_LI_EVB,
++	SSV6XXX_IQK_CFG_PA_HP,
++} ssv6xxx_iqk_cfg_pa;
++typedef enum {
++	SSV6XXX_IQK_CMD_INIT_CALI = 0,
++	SSV6XXX_IQK_CMD_RTBL_LOAD,
++	SSV6XXX_IQK_CMD_RTBL_LOAD_DEF,
++	SSV6XXX_IQK_CMD_RTBL_RESET,
++	SSV6XXX_IQK_CMD_RTBL_SET,
++	SSV6XXX_IQK_CMD_RTBL_EXPORT,
++	SSV6XXX_IQK_CMD_TK_EVM,
++	SSV6XXX_IQK_CMD_TK_TONE,
++	SSV6XXX_IQK_CMD_TK_CHCH,
++} ssv6xxx_iqk_cmd_sel;
++#define SSV6XXX_IQK_TEMPERATURE 0x00000004
++#define SSV6XXX_IQK_RXDC 0x00000008
++#define SSV6XXX_IQK_RXRC 0x00000010
++#define SSV6XXX_IQK_TXDC 0x00000020
++#define SSV6XXX_IQK_TXIQ 0x00000040
++#define SSV6XXX_IQK_RXIQ 0x00000080
++#define SSV6XXX_IQK_TSSI 0x00000100
++#define SSV6XXX_IQK_PAPD 0x00000200
++typedef struct ssv_cabrio_reg_st {
++	u32 address;
++	u32 data;
++} ssv_cabrio_reg;
++typedef enum __PBuf_Type_E {
++	NOTYPE_BUF = 0,
++	TX_BUF = 1,
++	RX_BUF = 2
++} PBuf_Type_E;
++struct SKB_info_st {
++	struct ieee80211_sta *sta;
++	u16 mpdu_retry_counter;
++	unsigned long aggr_timestamp;
++	u16 ampdu_tx_status;
++	u16 ampdu_tx_final_retry_count;
++	u16 lowest_rate;
++	struct fw_rc_retry_params rates[SSV62XX_TX_MAX_RATES];
++#ifdef CONFIG_DEBUG_SKB_TIMESTAMP
++	ktime_t timestamp;
++#endif
++};
++typedef struct SKB_info_st SKB_info;
++typedef struct SKB_info_st *p_SKB_info;
++#define SSV_SKB_info_size (sizeof(struct SKB_info_st))
++#ifdef CONFIG_DEBUG_SKB_TIMESTAMP
++#define SKB_DURATION_TIMEOUT_MS 100
++enum ssv_debug_skb_timestamp {
++	SKB_DURATION_STAGE_TX_ENQ,
++	SKB_DURATION_STAGE_TO_SDIO,
++	SKB_DURATION_STAGE_IN_HWQ,
++	SKB_DURATION_STAGE_END
++};
++#endif
++#define SSV6051Q_P1 0x00000000
++#define SSV6051Q_P2 0x70000000
++#define SSV6051Z 0x71000000
++#define SSV6051Q 0x73000000
++#define SSV6051P 0x75000000
++struct ssv6xxx_tx_loopback {
++	u32 reg;
++	u32 val;
++	u32 restore_val;
++	u8 restore;
++	u8 delay_ms;
++};
++#endif
+diff --git a/drivers/net/wireless/ssv6051/include/ssv6200_configuration.h b/drivers/net/wireless/ssv6051/include/ssv6200_configuration.h
+new file mode 100644
+index 000000000000..0327393de3f5
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/include/ssv6200_configuration.h
+@@ -0,0 +1,317 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation, either version 3 of the License, or
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++static ssv_cabrio_reg phy_setting[] = {
++	{0xce0071bc, 0x565B565B},
++	{0xce000008, 0x0000006a},
++	{0xce00000c, 0x00000064},
++	{0xce000010, 0x00007FFF},
++	{0xce000014, 0x00000003},
++	{0xce000018, 0x0055003C},
++	{0xce00001c, 0x00000064},
++	{0xce000020, 0x20000000},
++	{0xce00002c, 0x00000000},
++	{0xce000030, 0x80046072},
++	{0xce000034, 0x1f300f6f},
++	{0xce000038, 0x660F36D0},
++	{0xce00003c, 0x106C0004},
++	{0xce000040, 0x01601400},
++	{0xce000044, 0x00600008},
++	{0xce000048, 0xff000160},
++	{0xce00004c, 0x00000840},
++	{0xce000060, 0x01000405},
++	{0xce000064, 0x06090813},
++	{0xce000068, 0x12070000},
++	{0xce00006c, 0x01000405},
++	{0xce000070, 0x06090813},
++	{0xce000074, 0x12010000},
++	{0xce000078, 0x00000000},
++	{0xce00007c, 0x10110003},
++	{0xce000080, 0x0110000F},
++	{0xce000084, 0x00000000},
++	{0xce000088, 0x00000000},
++	{0xce000094, 0x01012425},
++	{0xce000098, 0x01010101},
++	{0xce00009c, 0x00000011},
++	{0xce0000a0, 0x1fff0000},
++	{0xce0000a4, 0x1fff0000},
++	{0xce0000a8, 0x1fff0000},
++	{0xce0000ac, 0x1fff0000},
++	{0xce0000b8, 0x0000fe3e},
++	{0xce0000fc, 0xffffffff},
++	{0xce000108, 0x0ead04f5},
++	{0xce00010c, 0x0fd60080},
++	{0xce000110, 0x00000009},
++	{0xce0010a4, 0x0000002c},
++	{0xce0010b4, 0x00003001},
++	{0xce0010d4, 0x00000001},
++	{0xce002000, 0x00000044},
++	{0xce002004, 0x00040000},
++	{0xce002008, 0x20300050},
++	{0xce00200c, 0x00003467},
++	{0xce002010, 0x00430000},
++	{0xce002014, 0x20304015},
++	{0xce002018, 0x00390005},
++	{0xce00201c, 0x05555555},
++	{0xce002020, 0x00570057},
++	{0xce002024, 0x00570057},
++	{0xce002028, 0x00236700},
++	{0xce00202c, 0x000d1746},
++	{0xce002030, 0x05061787},
++	{0xce002034, 0x07800000},
++	{0xce00209c, 0x00900008},
++	{0xce0020a0, 0x00000000},
++	{0xce0023f8, 0x00000000},
++	{0xce0023fc, 0x00000001},
++	{0xce0030a4, 0x00001901},
++	{0xce0030b8, 0x5d08908e},
++	{0xce004000, 0x00000044},
++	{0xce004004, 0x00750075},
++	{0xce004008, 0x00000075},
++	{0xce00400c, 0x10000075},
++	{0xce004010, 0x3F384905},
++	{0xce004014, 0x40182000},
++	{0xce004018, 0x20600000},
++	{0xce00401c, 0x0C010120},
++	{0xce004020, 0x50505050},
++	{0xce004024, 0x50000000},
++	{0xce004028, 0x50505050},
++	{0xce00402c, 0x506070A0},
++	{0xce004030, 0xF0000000},
++	{0xce004034, 0x00002424},
++	{0xce004038, 0x00001420},
++	{0xce00409c, 0x0000300A},
++	{0xce0040c0, 0x20000280},
++	{0xce0040c4, 0x30023002},
++	{0xce0040c8, 0x0000003a},
++	{0xce004130, 0x40000000},
++	{0xce004164, 0x009C007E},
++	{0xce004180, 0x00044400},
++	{0xce004188, 0x82000000},
++	{0xce004190, 0x00000000},
++	{0xce004194, 0xffffffff},
++	{0xce004380, 0x00700010},
++	{0xce004384, 0x00007575},
++	{0xce004388, 0x0001fe3e},
++	{0xce00438c, 0x0000fe3e},
++	{0xce0043f8, 0x00000001},
++	{0xce007000, 0x00000000},
++	{0xce007004, 0x00008000},
++	{0xce007008, 0x00000000},
++	{0xce00700c, 0x00000000},
++	{0xce007010, 0x00000000},
++	{0xce007014, 0x00000000},
++	{0xce007018, 0x00000000},
++	{0xce00701c, 0x00000000},
++	{0xce007020, 0x00000000},
++	{0xce007024, 0x00000000},
++	{0xce007028, 0x00000000},
++	{0xce00702c, 0x00000000},
++	{0xce007030, 0x00000000},
++	{0xce007034, 0x00000000},
++	{0xce007038, 0x00000000},
++	{0xce00703c, 0x00000000},
++	{0xce007040, 0x02000200},
++	{0xce007048, 0x00000000},
++	{0xce00704c, 0x00000000},
++	{0xce007050, 0x00000000},
++	{0xce007054, 0x00000000},
++	{0xce007058, 0x000028ff},
++	{0xce00705c, 0x00000000},
++	{0xce007060, 0x00000000},
++	{0xce007064, 0x00000000},
++	{0xce007068, 0x00000000},
++	{0xce00706c, 0x00000202},
++	{0xce007070, 0x80ffc200},
++	{0xce007074, 0x00000000},
++	{0xce007078, 0x00000000},
++	{0xce00707c, 0x00000000},
++	{0xce007080, 0x00000000},
++	{0xce007084, 0x00000000},
++	{0xce007088, 0x00000000},
++	{0xce00708c, 0x00000000},
++	{0xce007090, 0x00000000},
++	{0xce007094, 0x00000000},
++	{0xce007098, 0x00000000},
++	{0xce00709c, 0x00000000},
++	{0xce0070a0, 0x00000000},
++	{0xce0070a4, 0x00000000},
++	{0xce0070a8, 0x00000000},
++	{0xce0070ac, 0x00000000},
++	{0xce0070b0, 0x00000000},
++	{0xce0070b4, 0x00000000},
++	{0xce0070b8, 0x00000000},
++	{0xce0070bc, 0x00000000},
++	{0xce0070c0, 0x00000000},
++	{0xce0070c4, 0x00000000},
++	{0xce0070c8, 0x00000000},
++	{0xce0070cc, 0x00000000},
++	{0xce0070d0, 0x00000000},
++	{0xce0070d4, 0x00000000},
++	{0xce0070d8, 0x00000000},
++	{0xce0070dc, 0x00000000},
++	{0xce0070e0, 0x00000000},
++	{0xce0070e4, 0x00000000},
++	{0xce0070e8, 0x00000000},
++	{0xce0070ec, 0x00000000},
++	{0xce0070f0, 0x00000000},
++	{0xce0070f4, 0x00000000},
++	{0xce0070f8, 0x00000000},
++	{0xce0070fc, 0x00000000},
++	{0xce007100, 0x00000000},
++	{0xce007104, 0x00000000},
++	{0xce007108, 0x00000000},
++	{0xce00710c, 0x00000000},
++	{0xce007110, 0x00000000},
++	{0xce007114, 0x00000000},
++	{0xce007118, 0x00000000},
++	{0xce00711c, 0x00000000},
++	{0xce007120, 0x02000200},
++	{0xce007124, 0x02000200},
++	{0xce007128, 0x02000200},
++	{0xce00712c, 0x02000200},
++	{0xce007130, 0x02000200},
++	{0xce007134, 0x02000200},
++	{0xce007138, 0x02000200},
++	{0xce00713c, 0x02000200},
++	{0xce007140, 0x02000200},
++	{0xce007144, 0x02000200},
++	{0xce007148, 0x02000200},
++	{0xce00714c, 0x02000200},
++	{0xce007150, 0x02000200},
++	{0xce007154, 0x02000200},
++	{0xce007158, 0x00000000},
++	{0xce00715c, 0x00000000},
++	{0xce007160, 0x00000000},
++	{0xce007164, 0x00000000},
++	{0xce007168, 0x00000000},
++	{0xce00716c, 0x00000000},
++	{0xce007170, 0x00000000},
++	{0xce007174, 0x00000000},
++	{0xce007178, 0x00000000},
++	{0xce00717c, 0x00000000},
++	{0xce007180, 0x00000000},
++	{0xce007184, 0x00000000},
++	{0xce007188, 0x00000000},
++	{0xce00718c, 0x00000000},
++	{0xce007190, 0x00000000},
++	{0xce007194, 0x00000000},
++	{0xce007198, 0x00000000},
++	{0xce00719c, 0x00000000},
++	{0xce0071a0, 0x00000000},
++	{0xce0071a4, 0x00000000},
++	{0xce0071a8, 0x00000000},
++	{0xce0071ac, 0x00000000},
++	{0xce0071b0, 0x00000000},
++	{0xce0071b4, 0x00000100},
++	{0xce0071b8, 0x00000000},
++	{0xce0071c0, 0x00000000},
++	{0xce0071c4, 0x00000000},
++	{0xce0071c8, 0x00000000},
++	{0xce0071cc, 0x00000000},
++	{0xce0071d0, 0x00000000},
++	{0xce0071d4, 0x00000000},
++	{0xce0071d8, 0x00000000},
++	{0xce0071dc, 0x00000000},
++	{0xce0071e0, 0x00000000},
++	{0xce0071e4, 0x00000000},
++	{0xce0071e8, 0x00000000},
++	{0xce0071ec, 0x00000000},
++	{0xce0071f0, 0x00000000},
++	{0xce0071f4, 0x00000000},
++	{0xce0071f8, 0x00000000},
++	{0xce0071fc, 0x00000000},
++	{0xce0043fc, 0x000104E5},
++	{0xce007044, 0x00028080},
++	{0xce000000, 0x80000016},
++};
++
++static const u32 wifi_tx_gain[] = {
++	0x79807980,
++	0x72797279,
++	0x6C726C72,
++	0x666C666C,
++	0x60666066,
++	0x5B605B60,
++	0x565B565B,
++	0x51565156,
++	0x4C514C51,
++	0x484C484C,
++	0x44484448,
++	0x40444044,
++	0x3C403C40,
++	0x3A3D3A3D,
++	0x36393639,
++};
++
++static ssv_cabrio_reg asic_rf_setting[] = {
++	{0xCE010038, 0x0003E07C},
++	{0xCE010060, 0x00406000},
++	{0xCE01009C, 0x00000024},
++	{0xCE0100A0, 0x00EC4CC5},
++	{0xCE010000, 0x40002000},
++	{0xCE010004, 0x00020FC0},
++	{0xCE010008, 0x000DF69B},
++	{0xCE010014, 0x3D3E84FE},
++	{0xCE010018, 0x01457D79},
++	{0xCE01001C, 0x000103A7},
++	{0xCE010020, 0x000103A6},
++	{0xCE01002C, 0x00032CA8},
++	{0xCE010048, 0xFCCCCF27},
++	{0xCE010050, 0x00444000},
++	{0xCE01000C, 0x151558C5},
++	{0xCE010010, 0x01011A88},
++	{0xCE010024, 0x00012001},
++	{0xCE010028, 0x00036000},
++	{0xCE010030, 0x20EA0224},
++	{0xCE010034, 0x44000755},
++	{0xCE01003C, 0x55D89D8A},
++	{0xCE010040, 0x005508BB},
++	{0xCE010044, 0x07C08BFF},
++	{0xCE01004C, 0x07700830},
++	{0xCE010054, 0x00007FF4},
++	{0xCE010058, 0x0000000E},
++	{0xCE01005C, 0x00088018},
++	{0xCE010064, 0x08820820},
++	{0xCE010068, 0x00820820},
++	{0xCE01006C, 0x00820820},
++	{0xCE010070, 0x00820820},
++	{0xCE010074, 0x00820820},
++	{0xCE010078, 0x00820820},
++	{0xCE01007C, 0x00820820},
++	{0xCE010080, 0x00820820},
++	{0xCE010084, 0x00004080},
++	{0xCE010088, 0x200800FE},
++	{0xCE01008C, 0xAAAAAAAA},
++	{0xCE010090, 0xAAAAAAAA},
++	{0xCE010094, 0x0000A487},
++	{0xCE010098, 0x0000070E},
++	{0xCE0100A4, 0x00000F43},
++	{0xCE0100A8, 0x00098900},
++	{0xCE0100AC, 0x00000000},
++	{0xC00003AC, 0x00000000},
++	{0xC00003B0, 0x00000000},
++	{0xC00003B4, 0x00000000},
++	{0xC00003BC, 0x00000000},
++	{0xC0001D00, 0x5E000040},
++	{0xC0001D04, 0x015D015D},
++	{0xC0001D08, 0x00000001},
++	{0xC0001D0C, 0x55550000},
++	{0xC0001D20, 0x7FFF0000},
++	{0xC0001D24, 0x00000003},
++	{0xC0001D28, 0x00000000},
++	{0xC0001D2C, 0x00000000},
++};
+diff --git a/drivers/net/wireless/ssv6051/include/ssv6200_reg.h b/drivers/net/wireless/ssv6051/include/ssv6200_reg.h
+new file mode 100644
+index 000000000000..d4a99b25d61f
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/include/ssv6200_reg.h
+@@ -0,0 +1,9694 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation, either version 3 of the License, or
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#define SYS_REG_BASE 0xc0000000
++#define WBOOT_REG_BASE 0xc0000100
++#define TU0_US_REG_BASE 0xc0000200
++#define TU1_US_REG_BASE 0xc0000210
++#define TU2_US_REG_BASE 0xc0000220
++#define TU3_US_REG_BASE 0xc0000230
++#define TM0_MS_REG_BASE 0xc0000240
++#define TM1_MS_REG_BASE 0xc0000250
++#define TM2_MS_REG_BASE 0xc0000260
++#define TM3_MS_REG_BASE 0xc0000270
++#define MCU_WDT_REG_BASE 0xc0000280
++#define SYS_WDT_REG_BASE 0xc0000284
++#define GPIO_REG_BASE 0xc0000300
++#define SD_REG_BASE 0xc0000800
++#define SPI_REG_BASE 0xc0000a00
++#define CSR_I2C_MST_BASE 0xc0000b00
++#define UART_REG_BASE 0xc0000c00
++#define DAT_UART_REG_BASE 0xc0000d00
++#define INT_REG_BASE 0xc0000e00
++#define DBG_SPI_REG_BASE 0xc0000f00
++#define FLASH_SPI_REG_BASE 0xc0001000
++#define DMA_REG_BASE 0xc0001c00
++#define CSR_PMU_BASE 0xc0001d00
++#define CSR_RTC_BASE 0xc0001d20
++#define RTC_RAM_BASE 0xc0001d80
++#define D2_DMA_REG_BASE 0xc0001e00
++#define HCI_REG_BASE 0xc1000000
++#define CO_REG_BASE 0xc2000000
++#define EFS_REG_BASE 0xc2000100
++#define SMS4_REG_BASE 0xc3000000
++#define MRX_REG_BASE 0xc6000000
++#define AMPDU_REG_BASE 0xc6001000
++#define MT_REG_CSR_BASE 0xc6002000
++#define TXQ0_MT_Q_REG_CSR_BASE 0xc6002100
++#define TXQ1_MT_Q_REG_CSR_BASE 0xc6002200
++#define TXQ2_MT_Q_REG_CSR_BASE 0xc6002300
++#define TXQ3_MT_Q_REG_CSR_BASE 0xc6002400
++#define TXQ4_MT_Q_REG_CSR_BASE 0xc6002500
++#define HIF_INFO_BASE 0xca000000
++#define PHY_RATE_INFO_BASE 0xca000200
++#define MAC_GLB_SET_BASE 0xca000300
++#define BTCX_REG_BASE 0xca000400
++#define MIB_REG_BASE 0xca000800
++#define CBR_A_REG_BASE 0xcb000000
++#define MB_REG_BASE 0xcd000000
++#define ID_MNG_REG_BASE 0xcd010000
++#define CSR_PHY_BASE 0xce000000
++#define CSR_RF_BASE 0xce010000
++#define MMU_REG_BASE 0xcf000000
++#define SYS_REG_BANK_SIZE 0x000000b4
++#define WBOOT_REG_BANK_SIZE 0x0000000c
++#define TU0_US_REG_BANK_SIZE 0x00000010
++#define TU1_US_REG_BANK_SIZE 0x00000010
++#define TU2_US_REG_BANK_SIZE 0x00000010
++#define TU3_US_REG_BANK_SIZE 0x00000010
++#define TM0_MS_REG_BANK_SIZE 0x00000010
++#define TM1_MS_REG_BANK_SIZE 0x00000010
++#define TM2_MS_REG_BANK_SIZE 0x00000010
++#define TM3_MS_REG_BANK_SIZE 0x00000010
++#define MCU_WDT_REG_BANK_SIZE 0x00000004
++#define SYS_WDT_REG_BANK_SIZE 0x00000004
++#define GPIO_REG_BANK_SIZE 0x000000d4
++#define SD_REG_BANK_SIZE 0x00000180
++#define SPI_REG_BANK_SIZE 0x00000040
++#define CSR_I2C_MST_BANK_SIZE 0x00000018
++#define UART_REG_BANK_SIZE 0x00000028
++#define DAT_UART_REG_BANK_SIZE 0x00000028
++#define INT_REG_BANK_SIZE 0x0000004c
++#define DBG_SPI_REG_BANK_SIZE 0x00000040
++#define FLASH_SPI_REG_BANK_SIZE 0x0000002c
++#define DMA_REG_BANK_SIZE 0x00000014
++#define CSR_PMU_BANK_SIZE 0x00000100
++#define CSR_RTC_BANK_SIZE 0x000000e0
++#define RTC_RAM_BANK_SIZE 0x00000080
++#define D2_DMA_REG_BANK_SIZE 0x00000014
++#define HCI_REG_BANK_SIZE 0x000000cc
++#define CO_REG_BANK_SIZE 0x000000ac
++#define EFS_REG_BANK_SIZE 0x0000006c
++#define SMS4_REG_BANK_SIZE 0x00000070
++#define MRX_REG_BANK_SIZE 0x00000198
++#define AMPDU_REG_BANK_SIZE 0x00000014
++#define MT_REG_CSR_BANK_SIZE 0x00000100
++#define TXQ0_MT_Q_REG_CSR_BANK_SIZE 0x0000001c
++#define TXQ1_MT_Q_REG_CSR_BANK_SIZE 0x0000001c
++#define TXQ2_MT_Q_REG_CSR_BANK_SIZE 0x0000001c
++#define TXQ3_MT_Q_REG_CSR_BANK_SIZE 0x0000001c
++#define TXQ4_MT_Q_REG_CSR_BANK_SIZE 0x0000001c
++#define HIF_INFO_BANK_SIZE 0x0000009c
++#define PHY_RATE_INFO_BANK_SIZE 0x000000b8
++#define MAC_GLB_SET_BANK_SIZE 0x0000003c
++#define BTCX_REG_BANK_SIZE 0x0000000c
++#define MIB_REG_BANK_SIZE 0x00000480
++#define CBR_A_REG_BANK_SIZE 0x001203fc
++#define MB_REG_BANK_SIZE 0x000000a0
++#define ID_MNG_REG_BANK_SIZE 0x00000084
++#define CSR_PHY_BANK_SIZE 0x000071c0
++#define CSR_RF_BANK_SIZE 0x000000b0
++#define MMU_REG_BANK_SIZE 0x000000c0
++#define ADR_BRG_SW_RST (SYS_REG_BASE+0x00000000)
++#define ADR_BOOT (SYS_REG_BASE+0x00000004)
++#define ADR_CHIP_ID_0 (SYS_REG_BASE+0x00000008)
++#define ADR_CHIP_ID_1 (SYS_REG_BASE+0x0000000c)
++#define ADR_CHIP_ID_2 (SYS_REG_BASE+0x00000010)
++#define ADR_CHIP_ID_3 (SYS_REG_BASE+0x00000014)
++#define ADR_CLOCK_SELECTION (SYS_REG_BASE+0x00000018)
++#define ADR_PLATFORM_CLOCK_ENABLE (SYS_REG_BASE+0x0000001c)
++#define ADR_SYS_CSR_CLOCK_ENABLE (SYS_REG_BASE+0x00000020)
++#define ADR_MCU_DBG_SEL (SYS_REG_BASE+0x00000024)
++#define ADR_MCU_DBG_DATA (SYS_REG_BASE+0x00000028)
++#define ADR_AHB_BRG_STATUS (SYS_REG_BASE+0x0000002c)
++#define ADR_BIST_BIST_CTRL (SYS_REG_BASE+0x00000030)
++#define ADR_BIST_MODE_REG_IN (SYS_REG_BASE+0x00000034)
++#define ADR_BIST_MODE_REG_OUT (SYS_REG_BASE+0x00000038)
++#define ADR_BIST_MONITOR_BUS_LSB (SYS_REG_BASE+0x0000003c)
++#define ADR_BIST_MONITOR_BUS_MSB (SYS_REG_BASE+0x00000040)
++#define ADR_TB_ADR_SEL (SYS_REG_BASE+0x00000044)
++#define ADR_TB_RDATA (SYS_REG_BASE+0x00000048)
++#define ADR_UART_W2B (SYS_REG_BASE+0x0000004c)
++#define ADR_AHB_ILL_ADDR (SYS_REG_BASE+0x00000050)
++#define ADR_AHB_FEN_ADDR (SYS_REG_BASE+0x00000054)
++#define ADR_AHB_ILLFEN_STATUS (SYS_REG_BASE+0x00000058)
++#define ADR_PWM_A (SYS_REG_BASE+0x00000080)
++#define ADR_PWM_B (SYS_REG_BASE+0x00000084)
++#define ADR_HBUSREQ_LOCK (SYS_REG_BASE+0x00000090)
++#define ADR_HBURST_LOCK (SYS_REG_BASE+0x00000094)
++#define ADR_PRESCALER_USTIMER (SYS_REG_BASE+0x000000a0)
++#define ADR_BIST_MODE_REG_IN_MMU (SYS_REG_BASE+0x000000a4)
++#define ADR_BIST_MODE_REG_OUT_MMU (SYS_REG_BASE+0x000000a8)
++#define ADR_BIST_MONITOR_BUS_MMU (SYS_REG_BASE+0x000000ac)
++#define ADR_TEST_MODE (SYS_REG_BASE+0x000000b0)
++#define ADR_BOOT_INFO (WBOOT_REG_BASE+0x00000000)
++#define ADR_SD_INIT_CFG (WBOOT_REG_BASE+0x00000004)
++#define ADR_SPARE_UART_INFO (WBOOT_REG_BASE+0x00000008)
++#define ADR_TU0_MICROSECOND_TIMER (TU0_US_REG_BASE+0x00000000)
++#define ADR_TU0_CURRENT_MICROSECOND_TIME_VALUE (TU0_US_REG_BASE+0x00000004)
++#define ADR_TU0_DUMMY_BIT_0 (TU0_US_REG_BASE+0x00000008)
++#define ADR_TU0_DUMMY_BIT_1 (TU0_US_REG_BASE+0x0000000c)
++#define ADR_TU1_MICROSECOND_TIMER (TU1_US_REG_BASE+0x00000000)
++#define ADR_TU1_CURRENT_MICROSECOND_TIME_VALUE (TU1_US_REG_BASE+0x00000004)
++#define ADR_TU1_DUMMY_BIT_0 (TU1_US_REG_BASE+0x00000008)
++#define ADR_TU1_DUMMY_BIT_1 (TU1_US_REG_BASE+0x0000000c)
++#define ADR_TU2_MICROSECOND_TIMER (TU2_US_REG_BASE+0x00000000)
++#define ADR_TU2_CURRENT_MICROSECOND_TIME_VALUE (TU2_US_REG_BASE+0x00000004)
++#define ADR_TU2_DUMMY_BIT_0 (TU2_US_REG_BASE+0x00000008)
++#define ADR_TU2_DUMMY_BIT_1 (TU2_US_REG_BASE+0x0000000c)
++#define ADR_TU3_MICROSECOND_TIMER (TU3_US_REG_BASE+0x00000000)
++#define ADR_TU3_CURRENT_MICROSECOND_TIME_VALUE (TU3_US_REG_BASE+0x00000004)
++#define ADR_TU3_DUMMY_BIT_0 (TU3_US_REG_BASE+0x00000008)
++#define ADR_TU3_DUMMY_BIT_1 (TU3_US_REG_BASE+0x0000000c)
++#define ADR_TM0_MILISECOND_TIMER (TM0_MS_REG_BASE+0x00000000)
++#define ADR_TM0_CURRENT_MILISECOND_TIME_VALUE (TM0_MS_REG_BASE+0x00000004)
++#define ADR_TM0_DUMMY_BIT_0 (TM0_MS_REG_BASE+0x00000008)
++#define ADR_TM0_DUMMY_BIT_1 (TM0_MS_REG_BASE+0x0000000c)
++#define ADR_TM1_MILISECOND_TIMER (TM1_MS_REG_BASE+0x00000000)
++#define ADR_TM1_CURRENT_MILISECOND_TIME_VALUE (TM1_MS_REG_BASE+0x00000004)
++#define ADR_TM1_DUMMY_BIT_0 (TM1_MS_REG_BASE+0x00000008)
++#define ADR_TM1_DUMMY_BIT_1 (TM1_MS_REG_BASE+0x0000000c)
++#define ADR_TM2_MILISECOND_TIMER (TM2_MS_REG_BASE+0x00000000)
++#define ADR_TM2_CURRENT_MILISECOND_TIME_VALUE (TM2_MS_REG_BASE+0x00000004)
++#define ADR_TM2_DUMMY_BIT_0 (TM2_MS_REG_BASE+0x00000008)
++#define ADR_TM2_DUMMY_BIT_1 (TM2_MS_REG_BASE+0x0000000c)
++#define ADR_TM3_MILISECOND_TIMER (TM3_MS_REG_BASE+0x00000000)
++#define ADR_TM3_CURRENT_MILISECOND_TIME_VALUE (TM3_MS_REG_BASE+0x00000004)
++#define ADR_TM3_DUMMY_BIT_0 (TM3_MS_REG_BASE+0x00000008)
++#define ADR_TM3_DUMMY_BIT_1 (TM3_MS_REG_BASE+0x0000000c)
++#define ADR_MCU_WDOG_REG (MCU_WDT_REG_BASE+0x00000000)
++#define ADR_SYS_WDOG_REG (SYS_WDT_REG_BASE+0x00000000)
++#define ADR_PAD6 (GPIO_REG_BASE+0x00000000)
++#define ADR_PAD7 (GPIO_REG_BASE+0x00000004)
++#define ADR_PAD8 (GPIO_REG_BASE+0x00000008)
++#define ADR_PAD9 (GPIO_REG_BASE+0x0000000c)
++#define ADR_PAD11 (GPIO_REG_BASE+0x00000010)
++#define ADR_PAD15 (GPIO_REG_BASE+0x00000014)
++#define ADR_PAD16 (GPIO_REG_BASE+0x00000018)
++#define ADR_PAD17 (GPIO_REG_BASE+0x0000001c)
++#define ADR_PAD18 (GPIO_REG_BASE+0x00000020)
++#define ADR_PAD19 (GPIO_REG_BASE+0x00000024)
++#define ADR_PAD20 (GPIO_REG_BASE+0x00000028)
++#define ADR_PAD21 (GPIO_REG_BASE+0x0000002c)
++#define ADR_PAD22 (GPIO_REG_BASE+0x00000030)
++#define ADR_PAD24 (GPIO_REG_BASE+0x00000034)
++#define ADR_PAD25 (GPIO_REG_BASE+0x00000038)
++#define ADR_PAD27 (GPIO_REG_BASE+0x0000003c)
++#define ADR_PAD28 (GPIO_REG_BASE+0x00000040)
++#define ADR_PAD29 (GPIO_REG_BASE+0x00000044)
++#define ADR_PAD30 (GPIO_REG_BASE+0x00000048)
++#define ADR_PAD31 (GPIO_REG_BASE+0x0000004c)
++#define ADR_PAD32 (GPIO_REG_BASE+0x00000050)
++#define ADR_PAD33 (GPIO_REG_BASE+0x00000054)
++#define ADR_PAD34 (GPIO_REG_BASE+0x00000058)
++#define ADR_PAD42 (GPIO_REG_BASE+0x0000005c)
++#define ADR_PAD43 (GPIO_REG_BASE+0x00000060)
++#define ADR_PAD44 (GPIO_REG_BASE+0x00000064)
++#define ADR_PAD45 (GPIO_REG_BASE+0x00000068)
++#define ADR_PAD46 (GPIO_REG_BASE+0x0000006c)
++#define ADR_PAD47 (GPIO_REG_BASE+0x00000070)
++#define ADR_PAD48 (GPIO_REG_BASE+0x00000074)
++#define ADR_PAD49 (GPIO_REG_BASE+0x00000078)
++#define ADR_PAD50 (GPIO_REG_BASE+0x0000007c)
++#define ADR_PAD51 (GPIO_REG_BASE+0x00000080)
++#define ADR_PAD52 (GPIO_REG_BASE+0x00000084)
++#define ADR_PAD53 (GPIO_REG_BASE+0x00000088)
++#define ADR_PAD54 (GPIO_REG_BASE+0x0000008c)
++#define ADR_PAD56 (GPIO_REG_BASE+0x00000090)
++#define ADR_PAD57 (GPIO_REG_BASE+0x00000094)
++#define ADR_PAD58 (GPIO_REG_BASE+0x00000098)
++#define ADR_PAD59 (GPIO_REG_BASE+0x0000009c)
++#define ADR_PAD60 (GPIO_REG_BASE+0x000000a0)
++#define ADR_PAD61 (GPIO_REG_BASE+0x000000a4)
++#define ADR_PAD62 (GPIO_REG_BASE+0x000000a8)
++#define ADR_PAD64 (GPIO_REG_BASE+0x000000ac)
++#define ADR_PAD65 (GPIO_REG_BASE+0x000000b0)
++#define ADR_PAD66 (GPIO_REG_BASE+0x000000b4)
++#define ADR_PAD68 (GPIO_REG_BASE+0x000000b8)
++#define ADR_PAD67 (GPIO_REG_BASE+0x000000bc)
++#define ADR_PAD69 (GPIO_REG_BASE+0x000000c0)
++#define ADR_PAD70 (GPIO_REG_BASE+0x000000c4)
++#define ADR_PAD231 (GPIO_REG_BASE+0x000000c8)
++#define ADR_PIN_SEL_0 (GPIO_REG_BASE+0x000000cc)
++#define ADR_PIN_SEL_1 (GPIO_REG_BASE+0x000000d0)
++#define ADR_IO_PORT_REG (SD_REG_BASE+0x00000000)
++#define ADR_INT_MASK_REG (SD_REG_BASE+0x00000004)
++#define ADR_INT_STATUS_REG (SD_REG_BASE+0x00000008)
++#define ADR_FN1_STATUS_REG (SD_REG_BASE+0x0000000c)
++#define ADR_CARD_PKT_STATUS_TEST (SD_REG_BASE+0x00000010)
++#define ADR_SYSTEM_INFORMATION_REG (SD_REG_BASE+0x0000001c)
++#define ADR_CARD_RCA_REG (SD_REG_BASE+0x00000020)
++#define ADR_SDIO_FIFO_WR_THLD_REG (SD_REG_BASE+0x00000024)
++#define ADR_SDIO_FIFO_WR_LIMIT_REG (SD_REG_BASE+0x00000028)
++#define ADR_SDIO_TX_DATA_BATCH_SIZE_REG (SD_REG_BASE+0x0000002c)
++#define ADR_SDIO_THLD_FOR_CMD53RD_REG (SD_REG_BASE+0x00000030)
++#define ADR_SDIO_RX_DATA_BATCH_SIZE_REG (SD_REG_BASE+0x00000034)
++#define ADR_SDIO_LOG_START_END_DATA_REG (SD_REG_BASE+0x00000038)
++#define ADR_SDIO_BYTE_MODE_BATCH_SIZE_REG (SD_REG_BASE+0x00000040)
++#define ADR_SDIO_LAST_CMD_INDEX_CRC_REG (SD_REG_BASE+0x00000044)
++#define ADR_SDIO_LAST_CMD_ARG_REG (SD_REG_BASE+0x00000048)
++#define ADR_SDIO_BUS_STATE_DEBUG_MONITOR (SD_REG_BASE+0x0000004c)
++#define ADR_SDIO_CARD_STATUS_REG (SD_REG_BASE+0x00000050)
++#define ADR_R5_RESP_FLAG_OUT_TIMING (SD_REG_BASE+0x00000054)
++#define ADR_CMD52_DATA_FOR_LAST_TIME (SD_REG_BASE+0x0000005c)
++#define ADR_FN1_DMA_START_ADDR_REG (SD_REG_BASE+0x00000060)
++#define ADR_FN1_INT_CTRL_RESET (SD_REG_BASE+0x00000064)
++#define ADR_IO_REG_PORT_REG (SD_REG_BASE+0x00000070)
++#define ADR_SDIO_FIFO_ERROR_CNT (SD_REG_BASE+0x0000007c)
++#define ADR_SDIO_CRC7_CRC16_ERROR_REG (SD_REG_BASE+0x00000080)
++#define ADR_SDIO_BLOCK_CNT_INFO (SD_REG_BASE+0x00000084)
++#define ADR_RX_DATA_CMD52_ABORT_COUNT (SD_REG_BASE+0x0000008c)
++#define ADR_FIFO_PTR_READ_BLOCK_CNT (SD_REG_BASE+0x00000090)
++#define ADR_TX_TIME_OUT_READ_CTRL (SD_REG_BASE+0x00000094)
++#define ADR_SDIO_TX_ALLOC_REG (SD_REG_BASE+0x00000098)
++#define ADR_SDIO_TX_INFORM (SD_REG_BASE+0x0000009c)
++#define ADR_F1_BLOCK_SIZE_0_REG (SD_REG_BASE+0x000000a0)
++#define ADR_SDIO_COMMAND_LOG_DATA_31_0 (SD_REG_BASE+0x000000b0)
++#define ADR_SDIO_COMMAND_LOG_DATA_63_32 (SD_REG_BASE+0x000000b4)
++#define ADR_SYSTEM_INFORMATION_REGISTER (SD_REG_BASE+0x000000bc)
++#define ADR_CCCR_00H_REG (SD_REG_BASE+0x000000c0)
++#define ADR_CCCR_04H_REG (SD_REG_BASE+0x000000c4)
++#define ADR_CCCR_08H_REG (SD_REG_BASE+0x000000c8)
++#define ADR_CCCR_13H_REG (SD_REG_BASE+0x000000d0)
++#define ADR_FBR_100H_REG (SD_REG_BASE+0x000000e0)
++#define ADR_FBR_109H_REG (SD_REG_BASE+0x000000e8)
++#define ADR_F0_CIS_CONTENT_REG_0 (SD_REG_BASE+0x00000100)
++#define ADR_F0_CIS_CONTENT_REG_1 (SD_REG_BASE+0x00000104)
++#define ADR_F0_CIS_CONTENT_REG_2 (SD_REG_BASE+0x00000108)
++#define ADR_F0_CIS_CONTENT_REG_3 (SD_REG_BASE+0x0000010c)
++#define ADR_F0_CIS_CONTENT_REG_4 (SD_REG_BASE+0x00000110)
++#define ADR_F0_CIS_CONTENT_REG_5 (SD_REG_BASE+0x00000114)
++#define ADR_F0_CIS_CONTENT_REG_6 (SD_REG_BASE+0x00000118)
++#define ADR_F0_CIS_CONTENT_REG_7 (SD_REG_BASE+0x0000011c)
++#define ADR_F0_CIS_CONTENT_REG_8 (SD_REG_BASE+0x00000120)
++#define ADR_F0_CIS_CONTENT_REG_9 (SD_REG_BASE+0x00000124)
++#define ADR_F0_CIS_CONTENT_REG_10 (SD_REG_BASE+0x00000128)
++#define ADR_F0_CIS_CONTENT_REG_11 (SD_REG_BASE+0x0000012c)
++#define ADR_F0_CIS_CONTENT_REG_12 (SD_REG_BASE+0x00000130)
++#define ADR_F0_CIS_CONTENT_REG_13 (SD_REG_BASE+0x00000134)
++#define ADR_F0_CIS_CONTENT_REG_14 (SD_REG_BASE+0x00000138)
++#define ADR_F0_CIS_CONTENT_REG_15 (SD_REG_BASE+0x0000013c)
++#define ADR_F1_CIS_CONTENT_REG_0 (SD_REG_BASE+0x00000140)
++#define ADR_F1_CIS_CONTENT_REG_1 (SD_REG_BASE+0x00000144)
++#define ADR_F1_CIS_CONTENT_REG_2 (SD_REG_BASE+0x00000148)
++#define ADR_F1_CIS_CONTENT_REG_3 (SD_REG_BASE+0x0000014c)
++#define ADR_F1_CIS_CONTENT_REG_4 (SD_REG_BASE+0x00000150)
++#define ADR_F1_CIS_CONTENT_REG_5 (SD_REG_BASE+0x00000154)
++#define ADR_F1_CIS_CONTENT_REG_6 (SD_REG_BASE+0x00000158)
++#define ADR_F1_CIS_CONTENT_REG_7 (SD_REG_BASE+0x0000015c)
++#define ADR_F1_CIS_CONTENT_REG_8 (SD_REG_BASE+0x00000160)
++#define ADR_F1_CIS_CONTENT_REG_9 (SD_REG_BASE+0x00000164)
++#define ADR_F1_CIS_CONTENT_REG_10 (SD_REG_BASE+0x00000168)
++#define ADR_F1_CIS_CONTENT_REG_11 (SD_REG_BASE+0x0000016c)
++#define ADR_F1_CIS_CONTENT_REG_12 (SD_REG_BASE+0x00000170)
++#define ADR_F1_CIS_CONTENT_REG_13 (SD_REG_BASE+0x00000174)
++#define ADR_F1_CIS_CONTENT_REG_14 (SD_REG_BASE+0x00000178)
++#define ADR_F1_CIS_CONTENT_REG_15 (SD_REG_BASE+0x0000017c)
++#define ADR_SPI_MODE (SPI_REG_BASE+0x00000000)
++#define ADR_RX_QUOTA (SPI_REG_BASE+0x00000004)
++#define ADR_CONDITION_NUMBER (SPI_REG_BASE+0x00000008)
++#define ADR_HOST_PATH (SPI_REG_BASE+0x0000000c)
++#define ADR_TX_SEG (SPI_REG_BASE+0x00000010)
++#define ADR_DEBUG_BURST_MODE (SPI_REG_BASE+0x00000014)
++#define ADR_SPI_TO_PHY_PARAM1 (SPI_REG_BASE+0x00000018)
++#define ADR_SPI_TO_PHY_PARAM2 (SPI_REG_BASE+0x0000001c)
++#define ADR_SPI_STS (SPI_REG_BASE+0x00000020)
++#define ADR_TX_ALLOC_SET (SPI_REG_BASE+0x00000024)
++#define ADR_TX_ALLOC (SPI_REG_BASE+0x00000028)
++#define ADR_DBG_CNT (SPI_REG_BASE+0x0000002c)
++#define ADR_DBG_CNT2 (SPI_REG_BASE+0x00000030)
++#define ADR_DBG_CNT3 (SPI_REG_BASE+0x00000034)
++#define ADR_DBG_CNT4 (SPI_REG_BASE+0x00000038)
++#define ADR_INT_TAG (SPI_REG_BASE+0x0000003c)
++#define ADR_I2CM_EN (CSR_I2C_MST_BASE+0x00000000)
++#define ADR_I2CM_DEV_A (CSR_I2C_MST_BASE+0x00000004)
++#define ADR_I2CM_LEN (CSR_I2C_MST_BASE+0x00000008)
++#define ADR_I2CM_WDAT (CSR_I2C_MST_BASE+0x0000000c)
++#define ADR_I2CM_RDAT (CSR_I2C_MST_BASE+0x00000010)
++#define ADR_I2CM_EN_2 (CSR_I2C_MST_BASE+0x00000014)
++#define ADR_UART_DATA (UART_REG_BASE+0x00000000)
++#define ADR_UART_IER (UART_REG_BASE+0x00000004)
++#define ADR_UART_FCR (UART_REG_BASE+0x00000008)
++#define ADR_UART_LCR (UART_REG_BASE+0x0000000c)
++#define ADR_UART_MCR (UART_REG_BASE+0x00000010)
++#define ADR_UART_LSR (UART_REG_BASE+0x00000014)
++#define ADR_UART_MSR (UART_REG_BASE+0x00000018)
++#define ADR_UART_SPR (UART_REG_BASE+0x0000001c)
++#define ADR_UART_RTHR (UART_REG_BASE+0x00000020)
++#define ADR_UART_ISR (UART_REG_BASE+0x00000024)
++#define ADR_DAT_UART_DATA (DAT_UART_REG_BASE+0x00000000)
++#define ADR_DAT_UART_IER (DAT_UART_REG_BASE+0x00000004)
++#define ADR_DAT_UART_FCR (DAT_UART_REG_BASE+0x00000008)
++#define ADR_DAT_UART_LCR (DAT_UART_REG_BASE+0x0000000c)
++#define ADR_DAT_UART_MCR (DAT_UART_REG_BASE+0x00000010)
++#define ADR_DAT_UART_LSR (DAT_UART_REG_BASE+0x00000014)
++#define ADR_DAT_UART_MSR (DAT_UART_REG_BASE+0x00000018)
++#define ADR_DAT_UART_SPR (DAT_UART_REG_BASE+0x0000001c)
++#define ADR_DAT_UART_RTHR (DAT_UART_REG_BASE+0x00000020)
++#define ADR_DAT_UART_ISR (DAT_UART_REG_BASE+0x00000024)
++#define ADR_INT_MASK (INT_REG_BASE+0x00000000)
++#define ADR_INT_MODE (INT_REG_BASE+0x00000004)
++#define ADR_INT_IRQ_STS (INT_REG_BASE+0x00000008)
++#define ADR_INT_FIQ_STS (INT_REG_BASE+0x0000000c)
++#define ADR_INT_IRQ_RAW (INT_REG_BASE+0x00000010)
++#define ADR_INT_FIQ_RAW (INT_REG_BASE+0x00000014)
++#define ADR_INT_PERI_MASK (INT_REG_BASE+0x00000018)
++#define ADR_INT_PERI_STS (INT_REG_BASE+0x0000001c)
++#define ADR_INT_PERI_RAW (INT_REG_BASE+0x00000020)
++#define ADR_INT_GPI_CFG (INT_REG_BASE+0x00000024)
++#define ADR_SYS_INT_FOR_HOST (INT_REG_BASE+0x00000028)
++#define ADR_SPI_IPC (INT_REG_BASE+0x00000034)
++#define ADR_SDIO_IPC (INT_REG_BASE+0x00000038)
++#define ADR_SDIO_MASK (INT_REG_BASE+0x0000003c)
++#define ADR_SDIO_IRQ_STS (INT_REG_BASE+0x00000040)
++#define ADR_SD_PERI_MASK (INT_REG_BASE+0x00000044)
++#define ADR_SD_PERI_STS (INT_REG_BASE+0x00000048)
++#define ADR_DBG_SPI_MODE (DBG_SPI_REG_BASE+0x00000000)
++#define ADR_DBG_RX_QUOTA (DBG_SPI_REG_BASE+0x00000004)
++#define ADR_DBG_CONDITION_NUMBER (DBG_SPI_REG_BASE+0x00000008)
++#define ADR_DBG_HOST_PATH (DBG_SPI_REG_BASE+0x0000000c)
++#define ADR_DBG_TX_SEG (DBG_SPI_REG_BASE+0x00000010)
++#define ADR_DBG_DEBUG_BURST_MODE (DBG_SPI_REG_BASE+0x00000014)
++#define ADR_DBG_SPI_TO_PHY_PARAM1 (DBG_SPI_REG_BASE+0x00000018)
++#define ADR_DBG_SPI_TO_PHY_PARAM2 (DBG_SPI_REG_BASE+0x0000001c)
++#define ADR_DBG_SPI_STS (DBG_SPI_REG_BASE+0x00000020)
++#define ADR_DBG_TX_ALLOC_SET (DBG_SPI_REG_BASE+0x00000024)
++#define ADR_DBG_TX_ALLOC (DBG_SPI_REG_BASE+0x00000028)
++#define ADR_DBG_DBG_CNT (DBG_SPI_REG_BASE+0x0000002c)
++#define ADR_DBG_DBG_CNT2 (DBG_SPI_REG_BASE+0x00000030)
++#define ADR_DBG_DBG_CNT3 (DBG_SPI_REG_BASE+0x00000034)
++#define ADR_DBG_DBG_CNT4 (DBG_SPI_REG_BASE+0x00000038)
++#define ADR_DBG_INT_TAG (DBG_SPI_REG_BASE+0x0000003c)
++#define ADR_BOOT_ADDR (FLASH_SPI_REG_BASE+0x00000000)
++#define ADR_VERIFY_DATA (FLASH_SPI_REG_BASE+0x00000004)
++#define ADR_FLASH_ADDR (FLASH_SPI_REG_BASE+0x00000008)
++#define ADR_SRAM_ADDR (FLASH_SPI_REG_BASE+0x0000000c)
++#define ADR_LEN (FLASH_SPI_REG_BASE+0x00000010)
++#define ADR_SPI_PARAM (FLASH_SPI_REG_BASE+0x00000014)
++#define ADR_SPI_PARAM2 (FLASH_SPI_REG_BASE+0x00000018)
++#define ADR_CHECK_SUM_RESULT (FLASH_SPI_REG_BASE+0x0000001c)
++#define ADR_CHECK_SUM_IN_FILE (FLASH_SPI_REG_BASE+0x00000020)
++#define ADR_COMMAND_LEN (FLASH_SPI_REG_BASE+0x00000024)
++#define ADR_COMMAND_ADDR (FLASH_SPI_REG_BASE+0x00000028)
++#define ADR_DMA_ADR_SRC (DMA_REG_BASE+0x00000000)
++#define ADR_DMA_ADR_DST (DMA_REG_BASE+0x00000004)
++#define ADR_DMA_CTRL (DMA_REG_BASE+0x00000008)
++#define ADR_DMA_INT (DMA_REG_BASE+0x0000000c)
++#define ADR_DMA_FILL_CONST (DMA_REG_BASE+0x00000010)
++#define ADR_PMU_0 (CSR_PMU_BASE+0x00000000)
++#define ADR_PMU_1 (CSR_PMU_BASE+0x00000004)
++#define ADR_PMU_2 (CSR_PMU_BASE+0x00000008)
++#define ADR_PMU_3 (CSR_PMU_BASE+0x0000000c)
++#define ADR_RTC_1 (CSR_RTC_BASE+0x00000000)
++#define ADR_RTC_2 (CSR_RTC_BASE+0x00000004)
++#define ADR_RTC_3W (CSR_RTC_BASE+0x00000008)
++#define ADR_RTC_3R (CSR_RTC_BASE+0x00000008)
++#define ADR_RTC_4 (CSR_RTC_BASE+0x0000000c)
++#define ADR_RTC_RAM (RTC_RAM_BASE+0x00000000)
++#define ADR_D2_DMA_ADR_SRC (D2_DMA_REG_BASE+0x00000000)
++#define ADR_D2_DMA_ADR_DST (D2_DMA_REG_BASE+0x00000004)
++#define ADR_D2_DMA_CTRL (D2_DMA_REG_BASE+0x00000008)
++#define ADR_D2_DMA_INT (D2_DMA_REG_BASE+0x0000000c)
++#define ADR_D2_DMA_FILL_CONST (D2_DMA_REG_BASE+0x00000010)
++#define ADR_CONTROL (HCI_REG_BASE+0x00000000)
++#define ADR_SDIO_WAKE_MODE (HCI_REG_BASE+0x00000004)
++#define ADR_TX_FLOW_0 (HCI_REG_BASE+0x00000008)
++#define ADR_TX_FLOW_1 (HCI_REG_BASE+0x0000000c)
++#define ADR_THREASHOLD (HCI_REG_BASE+0x00000018)
++#define ADR_TXFID_INCREASE (HCI_REG_BASE+0x00000020)
++#define ADR_GLOBAL_SEQUENCE (HCI_REG_BASE+0x00000028)
++#define ADR_HCI_TX_RX_INFO_SIZE (HCI_REG_BASE+0x00000030)
++#define ADR_HCI_TX_INFO_CLEAR (HCI_REG_BASE+0x00000034)
++#define ADR_TX_ETHER_TYPE_0 (HCI_REG_BASE+0x00000050)
++#define ADR_TX_ETHER_TYPE_1 (HCI_REG_BASE+0x00000054)
++#define ADR_RX_ETHER_TYPE_0 (HCI_REG_BASE+0x00000060)
++#define ADR_RX_ETHER_TYPE_1 (HCI_REG_BASE+0x00000064)
++#define ADR_PACKET_COUNTER_INFO_0 (HCI_REG_BASE+0x00000070)
++#define ADR_PACKET_COUNTER_INFO_1 (HCI_REG_BASE+0x00000074)
++#define ADR_PACKET_COUNTER_INFO_2 (HCI_REG_BASE+0x00000078)
++#define ADR_PACKET_COUNTER_INFO_3 (HCI_REG_BASE+0x0000007c)
++#define ADR_PACKET_COUNTER_INFO_4 (HCI_REG_BASE+0x00000080)
++#define ADR_PACKET_COUNTER_INFO_5 (HCI_REG_BASE+0x00000084)
++#define ADR_PACKET_COUNTER_INFO_6 (HCI_REG_BASE+0x00000088)
++#define ADR_PACKET_COUNTER_INFO_7 (HCI_REG_BASE+0x0000008c)
++#define ADR_SDIO_TX_RX_FAIL_COUNTER_0 (HCI_REG_BASE+0x00000090)
++#define ADR_SDIO_TX_RX_FAIL_COUNTER_1 (HCI_REG_BASE+0x00000094)
++#define ADR_HCI_STATE_DEBUG_MODE_0 (HCI_REG_BASE+0x000000a0)
++#define ADR_HCI_STATE_DEBUG_MODE_1 (HCI_REG_BASE+0x000000a4)
++#define ADR_HCI_STATE_DEBUG_MODE_2 (HCI_REG_BASE+0x000000a8)
++#define ADR_HCI_STATE_DEBUG_MODE_3 (HCI_REG_BASE+0x000000ac)
++#define ADR_HCI_STATE_DEBUG_MODE_4 (HCI_REG_BASE+0x000000b0)
++#define ADR_HCI_STATE_DEBUG_MODE_5 (HCI_REG_BASE+0x000000b4)
++#define ADR_HCI_STATE_DEBUG_MODE_6 (HCI_REG_BASE+0x000000b8)
++#define ADR_HCI_STATE_DEBUG_MODE_7 (HCI_REG_BASE+0x000000bc)
++#define ADR_HCI_STATE_DEBUG_MODE_8 (HCI_REG_BASE+0x000000c0)
++#define ADR_HCI_STATE_DEBUG_MODE_9 (HCI_REG_BASE+0x000000c4)
++#define ADR_HCI_STATE_DEBUG_MODE_10 (HCI_REG_BASE+0x000000c8)
++#define ADR_CS_START_ADDR (CO_REG_BASE+0x00000000)
++#define ADR_CS_ADD_LEN (CO_REG_BASE+0x00000004)
++#define ADR_CS_CMD (CO_REG_BASE+0x00000008)
++#define ADR_CS_INI_BUF (CO_REG_BASE+0x0000000c)
++#define ADR_CS_PSEUDO_BUF (CO_REG_BASE+0x00000010)
++#define ADR_CS_CHECK_SUM (CO_REG_BASE+0x00000014)
++#define ADR_RAND_EN (CO_REG_BASE+0x00000018)
++#define ADR_RAND_NUM (CO_REG_BASE+0x0000001c)
++#define ADR_MUL_OP1 (CO_REG_BASE+0x00000060)
++#define ADR_MUL_OP2 (CO_REG_BASE+0x00000064)
++#define ADR_MUL_ANS0 (CO_REG_BASE+0x00000068)
++#define ADR_MUL_ANS1 (CO_REG_BASE+0x0000006c)
++#define ADR_DMA_RDATA (CO_REG_BASE+0x00000070)
++#define ADR_DMA_WDATA (CO_REG_BASE+0x00000074)
++#define ADR_DMA_LEN (CO_REG_BASE+0x00000078)
++#define ADR_DMA_CLR (CO_REG_BASE+0x0000007c)
++#define ADR_NAV_DATA (CO_REG_BASE+0x00000080)
++#define ADR_CO_NAV (CO_REG_BASE+0x00000084)
++#define ADR_SHA_DST_ADDR (CO_REG_BASE+0x000000a0)
++#define ADR_SHA_SRC_ADDR (CO_REG_BASE+0x000000a4)
++#define ADR_SHA_SETTING (CO_REG_BASE+0x000000a8)
++#define ADR_EFUSE_CLK_FREQ (EFS_REG_BASE+0x00000000)
++#define ADR_EFUSE_LDO_TIME (EFS_REG_BASE+0x00000004)
++#define ADR_EFUSE_AHB_RDATA_0 (EFS_REG_BASE+0x00000008)
++#define ADR_EFUSE_WDATA_0 (EFS_REG_BASE+0x00000008)
++#define ADR_EFUSE_AHB_RDATA_1 (EFS_REG_BASE+0x0000000c)
++#define ADR_EFUSE_WDATA_1 (EFS_REG_BASE+0x0000000c)
++#define ADR_EFUSE_AHB_RDATA_2 (EFS_REG_BASE+0x00000010)
++#define ADR_EFUSE_WDATA_2 (EFS_REG_BASE+0x00000010)
++#define ADR_EFUSE_AHB_RDATA_3 (EFS_REG_BASE+0x00000014)
++#define ADR_EFUSE_WDATA_3 (EFS_REG_BASE+0x00000014)
++#define ADR_EFUSE_AHB_RDATA_4 (EFS_REG_BASE+0x00000018)
++#define ADR_EFUSE_WDATA_4 (EFS_REG_BASE+0x00000018)
++#define ADR_EFUSE_AHB_RDATA_5 (EFS_REG_BASE+0x0000001c)
++#define ADR_EFUSE_WDATA_5 (EFS_REG_BASE+0x0000001c)
++#define ADR_EFUSE_AHB_RDATA_6 (EFS_REG_BASE+0x00000020)
++#define ADR_EFUSE_WDATA_6 (EFS_REG_BASE+0x00000020)
++#define ADR_EFUSE_AHB_RDATA_7 (EFS_REG_BASE+0x00000024)
++#define ADR_EFUSE_WDATA_7 (EFS_REG_BASE+0x00000024)
++#define ADR_EFUSE_SPI_RD0_EN (EFS_REG_BASE+0x00000028)
++#define ADR_EFUSE_SPI_RD1_EN (EFS_REG_BASE+0x0000002c)
++#define ADR_EFUSE_SPI_RD2_EN (EFS_REG_BASE+0x00000030)
++#define ADR_EFUSE_SPI_RD3_EN (EFS_REG_BASE+0x00000034)
++#define ADR_EFUSE_SPI_RD4_EN (EFS_REG_BASE+0x00000038)
++#define ADR_EFUSE_SPI_RD5_EN (EFS_REG_BASE+0x0000003c)
++#define ADR_EFUSE_SPI_RD6_EN (EFS_REG_BASE+0x00000040)
++#define ADR_EFUSE_SPI_RD7_EN (EFS_REG_BASE+0x00000044)
++#define ADR_EFUSE_SPI_BUSY (EFS_REG_BASE+0x00000048)
++#define ADR_EFUSE_SPI_RDATA_0 (EFS_REG_BASE+0x0000004c)
++#define ADR_EFUSE_SPI_RDATA_1 (EFS_REG_BASE+0x00000050)
++#define ADR_EFUSE_SPI_RDATA_2 (EFS_REG_BASE+0x00000054)
++#define ADR_EFUSE_SPI_RDATA_3 (EFS_REG_BASE+0x00000058)
++#define ADR_EFUSE_SPI_RDATA_4 (EFS_REG_BASE+0x0000005c)
++#define ADR_EFUSE_SPI_RDATA_5 (EFS_REG_BASE+0x00000060)
++#define ADR_EFUSE_SPI_RDATA_6 (EFS_REG_BASE+0x00000064)
++#define ADR_EFUSE_SPI_RDATA_7 (EFS_REG_BASE+0x00000068)
++#define ADR_SMS4_CFG1 (SMS4_REG_BASE+0x00000000)
++#define ADR_SMS4_CFG2 (SMS4_REG_BASE+0x00000004)
++#define ADR_SMS4_MODE1 (SMS4_REG_BASE+0x00000008)
++#define ADR_SMS4_TRIG (SMS4_REG_BASE+0x00000010)
++#define ADR_SMS4_STATUS1 (SMS4_REG_BASE+0x00000014)
++#define ADR_SMS4_STATUS2 (SMS4_REG_BASE+0x00000018)
++#define ADR_SMS4_DATA_IN0 (SMS4_REG_BASE+0x00000020)
++#define ADR_SMS4_DATA_IN1 (SMS4_REG_BASE+0x00000024)
++#define ADR_SMS4_DATA_IN2 (SMS4_REG_BASE+0x00000028)
++#define ADR_SMS4_DATA_IN3 (SMS4_REG_BASE+0x0000002c)
++#define ADR_SMS4_DATA_OUT0 (SMS4_REG_BASE+0x00000030)
++#define ADR_SMS4_DATA_OUT1 (SMS4_REG_BASE+0x00000034)
++#define ADR_SMS4_DATA_OUT2 (SMS4_REG_BASE+0x00000038)
++#define ADR_SMS4_DATA_OUT3 (SMS4_REG_BASE+0x0000003c)
++#define ADR_SMS4_KEY_0 (SMS4_REG_BASE+0x00000040)
++#define ADR_SMS4_KEY_1 (SMS4_REG_BASE+0x00000044)
++#define ADR_SMS4_KEY_2 (SMS4_REG_BASE+0x00000048)
++#define ADR_SMS4_KEY_3 (SMS4_REG_BASE+0x0000004c)
++#define ADR_SMS4_MODE_IV0 (SMS4_REG_BASE+0x00000050)
++#define ADR_SMS4_MODE_IV1 (SMS4_REG_BASE+0x00000054)
++#define ADR_SMS4_MODE_IV2 (SMS4_REG_BASE+0x00000058)
++#define ADR_SMS4_MODE_IV3 (SMS4_REG_BASE+0x0000005c)
++#define ADR_SMS4_OFB_ENC0 (SMS4_REG_BASE+0x00000060)
++#define ADR_SMS4_OFB_ENC1 (SMS4_REG_BASE+0x00000064)
++#define ADR_SMS4_OFB_ENC2 (SMS4_REG_BASE+0x00000068)
++#define ADR_SMS4_OFB_ENC3 (SMS4_REG_BASE+0x0000006c)
++#define ADR_MRX_MCAST_TB0_0 (MRX_REG_BASE+0x00000000)
++#define ADR_MRX_MCAST_TB0_1 (MRX_REG_BASE+0x00000004)
++#define ADR_MRX_MCAST_MK0_0 (MRX_REG_BASE+0x00000008)
++#define ADR_MRX_MCAST_MK0_1 (MRX_REG_BASE+0x0000000c)
++#define ADR_MRX_MCAST_CTRL0 (MRX_REG_BASE+0x00000010)
++#define ADR_MRX_MCAST_TB1_0 (MRX_REG_BASE+0x00000014)
++#define ADR_MRX_MCAST_TB1_1 (MRX_REG_BASE+0x00000018)
++#define ADR_MRX_MCAST_MK1_0 (MRX_REG_BASE+0x0000001c)
++#define ADR_MRX_MCAST_MK1_1 (MRX_REG_BASE+0x00000020)
++#define ADR_MRX_MCAST_CTRL1 (MRX_REG_BASE+0x00000024)
++#define ADR_MRX_MCAST_TB2_0 (MRX_REG_BASE+0x00000028)
++#define ADR_MRX_MCAST_TB2_1 (MRX_REG_BASE+0x0000002c)
++#define ADR_MRX_MCAST_MK2_0 (MRX_REG_BASE+0x00000030)
++#define ADR_MRX_MCAST_MK2_1 (MRX_REG_BASE+0x00000034)
++#define ADR_MRX_MCAST_CTRL2 (MRX_REG_BASE+0x00000038)
++#define ADR_MRX_MCAST_TB3_0 (MRX_REG_BASE+0x0000003c)
++#define ADR_MRX_MCAST_TB3_1 (MRX_REG_BASE+0x00000040)
++#define ADR_MRX_MCAST_MK3_0 (MRX_REG_BASE+0x00000044)
++#define ADR_MRX_MCAST_MK3_1 (MRX_REG_BASE+0x00000048)
++#define ADR_MRX_MCAST_CTRL3 (MRX_REG_BASE+0x0000004c)
++#define ADR_MRX_PHY_INFO (MRX_REG_BASE+0x00000050)
++#define ADR_MRX_BA_DBG (MRX_REG_BASE+0x00000054)
++#define ADR_MRX_FLT_TB0 (MRX_REG_BASE+0x00000070)
++#define ADR_MRX_FLT_TB1 (MRX_REG_BASE+0x00000074)
++#define ADR_MRX_FLT_TB2 (MRX_REG_BASE+0x00000078)
++#define ADR_MRX_FLT_TB3 (MRX_REG_BASE+0x0000007c)
++#define ADR_MRX_FLT_TB4 (MRX_REG_BASE+0x00000080)
++#define ADR_MRX_FLT_TB5 (MRX_REG_BASE+0x00000084)
++#define ADR_MRX_FLT_TB6 (MRX_REG_BASE+0x00000088)
++#define ADR_MRX_FLT_TB7 (MRX_REG_BASE+0x0000008c)
++#define ADR_MRX_FLT_TB8 (MRX_REG_BASE+0x00000090)
++#define ADR_MRX_FLT_TB9 (MRX_REG_BASE+0x00000094)
++#define ADR_MRX_FLT_TB10 (MRX_REG_BASE+0x00000098)
++#define ADR_MRX_FLT_TB11 (MRX_REG_BASE+0x0000009c)
++#define ADR_MRX_FLT_TB12 (MRX_REG_BASE+0x000000a0)
++#define ADR_MRX_FLT_TB13 (MRX_REG_BASE+0x000000a4)
++#define ADR_MRX_FLT_TB14 (MRX_REG_BASE+0x000000a8)
++#define ADR_MRX_FLT_TB15 (MRX_REG_BASE+0x000000ac)
++#define ADR_MRX_FLT_EN0 (MRX_REG_BASE+0x000000b0)
++#define ADR_MRX_FLT_EN1 (MRX_REG_BASE+0x000000b4)
++#define ADR_MRX_FLT_EN2 (MRX_REG_BASE+0x000000b8)
++#define ADR_MRX_FLT_EN3 (MRX_REG_BASE+0x000000bc)
++#define ADR_MRX_FLT_EN4 (MRX_REG_BASE+0x000000c0)
++#define ADR_MRX_FLT_EN5 (MRX_REG_BASE+0x000000c4)
++#define ADR_MRX_FLT_EN6 (MRX_REG_BASE+0x000000c8)
++#define ADR_MRX_FLT_EN7 (MRX_REG_BASE+0x000000cc)
++#define ADR_MRX_FLT_EN8 (MRX_REG_BASE+0x000000d0)
++#define ADR_MRX_LEN_FLT (MRX_REG_BASE+0x000000d4)
++#define ADR_RX_FLOW_DATA (MRX_REG_BASE+0x000000e0)
++#define ADR_RX_FLOW_MNG (MRX_REG_BASE+0x000000e4)
++#define ADR_RX_FLOW_CTRL (MRX_REG_BASE+0x000000e8)
++#define ADR_RX_TIME_STAMP_CFG (MRX_REG_BASE+0x000000ec)
++#define ADR_DBG_FF_FULL (MRX_REG_BASE+0x000000f0)
++#define ADR_DBG_WFF_FULL (MRX_REG_BASE+0x000000f4)
++#define ADR_DBG_MB_FULL (MRX_REG_BASE+0x000000f8)
++#define ADR_BA_CTRL (MRX_REG_BASE+0x00000100)
++#define ADR_BA_TA_0 (MRX_REG_BASE+0x00000104)
++#define ADR_BA_TA_1 (MRX_REG_BASE+0x00000108)
++#define ADR_BA_TID (MRX_REG_BASE+0x0000010c)
++#define ADR_BA_ST_SEQ (MRX_REG_BASE+0x00000110)
++#define ADR_BA_SB0 (MRX_REG_BASE+0x00000114)
++#define ADR_BA_SB1 (MRX_REG_BASE+0x00000118)
++#define ADR_MRX_WATCH_DOG (MRX_REG_BASE+0x0000011c)
++#define ADR_ACK_GEN_EN (MRX_REG_BASE+0x00000120)
++#define ADR_ACK_GEN_PARA (MRX_REG_BASE+0x00000124)
++#define ADR_ACK_GEN_RA_0 (MRX_REG_BASE+0x00000128)
++#define ADR_ACK_GEN_RA_1 (MRX_REG_BASE+0x0000012c)
++#define ADR_MIB_LEN_FAIL (MRX_REG_BASE+0x00000130)
++#define ADR_TRAP_HW_ID (MRX_REG_BASE+0x00000134)
++#define ADR_ID_IN_USE (MRX_REG_BASE+0x00000138)
++#define ADR_MRX_ERR (MRX_REG_BASE+0x0000013c)
++#define ADR_WSID0_TID0_RX_SEQ (MRX_REG_BASE+0x00000140)
++#define ADR_WSID0_TID1_RX_SEQ (MRX_REG_BASE+0x00000144)
++#define ADR_WSID0_TID2_RX_SEQ (MRX_REG_BASE+0x00000148)
++#define ADR_WSID0_TID3_RX_SEQ (MRX_REG_BASE+0x0000014c)
++#define ADR_WSID0_TID4_RX_SEQ (MRX_REG_BASE+0x00000150)
++#define ADR_WSID0_TID5_RX_SEQ (MRX_REG_BASE+0x00000154)
++#define ADR_WSID0_TID6_RX_SEQ (MRX_REG_BASE+0x00000158)
++#define ADR_WSID0_TID7_RX_SEQ (MRX_REG_BASE+0x0000015c)
++#define ADR_WSID1_TID0_RX_SEQ (MRX_REG_BASE+0x00000170)
++#define ADR_WSID1_TID1_RX_SEQ (MRX_REG_BASE+0x00000174)
++#define ADR_WSID1_TID2_RX_SEQ (MRX_REG_BASE+0x00000178)
++#define ADR_WSID1_TID3_RX_SEQ (MRX_REG_BASE+0x0000017c)
++#define ADR_WSID1_TID4_RX_SEQ (MRX_REG_BASE+0x00000180)
++#define ADR_WSID1_TID5_RX_SEQ (MRX_REG_BASE+0x00000184)
++#define ADR_WSID1_TID6_RX_SEQ (MRX_REG_BASE+0x00000188)
++#define ADR_WSID1_TID7_RX_SEQ (MRX_REG_BASE+0x0000018c)
++#define ADR_HDR_ADDR_SEL (MRX_REG_BASE+0x00000190)
++#define ADR_FRAME_TYPE_CNTR_SET (MRX_REG_BASE+0x00000194)
++#define ADR_PHY_INFO (AMPDU_REG_BASE+0x00000000)
++#define ADR_AMPDU_SIG (AMPDU_REG_BASE+0x00000004)
++#define ADR_MIB_AMPDU (AMPDU_REG_BASE+0x00000008)
++#define ADR_LEN_FLT (AMPDU_REG_BASE+0x0000000c)
++#define ADR_MIB_DELIMITER (AMPDU_REG_BASE+0x00000010)
++#define ADR_MTX_INT_STS (MT_REG_CSR_BASE+0x00000000)
++#define ADR_MTX_INT_EN (MT_REG_CSR_BASE+0x00000004)
++#define ADR_MTX_MISC_EN (MT_REG_CSR_BASE+0x00000008)
++#define ADR_MTX_EDCCA_TOUT (MT_REG_CSR_BASE+0x00000010)
++#define ADR_MTX_BCN_INT_STS (MT_REG_CSR_BASE+0x000000a0)
++#define ADR_MTX_BCN_EN_INT (MT_REG_CSR_BASE+0x000000a4)
++#define ADR_MTX_BCN_EN_MISC (MT_REG_CSR_BASE+0x000000a8)
++#define ADR_MTX_BCN_MISC (MT_REG_CSR_BASE+0x000000ac)
++#define ADR_MTX_BCN_PRD (MT_REG_CSR_BASE+0x000000b0)
++#define ADR_MTX_BCN_TSF_L (MT_REG_CSR_BASE+0x000000b4)
++#define ADR_MTX_BCN_TSF_U (MT_REG_CSR_BASE+0x000000b8)
++#define ADR_MTX_BCN_CFG0 (MT_REG_CSR_BASE+0x000000bc)
++#define ADR_MTX_BCN_CFG1 (MT_REG_CSR_BASE+0x000000c0)
++#define ADR_MTX_STATUS (MT_REG_CSR_BASE+0x000000cc)
++#define ADR_MTX_DBG_CTRL (MT_REG_CSR_BASE+0x000000d0)
++#define ADR_MTX_DBG_DAT0 (MT_REG_CSR_BASE+0x000000d4)
++#define ADR_MTX_DBG_DAT1 (MT_REG_CSR_BASE+0x000000d8)
++#define ADR_MTX_DBG_DAT2 (MT_REG_CSR_BASE+0x000000dc)
++#define ADR_MTX_DUR_TOUT (MT_REG_CSR_BASE+0x000000e0)
++#define ADR_MTX_DUR_IFS (MT_REG_CSR_BASE+0x000000e4)
++#define ADR_MTX_DUR_SIFS_G (MT_REG_CSR_BASE+0x000000e8)
++#define ADR_MTX_DBG_DAT3 (MT_REG_CSR_BASE+0x000000ec)
++#define ADR_MTX_NAV (MT_REG_CSR_BASE+0x000000f0)
++#define ADR_MTX_MIB_WSID0 (MT_REG_CSR_BASE+0x000000f4)
++#define ADR_MTX_MIB_WSID1 (MT_REG_CSR_BASE+0x000000f8)
++#define ADR_MTX_DBG_DAT4 (MT_REG_CSR_BASE+0x000000fc)
++#define ADR_TXQ0_MTX_Q_MISC_EN (TXQ0_MT_Q_REG_CSR_BASE+0x00000000)
++#define ADR_TXQ0_MTX_Q_AIFSN (TXQ0_MT_Q_REG_CSR_BASE+0x00000004)
++#define ADR_TXQ0_MTX_Q_BKF_CNT (TXQ0_MT_Q_REG_CSR_BASE+0x00000008)
++#define ADR_TXQ0_MTX_Q_RC_LIMIT (TXQ0_MT_Q_REG_CSR_BASE+0x0000000c)
++#define ADR_TXQ0_MTX_Q_ID_MAP_L (TXQ0_MT_Q_REG_CSR_BASE+0x00000010)
++#define ADR_TXQ0_MTX_Q_TXOP_CH_THD (TXQ0_MT_Q_REG_CSR_BASE+0x00000014)
++#define ADR_TXQ0_MTX_Q_TXOP_OV_THD (TXQ0_MT_Q_REG_CSR_BASE+0x00000018)
++#define ADR_TXQ1_MTX_Q_MISC_EN (TXQ1_MT_Q_REG_CSR_BASE+0x00000000)
++#define ADR_TXQ1_MTX_Q_AIFSN (TXQ1_MT_Q_REG_CSR_BASE+0x00000004)
++#define ADR_TXQ1_MTX_Q_BKF_CNT (TXQ1_MT_Q_REG_CSR_BASE+0x00000008)
++#define ADR_TXQ1_MTX_Q_RC_LIMIT (TXQ1_MT_Q_REG_CSR_BASE+0x0000000c)
++#define ADR_TXQ1_MTX_Q_ID_MAP_L (TXQ1_MT_Q_REG_CSR_BASE+0x00000010)
++#define ADR_TXQ1_MTX_Q_TXOP_CH_THD (TXQ1_MT_Q_REG_CSR_BASE+0x00000014)
++#define ADR_TXQ1_MTX_Q_TXOP_OV_THD (TXQ1_MT_Q_REG_CSR_BASE+0x00000018)
++#define ADR_TXQ2_MTX_Q_MISC_EN (TXQ2_MT_Q_REG_CSR_BASE+0x00000000)
++#define ADR_TXQ2_MTX_Q_AIFSN (TXQ2_MT_Q_REG_CSR_BASE+0x00000004)
++#define ADR_TXQ2_MTX_Q_BKF_CNT (TXQ2_MT_Q_REG_CSR_BASE+0x00000008)
++#define ADR_TXQ2_MTX_Q_RC_LIMIT (TXQ2_MT_Q_REG_CSR_BASE+0x0000000c)
++#define ADR_TXQ2_MTX_Q_ID_MAP_L (TXQ2_MT_Q_REG_CSR_BASE+0x00000010)
++#define ADR_TXQ2_MTX_Q_TXOP_CH_THD (TXQ2_MT_Q_REG_CSR_BASE+0x00000014)
++#define ADR_TXQ2_MTX_Q_TXOP_OV_THD (TXQ2_MT_Q_REG_CSR_BASE+0x00000018)
++#define ADR_TXQ3_MTX_Q_MISC_EN (TXQ3_MT_Q_REG_CSR_BASE+0x00000000)
++#define ADR_TXQ3_MTX_Q_AIFSN (TXQ3_MT_Q_REG_CSR_BASE+0x00000004)
++#define ADR_TXQ3_MTX_Q_BKF_CNT (TXQ3_MT_Q_REG_CSR_BASE+0x00000008)
++#define ADR_TXQ3_MTX_Q_RC_LIMIT (TXQ3_MT_Q_REG_CSR_BASE+0x0000000c)
++#define ADR_TXQ3_MTX_Q_ID_MAP_L (TXQ3_MT_Q_REG_CSR_BASE+0x00000010)
++#define ADR_TXQ3_MTX_Q_TXOP_CH_THD (TXQ3_MT_Q_REG_CSR_BASE+0x00000014)
++#define ADR_TXQ3_MTX_Q_TXOP_OV_THD (TXQ3_MT_Q_REG_CSR_BASE+0x00000018)
++#define ADR_TXQ4_MTX_Q_MISC_EN (TXQ4_MT_Q_REG_CSR_BASE+0x00000000)
++#define ADR_TXQ4_MTX_Q_AIFSN (TXQ4_MT_Q_REG_CSR_BASE+0x00000004)
++#define ADR_TXQ4_MTX_Q_BKF_CNT (TXQ4_MT_Q_REG_CSR_BASE+0x00000008)
++#define ADR_TXQ4_MTX_Q_RC_LIMIT (TXQ4_MT_Q_REG_CSR_BASE+0x0000000c)
++#define ADR_TXQ4_MTX_Q_ID_MAP_L (TXQ4_MT_Q_REG_CSR_BASE+0x00000010)
++#define ADR_TXQ4_MTX_Q_TXOP_CH_THD (TXQ4_MT_Q_REG_CSR_BASE+0x00000014)
++#define ADR_TXQ4_MTX_Q_TXOP_OV_THD (TXQ4_MT_Q_REG_CSR_BASE+0x00000018)
++#define ADR_WSID0 (HIF_INFO_BASE+0x00000000)
++#define ADR_PEER_MAC0_0 (HIF_INFO_BASE+0x00000004)
++#define ADR_PEER_MAC0_1 (HIF_INFO_BASE+0x00000008)
++#define ADR_TX_ACK_POLICY_0_0 (HIF_INFO_BASE+0x0000000c)
++#define ADR_TX_SEQ_CTRL_0_0 (HIF_INFO_BASE+0x00000010)
++#define ADR_TX_ACK_POLICY_0_1 (HIF_INFO_BASE+0x00000014)
++#define ADR_TX_SEQ_CTRL_0_1 (HIF_INFO_BASE+0x00000018)
++#define ADR_TX_ACK_POLICY_0_2 (HIF_INFO_BASE+0x0000001c)
++#define ADR_TX_SEQ_CTRL_0_2 (HIF_INFO_BASE+0x00000020)
++#define ADR_TX_ACK_POLICY_0_3 (HIF_INFO_BASE+0x00000024)
++#define ADR_TX_SEQ_CTRL_0_3 (HIF_INFO_BASE+0x00000028)
++#define ADR_TX_ACK_POLICY_0_4 (HIF_INFO_BASE+0x0000002c)
++#define ADR_TX_SEQ_CTRL_0_4 (HIF_INFO_BASE+0x00000030)
++#define ADR_TX_ACK_POLICY_0_5 (HIF_INFO_BASE+0x00000034)
++#define ADR_TX_SEQ_CTRL_0_5 (HIF_INFO_BASE+0x00000038)
++#define ADR_TX_ACK_POLICY_0_6 (HIF_INFO_BASE+0x0000003c)
++#define ADR_TX_SEQ_CTRL_0_6 (HIF_INFO_BASE+0x00000040)
++#define ADR_TX_ACK_POLICY_0_7 (HIF_INFO_BASE+0x00000044)
++#define ADR_TX_SEQ_CTRL_0_7 (HIF_INFO_BASE+0x00000048)
++#define ADR_WSID1 (HIF_INFO_BASE+0x00000050)
++#define ADR_PEER_MAC1_0 (HIF_INFO_BASE+0x00000054)
++#define ADR_PEER_MAC1_1 (HIF_INFO_BASE+0x00000058)
++#define ADR_TX_ACK_POLICY_1_0 (HIF_INFO_BASE+0x0000005c)
++#define ADR_TX_SEQ_CTRL_1_0 (HIF_INFO_BASE+0x00000060)
++#define ADR_TX_ACK_POLICY_1_1 (HIF_INFO_BASE+0x00000064)
++#define ADR_TX_SEQ_CTRL_1_1 (HIF_INFO_BASE+0x00000068)
++#define ADR_TX_ACK_POLICY_1_2 (HIF_INFO_BASE+0x0000006c)
++#define ADR_TX_SEQ_CTRL_1_2 (HIF_INFO_BASE+0x00000070)
++#define ADR_TX_ACK_POLICY_1_3 (HIF_INFO_BASE+0x00000074)
++#define ADR_TX_SEQ_CTRL_1_3 (HIF_INFO_BASE+0x00000078)
++#define ADR_TX_ACK_POLICY_1_4 (HIF_INFO_BASE+0x0000007c)
++#define ADR_TX_SEQ_CTRL_1_4 (HIF_INFO_BASE+0x00000080)
++#define ADR_TX_ACK_POLICY_1_5 (HIF_INFO_BASE+0x00000084)
++#define ADR_TX_SEQ_CTRL_1_5 (HIF_INFO_BASE+0x00000088)
++#define ADR_TX_ACK_POLICY_1_6 (HIF_INFO_BASE+0x0000008c)
++#define ADR_TX_SEQ_CTRL_1_6 (HIF_INFO_BASE+0x00000090)
++#define ADR_TX_ACK_POLICY_1_7 (HIF_INFO_BASE+0x00000094)
++#define ADR_TX_SEQ_CTRL_1_7 (HIF_INFO_BASE+0x00000098)
++#define ADR_INFO0 (PHY_RATE_INFO_BASE+0x00000000)
++#define ADR_INFO1 (PHY_RATE_INFO_BASE+0x00000004)
++#define ADR_INFO2 (PHY_RATE_INFO_BASE+0x00000008)
++#define ADR_INFO3 (PHY_RATE_INFO_BASE+0x0000000c)
++#define ADR_INFO4 (PHY_RATE_INFO_BASE+0x00000010)
++#define ADR_INFO5 (PHY_RATE_INFO_BASE+0x00000014)
++#define ADR_INFO6 (PHY_RATE_INFO_BASE+0x00000018)
++#define ADR_INFO7 (PHY_RATE_INFO_BASE+0x0000001c)
++#define ADR_INFO8 (PHY_RATE_INFO_BASE+0x00000020)
++#define ADR_INFO9 (PHY_RATE_INFO_BASE+0x00000024)
++#define ADR_INFO10 (PHY_RATE_INFO_BASE+0x00000028)
++#define ADR_INFO11 (PHY_RATE_INFO_BASE+0x0000002c)
++#define ADR_INFO12 (PHY_RATE_INFO_BASE+0x00000030)
++#define ADR_INFO13 (PHY_RATE_INFO_BASE+0x00000034)
++#define ADR_INFO14 (PHY_RATE_INFO_BASE+0x00000038)
++#define ADR_INFO15 (PHY_RATE_INFO_BASE+0x0000003c)
++#define ADR_INFO16 (PHY_RATE_INFO_BASE+0x00000040)
++#define ADR_INFO17 (PHY_RATE_INFO_BASE+0x00000044)
++#define ADR_INFO18 (PHY_RATE_INFO_BASE+0x00000048)
++#define ADR_INFO19 (PHY_RATE_INFO_BASE+0x0000004c)
++#define ADR_INFO20 (PHY_RATE_INFO_BASE+0x00000050)
++#define ADR_INFO21 (PHY_RATE_INFO_BASE+0x00000054)
++#define ADR_INFO22 (PHY_RATE_INFO_BASE+0x00000058)
++#define ADR_INFO23 (PHY_RATE_INFO_BASE+0x0000005c)
++#define ADR_INFO24 (PHY_RATE_INFO_BASE+0x00000060)
++#define ADR_INFO25 (PHY_RATE_INFO_BASE+0x00000064)
++#define ADR_INFO26 (PHY_RATE_INFO_BASE+0x00000068)
++#define ADR_INFO27 (PHY_RATE_INFO_BASE+0x0000006c)
++#define ADR_INFO28 (PHY_RATE_INFO_BASE+0x00000070)
++#define ADR_INFO29 (PHY_RATE_INFO_BASE+0x00000074)
++#define ADR_INFO30 (PHY_RATE_INFO_BASE+0x00000078)
++#define ADR_INFO31 (PHY_RATE_INFO_BASE+0x0000007c)
++#define ADR_INFO32 (PHY_RATE_INFO_BASE+0x00000080)
++#define ADR_INFO33 (PHY_RATE_INFO_BASE+0x00000084)
++#define ADR_INFO34 (PHY_RATE_INFO_BASE+0x00000088)
++#define ADR_INFO35 (PHY_RATE_INFO_BASE+0x0000008c)
++#define ADR_INFO36 (PHY_RATE_INFO_BASE+0x00000090)
++#define ADR_INFO37 (PHY_RATE_INFO_BASE+0x00000094)
++#define ADR_INFO38 (PHY_RATE_INFO_BASE+0x00000098)
++#define ADR_INFO_MASK (PHY_RATE_INFO_BASE+0x0000009c)
++#define ADR_INFO_RATE_OFFSET (PHY_RATE_INFO_BASE+0x000000a0)
++#define ADR_INFO_IDX_ADDR (PHY_RATE_INFO_BASE+0x000000a4)
++#define ADR_INFO_LEN_ADDR (PHY_RATE_INFO_BASE+0x000000a8)
++#define ADR_IC_TIME_TAG_0 (PHY_RATE_INFO_BASE+0x000000ac)
++#define ADR_IC_TIME_TAG_1 (PHY_RATE_INFO_BASE+0x000000b0)
++#define ADR_PACKET_ID_ALLOCATION_PRIORITY (PHY_RATE_INFO_BASE+0x000000b4)
++#define ADR_MAC_MODE (MAC_GLB_SET_BASE+0x00000000)
++#define ADR_ALL_SOFTWARE_RESET (MAC_GLB_SET_BASE+0x00000004)
++#define ADR_ENG_SOFTWARE_RESET (MAC_GLB_SET_BASE+0x00000008)
++#define ADR_CSR_SOFTWARE_RESET (MAC_GLB_SET_BASE+0x0000000c)
++#define ADR_MAC_CLOCK_ENABLE (MAC_GLB_SET_BASE+0x00000010)
++#define ADR_MAC_ENGINE_CLOCK_ENABLE (MAC_GLB_SET_BASE+0x00000014)
++#define ADR_MAC_CSR_CLOCK_ENABLE (MAC_GLB_SET_BASE+0x00000018)
++#define ADR_GLBLE_SET (MAC_GLB_SET_BASE+0x0000001c)
++#define ADR_REASON_TRAP0 (MAC_GLB_SET_BASE+0x00000020)
++#define ADR_REASON_TRAP1 (MAC_GLB_SET_BASE+0x00000024)
++#define ADR_BSSID_0 (MAC_GLB_SET_BASE+0x00000028)
++#define ADR_BSSID_1 (MAC_GLB_SET_BASE+0x0000002c)
++#define ADR_SCRT_STATE (MAC_GLB_SET_BASE+0x0000002c)
++#define ADR_STA_MAC_0 (MAC_GLB_SET_BASE+0x00000030)
++#define ADR_STA_MAC_1 (MAC_GLB_SET_BASE+0x00000034)
++#define ADR_SCRT_SET (MAC_GLB_SET_BASE+0x00000038)
++#define ADR_BTCX0 (BTCX_REG_BASE+0x00000000)
++#define ADR_BTCX1 (BTCX_REG_BASE+0x00000004)
++#define ADR_SWITCH_CTL (BTCX_REG_BASE+0x00000008)
++#define ADR_MIB_EN (MIB_REG_BASE+0x00000000)
++#define ADR_MTX_WSID0_SUCC (MIB_REG_BASE+0x00000118)
++#define ADR_MTX_WSID0_FRM (MIB_REG_BASE+0x00000128)
++#define ADR_MTX_WSID0_RETRY (MIB_REG_BASE+0x00000138)
++#define ADR_MTX_WSID0_TOTAL (MIB_REG_BASE+0x00000148)
++#define ADR_MTX_GROUP (MIB_REG_BASE+0x0000016c)
++#define ADR_MTX_FAIL (MIB_REG_BASE+0x00000170)
++#define ADR_MTX_RETRY (MIB_REG_BASE+0x00000174)
++#define ADR_MTX_MULTI_RETRY (MIB_REG_BASE+0x00000178)
++#define ADR_MTX_RTS_SUCCESS (MIB_REG_BASE+0x0000017c)
++#define ADR_MTX_RTS_FAIL (MIB_REG_BASE+0x00000180)
++#define ADR_MTX_ACK_FAIL (MIB_REG_BASE+0x00000184)
++#define ADR_MTX_FRM (MIB_REG_BASE+0x00000188)
++#define ADR_MTX_ACK_TX (MIB_REG_BASE+0x0000018c)
++#define ADR_MTX_CTS_TX (MIB_REG_BASE+0x00000190)
++#define ADR_MRX_DUP_FRM (MIB_REG_BASE+0x00000194)
++#define ADR_MRX_FRG_FRM (MIB_REG_BASE+0x00000198)
++#define ADR_MRX_GROUP_FRM (MIB_REG_BASE+0x0000019c)
++#define ADR_MRX_FCS_ERR (MIB_REG_BASE+0x000001a0)
++#define ADR_MRX_FCS_SUCC (MIB_REG_BASE+0x000001a4)
++#define ADR_MRX_MISS (MIB_REG_BASE+0x000001a8)
++#define ADR_MRX_ALC_FAIL (MIB_REG_BASE+0x000001ac)
++#define ADR_MRX_DAT_NTF (MIB_REG_BASE+0x000001b0)
++#define ADR_MRX_RTS_NTF (MIB_REG_BASE+0x000001b4)
++#define ADR_MRX_CTS_NTF (MIB_REG_BASE+0x000001b8)
++#define ADR_MRX_ACK_NTF (MIB_REG_BASE+0x000001bc)
++#define ADR_MRX_BA_NTF (MIB_REG_BASE+0x000001c0)
++#define ADR_MRX_DATA_NTF (MIB_REG_BASE+0x000001c4)
++#define ADR_MRX_MNG_NTF (MIB_REG_BASE+0x000001c8)
++#define ADR_MRX_DAT_CRC_NTF (MIB_REG_BASE+0x000001cc)
++#define ADR_MRX_BAR_NTF (MIB_REG_BASE+0x000001d0)
++#define ADR_MRX_MB_MISS (MIB_REG_BASE+0x000001d4)
++#define ADR_MRX_NIDLE_MISS (MIB_REG_BASE+0x000001d8)
++#define ADR_MRX_CSR_NTF (MIB_REG_BASE+0x000001dc)
++#define ADR_DBG_Q0_FRM_SUCCESS (MIB_REG_BASE+0x00000218)
++#define ADR_DBG_Q0_FRM_FAIL (MIB_REG_BASE+0x0000021c)
++#define ADR_DBG_Q0_ACK_SUCCESS (MIB_REG_BASE+0x00000220)
++#define ADR_DBG_Q0_ACK_FAIL (MIB_REG_BASE+0x00000224)
++#define ADR_DBG_Q1_FRM_SUCCESS (MIB_REG_BASE+0x00000268)
++#define ADR_DBG_Q1_FRM_FAIL (MIB_REG_BASE+0x0000026c)
++#define ADR_DBG_Q1_ACK_SUCCESS (MIB_REG_BASE+0x00000270)
++#define ADR_DBG_Q1_ACK_FAIL (MIB_REG_BASE+0x00000274)
++#define ADR_DBG_Q2_FRM_SUCCESS (MIB_REG_BASE+0x00000318)
++#define ADR_DBG_Q2_FRM_FAIL (MIB_REG_BASE+0x0000031c)
++#define ADR_DBG_Q2_ACK_SUCCESS (MIB_REG_BASE+0x00000320)
++#define ADR_DBG_Q2_ACK_FAIL (MIB_REG_BASE+0x00000324)
++#define ADR_DBG_Q3_FRM_SUCCESS (MIB_REG_BASE+0x00000368)
++#define ADR_DBG_Q3_FRM_FAIL (MIB_REG_BASE+0x0000036c)
++#define ADR_DBG_Q3_ACK_SUCCESS (MIB_REG_BASE+0x00000370)
++#define ADR_DBG_Q3_ACK_FAIL (MIB_REG_BASE+0x00000374)
++#define ADR_MIB_SCRT_TKIP0 (MIB_REG_BASE+0x00000418)
++#define ADR_MIB_SCRT_TKIP1 (MIB_REG_BASE+0x0000041c)
++#define ADR_MIB_SCRT_TKIP2 (MIB_REG_BASE+0x00000420)
++#define ADR_MIB_SCRT_CCMP0 (MIB_REG_BASE+0x00000424)
++#define ADR_MIB_SCRT_CCMP1 (MIB_REG_BASE+0x00000428)
++#define ADR_DBG_LEN_CRC_FAIL (MIB_REG_BASE+0x00000468)
++#define ADR_DBG_LEN_ALC_FAIL (MIB_REG_BASE+0x0000046c)
++#define ADR_DBG_AMPDU_PASS (MIB_REG_BASE+0x00000470)
++#define ADR_DBG_AMPDU_FAIL (MIB_REG_BASE+0x00000474)
++#define ADR_ID_ALC_FAIL1 (MIB_REG_BASE+0x00000478)
++#define ADR_ID_ALC_FAIL2 (MIB_REG_BASE+0x0000047c)
++#define ADR_CBR_HARD_WIRE_PIN_REGISTER (CBR_A_REG_BASE+0x00110000)
++#define ADR_CBR_MANUAL_ENABLE_REGISTER (CBR_A_REG_BASE+0x00110004)
++#define ADR_CBR_LDO_REGISTER (CBR_A_REG_BASE+0x00110008)
++#define ADR_CBR_ABB_REGISTER_1 (CBR_A_REG_BASE+0x0011000c)
++#define ADR_CBR_ABB_REGISTER_2 (CBR_A_REG_BASE+0x00110010)
++#define ADR_CBR_TX_FE_REGISTER (CBR_A_REG_BASE+0x00110014)
++#define ADR_CBR_RX_FE_REGISTER_1 (CBR_A_REG_BASE+0x00110018)
++#define ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1 (CBR_A_REG_BASE+0x0011001c)
++#define ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2 (CBR_A_REG_BASE+0x00110020)
++#define ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3 (CBR_A_REG_BASE+0x00110024)
++#define ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4 (CBR_A_REG_BASE+0x00110028)
++#define ADR_CBR_RX_FSM_REGISTER (CBR_A_REG_BASE+0x0011002c)
++#define ADR_CBR_RX_ADC_REGISTER (CBR_A_REG_BASE+0x00110030)
++#define ADR_CBR_TX_DAC_REGISTER (CBR_A_REG_BASE+0x00110034)
++#define ADR_CBR_SX_ENABLE_RGISTER (CBR_A_REG_BASE+0x00110038)
++#define ADR_CBR_SYN_RGISTER_1 (CBR_A_REG_BASE+0x0011003c)
++#define ADR_CBR_SYN_RGISTER_2 (CBR_A_REG_BASE+0x00110040)
++#define ADR_CBR_SYN_PFD_CHP (CBR_A_REG_BASE+0x00110044)
++#define ADR_CBR_SYN_VCO_LOBF (CBR_A_REG_BASE+0x00110048)
++#define ADR_CBR_SYN_DIV_SDM_XOSC (CBR_A_REG_BASE+0x0011004c)
++#define ADR_CBR_SYN_LCK1 (CBR_A_REG_BASE+0x00110050)
++#define ADR_CBR_SYN_LCK2 (CBR_A_REG_BASE+0x00110054)
++#define ADR_CBR_DPLL_VCO_REGISTER (CBR_A_REG_BASE+0x00110058)
++#define ADR_CBR_DPLL_CP_PFD_REGISTER (CBR_A_REG_BASE+0x0011005c)
++#define ADR_CBR_DPLL_DIVIDER_REGISTER (CBR_A_REG_BASE+0x00110060)
++#define ADR_CBR_DCOC_IDAC_REGISTER1 (CBR_A_REG_BASE+0x00110064)
++#define ADR_CBR_DCOC_IDAC_REGISTER2 (CBR_A_REG_BASE+0x00110068)
++#define ADR_CBR_DCOC_IDAC_REGISTER3 (CBR_A_REG_BASE+0x0011006c)
++#define ADR_CBR_DCOC_IDAC_REGISTER4 (CBR_A_REG_BASE+0x00110070)
++#define ADR_CBR_DCOC_IDAC_REGISTER5 (CBR_A_REG_BASE+0x00110074)
++#define ADR_CBR_DCOC_IDAC_REGISTER6 (CBR_A_REG_BASE+0x00110078)
++#define ADR_CBR_DCOC_IDAC_REGISTER7 (CBR_A_REG_BASE+0x0011007c)
++#define ADR_CBR_DCOC_IDAC_REGISTER8 (CBR_A_REG_BASE+0x00110080)
++#define ADR_CBR_RCAL_REGISTER (CBR_A_REG_BASE+0x00110084)
++#define ADR_CBR_MANUAL_REGISTER (CBR_A_REG_BASE+0x00110088)
++#define ADR_CBR_TRX_DUMMY_REGISTER (CBR_A_REG_BASE+0x0011008c)
++#define ADR_CBR_SX_DUMMY_REGISTER (CBR_A_REG_BASE+0x00110090)
++#define ADR_CBR_READ_ONLY_FLAGS_1 (CBR_A_REG_BASE+0x00110094)
++#define ADR_CBR_READ_ONLY_FLAGS_2 (CBR_A_REG_BASE+0x00110098)
++#define ADR_CBR_RG_PKT_GEN_0 (CBR_A_REG_BASE+0x00120080)
++#define ADR_CBR_RG_PKT_GEN_1 (CBR_A_REG_BASE+0x00120084)
++#define ADR_CBR_RG_PKT_GEN_2 (CBR_A_REG_BASE+0x00120088)
++#define ADR_CBR_RG_INTEGRATION (CBR_A_REG_BASE+0x00120090)
++#define ADR_CBR_RG_PKT_GEN_TXCNT (CBR_A_REG_BASE+0x00120094)
++#define ADR_CBR_PATTERN_GEN (CBR_A_REG_BASE+0x001203f8)
++#define ADR_MB_CPU_INT (MB_REG_BASE+0x00000004)
++#define ADR_CPU_ID_TB0 (MB_REG_BASE+0x00000008)
++#define ADR_CPU_ID_TB1 (MB_REG_BASE+0x0000000c)
++#define ADR_CH0_TRIG_1 (MB_REG_BASE+0x00000010)
++#define ADR_CH0_TRIG_0 (MB_REG_BASE+0x00000010)
++#define ADR_CH0_PRI_TRIG (MB_REG_BASE+0x00000014)
++#define ADR_MCU_STATUS (MB_REG_BASE+0x00000018)
++#define ADR_RD_IN_FFCNT1 (MB_REG_BASE+0x0000001c)
++#define ADR_RD_IN_FFCNT2 (MB_REG_BASE+0x00000020)
++#define ADR_RD_FFIN_FULL (MB_REG_BASE+0x00000024)
++#define ADR_MBOX_HALT_CFG (MB_REG_BASE+0x0000002c)
++#define ADR_MB_DBG_CFG1 (MB_REG_BASE+0x00000030)
++#define ADR_MB_DBG_CFG2 (MB_REG_BASE+0x00000034)
++#define ADR_MB_DBG_CFG3 (MB_REG_BASE+0x00000038)
++#define ADR_MB_DBG_CFG4 (MB_REG_BASE+0x0000003c)
++#define ADR_MB_OUT_QUEUE_CFG (MB_REG_BASE+0x00000040)
++#define ADR_MB_OUT_QUEUE_FLUSH (MB_REG_BASE+0x00000044)
++#define ADR_RD_FFOUT_CNT1 (MB_REG_BASE+0x00000048)
++#define ADR_RD_FFOUT_CNT2 (MB_REG_BASE+0x0000004c)
++#define ADR_RD_FFOUT_CNT3 (MB_REG_BASE+0x00000050)
++#define ADR_RD_FFOUT_FULL (MB_REG_BASE+0x00000054)
++#define ADR_MB_THRESHOLD6 (MB_REG_BASE+0x0000006c)
++#define ADR_MB_THRESHOLD7 (MB_REG_BASE+0x00000070)
++#define ADR_MB_THRESHOLD8 (MB_REG_BASE+0x00000074)
++#define ADR_MB_THRESHOLD9 (MB_REG_BASE+0x00000078)
++#define ADR_MB_THRESHOLD10 (MB_REG_BASE+0x0000007c)
++#define ADR_MB_TRASH_CFG (MB_REG_BASE+0x00000080)
++#define ADR_MB_IN_FF_FLUSH (MB_REG_BASE+0x00000084)
++#define ADR_CPU_ID_TB2 (MB_REG_BASE+0x00000088)
++#define ADR_CPU_ID_TB3 (MB_REG_BASE+0x0000008c)
++#define ADR_PHY_IQ_LOG_CFG0 (MB_REG_BASE+0x00000090)
++#define ADR_PHY_IQ_LOG_CFG1 (MB_REG_BASE+0x00000094)
++#define ADR_PHY_IQ_LOG_LEN (MB_REG_BASE+0x00000098)
++#define ADR_PHY_IQ_LOG_PTR (MB_REG_BASE+0x0000009c)
++#define ADR_WR_ALC (ID_MNG_REG_BASE+0x00000000)
++#define ADR_GETID (ID_MNG_REG_BASE+0x00000000)
++#define ADR_CH_STA_PRI (ID_MNG_REG_BASE+0x00000004)
++#define ADR_RD_ID0 (ID_MNG_REG_BASE+0x00000008)
++#define ADR_RD_ID1 (ID_MNG_REG_BASE+0x0000000c)
++#define ADR_IMD_CFG (ID_MNG_REG_BASE+0x00000010)
++#define ADR_IMD_STA (ID_MNG_REG_BASE+0x00000014)
++#define ADR_ALC_STA (ID_MNG_REG_BASE+0x00000018)
++#define ADR_TRX_ID_COUNT (ID_MNG_REG_BASE+0x0000001c)
++#define ADR_TRX_ID_THRESHOLD (ID_MNG_REG_BASE+0x00000020)
++#define ADR_TX_ID0 (ID_MNG_REG_BASE+0x00000024)
++#define ADR_TX_ID1 (ID_MNG_REG_BASE+0x00000028)
++#define ADR_RX_ID0 (ID_MNG_REG_BASE+0x0000002c)
++#define ADR_RX_ID1 (ID_MNG_REG_BASE+0x00000030)
++#define ADR_RTN_STA (ID_MNG_REG_BASE+0x00000034)
++#define ADR_ID_LEN_THREADSHOLD1 (ID_MNG_REG_BASE+0x00000038)
++#define ADR_ID_LEN_THREADSHOLD2 (ID_MNG_REG_BASE+0x0000003c)
++#define ADR_CH_ARB_PRI (ID_MNG_REG_BASE+0x00000040)
++#define ADR_TX_ID_REMAIN_STATUS (ID_MNG_REG_BASE+0x00000044)
++#define ADR_ID_INFO_STA (ID_MNG_REG_BASE+0x00000048)
++#define ADR_TX_LIMIT_INTR (ID_MNG_REG_BASE+0x0000004c)
++#define ADR_TX_ID_ALL_INFO (ID_MNG_REG_BASE+0x00000050)
++#define ADR_RD_ID2 (ID_MNG_REG_BASE+0x00000054)
++#define ADR_RD_ID3 (ID_MNG_REG_BASE+0x00000058)
++#define ADR_TX_ID2 (ID_MNG_REG_BASE+0x0000005c)
++#define ADR_TX_ID3 (ID_MNG_REG_BASE+0x00000060)
++#define ADR_RX_ID2 (ID_MNG_REG_BASE+0x00000064)
++#define ADR_RX_ID3 (ID_MNG_REG_BASE+0x00000068)
++#define ADR_TX_ID_ALL_INFO2 (ID_MNG_REG_BASE+0x0000006c)
++#define ADR_TX_ID_ALL_INFO_A (ID_MNG_REG_BASE+0x00000070)
++#define ADR_TX_ID_ALL_INFO_B (ID_MNG_REG_BASE+0x00000074)
++#define ADR_TX_ID_REMAIN_STATUS2 (ID_MNG_REG_BASE+0x00000078)
++#define ADR_ALC_ID_INFO (ID_MNG_REG_BASE+0x0000007c)
++#define ADR_ALC_ID_INF1 (ID_MNG_REG_BASE+0x00000080)
++#define ADR_PHY_EN_0 (CSR_PHY_BASE+0x00000000)
++#define ADR_PHY_EN_1 (CSR_PHY_BASE+0x00000004)
++#define ADR_SVN_VERSION_REG (CSR_PHY_BASE+0x00000008)
++#define ADR_PHY_PKT_GEN_0 (CSR_PHY_BASE+0x0000000c)
++#define ADR_PHY_PKT_GEN_1 (CSR_PHY_BASE+0x00000010)
++#define ADR_PHY_PKT_GEN_2 (CSR_PHY_BASE+0x00000014)
++#define ADR_PHY_PKT_GEN_3 (CSR_PHY_BASE+0x00000018)
++#define ADR_PHY_PKT_GEN_4 (CSR_PHY_BASE+0x0000001c)
++#define ADR_PHY_REG_00 (CSR_PHY_BASE+0x00000020)
++#define ADR_PHY_REG_01 (CSR_PHY_BASE+0x0000002c)
++#define ADR_PHY_REG_02_AGC (CSR_PHY_BASE+0x00000030)
++#define ADR_PHY_REG_03_AGC (CSR_PHY_BASE+0x00000034)
++#define ADR_PHY_REG_04_AGC (CSR_PHY_BASE+0x00000038)
++#define ADR_PHY_REG_05_AGC (CSR_PHY_BASE+0x0000003c)
++#define ADR_PHY_REG_06_11B_DAGC (CSR_PHY_BASE+0x00000040)
++#define ADR_PHY_REG_07_11B_DAGC (CSR_PHY_BASE+0x00000044)
++#define ADR_PHY_REG_08_11GN_DAGC (CSR_PHY_BASE+0x00000048)
++#define ADR_PHY_REG_09_11GN_DAGC (CSR_PHY_BASE+0x0000004c)
++#define ADR_PHY_READ_REG_00_DIG_PWR (CSR_PHY_BASE+0x00000050)
++#define ADR_PHY_READ_REG_01_RF_GAIN_PWR (CSR_PHY_BASE+0x00000054)
++#define ADR_PHY_READ_REG_02_RF_GAIN_PWR (CSR_PHY_BASE+0x00000058)
++#define ADR_PHY_READ_REG_03_RF_GAIN_PWR (CSR_PHY_BASE+0x0000005c)
++#define ADR_PHY_REG_10_TX_DES (CSR_PHY_BASE+0x00000060)
++#define ADR_PHY_REG_11_TX_DES (CSR_PHY_BASE+0x00000064)
++#define ADR_PHY_REG_12_TX_DES (CSR_PHY_BASE+0x00000068)
++#define ADR_PHY_REG_13_RX_DES (CSR_PHY_BASE+0x0000006c)
++#define ADR_PHY_REG_14_RX_DES (CSR_PHY_BASE+0x00000070)
++#define ADR_PHY_REG_15_RX_DES (CSR_PHY_BASE+0x00000074)
++#define ADR_PHY_REG_16_TX_DES_EXCP (CSR_PHY_BASE+0x00000078)
++#define ADR_PHY_REG_17_TX_DES_EXCP (CSR_PHY_BASE+0x0000007c)
++#define ADR_PHY_REG_18_RSSI_SNR (CSR_PHY_BASE+0x00000080)
++#define ADR_PHY_REG_19_DAC_MANUAL (CSR_PHY_BASE+0x00000084)
++#define ADR_PHY_REG_20_MRX_CNT (CSR_PHY_BASE+0x00000088)
++#define ADR_PHY_REG_21_TRX_RAMP (CSR_PHY_BASE+0x00000094)
++#define ADR_PHY_REG_22_TRX_RAMP (CSR_PHY_BASE+0x00000098)
++#define ADR_PHY_REG_23_ANT (CSR_PHY_BASE+0x0000009c)
++#define ADR_PHY_REG_24_MTX_LEN_CNT (CSR_PHY_BASE+0x000000a0)
++#define ADR_PHY_REG_25_MTX_LEN_CNT (CSR_PHY_BASE+0x000000a4)
++#define ADR_PHY_REG_26_MRX_LEN_CNT (CSR_PHY_BASE+0x000000a8)
++#define ADR_PHY_REG_27_MRX_LEN_CNT (CSR_PHY_BASE+0x000000ac)
++#define ADR_PHY_READ_REG_04 (CSR_PHY_BASE+0x000000b0)
++#define ADR_PHY_READ_REG_05 (CSR_PHY_BASE+0x000000b4)
++#define ADR_PHY_REG_28_BIST (CSR_PHY_BASE+0x000000b8)
++#define ADR_PHY_READ_REG_06_BIST (CSR_PHY_BASE+0x000000d8)
++#define ADR_PHY_READ_REG_07_BIST (CSR_PHY_BASE+0x000000f0)
++#define ADR_PHY_REG_29_MTRX_MAC (CSR_PHY_BASE+0x000000fc)
++#define ADR_PHY_READ_REG_08_MTRX_MAC (CSR_PHY_BASE+0x00000100)
++#define ADR_PHY_READ_REG_09_MTRX_MAC (CSR_PHY_BASE+0x00000104)
++#define ADR_PHY_REG_30_TX_UP_FIL (CSR_PHY_BASE+0x00000108)
++#define ADR_PHY_REG_31_TX_UP_FIL (CSR_PHY_BASE+0x0000010c)
++#define ADR_PHY_REG_32_TX_UP_FIL (CSR_PHY_BASE+0x00000110)
++#define ADR_PHY_READ_TBUS (CSR_PHY_BASE+0x000003fc)
++#define ADR_TX_11B_FIL_COEF_00 (CSR_PHY_BASE+0x00001000)
++#define ADR_TX_11B_FIL_COEF_01 (CSR_PHY_BASE+0x00001004)
++#define ADR_TX_11B_FIL_COEF_02 (CSR_PHY_BASE+0x00001008)
++#define ADR_TX_11B_FIL_COEF_03 (CSR_PHY_BASE+0x0000100c)
++#define ADR_TX_11B_FIL_COEF_04 (CSR_PHY_BASE+0x00001010)
++#define ADR_TX_11B_FIL_COEF_05 (CSR_PHY_BASE+0x00001014)
++#define ADR_TX_11B_FIL_COEF_06 (CSR_PHY_BASE+0x00001018)
++#define ADR_TX_11B_FIL_COEF_07 (CSR_PHY_BASE+0x0000101c)
++#define ADR_TX_11B_FIL_COEF_08 (CSR_PHY_BASE+0x00001020)
++#define ADR_TX_11B_FIL_COEF_09 (CSR_PHY_BASE+0x00001024)
++#define ADR_TX_11B_FIL_COEF_10 (CSR_PHY_BASE+0x00001028)
++#define ADR_TX_11B_FIL_COEF_11 (CSR_PHY_BASE+0x0000102c)
++#define ADR_TX_11B_FIL_COEF_12 (CSR_PHY_BASE+0x00001030)
++#define ADR_TX_11B_FIL_COEF_13 (CSR_PHY_BASE+0x00001034)
++#define ADR_TX_11B_FIL_COEF_14 (CSR_PHY_BASE+0x00001038)
++#define ADR_TX_11B_FIL_COEF_15 (CSR_PHY_BASE+0x0000103c)
++#define ADR_TX_11B_FIL_COEF_16 (CSR_PHY_BASE+0x00001040)
++#define ADR_TX_11B_FIL_COEF_17 (CSR_PHY_BASE+0x00001044)
++#define ADR_TX_11B_FIL_COEF_18 (CSR_PHY_BASE+0x00001048)
++#define ADR_TX_11B_FIL_COEF_19 (CSR_PHY_BASE+0x0000104c)
++#define ADR_TX_11B_FIL_COEF_20 (CSR_PHY_BASE+0x00001050)
++#define ADR_TX_11B_FIL_COEF_21 (CSR_PHY_BASE+0x00001054)
++#define ADR_TX_11B_FIL_COEF_22 (CSR_PHY_BASE+0x00001058)
++#define ADR_TX_11B_FIL_COEF_23 (CSR_PHY_BASE+0x0000105c)
++#define ADR_TX_11B_FIL_COEF_24 (CSR_PHY_BASE+0x00001060)
++#define ADR_TX_11B_FIL_COEF_25 (CSR_PHY_BASE+0x00001064)
++#define ADR_TX_11B_FIL_COEF_26 (CSR_PHY_BASE+0x00001068)
++#define ADR_TX_11B_FIL_COEF_27 (CSR_PHY_BASE+0x0000106c)
++#define ADR_TX_11B_FIL_COEF_28 (CSR_PHY_BASE+0x00001070)
++#define ADR_TX_11B_FIL_COEF_29 (CSR_PHY_BASE+0x00001074)
++#define ADR_TX_11B_FIL_COEF_30 (CSR_PHY_BASE+0x00001078)
++#define ADR_TX_11B_FIL_COEF_31 (CSR_PHY_BASE+0x0000107c)
++#define ADR_TX_11B_FIL_COEF_32 (CSR_PHY_BASE+0x00001080)
++#define ADR_TX_11B_FIL_COEF_33 (CSR_PHY_BASE+0x00001084)
++#define ADR_TX_11B_FIL_COEF_34 (CSR_PHY_BASE+0x00001088)
++#define ADR_TX_11B_FIL_COEF_35 (CSR_PHY_BASE+0x0000108c)
++#define ADR_TX_11B_FIL_COEF_36 (CSR_PHY_BASE+0x00001090)
++#define ADR_TX_11B_FIL_COEF_37 (CSR_PHY_BASE+0x00001094)
++#define ADR_TX_11B_FIL_COEF_38 (CSR_PHY_BASE+0x00001098)
++#define ADR_TX_11B_FIL_COEF_39 (CSR_PHY_BASE+0x0000109c)
++#define ADR_TX_11B_FIL_COEF_40 (CSR_PHY_BASE+0x000010a0)
++#define ADR_TX_11B_PLCP (CSR_PHY_BASE+0x000010a4)
++#define ADR_TX_11B_RAMP (CSR_PHY_BASE+0x000010b4)
++#define ADR_TX_11B_EN_CNT_RST_N (CSR_PHY_BASE+0x000010d4)
++#define ADR_TX_11B_EN_CNT (CSR_PHY_BASE+0x000010d8)
++#define ADR_TX_11B_PKT_GEN_CNT (CSR_PHY_BASE+0x00001c00)
++#define ADR_RX_11B_DES_DLY (CSR_PHY_BASE+0x00002000)
++#define ADR_RX_11B_CCA_0 (CSR_PHY_BASE+0x00002004)
++#define ADR_RX_11B_CCA_1 (CSR_PHY_BASE+0x00002008)
++#define ADR_RX_11B_TR_KP_KI_0 (CSR_PHY_BASE+0x0000200c)
++#define ADR_RX_11B_TR_KP_KI_1 (CSR_PHY_BASE+0x00002010)
++#define ADR_RX_11B_CE_CNT_THRESHOLD (CSR_PHY_BASE+0x00002014)
++#define ADR_RX_11B_CE_MU_0 (CSR_PHY_BASE+0x00002018)
++#define ADR_RX_11B_CE_MU_1 (CSR_PHY_BASE+0x0000201c)
++#define ADR_RX_11B_EQ_MU_0 (CSR_PHY_BASE+0x00002020)
++#define ADR_RX_11B_EQ_MU_1 (CSR_PHY_BASE+0x00002024)
++#define ADR_RX_11B_EQ_CR_KP_KI (CSR_PHY_BASE+0x00002028)
++#define ADR_RX_11B_LPF_RATE (CSR_PHY_BASE+0x0000202c)
++#define ADR_RX_11B_CIT_CNT_THRESHOLD (CSR_PHY_BASE+0x00002030)
++#define ADR_RX_11B_EQ_CH_MAIN_TAP (CSR_PHY_BASE+0x00002034)
++#define ADR_RX_11B_SEARCH_CNT_TH (CSR_PHY_BASE+0x0000209c)
++#define ADR_RX_11B_CCA_CONTROL (CSR_PHY_BASE+0x000020a0)
++#define ADR_RX_11B_FREQUENCY_OFFSET (CSR_PHY_BASE+0x000023d4)
++#define ADR_RX_11B_SNR_RSSI (CSR_PHY_BASE+0x000023d8)
++#define ADR_RX_11B_SFD_CRC_CNT (CSR_PHY_BASE+0x000023e4)
++#define ADR_RX_11B_PKT_ERR_AND_PKT_ERR_CNT (CSR_PHY_BASE+0x000023e8)
++#define ADR_RX_11B_PKT_CCA_AND_PKT_CNT (CSR_PHY_BASE+0x000023ec)
++#define ADR_RX_11B_SFD_FILED_0 (CSR_PHY_BASE+0x000023f0)
++#define ADR_RX_11B_SFD_FIELD_1 (CSR_PHY_BASE+0x000023f4)
++#define ADR_RX_11B_PKT_STAT_EN (CSR_PHY_BASE+0x000023f8)
++#define ADR_RX_11B_SOFT_RST (CSR_PHY_BASE+0x000023fc)
++#define ADR_TX_11GN_RAMP (CSR_PHY_BASE+0x000030a4)
++#define ADR_TX_11GN_PLCP (CSR_PHY_BASE+0x000030b8)
++#define ADR_TX_11GN_PKT_GEN_CNT (CSR_PHY_BASE+0x00003c00)
++#define ADR_TX_11GN_PLCP_CRC_ERR_CNT (CSR_PHY_BASE+0x00003c08)
++#define ADR_RX_11GN_DES_DLY (CSR_PHY_BASE+0x00004000)
++#define ADR_RX_11GN_TR_0 (CSR_PHY_BASE+0x00004004)
++#define ADR_RX_11GN_TR_1 (CSR_PHY_BASE+0x00004008)
++#define ADR_RX_11GN_TR_2 (CSR_PHY_BASE+0x0000400c)
++#define ADR_RX_11GN_CCA_0 (CSR_PHY_BASE+0x00004010)
++#define ADR_RX_11GN_CCA_1 (CSR_PHY_BASE+0x00004014)
++#define ADR_RX_11GN_CCA_2 (CSR_PHY_BASE+0x00004018)
++#define ADR_RX_11GN_CCA_FFT_SCALE (CSR_PHY_BASE+0x0000401c)
++#define ADR_RX_11GN_SOFT_DEMAP_0 (CSR_PHY_BASE+0x00004020)
++#define ADR_RX_11GN_SOFT_DEMAP_1 (CSR_PHY_BASE+0x00004024)
++#define ADR_RX_11GN_SOFT_DEMAP_2 (CSR_PHY_BASE+0x00004028)
++#define ADR_RX_11GN_SOFT_DEMAP_3 (CSR_PHY_BASE+0x0000402c)
++#define ADR_RX_11GN_SOFT_DEMAP_4 (CSR_PHY_BASE+0x00004030)
++#define ADR_RX_11GN_SOFT_DEMAP_5 (CSR_PHY_BASE+0x00004034)
++#define ADR_RX_11GN_SYM_BOUND_0 (CSR_PHY_BASE+0x00004038)
++#define ADR_RX_11GN_SYM_BOUND_1 (CSR_PHY_BASE+0x0000409c)
++#define ADR_RX_11GN_CCA_PWR (CSR_PHY_BASE+0x000040c0)
++#define ADR_RX_11GN_CCA_CNT (CSR_PHY_BASE+0x000040c4)
++#define ADR_RX_11GN_CCA_ATCOR_RE_CHECK (CSR_PHY_BASE+0x000040c8)
++#define ADR_RX_11GN_VTB_TB (CSR_PHY_BASE+0x00004130)
++#define ADR_RX_11GN_ERR_UPDATE (CSR_PHY_BASE+0x00004164)
++#define ADR_RX_11GN_SHORT_GI (CSR_PHY_BASE+0x00004180)
++#define ADR_RX_11GN_CHANNEL_UPDATE (CSR_PHY_BASE+0x00004188)
++#define ADR_RX_11GN_PKT_FORMAT_0 (CSR_PHY_BASE+0x00004190)
++#define ADR_RX_11GN_PKT_FORMAT_1 (CSR_PHY_BASE+0x00004194)
++#define ADR_RX_11GN_TX_TIME (CSR_PHY_BASE+0x00004380)
++#define ADR_RX_11GN_STBC_TR_KP_KI (CSR_PHY_BASE+0x00004384)
++#define ADR_RX_11GN_BIST_0 (CSR_PHY_BASE+0x00004388)
++#define ADR_RX_11GN_BIST_1 (CSR_PHY_BASE+0x0000438c)
++#define ADR_RX_11GN_BIST_2 (CSR_PHY_BASE+0x000043c0)
++#define ADR_RX_11GN_BIST_3 (CSR_PHY_BASE+0x000043c4)
++#define ADR_RX_11GN_BIST_4 (CSR_PHY_BASE+0x000043c8)
++#define ADR_RX_11GN_BIST_5 (CSR_PHY_BASE+0x000043cc)
++#define ADR_RX_11GN_SPECTRUM_ANALYZER (CSR_PHY_BASE+0x000043d4)
++#define ADR_RX_11GN_READ_0 (CSR_PHY_BASE+0x000043d8)
++#define ADR_RX_11GN_FREQ_OFFSET (CSR_PHY_BASE+0x000043dc)
++#define ADR_RX_11GN_SIGNAL_FIELD_0 (CSR_PHY_BASE+0x000043e0)
++#define ADR_RX_11GN_SIGNAL_FIELD_1 (CSR_PHY_BASE+0x000043e4)
++#define ADR_RX_11GN_PKT_ERR_CNT (CSR_PHY_BASE+0x000043e8)
++#define ADR_RX_11GN_PKT_CCA_AND_PKT_CNT (CSR_PHY_BASE+0x000043ec)
++#define ADR_RX_11GN_SERVICE_LENGTH_FIELD (CSR_PHY_BASE+0x000043f0)
++#define ADR_RX_11GN_RATE (CSR_PHY_BASE+0x000043f4)
++#define ADR_RX_11GN_STAT_EN (CSR_PHY_BASE+0x000043f8)
++#define ADR_RX_11GN_SOFT_RST (CSR_PHY_BASE+0x000043fc)
++#define ADR_RF_CONTROL_0 (CSR_PHY_BASE+0x00007000)
++#define ADR_RF_CONTROL_1 (CSR_PHY_BASE+0x00007004)
++#define ADR_TX_IQ_CONTROL_0 (CSR_PHY_BASE+0x00007040)
++#define ADR_TX_IQ_CONTROL_1 (CSR_PHY_BASE+0x00007044)
++#define ADR_TX_IQ_CONTROL_2 (CSR_PHY_BASE+0x00007048)
++#define ADR_TX_COMPENSATION_CONTROL (CSR_PHY_BASE+0x0000704c)
++#define ADR_RX_COMPENSATION_CONTROL (CSR_PHY_BASE+0x00007050)
++#define ADR_RX_OBSERVATION_CIRCUIT_0 (CSR_PHY_BASE+0x00007058)
++#define ADR_RX_OBSERVATION_CIRCUIT_1 (CSR_PHY_BASE+0x0000705c)
++#define ADR_RX_OBSERVATION_CIRCUIT_2 (CSR_PHY_BASE+0x00007060)
++#define ADR_RX_OBSERVATION_CIRCUIT_3 (CSR_PHY_BASE+0x00007064)
++#define ADR_RF_IQ_CONTROL_0 (CSR_PHY_BASE+0x0000706c)
++#define ADR_RF_IQ_CONTROL_1 (CSR_PHY_BASE+0x00007070)
++#define ADR_RF_IQ_CONTROL_2 (CSR_PHY_BASE+0x00007074)
++#define ADR_RF_IQ_CONTROL_3 (CSR_PHY_BASE+0x00007078)
++#define ADR_DPD_CONTROL (CSR_PHY_BASE+0x0000711c)
++#define ADR_DPD_GAIN_TABLE_0 (CSR_PHY_BASE+0x00007120)
++#define ADR_DPD_GAIN_TABLE_1 (CSR_PHY_BASE+0x00007124)
++#define ADR_DPD_GAIN_TABLE_2 (CSR_PHY_BASE+0x00007128)
++#define ADR_DPD_GAIN_TABLE_3 (CSR_PHY_BASE+0x00007130)
++#define ADR_DPD_GAIN_TABLE_4 (CSR_PHY_BASE+0x00007134)
++#define ADR_DPD_GAIN_TABLE_5 (CSR_PHY_BASE+0x00007138)
++#define ADR_DPD_GAIN_TABLE_6 (CSR_PHY_BASE+0x0000713c)
++#define ADR_DPD_GAIN_TABLE_7 (CSR_PHY_BASE+0x00007140)
++#define ADR_DPD_GAIN_TABLE_8 (CSR_PHY_BASE+0x00007144)
++#define ADR_DPD_GAIN_TABLE_9 (CSR_PHY_BASE+0x00007148)
++#define ADR_DPD_GAIN_TABLE_A (CSR_PHY_BASE+0x0000714c)
++#define ADR_DPD_GAIN_TABLE_B (CSR_PHY_BASE+0x00007150)
++#define ADR_DPD_GAIN_TABLE_C (CSR_PHY_BASE+0x00007154)
++#define ADR_DPD_PH_TABLE_0 (CSR_PHY_BASE+0x00007170)
++#define ADR_DPD_PH_TABLE_1 (CSR_PHY_BASE+0x00007174)
++#define ADR_DPD_PH_TABLE_2 (CSR_PHY_BASE+0x00007178)
++#define ADR_DPD_PH_TABLE_3 (CSR_PHY_BASE+0x00007180)
++#define ADR_DPD_PH_TABLE_4 (CSR_PHY_BASE+0x00007184)
++#define ADR_DPD_PH_TABLE_5 (CSR_PHY_BASE+0x00007188)
++#define ADR_DPD_PH_TABLE_6 (CSR_PHY_BASE+0x0000718c)
++#define ADR_DPD_PH_TABLE_7 (CSR_PHY_BASE+0x00007190)
++#define ADR_DPD_PH_TABLE_8 (CSR_PHY_BASE+0x00007194)
++#define ADR_DPD_PH_TABLE_9 (CSR_PHY_BASE+0x00007198)
++#define ADR_DPD_PH_TABLE_A (CSR_PHY_BASE+0x0000719c)
++#define ADR_DPD_PH_TABLE_B (CSR_PHY_BASE+0x000071a0)
++#define ADR_DPD_PH_TABLE_C (CSR_PHY_BASE+0x000071a4)
++#define ADR_DPD_GAIN_ESTIMATION_0 (CSR_PHY_BASE+0x000071b0)
++#define ADR_DPD_GAIN_ESTIMATION_1 (CSR_PHY_BASE+0x000071b4)
++#define ADR_DPD_GAIN_ESTIMATION_2 (CSR_PHY_BASE+0x000071b8)
++#define ADR_TX_GAIN_FACTOR (CSR_PHY_BASE+0x000071bc)
++#define ADR_HARD_WIRE_PIN_REGISTER (CSR_RF_BASE+0x00000000)
++#define ADR_MANUAL_ENABLE_REGISTER (CSR_RF_BASE+0x00000004)
++#define ADR_LDO_REGISTER (CSR_RF_BASE+0x00000008)
++#define ADR_ABB_REGISTER_1 (CSR_RF_BASE+0x0000000c)
++#define ADR_ABB_REGISTER_2 (CSR_RF_BASE+0x00000010)
++#define ADR_TX_FE_REGISTER (CSR_RF_BASE+0x00000014)
++#define ADR_RX_FE_REGISTER_1 (CSR_RF_BASE+0x00000018)
++#define ADR_RX_FE_GAIN_DECODER_REGISTER_1 (CSR_RF_BASE+0x0000001c)
++#define ADR_RX_FE_GAIN_DECODER_REGISTER_2 (CSR_RF_BASE+0x00000020)
++#define ADR_RX_FE_GAIN_DECODER_REGISTER_3 (CSR_RF_BASE+0x00000024)
++#define ADR_RX_FE_GAIN_DECODER_REGISTER_4 (CSR_RF_BASE+0x00000028)
++#define ADR_RX_TX_FSM_REGISTER (CSR_RF_BASE+0x0000002c)
++#define ADR_RX_ADC_REGISTER (CSR_RF_BASE+0x00000030)
++#define ADR_TX_DAC_REGISTER (CSR_RF_BASE+0x00000034)
++#define ADR_SX_ENABLE_REGISTER (CSR_RF_BASE+0x00000038)
++#define ADR_SYN_REGISTER_1 (CSR_RF_BASE+0x0000003c)
++#define ADR_SYN_REGISTER_2 (CSR_RF_BASE+0x00000040)
++#define ADR_SYN_PFD_CHP (CSR_RF_BASE+0x00000044)
++#define ADR_SYN_VCO_LOBF (CSR_RF_BASE+0x00000048)
++#define ADR_SYN_DIV_SDM_XOSC (CSR_RF_BASE+0x0000004c)
++#define ADR_SYN_KVCO_XO_FINE_TUNE_CBANK (CSR_RF_BASE+0x00000050)
++#define ADR_SYN_LCK_VT (CSR_RF_BASE+0x00000054)
++#define ADR_DPLL_VCO_REGISTER (CSR_RF_BASE+0x00000058)
++#define ADR_DPLL_CP_PFD_REGISTER (CSR_RF_BASE+0x0000005c)
++#define ADR_DPLL_DIVIDER_REGISTER (CSR_RF_BASE+0x00000060)
++#define ADR_DCOC_IDAC_REGISTER1 (CSR_RF_BASE+0x00000064)
++#define ADR_DCOC_IDAC_REGISTER2 (CSR_RF_BASE+0x00000068)
++#define ADR_DCOC_IDAC_REGISTER3 (CSR_RF_BASE+0x0000006c)
++#define ADR_DCOC_IDAC_REGISTER4 (CSR_RF_BASE+0x00000070)
++#define ADR_DCOC_IDAC_REGISTER5 (CSR_RF_BASE+0x00000074)
++#define ADR_DCOC_IDAC_REGISTER6 (CSR_RF_BASE+0x00000078)
++#define ADR_DCOC_IDAC_REGISTER7 (CSR_RF_BASE+0x0000007c)
++#define ADR_DCOC_IDAC_REGISTER8 (CSR_RF_BASE+0x00000080)
++#define ADR_RCAL_REGISTER (CSR_RF_BASE+0x00000084)
++#define ADR_SX_LCK_BIN_REGISTERS_I (CSR_RF_BASE+0x00000088)
++#define ADR_TRX_DUMMY_REGISTER (CSR_RF_BASE+0x0000008c)
++#define ADR_SX_DUMMY_REGISTER (CSR_RF_BASE+0x00000090)
++#define ADR_READ_ONLY_FLAGS_1 (CSR_RF_BASE+0x00000094)
++#define ADR_READ_ONLY_FLAGS_2 (CSR_RF_BASE+0x00000098)
++#define ADR_DPLL_FB_DIVIDER_REGISTERS_I (CSR_RF_BASE+0x0000009c)
++#define ADR_DPLL_FB_DIVIDER_REGISTERS_II (CSR_RF_BASE+0x000000a0)
++#define ADR_SX_LCK_BIN_REGISTERS_II (CSR_RF_BASE+0x000000a4)
++#define ADR_RC_OSC_32K_CAL_REGISTERS (CSR_RF_BASE+0x000000a8)
++#define ADR_RF_D_DIGITAL_DEBUG_PORT_REGISTER (CSR_RF_BASE+0x000000ac)
++#define ADR_MMU_CTRL (MMU_REG_BASE+0x00000000)
++#define ADR_HS_CTRL (MMU_REG_BASE+0x00000004)
++#define ADR_CPU_POR0_7 (MMU_REG_BASE+0x00000008)
++#define ADR_CPU_POR8_F (MMU_REG_BASE+0x0000000c)
++#define ADR_REG_LEN_CTRL (MMU_REG_BASE+0x00000010)
++#define ADR_DMN_READ_BYPASS (MMU_REG_BASE+0x00000014)
++#define ADR_ALC_RLS_ABORT (MMU_REG_BASE+0x00000018)
++#define ADR_DEBUG_CTL (MMU_REG_BASE+0x00000020)
++#define ADR_DEBUG_OUT (MMU_REG_BASE+0x00000024)
++#define ADR_MMU_STATUS (MMU_REG_BASE+0x00000028)
++#define ADR_DMN_STATUS (MMU_REG_BASE+0x0000002c)
++#define ADR_TAG_STATUS (MMU_REG_BASE+0x00000030)
++#define ADR_DMN_MCU_STATUS (MMU_REG_BASE+0x00000034)
++#define ADR_MB_IDTBL_0_STATUS (MMU_REG_BASE+0x00000040)
++#define ADR_MB_IDTBL_1_STATUS (MMU_REG_BASE+0x00000044)
++#define ADR_MB_IDTBL_2_STATUS (MMU_REG_BASE+0x00000048)
++#define ADR_MB_IDTBL_3_STATUS (MMU_REG_BASE+0x0000004c)
++#define ADR_PKT_IDTBL_0_STATUS (MMU_REG_BASE+0x00000050)
++#define ADR_PKT_IDTBL_1_STATUS (MMU_REG_BASE+0x00000054)
++#define ADR_PKT_IDTBL_2_STATUS (MMU_REG_BASE+0x00000058)
++#define ADR_PKT_IDTBL_3_STATUS (MMU_REG_BASE+0x0000005c)
++#define ADR_DMN_IDTBL_0_STATUS (MMU_REG_BASE+0x00000060)
++#define ADR_DMN_IDTBL_1_STATUS (MMU_REG_BASE+0x00000064)
++#define ADR_DMN_IDTBL_2_STATUS (MMU_REG_BASE+0x00000068)
++#define ADR_DMN_IDTBL_3_STATUS (MMU_REG_BASE+0x0000006c)
++#define ADR_MB_NEQID_0_STATUS (MMU_REG_BASE+0x00000070)
++#define ADR_MB_NEQID_1_STATUS (MMU_REG_BASE+0x00000074)
++#define ADR_MB_NEQID_2_STATUS (MMU_REG_BASE+0x00000078)
++#define ADR_MB_NEQID_3_STATUS (MMU_REG_BASE+0x0000007c)
++#define ADR_PKT_NEQID_0_STATUS (MMU_REG_BASE+0x00000080)
++#define ADR_PKT_NEQID_1_STATUS (MMU_REG_BASE+0x00000084)
++#define ADR_PKT_NEQID_2_STATUS (MMU_REG_BASE+0x00000088)
++#define ADR_PKT_NEQID_3_STATUS (MMU_REG_BASE+0x0000008c)
++#define ADR_ALC_NOCHG_ID_STATUS (MMU_REG_BASE+0x00000090)
++#define ADR_TAG_SRAM0_F_STATUS_0 (MMU_REG_BASE+0x000000a0)
++#define ADR_TAG_SRAM0_F_STATUS_1 (MMU_REG_BASE+0x000000a4)
++#define ADR_TAG_SRAM0_F_STATUS_2 (MMU_REG_BASE+0x000000a8)
++#define ADR_TAG_SRAM0_F_STATUS_3 (MMU_REG_BASE+0x000000ac)
++#define ADR_TAG_SRAM0_F_STATUS_4 (MMU_REG_BASE+0x000000b0)
++#define ADR_TAG_SRAM0_F_STATUS_5 (MMU_REG_BASE+0x000000b4)
++#define ADR_TAG_SRAM0_F_STATUS_6 (MMU_REG_BASE+0x000000b8)
++#define ADR_TAG_SRAM0_F_STATUS_7 (MMU_REG_BASE+0x000000bc)
++#define GET_MCU_ENABLE (((REG32(ADR_BRG_SW_RST)) & 0x00000001 ) >> 0)
++#define GET_MAC_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000002 ) >> 1)
++#define GET_MCU_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000004 ) >> 2)
++#define GET_SDIO_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000008 ) >> 3)
++#define GET_SPI_SLV_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000010 ) >> 4)
++#define GET_UART_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000020 ) >> 5)
++#define GET_DMA_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000040 ) >> 6)
++#define GET_WDT_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000080 ) >> 7)
++#define GET_I2C_SLV_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000100 ) >> 8)
++#define GET_INT_CTL_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000200 ) >> 9)
++#define GET_BTCX_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000400 ) >> 10)
++#define GET_GPIO_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000800 ) >> 11)
++#define GET_US0TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00001000 ) >> 12)
++#define GET_US1TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00002000 ) >> 13)
++#define GET_US2TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00004000 ) >> 14)
++#define GET_US3TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00008000 ) >> 15)
++#define GET_MS0TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00010000 ) >> 16)
++#define GET_MS1TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00020000 ) >> 17)
++#define GET_MS2TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00040000 ) >> 18)
++#define GET_MS3TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00080000 ) >> 19)
++#define GET_RF_BB_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00100000 ) >> 20)
++#define GET_SYS_ALL_RST (((REG32(ADR_BRG_SW_RST)) & 0x00200000 ) >> 21)
++#define GET_DAT_UART_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00400000 ) >> 22)
++#define GET_I2C_MST_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00800000 ) >> 23)
++#define GET_RG_REBOOT (((REG32(ADR_BOOT)) & 0x00000001 ) >> 0)
++#define GET_TRAP_IMG_FLS (((REG32(ADR_BOOT)) & 0x00010000 ) >> 16)
++#define GET_TRAP_REBOOT (((REG32(ADR_BOOT)) & 0x00020000 ) >> 17)
++#define GET_TRAP_BOOT_FLS (((REG32(ADR_BOOT)) & 0x00040000 ) >> 18)
++#define GET_CHIP_ID_31_0 (((REG32(ADR_CHIP_ID_0)) & 0xffffffff ) >> 0)
++#define GET_CHIP_ID_63_32 (((REG32(ADR_CHIP_ID_1)) & 0xffffffff ) >> 0)
++#define GET_CHIP_ID_95_64 (((REG32(ADR_CHIP_ID_2)) & 0xffffffff ) >> 0)
++#define GET_CHIP_ID_127_96 (((REG32(ADR_CHIP_ID_3)) & 0xffffffff ) >> 0)
++#define GET_CK_SEL_1_0 (((REG32(ADR_CLOCK_SELECTION)) & 0x00000003 ) >> 0)
++#define GET_CK_SEL_2 (((REG32(ADR_CLOCK_SELECTION)) & 0x00000004 ) >> 2)
++#define GET_SYS_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000001 ) >> 0)
++#define GET_MAC_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000002 ) >> 1)
++#define GET_MCU_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000004 ) >> 2)
++#define GET_SDIO_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000008 ) >> 3)
++#define GET_SPI_SLV_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000010 ) >> 4)
++#define GET_UART_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000020 ) >> 5)
++#define GET_DMA_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000040 ) >> 6)
++#define GET_WDT_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000080 ) >> 7)
++#define GET_I2C_SLV_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000100 ) >> 8)
++#define GET_INT_CTL_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000200 ) >> 9)
++#define GET_BTCX_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000400 ) >> 10)
++#define GET_GPIO_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000800 ) >> 11)
++#define GET_US0TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00001000 ) >> 12)
++#define GET_US1TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00002000 ) >> 13)
++#define GET_US2TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00004000 ) >> 14)
++#define GET_US3TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00008000 ) >> 15)
++#define GET_MS0TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00010000 ) >> 16)
++#define GET_MS1TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00020000 ) >> 17)
++#define GET_MS2TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00040000 ) >> 18)
++#define GET_MS3TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00080000 ) >> 19)
++#define GET_BIST_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00100000 ) >> 20)
++#define GET_I2C_MST_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00800000 ) >> 23)
++#define GET_BTCX_CSR_CLK_EN (((REG32(ADR_SYS_CSR_CLOCK_ENABLE)) & 0x00000400 ) >> 10)
++#define GET_MCU_DBG_SEL (((REG32(ADR_MCU_DBG_SEL)) & 0x0000003f ) >> 0)
++#define GET_MCU_STOP_NOGRANT (((REG32(ADR_MCU_DBG_SEL)) & 0x00000100 ) >> 8)
++#define GET_MCU_STOP_ANYTIME (((REG32(ADR_MCU_DBG_SEL)) & 0x00000200 ) >> 9)
++#define GET_MCU_DBG_DATA (((REG32(ADR_MCU_DBG_DATA)) & 0xffffffff ) >> 0)
++#define GET_AHB_SW_RST (((REG32(ADR_AHB_BRG_STATUS)) & 0x00000001 ) >> 0)
++#define GET_AHB_ERR_RST (((REG32(ADR_AHB_BRG_STATUS)) & 0x00000002 ) >> 1)
++#define GET_REG_AHB_DEBUG_MX (((REG32(ADR_AHB_BRG_STATUS)) & 0x00000030 ) >> 4)
++#define GET_REG_PKT_W_NBRT (((REG32(ADR_AHB_BRG_STATUS)) & 0x00000100 ) >> 8)
++#define GET_REG_PKT_R_NBRT (((REG32(ADR_AHB_BRG_STATUS)) & 0x00000200 ) >> 9)
++#define GET_IQ_SRAM_SEL_0 (((REG32(ADR_AHB_BRG_STATUS)) & 0x00001000 ) >> 12)
++#define GET_IQ_SRAM_SEL_1 (((REG32(ADR_AHB_BRG_STATUS)) & 0x00002000 ) >> 13)
++#define GET_IQ_SRAM_SEL_2 (((REG32(ADR_AHB_BRG_STATUS)) & 0x00004000 ) >> 14)
++#define GET_AHB_STATUS (((REG32(ADR_AHB_BRG_STATUS)) & 0xffff0000 ) >> 16)
++#define GET_PARALLEL_DR (((REG32(ADR_BIST_BIST_CTRL)) & 0x00000001 ) >> 0)
++#define GET_MBRUN (((REG32(ADR_BIST_BIST_CTRL)) & 0x00000010 ) >> 4)
++#define GET_SHIFT_DR (((REG32(ADR_BIST_BIST_CTRL)) & 0x00000100 ) >> 8)
++#define GET_MODE_REG_SI (((REG32(ADR_BIST_BIST_CTRL)) & 0x00000200 ) >> 9)
++#define GET_SIMULATION_MODE (((REG32(ADR_BIST_BIST_CTRL)) & 0x00000400 ) >> 10)
++#define GET_DBIST_MODE (((REG32(ADR_BIST_BIST_CTRL)) & 0x00000800 ) >> 11)
++#define GET_MODE_REG_IN (((REG32(ADR_BIST_MODE_REG_IN)) & 0x001fffff ) >> 0)
++#define GET_MODE_REG_OUT_MCU (((REG32(ADR_BIST_MODE_REG_OUT)) & 0x001fffff ) >> 0)
++#define GET_MODE_REG_SO_MCU (((REG32(ADR_BIST_MODE_REG_OUT)) & 0x80000000 ) >> 31)
++#define GET_MONITOR_BUS_MCU_31_0 (((REG32(ADR_BIST_MONITOR_BUS_LSB)) & 0xffffffff ) >> 0)
++#define GET_MONITOR_BUS_MCU_33_32 (((REG32(ADR_BIST_MONITOR_BUS_MSB)) & 0x00000003 ) >> 0)
++#define GET_TB_ADR_SEL (((REG32(ADR_TB_ADR_SEL)) & 0x0000ffff ) >> 0)
++#define GET_TB_CS (((REG32(ADR_TB_ADR_SEL)) & 0x80000000 ) >> 31)
++#define GET_TB_RDATA (((REG32(ADR_TB_RDATA)) & 0xffffffff ) >> 0)
++#define GET_UART_W2B_EN (((REG32(ADR_UART_W2B)) & 0x00000001 ) >> 0)
++#define GET_DATA_UART_W2B_EN (((REG32(ADR_UART_W2B)) & 0x00000010 ) >> 4)
++#define GET_AHB_ILL_ADDR (((REG32(ADR_AHB_ILL_ADDR)) & 0xffffffff ) >> 0)
++#define GET_AHB_FEN_ADDR (((REG32(ADR_AHB_FEN_ADDR)) & 0xffffffff ) >> 0)
++#define GET_ILL_ADDR_CLR (((REG32(ADR_AHB_ILLFEN_STATUS)) & 0x00000001 ) >> 0)
++#define GET_FENCE_HIT_CLR (((REG32(ADR_AHB_ILLFEN_STATUS)) & 0x00000002 ) >> 1)
++#define GET_ILL_ADDR_INT (((REG32(ADR_AHB_ILLFEN_STATUS)) & 0x00000010 ) >> 4)
++#define GET_FENCE_HIT_INT (((REG32(ADR_AHB_ILLFEN_STATUS)) & 0x00000020 ) >> 5)
++#define GET_PWM_INI_VALUE_P_A (((REG32(ADR_PWM_A)) & 0x000000ff ) >> 0)
++#define GET_PWM_INI_VALUE_N_A (((REG32(ADR_PWM_A)) & 0x0000ff00 ) >> 8)
++#define GET_PWM_POST_SCALER_A (((REG32(ADR_PWM_A)) & 0x000f0000 ) >> 16)
++#define GET_PWM_ALWAYSON_A (((REG32(ADR_PWM_A)) & 0x20000000 ) >> 29)
++#define GET_PWM_INVERT_A (((REG32(ADR_PWM_A)) & 0x40000000 ) >> 30)
++#define GET_PWM_ENABLE_A (((REG32(ADR_PWM_A)) & 0x80000000 ) >> 31)
++#define GET_PWM_INI_VALUE_P_B (((REG32(ADR_PWM_B)) & 0x000000ff ) >> 0)
++#define GET_PWM_INI_VALUE_N_B (((REG32(ADR_PWM_B)) & 0x0000ff00 ) >> 8)
++#define GET_PWM_POST_SCALER_B (((REG32(ADR_PWM_B)) & 0x000f0000 ) >> 16)
++#define GET_PWM_ALWAYSON_B (((REG32(ADR_PWM_B)) & 0x20000000 ) >> 29)
++#define GET_PWM_INVERT_B (((REG32(ADR_PWM_B)) & 0x40000000 ) >> 30)
++#define GET_PWM_ENABLE_B (((REG32(ADR_PWM_B)) & 0x80000000 ) >> 31)
++#define GET_HBUSREQ_LOCK (((REG32(ADR_HBUSREQ_LOCK)) & 0x00001fff ) >> 0)
++#define GET_HBURST_LOCK (((REG32(ADR_HBURST_LOCK)) & 0x00001fff ) >> 0)
++#define GET_PRESCALER_USTIMER (((REG32(ADR_PRESCALER_USTIMER)) & 0x000001ff ) >> 0)
++#define GET_MODE_REG_IN_MMU (((REG32(ADR_BIST_MODE_REG_IN_MMU)) & 0x0000ffff ) >> 0)
++#define GET_MODE_REG_OUT_MMU (((REG32(ADR_BIST_MODE_REG_OUT_MMU)) & 0x0000ffff ) >> 0)
++#define GET_MODE_REG_SO_MMU (((REG32(ADR_BIST_MODE_REG_OUT_MMU)) & 0x80000000 ) >> 31)
++#define GET_MONITOR_BUS_MMU (((REG32(ADR_BIST_MONITOR_BUS_MMU)) & 0x0007ffff ) >> 0)
++#define GET_TEST_MODE0 (((REG32(ADR_TEST_MODE)) & 0x00000001 ) >> 0)
++#define GET_TEST_MODE1 (((REG32(ADR_TEST_MODE)) & 0x00000002 ) >> 1)
++#define GET_TEST_MODE2 (((REG32(ADR_TEST_MODE)) & 0x00000004 ) >> 2)
++#define GET_TEST_MODE3 (((REG32(ADR_TEST_MODE)) & 0x00000008 ) >> 3)
++#define GET_TEST_MODE4 (((REG32(ADR_TEST_MODE)) & 0x00000010 ) >> 4)
++#define GET_TEST_MODE_ALL (((REG32(ADR_TEST_MODE)) & 0x00000020 ) >> 5)
++#define GET_WDT_INIT (((REG32(ADR_BOOT_INFO)) & 0x00000001 ) >> 0)
++#define GET_SD_HOST_INIT (((REG32(ADR_BOOT_INFO)) & 0x00000002 ) >> 1)
++#define GET_ALLOW_SD_RESET (((REG32(ADR_SD_INIT_CFG)) & 0x00000001 ) >> 0)
++#define GET_UART_NRTS (((REG32(ADR_SPARE_UART_INFO)) & 0x00000001 ) >> 0)
++#define GET_UART_NCTS (((REG32(ADR_SPARE_UART_INFO)) & 0x00000002 ) >> 1)
++#define GET_TU0_TM_INIT_VALUE (((REG32(ADR_TU0_MICROSECOND_TIMER)) & 0x0000ffff ) >> 0)
++#define GET_TU0_TM_MODE (((REG32(ADR_TU0_MICROSECOND_TIMER)) & 0x00010000 ) >> 16)
++#define GET_TU0_TM_INT_STS_DONE (((REG32(ADR_TU0_MICROSECOND_TIMER)) & 0x00020000 ) >> 17)
++#define GET_TU0_TM_INT_MASK (((REG32(ADR_TU0_MICROSECOND_TIMER)) & 0x00040000 ) >> 18)
++#define GET_TU0_TM_CUR_VALUE (((REG32(ADR_TU0_CURRENT_MICROSECOND_TIME_VALUE)) & 0x0000ffff ) >> 0)
++#define GET_TU1_TM_INIT_VALUE (((REG32(ADR_TU1_MICROSECOND_TIMER)) & 0x0000ffff ) >> 0)
++#define GET_TU1_TM_MODE (((REG32(ADR_TU1_MICROSECOND_TIMER)) & 0x00010000 ) >> 16)
++#define GET_TU1_TM_INT_STS_DONE (((REG32(ADR_TU1_MICROSECOND_TIMER)) & 0x00020000 ) >> 17)
++#define GET_TU1_TM_INT_MASK (((REG32(ADR_TU1_MICROSECOND_TIMER)) & 0x00040000 ) >> 18)
++#define GET_TU1_TM_CUR_VALUE (((REG32(ADR_TU1_CURRENT_MICROSECOND_TIME_VALUE)) & 0x0000ffff ) >> 0)
++#define GET_TU2_TM_INIT_VALUE (((REG32(ADR_TU2_MICROSECOND_TIMER)) & 0x0000ffff ) >> 0)
++#define GET_TU2_TM_MODE (((REG32(ADR_TU2_MICROSECOND_TIMER)) & 0x00010000 ) >> 16)
++#define GET_TU2_TM_INT_STS_DONE (((REG32(ADR_TU2_MICROSECOND_TIMER)) & 0x00020000 ) >> 17)
++#define GET_TU2_TM_INT_MASK (((REG32(ADR_TU2_MICROSECOND_TIMER)) & 0x00040000 ) >> 18)
++#define GET_TU2_TM_CUR_VALUE (((REG32(ADR_TU2_CURRENT_MICROSECOND_TIME_VALUE)) & 0x0000ffff ) >> 0)
++#define GET_TU3_TM_INIT_VALUE (((REG32(ADR_TU3_MICROSECOND_TIMER)) & 0x0000ffff ) >> 0)
++#define GET_TU3_TM_MODE (((REG32(ADR_TU3_MICROSECOND_TIMER)) & 0x00010000 ) >> 16)
++#define GET_TU3_TM_INT_STS_DONE (((REG32(ADR_TU3_MICROSECOND_TIMER)) & 0x00020000 ) >> 17)
++#define GET_TU3_TM_INT_MASK (((REG32(ADR_TU3_MICROSECOND_TIMER)) & 0x00040000 ) >> 18)
++#define GET_TU3_TM_CUR_VALUE (((REG32(ADR_TU3_CURRENT_MICROSECOND_TIME_VALUE)) & 0x0000ffff ) >> 0)
++#define GET_TM0_TM_INIT_VALUE (((REG32(ADR_TM0_MILISECOND_TIMER)) & 0x0000ffff ) >> 0)
++#define GET_TM0_TM_MODE (((REG32(ADR_TM0_MILISECOND_TIMER)) & 0x00010000 ) >> 16)
++#define GET_TM0_TM_INT_STS_DONE (((REG32(ADR_TM0_MILISECOND_TIMER)) & 0x00020000 ) >> 17)
++#define GET_TM0_TM_INT_MASK (((REG32(ADR_TM0_MILISECOND_TIMER)) & 0x00040000 ) >> 18)
++#define GET_TM0_TM_CUR_VALUE (((REG32(ADR_TM0_CURRENT_MILISECOND_TIME_VALUE)) & 0x0000ffff ) >> 0)
++#define GET_TM1_TM_INIT_VALUE (((REG32(ADR_TM1_MILISECOND_TIMER)) & 0x0000ffff ) >> 0)
++#define GET_TM1_TM_MODE (((REG32(ADR_TM1_MILISECOND_TIMER)) & 0x00010000 ) >> 16)
++#define GET_TM1_TM_INT_STS_DONE (((REG32(ADR_TM1_MILISECOND_TIMER)) & 0x00020000 ) >> 17)
++#define GET_TM1_TM_INT_MASK (((REG32(ADR_TM1_MILISECOND_TIMER)) & 0x00040000 ) >> 18)
++#define GET_TM1_TM_CUR_VALUE (((REG32(ADR_TM1_CURRENT_MILISECOND_TIME_VALUE)) & 0x0000ffff ) >> 0)
++#define GET_TM2_TM_INIT_VALUE (((REG32(ADR_TM2_MILISECOND_TIMER)) & 0x0000ffff ) >> 0)
++#define GET_TM2_TM_MODE (((REG32(ADR_TM2_MILISECOND_TIMER)) & 0x00010000 ) >> 16)
++#define GET_TM2_TM_INT_STS_DONE (((REG32(ADR_TM2_MILISECOND_TIMER)) & 0x00020000 ) >> 17)
++#define GET_TM2_TM_INT_MASK (((REG32(ADR_TM2_MILISECOND_TIMER)) & 0x00040000 ) >> 18)
++#define GET_TM2_TM_CUR_VALUE (((REG32(ADR_TM2_CURRENT_MILISECOND_TIME_VALUE)) & 0x0000ffff ) >> 0)
++#define GET_TM3_TM_INIT_VALUE (((REG32(ADR_TM3_MILISECOND_TIMER)) & 0x0000ffff ) >> 0)
++#define GET_TM3_TM_MODE (((REG32(ADR_TM3_MILISECOND_TIMER)) & 0x00010000 ) >> 16)
++#define GET_TM3_TM_INT_STS_DONE (((REG32(ADR_TM3_MILISECOND_TIMER)) & 0x00020000 ) >> 17)
++#define GET_TM3_TM_INT_MASK (((REG32(ADR_TM3_MILISECOND_TIMER)) & 0x00040000 ) >> 18)
++#define GET_TM3_TM_CUR_VALUE (((REG32(ADR_TM3_CURRENT_MILISECOND_TIME_VALUE)) & 0x0000ffff ) >> 0)
++#define GET_MCU_WDT_TIME_CNT (((REG32(ADR_MCU_WDOG_REG)) & 0x0000ffff ) >> 0)
++#define GET_MCU_WDT_STATUS (((REG32(ADR_MCU_WDOG_REG)) & 0x00020000 ) >> 17)
++#define GET_MCU_WDOG_ENA (((REG32(ADR_MCU_WDOG_REG)) & 0x80000000 ) >> 31)
++#define GET_SYS_WDT_TIME_CNT (((REG32(ADR_SYS_WDOG_REG)) & 0x0000ffff ) >> 0)
++#define GET_SYS_WDT_STATUS (((REG32(ADR_SYS_WDOG_REG)) & 0x00020000 ) >> 17)
++#define GET_SYS_WDOG_ENA (((REG32(ADR_SYS_WDOG_REG)) & 0x80000000 ) >> 31)
++#define GET_XLNA_EN_O_OE (((REG32(ADR_PAD6)) & 0x00000001 ) >> 0)
++#define GET_XLNA_EN_O_PE (((REG32(ADR_PAD6)) & 0x00000002 ) >> 1)
++#define GET_PAD6_IE (((REG32(ADR_PAD6)) & 0x00000008 ) >> 3)
++#define GET_PAD6_SEL_I (((REG32(ADR_PAD6)) & 0x00000030 ) >> 4)
++#define GET_PAD6_OD (((REG32(ADR_PAD6)) & 0x00000100 ) >> 8)
++#define GET_PAD6_SEL_O (((REG32(ADR_PAD6)) & 0x00001000 ) >> 12)
++#define GET_XLNA_EN_O_C (((REG32(ADR_PAD6)) & 0x10000000 ) >> 28)
++#define GET_WIFI_TX_SW_O_OE (((REG32(ADR_PAD7)) & 0x00000001 ) >> 0)
++#define GET_WIFI_TX_SW_O_PE (((REG32(ADR_PAD7)) & 0x00000002 ) >> 1)
++#define GET_PAD7_IE (((REG32(ADR_PAD7)) & 0x00000008 ) >> 3)
++#define GET_PAD7_SEL_I (((REG32(ADR_PAD7)) & 0x00000030 ) >> 4)
++#define GET_PAD7_OD (((REG32(ADR_PAD7)) & 0x00000100 ) >> 8)
++#define GET_PAD7_SEL_O (((REG32(ADR_PAD7)) & 0x00001000 ) >> 12)
++#define GET_WIFI_TX_SW_O_C (((REG32(ADR_PAD7)) & 0x10000000 ) >> 28)
++#define GET_WIFI_RX_SW_O_OE (((REG32(ADR_PAD8)) & 0x00000001 ) >> 0)
++#define GET_WIFI_RX_SW_O_PE (((REG32(ADR_PAD8)) & 0x00000002 ) >> 1)
++#define GET_PAD8_IE (((REG32(ADR_PAD8)) & 0x00000008 ) >> 3)
++#define GET_PAD8_SEL_I (((REG32(ADR_PAD8)) & 0x00000030 ) >> 4)
++#define GET_PAD8_OD (((REG32(ADR_PAD8)) & 0x00000100 ) >> 8)
++#define GET_WIFI_RX_SW_O_C (((REG32(ADR_PAD8)) & 0x10000000 ) >> 28)
++#define GET_BT_SW_O_OE (((REG32(ADR_PAD9)) & 0x00000001 ) >> 0)
++#define GET_BT_SW_O_PE (((REG32(ADR_PAD9)) & 0x00000002 ) >> 1)
++#define GET_PAD9_IE (((REG32(ADR_PAD9)) & 0x00000008 ) >> 3)
++#define GET_PAD9_SEL_I (((REG32(ADR_PAD9)) & 0x00000030 ) >> 4)
++#define GET_PAD9_OD (((REG32(ADR_PAD9)) & 0x00000100 ) >> 8)
++#define GET_PAD9_SEL_O (((REG32(ADR_PAD9)) & 0x00001000 ) >> 12)
++#define GET_BT_SW_O_C (((REG32(ADR_PAD9)) & 0x10000000 ) >> 28)
++#define GET_XPA_EN_O_OE (((REG32(ADR_PAD11)) & 0x00000001 ) >> 0)
++#define GET_XPA_EN_O_PE (((REG32(ADR_PAD11)) & 0x00000002 ) >> 1)
++#define GET_PAD11_IE (((REG32(ADR_PAD11)) & 0x00000008 ) >> 3)
++#define GET_PAD11_SEL_I (((REG32(ADR_PAD11)) & 0x00000030 ) >> 4)
++#define GET_PAD11_OD (((REG32(ADR_PAD11)) & 0x00000100 ) >> 8)
++#define GET_PAD11_SEL_O (((REG32(ADR_PAD11)) & 0x00001000 ) >> 12)
++#define GET_XPA_EN_O_C (((REG32(ADR_PAD11)) & 0x10000000 ) >> 28)
++#define GET_PAD15_OE (((REG32(ADR_PAD15)) & 0x00000001 ) >> 0)
++#define GET_PAD15_PE (((REG32(ADR_PAD15)) & 0x00000002 ) >> 1)
++#define GET_PAD15_DS (((REG32(ADR_PAD15)) & 0x00000004 ) >> 2)
++#define GET_PAD15_IE (((REG32(ADR_PAD15)) & 0x00000008 ) >> 3)
++#define GET_PAD15_SEL_I (((REG32(ADR_PAD15)) & 0x00000030 ) >> 4)
++#define GET_PAD15_OD (((REG32(ADR_PAD15)) & 0x00000100 ) >> 8)
++#define GET_PAD15_SEL_O (((REG32(ADR_PAD15)) & 0x00001000 ) >> 12)
++#define GET_TEST_1_ID (((REG32(ADR_PAD15)) & 0x10000000 ) >> 28)
++#define GET_PAD16_OE (((REG32(ADR_PAD16)) & 0x00000001 ) >> 0)
++#define GET_PAD16_PE (((REG32(ADR_PAD16)) & 0x00000002 ) >> 1)
++#define GET_PAD16_DS (((REG32(ADR_PAD16)) & 0x00000004 ) >> 2)
++#define GET_PAD16_IE (((REG32(ADR_PAD16)) & 0x00000008 ) >> 3)
++#define GET_PAD16_SEL_I (((REG32(ADR_PAD16)) & 0x00000030 ) >> 4)
++#define GET_PAD16_OD (((REG32(ADR_PAD16)) & 0x00000100 ) >> 8)
++#define GET_PAD16_SEL_O (((REG32(ADR_PAD16)) & 0x00001000 ) >> 12)
++#define GET_TEST_2_ID (((REG32(ADR_PAD16)) & 0x10000000 ) >> 28)
++#define GET_PAD17_OE (((REG32(ADR_PAD17)) & 0x00000001 ) >> 0)
++#define GET_PAD17_PE (((REG32(ADR_PAD17)) & 0x00000002 ) >> 1)
++#define GET_PAD17_DS (((REG32(ADR_PAD17)) & 0x00000004 ) >> 2)
++#define GET_PAD17_IE (((REG32(ADR_PAD17)) & 0x00000008 ) >> 3)
++#define GET_PAD17_SEL_I (((REG32(ADR_PAD17)) & 0x00000030 ) >> 4)
++#define GET_PAD17_OD (((REG32(ADR_PAD17)) & 0x00000100 ) >> 8)
++#define GET_PAD17_SEL_O (((REG32(ADR_PAD17)) & 0x00001000 ) >> 12)
++#define GET_TEST_3_ID (((REG32(ADR_PAD17)) & 0x10000000 ) >> 28)
++#define GET_PAD18_OE (((REG32(ADR_PAD18)) & 0x00000001 ) >> 0)
++#define GET_PAD18_PE (((REG32(ADR_PAD18)) & 0x00000002 ) >> 1)
++#define GET_PAD18_DS (((REG32(ADR_PAD18)) & 0x00000004 ) >> 2)
++#define GET_PAD18_IE (((REG32(ADR_PAD18)) & 0x00000008 ) >> 3)
++#define GET_PAD18_SEL_I (((REG32(ADR_PAD18)) & 0x00000030 ) >> 4)
++#define GET_PAD18_OD (((REG32(ADR_PAD18)) & 0x00000100 ) >> 8)
++#define GET_PAD18_SEL_O (((REG32(ADR_PAD18)) & 0x00003000 ) >> 12)
++#define GET_TEST_4_ID (((REG32(ADR_PAD18)) & 0x10000000 ) >> 28)
++#define GET_PAD19_OE (((REG32(ADR_PAD19)) & 0x00000001 ) >> 0)
++#define GET_PAD19_PE (((REG32(ADR_PAD19)) & 0x00000002 ) >> 1)
++#define GET_PAD19_DS (((REG32(ADR_PAD19)) & 0x00000004 ) >> 2)
++#define GET_PAD19_IE (((REG32(ADR_PAD19)) & 0x00000008 ) >> 3)
++#define GET_PAD19_SEL_I (((REG32(ADR_PAD19)) & 0x00000030 ) >> 4)
++#define GET_PAD19_OD (((REG32(ADR_PAD19)) & 0x00000100 ) >> 8)
++#define GET_PAD19_SEL_O (((REG32(ADR_PAD19)) & 0x00007000 ) >> 12)
++#define GET_SHORT_TO_20_ID (((REG32(ADR_PAD19)) & 0x10000000 ) >> 28)
++#define GET_PAD20_OE (((REG32(ADR_PAD20)) & 0x00000001 ) >> 0)
++#define GET_PAD20_PE (((REG32(ADR_PAD20)) & 0x00000002 ) >> 1)
++#define GET_PAD20_DS (((REG32(ADR_PAD20)) & 0x00000004 ) >> 2)
++#define GET_PAD20_IE (((REG32(ADR_PAD20)) & 0x00000008 ) >> 3)
++#define GET_PAD20_SEL_I (((REG32(ADR_PAD20)) & 0x000000f0 ) >> 4)
++#define GET_PAD20_OD (((REG32(ADR_PAD20)) & 0x00000100 ) >> 8)
++#define GET_PAD20_SEL_O (((REG32(ADR_PAD20)) & 0x00003000 ) >> 12)
++#define GET_STRAP0 (((REG32(ADR_PAD20)) & 0x08000000 ) >> 27)
++#define GET_GPIO_TEST_1_ID (((REG32(ADR_PAD20)) & 0x10000000 ) >> 28)
++#define GET_PAD21_OE (((REG32(ADR_PAD21)) & 0x00000001 ) >> 0)
++#define GET_PAD21_PE (((REG32(ADR_PAD21)) & 0x00000002 ) >> 1)
++#define GET_PAD21_DS (((REG32(ADR_PAD21)) & 0x00000004 ) >> 2)
++#define GET_PAD21_IE (((REG32(ADR_PAD21)) & 0x00000008 ) >> 3)
++#define GET_PAD21_SEL_I (((REG32(ADR_PAD21)) & 0x00000070 ) >> 4)
++#define GET_PAD21_OD (((REG32(ADR_PAD21)) & 0x00000100 ) >> 8)
++#define GET_PAD21_SEL_O (((REG32(ADR_PAD21)) & 0x00003000 ) >> 12)
++#define GET_STRAP3 (((REG32(ADR_PAD21)) & 0x08000000 ) >> 27)
++#define GET_GPIO_TEST_2_ID (((REG32(ADR_PAD21)) & 0x10000000 ) >> 28)
++#define GET_PAD22_OE (((REG32(ADR_PAD22)) & 0x00000001 ) >> 0)
++#define GET_PAD22_PE (((REG32(ADR_PAD22)) & 0x00000002 ) >> 1)
++#define GET_PAD22_DS (((REG32(ADR_PAD22)) & 0x00000004 ) >> 2)
++#define GET_PAD22_IE (((REG32(ADR_PAD22)) & 0x00000008 ) >> 3)
++#define GET_PAD22_SEL_I (((REG32(ADR_PAD22)) & 0x00000070 ) >> 4)
++#define GET_PAD22_OD (((REG32(ADR_PAD22)) & 0x00000100 ) >> 8)
++#define GET_PAD22_SEL_O (((REG32(ADR_PAD22)) & 0x00007000 ) >> 12)
++#define GET_PAD22_SEL_OE (((REG32(ADR_PAD22)) & 0x00100000 ) >> 20)
++#define GET_GPIO_TEST_3_ID (((REG32(ADR_PAD22)) & 0x10000000 ) >> 28)
++#define GET_PAD24_OE (((REG32(ADR_PAD24)) & 0x00000001 ) >> 0)
++#define GET_PAD24_PE (((REG32(ADR_PAD24)) & 0x00000002 ) >> 1)
++#define GET_PAD24_DS (((REG32(ADR_PAD24)) & 0x00000004 ) >> 2)
++#define GET_PAD24_IE (((REG32(ADR_PAD24)) & 0x00000008 ) >> 3)
++#define GET_PAD24_SEL_I (((REG32(ADR_PAD24)) & 0x00000030 ) >> 4)
++#define GET_PAD24_OD (((REG32(ADR_PAD24)) & 0x00000100 ) >> 8)
++#define GET_PAD24_SEL_O (((REG32(ADR_PAD24)) & 0x00007000 ) >> 12)
++#define GET_GPIO_TEST_4_ID (((REG32(ADR_PAD24)) & 0x10000000 ) >> 28)
++#define GET_PAD25_OE (((REG32(ADR_PAD25)) & 0x00000001 ) >> 0)
++#define GET_PAD25_PE (((REG32(ADR_PAD25)) & 0x00000002 ) >> 1)
++#define GET_PAD25_DS (((REG32(ADR_PAD25)) & 0x00000004 ) >> 2)
++#define GET_PAD25_IE (((REG32(ADR_PAD25)) & 0x00000008 ) >> 3)
++#define GET_PAD25_SEL_I (((REG32(ADR_PAD25)) & 0x00000070 ) >> 4)
++#define GET_PAD25_OD (((REG32(ADR_PAD25)) & 0x00000100 ) >> 8)
++#define GET_PAD25_SEL_O (((REG32(ADR_PAD25)) & 0x00007000 ) >> 12)
++#define GET_PAD25_SEL_OE (((REG32(ADR_PAD25)) & 0x00100000 ) >> 20)
++#define GET_STRAP1 (((REG32(ADR_PAD25)) & 0x08000000 ) >> 27)
++#define GET_GPIO_1_ID (((REG32(ADR_PAD25)) & 0x10000000 ) >> 28)
++#define GET_PAD27_OE (((REG32(ADR_PAD27)) & 0x00000001 ) >> 0)
++#define GET_PAD27_PE (((REG32(ADR_PAD27)) & 0x00000002 ) >> 1)
++#define GET_PAD27_DS (((REG32(ADR_PAD27)) & 0x00000004 ) >> 2)
++#define GET_PAD27_IE (((REG32(ADR_PAD27)) & 0x00000008 ) >> 3)
++#define GET_PAD27_SEL_I (((REG32(ADR_PAD27)) & 0x00000070 ) >> 4)
++#define GET_PAD27_OD (((REG32(ADR_PAD27)) & 0x00000100 ) >> 8)
++#define GET_PAD27_SEL_O (((REG32(ADR_PAD27)) & 0x00007000 ) >> 12)
++#define GET_GPIO_2_ID (((REG32(ADR_PAD27)) & 0x10000000 ) >> 28)
++#define GET_PAD28_OE (((REG32(ADR_PAD28)) & 0x00000001 ) >> 0)
++#define GET_PAD28_PE (((REG32(ADR_PAD28)) & 0x00000002 ) >> 1)
++#define GET_PAD28_DS (((REG32(ADR_PAD28)) & 0x00000004 ) >> 2)
++#define GET_PAD28_IE (((REG32(ADR_PAD28)) & 0x00000008 ) >> 3)
++#define GET_PAD28_SEL_I (((REG32(ADR_PAD28)) & 0x00000070 ) >> 4)
++#define GET_PAD28_OD (((REG32(ADR_PAD28)) & 0x00000100 ) >> 8)
++#define GET_PAD28_SEL_O (((REG32(ADR_PAD28)) & 0x0000f000 ) >> 12)
++#define GET_PAD28_SEL_OE (((REG32(ADR_PAD28)) & 0x00100000 ) >> 20)
++#define GET_GPIO_3_ID (((REG32(ADR_PAD28)) & 0x10000000 ) >> 28)
++#define GET_PAD29_OE (((REG32(ADR_PAD29)) & 0x00000001 ) >> 0)
++#define GET_PAD29_PE (((REG32(ADR_PAD29)) & 0x00000002 ) >> 1)
++#define GET_PAD29_DS (((REG32(ADR_PAD29)) & 0x00000004 ) >> 2)
++#define GET_PAD29_IE (((REG32(ADR_PAD29)) & 0x00000008 ) >> 3)
++#define GET_PAD29_SEL_I (((REG32(ADR_PAD29)) & 0x00000070 ) >> 4)
++#define GET_PAD29_OD (((REG32(ADR_PAD29)) & 0x00000100 ) >> 8)
++#define GET_PAD29_SEL_O (((REG32(ADR_PAD29)) & 0x00007000 ) >> 12)
++#define GET_GPIO_TEST_5_ID (((REG32(ADR_PAD29)) & 0x10000000 ) >> 28)
++#define GET_PAD30_OE (((REG32(ADR_PAD30)) & 0x00000001 ) >> 0)
++#define GET_PAD30_PE (((REG32(ADR_PAD30)) & 0x00000002 ) >> 1)
++#define GET_PAD30_DS (((REG32(ADR_PAD30)) & 0x00000004 ) >> 2)
++#define GET_PAD30_IE (((REG32(ADR_PAD30)) & 0x00000008 ) >> 3)
++#define GET_PAD30_SEL_I (((REG32(ADR_PAD30)) & 0x00000030 ) >> 4)
++#define GET_PAD30_OD (((REG32(ADR_PAD30)) & 0x00000100 ) >> 8)
++#define GET_PAD30_SEL_O (((REG32(ADR_PAD30)) & 0x00003000 ) >> 12)
++#define GET_TEST_6_ID (((REG32(ADR_PAD30)) & 0x10000000 ) >> 28)
++#define GET_PAD31_OE (((REG32(ADR_PAD31)) & 0x00000001 ) >> 0)
++#define GET_PAD31_PE (((REG32(ADR_PAD31)) & 0x00000002 ) >> 1)
++#define GET_PAD31_DS (((REG32(ADR_PAD31)) & 0x00000004 ) >> 2)
++#define GET_PAD31_IE (((REG32(ADR_PAD31)) & 0x00000008 ) >> 3)
++#define GET_PAD31_SEL_I (((REG32(ADR_PAD31)) & 0x00000030 ) >> 4)
++#define GET_PAD31_OD (((REG32(ADR_PAD31)) & 0x00000100 ) >> 8)
++#define GET_PAD31_SEL_O (((REG32(ADR_PAD31)) & 0x00003000 ) >> 12)
++#define GET_TEST_7_ID (((REG32(ADR_PAD31)) & 0x10000000 ) >> 28)
++#define GET_PAD32_OE (((REG32(ADR_PAD32)) & 0x00000001 ) >> 0)
++#define GET_PAD32_PE (((REG32(ADR_PAD32)) & 0x00000002 ) >> 1)
++#define GET_PAD32_DS (((REG32(ADR_PAD32)) & 0x00000004 ) >> 2)
++#define GET_PAD32_IE (((REG32(ADR_PAD32)) & 0x00000008 ) >> 3)
++#define GET_PAD32_SEL_I (((REG32(ADR_PAD32)) & 0x00000030 ) >> 4)
++#define GET_PAD32_OD (((REG32(ADR_PAD32)) & 0x00000100 ) >> 8)
++#define GET_PAD32_SEL_O (((REG32(ADR_PAD32)) & 0x00003000 ) >> 12)
++#define GET_TEST_8_ID (((REG32(ADR_PAD32)) & 0x10000000 ) >> 28)
++#define GET_PAD33_OE (((REG32(ADR_PAD33)) & 0x00000001 ) >> 0)
++#define GET_PAD33_PE (((REG32(ADR_PAD33)) & 0x00000002 ) >> 1)
++#define GET_PAD33_DS (((REG32(ADR_PAD33)) & 0x00000004 ) >> 2)
++#define GET_PAD33_IE (((REG32(ADR_PAD33)) & 0x00000008 ) >> 3)
++#define GET_PAD33_SEL_I (((REG32(ADR_PAD33)) & 0x00000030 ) >> 4)
++#define GET_PAD33_OD (((REG32(ADR_PAD33)) & 0x00000100 ) >> 8)
++#define GET_PAD33_SEL_O (((REG32(ADR_PAD33)) & 0x00003000 ) >> 12)
++#define GET_TEST_9_ID (((REG32(ADR_PAD33)) & 0x10000000 ) >> 28)
++#define GET_PAD34_OE (((REG32(ADR_PAD34)) & 0x00000001 ) >> 0)
++#define GET_PAD34_PE (((REG32(ADR_PAD34)) & 0x00000002 ) >> 1)
++#define GET_PAD34_DS (((REG32(ADR_PAD34)) & 0x00000004 ) >> 2)
++#define GET_PAD34_IE (((REG32(ADR_PAD34)) & 0x00000008 ) >> 3)
++#define GET_PAD34_SEL_I (((REG32(ADR_PAD34)) & 0x00000030 ) >> 4)
++#define GET_PAD34_OD (((REG32(ADR_PAD34)) & 0x00000100 ) >> 8)
++#define GET_PAD34_SEL_O (((REG32(ADR_PAD34)) & 0x00003000 ) >> 12)
++#define GET_TEST_10_ID (((REG32(ADR_PAD34)) & 0x10000000 ) >> 28)
++#define GET_PAD42_OE (((REG32(ADR_PAD42)) & 0x00000001 ) >> 0)
++#define GET_PAD42_PE (((REG32(ADR_PAD42)) & 0x00000002 ) >> 1)
++#define GET_PAD42_DS (((REG32(ADR_PAD42)) & 0x00000004 ) >> 2)
++#define GET_PAD42_IE (((REG32(ADR_PAD42)) & 0x00000008 ) >> 3)
++#define GET_PAD42_SEL_I (((REG32(ADR_PAD42)) & 0x00000030 ) >> 4)
++#define GET_PAD42_OD (((REG32(ADR_PAD42)) & 0x00000100 ) >> 8)
++#define GET_PAD42_SEL_O (((REG32(ADR_PAD42)) & 0x00001000 ) >> 12)
++#define GET_TEST_11_ID (((REG32(ADR_PAD42)) & 0x10000000 ) >> 28)
++#define GET_PAD43_OE (((REG32(ADR_PAD43)) & 0x00000001 ) >> 0)
++#define GET_PAD43_PE (((REG32(ADR_PAD43)) & 0x00000002 ) >> 1)
++#define GET_PAD43_DS (((REG32(ADR_PAD43)) & 0x00000004 ) >> 2)
++#define GET_PAD43_IE (((REG32(ADR_PAD43)) & 0x00000008 ) >> 3)
++#define GET_PAD43_SEL_I (((REG32(ADR_PAD43)) & 0x00000030 ) >> 4)
++#define GET_PAD43_OD (((REG32(ADR_PAD43)) & 0x00000100 ) >> 8)
++#define GET_PAD43_SEL_O (((REG32(ADR_PAD43)) & 0x00001000 ) >> 12)
++#define GET_TEST_12_ID (((REG32(ADR_PAD43)) & 0x10000000 ) >> 28)
++#define GET_PAD44_OE (((REG32(ADR_PAD44)) & 0x00000001 ) >> 0)
++#define GET_PAD44_PE (((REG32(ADR_PAD44)) & 0x00000002 ) >> 1)
++#define GET_PAD44_DS (((REG32(ADR_PAD44)) & 0x00000004 ) >> 2)
++#define GET_PAD44_IE (((REG32(ADR_PAD44)) & 0x00000008 ) >> 3)
++#define GET_PAD44_SEL_I (((REG32(ADR_PAD44)) & 0x00000030 ) >> 4)
++#define GET_PAD44_OD (((REG32(ADR_PAD44)) & 0x00000100 ) >> 8)
++#define GET_PAD44_SEL_O (((REG32(ADR_PAD44)) & 0x00003000 ) >> 12)
++#define GET_TEST_13_ID (((REG32(ADR_PAD44)) & 0x10000000 ) >> 28)
++#define GET_PAD45_OE (((REG32(ADR_PAD45)) & 0x00000001 ) >> 0)
++#define GET_PAD45_PE (((REG32(ADR_PAD45)) & 0x00000002 ) >> 1)
++#define GET_PAD45_DS (((REG32(ADR_PAD45)) & 0x00000004 ) >> 2)
++#define GET_PAD45_IE (((REG32(ADR_PAD45)) & 0x00000008 ) >> 3)
++#define GET_PAD45_SEL_I (((REG32(ADR_PAD45)) & 0x00000030 ) >> 4)
++#define GET_PAD45_OD (((REG32(ADR_PAD45)) & 0x00000100 ) >> 8)
++#define GET_PAD45_SEL_O (((REG32(ADR_PAD45)) & 0x00003000 ) >> 12)
++#define GET_TEST_14_ID (((REG32(ADR_PAD45)) & 0x10000000 ) >> 28)
++#define GET_PAD46_OE (((REG32(ADR_PAD46)) & 0x00000001 ) >> 0)
++#define GET_PAD46_PE (((REG32(ADR_PAD46)) & 0x00000002 ) >> 1)
++#define GET_PAD46_DS (((REG32(ADR_PAD46)) & 0x00000004 ) >> 2)
++#define GET_PAD46_IE (((REG32(ADR_PAD46)) & 0x00000008 ) >> 3)
++#define GET_PAD46_SEL_I (((REG32(ADR_PAD46)) & 0x00000030 ) >> 4)
++#define GET_PAD46_OD (((REG32(ADR_PAD46)) & 0x00000100 ) >> 8)
++#define GET_PAD46_SEL_O (((REG32(ADR_PAD46)) & 0x00003000 ) >> 12)
++#define GET_TEST_15_ID (((REG32(ADR_PAD46)) & 0x10000000 ) >> 28)
++#define GET_PAD47_OE (((REG32(ADR_PAD47)) & 0x00000001 ) >> 0)
++#define GET_PAD47_PE (((REG32(ADR_PAD47)) & 0x00000002 ) >> 1)
++#define GET_PAD47_DS (((REG32(ADR_PAD47)) & 0x00000004 ) >> 2)
++#define GET_PAD47_SEL_I (((REG32(ADR_PAD47)) & 0x00000030 ) >> 4)
++#define GET_PAD47_OD (((REG32(ADR_PAD47)) & 0x00000100 ) >> 8)
++#define GET_PAD47_SEL_O (((REG32(ADR_PAD47)) & 0x00003000 ) >> 12)
++#define GET_PAD47_SEL_OE (((REG32(ADR_PAD47)) & 0x00100000 ) >> 20)
++#define GET_GPIO_9_ID (((REG32(ADR_PAD47)) & 0x10000000 ) >> 28)
++#define GET_PAD48_OE (((REG32(ADR_PAD48)) & 0x00000001 ) >> 0)
++#define GET_PAD48_PE (((REG32(ADR_PAD48)) & 0x00000002 ) >> 1)
++#define GET_PAD48_DS (((REG32(ADR_PAD48)) & 0x00000004 ) >> 2)
++#define GET_PAD48_IE (((REG32(ADR_PAD48)) & 0x00000008 ) >> 3)
++#define GET_PAD48_SEL_I (((REG32(ADR_PAD48)) & 0x00000070 ) >> 4)
++#define GET_PAD48_OD (((REG32(ADR_PAD48)) & 0x00000100 ) >> 8)
++#define GET_PAD48_PE_SEL (((REG32(ADR_PAD48)) & 0x00000800 ) >> 11)
++#define GET_PAD48_SEL_O (((REG32(ADR_PAD48)) & 0x00003000 ) >> 12)
++#define GET_PAD48_SEL_OE (((REG32(ADR_PAD48)) & 0x00100000 ) >> 20)
++#define GET_GPIO_10_ID (((REG32(ADR_PAD48)) & 0x10000000 ) >> 28)
++#define GET_PAD49_OE (((REG32(ADR_PAD49)) & 0x00000001 ) >> 0)
++#define GET_PAD49_PE (((REG32(ADR_PAD49)) & 0x00000002 ) >> 1)
++#define GET_PAD49_DS (((REG32(ADR_PAD49)) & 0x00000004 ) >> 2)
++#define GET_PAD49_IE (((REG32(ADR_PAD49)) & 0x00000008 ) >> 3)
++#define GET_PAD49_SEL_I (((REG32(ADR_PAD49)) & 0x00000070 ) >> 4)
++#define GET_PAD49_OD (((REG32(ADR_PAD49)) & 0x00000100 ) >> 8)
++#define GET_PAD49_SEL_O (((REG32(ADR_PAD49)) & 0x00003000 ) >> 12)
++#define GET_PAD49_SEL_OE (((REG32(ADR_PAD49)) & 0x00100000 ) >> 20)
++#define GET_GPIO_11_ID (((REG32(ADR_PAD49)) & 0x10000000 ) >> 28)
++#define GET_PAD50_OE (((REG32(ADR_PAD50)) & 0x00000001 ) >> 0)
++#define GET_PAD50_PE (((REG32(ADR_PAD50)) & 0x00000002 ) >> 1)
++#define GET_PAD50_DS (((REG32(ADR_PAD50)) & 0x00000004 ) >> 2)
++#define GET_PAD50_IE (((REG32(ADR_PAD50)) & 0x00000008 ) >> 3)
++#define GET_PAD50_SEL_I (((REG32(ADR_PAD50)) & 0x00000070 ) >> 4)
++#define GET_PAD50_OD (((REG32(ADR_PAD50)) & 0x00000100 ) >> 8)
++#define GET_PAD50_SEL_O (((REG32(ADR_PAD50)) & 0x00003000 ) >> 12)
++#define GET_PAD50_SEL_OE (((REG32(ADR_PAD50)) & 0x00100000 ) >> 20)
++#define GET_GPIO_12_ID (((REG32(ADR_PAD50)) & 0x10000000 ) >> 28)
++#define GET_PAD51_OE (((REG32(ADR_PAD51)) & 0x00000001 ) >> 0)
++#define GET_PAD51_PE (((REG32(ADR_PAD51)) & 0x00000002 ) >> 1)
++#define GET_PAD51_DS (((REG32(ADR_PAD51)) & 0x00000004 ) >> 2)
++#define GET_PAD51_IE (((REG32(ADR_PAD51)) & 0x00000008 ) >> 3)
++#define GET_PAD51_SEL_I (((REG32(ADR_PAD51)) & 0x00000030 ) >> 4)
++#define GET_PAD51_OD (((REG32(ADR_PAD51)) & 0x00000100 ) >> 8)
++#define GET_PAD51_SEL_O (((REG32(ADR_PAD51)) & 0x00001000 ) >> 12)
++#define GET_PAD51_SEL_OE (((REG32(ADR_PAD51)) & 0x00100000 ) >> 20)
++#define GET_GPIO_13_ID (((REG32(ADR_PAD51)) & 0x10000000 ) >> 28)
++#define GET_PAD52_OE (((REG32(ADR_PAD52)) & 0x00000001 ) >> 0)
++#define GET_PAD52_PE (((REG32(ADR_PAD52)) & 0x00000002 ) >> 1)
++#define GET_PAD52_DS (((REG32(ADR_PAD52)) & 0x00000004 ) >> 2)
++#define GET_PAD52_SEL_I (((REG32(ADR_PAD52)) & 0x00000030 ) >> 4)
++#define GET_PAD52_OD (((REG32(ADR_PAD52)) & 0x00000100 ) >> 8)
++#define GET_PAD52_SEL_O (((REG32(ADR_PAD52)) & 0x00001000 ) >> 12)
++#define GET_PAD52_SEL_OE (((REG32(ADR_PAD52)) & 0x00100000 ) >> 20)
++#define GET_GPIO_14_ID (((REG32(ADR_PAD52)) & 0x10000000 ) >> 28)
++#define GET_PAD53_OE (((REG32(ADR_PAD53)) & 0x00000001 ) >> 0)
++#define GET_PAD53_PE (((REG32(ADR_PAD53)) & 0x00000002 ) >> 1)
++#define GET_PAD53_DS (((REG32(ADR_PAD53)) & 0x00000004 ) >> 2)
++#define GET_PAD53_IE (((REG32(ADR_PAD53)) & 0x00000008 ) >> 3)
++#define GET_PAD53_SEL_I (((REG32(ADR_PAD53)) & 0x00000030 ) >> 4)
++#define GET_PAD53_OD (((REG32(ADR_PAD53)) & 0x00000100 ) >> 8)
++#define GET_PAD53_SEL_O (((REG32(ADR_PAD53)) & 0x00001000 ) >> 12)
++#define GET_JTAG_TMS_ID (((REG32(ADR_PAD53)) & 0x10000000 ) >> 28)
++#define GET_PAD54_OE (((REG32(ADR_PAD54)) & 0x00000001 ) >> 0)
++#define GET_PAD54_PE (((REG32(ADR_PAD54)) & 0x00000002 ) >> 1)
++#define GET_PAD54_DS (((REG32(ADR_PAD54)) & 0x00000004 ) >> 2)
++#define GET_PAD54_OD (((REG32(ADR_PAD54)) & 0x00000100 ) >> 8)
++#define GET_PAD54_SEL_O (((REG32(ADR_PAD54)) & 0x00003000 ) >> 12)
++#define GET_JTAG_TCK_ID (((REG32(ADR_PAD54)) & 0x10000000 ) >> 28)
++#define GET_PAD56_PE (((REG32(ADR_PAD56)) & 0x00000002 ) >> 1)
++#define GET_PAD56_DS (((REG32(ADR_PAD56)) & 0x00000004 ) >> 2)
++#define GET_PAD56_SEL_I (((REG32(ADR_PAD56)) & 0x00000010 ) >> 4)
++#define GET_PAD56_OD (((REG32(ADR_PAD56)) & 0x00000100 ) >> 8)
++#define GET_JTAG_TDI_ID (((REG32(ADR_PAD56)) & 0x10000000 ) >> 28)
++#define GET_PAD57_OE (((REG32(ADR_PAD57)) & 0x00000001 ) >> 0)
++#define GET_PAD57_PE (((REG32(ADR_PAD57)) & 0x00000002 ) >> 1)
++#define GET_PAD57_DS (((REG32(ADR_PAD57)) & 0x00000004 ) >> 2)
++#define GET_PAD57_IE (((REG32(ADR_PAD57)) & 0x00000008 ) >> 3)
++#define GET_PAD57_SEL_I (((REG32(ADR_PAD57)) & 0x00000030 ) >> 4)
++#define GET_PAD57_OD (((REG32(ADR_PAD57)) & 0x00000100 ) >> 8)
++#define GET_PAD57_SEL_O (((REG32(ADR_PAD57)) & 0x00003000 ) >> 12)
++#define GET_PAD57_SEL_OE (((REG32(ADR_PAD57)) & 0x00100000 ) >> 20)
++#define GET_JTAG_TDO_ID (((REG32(ADR_PAD57)) & 0x10000000 ) >> 28)
++#define GET_PAD58_OE (((REG32(ADR_PAD58)) & 0x00000001 ) >> 0)
++#define GET_PAD58_PE (((REG32(ADR_PAD58)) & 0x00000002 ) >> 1)
++#define GET_PAD58_DS (((REG32(ADR_PAD58)) & 0x00000004 ) >> 2)
++#define GET_PAD58_IE (((REG32(ADR_PAD58)) & 0x00000008 ) >> 3)
++#define GET_PAD58_SEL_I (((REG32(ADR_PAD58)) & 0x00000030 ) >> 4)
++#define GET_PAD58_OD (((REG32(ADR_PAD58)) & 0x00000100 ) >> 8)
++#define GET_PAD58_SEL_O (((REG32(ADR_PAD58)) & 0x00001000 ) >> 12)
++#define GET_TEST_16_ID (((REG32(ADR_PAD58)) & 0x10000000 ) >> 28)
++#define GET_PAD59_OE (((REG32(ADR_PAD59)) & 0x00000001 ) >> 0)
++#define GET_PAD59_PE (((REG32(ADR_PAD59)) & 0x00000002 ) >> 1)
++#define GET_PAD59_DS (((REG32(ADR_PAD59)) & 0x00000004 ) >> 2)
++#define GET_PAD59_IE (((REG32(ADR_PAD59)) & 0x00000008 ) >> 3)
++#define GET_PAD59_SEL_I (((REG32(ADR_PAD59)) & 0x00000030 ) >> 4)
++#define GET_PAD59_OD (((REG32(ADR_PAD59)) & 0x00000100 ) >> 8)
++#define GET_PAD59_SEL_O (((REG32(ADR_PAD59)) & 0x00001000 ) >> 12)
++#define GET_TEST_17_ID (((REG32(ADR_PAD59)) & 0x10000000 ) >> 28)
++#define GET_PAD60_OE (((REG32(ADR_PAD60)) & 0x00000001 ) >> 0)
++#define GET_PAD60_PE (((REG32(ADR_PAD60)) & 0x00000002 ) >> 1)
++#define GET_PAD60_DS (((REG32(ADR_PAD60)) & 0x00000004 ) >> 2)
++#define GET_PAD60_IE (((REG32(ADR_PAD60)) & 0x00000008 ) >> 3)
++#define GET_PAD60_SEL_I (((REG32(ADR_PAD60)) & 0x00000030 ) >> 4)
++#define GET_PAD60_OD (((REG32(ADR_PAD60)) & 0x00000100 ) >> 8)
++#define GET_PAD60_SEL_O (((REG32(ADR_PAD60)) & 0x00001000 ) >> 12)
++#define GET_TEST_18_ID (((REG32(ADR_PAD60)) & 0x10000000 ) >> 28)
++#define GET_PAD61_OE (((REG32(ADR_PAD61)) & 0x00000001 ) >> 0)
++#define GET_PAD61_PE (((REG32(ADR_PAD61)) & 0x00000002 ) >> 1)
++#define GET_PAD61_DS (((REG32(ADR_PAD61)) & 0x00000004 ) >> 2)
++#define GET_PAD61_IE (((REG32(ADR_PAD61)) & 0x00000008 ) >> 3)
++#define GET_PAD61_SEL_I (((REG32(ADR_PAD61)) & 0x00000010 ) >> 4)
++#define GET_PAD61_OD (((REG32(ADR_PAD61)) & 0x00000100 ) >> 8)
++#define GET_PAD61_SEL_O (((REG32(ADR_PAD61)) & 0x00003000 ) >> 12)
++#define GET_TEST_19_ID (((REG32(ADR_PAD61)) & 0x10000000 ) >> 28)
++#define GET_PAD62_OE (((REG32(ADR_PAD62)) & 0x00000001 ) >> 0)
++#define GET_PAD62_PE (((REG32(ADR_PAD62)) & 0x00000002 ) >> 1)
++#define GET_PAD62_DS (((REG32(ADR_PAD62)) & 0x00000004 ) >> 2)
++#define GET_PAD62_IE (((REG32(ADR_PAD62)) & 0x00000008 ) >> 3)
++#define GET_PAD62_SEL_I (((REG32(ADR_PAD62)) & 0x00000010 ) >> 4)
++#define GET_PAD62_OD (((REG32(ADR_PAD62)) & 0x00000100 ) >> 8)
++#define GET_PAD62_SEL_O (((REG32(ADR_PAD62)) & 0x00001000 ) >> 12)
++#define GET_TEST_20_ID (((REG32(ADR_PAD62)) & 0x10000000 ) >> 28)
++#define GET_PAD64_OE (((REG32(ADR_PAD64)) & 0x00000001 ) >> 0)
++#define GET_PAD64_PE (((REG32(ADR_PAD64)) & 0x00000002 ) >> 1)
++#define GET_PAD64_DS (((REG32(ADR_PAD64)) & 0x00000004 ) >> 2)
++#define GET_PAD64_IE (((REG32(ADR_PAD64)) & 0x00000008 ) >> 3)
++#define GET_PAD64_SEL_I (((REG32(ADR_PAD64)) & 0x00000070 ) >> 4)
++#define GET_PAD64_OD (((REG32(ADR_PAD64)) & 0x00000100 ) >> 8)
++#define GET_PAD64_SEL_O (((REG32(ADR_PAD64)) & 0x00003000 ) >> 12)
++#define GET_PAD64_SEL_OE (((REG32(ADR_PAD64)) & 0x00100000 ) >> 20)
++#define GET_GPIO_15_IP_ID (((REG32(ADR_PAD64)) & 0x10000000 ) >> 28)
++#define GET_PAD65_OE (((REG32(ADR_PAD65)) & 0x00000001 ) >> 0)
++#define GET_PAD65_PE (((REG32(ADR_PAD65)) & 0x00000002 ) >> 1)
++#define GET_PAD65_DS (((REG32(ADR_PAD65)) & 0x00000004 ) >> 2)
++#define GET_PAD65_IE (((REG32(ADR_PAD65)) & 0x00000008 ) >> 3)
++#define GET_PAD65_SEL_I (((REG32(ADR_PAD65)) & 0x00000070 ) >> 4)
++#define GET_PAD65_OD (((REG32(ADR_PAD65)) & 0x00000100 ) >> 8)
++#define GET_PAD65_SEL_O (((REG32(ADR_PAD65)) & 0x00001000 ) >> 12)
++#define GET_GPIO_TEST_7_IN_ID (((REG32(ADR_PAD65)) & 0x10000000 ) >> 28)
++#define GET_PAD66_OE (((REG32(ADR_PAD66)) & 0x00000001 ) >> 0)
++#define GET_PAD66_PE (((REG32(ADR_PAD66)) & 0x00000002 ) >> 1)
++#define GET_PAD66_DS (((REG32(ADR_PAD66)) & 0x00000004 ) >> 2)
++#define GET_PAD66_IE (((REG32(ADR_PAD66)) & 0x00000008 ) >> 3)
++#define GET_PAD66_SEL_I (((REG32(ADR_PAD66)) & 0x00000030 ) >> 4)
++#define GET_PAD66_OD (((REG32(ADR_PAD66)) & 0x00000100 ) >> 8)
++#define GET_PAD66_SEL_O (((REG32(ADR_PAD66)) & 0x00003000 ) >> 12)
++#define GET_GPIO_17_QP_ID (((REG32(ADR_PAD66)) & 0x10000000 ) >> 28)
++#define GET_PAD68_OE (((REG32(ADR_PAD68)) & 0x00000001 ) >> 0)
++#define GET_PAD68_PE (((REG32(ADR_PAD68)) & 0x00000002 ) >> 1)
++#define GET_PAD68_DS (((REG32(ADR_PAD68)) & 0x00000004 ) >> 2)
++#define GET_PAD68_IE (((REG32(ADR_PAD68)) & 0x00000008 ) >> 3)
++#define GET_PAD68_OD (((REG32(ADR_PAD68)) & 0x00000100 ) >> 8)
++#define GET_PAD68_SEL_O (((REG32(ADR_PAD68)) & 0x00001000 ) >> 12)
++#define GET_GPIO_19_ID (((REG32(ADR_PAD68)) & 0x10000000 ) >> 28)
++#define GET_PAD67_OE (((REG32(ADR_PAD67)) & 0x00000001 ) >> 0)
++#define GET_PAD67_PE (((REG32(ADR_PAD67)) & 0x00000002 ) >> 1)
++#define GET_PAD67_DS (((REG32(ADR_PAD67)) & 0x00000004 ) >> 2)
++#define GET_PAD67_IE (((REG32(ADR_PAD67)) & 0x00000008 ) >> 3)
++#define GET_PAD67_SEL_I (((REG32(ADR_PAD67)) & 0x00000070 ) >> 4)
++#define GET_PAD67_OD (((REG32(ADR_PAD67)) & 0x00000100 ) >> 8)
++#define GET_PAD67_SEL_O (((REG32(ADR_PAD67)) & 0x00003000 ) >> 12)
++#define GET_GPIO_TEST_8_QN_ID (((REG32(ADR_PAD67)) & 0x10000000 ) >> 28)
++#define GET_PAD69_OE (((REG32(ADR_PAD69)) & 0x00000001 ) >> 0)
++#define GET_PAD69_PE (((REG32(ADR_PAD69)) & 0x00000002 ) >> 1)
++#define GET_PAD69_DS (((REG32(ADR_PAD69)) & 0x00000004 ) >> 2)
++#define GET_PAD69_IE (((REG32(ADR_PAD69)) & 0x00000008 ) >> 3)
++#define GET_PAD69_SEL_I (((REG32(ADR_PAD69)) & 0x00000030 ) >> 4)
++#define GET_PAD69_OD (((REG32(ADR_PAD69)) & 0x00000100 ) >> 8)
++#define GET_PAD69_SEL_O (((REG32(ADR_PAD69)) & 0x00001000 ) >> 12)
++#define GET_STRAP2 (((REG32(ADR_PAD69)) & 0x08000000 ) >> 27)
++#define GET_GPIO_20_ID (((REG32(ADR_PAD69)) & 0x10000000 ) >> 28)
++#define GET_PAD70_OE (((REG32(ADR_PAD70)) & 0x00000001 ) >> 0)
++#define GET_PAD70_PE (((REG32(ADR_PAD70)) & 0x00000002 ) >> 1)
++#define GET_PAD70_DS (((REG32(ADR_PAD70)) & 0x00000004 ) >> 2)
++#define GET_PAD70_IE (((REG32(ADR_PAD70)) & 0x00000008 ) >> 3)
++#define GET_PAD70_SEL_I (((REG32(ADR_PAD70)) & 0x00000030 ) >> 4)
++#define GET_PAD70_OD (((REG32(ADR_PAD70)) & 0x00000100 ) >> 8)
++#define GET_PAD70_SEL_O (((REG32(ADR_PAD70)) & 0x00007000 ) >> 12)
++#define GET_GPIO_21_ID (((REG32(ADR_PAD70)) & 0x10000000 ) >> 28)
++#define GET_PAD231_OE (((REG32(ADR_PAD231)) & 0x00000001 ) >> 0)
++#define GET_PAD231_PE (((REG32(ADR_PAD231)) & 0x00000002 ) >> 1)
++#define GET_PAD231_DS (((REG32(ADR_PAD231)) & 0x00000004 ) >> 2)
++#define GET_PAD231_IE (((REG32(ADR_PAD231)) & 0x00000008 ) >> 3)
++#define GET_PAD231_OD (((REG32(ADR_PAD231)) & 0x00000100 ) >> 8)
++#define GET_PIN_40_OR_56_ID (((REG32(ADR_PAD231)) & 0x10000000 ) >> 28)
++#define GET_MP_PHY2RX_DATA__0_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000001 ) >> 0)
++#define GET_MP_PHY2RX_DATA__1_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000002 ) >> 1)
++#define GET_MP_TX_FF_RPTR__1_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000004 ) >> 2)
++#define GET_MP_RX_FF_WPTR__2_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000008 ) >> 3)
++#define GET_MP_RX_FF_WPTR__1_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000010 ) >> 4)
++#define GET_MP_RX_FF_WPTR__0_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000020 ) >> 5)
++#define GET_MP_PHY2RX_DATA__2_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000040 ) >> 6)
++#define GET_MP_PHY2RX_DATA__4_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000080 ) >> 7)
++#define GET_I2CM_SDA_ID_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000300 ) >> 8)
++#define GET_CRYSTAL_OUT_REQ_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000400 ) >> 10)
++#define GET_MP_PHY2RX_DATA__5_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000800 ) >> 11)
++#define GET_MP_PHY2RX_DATA__3_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00001000 ) >> 12)
++#define GET_UART_RXD_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00006000 ) >> 13)
++#define GET_MP_PHY2RX_DATA__6_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00008000 ) >> 15)
++#define GET_DAT_UART_NCTS_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00010000 ) >> 16)
++#define GET_GPIO_LOG_STOP_SEL (((REG32(ADR_PIN_SEL_0)) & 0x000e0000 ) >> 17)
++#define GET_MP_TX_FF_RPTR__0_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00100000 ) >> 20)
++#define GET_MP_PHY_RX_WRST_N_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00200000 ) >> 21)
++#define GET_EXT_32K_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00c00000 ) >> 22)
++#define GET_MP_PHY2RX_DATA__7_SEL (((REG32(ADR_PIN_SEL_0)) & 0x01000000 ) >> 24)
++#define GET_MP_TX_FF_RPTR__2_SEL (((REG32(ADR_PIN_SEL_0)) & 0x02000000 ) >> 25)
++#define GET_PMUINT_WAKE_SEL (((REG32(ADR_PIN_SEL_0)) & 0x1c000000 ) >> 26)
++#define GET_I2CM_SCL_ID_SEL (((REG32(ADR_PIN_SEL_0)) & 0x20000000 ) >> 29)
++#define GET_MP_MRX_RX_EN_SEL (((REG32(ADR_PIN_SEL_0)) & 0x40000000 ) >> 30)
++#define GET_DAT_UART_RXD_SEL_0 (((REG32(ADR_PIN_SEL_0)) & 0x80000000 ) >> 31)
++#define GET_DAT_UART_RXD_SEL_1 (((REG32(ADR_PIN_SEL_1)) & 0x00000001 ) >> 0)
++#define GET_SPI_DI_SEL (((REG32(ADR_PIN_SEL_1)) & 0x00000002 ) >> 1)
++#define GET_IO_PORT_REG (((REG32(ADR_IO_PORT_REG)) & 0x0001ffff ) >> 0)
++#define GET_MASK_RX_INT (((REG32(ADR_INT_MASK_REG)) & 0x00000001 ) >> 0)
++#define GET_MASK_TX_INT (((REG32(ADR_INT_MASK_REG)) & 0x00000002 ) >> 1)
++#define GET_MASK_SOC_SYSTEM_INT (((REG32(ADR_INT_MASK_REG)) & 0x00000004 ) >> 2)
++#define GET_EDCA0_LOW_THR_INT_MASK (((REG32(ADR_INT_MASK_REG)) & 0x00000008 ) >> 3)
++#define GET_EDCA1_LOW_THR_INT_MASK (((REG32(ADR_INT_MASK_REG)) & 0x00000010 ) >> 4)
++#define GET_EDCA2_LOW_THR_INT_MASK (((REG32(ADR_INT_MASK_REG)) & 0x00000020 ) >> 5)
++#define GET_EDCA3_LOW_THR_INT_MASK (((REG32(ADR_INT_MASK_REG)) & 0x00000040 ) >> 6)
++#define GET_TX_LIMIT_INT_MASK (((REG32(ADR_INT_MASK_REG)) & 0x00000080 ) >> 7)
++#define GET_RX_INT (((REG32(ADR_INT_STATUS_REG)) & 0x00000001 ) >> 0)
++#define GET_TX_COMPLETE_INT (((REG32(ADR_INT_STATUS_REG)) & 0x00000002 ) >> 1)
++#define GET_SOC_SYSTEM_INT_STATUS (((REG32(ADR_INT_STATUS_REG)) & 0x00000004 ) >> 2)
++#define GET_EDCA0_LOW_THR_INT_STS (((REG32(ADR_INT_STATUS_REG)) & 0x00000008 ) >> 3)
++#define GET_EDCA1_LOW_THR_INT_STS (((REG32(ADR_INT_STATUS_REG)) & 0x00000010 ) >> 4)
++#define GET_EDCA2_LOW_THR_INT_STS (((REG32(ADR_INT_STATUS_REG)) & 0x00000020 ) >> 5)
++#define GET_EDCA3_LOW_THR_INT_STS (((REG32(ADR_INT_STATUS_REG)) & 0x00000040 ) >> 6)
++#define GET_TX_LIMIT_INT_STS (((REG32(ADR_INT_STATUS_REG)) & 0x00000080 ) >> 7)
++#define GET_HOST_TRIGGERED_RX_INT (((REG32(ADR_INT_STATUS_REG)) & 0x00000100 ) >> 8)
++#define GET_HOST_TRIGGERED_TX_INT (((REG32(ADR_INT_STATUS_REG)) & 0x00000200 ) >> 9)
++#define GET_SOC_TRIGGER_RX_INT (((REG32(ADR_INT_STATUS_REG)) & 0x00000400 ) >> 10)
++#define GET_SOC_TRIGGER_TX_INT (((REG32(ADR_INT_STATUS_REG)) & 0x00000800 ) >> 11)
++#define GET_RDY_FOR_TX_RX (((REG32(ADR_FN1_STATUS_REG)) & 0x00000001 ) >> 0)
++#define GET_RDY_FOR_FW_DOWNLOAD (((REG32(ADR_FN1_STATUS_REG)) & 0x00000002 ) >> 1)
++#define GET_ILLEGAL_CMD_RESP_OPTION (((REG32(ADR_FN1_STATUS_REG)) & 0x00000004 ) >> 2)
++#define GET_SDIO_TRX_DATA_SEQUENCE (((REG32(ADR_FN1_STATUS_REG)) & 0x00000008 ) >> 3)
++#define GET_GPIO_INT_TRIGGER_OPTION (((REG32(ADR_FN1_STATUS_REG)) & 0x00000010 ) >> 4)
++#define GET_TRIGGER_FUNCTION_SETTING (((REG32(ADR_FN1_STATUS_REG)) & 0x00000060 ) >> 5)
++#define GET_CMD52_ABORT_RESPONSE (((REG32(ADR_FN1_STATUS_REG)) & 0x00000080 ) >> 7)
++#define GET_RX_PACKET_LENGTH (((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0x0000ffff ) >> 0)
++#define GET_CARD_FW_DL_STATUS (((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0x00ff0000 ) >> 16)
++#define GET_TX_RX_LOOP_BACK_TEST (((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0x01000000 ) >> 24)
++#define GET_SDIO_LOOP_BACK_TEST (((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0x02000000 ) >> 25)
++#define GET_CMD52_ABORT_ACTIVE (((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0x10000000 ) >> 28)
++#define GET_CMD52_RESET_ACTIVE (((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0x20000000 ) >> 29)
++#define GET_SDIO_PARTIAL_RESET_ACTIVE (((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0x40000000 ) >> 30)
++#define GET_SDIO_ALL_RESE_ACTIVE (((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0x80000000 ) >> 31)
++#define GET_RX_PACKET_LENGTH2 (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x0000ffff ) >> 0)
++#define GET_RX_INT1 (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x00010000 ) >> 16)
++#define GET_TX_DONE (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x00020000 ) >> 17)
++#define GET_HCI_TRX_FINISH (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x00040000 ) >> 18)
++#define GET_ALLOCATE_STATUS (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x00080000 ) >> 19)
++#define GET_HCI_INPUT_FF_CNT (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x00f00000 ) >> 20)
++#define GET_HCI_OUTPUT_FF_CNT (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x1f000000 ) >> 24)
++#define GET_AHB_HANG4 (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x20000000 ) >> 29)
++#define GET_HCI_IN_QUE_EMPTY (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x40000000 ) >> 30)
++#define GET_SYSTEM_INT (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x80000000 ) >> 31)
++#define GET_CARD_RCA_REG (((REG32(ADR_CARD_RCA_REG)) & 0x0000ffff ) >> 0)
++#define GET_SDIO_FIFO_WR_THLD_REG (((REG32(ADR_SDIO_FIFO_WR_THLD_REG)) & 0x000001ff ) >> 0)
++#define GET_SDIO_FIFO_WR_LIMIT_REG (((REG32(ADR_SDIO_FIFO_WR_LIMIT_REG)) & 0x000001ff ) >> 0)
++#define GET_SDIO_TX_DATA_BATCH_SIZE_REG (((REG32(ADR_SDIO_TX_DATA_BATCH_SIZE_REG)) & 0x000001ff ) >> 0)
++#define GET_SDIO_THLD_FOR_CMD53RD_REG (((REG32(ADR_SDIO_THLD_FOR_CMD53RD_REG)) & 0x000001ff ) >> 0)
++#define GET_SDIO_RX_DATA_BATCH_SIZE_REG (((REG32(ADR_SDIO_RX_DATA_BATCH_SIZE_REG)) & 0x000001ff ) >> 0)
++#define GET_START_BYTE_VALUE (((REG32(ADR_SDIO_LOG_START_END_DATA_REG)) & 0x000000ff ) >> 0)
++#define GET_END_BYTE_VALUE (((REG32(ADR_SDIO_LOG_START_END_DATA_REG)) & 0x0000ff00 ) >> 8)
++#define GET_SDIO_BYTE_MODE_BATCH_SIZE_REG (((REG32(ADR_SDIO_BYTE_MODE_BATCH_SIZE_REG)) & 0x000000ff ) >> 0)
++#define GET_SDIO_LAST_CMD_INDEX_REG (((REG32(ADR_SDIO_LAST_CMD_INDEX_CRC_REG)) & 0x0000003f ) >> 0)
++#define GET_SDIO_LAST_CMD_CRC_REG (((REG32(ADR_SDIO_LAST_CMD_INDEX_CRC_REG)) & 0x00007f00 ) >> 8)
++#define GET_SDIO_LAST_CMD_ARG_REG (((REG32(ADR_SDIO_LAST_CMD_ARG_REG)) & 0xffffffff ) >> 0)
++#define GET_SDIO_BUS_STATE_REG (((REG32(ADR_SDIO_BUS_STATE_DEBUG_MONITOR)) & 0x0000001f ) >> 0)
++#define GET_SDIO_BUSY_LONG_CNT (((REG32(ADR_SDIO_BUS_STATE_DEBUG_MONITOR)) & 0xffff0000 ) >> 16)
++#define GET_SDIO_CARD_STATUS_REG (((REG32(ADR_SDIO_CARD_STATUS_REG)) & 0xffffffff ) >> 0)
++#define GET_R5_RESPONSE_FLAG (((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0x000000ff ) >> 0)
++#define GET_RESP_OUT_EDGE (((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0x00000100 ) >> 8)
++#define GET_DAT_OUT_EDGE (((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0x00000200 ) >> 9)
++#define GET_MCU_TO_SDIO_INFO_MASK (((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0x00010000 ) >> 16)
++#define GET_INT_THROUGH_PIN (((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0x00020000 ) >> 17)
++#define GET_WRITE_DATA (((REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) & 0x000000ff ) >> 0)
++#define GET_WRITE_ADDRESS (((REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) & 0x0000ff00 ) >> 8)
++#define GET_READ_DATA (((REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) & 0x00ff0000 ) >> 16)
++#define GET_READ_ADDRESS (((REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) & 0xff000000 ) >> 24)
++#define GET_FN1_DMA_START_ADDR_REG (((REG32(ADR_FN1_DMA_START_ADDR_REG)) & 0xffffffff ) >> 0)
++#define GET_SDIO_TO_MCU_INFO (((REG32(ADR_FN1_INT_CTRL_RESET)) & 0x000000ff ) >> 0)
++#define GET_SDIO_PARTIAL_RESET (((REG32(ADR_FN1_INT_CTRL_RESET)) & 0x00000100 ) >> 8)
++#define GET_SDIO_ALL_RESET (((REG32(ADR_FN1_INT_CTRL_RESET)) & 0x00000200 ) >> 9)
++#define GET_PERI_MAC_ALL_RESET (((REG32(ADR_FN1_INT_CTRL_RESET)) & 0x00000400 ) >> 10)
++#define GET_MAC_ALL_RESET (((REG32(ADR_FN1_INT_CTRL_RESET)) & 0x00000800 ) >> 11)
++#define GET_AHB_BRIDGE_RESET (((REG32(ADR_FN1_INT_CTRL_RESET)) & 0x00001000 ) >> 12)
++#define GET_IO_REG_PORT_REG (((REG32(ADR_IO_REG_PORT_REG)) & 0x0001ffff ) >> 0)
++#define GET_SDIO_FIFO_EMPTY_CNT (((REG32(ADR_SDIO_FIFO_ERROR_CNT)) & 0x0000ffff ) >> 0)
++#define GET_SDIO_FIFO_FULL_CNT (((REG32(ADR_SDIO_FIFO_ERROR_CNT)) & 0xffff0000 ) >> 16)
++#define GET_SDIO_CRC7_ERROR_CNT (((REG32(ADR_SDIO_CRC7_CRC16_ERROR_REG)) & 0x0000ffff ) >> 0)
++#define GET_SDIO_CRC16_ERROR_CNT (((REG32(ADR_SDIO_CRC7_CRC16_ERROR_REG)) & 0xffff0000 ) >> 16)
++#define GET_SDIO_RD_BLOCK_CNT (((REG32(ADR_SDIO_BLOCK_CNT_INFO)) & 0x000001ff ) >> 0)
++#define GET_SDIO_WR_BLOCK_CNT (((REG32(ADR_SDIO_BLOCK_CNT_INFO)) & 0x01ff0000 ) >> 16)
++#define GET_CMD52_RD_ABORT_CNT (((REG32(ADR_RX_DATA_CMD52_ABORT_COUNT)) & 0x000f0000 ) >> 16)
++#define GET_CMD52_WR_ABORT_CNT (((REG32(ADR_RX_DATA_CMD52_ABORT_COUNT)) & 0x00f00000 ) >> 20)
++#define GET_SDIO_FIFO_WR_PTR_REG (((REG32(ADR_FIFO_PTR_READ_BLOCK_CNT)) & 0x000000ff ) >> 0)
++#define GET_SDIO_FIFO_RD_PTR_REG (((REG32(ADR_FIFO_PTR_READ_BLOCK_CNT)) & 0x0000ff00 ) >> 8)
++#define GET_SDIO_READ_DATA_CTRL (((REG32(ADR_TX_TIME_OUT_READ_CTRL)) & 0x00010000 ) >> 16)
++#define GET_TX_SIZE_BEFORE_SHIFT (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x000000ff ) >> 0)
++#define GET_TX_SIZE_SHIFT_BITS (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00000700 ) >> 8)
++#define GET_SDIO_TX_ALLOC_STATE (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00001000 ) >> 12)
++#define GET_ALLOCATE_STATUS2 (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00010000 ) >> 16)
++#define GET_NO_ALLOCATE_SEND_ERROR (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00020000 ) >> 17)
++#define GET_DOUBLE_ALLOCATE_ERROR (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00040000 ) >> 18)
++#define GET_TX_DONE_STATUS (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00080000 ) >> 19)
++#define GET_AHB_HANG2 (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00100000 ) >> 20)
++#define GET_HCI_TRX_FINISH2 (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00200000 ) >> 21)
++#define GET_INTR_RX (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00400000 ) >> 22)
++#define GET_HCI_INPUT_QUEUE_FULL (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00800000 ) >> 23)
++#define GET_ALLOCATESTATUS (((REG32(ADR_SDIO_TX_INFORM)) & 0x00000001 ) >> 0)
++#define GET_HCI_TRX_FINISH3 (((REG32(ADR_SDIO_TX_INFORM)) & 0x00000002 ) >> 1)
++#define GET_HCI_IN_QUE_EMPTY2 (((REG32(ADR_SDIO_TX_INFORM)) & 0x00000004 ) >> 2)
++#define GET_MTX_MNG_UPTHOLD_INT (((REG32(ADR_SDIO_TX_INFORM)) & 0x00000008 ) >> 3)
++#define GET_EDCA0_UPTHOLD_INT (((REG32(ADR_SDIO_TX_INFORM)) & 0x00000010 ) >> 4)
++#define GET_EDCA1_UPTHOLD_INT (((REG32(ADR_SDIO_TX_INFORM)) & 0x00000020 ) >> 5)
++#define GET_EDCA2_UPTHOLD_INT (((REG32(ADR_SDIO_TX_INFORM)) & 0x00000040 ) >> 6)
++#define GET_EDCA3_UPTHOLD_INT (((REG32(ADR_SDIO_TX_INFORM)) & 0x00000080 ) >> 7)
++#define GET_TX_PAGE_REMAIN2 (((REG32(ADR_SDIO_TX_INFORM)) & 0x0000ff00 ) >> 8)
++#define GET_TX_ID_REMAIN3 (((REG32(ADR_SDIO_TX_INFORM)) & 0x007f0000 ) >> 16)
++#define GET_HCI_OUTPUT_FF_CNT_0 (((REG32(ADR_SDIO_TX_INFORM)) & 0x00800000 ) >> 23)
++#define GET_HCI_OUTPUT_FF_CNT2 (((REG32(ADR_SDIO_TX_INFORM)) & 0x0f000000 ) >> 24)
++#define GET_HCI_INPUT_FF_CNT2 (((REG32(ADR_SDIO_TX_INFORM)) & 0xf0000000 ) >> 28)
++#define GET_F1_BLOCK_SIZE_0_REG (((REG32(ADR_F1_BLOCK_SIZE_0_REG)) & 0x00000fff ) >> 0)
++#define GET_START_BYTE_VALUE2 (((REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) & 0x000000ff ) >> 0)
++#define GET_COMMAND_COUNTER (((REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) & 0x0000ff00 ) >> 8)
++#define GET_CMD_LOG_PART1 (((REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) & 0xffff0000 ) >> 16)
++#define GET_CMD_LOG_PART2 (((REG32(ADR_SDIO_COMMAND_LOG_DATA_63_32)) & 0x00ffffff ) >> 0)
++#define GET_END_BYTE_VALUE2 (((REG32(ADR_SDIO_COMMAND_LOG_DATA_63_32)) & 0xff000000 ) >> 24)
++#define GET_RX_PACKET_LENGTH3 (((REG32(ADR_SYSTEM_INFORMATION_REGISTER)) & 0x0000ffff ) >> 0)
++#define GET_RX_INT3 (((REG32(ADR_SYSTEM_INFORMATION_REGISTER)) & 0x00010000 ) >> 16)
++#define GET_TX_ID_REMAIN2 (((REG32(ADR_SYSTEM_INFORMATION_REGISTER)) & 0x00fe0000 ) >> 17)
++#define GET_TX_PAGE_REMAIN3 (((REG32(ADR_SYSTEM_INFORMATION_REGISTER)) & 0xff000000 ) >> 24)
++#define GET_CCCR_00H_REG (((REG32(ADR_CCCR_00H_REG)) & 0x000000ff ) >> 0)
++#define GET_CCCR_02H_REG (((REG32(ADR_CCCR_00H_REG)) & 0x00ff0000 ) >> 16)
++#define GET_CCCR_03H_REG (((REG32(ADR_CCCR_00H_REG)) & 0xff000000 ) >> 24)
++#define GET_CCCR_04H_REG (((REG32(ADR_CCCR_04H_REG)) & 0x000000ff ) >> 0)
++#define GET_CCCR_05H_REG (((REG32(ADR_CCCR_04H_REG)) & 0x0000ff00 ) >> 8)
++#define GET_CCCR_06H_REG (((REG32(ADR_CCCR_04H_REG)) & 0x000f0000 ) >> 16)
++#define GET_CCCR_07H_REG (((REG32(ADR_CCCR_04H_REG)) & 0xff000000 ) >> 24)
++#define GET_SUPPORT_DIRECT_COMMAND_SDIO (((REG32(ADR_CCCR_08H_REG)) & 0x00000001 ) >> 0)
++#define GET_SUPPORT_MULTIPLE_BLOCK_TRANSFER (((REG32(ADR_CCCR_08H_REG)) & 0x00000002 ) >> 1)
++#define GET_SUPPORT_READ_WAIT (((REG32(ADR_CCCR_08H_REG)) & 0x00000004 ) >> 2)
++#define GET_SUPPORT_BUS_CONTROL (((REG32(ADR_CCCR_08H_REG)) & 0x00000008 ) >> 3)
++#define GET_SUPPORT_BLOCK_GAP_INTERRUPT (((REG32(ADR_CCCR_08H_REG)) & 0x00000010 ) >> 4)
++#define GET_ENABLE_BLOCK_GAP_INTERRUPT (((REG32(ADR_CCCR_08H_REG)) & 0x00000020 ) >> 5)
++#define GET_LOW_SPEED_CARD (((REG32(ADR_CCCR_08H_REG)) & 0x00000040 ) >> 6)
++#define GET_LOW_SPEED_CARD_4BIT (((REG32(ADR_CCCR_08H_REG)) & 0x00000080 ) >> 7)
++#define GET_COMMON_CIS_PONTER (((REG32(ADR_CCCR_08H_REG)) & 0x01ffff00 ) >> 8)
++#define GET_SUPPORT_HIGH_SPEED (((REG32(ADR_CCCR_13H_REG)) & 0x01000000 ) >> 24)
++#define GET_BSS (((REG32(ADR_CCCR_13H_REG)) & 0x0e000000 ) >> 25)
++#define GET_FBR_100H_REG (((REG32(ADR_FBR_100H_REG)) & 0x0000000f ) >> 0)
++#define GET_CSASUPPORT (((REG32(ADR_FBR_100H_REG)) & 0x00000040 ) >> 6)
++#define GET_ENABLECSA (((REG32(ADR_FBR_100H_REG)) & 0x00000080 ) >> 7)
++#define GET_FBR_101H_REG (((REG32(ADR_FBR_100H_REG)) & 0x0000ff00 ) >> 8)
++#define GET_FBR_109H_REG (((REG32(ADR_FBR_109H_REG)) & 0x01ffff00 ) >> 8)
++#define GET_F0_CIS_CONTENT_REG_31_0 (((REG32(ADR_F0_CIS_CONTENT_REG_0)) & 0xffffffff ) >> 0)
++#define GET_F0_CIS_CONTENT_REG_63_32 (((REG32(ADR_F0_CIS_CONTENT_REG_1)) & 0xffffffff ) >> 0)
++#define GET_F0_CIS_CONTENT_REG_95_64 (((REG32(ADR_F0_CIS_CONTENT_REG_2)) & 0xffffffff ) >> 0)
++#define GET_F0_CIS_CONTENT_REG_127_96 (((REG32(ADR_F0_CIS_CONTENT_REG_3)) & 0xffffffff ) >> 0)
++#define GET_F0_CIS_CONTENT_REG_159_128 (((REG32(ADR_F0_CIS_CONTENT_REG_4)) & 0xffffffff ) >> 0)
++#define GET_F0_CIS_CONTENT_REG_191_160 (((REG32(ADR_F0_CIS_CONTENT_REG_5)) & 0xffffffff ) >> 0)
++#define GET_F0_CIS_CONTENT_REG_223_192 (((REG32(ADR_F0_CIS_CONTENT_REG_6)) & 0xffffffff ) >> 0)
++#define GET_F0_CIS_CONTENT_REG_255_224 (((REG32(ADR_F0_CIS_CONTENT_REG_7)) & 0xffffffff ) >> 0)
++#define GET_F0_CIS_CONTENT_REG_287_256 (((REG32(ADR_F0_CIS_CONTENT_REG_8)) & 0xffffffff ) >> 0)
++#define GET_F0_CIS_CONTENT_REG_319_288 (((REG32(ADR_F0_CIS_CONTENT_REG_9)) & 0xffffffff ) >> 0)
++#define GET_F0_CIS_CONTENT_REG_351_320 (((REG32(ADR_F0_CIS_CONTENT_REG_10)) & 0xffffffff ) >> 0)
++#define GET_F0_CIS_CONTENT_REG_383_352 (((REG32(ADR_F0_CIS_CONTENT_REG_11)) & 0xffffffff ) >> 0)
++#define GET_F0_CIS_CONTENT_REG_415_384 (((REG32(ADR_F0_CIS_CONTENT_REG_12)) & 0xffffffff ) >> 0)
++#define GET_F0_CIS_CONTENT_REG_447_416 (((REG32(ADR_F0_CIS_CONTENT_REG_13)) & 0xffffffff ) >> 0)
++#define GET_F0_CIS_CONTENT_REG_479_448 (((REG32(ADR_F0_CIS_CONTENT_REG_14)) & 0xffffffff ) >> 0)
++#define GET_F0_CIS_CONTENT_REG_511_480 (((REG32(ADR_F0_CIS_CONTENT_REG_15)) & 0xffffffff ) >> 0)
++#define GET_F1_CIS_CONTENT_REG_31_0 (((REG32(ADR_F1_CIS_CONTENT_REG_0)) & 0xffffffff ) >> 0)
++#define GET_F1_CIS_CONTENT_REG_63_32 (((REG32(ADR_F1_CIS_CONTENT_REG_1)) & 0xffffffff ) >> 0)
++#define GET_F1_CIS_CONTENT_REG_95_64 (((REG32(ADR_F1_CIS_CONTENT_REG_2)) & 0xffffffff ) >> 0)
++#define GET_F1_CIS_CONTENT_REG_127_96 (((REG32(ADR_F1_CIS_CONTENT_REG_3)) & 0xffffffff ) >> 0)
++#define GET_F1_CIS_CONTENT_REG_159_128 (((REG32(ADR_F1_CIS_CONTENT_REG_4)) & 0xffffffff ) >> 0)
++#define GET_F1_CIS_CONTENT_REG_191_160 (((REG32(ADR_F1_CIS_CONTENT_REG_5)) & 0xffffffff ) >> 0)
++#define GET_F1_CIS_CONTENT_REG_223_192 (((REG32(ADR_F1_CIS_CONTENT_REG_6)) & 0xffffffff ) >> 0)
++#define GET_F1_CIS_CONTENT_REG_255_224 (((REG32(ADR_F1_CIS_CONTENT_REG_7)) & 0xffffffff ) >> 0)
++#define GET_F1_CIS_CONTENT_REG_287_256 (((REG32(ADR_F1_CIS_CONTENT_REG_8)) & 0xffffffff ) >> 0)
++#define GET_F1_CIS_CONTENT_REG_319_288 (((REG32(ADR_F1_CIS_CONTENT_REG_9)) & 0xffffffff ) >> 0)
++#define GET_F1_CIS_CONTENT_REG_351_320 (((REG32(ADR_F1_CIS_CONTENT_REG_10)) & 0xffffffff ) >> 0)
++#define GET_F1_CIS_CONTENT_REG_383_352 (((REG32(ADR_F1_CIS_CONTENT_REG_11)) & 0xffffffff ) >> 0)
++#define GET_F1_CIS_CONTENT_REG_415_384 (((REG32(ADR_F1_CIS_CONTENT_REG_12)) & 0xffffffff ) >> 0)
++#define GET_F1_CIS_CONTENT_REG_447_416 (((REG32(ADR_F1_CIS_CONTENT_REG_13)) & 0xffffffff ) >> 0)
++#define GET_F1_CIS_CONTENT_REG_479_448 (((REG32(ADR_F1_CIS_CONTENT_REG_14)) & 0xffffffff ) >> 0)
++#define GET_F1_CIS_CONTENT_REG_511_480 (((REG32(ADR_F1_CIS_CONTENT_REG_15)) & 0xffffffff ) >> 0)
++#define GET_SPI_MODE (((REG32(ADR_SPI_MODE)) & 0xffffffff ) >> 0)
++#define GET_RX_QUOTA (((REG32(ADR_RX_QUOTA)) & 0x0000ffff ) >> 0)
++#define GET_CONDI_NUM (((REG32(ADR_CONDITION_NUMBER)) & 0x000000ff ) >> 0)
++#define GET_HOST_PATH (((REG32(ADR_HOST_PATH)) & 0x00000001 ) >> 0)
++#define GET_TX_SEG (((REG32(ADR_TX_SEG)) & 0xffffffff ) >> 0)
++#define GET_BRST_MODE (((REG32(ADR_DEBUG_BURST_MODE)) & 0x00000001 ) >> 0)
++#define GET_CLK_WIDTH (((REG32(ADR_SPI_TO_PHY_PARAM1)) & 0x0000ffff ) >> 0)
++#define GET_CSN_INTER (((REG32(ADR_SPI_TO_PHY_PARAM1)) & 0xffff0000 ) >> 16)
++#define GET_BACK_DLY (((REG32(ADR_SPI_TO_PHY_PARAM2)) & 0x0000ffff ) >> 0)
++#define GET_FRONT_DLY (((REG32(ADR_SPI_TO_PHY_PARAM2)) & 0xffff0000 ) >> 16)
++#define GET_RX_FIFO_FAIL (((REG32(ADR_SPI_STS)) & 0x00000002 ) >> 1)
++#define GET_RX_HOST_FAIL (((REG32(ADR_SPI_STS)) & 0x00000004 ) >> 2)
++#define GET_TX_FIFO_FAIL (((REG32(ADR_SPI_STS)) & 0x00000008 ) >> 3)
++#define GET_TX_HOST_FAIL (((REG32(ADR_SPI_STS)) & 0x00000010 ) >> 4)
++#define GET_SPI_DOUBLE_ALLOC (((REG32(ADR_SPI_STS)) & 0x00000020 ) >> 5)
++#define GET_SPI_TX_NO_ALLOC (((REG32(ADR_SPI_STS)) & 0x00000040 ) >> 6)
++#define GET_RDATA_RDY (((REG32(ADR_SPI_STS)) & 0x00000080 ) >> 7)
++#define GET_SPI_ALLOC_STATUS (((REG32(ADR_SPI_STS)) & 0x00000100 ) >> 8)
++#define GET_SPI_DBG_WR_FIFO_FULL (((REG32(ADR_SPI_STS)) & 0x00000200 ) >> 9)
++#define GET_RX_LEN (((REG32(ADR_SPI_STS)) & 0xffff0000 ) >> 16)
++#define GET_SPI_TX_ALLOC_SIZE_SHIFT_BITS (((REG32(ADR_TX_ALLOC_SET)) & 0x00000007 ) >> 0)
++#define GET_SPI_HOST_TX_ALLOC_PKBUF (((REG32(ADR_TX_ALLOC_SET)) & 0x00000100 ) >> 8)
++#define GET_SPI_TX_ALLOC_SIZE (((REG32(ADR_TX_ALLOC)) & 0x000000ff ) >> 0)
++#define GET_RD_DAT_CNT (((REG32(ADR_DBG_CNT)) & 0x0000ffff ) >> 0)
++#define GET_RD_STS_CNT (((REG32(ADR_DBG_CNT)) & 0xffff0000 ) >> 16)
++#define GET_JUDGE_CNT (((REG32(ADR_DBG_CNT2)) & 0x0000ffff ) >> 0)
++#define GET_RD_STS_CNT_CLR (((REG32(ADR_DBG_CNT2)) & 0x00010000 ) >> 16)
++#define GET_RD_DAT_CNT_CLR (((REG32(ADR_DBG_CNT2)) & 0x00020000 ) >> 17)
++#define GET_JUDGE_CNT_CLR (((REG32(ADR_DBG_CNT2)) & 0x00040000 ) >> 18)
++#define GET_TX_DONE_CNT (((REG32(ADR_DBG_CNT3)) & 0x0000ffff ) >> 0)
++#define GET_TX_DISCARD_CNT (((REG32(ADR_DBG_CNT3)) & 0xffff0000 ) >> 16)
++#define GET_TX_SET_CNT (((REG32(ADR_DBG_CNT4)) & 0x0000ffff ) >> 0)
++#define GET_TX_DISCARD_CNT_CLR (((REG32(ADR_DBG_CNT4)) & 0x00010000 ) >> 16)
++#define GET_TX_DONE_CNT_CLR (((REG32(ADR_DBG_CNT4)) & 0x00020000 ) >> 17)
++#define GET_TX_SET_CNT_CLR (((REG32(ADR_DBG_CNT4)) & 0x00040000 ) >> 18)
++#define GET_DAT_MODE_OFF (((REG32(ADR_DBG_CNT4)) & 0x00080000 ) >> 19)
++#define GET_TX_FIFO_RESIDUE (((REG32(ADR_DBG_CNT4)) & 0x00700000 ) >> 20)
++#define GET_RX_FIFO_RESIDUE (((REG32(ADR_DBG_CNT4)) & 0x07000000 ) >> 24)
++#define GET_RX_RDY (((REG32(ADR_INT_TAG)) & 0x00000001 ) >> 0)
++#define GET_SDIO_SYS_INT (((REG32(ADR_INT_TAG)) & 0x00000004 ) >> 2)
++#define GET_EDCA0_LOWTHOLD_INT (((REG32(ADR_INT_TAG)) & 0x00000008 ) >> 3)
++#define GET_EDCA1_LOWTHOLD_INT (((REG32(ADR_INT_TAG)) & 0x00000010 ) >> 4)
++#define GET_EDCA2_LOWTHOLD_INT (((REG32(ADR_INT_TAG)) & 0x00000020 ) >> 5)
++#define GET_EDCA3_LOWTHOLD_INT (((REG32(ADR_INT_TAG)) & 0x00000040 ) >> 6)
++#define GET_TX_LIMIT_INT_IN (((REG32(ADR_INT_TAG)) & 0x00000080 ) >> 7)
++#define GET_SPI_FN1 (((REG32(ADR_INT_TAG)) & 0x00007f00 ) >> 8)
++#define GET_SPI_CLK_EN_INT (((REG32(ADR_INT_TAG)) & 0x00008000 ) >> 15)
++#define GET_SPI_HOST_MASK (((REG32(ADR_INT_TAG)) & 0x00ff0000 ) >> 16)
++#define GET_I2CM_INT_WDONE (((REG32(ADR_I2CM_EN)) & 0x00000001 ) >> 0)
++#define GET_I2CM_INT_RDONE (((REG32(ADR_I2CM_EN)) & 0x00000002 ) >> 1)
++#define GET_I2CM_IDLE (((REG32(ADR_I2CM_EN)) & 0x00000004 ) >> 2)
++#define GET_I2CM_INT_MISMATCH (((REG32(ADR_I2CM_EN)) & 0x00000008 ) >> 3)
++#define GET_I2CM_PSCL (((REG32(ADR_I2CM_EN)) & 0x00003ff0 ) >> 4)
++#define GET_I2CM_MANUAL_MODE (((REG32(ADR_I2CM_EN)) & 0x00010000 ) >> 16)
++#define GET_I2CM_INT_WDATA_NEED (((REG32(ADR_I2CM_EN)) & 0x00020000 ) >> 17)
++#define GET_I2CM_INT_RDATA_NEED (((REG32(ADR_I2CM_EN)) & 0x00040000 ) >> 18)
++#define GET_I2CM_DEV_A (((REG32(ADR_I2CM_DEV_A)) & 0x000003ff ) >> 0)
++#define GET_I2CM_DEV_A10B (((REG32(ADR_I2CM_DEV_A)) & 0x00004000 ) >> 14)
++#define GET_I2CM_RX (((REG32(ADR_I2CM_DEV_A)) & 0x00008000 ) >> 15)
++#define GET_I2CM_LEN (((REG32(ADR_I2CM_LEN)) & 0x0000ffff ) >> 0)
++#define GET_I2CM_T_LEFT (((REG32(ADR_I2CM_LEN)) & 0x00070000 ) >> 16)
++#define GET_I2CM_R_GET (((REG32(ADR_I2CM_LEN)) & 0x07000000 ) >> 24)
++#define GET_I2CM_WDAT (((REG32(ADR_I2CM_WDAT)) & 0xffffffff ) >> 0)
++#define GET_I2CM_RDAT (((REG32(ADR_I2CM_RDAT)) & 0xffffffff ) >> 0)
++#define GET_I2CM_SR_LEN (((REG32(ADR_I2CM_EN_2)) & 0x0000ffff ) >> 0)
++#define GET_I2CM_SR_RX (((REG32(ADR_I2CM_EN_2)) & 0x00010000 ) >> 16)
++#define GET_I2CM_REPEAT_START (((REG32(ADR_I2CM_EN_2)) & 0x00020000 ) >> 17)
++#define GET_UART_DATA (((REG32(ADR_UART_DATA)) & 0x000000ff ) >> 0)
++#define GET_DATA_RDY_IE (((REG32(ADR_UART_IER)) & 0x00000001 ) >> 0)
++#define GET_THR_EMPTY_IE (((REG32(ADR_UART_IER)) & 0x00000002 ) >> 1)
++#define GET_RX_LINESTS_IE (((REG32(ADR_UART_IER)) & 0x00000004 ) >> 2)
++#define GET_MDM_STS_IE (((REG32(ADR_UART_IER)) & 0x00000008 ) >> 3)
++#define GET_DMA_RXEND_IE (((REG32(ADR_UART_IER)) & 0x00000040 ) >> 6)
++#define GET_DMA_TXEND_IE (((REG32(ADR_UART_IER)) & 0x00000080 ) >> 7)
++#define GET_FIFO_EN (((REG32(ADR_UART_FCR)) & 0x00000001 ) >> 0)
++#define GET_RXFIFO_RST (((REG32(ADR_UART_FCR)) & 0x00000002 ) >> 1)
++#define GET_TXFIFO_RST (((REG32(ADR_UART_FCR)) & 0x00000004 ) >> 2)
++#define GET_DMA_MODE (((REG32(ADR_UART_FCR)) & 0x00000008 ) >> 3)
++#define GET_EN_AUTO_RTS (((REG32(ADR_UART_FCR)) & 0x00000010 ) >> 4)
++#define GET_EN_AUTO_CTS (((REG32(ADR_UART_FCR)) & 0x00000020 ) >> 5)
++#define GET_RXFIFO_TRGLVL (((REG32(ADR_UART_FCR)) & 0x000000c0 ) >> 6)
++#define GET_WORD_LEN (((REG32(ADR_UART_LCR)) & 0x00000003 ) >> 0)
++#define GET_STOP_BIT (((REG32(ADR_UART_LCR)) & 0x00000004 ) >> 2)
++#define GET_PARITY_EN (((REG32(ADR_UART_LCR)) & 0x00000008 ) >> 3)
++#define GET_EVEN_PARITY (((REG32(ADR_UART_LCR)) & 0x00000010 ) >> 4)
++#define GET_FORCE_PARITY (((REG32(ADR_UART_LCR)) & 0x00000020 ) >> 5)
++#define GET_SET_BREAK (((REG32(ADR_UART_LCR)) & 0x00000040 ) >> 6)
++#define GET_DLAB (((REG32(ADR_UART_LCR)) & 0x00000080 ) >> 7)
++#define GET_DTR (((REG32(ADR_UART_MCR)) & 0x00000001 ) >> 0)
++#define GET_RTS (((REG32(ADR_UART_MCR)) & 0x00000002 ) >> 1)
++#define GET_OUT_1 (((REG32(ADR_UART_MCR)) & 0x00000004 ) >> 2)
++#define GET_OUT_2 (((REG32(ADR_UART_MCR)) & 0x00000008 ) >> 3)
++#define GET_LOOP_BACK (((REG32(ADR_UART_MCR)) & 0x00000010 ) >> 4)
++#define GET_DATA_RDY (((REG32(ADR_UART_LSR)) & 0x00000001 ) >> 0)
++#define GET_OVERRUN_ERR (((REG32(ADR_UART_LSR)) & 0x00000002 ) >> 1)
++#define GET_PARITY_ERR (((REG32(ADR_UART_LSR)) & 0x00000004 ) >> 2)
++#define GET_FRAMING_ERR (((REG32(ADR_UART_LSR)) & 0x00000008 ) >> 3)
++#define GET_BREAK_INT (((REG32(ADR_UART_LSR)) & 0x00000010 ) >> 4)
++#define GET_THR_EMPTY (((REG32(ADR_UART_LSR)) & 0x00000020 ) >> 5)
++#define GET_TX_EMPTY (((REG32(ADR_UART_LSR)) & 0x00000040 ) >> 6)
++#define GET_FIFODATA_ERR (((REG32(ADR_UART_LSR)) & 0x00000080 ) >> 7)
++#define GET_DELTA_CTS (((REG32(ADR_UART_MSR)) & 0x00000001 ) >> 0)
++#define GET_DELTA_DSR (((REG32(ADR_UART_MSR)) & 0x00000002 ) >> 1)
++#define GET_TRAILEDGE_RI (((REG32(ADR_UART_MSR)) & 0x00000004 ) >> 2)
++#define GET_DELTA_CD (((REG32(ADR_UART_MSR)) & 0x00000008 ) >> 3)
++#define GET_CTS (((REG32(ADR_UART_MSR)) & 0x00000010 ) >> 4)
++#define GET_DSR (((REG32(ADR_UART_MSR)) & 0x00000020 ) >> 5)
++#define GET_RI (((REG32(ADR_UART_MSR)) & 0x00000040 ) >> 6)
++#define GET_CD (((REG32(ADR_UART_MSR)) & 0x00000080 ) >> 7)
++#define GET_BRDC_DIV (((REG32(ADR_UART_SPR)) & 0x0000ffff ) >> 0)
++#define GET_RTHR_L (((REG32(ADR_UART_RTHR)) & 0x0000000f ) >> 0)
++#define GET_RTHR_H (((REG32(ADR_UART_RTHR)) & 0x000000f0 ) >> 4)
++#define GET_INT_IDCODE (((REG32(ADR_UART_ISR)) & 0x0000000f ) >> 0)
++#define GET_FIFOS_ENABLED (((REG32(ADR_UART_ISR)) & 0x000000c0 ) >> 6)
++#define GET_DAT_UART_DATA (((REG32(ADR_DAT_UART_DATA)) & 0x000000ff ) >> 0)
++#define GET_DAT_DATA_RDY_IE (((REG32(ADR_DAT_UART_IER)) & 0x00000001 ) >> 0)
++#define GET_DAT_THR_EMPTY_IE (((REG32(ADR_DAT_UART_IER)) & 0x00000002 ) >> 1)
++#define GET_DAT_RX_LINESTS_IE (((REG32(ADR_DAT_UART_IER)) & 0x00000004 ) >> 2)
++#define GET_DAT_MDM_STS_IE (((REG32(ADR_DAT_UART_IER)) & 0x00000008 ) >> 3)
++#define GET_DAT_DMA_RXEND_IE (((REG32(ADR_DAT_UART_IER)) & 0x00000040 ) >> 6)
++#define GET_DAT_DMA_TXEND_IE (((REG32(ADR_DAT_UART_IER)) & 0x00000080 ) >> 7)
++#define GET_DAT_FIFO_EN (((REG32(ADR_DAT_UART_FCR)) & 0x00000001 ) >> 0)
++#define GET_DAT_RXFIFO_RST (((REG32(ADR_DAT_UART_FCR)) & 0x00000002 ) >> 1)
++#define GET_DAT_TXFIFO_RST (((REG32(ADR_DAT_UART_FCR)) & 0x00000004 ) >> 2)
++#define GET_DAT_DMA_MODE (((REG32(ADR_DAT_UART_FCR)) & 0x00000008 ) >> 3)
++#define GET_DAT_EN_AUTO_RTS (((REG32(ADR_DAT_UART_FCR)) & 0x00000010 ) >> 4)
++#define GET_DAT_EN_AUTO_CTS (((REG32(ADR_DAT_UART_FCR)) & 0x00000020 ) >> 5)
++#define GET_DAT_RXFIFO_TRGLVL (((REG32(ADR_DAT_UART_FCR)) & 0x000000c0 ) >> 6)
++#define GET_DAT_WORD_LEN (((REG32(ADR_DAT_UART_LCR)) & 0x00000003 ) >> 0)
++#define GET_DAT_STOP_BIT (((REG32(ADR_DAT_UART_LCR)) & 0x00000004 ) >> 2)
++#define GET_DAT_PARITY_EN (((REG32(ADR_DAT_UART_LCR)) & 0x00000008 ) >> 3)
++#define GET_DAT_EVEN_PARITY (((REG32(ADR_DAT_UART_LCR)) & 0x00000010 ) >> 4)
++#define GET_DAT_FORCE_PARITY (((REG32(ADR_DAT_UART_LCR)) & 0x00000020 ) >> 5)
++#define GET_DAT_SET_BREAK (((REG32(ADR_DAT_UART_LCR)) & 0x00000040 ) >> 6)
++#define GET_DAT_DLAB (((REG32(ADR_DAT_UART_LCR)) & 0x00000080 ) >> 7)
++#define GET_DAT_DTR (((REG32(ADR_DAT_UART_MCR)) & 0x00000001 ) >> 0)
++#define GET_DAT_RTS (((REG32(ADR_DAT_UART_MCR)) & 0x00000002 ) >> 1)
++#define GET_DAT_OUT_1 (((REG32(ADR_DAT_UART_MCR)) & 0x00000004 ) >> 2)
++#define GET_DAT_OUT_2 (((REG32(ADR_DAT_UART_MCR)) & 0x00000008 ) >> 3)
++#define GET_DAT_LOOP_BACK (((REG32(ADR_DAT_UART_MCR)) & 0x00000010 ) >> 4)
++#define GET_DAT_DATA_RDY (((REG32(ADR_DAT_UART_LSR)) & 0x00000001 ) >> 0)
++#define GET_DAT_OVERRUN_ERR (((REG32(ADR_DAT_UART_LSR)) & 0x00000002 ) >> 1)
++#define GET_DAT_PARITY_ERR (((REG32(ADR_DAT_UART_LSR)) & 0x00000004 ) >> 2)
++#define GET_DAT_FRAMING_ERR (((REG32(ADR_DAT_UART_LSR)) & 0x00000008 ) >> 3)
++#define GET_DAT_BREAK_INT (((REG32(ADR_DAT_UART_LSR)) & 0x00000010 ) >> 4)
++#define GET_DAT_THR_EMPTY (((REG32(ADR_DAT_UART_LSR)) & 0x00000020 ) >> 5)
++#define GET_DAT_TX_EMPTY (((REG32(ADR_DAT_UART_LSR)) & 0x00000040 ) >> 6)
++#define GET_DAT_FIFODATA_ERR (((REG32(ADR_DAT_UART_LSR)) & 0x00000080 ) >> 7)
++#define GET_DAT_DELTA_CTS (((REG32(ADR_DAT_UART_MSR)) & 0x00000001 ) >> 0)
++#define GET_DAT_DELTA_DSR (((REG32(ADR_DAT_UART_MSR)) & 0x00000002 ) >> 1)
++#define GET_DAT_TRAILEDGE_RI (((REG32(ADR_DAT_UART_MSR)) & 0x00000004 ) >> 2)
++#define GET_DAT_DELTA_CD (((REG32(ADR_DAT_UART_MSR)) & 0x00000008 ) >> 3)
++#define GET_DAT_CTS (((REG32(ADR_DAT_UART_MSR)) & 0x00000010 ) >> 4)
++#define GET_DAT_DSR (((REG32(ADR_DAT_UART_MSR)) & 0x00000020 ) >> 5)
++#define GET_DAT_RI (((REG32(ADR_DAT_UART_MSR)) & 0x00000040 ) >> 6)
++#define GET_DAT_CD (((REG32(ADR_DAT_UART_MSR)) & 0x00000080 ) >> 7)
++#define GET_DAT_BRDC_DIV (((REG32(ADR_DAT_UART_SPR)) & 0x0000ffff ) >> 0)
++#define GET_DAT_RTHR_L (((REG32(ADR_DAT_UART_RTHR)) & 0x0000000f ) >> 0)
++#define GET_DAT_RTHR_H (((REG32(ADR_DAT_UART_RTHR)) & 0x000000f0 ) >> 4)
++#define GET_DAT_INT_IDCODE (((REG32(ADR_DAT_UART_ISR)) & 0x0000000f ) >> 0)
++#define GET_DAT_FIFOS_ENABLED (((REG32(ADR_DAT_UART_ISR)) & 0x000000c0 ) >> 6)
++#define GET_MASK_TOP (((REG32(ADR_INT_MASK)) & 0xffffffff ) >> 0)
++#define GET_INT_MODE (((REG32(ADR_INT_MODE)) & 0xffffffff ) >> 0)
++#define GET_IRQ_PHY_0 (((REG32(ADR_INT_IRQ_STS)) & 0x00000001 ) >> 0)
++#define GET_IRQ_PHY_1 (((REG32(ADR_INT_IRQ_STS)) & 0x00000002 ) >> 1)
++#define GET_IRQ_SDIO (((REG32(ADR_INT_IRQ_STS)) & 0x00000004 ) >> 2)
++#define GET_IRQ_BEACON_DONE (((REG32(ADR_INT_IRQ_STS)) & 0x00000008 ) >> 3)
++#define GET_IRQ_BEACON (((REG32(ADR_INT_IRQ_STS)) & 0x00000010 ) >> 4)
++#define GET_IRQ_PRE_BEACON (((REG32(ADR_INT_IRQ_STS)) & 0x00000020 ) >> 5)
++#define GET_IRQ_EDCA0_TX_DONE (((REG32(ADR_INT_IRQ_STS)) & 0x00000040 ) >> 6)
++#define GET_IRQ_EDCA1_TX_DONE (((REG32(ADR_INT_IRQ_STS)) & 0x00000080 ) >> 7)
++#define GET_IRQ_EDCA2_TX_DONE (((REG32(ADR_INT_IRQ_STS)) & 0x00000100 ) >> 8)
++#define GET_IRQ_EDCA3_TX_DONE (((REG32(ADR_INT_IRQ_STS)) & 0x00000200 ) >> 9)
++#define GET_IRQ_EDCA4_TX_DONE (((REG32(ADR_INT_IRQ_STS)) & 0x00000400 ) >> 10)
++#define GET_IRQ_BEACON_DTIM (((REG32(ADR_INT_IRQ_STS)) & 0x00001000 ) >> 12)
++#define GET_IRQ_EDCA0_LOWTHOLD_INT (((REG32(ADR_INT_IRQ_STS)) & 0x00002000 ) >> 13)
++#define GET_IRQ_EDCA1_LOWTHOLD_INT (((REG32(ADR_INT_IRQ_STS)) & 0x00004000 ) >> 14)
++#define GET_IRQ_EDCA2_LOWTHOLD_INT (((REG32(ADR_INT_IRQ_STS)) & 0x00008000 ) >> 15)
++#define GET_IRQ_EDCA3_LOWTHOLD_INT (((REG32(ADR_INT_IRQ_STS)) & 0x00010000 ) >> 16)
++#define GET_IRQ_FENCE_HIT_INT (((REG32(ADR_INT_IRQ_STS)) & 0x00020000 ) >> 17)
++#define GET_IRQ_ILL_ADDR_INT (((REG32(ADR_INT_IRQ_STS)) & 0x00040000 ) >> 18)
++#define GET_IRQ_MBOX (((REG32(ADR_INT_IRQ_STS)) & 0x00080000 ) >> 19)
++#define GET_IRQ_US_TIMER0 (((REG32(ADR_INT_IRQ_STS)) & 0x00100000 ) >> 20)
++#define GET_IRQ_US_TIMER1 (((REG32(ADR_INT_IRQ_STS)) & 0x00200000 ) >> 21)
++#define GET_IRQ_US_TIMER2 (((REG32(ADR_INT_IRQ_STS)) & 0x00400000 ) >> 22)
++#define GET_IRQ_US_TIMER3 (((REG32(ADR_INT_IRQ_STS)) & 0x00800000 ) >> 23)
++#define GET_IRQ_MS_TIMER0 (((REG32(ADR_INT_IRQ_STS)) & 0x01000000 ) >> 24)
++#define GET_IRQ_MS_TIMER1 (((REG32(ADR_INT_IRQ_STS)) & 0x02000000 ) >> 25)
++#define GET_IRQ_MS_TIMER2 (((REG32(ADR_INT_IRQ_STS)) & 0x04000000 ) >> 26)
++#define GET_IRQ_MS_TIMER3 (((REG32(ADR_INT_IRQ_STS)) & 0x08000000 ) >> 27)
++#define GET_IRQ_TX_LIMIT_INT (((REG32(ADR_INT_IRQ_STS)) & 0x10000000 ) >> 28)
++#define GET_IRQ_DMA0 (((REG32(ADR_INT_IRQ_STS)) & 0x20000000 ) >> 29)
++#define GET_IRQ_CO_DMA (((REG32(ADR_INT_IRQ_STS)) & 0x40000000 ) >> 30)
++#define GET_IRQ_PERI_GROUP (((REG32(ADR_INT_IRQ_STS)) & 0x80000000 ) >> 31)
++#define GET_FIQ_STATUS (((REG32(ADR_INT_FIQ_STS)) & 0xffffffff ) >> 0)
++#define GET_IRQ_RAW (((REG32(ADR_INT_IRQ_RAW)) & 0xffffffff ) >> 0)
++#define GET_FIQ_RAW (((REG32(ADR_INT_FIQ_RAW)) & 0xffffffff ) >> 0)
++#define GET_INT_PERI_MASK (((REG32(ADR_INT_PERI_MASK)) & 0xffffffff ) >> 0)
++#define GET_PERI_RTC (((REG32(ADR_INT_PERI_STS)) & 0x00000001 ) >> 0)
++#define GET_IRQ_UART0_TX (((REG32(ADR_INT_PERI_STS)) & 0x00000002 ) >> 1)
++#define GET_IRQ_UART0_RX (((REG32(ADR_INT_PERI_STS)) & 0x00000004 ) >> 2)
++#define GET_PERI_GPI_2 (((REG32(ADR_INT_PERI_STS)) & 0x00000008 ) >> 3)
++#define GET_IRQ_SPI_IPC (((REG32(ADR_INT_PERI_STS)) & 0x00000010 ) >> 4)
++#define GET_PERI_GPI_1_0 (((REG32(ADR_INT_PERI_STS)) & 0x00000060 ) >> 5)
++#define GET_SCRT_INT_1 (((REG32(ADR_INT_PERI_STS)) & 0x00000080 ) >> 7)
++#define GET_MMU_ALC_ERR (((REG32(ADR_INT_PERI_STS)) & 0x00000100 ) >> 8)
++#define GET_MMU_RLS_ERR (((REG32(ADR_INT_PERI_STS)) & 0x00000200 ) >> 9)
++#define GET_ID_MNG_INT_1 (((REG32(ADR_INT_PERI_STS)) & 0x00000400 ) >> 10)
++#define GET_MBOX_INT_1 (((REG32(ADR_INT_PERI_STS)) & 0x00000800 ) >> 11)
++#define GET_MBOX_INT_2 (((REG32(ADR_INT_PERI_STS)) & 0x00001000 ) >> 12)
++#define GET_MBOX_INT_3 (((REG32(ADR_INT_PERI_STS)) & 0x00002000 ) >> 13)
++#define GET_HCI_INT_1 (((REG32(ADR_INT_PERI_STS)) & 0x00004000 ) >> 14)
++#define GET_UART_RX_TIMEOUT (((REG32(ADR_INT_PERI_STS)) & 0x00008000 ) >> 15)
++#define GET_UART_MULTI_IRQ (((REG32(ADR_INT_PERI_STS)) & 0x00010000 ) >> 16)
++#define GET_ID_MNG_INT_2 (((REG32(ADR_INT_PERI_STS)) & 0x00020000 ) >> 17)
++#define GET_DMN_NOHIT_INT (((REG32(ADR_INT_PERI_STS)) & 0x00040000 ) >> 18)
++#define GET_ID_THOLD_RX (((REG32(ADR_INT_PERI_STS)) & 0x00080000 ) >> 19)
++#define GET_ID_THOLD_TX (((REG32(ADR_INT_PERI_STS)) & 0x00100000 ) >> 20)
++#define GET_ID_DOUBLE_RLS (((REG32(ADR_INT_PERI_STS)) & 0x00200000 ) >> 21)
++#define GET_RX_ID_LEN_THOLD (((REG32(ADR_INT_PERI_STS)) & 0x00400000 ) >> 22)
++#define GET_TX_ID_LEN_THOLD (((REG32(ADR_INT_PERI_STS)) & 0x00800000 ) >> 23)
++#define GET_ALL_ID_LEN_THOLD (((REG32(ADR_INT_PERI_STS)) & 0x01000000 ) >> 24)
++#define GET_DMN_MCU_INT (((REG32(ADR_INT_PERI_STS)) & 0x02000000 ) >> 25)
++#define GET_IRQ_DAT_UART_TX (((REG32(ADR_INT_PERI_STS)) & 0x04000000 ) >> 26)
++#define GET_IRQ_DAT_UART_RX (((REG32(ADR_INT_PERI_STS)) & 0x08000000 ) >> 27)
++#define GET_DAT_UART_RX_TIMEOUT (((REG32(ADR_INT_PERI_STS)) & 0x10000000 ) >> 28)
++#define GET_DAT_UART_MULTI_IRQ (((REG32(ADR_INT_PERI_STS)) & 0x20000000 ) >> 29)
++#define GET_ALR_ABT_NOCHG_INT_IRQ (((REG32(ADR_INT_PERI_STS)) & 0x40000000 ) >> 30)
++#define GET_TBLNEQ_MNGPKT_INT_IRQ (((REG32(ADR_INT_PERI_STS)) & 0x80000000 ) >> 31)
++#define GET_INTR_PERI_RAW (((REG32(ADR_INT_PERI_RAW)) & 0xffffffff ) >> 0)
++#define GET_INTR_GPI00_CFG (((REG32(ADR_INT_GPI_CFG)) & 0x00000003 ) >> 0)
++#define GET_INTR_GPI01_CFG (((REG32(ADR_INT_GPI_CFG)) & 0x0000000c ) >> 2)
++#define GET_SYS_RST_INT (((REG32(ADR_SYS_INT_FOR_HOST)) & 0x00000001 ) >> 0)
++#define GET_SPI_IPC_ADDR (((REG32(ADR_SPI_IPC)) & 0xffffffff ) >> 0)
++#define GET_SD_MASK_TOP (((REG32(ADR_SDIO_MASK)) & 0xffffffff ) >> 0)
++#define GET_IRQ_PHY_0_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000001 ) >> 0)
++#define GET_IRQ_PHY_1_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000002 ) >> 1)
++#define GET_IRQ_SDIO_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000004 ) >> 2)
++#define GET_IRQ_BEACON_DONE_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000008 ) >> 3)
++#define GET_IRQ_BEACON_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000010 ) >> 4)
++#define GET_IRQ_PRE_BEACON_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000020 ) >> 5)
++#define GET_IRQ_EDCA0_TX_DONE_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000040 ) >> 6)
++#define GET_IRQ_EDCA1_TX_DONE_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000080 ) >> 7)
++#define GET_IRQ_EDCA2_TX_DONE_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000100 ) >> 8)
++#define GET_IRQ_EDCA3_TX_DONE_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000200 ) >> 9)
++#define GET_IRQ_EDCA4_TX_DONE_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000400 ) >> 10)
++#define GET_IRQ_BEACON_DTIM_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00001000 ) >> 12)
++#define GET_IRQ_EDCA0_LOWTHOLD_INT_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00002000 ) >> 13)
++#define GET_IRQ_EDCA1_LOWTHOLD_INT_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00004000 ) >> 14)
++#define GET_IRQ_EDCA2_LOWTHOLD_INT_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00008000 ) >> 15)
++#define GET_IRQ_EDCA3_LOWTHOLD_INT_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00010000 ) >> 16)
++#define GET_IRQ_FENCE_HIT_INT_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00020000 ) >> 17)
++#define GET_IRQ_ILL_ADDR_INT_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00040000 ) >> 18)
++#define GET_IRQ_MBOX_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00080000 ) >> 19)
++#define GET_IRQ_US_TIMER0_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00100000 ) >> 20)
++#define GET_IRQ_US_TIMER1_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00200000 ) >> 21)
++#define GET_IRQ_US_TIMER2_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00400000 ) >> 22)
++#define GET_IRQ_US_TIMER3_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00800000 ) >> 23)
++#define GET_IRQ_MS_TIMER0_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x01000000 ) >> 24)
++#define GET_IRQ_MS_TIMER1_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x02000000 ) >> 25)
++#define GET_IRQ_MS_TIMER2_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x04000000 ) >> 26)
++#define GET_IRQ_MS_TIMER3_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x08000000 ) >> 27)
++#define GET_IRQ_TX_LIMIT_INT_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x10000000 ) >> 28)
++#define GET_IRQ_DMA0_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x20000000 ) >> 29)
++#define GET_IRQ_CO_DMA_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x40000000 ) >> 30)
++#define GET_IRQ_PERI_GROUP_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x80000000 ) >> 31)
++#define GET_INT_PERI_MASK_SD (((REG32(ADR_SD_PERI_MASK)) & 0xffffffff ) >> 0)
++#define GET_PERI_RTC_SD (((REG32(ADR_SD_PERI_STS)) & 0x00000001 ) >> 0)
++#define GET_IRQ_UART0_TX_SD (((REG32(ADR_SD_PERI_STS)) & 0x00000002 ) >> 1)
++#define GET_IRQ_UART0_RX_SD (((REG32(ADR_SD_PERI_STS)) & 0x00000004 ) >> 2)
++#define GET_PERI_GPI_SD_2 (((REG32(ADR_SD_PERI_STS)) & 0x00000008 ) >> 3)
++#define GET_IRQ_SPI_IPC_SD (((REG32(ADR_SD_PERI_STS)) & 0x00000010 ) >> 4)
++#define GET_PERI_GPI_SD_1_0 (((REG32(ADR_SD_PERI_STS)) & 0x00000060 ) >> 5)
++#define GET_SCRT_INT_1_SD (((REG32(ADR_SD_PERI_STS)) & 0x00000080 ) >> 7)
++#define GET_MMU_ALC_ERR_SD (((REG32(ADR_SD_PERI_STS)) & 0x00000100 ) >> 8)
++#define GET_MMU_RLS_ERR_SD (((REG32(ADR_SD_PERI_STS)) & 0x00000200 ) >> 9)
++#define GET_ID_MNG_INT_1_SD (((REG32(ADR_SD_PERI_STS)) & 0x00000400 ) >> 10)
++#define GET_MBOX_INT_1_SD (((REG32(ADR_SD_PERI_STS)) & 0x00000800 ) >> 11)
++#define GET_MBOX_INT_2_SD (((REG32(ADR_SD_PERI_STS)) & 0x00001000 ) >> 12)
++#define GET_MBOX_INT_3_SD (((REG32(ADR_SD_PERI_STS)) & 0x00002000 ) >> 13)
++#define GET_HCI_INT_1_SD (((REG32(ADR_SD_PERI_STS)) & 0x00004000 ) >> 14)
++#define GET_UART_RX_TIMEOUT_SD (((REG32(ADR_SD_PERI_STS)) & 0x00008000 ) >> 15)
++#define GET_UART_MULTI_IRQ_SD (((REG32(ADR_SD_PERI_STS)) & 0x00010000 ) >> 16)
++#define GET_ID_MNG_INT_2_SD (((REG32(ADR_SD_PERI_STS)) & 0x00020000 ) >> 17)
++#define GET_DMN_NOHIT_INT_SD (((REG32(ADR_SD_PERI_STS)) & 0x00040000 ) >> 18)
++#define GET_ID_THOLD_RX_SD (((REG32(ADR_SD_PERI_STS)) & 0x00080000 ) >> 19)
++#define GET_ID_THOLD_TX_SD (((REG32(ADR_SD_PERI_STS)) & 0x00100000 ) >> 20)
++#define GET_ID_DOUBLE_RLS_SD (((REG32(ADR_SD_PERI_STS)) & 0x00200000 ) >> 21)
++#define GET_RX_ID_LEN_THOLD_SD (((REG32(ADR_SD_PERI_STS)) & 0x00400000 ) >> 22)
++#define GET_TX_ID_LEN_THOLD_SD (((REG32(ADR_SD_PERI_STS)) & 0x00800000 ) >> 23)
++#define GET_ALL_ID_LEN_THOLD_SD (((REG32(ADR_SD_PERI_STS)) & 0x01000000 ) >> 24)
++#define GET_DMN_MCU_INT_SD (((REG32(ADR_SD_PERI_STS)) & 0x02000000 ) >> 25)
++#define GET_IRQ_DAT_UART_TX_SD (((REG32(ADR_SD_PERI_STS)) & 0x04000000 ) >> 26)
++#define GET_IRQ_DAT_UART_RX_SD (((REG32(ADR_SD_PERI_STS)) & 0x08000000 ) >> 27)
++#define GET_DAT_UART_RX_TIMEOUT_SD (((REG32(ADR_SD_PERI_STS)) & 0x10000000 ) >> 28)
++#define GET_DAT_UART_MULTI_IRQ_SD (((REG32(ADR_SD_PERI_STS)) & 0x20000000 ) >> 29)
++#define GET_ALR_ABT_NOCHG_INT_IRQ_SD (((REG32(ADR_SD_PERI_STS)) & 0x40000000 ) >> 30)
++#define GET_TBLNEQ_MNGPKT_INT_IRQ_SD (((REG32(ADR_SD_PERI_STS)) & 0x80000000 ) >> 31)
++#define GET_DBG_SPI_MODE (((REG32(ADR_DBG_SPI_MODE)) & 0xffffffff ) >> 0)
++#define GET_DBG_RX_QUOTA (((REG32(ADR_DBG_RX_QUOTA)) & 0x0000ffff ) >> 0)
++#define GET_DBG_CONDI_NUM (((REG32(ADR_DBG_CONDITION_NUMBER)) & 0x000000ff ) >> 0)
++#define GET_DBG_HOST_PATH (((REG32(ADR_DBG_HOST_PATH)) & 0x00000001 ) >> 0)
++#define GET_DBG_TX_SEG (((REG32(ADR_DBG_TX_SEG)) & 0xffffffff ) >> 0)
++#define GET_DBG_BRST_MODE (((REG32(ADR_DBG_DEBUG_BURST_MODE)) & 0x00000001 ) >> 0)
++#define GET_DBG_CLK_WIDTH (((REG32(ADR_DBG_SPI_TO_PHY_PARAM1)) & 0x0000ffff ) >> 0)
++#define GET_DBG_CSN_INTER (((REG32(ADR_DBG_SPI_TO_PHY_PARAM1)) & 0xffff0000 ) >> 16)
++#define GET_DBG_BACK_DLY (((REG32(ADR_DBG_SPI_TO_PHY_PARAM2)) & 0x0000ffff ) >> 0)
++#define GET_DBG_FRONT_DLY (((REG32(ADR_DBG_SPI_TO_PHY_PARAM2)) & 0xffff0000 ) >> 16)
++#define GET_DBG_RX_FIFO_FAIL (((REG32(ADR_DBG_SPI_STS)) & 0x00000002 ) >> 1)
++#define GET_DBG_RX_HOST_FAIL (((REG32(ADR_DBG_SPI_STS)) & 0x00000004 ) >> 2)
++#define GET_DBG_TX_FIFO_FAIL (((REG32(ADR_DBG_SPI_STS)) & 0x00000008 ) >> 3)
++#define GET_DBG_TX_HOST_FAIL (((REG32(ADR_DBG_SPI_STS)) & 0x00000010 ) >> 4)
++#define GET_DBG_SPI_DOUBLE_ALLOC (((REG32(ADR_DBG_SPI_STS)) & 0x00000020 ) >> 5)
++#define GET_DBG_SPI_TX_NO_ALLOC (((REG32(ADR_DBG_SPI_STS)) & 0x00000040 ) >> 6)
++#define GET_DBG_RDATA_RDY (((REG32(ADR_DBG_SPI_STS)) & 0x00000080 ) >> 7)
++#define GET_DBG_SPI_ALLOC_STATUS (((REG32(ADR_DBG_SPI_STS)) & 0x00000100 ) >> 8)
++#define GET_DBG_SPI_DBG_WR_FIFO_FULL (((REG32(ADR_DBG_SPI_STS)) & 0x00000200 ) >> 9)
++#define GET_DBG_RX_LEN (((REG32(ADR_DBG_SPI_STS)) & 0xffff0000 ) >> 16)
++#define GET_DBG_SPI_TX_ALLOC_SIZE_SHIFT_BITS (((REG32(ADR_DBG_TX_ALLOC_SET)) & 0x00000007 ) >> 0)
++#define GET_DBG_SPI_HOST_TX_ALLOC_PKBUF (((REG32(ADR_DBG_TX_ALLOC_SET)) & 0x00000100 ) >> 8)
++#define GET_DBG_SPI_TX_ALLOC_SIZE (((REG32(ADR_DBG_TX_ALLOC)) & 0x000000ff ) >> 0)
++#define GET_DBG_RD_DAT_CNT (((REG32(ADR_DBG_DBG_CNT)) & 0x0000ffff ) >> 0)
++#define GET_DBG_RD_STS_CNT (((REG32(ADR_DBG_DBG_CNT)) & 0xffff0000 ) >> 16)
++#define GET_DBG_JUDGE_CNT (((REG32(ADR_DBG_DBG_CNT2)) & 0x0000ffff ) >> 0)
++#define GET_DBG_RD_STS_CNT_CLR (((REG32(ADR_DBG_DBG_CNT2)) & 0x00010000 ) >> 16)
++#define GET_DBG_RD_DAT_CNT_CLR (((REG32(ADR_DBG_DBG_CNT2)) & 0x00020000 ) >> 17)
++#define GET_DBG_JUDGE_CNT_CLR (((REG32(ADR_DBG_DBG_CNT2)) & 0x00040000 ) >> 18)
++#define GET_DBG_TX_DONE_CNT (((REG32(ADR_DBG_DBG_CNT3)) & 0x0000ffff ) >> 0)
++#define GET_DBG_TX_DISCARD_CNT (((REG32(ADR_DBG_DBG_CNT3)) & 0xffff0000 ) >> 16)
++#define GET_DBG_TX_SET_CNT (((REG32(ADR_DBG_DBG_CNT4)) & 0x0000ffff ) >> 0)
++#define GET_DBG_TX_DISCARD_CNT_CLR (((REG32(ADR_DBG_DBG_CNT4)) & 0x00010000 ) >> 16)
++#define GET_DBG_TX_DONE_CNT_CLR (((REG32(ADR_DBG_DBG_CNT4)) & 0x00020000 ) >> 17)
++#define GET_DBG_TX_SET_CNT_CLR (((REG32(ADR_DBG_DBG_CNT4)) & 0x00040000 ) >> 18)
++#define GET_DBG_DAT_MODE_OFF (((REG32(ADR_DBG_DBG_CNT4)) & 0x00080000 ) >> 19)
++#define GET_DBG_TX_FIFO_RESIDUE (((REG32(ADR_DBG_DBG_CNT4)) & 0x00700000 ) >> 20)
++#define GET_DBG_RX_FIFO_RESIDUE (((REG32(ADR_DBG_DBG_CNT4)) & 0x07000000 ) >> 24)
++#define GET_DBG_RX_RDY (((REG32(ADR_DBG_INT_TAG)) & 0x00000001 ) >> 0)
++#define GET_DBG_SDIO_SYS_INT (((REG32(ADR_DBG_INT_TAG)) & 0x00000004 ) >> 2)
++#define GET_DBG_EDCA0_LOWTHOLD_INT (((REG32(ADR_DBG_INT_TAG)) & 0x00000008 ) >> 3)
++#define GET_DBG_EDCA1_LOWTHOLD_INT (((REG32(ADR_DBG_INT_TAG)) & 0x00000010 ) >> 4)
++#define GET_DBG_EDCA2_LOWTHOLD_INT (((REG32(ADR_DBG_INT_TAG)) & 0x00000020 ) >> 5)
++#define GET_DBG_EDCA3_LOWTHOLD_INT (((REG32(ADR_DBG_INT_TAG)) & 0x00000040 ) >> 6)
++#define GET_DBG_TX_LIMIT_INT_IN (((REG32(ADR_DBG_INT_TAG)) & 0x00000080 ) >> 7)
++#define GET_DBG_SPI_FN1 (((REG32(ADR_DBG_INT_TAG)) & 0x00007f00 ) >> 8)
++#define GET_DBG_SPI_CLK_EN_INT (((REG32(ADR_DBG_INT_TAG)) & 0x00008000 ) >> 15)
++#define GET_DBG_SPI_HOST_MASK (((REG32(ADR_DBG_INT_TAG)) & 0x00ff0000 ) >> 16)
++#define GET_BOOT_ADDR (((REG32(ADR_BOOT_ADDR)) & 0x00ffffff ) >> 0)
++#define GET_CHECK_SUM_FAIL (((REG32(ADR_BOOT_ADDR)) & 0x80000000 ) >> 31)
++#define GET_VERIFY_DATA (((REG32(ADR_VERIFY_DATA)) & 0xffffffff ) >> 0)
++#define GET_FLASH_ADDR (((REG32(ADR_FLASH_ADDR)) & 0x00ffffff ) >> 0)
++#define GET_FLASH_CMD_CLR (((REG32(ADR_FLASH_ADDR)) & 0x10000000 ) >> 28)
++#define GET_FLASH_DMA_CLR (((REG32(ADR_FLASH_ADDR)) & 0x20000000 ) >> 29)
++#define GET_DMA_EN (((REG32(ADR_FLASH_ADDR)) & 0x40000000 ) >> 30)
++#define GET_DMA_BUSY (((REG32(ADR_FLASH_ADDR)) & 0x80000000 ) >> 31)
++#define GET_SRAM_ADDR (((REG32(ADR_SRAM_ADDR)) & 0xffffffff ) >> 0)
++#define GET_FLASH_DMA_LEN (((REG32(ADR_LEN)) & 0xffffffff ) >> 0)
++#define GET_FLASH_FRONT_DLY (((REG32(ADR_SPI_PARAM)) & 0x0000ffff ) >> 0)
++#define GET_FLASH_BACK_DLY (((REG32(ADR_SPI_PARAM)) & 0xffff0000 ) >> 16)
++#define GET_FLASH_CLK_WIDTH (((REG32(ADR_SPI_PARAM2)) & 0x0000ffff ) >> 0)
++#define GET_SPI_BUSY (((REG32(ADR_SPI_PARAM2)) & 0x00010000 ) >> 16)
++#define GET_FLS_REMAP (((REG32(ADR_SPI_PARAM2)) & 0x00020000 ) >> 17)
++#define GET_PBUS_SWP (((REG32(ADR_SPI_PARAM2)) & 0x00040000 ) >> 18)
++#define GET_BIT_MODE1 (((REG32(ADR_SPI_PARAM2)) & 0x00080000 ) >> 19)
++#define GET_BIT_MODE2 (((REG32(ADR_SPI_PARAM2)) & 0x00100000 ) >> 20)
++#define GET_BIT_MODE4 (((REG32(ADR_SPI_PARAM2)) & 0x00200000 ) >> 21)
++#define GET_BOOT_CHECK_SUM (((REG32(ADR_CHECK_SUM_RESULT)) & 0xffffffff ) >> 0)
++#define GET_CHECK_SUM_TAG (((REG32(ADR_CHECK_SUM_IN_FILE)) & 0xffffffff ) >> 0)
++#define GET_CMD_LEN (((REG32(ADR_COMMAND_LEN)) & 0x0000ffff ) >> 0)
++#define GET_CMD_ADDR (((REG32(ADR_COMMAND_ADDR)) & 0xffffffff ) >> 0)
++#define GET_DMA_ADR_SRC (((REG32(ADR_DMA_ADR_SRC)) & 0xffffffff ) >> 0)
++#define GET_DMA_ADR_DST (((REG32(ADR_DMA_ADR_DST)) & 0xffffffff ) >> 0)
++#define GET_DMA_SRC_SIZE (((REG32(ADR_DMA_CTRL)) & 0x00000007 ) >> 0)
++#define GET_DMA_SRC_INC (((REG32(ADR_DMA_CTRL)) & 0x00000008 ) >> 3)
++#define GET_DMA_DST_SIZE (((REG32(ADR_DMA_CTRL)) & 0x00000070 ) >> 4)
++#define GET_DMA_DST_INC (((REG32(ADR_DMA_CTRL)) & 0x00000080 ) >> 7)
++#define GET_DMA_FAST_FILL (((REG32(ADR_DMA_CTRL)) & 0x00000100 ) >> 8)
++#define GET_DMA_SDIO_KICK (((REG32(ADR_DMA_CTRL)) & 0x00001000 ) >> 12)
++#define GET_DMA_BADR_EN (((REG32(ADR_DMA_CTRL)) & 0x00002000 ) >> 13)
++#define GET_DMA_LEN (((REG32(ADR_DMA_CTRL)) & 0xffff0000 ) >> 16)
++#define GET_DMA_INT_MASK (((REG32(ADR_DMA_INT)) & 0x00000001 ) >> 0)
++#define GET_DMA_STS (((REG32(ADR_DMA_INT)) & 0x00000100 ) >> 8)
++#define GET_DMA_FINISH (((REG32(ADR_DMA_INT)) & 0x80000000 ) >> 31)
++#define GET_DMA_CONST (((REG32(ADR_DMA_FILL_CONST)) & 0xffffffff ) >> 0)
++#define GET_SLEEP_WAKE_CNT (((REG32(ADR_PMU_0)) & 0x00ffffff ) >> 0)
++#define GET_RG_DLDO_LEVEL (((REG32(ADR_PMU_0)) & 0x07000000 ) >> 24)
++#define GET_RG_DLDO_BOOST_IQ (((REG32(ADR_PMU_0)) & 0x08000000 ) >> 27)
++#define GET_RG_BUCK_LEVEL (((REG32(ADR_PMU_0)) & 0x70000000 ) >> 28)
++#define GET_RG_BUCK_VREF_SEL (((REG32(ADR_PMU_0)) & 0x80000000 ) >> 31)
++#define GET_RG_RTC_OSC_RES_SW_MANUAL (((REG32(ADR_PMU_1)) & 0x000003ff ) >> 0)
++#define GET_RG_RTC_OSC_RES_SW (((REG32(ADR_PMU_1)) & 0x03ff0000 ) >> 16)
++#define GET_RTC_OSC_CAL_RES_RDY (((REG32(ADR_PMU_1)) & 0x80000000 ) >> 31)
++#define GET_RG_DCDC_MODE (((REG32(ADR_PMU_2)) & 0x00000001 ) >> 0)
++#define GET_RG_BUCK_EN_PSM (((REG32(ADR_PMU_2)) & 0x00000010 ) >> 4)
++#define GET_RG_BUCK_PSM_VTH (((REG32(ADR_PMU_2)) & 0x00000100 ) >> 8)
++#define GET_RG_RTC_OSC_RES_SW_MANUAL_EN (((REG32(ADR_PMU_2)) & 0x00001000 ) >> 12)
++#define GET_RG_RTC_RDY_DEGLITCH_TIMER (((REG32(ADR_PMU_2)) & 0x00006000 ) >> 13)
++#define GET_RTC_CAL_ENA (((REG32(ADR_PMU_2)) & 0x00010000 ) >> 16)
++#define GET_PMU_WAKE_TRIG_EVENT (((REG32(ADR_PMU_3)) & 0x00000003 ) >> 0)
++#define GET_DIGI_TOP_POR_MASK (((REG32(ADR_PMU_3)) & 0x00000010 ) >> 4)
++#define GET_PMU_ENTER_SLEEP_MODE (((REG32(ADR_PMU_3)) & 0x00000100 ) >> 8)
++#define GET_RG_RTC_DUMMIES (((REG32(ADR_PMU_3)) & 0xffff0000 ) >> 16)
++#define GET_RTC_EN (((REG32(ADR_RTC_1)) & 0x00000001 ) >> 0)
++#define GET_RTC_SRC (((REG32(ADR_RTC_1)) & 0x00000002 ) >> 1)
++#define GET_RTC_TICK_CNT (((REG32(ADR_RTC_1)) & 0x7fff0000 ) >> 16)
++#define GET_RTC_INT_SEC_MASK (((REG32(ADR_RTC_2)) & 0x00000001 ) >> 0)
++#define GET_RTC_INT_ALARM_MASK (((REG32(ADR_RTC_2)) & 0x00000002 ) >> 1)
++#define GET_RTC_INT_SEC (((REG32(ADR_RTC_2)) & 0x00010000 ) >> 16)
++#define GET_RTC_INT_ALARM (((REG32(ADR_RTC_2)) & 0x00020000 ) >> 17)
++#define GET_RTC_SEC_START_CNT (((REG32(ADR_RTC_3W)) & 0xffffffff ) >> 0)
++#define GET_RTC_SEC_CNT (((REG32(ADR_RTC_3R)) & 0xffffffff ) >> 0)
++#define GET_RTC_SEC_ALARM_VALUE (((REG32(ADR_RTC_4)) & 0xffffffff ) >> 0)
++#define GET_D2_DMA_ADR_SRC (((REG32(ADR_D2_DMA_ADR_SRC)) & 0xffffffff ) >> 0)
++#define GET_D2_DMA_ADR_DST (((REG32(ADR_D2_DMA_ADR_DST)) & 0xffffffff ) >> 0)
++#define GET_D2_DMA_SRC_SIZE (((REG32(ADR_D2_DMA_CTRL)) & 0x00000007 ) >> 0)
++#define GET_D2_DMA_SRC_INC (((REG32(ADR_D2_DMA_CTRL)) & 0x00000008 ) >> 3)
++#define GET_D2_DMA_DST_SIZE (((REG32(ADR_D2_DMA_CTRL)) & 0x00000070 ) >> 4)
++#define GET_D2_DMA_DST_INC (((REG32(ADR_D2_DMA_CTRL)) & 0x00000080 ) >> 7)
++#define GET_D2_DMA_FAST_FILL (((REG32(ADR_D2_DMA_CTRL)) & 0x00000100 ) >> 8)
++#define GET_D2_DMA_SDIO_KICK (((REG32(ADR_D2_DMA_CTRL)) & 0x00001000 ) >> 12)
++#define GET_D2_DMA_BADR_EN (((REG32(ADR_D2_DMA_CTRL)) & 0x00002000 ) >> 13)
++#define GET_D2_DMA_LEN (((REG32(ADR_D2_DMA_CTRL)) & 0xffff0000 ) >> 16)
++#define GET_D2_DMA_INT_MASK (((REG32(ADR_D2_DMA_INT)) & 0x00000001 ) >> 0)
++#define GET_D2_DMA_STS (((REG32(ADR_D2_DMA_INT)) & 0x00000100 ) >> 8)
++#define GET_D2_DMA_FINISH (((REG32(ADR_D2_DMA_INT)) & 0x80000000 ) >> 31)
++#define GET_D2_DMA_CONST (((REG32(ADR_D2_DMA_FILL_CONST)) & 0xffffffff ) >> 0)
++#define GET_TRAP_UNKNOWN_TYPE (((REG32(ADR_CONTROL)) & 0x00000001 ) >> 0)
++#define GET_TX_ON_DEMAND_ENA (((REG32(ADR_CONTROL)) & 0x00000002 ) >> 1)
++#define GET_RX_2_HOST (((REG32(ADR_CONTROL)) & 0x00000004 ) >> 2)
++#define GET_AUTO_SEQNO (((REG32(ADR_CONTROL)) & 0x00000008 ) >> 3)
++#define GET_BYPASSS_TX_PARSER_ENCAP (((REG32(ADR_CONTROL)) & 0x00000010 ) >> 4)
++#define GET_HDR_STRIP (((REG32(ADR_CONTROL)) & 0x00000020 ) >> 5)
++#define GET_ERP_PROTECT (((REG32(ADR_CONTROL)) & 0x000000c0 ) >> 6)
++#define GET_PRO_VER (((REG32(ADR_CONTROL)) & 0x00000300 ) >> 8)
++#define GET_TXQ_ID0 (((REG32(ADR_CONTROL)) & 0x00007000 ) >> 12)
++#define GET_TXQ_ID1 (((REG32(ADR_CONTROL)) & 0x00070000 ) >> 16)
++#define GET_TX_ETHER_TRAP_EN (((REG32(ADR_CONTROL)) & 0x00100000 ) >> 20)
++#define GET_RX_ETHER_TRAP_EN (((REG32(ADR_CONTROL)) & 0x00200000 ) >> 21)
++#define GET_RX_NULL_TRAP_EN (((REG32(ADR_CONTROL)) & 0x00400000 ) >> 22)
++#define GET_RX_GET_TX_QUEUE_EN (((REG32(ADR_CONTROL)) & 0x02000000 ) >> 25)
++#define GET_HCI_INQ_SEL (((REG32(ADR_CONTROL)) & 0x04000000 ) >> 26)
++#define GET_TRX_DEBUG_CNT_ENA (((REG32(ADR_CONTROL)) & 0x10000000 ) >> 28)
++#define GET_WAKE_SOON_WITH_SCK (((REG32(ADR_SDIO_WAKE_MODE)) & 0x00000001 ) >> 0)
++#define GET_TX_FLOW_CTRL (((REG32(ADR_TX_FLOW_0)) & 0x0000ffff ) >> 0)
++#define GET_TX_FLOW_MGMT (((REG32(ADR_TX_FLOW_0)) & 0xffff0000 ) >> 16)
++#define GET_TX_FLOW_DATA (((REG32(ADR_TX_FLOW_1)) & 0xffffffff ) >> 0)
++#define GET_DOT11RTSTHRESHOLD (((REG32(ADR_THREASHOLD)) & 0xffff0000 ) >> 16)
++#define GET_TXF_ID (((REG32(ADR_TXFID_INCREASE)) & 0x0000003f ) >> 0)
++#define GET_SEQ_CTRL (((REG32(ADR_GLOBAL_SEQUENCE)) & 0x0000ffff ) >> 0)
++#define GET_TX_PBOFFSET (((REG32(ADR_HCI_TX_RX_INFO_SIZE)) & 0x000000ff ) >> 0)
++#define GET_TX_INFO_SIZE (((REG32(ADR_HCI_TX_RX_INFO_SIZE)) & 0x0000ff00 ) >> 8)
++#define GET_RX_INFO_SIZE (((REG32(ADR_HCI_TX_RX_INFO_SIZE)) & 0x00ff0000 ) >> 16)
++#define GET_RX_LAST_PHY_SIZE (((REG32(ADR_HCI_TX_RX_INFO_SIZE)) & 0xff000000 ) >> 24)
++#define GET_TX_INFO_CLEAR_SIZE (((REG32(ADR_HCI_TX_INFO_CLEAR)) & 0x0000003f ) >> 0)
++#define GET_TX_INFO_CLEAR_ENABLE (((REG32(ADR_HCI_TX_INFO_CLEAR)) & 0x00000100 ) >> 8)
++#define GET_TXTRAP_ETHTYPE1 (((REG32(ADR_TX_ETHER_TYPE_1)) & 0x0000ffff ) >> 0)
++#define GET_TXTRAP_ETHTYPE0 (((REG32(ADR_TX_ETHER_TYPE_1)) & 0xffff0000 ) >> 16)
++#define GET_RXTRAP_ETHTYPE1 (((REG32(ADR_RX_ETHER_TYPE_1)) & 0x0000ffff ) >> 0)
++#define GET_RXTRAP_ETHTYPE0 (((REG32(ADR_RX_ETHER_TYPE_1)) & 0xffff0000 ) >> 16)
++#define GET_TX_PKT_COUNTER (((REG32(ADR_PACKET_COUNTER_INFO_0)) & 0xffffffff ) >> 0)
++#define GET_RX_PKT_COUNTER (((REG32(ADR_PACKET_COUNTER_INFO_1)) & 0xffffffff ) >> 0)
++#define GET_HOST_CMD_COUNTER (((REG32(ADR_PACKET_COUNTER_INFO_2)) & 0x000000ff ) >> 0)
++#define GET_HOST_EVENT_COUNTER (((REG32(ADR_PACKET_COUNTER_INFO_3)) & 0x000000ff ) >> 0)
++#define GET_TX_PKT_DROP_COUNTER (((REG32(ADR_PACKET_COUNTER_INFO_4)) & 0x000000ff ) >> 0)
++#define GET_RX_PKT_DROP_COUNTER (((REG32(ADR_PACKET_COUNTER_INFO_5)) & 0x000000ff ) >> 0)
++#define GET_TX_PKT_TRAP_COUNTER (((REG32(ADR_PACKET_COUNTER_INFO_6)) & 0x000000ff ) >> 0)
++#define GET_RX_PKT_TRAP_COUNTER (((REG32(ADR_PACKET_COUNTER_INFO_7)) & 0x000000ff ) >> 0)
++#define GET_HOST_TX_FAIL_COUNTER (((REG32(ADR_SDIO_TX_RX_FAIL_COUNTER_0)) & 0x000000ff ) >> 0)
++#define GET_HOST_RX_FAIL_COUNTER (((REG32(ADR_SDIO_TX_RX_FAIL_COUNTER_1)) & 0x000000ff ) >> 0)
++#define GET_HCI_STATE_MONITOR (((REG32(ADR_HCI_STATE_DEBUG_MODE_0)) & 0xffffffff ) >> 0)
++#define GET_HCI_ST_TIMEOUT_MONITOR (((REG32(ADR_HCI_STATE_DEBUG_MODE_1)) & 0xffffffff ) >> 0)
++#define GET_TX_ON_DEMAND_LENGTH (((REG32(ADR_HCI_STATE_DEBUG_MODE_2)) & 0xffffffff ) >> 0)
++#define GET_HCI_MONITOR_REG1 (((REG32(ADR_HCI_STATE_DEBUG_MODE_3)) & 0xffffffff ) >> 0)
++#define GET_HCI_MONITOR_REG2 (((REG32(ADR_HCI_STATE_DEBUG_MODE_4)) & 0xffffffff ) >> 0)
++#define GET_HCI_TX_ALLOC_TIME_31_0 (((REG32(ADR_HCI_STATE_DEBUG_MODE_5)) & 0xffffffff ) >> 0)
++#define GET_HCI_TX_ALLOC_TIME_47_32 (((REG32(ADR_HCI_STATE_DEBUG_MODE_6)) & 0x0000ffff ) >> 0)
++#define GET_HCI_MB_MAX_CNT (((REG32(ADR_HCI_STATE_DEBUG_MODE_6)) & 0x00ff0000 ) >> 16)
++#define GET_HCI_TX_ALLOC_CNT_31_0 (((REG32(ADR_HCI_STATE_DEBUG_MODE_7)) & 0xffffffff ) >> 0)
++#define GET_HCI_TX_ALLOC_CNT_47_32 (((REG32(ADR_HCI_STATE_DEBUG_MODE_8)) & 0x0000ffff ) >> 0)
++#define GET_HCI_PROC_CNT (((REG32(ADR_HCI_STATE_DEBUG_MODE_8)) & 0x00ff0000 ) >> 16)
++#define GET_SDIO_TRANS_CNT (((REG32(ADR_HCI_STATE_DEBUG_MODE_8)) & 0xff000000 ) >> 24)
++#define GET_SDIO_TX_INVALID_CNT_31_0 (((REG32(ADR_HCI_STATE_DEBUG_MODE_9)) & 0xffffffff ) >> 0)
++#define GET_SDIO_TX_INVALID_CNT_47_32 (((REG32(ADR_HCI_STATE_DEBUG_MODE_10)) & 0x0000ffff ) >> 0)
++#define GET_CS_START_ADDR (((REG32(ADR_CS_START_ADDR)) & 0x0000ffff ) >> 0)
++#define GET_CS_PKT_ID (((REG32(ADR_CS_START_ADDR)) & 0x007f0000 ) >> 16)
++#define GET_ADD_LEN (((REG32(ADR_CS_ADD_LEN)) & 0x0000ffff ) >> 0)
++#define GET_CS_ADDER_EN (((REG32(ADR_CS_CMD)) & 0x00000001 ) >> 0)
++#define GET_PSEUDO (((REG32(ADR_CS_CMD)) & 0x00000002 ) >> 1)
++#define GET_CALCULATE (((REG32(ADR_CS_INI_BUF)) & 0xffffffff ) >> 0)
++#define GET_L4_LEN (((REG32(ADR_CS_PSEUDO_BUF)) & 0x0000ffff ) >> 0)
++#define GET_L4_PROTOL (((REG32(ADR_CS_PSEUDO_BUF)) & 0x00ff0000 ) >> 16)
++#define GET_CHECK_SUM (((REG32(ADR_CS_CHECK_SUM)) & 0x0000ffff ) >> 0)
++#define GET_RAND_EN (((REG32(ADR_RAND_EN)) & 0x00000001 ) >> 0)
++#define GET_RAND_NUM (((REG32(ADR_RAND_NUM)) & 0xffffffff ) >> 0)
++#define GET_MUL_OP1 (((REG32(ADR_MUL_OP1)) & 0xffffffff ) >> 0)
++#define GET_MUL_OP2 (((REG32(ADR_MUL_OP2)) & 0xffffffff ) >> 0)
++#define GET_MUL_ANS0 (((REG32(ADR_MUL_ANS0)) & 0xffffffff ) >> 0)
++#define GET_MUL_ANS1 (((REG32(ADR_MUL_ANS1)) & 0xffffffff ) >> 0)
++#define GET_RD_ADDR (((REG32(ADR_DMA_RDATA)) & 0x0000ffff ) >> 0)
++#define GET_RD_ID (((REG32(ADR_DMA_RDATA)) & 0x007f0000 ) >> 16)
++#define GET_WR_ADDR (((REG32(ADR_DMA_WDATA)) & 0x0000ffff ) >> 0)
++#define GET_WR_ID (((REG32(ADR_DMA_WDATA)) & 0x007f0000 ) >> 16)
++#define GET_LEN (((REG32(ADR_DMA_LEN)) & 0x0000ffff ) >> 0)
++#define GET_CLR (((REG32(ADR_DMA_CLR)) & 0x00000001 ) >> 0)
++#define GET_PHY_MODE (((REG32(ADR_NAV_DATA)) & 0x00000003 ) >> 0)
++#define GET_SHRT_PREAM (((REG32(ADR_NAV_DATA)) & 0x00000004 ) >> 2)
++#define GET_SHRT_GI (((REG32(ADR_NAV_DATA)) & 0x00000008 ) >> 3)
++#define GET_DATA_RATE (((REG32(ADR_NAV_DATA)) & 0x000007f0 ) >> 4)
++#define GET_MCS (((REG32(ADR_NAV_DATA)) & 0x00007000 ) >> 12)
++#define GET_FRAME_LEN (((REG32(ADR_NAV_DATA)) & 0xffff0000 ) >> 16)
++#define GET_DURATION (((REG32(ADR_CO_NAV)) & 0x0000ffff ) >> 0)
++#define GET_SHA_DST_ADDR (((REG32(ADR_SHA_DST_ADDR)) & 0xffffffff ) >> 0)
++#define GET_SHA_SRC_ADDR (((REG32(ADR_SHA_SRC_ADDR)) & 0xffffffff ) >> 0)
++#define GET_SHA_BUSY (((REG32(ADR_SHA_SETTING)) & 0x00000001 ) >> 0)
++#define GET_SHA_ENDIAN (((REG32(ADR_SHA_SETTING)) & 0x00000002 ) >> 1)
++#define GET_EFS_CLKFREQ (((REG32(ADR_EFUSE_CLK_FREQ)) & 0x00000fff ) >> 0)
++#define GET_LOW_ACTIVE (((REG32(ADR_EFUSE_CLK_FREQ)) & 0x00010000 ) >> 16)
++#define GET_EFS_CLKFREQ_RD (((REG32(ADR_EFUSE_CLK_FREQ)) & 0x0ff00000 ) >> 20)
++#define GET_EFS_PRE_RD (((REG32(ADR_EFUSE_CLK_FREQ)) & 0xf0000000 ) >> 28)
++#define GET_EFS_LDO_ON (((REG32(ADR_EFUSE_LDO_TIME)) & 0x0000ffff ) >> 0)
++#define GET_EFS_LDO_OFF (((REG32(ADR_EFUSE_LDO_TIME)) & 0xffff0000 ) >> 16)
++#define GET_EFS_RDATA_0 (((REG32(ADR_EFUSE_AHB_RDATA_0)) & 0xffffffff ) >> 0)
++#define GET_EFS_WDATA_0 (((REG32(ADR_EFUSE_WDATA_0)) & 0xffffffff ) >> 0)
++#define GET_EFS_RDATA_1 (((REG32(ADR_EFUSE_AHB_RDATA_1)) & 0xffffffff ) >> 0)
++#define GET_EFS_WDATA_1 (((REG32(ADR_EFUSE_WDATA_1)) & 0xffffffff ) >> 0)
++#define GET_EFS_RDATA_2 (((REG32(ADR_EFUSE_AHB_RDATA_2)) & 0xffffffff ) >> 0)
++#define GET_EFS_WDATA_2 (((REG32(ADR_EFUSE_WDATA_2)) & 0xffffffff ) >> 0)
++#define GET_EFS_RDATA_3 (((REG32(ADR_EFUSE_AHB_RDATA_3)) & 0xffffffff ) >> 0)
++#define GET_EFS_WDATA_3 (((REG32(ADR_EFUSE_WDATA_3)) & 0xffffffff ) >> 0)
++#define GET_EFS_RDATA_4 (((REG32(ADR_EFUSE_AHB_RDATA_4)) & 0xffffffff ) >> 0)
++#define GET_EFS_WDATA_4 (((REG32(ADR_EFUSE_WDATA_4)) & 0xffffffff ) >> 0)
++#define GET_EFS_RDATA_5 (((REG32(ADR_EFUSE_AHB_RDATA_5)) & 0xffffffff ) >> 0)
++#define GET_EFS_WDATA_5 (((REG32(ADR_EFUSE_WDATA_5)) & 0xffffffff ) >> 0)
++#define GET_EFS_RDATA_6 (((REG32(ADR_EFUSE_AHB_RDATA_6)) & 0xffffffff ) >> 0)
++#define GET_EFS_WDATA_6 (((REG32(ADR_EFUSE_WDATA_6)) & 0xffffffff ) >> 0)
++#define GET_EFS_RDATA_7 (((REG32(ADR_EFUSE_AHB_RDATA_7)) & 0xffffffff ) >> 0)
++#define GET_EFS_WDATA_7 (((REG32(ADR_EFUSE_WDATA_7)) & 0xffffffff ) >> 0)
++#define GET_EFS_SPI_RD0_EN (((REG32(ADR_EFUSE_SPI_RD0_EN)) & 0x00000001 ) >> 0)
++#define GET_EFS_SPI_RD1_EN (((REG32(ADR_EFUSE_SPI_RD1_EN)) & 0x00000001 ) >> 0)
++#define GET_EFS_SPI_RD2_EN (((REG32(ADR_EFUSE_SPI_RD2_EN)) & 0x00000001 ) >> 0)
++#define GET_EFS_SPI_RD3_EN (((REG32(ADR_EFUSE_SPI_RD3_EN)) & 0x00000001 ) >> 0)
++#define GET_EFS_SPI_RD4_EN (((REG32(ADR_EFUSE_SPI_RD4_EN)) & 0x00000001 ) >> 0)
++#define GET_EFS_SPI_RD5_EN (((REG32(ADR_EFUSE_SPI_RD5_EN)) & 0x00000001 ) >> 0)
++#define GET_EFS_SPI_RD6_EN (((REG32(ADR_EFUSE_SPI_RD6_EN)) & 0x00000001 ) >> 0)
++#define GET_EFS_SPI_RD7_EN (((REG32(ADR_EFUSE_SPI_RD7_EN)) & 0x00000001 ) >> 0)
++#define GET_EFS_SPI_RBUSY (((REG32(ADR_EFUSE_SPI_BUSY)) & 0x00000001 ) >> 0)
++#define GET_EFS_SPI_RDATA_0 (((REG32(ADR_EFUSE_SPI_RDATA_0)) & 0xffffffff ) >> 0)
++#define GET_EFS_SPI_RDATA_1 (((REG32(ADR_EFUSE_SPI_RDATA_1)) & 0xffffffff ) >> 0)
++#define GET_EFS_SPI_RDATA_2 (((REG32(ADR_EFUSE_SPI_RDATA_2)) & 0xffffffff ) >> 0)
++#define GET_EFS_SPI_RDATA_3 (((REG32(ADR_EFUSE_SPI_RDATA_3)) & 0xffffffff ) >> 0)
++#define GET_EFS_SPI_RDATA_4 (((REG32(ADR_EFUSE_SPI_RDATA_4)) & 0xffffffff ) >> 0)
++#define GET_EFS_SPI_RDATA_5 (((REG32(ADR_EFUSE_SPI_RDATA_5)) & 0xffffffff ) >> 0)
++#define GET_EFS_SPI_RDATA_6 (((REG32(ADR_EFUSE_SPI_RDATA_6)) & 0xffffffff ) >> 0)
++#define GET_EFS_SPI_RDATA_7 (((REG32(ADR_EFUSE_SPI_RDATA_7)) & 0xffffffff ) >> 0)
++#define GET_GET_RK (((REG32(ADR_SMS4_CFG1)) & 0x00000001 ) >> 0)
++#define GET_FORCE_GET_RK (((REG32(ADR_SMS4_CFG1)) & 0x00000002 ) >> 1)
++#define GET_SMS4_DESCRY_EN (((REG32(ADR_SMS4_CFG1)) & 0x00000010 ) >> 4)
++#define GET_DEC_DOUT_MSB (((REG32(ADR_SMS4_CFG2)) & 0x00000001 ) >> 0)
++#define GET_DEC_DIN_MSB (((REG32(ADR_SMS4_CFG2)) & 0x00000002 ) >> 1)
++#define GET_ENC_DOUT_MSB (((REG32(ADR_SMS4_CFG2)) & 0x00000004 ) >> 2)
++#define GET_ENC_DIN_MSB (((REG32(ADR_SMS4_CFG2)) & 0x00000008 ) >> 3)
++#define GET_KEY_DIN_MSB (((REG32(ADR_SMS4_CFG2)) & 0x00000010 ) >> 4)
++#define GET_SMS4_CBC_EN (((REG32(ADR_SMS4_MODE1)) & 0x00000001 ) >> 0)
++#define GET_SMS4_CFB_EN (((REG32(ADR_SMS4_MODE1)) & 0x00000002 ) >> 1)
++#define GET_SMS4_OFB_EN (((REG32(ADR_SMS4_MODE1)) & 0x00000004 ) >> 2)
++#define GET_SMS4_START_TRIG (((REG32(ADR_SMS4_TRIG)) & 0x00000001 ) >> 0)
++#define GET_SMS4_BUSY (((REG32(ADR_SMS4_STATUS1)) & 0x00000001 ) >> 0)
++#define GET_SMS4_DONE (((REG32(ADR_SMS4_STATUS2)) & 0x00000001 ) >> 0)
++#define GET_SMS4_DATAIN_0 (((REG32(ADR_SMS4_DATA_IN0)) & 0xffffffff ) >> 0)
++#define GET_SMS4_DATAIN_1 (((REG32(ADR_SMS4_DATA_IN1)) & 0xffffffff ) >> 0)
++#define GET_SMS4_DATAIN_2 (((REG32(ADR_SMS4_DATA_IN2)) & 0xffffffff ) >> 0)
++#define GET_SMS4_DATAIN_3 (((REG32(ADR_SMS4_DATA_IN3)) & 0xffffffff ) >> 0)
++#define GET_SMS4_DATAOUT_0 (((REG32(ADR_SMS4_DATA_OUT0)) & 0xffffffff ) >> 0)
++#define GET_SMS4_DATAOUT_1 (((REG32(ADR_SMS4_DATA_OUT1)) & 0xffffffff ) >> 0)
++#define GET_SMS4_DATAOUT_2 (((REG32(ADR_SMS4_DATA_OUT2)) & 0xffffffff ) >> 0)
++#define GET_SMS4_DATAOUT_3 (((REG32(ADR_SMS4_DATA_OUT3)) & 0xffffffff ) >> 0)
++#define GET_SMS4_KEY_0 (((REG32(ADR_SMS4_KEY_0)) & 0xffffffff ) >> 0)
++#define GET_SMS4_KEY_1 (((REG32(ADR_SMS4_KEY_1)) & 0xffffffff ) >> 0)
++#define GET_SMS4_KEY_2 (((REG32(ADR_SMS4_KEY_2)) & 0xffffffff ) >> 0)
++#define GET_SMS4_KEY_3 (((REG32(ADR_SMS4_KEY_3)) & 0xffffffff ) >> 0)
++#define GET_SMS4_MODE_IV0 (((REG32(ADR_SMS4_MODE_IV0)) & 0xffffffff ) >> 0)
++#define GET_SMS4_MODE_IV1 (((REG32(ADR_SMS4_MODE_IV1)) & 0xffffffff ) >> 0)
++#define GET_SMS4_MODE_IV2 (((REG32(ADR_SMS4_MODE_IV2)) & 0xffffffff ) >> 0)
++#define GET_SMS4_MODE_IV3 (((REG32(ADR_SMS4_MODE_IV3)) & 0xffffffff ) >> 0)
++#define GET_SMS4_OFB_ENC0 (((REG32(ADR_SMS4_OFB_ENC0)) & 0xffffffff ) >> 0)
++#define GET_SMS4_OFB_ENC1 (((REG32(ADR_SMS4_OFB_ENC1)) & 0xffffffff ) >> 0)
++#define GET_SMS4_OFB_ENC2 (((REG32(ADR_SMS4_OFB_ENC2)) & 0xffffffff ) >> 0)
++#define GET_SMS4_OFB_ENC3 (((REG32(ADR_SMS4_OFB_ENC3)) & 0xffffffff ) >> 0)
++#define GET_MRX_MCAST_TB0_31_0 (((REG32(ADR_MRX_MCAST_TB0_0)) & 0xffffffff ) >> 0)
++#define GET_MRX_MCAST_TB0_47_32 (((REG32(ADR_MRX_MCAST_TB0_1)) & 0x0000ffff ) >> 0)
++#define GET_MRX_MCAST_MASK0_31_0 (((REG32(ADR_MRX_MCAST_MK0_0)) & 0xffffffff ) >> 0)
++#define GET_MRX_MCAST_MASK0_47_32 (((REG32(ADR_MRX_MCAST_MK0_1)) & 0x0000ffff ) >> 0)
++#define GET_MRX_MCAST_CTRL_0 (((REG32(ADR_MRX_MCAST_CTRL0)) & 0x00000003 ) >> 0)
++#define GET_MRX_MCAST_TB1_31_0 (((REG32(ADR_MRX_MCAST_TB1_0)) & 0xffffffff ) >> 0)
++#define GET_MRX_MCAST_TB1_47_32 (((REG32(ADR_MRX_MCAST_TB1_1)) & 0x0000ffff ) >> 0)
++#define GET_MRX_MCAST_MASK1_31_0 (((REG32(ADR_MRX_MCAST_MK1_0)) & 0xffffffff ) >> 0)
++#define GET_MRX_MCAST_MASK1_47_32 (((REG32(ADR_MRX_MCAST_MK1_1)) & 0x0000ffff ) >> 0)
++#define GET_MRX_MCAST_CTRL_1 (((REG32(ADR_MRX_MCAST_CTRL1)) & 0x00000003 ) >> 0)
++#define GET_MRX_MCAST_TB2_31_0 (((REG32(ADR_MRX_MCAST_TB2_0)) & 0xffffffff ) >> 0)
++#define GET_MRX_MCAST_TB2_47_32 (((REG32(ADR_MRX_MCAST_TB2_1)) & 0x0000ffff ) >> 0)
++#define GET_MRX_MCAST_MASK2_31_0 (((REG32(ADR_MRX_MCAST_MK2_0)) & 0xffffffff ) >> 0)
++#define GET_MRX_MCAST_MASK2_47_32 (((REG32(ADR_MRX_MCAST_MK2_1)) & 0x0000ffff ) >> 0)
++#define GET_MRX_MCAST_CTRL_2 (((REG32(ADR_MRX_MCAST_CTRL2)) & 0x00000003 ) >> 0)
++#define GET_MRX_MCAST_TB3_31_0 (((REG32(ADR_MRX_MCAST_TB3_0)) & 0xffffffff ) >> 0)
++#define GET_MRX_MCAST_TB3_47_32 (((REG32(ADR_MRX_MCAST_TB3_1)) & 0x0000ffff ) >> 0)
++#define GET_MRX_MCAST_MASK3_31_0 (((REG32(ADR_MRX_MCAST_MK3_0)) & 0xffffffff ) >> 0)
++#define GET_MRX_MCAST_MASK3_47_32 (((REG32(ADR_MRX_MCAST_MK3_1)) & 0x0000ffff ) >> 0)
++#define GET_MRX_MCAST_CTRL_3 (((REG32(ADR_MRX_MCAST_CTRL3)) & 0x00000003 ) >> 0)
++#define GET_MRX_PHY_INFO (((REG32(ADR_MRX_PHY_INFO)) & 0xffffffff ) >> 0)
++#define GET_DBG_BA_TYPE (((REG32(ADR_MRX_BA_DBG)) & 0x0000003f ) >> 0)
++#define GET_DBG_BA_SEQ (((REG32(ADR_MRX_BA_DBG)) & 0x000fff00 ) >> 8)
++#define GET_MRX_FLT_TB0 (((REG32(ADR_MRX_FLT_TB0)) & 0x00007fff ) >> 0)
++#define GET_MRX_FLT_TB1 (((REG32(ADR_MRX_FLT_TB1)) & 0x00007fff ) >> 0)
++#define GET_MRX_FLT_TB2 (((REG32(ADR_MRX_FLT_TB2)) & 0x00007fff ) >> 0)
++#define GET_MRX_FLT_TB3 (((REG32(ADR_MRX_FLT_TB3)) & 0x00007fff ) >> 0)
++#define GET_MRX_FLT_TB4 (((REG32(ADR_MRX_FLT_TB4)) & 0x00007fff ) >> 0)
++#define GET_MRX_FLT_TB5 (((REG32(ADR_MRX_FLT_TB5)) & 0x00007fff ) >> 0)
++#define GET_MRX_FLT_TB6 (((REG32(ADR_MRX_FLT_TB6)) & 0x00007fff ) >> 0)
++#define GET_MRX_FLT_TB7 (((REG32(ADR_MRX_FLT_TB7)) & 0x00007fff ) >> 0)
++#define GET_MRX_FLT_TB8 (((REG32(ADR_MRX_FLT_TB8)) & 0x00007fff ) >> 0)
++#define GET_MRX_FLT_TB9 (((REG32(ADR_MRX_FLT_TB9)) & 0x00007fff ) >> 0)
++#define GET_MRX_FLT_TB10 (((REG32(ADR_MRX_FLT_TB10)) & 0x00007fff ) >> 0)
++#define GET_MRX_FLT_TB11 (((REG32(ADR_MRX_FLT_TB11)) & 0x00007fff ) >> 0)
++#define GET_MRX_FLT_TB12 (((REG32(ADR_MRX_FLT_TB12)) & 0x00007fff ) >> 0)
++#define GET_MRX_FLT_TB13 (((REG32(ADR_MRX_FLT_TB13)) & 0x00007fff ) >> 0)
++#define GET_MRX_FLT_TB14 (((REG32(ADR_MRX_FLT_TB14)) & 0x00007fff ) >> 0)
++#define GET_MRX_FLT_TB15 (((REG32(ADR_MRX_FLT_TB15)) & 0x00007fff ) >> 0)
++#define GET_MRX_FLT_EN0 (((REG32(ADR_MRX_FLT_EN0)) & 0x0000ffff ) >> 0)
++#define GET_MRX_FLT_EN1 (((REG32(ADR_MRX_FLT_EN1)) & 0x0000ffff ) >> 0)
++#define GET_MRX_FLT_EN2 (((REG32(ADR_MRX_FLT_EN2)) & 0x0000ffff ) >> 0)
++#define GET_MRX_FLT_EN3 (((REG32(ADR_MRX_FLT_EN3)) & 0x0000ffff ) >> 0)
++#define GET_MRX_FLT_EN4 (((REG32(ADR_MRX_FLT_EN4)) & 0x0000ffff ) >> 0)
++#define GET_MRX_FLT_EN5 (((REG32(ADR_MRX_FLT_EN5)) & 0x0000ffff ) >> 0)
++#define GET_MRX_FLT_EN6 (((REG32(ADR_MRX_FLT_EN6)) & 0x0000ffff ) >> 0)
++#define GET_MRX_FLT_EN7 (((REG32(ADR_MRX_FLT_EN7)) & 0x0000ffff ) >> 0)
++#define GET_MRX_FLT_EN8 (((REG32(ADR_MRX_FLT_EN8)) & 0x0000ffff ) >> 0)
++#define GET_MRX_LEN_FLT (((REG32(ADR_MRX_LEN_FLT)) & 0x0000ffff ) >> 0)
++#define GET_RX_FLOW_DATA (((REG32(ADR_RX_FLOW_DATA)) & 0xffffffff ) >> 0)
++#define GET_RX_FLOW_MNG (((REG32(ADR_RX_FLOW_MNG)) & 0x0000ffff ) >> 0)
++#define GET_RX_FLOW_CTRL (((REG32(ADR_RX_FLOW_CTRL)) & 0x0000ffff ) >> 0)
++#define GET_MRX_STP_EN (((REG32(ADR_RX_TIME_STAMP_CFG)) & 0x00000001 ) >> 0)
++#define GET_MRX_STP_OFST (((REG32(ADR_RX_TIME_STAMP_CFG)) & 0x0000ff00 ) >> 8)
++#define GET_DBG_FF_FULL (((REG32(ADR_DBG_FF_FULL)) & 0x0000ffff ) >> 0)
++#define GET_DBG_FF_FULL_CLR (((REG32(ADR_DBG_FF_FULL)) & 0x80000000 ) >> 31)
++#define GET_DBG_WFF_FULL (((REG32(ADR_DBG_WFF_FULL)) & 0x0000ffff ) >> 0)
++#define GET_DBG_WFF_FULL_CLR (((REG32(ADR_DBG_WFF_FULL)) & 0x80000000 ) >> 31)
++#define GET_DBG_MB_FULL (((REG32(ADR_DBG_MB_FULL)) & 0x0000ffff ) >> 0)
++#define GET_DBG_MB_FULL_CLR (((REG32(ADR_DBG_MB_FULL)) & 0x80000000 ) >> 31)
++#define GET_BA_CTRL (((REG32(ADR_BA_CTRL)) & 0x00000003 ) >> 0)
++#define GET_BA_DBG_EN (((REG32(ADR_BA_CTRL)) & 0x00000004 ) >> 2)
++#define GET_BA_AGRE_EN (((REG32(ADR_BA_CTRL)) & 0x00000008 ) >> 3)
++#define GET_BA_TA_31_0 (((REG32(ADR_BA_TA_0)) & 0xffffffff ) >> 0)
++#define GET_BA_TA_47_32 (((REG32(ADR_BA_TA_1)) & 0x0000ffff ) >> 0)
++#define GET_BA_TID (((REG32(ADR_BA_TID)) & 0x0000000f ) >> 0)
++#define GET_BA_ST_SEQ (((REG32(ADR_BA_ST_SEQ)) & 0x00000fff ) >> 0)
++#define GET_BA_SB0 (((REG32(ADR_BA_SB0)) & 0xffffffff ) >> 0)
++#define GET_BA_SB1 (((REG32(ADR_BA_SB1)) & 0xffffffff ) >> 0)
++#define GET_MRX_WD (((REG32(ADR_MRX_WATCH_DOG)) & 0x0001ffff ) >> 0)
++#define GET_ACK_GEN_EN (((REG32(ADR_ACK_GEN_EN)) & 0x00000001 ) >> 0)
++#define GET_BA_GEN_EN (((REG32(ADR_ACK_GEN_EN)) & 0x00000002 ) >> 1)
++#define GET_ACK_GEN_DUR (((REG32(ADR_ACK_GEN_PARA)) & 0x0000ffff ) >> 0)
++#define GET_ACK_GEN_INFO (((REG32(ADR_ACK_GEN_PARA)) & 0x003f0000 ) >> 16)
++#define GET_ACK_GEN_RA_31_0 (((REG32(ADR_ACK_GEN_RA_0)) & 0xffffffff ) >> 0)
++#define GET_ACK_GEN_RA_47_32 (((REG32(ADR_ACK_GEN_RA_1)) & 0x0000ffff ) >> 0)
++#define GET_MIB_LEN_FAIL (((REG32(ADR_MIB_LEN_FAIL)) & 0x0000ffff ) >> 0)
++#define GET_TRAP_HW_ID (((REG32(ADR_TRAP_HW_ID)) & 0x0000000f ) >> 0)
++#define GET_ID_IN_USE (((REG32(ADR_ID_IN_USE)) & 0x000000ff ) >> 0)
++#define GET_MRX_ERR (((REG32(ADR_MRX_ERR)) & 0xffffffff ) >> 0)
++#define GET_W0_T0_SEQ (((REG32(ADR_WSID0_TID0_RX_SEQ)) & 0x0000ffff ) >> 0)
++#define GET_W0_T1_SEQ (((REG32(ADR_WSID0_TID1_RX_SEQ)) & 0x0000ffff ) >> 0)
++#define GET_W0_T2_SEQ (((REG32(ADR_WSID0_TID2_RX_SEQ)) & 0x0000ffff ) >> 0)
++#define GET_W0_T3_SEQ (((REG32(ADR_WSID0_TID3_RX_SEQ)) & 0x0000ffff ) >> 0)
++#define GET_W0_T4_SEQ (((REG32(ADR_WSID0_TID4_RX_SEQ)) & 0x0000ffff ) >> 0)
++#define GET_W0_T5_SEQ (((REG32(ADR_WSID0_TID5_RX_SEQ)) & 0x0000ffff ) >> 0)
++#define GET_W0_T6_SEQ (((REG32(ADR_WSID0_TID6_RX_SEQ)) & 0x0000ffff ) >> 0)
++#define GET_W0_T7_SEQ (((REG32(ADR_WSID0_TID7_RX_SEQ)) & 0x0000ffff ) >> 0)
++#define GET_W1_T0_SEQ (((REG32(ADR_WSID1_TID0_RX_SEQ)) & 0x0000ffff ) >> 0)
++#define GET_W1_T1_SEQ (((REG32(ADR_WSID1_TID1_RX_SEQ)) & 0x0000ffff ) >> 0)
++#define GET_W1_T2_SEQ (((REG32(ADR_WSID1_TID2_RX_SEQ)) & 0x0000ffff ) >> 0)
++#define GET_W1_T3_SEQ (((REG32(ADR_WSID1_TID3_RX_SEQ)) & 0x0000ffff ) >> 0)
++#define GET_W1_T4_SEQ (((REG32(ADR_WSID1_TID4_RX_SEQ)) & 0x0000ffff ) >> 0)
++#define GET_W1_T5_SEQ (((REG32(ADR_WSID1_TID5_RX_SEQ)) & 0x0000ffff ) >> 0)
++#define GET_W1_T6_SEQ (((REG32(ADR_WSID1_TID6_RX_SEQ)) & 0x0000ffff ) >> 0)
++#define GET_W1_T7_SEQ (((REG32(ADR_WSID1_TID7_RX_SEQ)) & 0x0000ffff ) >> 0)
++#define GET_ADDR1A_SEL (((REG32(ADR_HDR_ADDR_SEL)) & 0x00000003 ) >> 0)
++#define GET_ADDR2A_SEL (((REG32(ADR_HDR_ADDR_SEL)) & 0x0000000c ) >> 2)
++#define GET_ADDR3A_SEL (((REG32(ADR_HDR_ADDR_SEL)) & 0x00000030 ) >> 4)
++#define GET_ADDR1B_SEL (((REG32(ADR_HDR_ADDR_SEL)) & 0x000000c0 ) >> 6)
++#define GET_ADDR2B_SEL (((REG32(ADR_HDR_ADDR_SEL)) & 0x00000300 ) >> 8)
++#define GET_ADDR3B_SEL (((REG32(ADR_HDR_ADDR_SEL)) & 0x00000c00 ) >> 10)
++#define GET_ADDR3C_SEL (((REG32(ADR_HDR_ADDR_SEL)) & 0x00003000 ) >> 12)
++#define GET_FRM_CTRL (((REG32(ADR_FRAME_TYPE_CNTR_SET)) & 0x0000003f ) >> 0)
++#define GET_CSR_PHY_INFO (((REG32(ADR_PHY_INFO)) & 0x00007fff ) >> 0)
++#define GET_AMPDU_SIG (((REG32(ADR_AMPDU_SIG)) & 0x000000ff ) >> 0)
++#define GET_MIB_AMPDU (((REG32(ADR_MIB_AMPDU)) & 0xffffffff ) >> 0)
++#define GET_LEN_FLT (((REG32(ADR_LEN_FLT)) & 0x0000ffff ) >> 0)
++#define GET_MIB_DELIMITER (((REG32(ADR_MIB_DELIMITER)) & 0x0000ffff ) >> 0)
++#define GET_MTX_INT_Q0_Q_EMPTY (((REG32(ADR_MTX_INT_STS)) & 0x00010000 ) >> 16)
++#define GET_MTX_INT_Q0_TXOP_RUNOUT (((REG32(ADR_MTX_INT_STS)) & 0x00020000 ) >> 17)
++#define GET_MTX_INT_Q1_Q_EMPTY (((REG32(ADR_MTX_INT_STS)) & 0x00040000 ) >> 18)
++#define GET_MTX_INT_Q1_TXOP_RUNOUT (((REG32(ADR_MTX_INT_STS)) & 0x00080000 ) >> 19)
++#define GET_MTX_INT_Q2_Q_EMPTY (((REG32(ADR_MTX_INT_STS)) & 0x00100000 ) >> 20)
++#define GET_MTX_INT_Q2_TXOP_RUNOUT (((REG32(ADR_MTX_INT_STS)) & 0x00200000 ) >> 21)
++#define GET_MTX_INT_Q3_Q_EMPTY (((REG32(ADR_MTX_INT_STS)) & 0x00400000 ) >> 22)
++#define GET_MTX_INT_Q3_TXOP_RUNOUT (((REG32(ADR_MTX_INT_STS)) & 0x00800000 ) >> 23)
++#define GET_MTX_INT_Q4_Q_EMPTY (((REG32(ADR_MTX_INT_STS)) & 0x01000000 ) >> 24)
++#define GET_MTX_INT_Q4_TXOP_RUNOUT (((REG32(ADR_MTX_INT_STS)) & 0x02000000 ) >> 25)
++#define GET_MTX_EN_INT_Q0_Q_EMPTY (((REG32(ADR_MTX_INT_EN)) & 0x00010000 ) >> 16)
++#define GET_MTX_EN_INT_Q0_TXOP_RUNOUT (((REG32(ADR_MTX_INT_EN)) & 0x00020000 ) >> 17)
++#define GET_MTX_EN_INT_Q1_Q_EMPTY (((REG32(ADR_MTX_INT_EN)) & 0x00040000 ) >> 18)
++#define GET_MTX_EN_INT_Q1_TXOP_RUNOUT (((REG32(ADR_MTX_INT_EN)) & 0x00080000 ) >> 19)
++#define GET_MTX_EN_INT_Q2_Q_EMPTY (((REG32(ADR_MTX_INT_EN)) & 0x00100000 ) >> 20)
++#define GET_MTX_EN_INT_Q2_TXOP_RUNOUT (((REG32(ADR_MTX_INT_EN)) & 0x00200000 ) >> 21)
++#define GET_MTX_EN_INT_Q3_Q_EMPTY (((REG32(ADR_MTX_INT_EN)) & 0x00400000 ) >> 22)
++#define GET_MTX_EN_INT_Q3_TXOP_RUNOUT (((REG32(ADR_MTX_INT_EN)) & 0x00800000 ) >> 23)
++#define GET_MTX_EN_INT_Q4_Q_EMPTY (((REG32(ADR_MTX_INT_EN)) & 0x01000000 ) >> 24)
++#define GET_MTX_EN_INT_Q4_TXOP_RUNOUT (((REG32(ADR_MTX_INT_EN)) & 0x02000000 ) >> 25)
++#define GET_MTX_MTX2PHY_SLOW (((REG32(ADR_MTX_MISC_EN)) & 0x00000001 ) >> 0)
++#define GET_MTX_M2M_SLOW_PRD (((REG32(ADR_MTX_MISC_EN)) & 0x0000000e ) >> 1)
++#define GET_MTX_AMPDU_CRC_AUTO (((REG32(ADR_MTX_MISC_EN)) & 0x00000020 ) >> 5)
++#define GET_MTX_FAST_RSP_MODE (((REG32(ADR_MTX_MISC_EN)) & 0x00000040 ) >> 6)
++#define GET_MTX_RAW_DATA_MODE (((REG32(ADR_MTX_MISC_EN)) & 0x00000080 ) >> 7)
++#define GET_MTX_ACK_DUR0 (((REG32(ADR_MTX_MISC_EN)) & 0x00000100 ) >> 8)
++#define GET_MTX_TSF_AUTO_BCN (((REG32(ADR_MTX_MISC_EN)) & 0x00000400 ) >> 10)
++#define GET_MTX_TSF_AUTO_MISC (((REG32(ADR_MTX_MISC_EN)) & 0x00000800 ) >> 11)
++#define GET_MTX_FORCE_CS_IDLE (((REG32(ADR_MTX_MISC_EN)) & 0x00001000 ) >> 12)
++#define GET_MTX_FORCE_BKF_RXEN0 (((REG32(ADR_MTX_MISC_EN)) & 0x00002000 ) >> 13)
++#define GET_MTX_FORCE_DMA_RXEN0 (((REG32(ADR_MTX_MISC_EN)) & 0x00004000 ) >> 14)
++#define GET_MTX_FORCE_RXEN0 (((REG32(ADR_MTX_MISC_EN)) & 0x00008000 ) >> 15)
++#define GET_MTX_HALT_Q_MB (((REG32(ADR_MTX_MISC_EN)) & 0x003f0000 ) >> 16)
++#define GET_MTX_CTS_SET_DIF (((REG32(ADR_MTX_MISC_EN)) & 0x00400000 ) >> 22)
++#define GET_MTX_AMPDU_SET_DIF (((REG32(ADR_MTX_MISC_EN)) & 0x00800000 ) >> 23)
++#define GET_MTX_EDCCA_TOUT (((REG32(ADR_MTX_EDCCA_TOUT)) & 0x000003ff ) >> 0)
++#define GET_MTX_INT_BCN (((REG32(ADR_MTX_BCN_INT_STS)) & 0x00000002 ) >> 1)
++#define GET_MTX_INT_DTIM (((REG32(ADR_MTX_BCN_INT_STS)) & 0x00000008 ) >> 3)
++#define GET_MTX_EN_INT_BCN (((REG32(ADR_MTX_BCN_EN_INT)) & 0x00000002 ) >> 1)
++#define GET_MTX_EN_INT_DTIM (((REG32(ADR_MTX_BCN_EN_INT)) & 0x00000008 ) >> 3)
++#define GET_MTX_BCN_TIMER_EN (((REG32(ADR_MTX_BCN_EN_MISC)) & 0x00000001 ) >> 0)
++#define GET_MTX_TIME_STAMP_AUTO_FILL (((REG32(ADR_MTX_BCN_EN_MISC)) & 0x00000002 ) >> 1)
++#define GET_MTX_TSF_TIMER_EN (((REG32(ADR_MTX_BCN_EN_MISC)) & 0x00000020 ) >> 5)
++#define GET_MTX_HALT_MNG_UNTIL_DTIM (((REG32(ADR_MTX_BCN_EN_MISC)) & 0x00000040 ) >> 6)
++#define GET_MTX_INT_DTIM_NUM (((REG32(ADR_MTX_BCN_EN_MISC)) & 0x0000ff00 ) >> 8)
++#define GET_MTX_AUTO_FLUSH_Q4 (((REG32(ADR_MTX_BCN_EN_MISC)) & 0x00010000 ) >> 16)
++#define GET_MTX_BCN_PKTID_CH_LOCK (((REG32(ADR_MTX_BCN_MISC)) & 0x00000001 ) >> 0)
++#define GET_MTX_BCN_CFG_VLD (((REG32(ADR_MTX_BCN_MISC)) & 0x00000006 ) >> 1)
++#define GET_MTX_AUTO_BCN_ONGOING (((REG32(ADR_MTX_BCN_MISC)) & 0x00000008 ) >> 3)
++#define GET_MTX_BCN_TIMER (((REG32(ADR_MTX_BCN_MISC)) & 0xffff0000 ) >> 16)
++#define GET_MTX_BCN_PERIOD (((REG32(ADR_MTX_BCN_PRD)) & 0x0000ffff ) >> 0)
++#define GET_MTX_DTIM_NUM (((REG32(ADR_MTX_BCN_PRD)) & 0xff000000 ) >> 24)
++#define GET_MTX_BCN_TSF_L (((REG32(ADR_MTX_BCN_TSF_L)) & 0xffffffff ) >> 0)
++#define GET_MTX_BCN_TSF_U (((REG32(ADR_MTX_BCN_TSF_U)) & 0xffffffff ) >> 0)
++#define GET_MTX_BCN_PKT_ID0 (((REG32(ADR_MTX_BCN_CFG0)) & 0x0000007f ) >> 0)
++#define GET_MTX_DTIM_OFST0 (((REG32(ADR_MTX_BCN_CFG0)) & 0x03ff0000 ) >> 16)
++#define GET_MTX_BCN_PKT_ID1 (((REG32(ADR_MTX_BCN_CFG1)) & 0x0000007f ) >> 0)
++#define GET_MTX_DTIM_OFST1 (((REG32(ADR_MTX_BCN_CFG1)) & 0x03ff0000 ) >> 16)
++#define GET_MTX_CCA (((REG32(ADR_MTX_STATUS)) & 0x00000001 ) >> 0)
++#define GET_MRX_CCA (((REG32(ADR_MTX_STATUS)) & 0x00000002 ) >> 1)
++#define GET_MTX_DMA_FSM (((REG32(ADR_MTX_STATUS)) & 0x0000001c ) >> 2)
++#define GET_CH_ST_FSM (((REG32(ADR_MTX_STATUS)) & 0x000000e0 ) >> 5)
++#define GET_MTX_GNT_LOCK (((REG32(ADR_MTX_STATUS)) & 0x00000100 ) >> 8)
++#define GET_MTX_DMA_REQ (((REG32(ADR_MTX_STATUS)) & 0x00000200 ) >> 9)
++#define GET_MTX_Q_REQ (((REG32(ADR_MTX_STATUS)) & 0x00000400 ) >> 10)
++#define GET_MTX_TX_EN (((REG32(ADR_MTX_STATUS)) & 0x00000800 ) >> 11)
++#define GET_MRX_RX_EN (((REG32(ADR_MTX_STATUS)) & 0x00001000 ) >> 12)
++#define GET_DBG_PRTC_PRD (((REG32(ADR_MTX_STATUS)) & 0x00002000 ) >> 13)
++#define GET_DBG_DMA_RDY (((REG32(ADR_MTX_STATUS)) & 0x00004000 ) >> 14)
++#define GET_DBG_WAIT_RSP (((REG32(ADR_MTX_STATUS)) & 0x00008000 ) >> 15)
++#define GET_DBG_CFRM_BUSY (((REG32(ADR_MTX_STATUS)) & 0x00010000 ) >> 16)
++#define GET_DBG_RST (((REG32(ADR_MTX_DBG_CTRL)) & 0x00000001 ) >> 0)
++#define GET_DBG_MODE (((REG32(ADR_MTX_DBG_CTRL)) & 0x00000002 ) >> 1)
++#define GET_MB_REQ_DUR (((REG32(ADR_MTX_DBG_DAT0)) & 0x0000ffff ) >> 0)
++#define GET_RX_EN_DUR (((REG32(ADR_MTX_DBG_DAT0)) & 0xffff0000 ) >> 16)
++#define GET_RX_CS_DUR (((REG32(ADR_MTX_DBG_DAT1)) & 0x0000ffff ) >> 0)
++#define GET_TX_CCA_DUR (((REG32(ADR_MTX_DBG_DAT1)) & 0xffff0000 ) >> 16)
++#define GET_Q_REQ_DUR (((REG32(ADR_MTX_DBG_DAT2)) & 0x0000ffff ) >> 0)
++#define GET_CH_STA0_DUR (((REG32(ADR_MTX_DBG_DAT2)) & 0xffff0000 ) >> 16)
++#define GET_MTX_DUR_RSP_TOUT_B (((REG32(ADR_MTX_DUR_TOUT)) & 0x000000ff ) >> 0)
++#define GET_MTX_DUR_RSP_TOUT_G (((REG32(ADR_MTX_DUR_TOUT)) & 0x0000ff00 ) >> 8)
++#define GET_MTX_DUR_RSP_SIFS (((REG32(ADR_MTX_DUR_IFS)) & 0x000000ff ) >> 0)
++#define GET_MTX_DUR_BURST_SIFS (((REG32(ADR_MTX_DUR_IFS)) & 0x0000ff00 ) >> 8)
++#define GET_MTX_DUR_SLOT (((REG32(ADR_MTX_DUR_IFS)) & 0x003f0000 ) >> 16)
++#define GET_MTX_DUR_RSP_EIFS (((REG32(ADR_MTX_DUR_IFS)) & 0xffc00000 ) >> 22)
++#define GET_MTX_DUR_RSP_SIFS_G (((REG32(ADR_MTX_DUR_SIFS_G)) & 0x000000ff ) >> 0)
++#define GET_MTX_DUR_BURST_SIFS_G (((REG32(ADR_MTX_DUR_SIFS_G)) & 0x0000ff00 ) >> 8)
++#define GET_MTX_DUR_SLOT_G (((REG32(ADR_MTX_DUR_SIFS_G)) & 0x003f0000 ) >> 16)
++#define GET_MTX_DUR_RSP_EIFS_G (((REG32(ADR_MTX_DUR_SIFS_G)) & 0xffc00000 ) >> 22)
++#define GET_CH_STA1_DUR (((REG32(ADR_MTX_DBG_DAT3)) & 0x0000ffff ) >> 0)
++#define GET_CH_STA2_DUR (((REG32(ADR_MTX_DBG_DAT3)) & 0xffff0000 ) >> 16)
++#define GET_MTX_NAV (((REG32(ADR_MTX_NAV)) & 0x0000ffff ) >> 0)
++#define GET_MTX_MIB_CNT0 (((REG32(ADR_MTX_MIB_WSID0)) & 0x3fffffff ) >> 0)
++#define GET_MTX_MIB_EN0 (((REG32(ADR_MTX_MIB_WSID0)) & 0x40000000 ) >> 30)
++#define GET_MTX_MIB_CNT1 (((REG32(ADR_MTX_MIB_WSID1)) & 0x3fffffff ) >> 0)
++#define GET_MTX_MIB_EN1 (((REG32(ADR_MTX_MIB_WSID1)) & 0x40000000 ) >> 30)
++#define GET_CH_STA3_DUR (((REG32(ADR_MTX_DBG_DAT4)) & 0x0000ffff ) >> 0)
++#define GET_CH_STA4_DUR (((REG32(ADR_MTX_DBG_DAT4)) & 0xffff0000 ) >> 16)
++#define GET_TXQ0_MTX_Q_PRE_LD (((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0x00000002 ) >> 1)
++#define GET_TXQ0_MTX_Q_BKF_CNT_FIXED (((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0x00000004 ) >> 2)
++#define GET_TXQ0_MTX_Q_TXOP_SUB_FRM_TIME (((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0x00000008 ) >> 3)
++#define GET_TXQ0_MTX_Q_MB_NO_RLS (((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0x00000010 ) >> 4)
++#define GET_TXQ0_MTX_Q_TXOP_FRC_BUR (((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0x00000020 ) >> 5)
++#define GET_TXQ0_MTX_Q_RND_MODE (((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0x000000c0 ) >> 6)
++#define GET_TXQ0_MTX_Q_AIFSN (((REG32(ADR_TXQ0_MTX_Q_AIFSN)) & 0x0000000f ) >> 0)
++#define GET_TXQ0_MTX_Q_ECWMIN (((REG32(ADR_TXQ0_MTX_Q_AIFSN)) & 0x00000f00 ) >> 8)
++#define GET_TXQ0_MTX_Q_ECWMAX (((REG32(ADR_TXQ0_MTX_Q_AIFSN)) & 0x0000f000 ) >> 12)
++#define GET_TXQ0_MTX_Q_TXOP_LIMIT (((REG32(ADR_TXQ0_MTX_Q_AIFSN)) & 0xffff0000 ) >> 16)
++#define GET_TXQ0_MTX_Q_BKF_CNT (((REG32(ADR_TXQ0_MTX_Q_BKF_CNT)) & 0x0000ffff ) >> 0)
++#define GET_TXQ0_MTX_Q_SRC_LIMIT (((REG32(ADR_TXQ0_MTX_Q_RC_LIMIT)) & 0x000000ff ) >> 0)
++#define GET_TXQ0_MTX_Q_LRC_LIMIT (((REG32(ADR_TXQ0_MTX_Q_RC_LIMIT)) & 0x0000ff00 ) >> 8)
++#define GET_TXQ0_MTX_Q_ID_MAP_L (((REG32(ADR_TXQ0_MTX_Q_ID_MAP_L)) & 0xffffffff ) >> 0)
++#define GET_TXQ0_MTX_Q_TXOP_CH_THD (((REG32(ADR_TXQ0_MTX_Q_TXOP_CH_THD)) & 0x0000ffff ) >> 0)
++#define GET_TXQ0_MTX_Q_TXOP_OV_THD (((REG32(ADR_TXQ0_MTX_Q_TXOP_OV_THD)) & 0x0000ffff ) >> 0)
++#define GET_TXQ1_MTX_Q_PRE_LD (((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0x00000002 ) >> 1)
++#define GET_TXQ1_MTX_Q_BKF_CNT_FIXED (((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0x00000004 ) >> 2)
++#define GET_TXQ1_MTX_Q_TXOP_SUB_FRM_TIME (((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0x00000008 ) >> 3)
++#define GET_TXQ1_MTX_Q_MB_NO_RLS (((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0x00000010 ) >> 4)
++#define GET_TXQ1_MTX_Q_TXOP_FRC_BUR (((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0x00000020 ) >> 5)
++#define GET_TXQ1_MTX_Q_RND_MODE (((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0x000000c0 ) >> 6)
++#define GET_TXQ1_MTX_Q_AIFSN (((REG32(ADR_TXQ1_MTX_Q_AIFSN)) & 0x0000000f ) >> 0)
++#define GET_TXQ1_MTX_Q_ECWMIN (((REG32(ADR_TXQ1_MTX_Q_AIFSN)) & 0x00000f00 ) >> 8)
++#define GET_TXQ1_MTX_Q_ECWMAX (((REG32(ADR_TXQ1_MTX_Q_AIFSN)) & 0x0000f000 ) >> 12)
++#define GET_TXQ1_MTX_Q_TXOP_LIMIT (((REG32(ADR_TXQ1_MTX_Q_AIFSN)) & 0xffff0000 ) >> 16)
++#define GET_TXQ1_MTX_Q_BKF_CNT (((REG32(ADR_TXQ1_MTX_Q_BKF_CNT)) & 0x0000ffff ) >> 0)
++#define GET_TXQ1_MTX_Q_SRC_LIMIT (((REG32(ADR_TXQ1_MTX_Q_RC_LIMIT)) & 0x000000ff ) >> 0)
++#define GET_TXQ1_MTX_Q_LRC_LIMIT (((REG32(ADR_TXQ1_MTX_Q_RC_LIMIT)) & 0x0000ff00 ) >> 8)
++#define GET_TXQ1_MTX_Q_ID_MAP_L (((REG32(ADR_TXQ1_MTX_Q_ID_MAP_L)) & 0xffffffff ) >> 0)
++#define GET_TXQ1_MTX_Q_TXOP_CH_THD (((REG32(ADR_TXQ1_MTX_Q_TXOP_CH_THD)) & 0x0000ffff ) >> 0)
++#define GET_TXQ1_MTX_Q_TXOP_OV_THD (((REG32(ADR_TXQ1_MTX_Q_TXOP_OV_THD)) & 0x0000ffff ) >> 0)
++#define GET_TXQ2_MTX_Q_PRE_LD (((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0x00000002 ) >> 1)
++#define GET_TXQ2_MTX_Q_BKF_CNT_FIXED (((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0x00000004 ) >> 2)
++#define GET_TXQ2_MTX_Q_TXOP_SUB_FRM_TIME (((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0x00000008 ) >> 3)
++#define GET_TXQ2_MTX_Q_MB_NO_RLS (((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0x00000010 ) >> 4)
++#define GET_TXQ2_MTX_Q_TXOP_FRC_BUR (((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0x00000020 ) >> 5)
++#define GET_TXQ2_MTX_Q_RND_MODE (((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0x000000c0 ) >> 6)
++#define GET_TXQ2_MTX_Q_AIFSN (((REG32(ADR_TXQ2_MTX_Q_AIFSN)) & 0x0000000f ) >> 0)
++#define GET_TXQ2_MTX_Q_ECWMIN (((REG32(ADR_TXQ2_MTX_Q_AIFSN)) & 0x00000f00 ) >> 8)
++#define GET_TXQ2_MTX_Q_ECWMAX (((REG32(ADR_TXQ2_MTX_Q_AIFSN)) & 0x0000f000 ) >> 12)
++#define GET_TXQ2_MTX_Q_TXOP_LIMIT (((REG32(ADR_TXQ2_MTX_Q_AIFSN)) & 0xffff0000 ) >> 16)
++#define GET_TXQ2_MTX_Q_BKF_CNT (((REG32(ADR_TXQ2_MTX_Q_BKF_CNT)) & 0x0000ffff ) >> 0)
++#define GET_TXQ2_MTX_Q_SRC_LIMIT (((REG32(ADR_TXQ2_MTX_Q_RC_LIMIT)) & 0x000000ff ) >> 0)
++#define GET_TXQ2_MTX_Q_LRC_LIMIT (((REG32(ADR_TXQ2_MTX_Q_RC_LIMIT)) & 0x0000ff00 ) >> 8)
++#define GET_TXQ2_MTX_Q_ID_MAP_L (((REG32(ADR_TXQ2_MTX_Q_ID_MAP_L)) & 0xffffffff ) >> 0)
++#define GET_TXQ2_MTX_Q_TXOP_CH_THD (((REG32(ADR_TXQ2_MTX_Q_TXOP_CH_THD)) & 0x0000ffff ) >> 0)
++#define GET_TXQ2_MTX_Q_TXOP_OV_THD (((REG32(ADR_TXQ2_MTX_Q_TXOP_OV_THD)) & 0x0000ffff ) >> 0)
++#define GET_TXQ3_MTX_Q_PRE_LD (((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0x00000002 ) >> 1)
++#define GET_TXQ3_MTX_Q_BKF_CNT_FIXED (((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0x00000004 ) >> 2)
++#define GET_TXQ3_MTX_Q_TXOP_SUB_FRM_TIME (((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0x00000008 ) >> 3)
++#define GET_TXQ3_MTX_Q_MB_NO_RLS (((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0x00000010 ) >> 4)
++#define GET_TXQ3_MTX_Q_TXOP_FRC_BUR (((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0x00000020 ) >> 5)
++#define GET_TXQ3_MTX_Q_RND_MODE (((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0x000000c0 ) >> 6)
++#define GET_TXQ3_MTX_Q_AIFSN (((REG32(ADR_TXQ3_MTX_Q_AIFSN)) & 0x0000000f ) >> 0)
++#define GET_TXQ3_MTX_Q_ECWMIN (((REG32(ADR_TXQ3_MTX_Q_AIFSN)) & 0x00000f00 ) >> 8)
++#define GET_TXQ3_MTX_Q_ECWMAX (((REG32(ADR_TXQ3_MTX_Q_AIFSN)) & 0x0000f000 ) >> 12)
++#define GET_TXQ3_MTX_Q_TXOP_LIMIT (((REG32(ADR_TXQ3_MTX_Q_AIFSN)) & 0xffff0000 ) >> 16)
++#define GET_TXQ3_MTX_Q_BKF_CNT (((REG32(ADR_TXQ3_MTX_Q_BKF_CNT)) & 0x0000ffff ) >> 0)
++#define GET_TXQ3_MTX_Q_SRC_LIMIT (((REG32(ADR_TXQ3_MTX_Q_RC_LIMIT)) & 0x000000ff ) >> 0)
++#define GET_TXQ3_MTX_Q_LRC_LIMIT (((REG32(ADR_TXQ3_MTX_Q_RC_LIMIT)) & 0x0000ff00 ) >> 8)
++#define GET_TXQ3_MTX_Q_ID_MAP_L (((REG32(ADR_TXQ3_MTX_Q_ID_MAP_L)) & 0xffffffff ) >> 0)
++#define GET_TXQ3_MTX_Q_TXOP_CH_THD (((REG32(ADR_TXQ3_MTX_Q_TXOP_CH_THD)) & 0x0000ffff ) >> 0)
++#define GET_TXQ3_MTX_Q_TXOP_OV_THD (((REG32(ADR_TXQ3_MTX_Q_TXOP_OV_THD)) & 0x0000ffff ) >> 0)
++#define GET_TXQ4_MTX_Q_PRE_LD (((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0x00000002 ) >> 1)
++#define GET_TXQ4_MTX_Q_BKF_CNT_FIXED (((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0x00000004 ) >> 2)
++#define GET_TXQ4_MTX_Q_TXOP_SUB_FRM_TIME (((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0x00000008 ) >> 3)
++#define GET_TXQ4_MTX_Q_MB_NO_RLS (((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0x00000010 ) >> 4)
++#define GET_TXQ4_MTX_Q_TXOP_FRC_BUR (((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0x00000020 ) >> 5)
++#define GET_TXQ4_MTX_Q_RND_MODE (((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0x000000c0 ) >> 6)
++#define GET_TXQ4_MTX_Q_AIFSN (((REG32(ADR_TXQ4_MTX_Q_AIFSN)) & 0x0000000f ) >> 0)
++#define GET_TXQ4_MTX_Q_ECWMIN (((REG32(ADR_TXQ4_MTX_Q_AIFSN)) & 0x00000f00 ) >> 8)
++#define GET_TXQ4_MTX_Q_ECWMAX (((REG32(ADR_TXQ4_MTX_Q_AIFSN)) & 0x0000f000 ) >> 12)
++#define GET_TXQ4_MTX_Q_TXOP_LIMIT (((REG32(ADR_TXQ4_MTX_Q_AIFSN)) & 0xffff0000 ) >> 16)
++#define GET_TXQ4_MTX_Q_BKF_CNT (((REG32(ADR_TXQ4_MTX_Q_BKF_CNT)) & 0x0000ffff ) >> 0)
++#define GET_TXQ4_MTX_Q_SRC_LIMIT (((REG32(ADR_TXQ4_MTX_Q_RC_LIMIT)) & 0x000000ff ) >> 0)
++#define GET_TXQ4_MTX_Q_LRC_LIMIT (((REG32(ADR_TXQ4_MTX_Q_RC_LIMIT)) & 0x0000ff00 ) >> 8)
++#define GET_TXQ4_MTX_Q_ID_MAP_L (((REG32(ADR_TXQ4_MTX_Q_ID_MAP_L)) & 0xffffffff ) >> 0)
++#define GET_TXQ4_MTX_Q_TXOP_CH_THD (((REG32(ADR_TXQ4_MTX_Q_TXOP_CH_THD)) & 0x0000ffff ) >> 0)
++#define GET_TXQ4_MTX_Q_TXOP_OV_THD (((REG32(ADR_TXQ4_MTX_Q_TXOP_OV_THD)) & 0x0000ffff ) >> 0)
++#define GET_VALID0 (((REG32(ADR_WSID0)) & 0x00000001 ) >> 0)
++#define GET_PEER_QOS_EN0 (((REG32(ADR_WSID0)) & 0x00000002 ) >> 1)
++#define GET_PEER_OP_MODE0 (((REG32(ADR_WSID0)) & 0x0000000c ) >> 2)
++#define GET_PEER_HT_MODE0 (((REG32(ADR_WSID0)) & 0x00000030 ) >> 4)
++#define GET_PEER_MAC0_31_0 (((REG32(ADR_PEER_MAC0_0)) & 0xffffffff ) >> 0)
++#define GET_PEER_MAC0_47_32 (((REG32(ADR_PEER_MAC0_1)) & 0x0000ffff ) >> 0)
++#define GET_TX_ACK_POLICY_0_0 (((REG32(ADR_TX_ACK_POLICY_0_0)) & 0x00000003 ) >> 0)
++#define GET_TX_SEQ_CTRL_0_0 (((REG32(ADR_TX_SEQ_CTRL_0_0)) & 0x00000fff ) >> 0)
++#define GET_TX_ACK_POLICY_0_1 (((REG32(ADR_TX_ACK_POLICY_0_1)) & 0x00000003 ) >> 0)
++#define GET_TX_SEQ_CTRL_0_1 (((REG32(ADR_TX_SEQ_CTRL_0_1)) & 0x00000fff ) >> 0)
++#define GET_TX_ACK_POLICY_0_2 (((REG32(ADR_TX_ACK_POLICY_0_2)) & 0x00000003 ) >> 0)
++#define GET_TX_SEQ_CTRL_0_2 (((REG32(ADR_TX_SEQ_CTRL_0_2)) & 0x00000fff ) >> 0)
++#define GET_TX_ACK_POLICY_0_3 (((REG32(ADR_TX_ACK_POLICY_0_3)) & 0x00000003 ) >> 0)
++#define GET_TX_SEQ_CTRL_0_3 (((REG32(ADR_TX_SEQ_CTRL_0_3)) & 0x00000fff ) >> 0)
++#define GET_TX_ACK_POLICY_0_4 (((REG32(ADR_TX_ACK_POLICY_0_4)) & 0x00000003 ) >> 0)
++#define GET_TX_SEQ_CTRL_0_4 (((REG32(ADR_TX_SEQ_CTRL_0_4)) & 0x00000fff ) >> 0)
++#define GET_TX_ACK_POLICY_0_5 (((REG32(ADR_TX_ACK_POLICY_0_5)) & 0x00000003 ) >> 0)
++#define GET_TX_SEQ_CTRL_0_5 (((REG32(ADR_TX_SEQ_CTRL_0_5)) & 0x00000fff ) >> 0)
++#define GET_TX_ACK_POLICY_0_6 (((REG32(ADR_TX_ACK_POLICY_0_6)) & 0x00000003 ) >> 0)
++#define GET_TX_SEQ_CTRL_0_6 (((REG32(ADR_TX_SEQ_CTRL_0_6)) & 0x00000fff ) >> 0)
++#define GET_TX_ACK_POLICY_0_7 (((REG32(ADR_TX_ACK_POLICY_0_7)) & 0x00000003 ) >> 0)
++#define GET_TX_SEQ_CTRL_0_7 (((REG32(ADR_TX_SEQ_CTRL_0_7)) & 0x00000fff ) >> 0)
++#define GET_VALID1 (((REG32(ADR_WSID1)) & 0x00000001 ) >> 0)
++#define GET_PEER_QOS_EN1 (((REG32(ADR_WSID1)) & 0x00000002 ) >> 1)
++#define GET_PEER_OP_MODE1 (((REG32(ADR_WSID1)) & 0x0000000c ) >> 2)
++#define GET_PEER_HT_MODE1 (((REG32(ADR_WSID1)) & 0x00000030 ) >> 4)
++#define GET_PEER_MAC1_31_0 (((REG32(ADR_PEER_MAC1_0)) & 0xffffffff ) >> 0)
++#define GET_PEER_MAC1_47_32 (((REG32(ADR_PEER_MAC1_1)) & 0x0000ffff ) >> 0)
++#define GET_TX_ACK_POLICY_1_0 (((REG32(ADR_TX_ACK_POLICY_1_0)) & 0x00000003 ) >> 0)
++#define GET_TX_SEQ_CTRL_1_0 (((REG32(ADR_TX_SEQ_CTRL_1_0)) & 0x00000fff ) >> 0)
++#define GET_TX_ACK_POLICY_1_1 (((REG32(ADR_TX_ACK_POLICY_1_1)) & 0x00000003 ) >> 0)
++#define GET_TX_SEQ_CTRL_1_1 (((REG32(ADR_TX_SEQ_CTRL_1_1)) & 0x00000fff ) >> 0)
++#define GET_TX_ACK_POLICY_1_2 (((REG32(ADR_TX_ACK_POLICY_1_2)) & 0x00000003 ) >> 0)
++#define GET_TX_SEQ_CTRL_1_2 (((REG32(ADR_TX_SEQ_CTRL_1_2)) & 0x00000fff ) >> 0)
++#define GET_TX_ACK_POLICY_1_3 (((REG32(ADR_TX_ACK_POLICY_1_3)) & 0x00000003 ) >> 0)
++#define GET_TX_SEQ_CTRL_1_3 (((REG32(ADR_TX_SEQ_CTRL_1_3)) & 0x00000fff ) >> 0)
++#define GET_TX_ACK_POLICY_1_4 (((REG32(ADR_TX_ACK_POLICY_1_4)) & 0x00000003 ) >> 0)
++#define GET_TX_SEQ_CTRL_1_4 (((REG32(ADR_TX_SEQ_CTRL_1_4)) & 0x00000fff ) >> 0)
++#define GET_TX_ACK_POLICY_1_5 (((REG32(ADR_TX_ACK_POLICY_1_5)) & 0x00000003 ) >> 0)
++#define GET_TX_SEQ_CTRL_1_5 (((REG32(ADR_TX_SEQ_CTRL_1_5)) & 0x00000fff ) >> 0)
++#define GET_TX_ACK_POLICY_1_6 (((REG32(ADR_TX_ACK_POLICY_1_6)) & 0x00000003 ) >> 0)
++#define GET_TX_SEQ_CTRL_1_6 (((REG32(ADR_TX_SEQ_CTRL_1_6)) & 0x00000fff ) >> 0)
++#define GET_TX_ACK_POLICY_1_7 (((REG32(ADR_TX_ACK_POLICY_1_7)) & 0x00000003 ) >> 0)
++#define GET_TX_SEQ_CTRL_1_7 (((REG32(ADR_TX_SEQ_CTRL_1_7)) & 0x00000fff ) >> 0)
++#define GET_INFO0 (((REG32(ADR_INFO0)) & 0xffffffff ) >> 0)
++#define GET_INFO1 (((REG32(ADR_INFO1)) & 0xffffffff ) >> 0)
++#define GET_INFO2 (((REG32(ADR_INFO2)) & 0xffffffff ) >> 0)
++#define GET_INFO3 (((REG32(ADR_INFO3)) & 0xffffffff ) >> 0)
++#define GET_INFO4 (((REG32(ADR_INFO4)) & 0xffffffff ) >> 0)
++#define GET_INFO5 (((REG32(ADR_INFO5)) & 0xffffffff ) >> 0)
++#define GET_INFO6 (((REG32(ADR_INFO6)) & 0xffffffff ) >> 0)
++#define GET_INFO7 (((REG32(ADR_INFO7)) & 0xffffffff ) >> 0)
++#define GET_INFO8 (((REG32(ADR_INFO8)) & 0xffffffff ) >> 0)
++#define GET_INFO9 (((REG32(ADR_INFO9)) & 0xffffffff ) >> 0)
++#define GET_INFO10 (((REG32(ADR_INFO10)) & 0xffffffff ) >> 0)
++#define GET_INFO11 (((REG32(ADR_INFO11)) & 0xffffffff ) >> 0)
++#define GET_INFO12 (((REG32(ADR_INFO12)) & 0xffffffff ) >> 0)
++#define GET_INFO13 (((REG32(ADR_INFO13)) & 0xffffffff ) >> 0)
++#define GET_INFO14 (((REG32(ADR_INFO14)) & 0xffffffff ) >> 0)
++#define GET_INFO15 (((REG32(ADR_INFO15)) & 0xffffffff ) >> 0)
++#define GET_INFO16 (((REG32(ADR_INFO16)) & 0xffffffff ) >> 0)
++#define GET_INFO17 (((REG32(ADR_INFO17)) & 0xffffffff ) >> 0)
++#define GET_INFO18 (((REG32(ADR_INFO18)) & 0xffffffff ) >> 0)
++#define GET_INFO19 (((REG32(ADR_INFO19)) & 0xffffffff ) >> 0)
++#define GET_INFO20 (((REG32(ADR_INFO20)) & 0xffffffff ) >> 0)
++#define GET_INFO21 (((REG32(ADR_INFO21)) & 0xffffffff ) >> 0)
++#define GET_INFO22 (((REG32(ADR_INFO22)) & 0xffffffff ) >> 0)
++#define GET_INFO23 (((REG32(ADR_INFO23)) & 0xffffffff ) >> 0)
++#define GET_INFO24 (((REG32(ADR_INFO24)) & 0xffffffff ) >> 0)
++#define GET_INFO25 (((REG32(ADR_INFO25)) & 0xffffffff ) >> 0)
++#define GET_INFO26 (((REG32(ADR_INFO26)) & 0xffffffff ) >> 0)
++#define GET_INFO27 (((REG32(ADR_INFO27)) & 0xffffffff ) >> 0)
++#define GET_INFO28 (((REG32(ADR_INFO28)) & 0xffffffff ) >> 0)
++#define GET_INFO29 (((REG32(ADR_INFO29)) & 0xffffffff ) >> 0)
++#define GET_INFO30 (((REG32(ADR_INFO30)) & 0xffffffff ) >> 0)
++#define GET_INFO31 (((REG32(ADR_INFO31)) & 0xffffffff ) >> 0)
++#define GET_INFO32 (((REG32(ADR_INFO32)) & 0xffffffff ) >> 0)
++#define GET_INFO33 (((REG32(ADR_INFO33)) & 0xffffffff ) >> 0)
++#define GET_INFO34 (((REG32(ADR_INFO34)) & 0xffffffff ) >> 0)
++#define GET_INFO35 (((REG32(ADR_INFO35)) & 0xffffffff ) >> 0)
++#define GET_INFO36 (((REG32(ADR_INFO36)) & 0xffffffff ) >> 0)
++#define GET_INFO37 (((REG32(ADR_INFO37)) & 0xffffffff ) >> 0)
++#define GET_INFO38 (((REG32(ADR_INFO38)) & 0xffffffff ) >> 0)
++#define GET_INFO_MASK (((REG32(ADR_INFO_MASK)) & 0xffffffff ) >> 0)
++#define GET_INFO_DEF_RATE (((REG32(ADR_INFO_RATE_OFFSET)) & 0x0000003f ) >> 0)
++#define GET_INFO_MRX_OFFSET (((REG32(ADR_INFO_RATE_OFFSET)) & 0x000f0000 ) >> 16)
++#define GET_BCAST_RATEUNKNOW (((REG32(ADR_INFO_RATE_OFFSET)) & 0x3f000000 ) >> 24)
++#define GET_INFO_IDX_TBL_ADDR (((REG32(ADR_INFO_IDX_ADDR)) & 0xffffffff ) >> 0)
++#define GET_INFO_LEN_TBL_ADDR (((REG32(ADR_INFO_LEN_ADDR)) & 0xffffffff ) >> 0)
++#define GET_IC_TAG_31_0 (((REG32(ADR_IC_TIME_TAG_0)) & 0xffffffff ) >> 0)
++#define GET_IC_TAG_63_32 (((REG32(ADR_IC_TIME_TAG_1)) & 0xffffffff ) >> 0)
++#define GET_CH1_PRI (((REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) & 0x00000003 ) >> 0)
++#define GET_CH2_PRI (((REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) & 0x00000300 ) >> 8)
++#define GET_CH3_PRI (((REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) & 0x00030000 ) >> 16)
++#define GET_RG_MAC_LPBK (((REG32(ADR_MAC_MODE)) & 0x00000001 ) >> 0)
++#define GET_RG_MAC_M2M (((REG32(ADR_MAC_MODE)) & 0x00000002 ) >> 1)
++#define GET_RG_PHY_LPBK (((REG32(ADR_MAC_MODE)) & 0x00000004 ) >> 2)
++#define GET_RG_LPBK_RX_EN (((REG32(ADR_MAC_MODE)) & 0x00000008 ) >> 3)
++#define GET_EXT_MAC_MODE (((REG32(ADR_MAC_MODE)) & 0x00000010 ) >> 4)
++#define GET_EXT_PHY_MODE (((REG32(ADR_MAC_MODE)) & 0x00000020 ) >> 5)
++#define GET_ASIC_TAG (((REG32(ADR_MAC_MODE)) & 0xff000000 ) >> 24)
++#define GET_HCI_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000001 ) >> 0)
++#define GET_CO_PROC_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000002 ) >> 1)
++#define GET_MTX_MISC_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000008 ) >> 3)
++#define GET_MTX_QUE_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000010 ) >> 4)
++#define GET_MTX_CHST_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000020 ) >> 5)
++#define GET_MTX_BCN_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000040 ) >> 6)
++#define GET_MRX_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000080 ) >> 7)
++#define GET_AMPDU_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000100 ) >> 8)
++#define GET_MMU_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000200 ) >> 9)
++#define GET_ID_MNG_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000800 ) >> 11)
++#define GET_MBOX_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00001000 ) >> 12)
++#define GET_SCRT_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00002000 ) >> 13)
++#define GET_MIC_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00004000 ) >> 14)
++#define GET_CO_PROC_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00000002 ) >> 1)
++#define GET_MTX_MISC_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00000008 ) >> 3)
++#define GET_MTX_QUE_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00000010 ) >> 4)
++#define GET_MTX_CHST_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00000020 ) >> 5)
++#define GET_MTX_BCN_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00000040 ) >> 6)
++#define GET_MRX_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00000080 ) >> 7)
++#define GET_AMPDU_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00000100 ) >> 8)
++#define GET_ID_MNG_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00004000 ) >> 14)
++#define GET_MBOX_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00008000 ) >> 15)
++#define GET_SCRT_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00010000 ) >> 16)
++#define GET_MIC_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00020000 ) >> 17)
++#define GET_CO_PROC_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000002 ) >> 1)
++#define GET_MTX_MISC_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000008 ) >> 3)
++#define GET_MTX_QUE0_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000010 ) >> 4)
++#define GET_MTX_QUE1_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000020 ) >> 5)
++#define GET_MTX_QUE2_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000040 ) >> 6)
++#define GET_MTX_QUE3_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000080 ) >> 7)
++#define GET_MTX_QUE4_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000100 ) >> 8)
++#define GET_MTX_QUE5_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000200 ) >> 9)
++#define GET_MRX_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000400 ) >> 10)
++#define GET_AMPDU_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000800 ) >> 11)
++#define GET_SCRT_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00002000 ) >> 13)
++#define GET_ID_MNG_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00004000 ) >> 14)
++#define GET_MBOX_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00008000 ) >> 15)
++#define GET_HCI_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000001 ) >> 0)
++#define GET_CO_PROC_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000002 ) >> 1)
++#define GET_MTX_MISC_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000008 ) >> 3)
++#define GET_MTX_QUE_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000010 ) >> 4)
++#define GET_MRX_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000020 ) >> 5)
++#define GET_AMPDU_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000040 ) >> 6)
++#define GET_MMU_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000080 ) >> 7)
++#define GET_ID_MNG_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000200 ) >> 9)
++#define GET_MBOX_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000400 ) >> 10)
++#define GET_SCRT_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000800 ) >> 11)
++#define GET_MIC_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00001000 ) >> 12)
++#define GET_MIB_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00002000 ) >> 13)
++#define GET_HCI_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00000001 ) >> 0)
++#define GET_CO_PROC_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00000002 ) >> 1)
++#define GET_MTX_MISC_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00000008 ) >> 3)
++#define GET_MTX_QUE_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00000010 ) >> 4)
++#define GET_MRX_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00000020 ) >> 5)
++#define GET_AMPDU_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00000040 ) >> 6)
++#define GET_ID_MNG_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00001000 ) >> 12)
++#define GET_MBOX_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00002000 ) >> 13)
++#define GET_SCRT_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00004000 ) >> 14)
++#define GET_MIC_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00008000 ) >> 15)
++#define GET_CO_PROC_CSR_CLK_EN (((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0x00000002 ) >> 1)
++#define GET_MRX_CSR_CLK_EN (((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0x00000400 ) >> 10)
++#define GET_AMPDU_CSR_CLK_EN (((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0x00000800 ) >> 11)
++#define GET_SCRT_CSR_CLK_EN (((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0x00002000 ) >> 13)
++#define GET_ID_MNG_CSR_CLK_EN (((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0x00004000 ) >> 14)
++#define GET_MBOX_CSR_CLK_EN (((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0x00008000 ) >> 15)
++#define GET_OP_MODE (((REG32(ADR_GLBLE_SET)) & 0x00000003 ) >> 0)
++#define GET_HT_MODE (((REG32(ADR_GLBLE_SET)) & 0x0000000c ) >> 2)
++#define GET_QOS_EN (((REG32(ADR_GLBLE_SET)) & 0x00000010 ) >> 4)
++#define GET_PB_OFFSET (((REG32(ADR_GLBLE_SET)) & 0x0000ff00 ) >> 8)
++#define GET_SNIFFER_MODE (((REG32(ADR_GLBLE_SET)) & 0x00010000 ) >> 16)
++#define GET_DUP_FLT (((REG32(ADR_GLBLE_SET)) & 0x00020000 ) >> 17)
++#define GET_TX_PKT_RSVD (((REG32(ADR_GLBLE_SET)) & 0x001c0000 ) >> 18)
++#define GET_AMPDU_SNIFFER (((REG32(ADR_GLBLE_SET)) & 0x00200000 ) >> 21)
++#define GET_REASON_TRAP0 (((REG32(ADR_REASON_TRAP0)) & 0xffffffff ) >> 0)
++#define GET_REASON_TRAP1 (((REG32(ADR_REASON_TRAP1)) & 0xffffffff ) >> 0)
++#define GET_BSSID_31_0 (((REG32(ADR_BSSID_0)) & 0xffffffff ) >> 0)
++#define GET_BSSID_47_32 (((REG32(ADR_BSSID_1)) & 0x0000ffff ) >> 0)
++#define GET_SCRT_STATE (((REG32(ADR_SCRT_STATE)) & 0x0000000f ) >> 0)
++#define GET_STA_MAC_31_0 (((REG32(ADR_STA_MAC_0)) & 0xffffffff ) >> 0)
++#define GET_STA_MAC_47_32 (((REG32(ADR_STA_MAC_1)) & 0x0000ffff ) >> 0)
++#define GET_PAIR_SCRT (((REG32(ADR_SCRT_SET)) & 0x00000007 ) >> 0)
++#define GET_GRP_SCRT (((REG32(ADR_SCRT_SET)) & 0x00000038 ) >> 3)
++#define GET_SCRT_PKT_ID (((REG32(ADR_SCRT_SET)) & 0x00001fc0 ) >> 6)
++#define GET_SCRT_RPLY_IGNORE (((REG32(ADR_SCRT_SET)) & 0x00010000 ) >> 16)
++#define GET_COEXIST_EN (((REG32(ADR_BTCX0)) & 0x00000001 ) >> 0)
++#define GET_WIRE_MODE (((REG32(ADR_BTCX0)) & 0x0000000e ) >> 1)
++#define GET_WL_RX_PRI (((REG32(ADR_BTCX0)) & 0x00000010 ) >> 4)
++#define GET_WL_TX_PRI (((REG32(ADR_BTCX0)) & 0x00000020 ) >> 5)
++#define GET_GURAN_USE_EN (((REG32(ADR_BTCX0)) & 0x00000100 ) >> 8)
++#define GET_GURAN_USE_CTRL (((REG32(ADR_BTCX0)) & 0x00000200 ) >> 9)
++#define GET_BEACON_TIMEOUT_EN (((REG32(ADR_BTCX0)) & 0x00000400 ) >> 10)
++#define GET_WLAN_ACT_POL (((REG32(ADR_BTCX0)) & 0x00000800 ) >> 11)
++#define GET_DUAL_ANT_EN (((REG32(ADR_BTCX0)) & 0x00001000 ) >> 12)
++#define GET_TRSW_PHY_POL (((REG32(ADR_BTCX0)) & 0x00010000 ) >> 16)
++#define GET_WIFI_TX_SW_POL (((REG32(ADR_BTCX0)) & 0x00020000 ) >> 17)
++#define GET_WIFI_RX_SW_POL (((REG32(ADR_BTCX0)) & 0x00040000 ) >> 18)
++#define GET_BT_SW_POL (((REG32(ADR_BTCX0)) & 0x00080000 ) >> 19)
++#define GET_BT_PRI_SMP_TIME (((REG32(ADR_BTCX1)) & 0x000000ff ) >> 0)
++#define GET_BT_STA_SMP_TIME (((REG32(ADR_BTCX1)) & 0x0000ff00 ) >> 8)
++#define GET_BEACON_TIMEOUT (((REG32(ADR_BTCX1)) & 0x00ff0000 ) >> 16)
++#define GET_WLAN_REMAIN_TIME (((REG32(ADR_BTCX1)) & 0xff000000 ) >> 24)
++#define GET_SW_MANUAL_EN (((REG32(ADR_SWITCH_CTL)) & 0x00000001 ) >> 0)
++#define GET_SW_WL_TX (((REG32(ADR_SWITCH_CTL)) & 0x00000002 ) >> 1)
++#define GET_SW_WL_RX (((REG32(ADR_SWITCH_CTL)) & 0x00000004 ) >> 2)
++#define GET_SW_BT_TRX (((REG32(ADR_SWITCH_CTL)) & 0x00000008 ) >> 3)
++#define GET_BT_TXBAR_MANUAL_EN (((REG32(ADR_SWITCH_CTL)) & 0x00000010 ) >> 4)
++#define GET_BT_TXBAR_SET (((REG32(ADR_SWITCH_CTL)) & 0x00000020 ) >> 5)
++#define GET_BT_BUSY_MANUAL_EN (((REG32(ADR_SWITCH_CTL)) & 0x00000100 ) >> 8)
++#define GET_BT_BUSY_SET (((REG32(ADR_SWITCH_CTL)) & 0x00000200 ) >> 9)
++#define GET_G0_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00000004 ) >> 2)
++#define GET_G0_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00000008 ) >> 3)
++#define GET_G1_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00000010 ) >> 4)
++#define GET_G1_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00000020 ) >> 5)
++#define GET_Q0_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00000040 ) >> 6)
++#define GET_Q0_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00000080 ) >> 7)
++#define GET_Q1_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00000100 ) >> 8)
++#define GET_Q1_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00000200 ) >> 9)
++#define GET_Q2_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00000400 ) >> 10)
++#define GET_Q2_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00000800 ) >> 11)
++#define GET_Q3_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00001000 ) >> 12)
++#define GET_Q3_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00002000 ) >> 13)
++#define GET_SCRT_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00004000 ) >> 14)
++#define GET_SCRT_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00008000 ) >> 15)
++#define GET_MISC_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00010000 ) >> 16)
++#define GET_MISC_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00020000 ) >> 17)
++#define GET_MTX_WSID0_SUCC (((REG32(ADR_MTX_WSID0_SUCC)) & 0x0000ffff ) >> 0)
++#define GET_MTX_WSID0_FRM (((REG32(ADR_MTX_WSID0_FRM)) & 0x0000ffff ) >> 0)
++#define GET_MTX_WSID0_RETRY (((REG32(ADR_MTX_WSID0_RETRY)) & 0x0000ffff ) >> 0)
++#define GET_MTX_WSID0_TOTAL (((REG32(ADR_MTX_WSID0_TOTAL)) & 0x0000ffff ) >> 0)
++#define GET_MTX_GRP (((REG32(ADR_MTX_GROUP)) & 0x000fffff ) >> 0)
++#define GET_MTX_FAIL (((REG32(ADR_MTX_FAIL)) & 0x0000ffff ) >> 0)
++#define GET_MTX_RETRY (((REG32(ADR_MTX_RETRY)) & 0x000fffff ) >> 0)
++#define GET_MTX_MULTI_RETRY (((REG32(ADR_MTX_MULTI_RETRY)) & 0x000fffff ) >> 0)
++#define GET_MTX_RTS_SUCC (((REG32(ADR_MTX_RTS_SUCCESS)) & 0x0000ffff ) >> 0)
++#define GET_MTX_RTS_FAIL (((REG32(ADR_MTX_RTS_FAIL)) & 0x0000ffff ) >> 0)
++#define GET_MTX_ACK_FAIL (((REG32(ADR_MTX_ACK_FAIL)) & 0x0000ffff ) >> 0)
++#define GET_MTX_FRM (((REG32(ADR_MTX_FRM)) & 0x000fffff ) >> 0)
++#define GET_MTX_ACK_TX (((REG32(ADR_MTX_ACK_TX)) & 0x0000ffff ) >> 0)
++#define GET_MTX_CTS_TX (((REG32(ADR_MTX_CTS_TX)) & 0x0000ffff ) >> 0)
++#define GET_MRX_DUP (((REG32(ADR_MRX_DUP_FRM)) & 0x0000ffff ) >> 0)
++#define GET_MRX_FRG (((REG32(ADR_MRX_FRG_FRM)) & 0x000fffff ) >> 0)
++#define GET_MRX_GRP (((REG32(ADR_MRX_GROUP_FRM)) & 0x000fffff ) >> 0)
++#define GET_MRX_FCS_ERR (((REG32(ADR_MRX_FCS_ERR)) & 0x0000ffff ) >> 0)
++#define GET_MRX_FCS_SUC (((REG32(ADR_MRX_FCS_SUCC)) & 0x0000ffff ) >> 0)
++#define GET_MRX_MISS (((REG32(ADR_MRX_MISS)) & 0x0000ffff ) >> 0)
++#define GET_MRX_ALC_FAIL (((REG32(ADR_MRX_ALC_FAIL)) & 0x0000ffff ) >> 0)
++#define GET_MRX_DAT_NTF (((REG32(ADR_MRX_DAT_NTF)) & 0x0000ffff ) >> 0)
++#define GET_MRX_RTS_NTF (((REG32(ADR_MRX_RTS_NTF)) & 0x0000ffff ) >> 0)
++#define GET_MRX_CTS_NTF (((REG32(ADR_MRX_CTS_NTF)) & 0x0000ffff ) >> 0)
++#define GET_MRX_ACK_NTF (((REG32(ADR_MRX_ACK_NTF)) & 0x0000ffff ) >> 0)
++#define GET_MRX_BA_NTF (((REG32(ADR_MRX_BA_NTF)) & 0x0000ffff ) >> 0)
++#define GET_MRX_DATA_NTF (((REG32(ADR_MRX_DATA_NTF)) & 0x0000ffff ) >> 0)
++#define GET_MRX_MNG_NTF (((REG32(ADR_MRX_MNG_NTF)) & 0x0000ffff ) >> 0)
++#define GET_MRX_DAT_CRC_NTF (((REG32(ADR_MRX_DAT_CRC_NTF)) & 0x0000ffff ) >> 0)
++#define GET_MRX_BAR_NTF (((REG32(ADR_MRX_BAR_NTF)) & 0x0000ffff ) >> 0)
++#define GET_MRX_MB_MISS (((REG32(ADR_MRX_MB_MISS)) & 0x0000ffff ) >> 0)
++#define GET_MRX_NIDLE_MISS (((REG32(ADR_MRX_NIDLE_MISS)) & 0x0000ffff ) >> 0)
++#define GET_MRX_CSR_NTF (((REG32(ADR_MRX_CSR_NTF)) & 0x0000ffff ) >> 0)
++#define GET_DBG_Q0_SUCC (((REG32(ADR_DBG_Q0_FRM_SUCCESS)) & 0x0000ffff ) >> 0)
++#define GET_DBG_Q0_FAIL (((REG32(ADR_DBG_Q0_FRM_FAIL)) & 0x0000ffff ) >> 0)
++#define GET_DBG_Q0_ACK_SUCC (((REG32(ADR_DBG_Q0_ACK_SUCCESS)) & 0x0000ffff ) >> 0)
++#define GET_DBG_Q0_ACK_FAIL (((REG32(ADR_DBG_Q0_ACK_FAIL)) & 0x0000ffff ) >> 0)
++#define GET_DBG_Q1_SUCC (((REG32(ADR_DBG_Q1_FRM_SUCCESS)) & 0x0000ffff ) >> 0)
++#define GET_DBG_Q1_FAIL (((REG32(ADR_DBG_Q1_FRM_FAIL)) & 0x0000ffff ) >> 0)
++#define GET_DBG_Q1_ACK_SUCC (((REG32(ADR_DBG_Q1_ACK_SUCCESS)) & 0x0000ffff ) >> 0)
++#define GET_DBG_Q1_ACK_FAIL (((REG32(ADR_DBG_Q1_ACK_FAIL)) & 0x0000ffff ) >> 0)
++#define GET_DBG_Q2_SUCC (((REG32(ADR_DBG_Q2_FRM_SUCCESS)) & 0x0000ffff ) >> 0)
++#define GET_DBG_Q2_FAIL (((REG32(ADR_DBG_Q2_FRM_FAIL)) & 0x0000ffff ) >> 0)
++#define GET_DBG_Q2_ACK_SUCC (((REG32(ADR_DBG_Q2_ACK_SUCCESS)) & 0x0000ffff ) >> 0)
++#define GET_DBG_Q2_ACK_FAIL (((REG32(ADR_DBG_Q2_ACK_FAIL)) & 0x0000ffff ) >> 0)
++#define GET_DBG_Q3_SUCC (((REG32(ADR_DBG_Q3_FRM_SUCCESS)) & 0x0000ffff ) >> 0)
++#define GET_DBG_Q3_FAIL (((REG32(ADR_DBG_Q3_FRM_FAIL)) & 0x0000ffff ) >> 0)
++#define GET_DBG_Q3_ACK_SUCC (((REG32(ADR_DBG_Q3_ACK_SUCCESS)) & 0x0000ffff ) >> 0)
++#define GET_DBG_Q3_ACK_FAIL (((REG32(ADR_DBG_Q3_ACK_FAIL)) & 0x0000ffff ) >> 0)
++#define GET_SCRT_TKIP_CERR (((REG32(ADR_MIB_SCRT_TKIP0)) & 0x000fffff ) >> 0)
++#define GET_SCRT_TKIP_MIC_ERR (((REG32(ADR_MIB_SCRT_TKIP1)) & 0x000fffff ) >> 0)
++#define GET_SCRT_TKIP_RPLY (((REG32(ADR_MIB_SCRT_TKIP2)) & 0x000fffff ) >> 0)
++#define GET_SCRT_CCMP_RPLY (((REG32(ADR_MIB_SCRT_CCMP0)) & 0x000fffff ) >> 0)
++#define GET_SCRT_CCMP_CERR (((REG32(ADR_MIB_SCRT_CCMP1)) & 0x000fffff ) >> 0)
++#define GET_DBG_LEN_CRC_FAIL (((REG32(ADR_DBG_LEN_CRC_FAIL)) & 0x0000ffff ) >> 0)
++#define GET_DBG_LEN_ALC_FAIL (((REG32(ADR_DBG_LEN_ALC_FAIL)) & 0x0000ffff ) >> 0)
++#define GET_DBG_AMPDU_PASS (((REG32(ADR_DBG_AMPDU_PASS)) & 0x0000ffff ) >> 0)
++#define GET_DBG_AMPDU_FAIL (((REG32(ADR_DBG_AMPDU_FAIL)) & 0x0000ffff ) >> 0)
++#define GET_RXID_ALC_CNT_FAIL (((REG32(ADR_ID_ALC_FAIL1)) & 0x0000ffff ) >> 0)
++#define GET_RXID_ALC_LEN_FAIL (((REG32(ADR_ID_ALC_FAIL2)) & 0x0000ffff ) >> 0)
++#define GET_CBR_RG_EN_MANUAL (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00000001 ) >> 0)
++#define GET_CBR_RG_TX_EN (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00000002 ) >> 1)
++#define GET_CBR_RG_TX_PA_EN (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00000004 ) >> 2)
++#define GET_CBR_RG_TX_DAC_EN (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00000008 ) >> 3)
++#define GET_CBR_RG_RX_AGC (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00000010 ) >> 4)
++#define GET_CBR_RG_RX_GAIN_MANUAL (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00000020 ) >> 5)
++#define GET_CBR_RG_RFG (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x000000c0 ) >> 6)
++#define GET_CBR_RG_PGAG (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00000f00 ) >> 8)
++#define GET_CBR_RG_MODE (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00003000 ) >> 12)
++#define GET_CBR_RG_EN_TX_TRSW (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00004000 ) >> 14)
++#define GET_CBR_RG_EN_SX (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00008000 ) >> 15)
++#define GET_CBR_RG_EN_RX_LNA (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00010000 ) >> 16)
++#define GET_CBR_RG_EN_RX_MIXER (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00020000 ) >> 17)
++#define GET_CBR_RG_EN_RX_DIV2 (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00040000 ) >> 18)
++#define GET_CBR_RG_EN_RX_LOBUF (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00080000 ) >> 19)
++#define GET_CBR_RG_EN_RX_TZ (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00100000 ) >> 20)
++#define GET_CBR_RG_EN_RX_FILTER (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00200000 ) >> 21)
++#define GET_CBR_RG_EN_RX_HPF (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00400000 ) >> 22)
++#define GET_CBR_RG_EN_RX_RSSI (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00800000 ) >> 23)
++#define GET_CBR_RG_EN_ADC (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x01000000 ) >> 24)
++#define GET_CBR_RG_EN_TX_MOD (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x02000000 ) >> 25)
++#define GET_CBR_RG_EN_TX_DIV2 (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x04000000 ) >> 26)
++#define GET_CBR_RG_EN_TX_DIV2_BUF (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x08000000 ) >> 27)
++#define GET_CBR_RG_EN_TX_LOBF (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x10000000 ) >> 28)
++#define GET_CBR_RG_EN_RX_LOBF (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x20000000 ) >> 29)
++#define GET_CBR_RG_SEL_DPLL_CLK (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x40000000 ) >> 30)
++#define GET_CBR_RG_EN_TX_DPD (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000001 ) >> 0)
++#define GET_CBR_RG_EN_TX_TSSI (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000002 ) >> 1)
++#define GET_CBR_RG_EN_RX_IQCAL (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000004 ) >> 2)
++#define GET_CBR_RG_EN_TX_DAC_CAL (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000008 ) >> 3)
++#define GET_CBR_RG_EN_TX_SELF_MIXER (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000010 ) >> 4)
++#define GET_CBR_RG_EN_TX_DAC_OUT (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000020 ) >> 5)
++#define GET_CBR_RG_EN_LDO_RX_FE (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000040 ) >> 6)
++#define GET_CBR_RG_EN_LDO_ABB (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000080 ) >> 7)
++#define GET_CBR_RG_EN_LDO_AFE (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000100 ) >> 8)
++#define GET_CBR_RG_EN_SX_CHPLDO (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000200 ) >> 9)
++#define GET_CBR_RG_EN_SX_LOBFLDO (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000400 ) >> 10)
++#define GET_CBR_RG_EN_IREF_RX (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000800 ) >> 11)
++#define GET_CBR_RG_DCDC_MODE (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00001000 ) >> 12)
++#define GET_CBR_RG_LDO_LEVEL_RX_FE (((REG32(ADR_CBR_LDO_REGISTER)) & 0x00000007 ) >> 0)
++#define GET_CBR_RG_LDO_LEVEL_ABB (((REG32(ADR_CBR_LDO_REGISTER)) & 0x00000038 ) >> 3)
++#define GET_CBR_RG_LDO_LEVEL_AFE (((REG32(ADR_CBR_LDO_REGISTER)) & 0x000001c0 ) >> 6)
++#define GET_CBR_RG_SX_LDO_CHP_LEVEL (((REG32(ADR_CBR_LDO_REGISTER)) & 0x00000e00 ) >> 9)
++#define GET_CBR_RG_SX_LDO_LOBF_LEVEL (((REG32(ADR_CBR_LDO_REGISTER)) & 0x00007000 ) >> 12)
++#define GET_CBR_RG_SX_LDO_XOSC_LEVEL (((REG32(ADR_CBR_LDO_REGISTER)) & 0x00038000 ) >> 15)
++#define GET_CBR_RG_DP_LDO_LEVEL (((REG32(ADR_CBR_LDO_REGISTER)) & 0x001c0000 ) >> 18)
++#define GET_CBR_RG_SX_LDO_VCO_LEVEL (((REG32(ADR_CBR_LDO_REGISTER)) & 0x00e00000 ) >> 21)
++#define GET_CBR_RG_TX_LDO_TX_LEVEL (((REG32(ADR_CBR_LDO_REGISTER)) & 0x07000000 ) >> 24)
++#define GET_CBR_RG_BUCK_LEVEL (((REG32(ADR_CBR_LDO_REGISTER)) & 0x38000000 ) >> 27)
++#define GET_CBR_RG_EN_RX_PADSW (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00000001 ) >> 0)
++#define GET_CBR_RG_EN_RX_TESTNODE (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00000002 ) >> 1)
++#define GET_CBR_RG_RX_ABBCFIX (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00000004 ) >> 2)
++#define GET_CBR_RG_RX_ABBCTUNE (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x000001f8 ) >> 3)
++#define GET_CBR_RG_RX_ABBOUT_TRI_STATE (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00000200 ) >> 9)
++#define GET_CBR_RG_RX_ABB_N_MODE (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00000400 ) >> 10)
++#define GET_CBR_RG_RX_EN_LOOPA (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00000800 ) >> 11)
++#define GET_CBR_RG_RX_FILTERI1ST (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00003000 ) >> 12)
++#define GET_CBR_RG_RX_FILTERI2ND (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x0000c000 ) >> 14)
++#define GET_CBR_RG_RX_FILTERI3RD (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00030000 ) >> 16)
++#define GET_CBR_RG_RX_FILTERI_COURSE (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x000c0000 ) >> 18)
++#define GET_CBR_RG_RX_FILTERVCM (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00300000 ) >> 20)
++#define GET_CBR_RG_RX_HPF3M (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00400000 ) >> 22)
++#define GET_CBR_RG_RX_HPF300K (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00800000 ) >> 23)
++#define GET_CBR_RG_RX_HPFI (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x03000000 ) >> 24)
++#define GET_CBR_RG_RX_HPF_FINALCORNER (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x0c000000 ) >> 26)
++#define GET_CBR_RG_RX_HPF_SETTLE1_C (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x30000000 ) >> 28)
++#define GET_CBR_RG_RX_HPF_SETTLE1_R (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x00000003 ) >> 0)
++#define GET_CBR_RG_RX_HPF_SETTLE2_C (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x0000000c ) >> 2)
++#define GET_CBR_RG_RX_HPF_SETTLE2_R (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x00000030 ) >> 4)
++#define GET_CBR_RG_RX_HPF_VCMCON2 (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x000000c0 ) >> 6)
++#define GET_CBR_RG_RX_HPF_VCMCON (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x00000300 ) >> 8)
++#define GET_CBR_RG_RX_OUTVCM (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x00000c00 ) >> 10)
++#define GET_CBR_RG_RX_TZI (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x00003000 ) >> 12)
++#define GET_CBR_RG_RX_TZ_OUT_TRISTATE (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x00004000 ) >> 14)
++#define GET_CBR_RG_RX_TZ_VCM (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x00018000 ) >> 15)
++#define GET_CBR_RG_EN_RX_RSSI_TESTNODE (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x000e0000 ) >> 17)
++#define GET_CBR_RG_RX_ADCRSSI_CLKSEL (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x00100000 ) >> 20)
++#define GET_CBR_RG_RX_ADCRSSI_VCM (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x00600000 ) >> 21)
++#define GET_CBR_RG_RX_REC_LPFCORNER (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x01800000 ) >> 23)
++#define GET_CBR_RG_RSSI_CLOCK_GATING (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x02000000 ) >> 25)
++#define GET_CBR_RG_TXPGA_CAPSW (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x00000003 ) >> 0)
++#define GET_CBR_RG_TXPGA_MAIN (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x000000fc ) >> 2)
++#define GET_CBR_RG_TXPGA_STEER (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x00003f00 ) >> 8)
++#define GET_CBR_RG_TXMOD_GMCELL (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x0000c000 ) >> 14)
++#define GET_CBR_RG_TXLPF_GMCELL (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x00030000 ) >> 16)
++#define GET_CBR_RG_PACELL_EN (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x001c0000 ) >> 18)
++#define GET_CBR_RG_PABIAS_CTRL (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x01e00000 ) >> 21)
++#define GET_CBR_RG_PABIAS_AB (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x02000000 ) >> 25)
++#define GET_CBR_RG_TX_DIV_VSET (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x0c000000 ) >> 26)
++#define GET_CBR_RG_TX_LOBUF_VSET (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x30000000 ) >> 28)
++#define GET_CBR_RG_RX_SQDC (((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0x00000007 ) >> 0)
++#define GET_CBR_RG_RX_DIV2_CORE (((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0x00000018 ) >> 3)
++#define GET_CBR_RG_RX_LOBUF (((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0x00000060 ) >> 5)
++#define GET_CBR_RG_TX_DPDGM_BIAS (((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0x00000780 ) >> 7)
++#define GET_CBR_RG_TX_DPD_DIV (((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0x00007800 ) >> 11)
++#define GET_CBR_RG_TX_TSSI_BIAS (((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0x00038000 ) >> 15)
++#define GET_CBR_RG_TX_TSSI_DIV (((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0x001c0000 ) >> 18)
++#define GET_CBR_RG_TX_TSSI_TESTMODE (((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0x00200000 ) >> 21)
++#define GET_CBR_RG_TX_TSSI_TEST (((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0x00c00000 ) >> 22)
++#define GET_CBR_RG_RX_HG_LNA_GC (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x00000003 ) >> 0)
++#define GET_CBR_RG_RX_HG_LNAHGN_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x0000003c ) >> 2)
++#define GET_CBR_RG_RX_HG_LNAHGP_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x000003c0 ) >> 6)
++#define GET_CBR_RG_RX_HG_LNALG_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x00003c00 ) >> 10)
++#define GET_CBR_RG_RX_HG_TZ_GC (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x0000c000 ) >> 14)
++#define GET_CBR_RG_RX_HG_TZ_CAP (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x00070000 ) >> 16)
++#define GET_CBR_RG_RX_MG_LNA_GC (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x00000003 ) >> 0)
++#define GET_CBR_RG_RX_MG_LNAHGN_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x0000003c ) >> 2)
++#define GET_CBR_RG_RX_MG_LNAHGP_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x000003c0 ) >> 6)
++#define GET_CBR_RG_RX_MG_LNALG_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x00003c00 ) >> 10)
++#define GET_CBR_RG_RX_MG_TZ_GC (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x0000c000 ) >> 14)
++#define GET_CBR_RG_RX_MG_TZ_CAP (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x00070000 ) >> 16)
++#define GET_CBR_RG_RX_LG_LNA_GC (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x00000003 ) >> 0)
++#define GET_CBR_RG_RX_LG_LNAHGN_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x0000003c ) >> 2)
++#define GET_CBR_RG_RX_LG_LNAHGP_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x000003c0 ) >> 6)
++#define GET_CBR_RG_RX_LG_LNALG_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x00003c00 ) >> 10)
++#define GET_CBR_RG_RX_LG_TZ_GC (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x0000c000 ) >> 14)
++#define GET_CBR_RG_RX_LG_TZ_CAP (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x00070000 ) >> 16)
++#define GET_CBR_RG_RX_ULG_LNA_GC (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x00000003 ) >> 0)
++#define GET_CBR_RG_RX_ULG_LNAHGN_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x0000003c ) >> 2)
++#define GET_CBR_RG_RX_ULG_LNAHGP_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x000003c0 ) >> 6)
++#define GET_CBR_RG_RX_ULG_LNALG_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x00003c00 ) >> 10)
++#define GET_CBR_RG_RX_ULG_TZ_GC (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x0000c000 ) >> 14)
++#define GET_CBR_RG_RX_ULG_TZ_CAP (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x00070000 ) >> 16)
++#define GET_CBR_RG_HPF1_FAST_SET_X (((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0x00000001 ) >> 0)
++#define GET_CBR_RG_HPF1_FAST_SET_Y (((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0x00000002 ) >> 1)
++#define GET_CBR_RG_HPF1_FAST_SET_Z (((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0x00000004 ) >> 2)
++#define GET_CBR_RG_HPF_T1A (((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0x00000018 ) >> 3)
++#define GET_CBR_RG_HPF_T1B (((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0x00000060 ) >> 5)
++#define GET_CBR_RG_HPF_T1C (((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0x00000180 ) >> 7)
++#define GET_CBR_RG_RX_LNA_TRI_SEL (((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0x00000600 ) >> 9)
++#define GET_CBR_RG_RX_LNA_SETTLE (((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0x00001800 ) >> 11)
++#define GET_CBR_RG_ADC_CLKSEL (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x00000001 ) >> 0)
++#define GET_CBR_RG_ADC_DIBIAS (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x00000006 ) >> 1)
++#define GET_CBR_RG_ADC_DIVR (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x00000008 ) >> 3)
++#define GET_CBR_RG_ADC_DVCMI (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x00000030 ) >> 4)
++#define GET_CBR_RG_ADC_SAMSEL (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x000003c0 ) >> 6)
++#define GET_CBR_RG_ADC_STNBY (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x00000400 ) >> 10)
++#define GET_CBR_RG_ADC_TESTMODE (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x00000800 ) >> 11)
++#define GET_CBR_RG_ADC_TSEL (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x0000f000 ) >> 12)
++#define GET_CBR_RG_ADC_VRSEL (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x00030000 ) >> 16)
++#define GET_CBR_RG_DICMP (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x000c0000 ) >> 18)
++#define GET_CBR_RG_DIOP (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x00300000 ) >> 20)
++#define GET_CBR_RG_DACI1ST (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x00000003 ) >> 0)
++#define GET_CBR_RG_TX_DACLPF_ICOURSE (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x0000000c ) >> 2)
++#define GET_CBR_RG_TX_DACLPF_IFINE (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x00000030 ) >> 4)
++#define GET_CBR_RG_TX_DACLPF_VCM (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x000000c0 ) >> 6)
++#define GET_CBR_RG_TX_DAC_CKEDGE_SEL (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x00000100 ) >> 8)
++#define GET_CBR_RG_TX_DAC_IBIAS (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x00000600 ) >> 9)
++#define GET_CBR_RG_TX_DAC_OS (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x00003800 ) >> 11)
++#define GET_CBR_RG_TX_DAC_RCAL (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x0000c000 ) >> 14)
++#define GET_CBR_RG_TX_DAC_TSEL (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x000f0000 ) >> 16)
++#define GET_CBR_RG_TX_EN_VOLTAGE_IN (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x00100000 ) >> 20)
++#define GET_CBR_RG_TXLPF_BYPASS (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x00200000 ) >> 21)
++#define GET_CBR_RG_TXLPF_BOOSTI (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x00400000 ) >> 22)
++#define GET_CBR_RG_EN_SX_R3 (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000001 ) >> 0)
++#define GET_CBR_RG_EN_SX_CH (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000002 ) >> 1)
++#define GET_CBR_RG_EN_SX_CHP (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000004 ) >> 2)
++#define GET_CBR_RG_EN_SX_DIVCK (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000008 ) >> 3)
++#define GET_CBR_RG_EN_SX_VCOBF (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000010 ) >> 4)
++#define GET_CBR_RG_EN_SX_VCO (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000020 ) >> 5)
++#define GET_CBR_RG_EN_SX_MOD (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000040 ) >> 6)
++#define GET_CBR_RG_EN_SX_LCK (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000080 ) >> 7)
++#define GET_CBR_RG_EN_SX_DITHER (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000100 ) >> 8)
++#define GET_CBR_RG_EN_SX_DELCAL (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000200 ) >> 9)
++#define GET_CBR_RG_EN_SX_PC_BYPASS (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000400 ) >> 10)
++#define GET_CBR_RG_EN_SX_VT_MON (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000800 ) >> 11)
++#define GET_CBR_RG_EN_SX_VT_MON_DG (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00001000 ) >> 12)
++#define GET_CBR_RG_EN_SX_DIV (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00002000 ) >> 13)
++#define GET_CBR_RG_EN_SX_LPF (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00004000 ) >> 14)
++#define GET_CBR_RG_SX_RFCTRL_F (((REG32(ADR_CBR_SYN_RGISTER_1)) & 0x00ffffff ) >> 0)
++#define GET_CBR_RG_SX_SEL_CP (((REG32(ADR_CBR_SYN_RGISTER_1)) & 0x0f000000 ) >> 24)
++#define GET_CBR_RG_SX_SEL_CS (((REG32(ADR_CBR_SYN_RGISTER_1)) & 0xf0000000 ) >> 28)
++#define GET_CBR_RG_SX_RFCTRL_CH (((REG32(ADR_CBR_SYN_RGISTER_2)) & 0x000007ff ) >> 0)
++#define GET_CBR_RG_SX_SEL_C3 (((REG32(ADR_CBR_SYN_RGISTER_2)) & 0x00007800 ) >> 11)
++#define GET_CBR_RG_SX_SEL_RS (((REG32(ADR_CBR_SYN_RGISTER_2)) & 0x000f8000 ) >> 15)
++#define GET_CBR_RG_SX_SEL_R3 (((REG32(ADR_CBR_SYN_RGISTER_2)) & 0x01f00000 ) >> 20)
++#define GET_CBR_RG_SX_SEL_ICHP (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x0000001f ) >> 0)
++#define GET_CBR_RG_SX_SEL_PCHP (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x000003e0 ) >> 5)
++#define GET_CBR_RG_SX_SEL_CHP_REGOP (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x00003c00 ) >> 10)
++#define GET_CBR_RG_SX_SEL_CHP_UNIOP (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x0003c000 ) >> 14)
++#define GET_CBR_RG_SX_CHP_IOST_POL (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x00040000 ) >> 18)
++#define GET_CBR_RG_SX_CHP_IOST (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x00380000 ) >> 19)
++#define GET_CBR_RG_SX_PFDSEL (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x00400000 ) >> 22)
++#define GET_CBR_RG_SX_PFD_SET (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x00800000 ) >> 23)
++#define GET_CBR_RG_SX_PFD_SET1 (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x01000000 ) >> 24)
++#define GET_CBR_RG_SX_PFD_SET2 (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x02000000 ) >> 25)
++#define GET_CBR_RG_SX_VBNCAS_SEL (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x04000000 ) >> 26)
++#define GET_CBR_RG_SX_PFD_RST_H (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x08000000 ) >> 27)
++#define GET_CBR_RG_SX_PFD_TRUP (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x10000000 ) >> 28)
++#define GET_CBR_RG_SX_PFD_TRDN (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x20000000 ) >> 29)
++#define GET_CBR_RG_SX_PFD_TRSEL (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x40000000 ) >> 30)
++#define GET_CBR_RG_SX_VCOBA_R (((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0x00000007 ) >> 0)
++#define GET_CBR_RG_SX_VCORSEL (((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0x000000f8 ) >> 3)
++#define GET_CBR_RG_SX_VCOCUSEL (((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0x00000f00 ) >> 8)
++#define GET_CBR_RG_SX_RXBFSEL (((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0x0000f000 ) >> 12)
++#define GET_CBR_RG_SX_TXBFSEL (((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0x000f0000 ) >> 16)
++#define GET_CBR_RG_SX_VCOBFSEL (((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0x00f00000 ) >> 20)
++#define GET_CBR_RG_SX_DIVBFSEL (((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0x0f000000 ) >> 24)
++#define GET_CBR_RG_SX_GNDR_SEL (((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0xf0000000 ) >> 28)
++#define GET_CBR_RG_SX_DITHER_WEIGHT (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00000003 ) >> 0)
++#define GET_CBR_RG_SX_MOD_ERRCMP (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x0000000c ) >> 2)
++#define GET_CBR_RG_SX_MOD_ORDER (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00000030 ) >> 4)
++#define GET_CBR_RG_SX_SDM_D1 (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00000040 ) >> 6)
++#define GET_CBR_RG_SX_SDM_D2 (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00000080 ) >> 7)
++#define GET_CBR_RG_SDM_PASS (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00000100 ) >> 8)
++#define GET_CBR_RG_SX_RST_H_DIV (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00000200 ) >> 9)
++#define GET_CBR_RG_SX_SDM_EDGE (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00000400 ) >> 10)
++#define GET_CBR_RG_SX_XO_GM (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00001800 ) >> 11)
++#define GET_CBR_RG_SX_REFBYTWO (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00002000 ) >> 13)
++#define GET_CBR_RG_SX_XO_SWCAP (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x0003c000 ) >> 14)
++#define GET_CBR_RG_SX_SDMLUT_INV (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00040000 ) >> 18)
++#define GET_CBR_RG_SX_LCKEN (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00080000 ) >> 19)
++#define GET_CBR_RG_SX_PREVDD (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00f00000 ) >> 20)
++#define GET_CBR_RG_SX_PSCONTERVDD (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x0f000000 ) >> 24)
++#define GET_CBR_RG_SX_MOD_ERR_DELAY (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x30000000 ) >> 28)
++#define GET_CBR_RG_SX_MODDB (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x40000000 ) >> 30)
++#define GET_CBR_RG_SX_CV_CURVE_SEL (((REG32(ADR_CBR_SYN_LCK1)) & 0x00000003 ) >> 0)
++#define GET_CBR_RG_SX_SEL_DELAY (((REG32(ADR_CBR_SYN_LCK1)) & 0x0000007c ) >> 2)
++#define GET_CBR_RG_SX_REF_CYCLE (((REG32(ADR_CBR_SYN_LCK1)) & 0x00000780 ) >> 7)
++#define GET_CBR_RG_SX_VCOBY16 (((REG32(ADR_CBR_SYN_LCK1)) & 0x00000800 ) >> 11)
++#define GET_CBR_RG_SX_VCOBY32 (((REG32(ADR_CBR_SYN_LCK1)) & 0x00001000 ) >> 12)
++#define GET_CBR_RG_SX_PH (((REG32(ADR_CBR_SYN_LCK1)) & 0x00002000 ) >> 13)
++#define GET_CBR_RG_SX_PL (((REG32(ADR_CBR_SYN_LCK1)) & 0x00004000 ) >> 14)
++#define GET_CBR_RG_SX_VT_MON_MODE (((REG32(ADR_CBR_SYN_LCK2)) & 0x00000001 ) >> 0)
++#define GET_CBR_RG_SX_VT_TH_HI (((REG32(ADR_CBR_SYN_LCK2)) & 0x00000006 ) >> 1)
++#define GET_CBR_RG_SX_VT_TH_LO (((REG32(ADR_CBR_SYN_LCK2)) & 0x00000018 ) >> 3)
++#define GET_CBR_RG_SX_VT_SET (((REG32(ADR_CBR_SYN_LCK2)) & 0x00000020 ) >> 5)
++#define GET_CBR_RG_SX_VT_MON_TMR (((REG32(ADR_CBR_SYN_LCK2)) & 0x00007fc0 ) >> 6)
++#define GET_CBR_RG_IDEAL_CYCLE (((REG32(ADR_CBR_SYN_LCK2)) & 0x0fff8000 ) >> 15)
++#define GET_CBR_RG_EN_DP_VT_MON (((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0x00000001 ) >> 0)
++#define GET_CBR_RG_DP_VT_TH_HI (((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0x00000006 ) >> 1)
++#define GET_CBR_RG_DP_VT_TH_LO (((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0x00000018 ) >> 3)
++#define GET_CBR_RG_DP_VT_MON_TMR (((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0x00003fe0 ) >> 5)
++#define GET_CBR_RG_DP_CK320BY2 (((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0x00004000 ) >> 14)
++#define GET_CBR_RG_SX_DELCTRL (((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0x001f8000 ) >> 15)
++#define GET_CBR_RG_DP_OD_TEST (((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0x00200000 ) >> 21)
++#define GET_CBR_RG_DP_BBPLL_BP (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x00000001 ) >> 0)
++#define GET_CBR_RG_DP_BBPLL_ICP (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x00000006 ) >> 1)
++#define GET_CBR_RG_DP_BBPLL_IDUAL (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x00000018 ) >> 3)
++#define GET_CBR_RG_DP_BBPLL_OD_TEST (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x000001e0 ) >> 5)
++#define GET_CBR_RG_DP_BBPLL_PD (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x00000200 ) >> 9)
++#define GET_CBR_RG_DP_BBPLL_TESTSEL (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x00001c00 ) >> 10)
++#define GET_CBR_RG_DP_BBPLL_PFD_DLY (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x00006000 ) >> 13)
++#define GET_CBR_RG_DP_RP (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x00038000 ) >> 15)
++#define GET_CBR_RG_DP_RHP (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x000c0000 ) >> 18)
++#define GET_CBR_RG_DP_DR3 (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x00700000 ) >> 20)
++#define GET_CBR_RG_DP_DCP (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x07800000 ) >> 23)
++#define GET_CBR_RG_DP_DCS (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x78000000 ) >> 27)
++#define GET_CBR_RG_DP_FBDIV (((REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) & 0x00000fff ) >> 0)
++#define GET_CBR_RG_DP_FODIV (((REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) & 0x003ff000 ) >> 12)
++#define GET_CBR_RG_DP_REFDIV (((REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) & 0xffc00000 ) >> 22)
++#define GET_CBR_RG_IDACAI_PGAG15 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) & 0x0000003f ) >> 0)
++#define GET_CBR_RG_IDACAQ_PGAG15 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) & 0x00000fc0 ) >> 6)
++#define GET_CBR_RG_IDACAI_PGAG14 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) & 0x0003f000 ) >> 12)
++#define GET_CBR_RG_IDACAQ_PGAG14 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) & 0x00fc0000 ) >> 18)
++#define GET_CBR_RG_IDACAI_PGAG13 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) & 0x0000003f ) >> 0)
++#define GET_CBR_RG_IDACAQ_PGAG13 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) & 0x00000fc0 ) >> 6)
++#define GET_CBR_RG_IDACAI_PGAG12 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) & 0x0003f000 ) >> 12)
++#define GET_CBR_RG_IDACAQ_PGAG12 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) & 0x00fc0000 ) >> 18)
++#define GET_CBR_RG_IDACAI_PGAG11 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) & 0x0000003f ) >> 0)
++#define GET_CBR_RG_IDACAQ_PGAG11 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) & 0x00000fc0 ) >> 6)
++#define GET_CBR_RG_IDACAI_PGAG10 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) & 0x0003f000 ) >> 12)
++#define GET_CBR_RG_IDACAQ_PGAG10 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) & 0x00fc0000 ) >> 18)
++#define GET_CBR_RG_IDACAI_PGAG9 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) & 0x0000003f ) >> 0)
++#define GET_CBR_RG_IDACAQ_PGAG9 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) & 0x00000fc0 ) >> 6)
++#define GET_CBR_RG_IDACAI_PGAG8 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) & 0x0003f000 ) >> 12)
++#define GET_CBR_RG_IDACAQ_PGAG8 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) & 0x00fc0000 ) >> 18)
++#define GET_CBR_RG_IDACAI_PGAG7 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) & 0x0000003f ) >> 0)
++#define GET_CBR_RG_IDACAQ_PGAG7 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) & 0x00000fc0 ) >> 6)
++#define GET_CBR_RG_IDACAI_PGAG6 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) & 0x0003f000 ) >> 12)
++#define GET_CBR_RG_IDACAQ_PGAG6 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) & 0x00fc0000 ) >> 18)
++#define GET_CBR_RG_IDACAI_PGAG5 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) & 0x0000003f ) >> 0)
++#define GET_CBR_RG_IDACAQ_PGAG5 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) & 0x00000fc0 ) >> 6)
++#define GET_CBR_RG_IDACAI_PGAG4 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) & 0x0003f000 ) >> 12)
++#define GET_CBR_RG_IDACAQ_PGAG4 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) & 0x00fc0000 ) >> 18)
++#define GET_CBR_RG_IDACAI_PGAG3 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) & 0x0000003f ) >> 0)
++#define GET_CBR_RG_IDACAQ_PGAG3 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) & 0x00000fc0 ) >> 6)
++#define GET_CBR_RG_IDACAI_PGAG2 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) & 0x0003f000 ) >> 12)
++#define GET_CBR_RG_IDACAQ_PGAG2 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) & 0x00fc0000 ) >> 18)
++#define GET_CBR_RG_IDACAI_PGAG1 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) & 0x0000003f ) >> 0)
++#define GET_CBR_RG_IDACAQ_PGAG1 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) & 0x00000fc0 ) >> 6)
++#define GET_CBR_RG_IDACAI_PGAG0 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) & 0x0003f000 ) >> 12)
++#define GET_CBR_RG_IDACAQ_PGAG0 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) & 0x00fc0000 ) >> 18)
++#define GET_CBR_RG_EN_RCAL (((REG32(ADR_CBR_RCAL_REGISTER)) & 0x00000001 ) >> 0)
++#define GET_CBR_RG_RCAL_SPD (((REG32(ADR_CBR_RCAL_REGISTER)) & 0x00000002 ) >> 1)
++#define GET_CBR_RG_RCAL_TMR (((REG32(ADR_CBR_RCAL_REGISTER)) & 0x000001fc ) >> 2)
++#define GET_CBR_RG_RCAL_CODE_CWR (((REG32(ADR_CBR_RCAL_REGISTER)) & 0x00000200 ) >> 9)
++#define GET_CBR_RG_RCAL_CODE_CWD (((REG32(ADR_CBR_RCAL_REGISTER)) & 0x00007c00 ) >> 10)
++#define GET_CBR_RG_SX_SUB_SEL_CWR (((REG32(ADR_CBR_MANUAL_REGISTER)) & 0x00000001 ) >> 0)
++#define GET_CBR_RG_SX_SUB_SEL_CWD (((REG32(ADR_CBR_MANUAL_REGISTER)) & 0x000000fe ) >> 1)
++#define GET_CBR_RG_DP_BBPLL_BS_CWR (((REG32(ADR_CBR_MANUAL_REGISTER)) & 0x00000100 ) >> 8)
++#define GET_CBR_RG_DP_BBPLL_BS_CWD (((REG32(ADR_CBR_MANUAL_REGISTER)) & 0x00007e00 ) >> 9)
++#define GET_CBR_RCAL_RDY (((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0x00000001 ) >> 0)
++#define GET_CBR_DA_LCK_RDY (((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0x00000002 ) >> 1)
++#define GET_CBR_VT_MON_RDY (((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0x00000004 ) >> 2)
++#define GET_CBR_DP_VT_MON_RDY (((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0x00000008 ) >> 3)
++#define GET_CBR_CH_RDY (((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0x00000010 ) >> 4)
++#define GET_CBR_DA_R_CODE_LUT (((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0x000007c0 ) >> 6)
++#define GET_CBR_AD_SX_VT_MON_Q (((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0x00001800 ) >> 11)
++#define GET_CBR_AD_DP_VT_MON_Q (((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0x00006000 ) >> 13)
++#define GET_CBR_DA_R_CAL_CODE (((REG32(ADR_CBR_READ_ONLY_FLAGS_2)) & 0x0000001f ) >> 0)
++#define GET_CBR_DA_SX_SUB_SEL (((REG32(ADR_CBR_READ_ONLY_FLAGS_2)) & 0x00000fe0 ) >> 5)
++#define GET_CBR_DA_DP_BBPLL_BS (((REG32(ADR_CBR_READ_ONLY_FLAGS_2)) & 0x0003f000 ) >> 12)
++#define GET_CBR_TX_EN (((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0x00000001 ) >> 0)
++#define GET_CBR_TX_CNT_RST (((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0x00000002 ) >> 1)
++#define GET_CBR_IFS_TIME (((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0x000000fc ) >> 2)
++#define GET_CBR_LENGTH_TARGET (((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0x000fff00 ) >> 8)
++#define GET_CBR_TX_CNT_TARGET (((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0xff000000 ) >> 24)
++#define GET_CBR_TC_CNT_TARGET (((REG32(ADR_CBR_RG_PKT_GEN_1)) & 0x00ffffff ) >> 0)
++#define GET_CBR_PLCP_PSDU_DATA_MEM (((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0x000000ff ) >> 0)
++#define GET_CBR_PLCP_PSDU_PREAMBLE_SHORT (((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0x00000100 ) >> 8)
++#define GET_CBR_PLCP_BYTE_LENGTH (((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0x001ffe00 ) >> 9)
++#define GET_CBR_PLCP_PSDU_RATE (((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0x00600000 ) >> 21)
++#define GET_CBR_TAIL_TIME (((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0x1f800000 ) >> 23)
++#define GET_CBR_RG_O_PAD_PD (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00000001 ) >> 0)
++#define GET_CBR_RG_I_PAD_PD (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00000002 ) >> 1)
++#define GET_CBR_SEL_ADCKP_INV (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00000004 ) >> 2)
++#define GET_CBR_RG_PAD_DS (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00000008 ) >> 3)
++#define GET_CBR_SEL_ADCKP_MUX (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00000010 ) >> 4)
++#define GET_CBR_RG_PAD_DS_CLK (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00000020 ) >> 5)
++#define GET_CBR_INTP_SEL (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00000200 ) >> 9)
++#define GET_CBR_IQ_SWP (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00000400 ) >> 10)
++#define GET_CBR_RG_EN_EXT_DA (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00000800 ) >> 11)
++#define GET_CBR_RG_DIS_DA_OFFSET (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00001000 ) >> 12)
++#define GET_CBR_DBG_SEL (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x000f0000 ) >> 16)
++#define GET_CBR_DBG_EN (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00100000 ) >> 20)
++#define GET_CBR_RG_PKT_GEN_TX_CNT (((REG32(ADR_CBR_RG_PKT_GEN_TXCNT)) & 0xffffffff ) >> 0)
++#define GET_CBR_TP_SEL (((REG32(ADR_CBR_PATTERN_GEN)) & 0x0000001f ) >> 0)
++#define GET_CBR_IDEAL_IQ_EN (((REG32(ADR_CBR_PATTERN_GEN)) & 0x00000020 ) >> 5)
++#define GET_CBR_DATA_OUT_SEL (((REG32(ADR_CBR_PATTERN_GEN)) & 0x000001c0 ) >> 6)
++#define GET_CBR_TWO_TONE_EN (((REG32(ADR_CBR_PATTERN_GEN)) & 0x00000200 ) >> 9)
++#define GET_CBR_FREQ_SEL (((REG32(ADR_CBR_PATTERN_GEN)) & 0x00ff0000 ) >> 16)
++#define GET_CBR_IQ_SCALE (((REG32(ADR_CBR_PATTERN_GEN)) & 0xff000000 ) >> 24)
++#define GET_CPU_QUE_POP (((REG32(ADR_MB_CPU_INT)) & 0x00000001 ) >> 0)
++#define GET_CPU_INT (((REG32(ADR_MB_CPU_INT)) & 0x00000004 ) >> 2)
++#define GET_CPU_ID_TB0 (((REG32(ADR_CPU_ID_TB0)) & 0xffffffff ) >> 0)
++#define GET_CPU_ID_TB1 (((REG32(ADR_CPU_ID_TB1)) & 0xffffffff ) >> 0)
++#define GET_HW_PKTID (((REG32(ADR_CH0_TRIG_1)) & 0x000007ff ) >> 0)
++#define GET_CH0_INT_ADDR (((REG32(ADR_CH0_TRIG_0)) & 0xffffffff ) >> 0)
++#define GET_PRI_HW_PKTID (((REG32(ADR_CH0_PRI_TRIG)) & 0x000007ff ) >> 0)
++#define GET_CH0_FULL (((REG32(ADR_MCU_STATUS)) & 0x00000001 ) >> 0)
++#define GET_FF0_EMPTY (((REG32(ADR_MCU_STATUS)) & 0x00000002 ) >> 1)
++#define GET_RLS_BUSY (((REG32(ADR_MCU_STATUS)) & 0x00000200 ) >> 9)
++#define GET_RLS_COUNT_CLR (((REG32(ADR_MCU_STATUS)) & 0x00000400 ) >> 10)
++#define GET_RTN_COUNT_CLR (((REG32(ADR_MCU_STATUS)) & 0x00000800 ) >> 11)
++#define GET_RLS_COUNT (((REG32(ADR_MCU_STATUS)) & 0x00ff0000 ) >> 16)
++#define GET_RTN_COUNT (((REG32(ADR_MCU_STATUS)) & 0xff000000 ) >> 24)
++#define GET_FF0_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0x0000001f ) >> 0)
++#define GET_FF1_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0x000001e0 ) >> 5)
++#define GET_FF3_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0x00003800 ) >> 11)
++#define GET_FF5_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0x000e0000 ) >> 17)
++#define GET_FF6_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0x00700000 ) >> 20)
++#define GET_FF7_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0x03800000 ) >> 23)
++#define GET_FF8_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0x1c000000 ) >> 26)
++#define GET_FF9_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0xe0000000 ) >> 29)
++#define GET_FF10_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x00000007 ) >> 0)
++#define GET_FF11_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x00000038 ) >> 3)
++#define GET_FF12_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x000001c0 ) >> 6)
++#define GET_FF13_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x00000600 ) >> 9)
++#define GET_FF14_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x00001800 ) >> 11)
++#define GET_FF15_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x00006000 ) >> 13)
++#define GET_FF4_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x000f8000 ) >> 15)
++#define GET_FF2_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x00700000 ) >> 20)
++#define GET_CH1_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000002 ) >> 1)
++#define GET_CH2_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000004 ) >> 2)
++#define GET_CH3_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000008 ) >> 3)
++#define GET_CH4_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000010 ) >> 4)
++#define GET_CH5_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000020 ) >> 5)
++#define GET_CH6_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000040 ) >> 6)
++#define GET_CH7_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000080 ) >> 7)
++#define GET_CH8_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000100 ) >> 8)
++#define GET_CH9_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000200 ) >> 9)
++#define GET_CH10_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000400 ) >> 10)
++#define GET_CH11_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000800 ) >> 11)
++#define GET_CH12_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00001000 ) >> 12)
++#define GET_CH13_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00002000 ) >> 13)
++#define GET_CH14_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00004000 ) >> 14)
++#define GET_CH15_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00008000 ) >> 15)
++#define GET_HALT_CH0 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000001 ) >> 0)
++#define GET_HALT_CH1 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000002 ) >> 1)
++#define GET_HALT_CH2 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000004 ) >> 2)
++#define GET_HALT_CH3 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000008 ) >> 3)
++#define GET_HALT_CH4 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000010 ) >> 4)
++#define GET_HALT_CH5 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000020 ) >> 5)
++#define GET_HALT_CH6 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000040 ) >> 6)
++#define GET_HALT_CH7 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000080 ) >> 7)
++#define GET_HALT_CH8 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000100 ) >> 8)
++#define GET_HALT_CH9 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000200 ) >> 9)
++#define GET_HALT_CH10 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000400 ) >> 10)
++#define GET_HALT_CH11 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000800 ) >> 11)
++#define GET_HALT_CH12 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00001000 ) >> 12)
++#define GET_HALT_CH13 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00002000 ) >> 13)
++#define GET_HALT_CH14 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00004000 ) >> 14)
++#define GET_HALT_CH15 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00008000 ) >> 15)
++#define GET_STOP_MBOX (((REG32(ADR_MBOX_HALT_CFG)) & 0x00010000 ) >> 16)
++#define GET_MB_ERR_AUTO_HALT_EN (((REG32(ADR_MBOX_HALT_CFG)) & 0x00100000 ) >> 20)
++#define GET_MB_EXCEPT_CLR (((REG32(ADR_MBOX_HALT_CFG)) & 0x00200000 ) >> 21)
++#define GET_MB_EXCEPT_CASE (((REG32(ADR_MBOX_HALT_CFG)) & 0xff000000 ) >> 24)
++#define GET_MB_DBG_TIME_STEP (((REG32(ADR_MB_DBG_CFG1)) & 0x0000ffff ) >> 0)
++#define GET_DBG_TYPE (((REG32(ADR_MB_DBG_CFG1)) & 0x00030000 ) >> 16)
++#define GET_MB_DBG_CLR (((REG32(ADR_MB_DBG_CFG1)) & 0x00040000 ) >> 18)
++#define GET_DBG_ALC_LOG_EN (((REG32(ADR_MB_DBG_CFG1)) & 0x00080000 ) >> 19)
++#define GET_MB_DBG_COUNTER_EN (((REG32(ADR_MB_DBG_CFG1)) & 0x01000000 ) >> 24)
++#define GET_MB_DBG_EN (((REG32(ADR_MB_DBG_CFG1)) & 0x80000000 ) >> 31)
++#define GET_MB_DBG_RECORD_CNT (((REG32(ADR_MB_DBG_CFG2)) & 0x0000ffff ) >> 0)
++#define GET_MB_DBG_LENGTH (((REG32(ADR_MB_DBG_CFG2)) & 0xffff0000 ) >> 16)
++#define GET_MB_DBG_CFG_ADDR (((REG32(ADR_MB_DBG_CFG3)) & 0xffffffff ) >> 0)
++#define GET_DBG_HWID0_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000001 ) >> 0)
++#define GET_DBG_HWID1_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000002 ) >> 1)
++#define GET_DBG_HWID2_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000004 ) >> 2)
++#define GET_DBG_HWID3_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000008 ) >> 3)
++#define GET_DBG_HWID4_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000010 ) >> 4)
++#define GET_DBG_HWID5_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000020 ) >> 5)
++#define GET_DBG_HWID6_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000040 ) >> 6)
++#define GET_DBG_HWID7_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000080 ) >> 7)
++#define GET_DBG_HWID8_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000100 ) >> 8)
++#define GET_DBG_HWID9_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000200 ) >> 9)
++#define GET_DBG_HWID10_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000400 ) >> 10)
++#define GET_DBG_HWID11_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000800 ) >> 11)
++#define GET_DBG_HWID12_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00001000 ) >> 12)
++#define GET_DBG_HWID13_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00002000 ) >> 13)
++#define GET_DBG_HWID14_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00004000 ) >> 14)
++#define GET_DBG_HWID15_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00008000 ) >> 15)
++#define GET_DBG_HWID0_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00010000 ) >> 16)
++#define GET_DBG_HWID1_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00020000 ) >> 17)
++#define GET_DBG_HWID2_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00040000 ) >> 18)
++#define GET_DBG_HWID3_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00080000 ) >> 19)
++#define GET_DBG_HWID4_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00100000 ) >> 20)
++#define GET_DBG_HWID5_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00200000 ) >> 21)
++#define GET_DBG_HWID6_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00400000 ) >> 22)
++#define GET_DBG_HWID7_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00800000 ) >> 23)
++#define GET_DBG_HWID8_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x01000000 ) >> 24)
++#define GET_DBG_HWID9_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x02000000 ) >> 25)
++#define GET_DBG_HWID10_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x04000000 ) >> 26)
++#define GET_DBG_HWID11_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x08000000 ) >> 27)
++#define GET_DBG_HWID12_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x10000000 ) >> 28)
++#define GET_DBG_HWID13_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x20000000 ) >> 29)
++#define GET_DBG_HWID14_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x40000000 ) >> 30)
++#define GET_DBG_HWID15_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x80000000 ) >> 31)
++#define GET_MB_OUT_QUEUE_EN (((REG32(ADR_MB_OUT_QUEUE_CFG)) & 0x00000002 ) >> 1)
++#define GET_CH0_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000001 ) >> 0)
++#define GET_CH1_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000002 ) >> 1)
++#define GET_CH2_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000004 ) >> 2)
++#define GET_CH3_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000008 ) >> 3)
++#define GET_CH4_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000010 ) >> 4)
++#define GET_CH5_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000020 ) >> 5)
++#define GET_CH6_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000040 ) >> 6)
++#define GET_CH7_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000080 ) >> 7)
++#define GET_CH8_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000100 ) >> 8)
++#define GET_CH9_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000200 ) >> 9)
++#define GET_CH10_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000400 ) >> 10)
++#define GET_CH11_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000800 ) >> 11)
++#define GET_CH12_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00001000 ) >> 12)
++#define GET_CH13_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00002000 ) >> 13)
++#define GET_CH14_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00004000 ) >> 14)
++#define GET_CH15_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00008000 ) >> 15)
++#define GET_FFO0_CNT (((REG32(ADR_RD_FFOUT_CNT1)) & 0x0000001f ) >> 0)
++#define GET_FFO1_CNT (((REG32(ADR_RD_FFOUT_CNT1)) & 0x000003e0 ) >> 5)
++#define GET_FFO2_CNT (((REG32(ADR_RD_FFOUT_CNT1)) & 0x00000c00 ) >> 10)
++#define GET_FFO3_CNT (((REG32(ADR_RD_FFOUT_CNT1)) & 0x000f8000 ) >> 15)
++#define GET_FFO4_CNT (((REG32(ADR_RD_FFOUT_CNT1)) & 0x00300000 ) >> 20)
++#define GET_FFO5_CNT (((REG32(ADR_RD_FFOUT_CNT1)) & 0x0e000000 ) >> 25)
++#define GET_FFO6_CNT (((REG32(ADR_RD_FFOUT_CNT2)) & 0x0000000f ) >> 0)
++#define GET_FFO7_CNT (((REG32(ADR_RD_FFOUT_CNT2)) & 0x000003e0 ) >> 5)
++#define GET_FFO8_CNT (((REG32(ADR_RD_FFOUT_CNT2)) & 0x00007c00 ) >> 10)
++#define GET_FFO9_CNT (((REG32(ADR_RD_FFOUT_CNT2)) & 0x000f8000 ) >> 15)
++#define GET_FFO10_CNT (((REG32(ADR_RD_FFOUT_CNT2)) & 0x00f00000 ) >> 20)
++#define GET_FFO11_CNT (((REG32(ADR_RD_FFOUT_CNT2)) & 0x3e000000 ) >> 25)
++#define GET_FFO12_CNT (((REG32(ADR_RD_FFOUT_CNT3)) & 0x00000007 ) >> 0)
++#define GET_FFO13_CNT (((REG32(ADR_RD_FFOUT_CNT3)) & 0x00000060 ) >> 5)
++#define GET_FFO14_CNT (((REG32(ADR_RD_FFOUT_CNT3)) & 0x00000c00 ) >> 10)
++#define GET_FFO15_CNT (((REG32(ADR_RD_FFOUT_CNT3)) & 0x001f8000 ) >> 15)
++#define GET_CH0_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000001 ) >> 0)
++#define GET_CH1_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000002 ) >> 1)
++#define GET_CH2_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000004 ) >> 2)
++#define GET_CH3_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000008 ) >> 3)
++#define GET_CH4_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000010 ) >> 4)
++#define GET_CH5_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000020 ) >> 5)
++#define GET_CH6_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000040 ) >> 6)
++#define GET_CH7_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000080 ) >> 7)
++#define GET_CH8_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000100 ) >> 8)
++#define GET_CH9_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000200 ) >> 9)
++#define GET_CH10_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000400 ) >> 10)
++#define GET_CH11_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000800 ) >> 11)
++#define GET_CH12_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00001000 ) >> 12)
++#define GET_CH13_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00002000 ) >> 13)
++#define GET_CH14_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00004000 ) >> 14)
++#define GET_CH15_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00008000 ) >> 15)
++#define GET_CH0_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000001 ) >> 0)
++#define GET_CH1_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000002 ) >> 1)
++#define GET_CH2_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000004 ) >> 2)
++#define GET_CH3_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000008 ) >> 3)
++#define GET_CH4_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000010 ) >> 4)
++#define GET_CH5_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000020 ) >> 5)
++#define GET_CH6_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000040 ) >> 6)
++#define GET_CH7_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000080 ) >> 7)
++#define GET_CH8_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000100 ) >> 8)
++#define GET_CH9_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000200 ) >> 9)
++#define GET_CH10_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000400 ) >> 10)
++#define GET_CH11_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000800 ) >> 11)
++#define GET_CH12_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00001000 ) >> 12)
++#define GET_CH13_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00002000 ) >> 13)
++#define GET_CH14_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00004000 ) >> 14)
++#define GET_CH15_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00008000 ) >> 15)
++#define GET_MB_LOW_THOLD_EN (((REG32(ADR_MB_THRESHOLD6)) & 0x80000000 ) >> 31)
++#define GET_CH0_LOWTHOLD (((REG32(ADR_MB_THRESHOLD7)) & 0x0000001f ) >> 0)
++#define GET_CH1_LOWTHOLD (((REG32(ADR_MB_THRESHOLD7)) & 0x00001f00 ) >> 8)
++#define GET_CH2_LOWTHOLD (((REG32(ADR_MB_THRESHOLD7)) & 0x001f0000 ) >> 16)
++#define GET_CH3_LOWTHOLD (((REG32(ADR_MB_THRESHOLD7)) & 0x1f000000 ) >> 24)
++#define GET_CH4_LOWTHOLD (((REG32(ADR_MB_THRESHOLD8)) & 0x0000001f ) >> 0)
++#define GET_CH5_LOWTHOLD (((REG32(ADR_MB_THRESHOLD8)) & 0x00001f00 ) >> 8)
++#define GET_CH6_LOWTHOLD (((REG32(ADR_MB_THRESHOLD8)) & 0x001f0000 ) >> 16)
++#define GET_CH7_LOWTHOLD (((REG32(ADR_MB_THRESHOLD8)) & 0x1f000000 ) >> 24)
++#define GET_CH8_LOWTHOLD (((REG32(ADR_MB_THRESHOLD9)) & 0x0000001f ) >> 0)
++#define GET_CH9_LOWTHOLD (((REG32(ADR_MB_THRESHOLD9)) & 0x00001f00 ) >> 8)
++#define GET_CH10_LOWTHOLD (((REG32(ADR_MB_THRESHOLD9)) & 0x001f0000 ) >> 16)
++#define GET_CH11_LOWTHOLD (((REG32(ADR_MB_THRESHOLD9)) & 0x1f000000 ) >> 24)
++#define GET_CH12_LOWTHOLD (((REG32(ADR_MB_THRESHOLD10)) & 0x0000001f ) >> 0)
++#define GET_CH13_LOWTHOLD (((REG32(ADR_MB_THRESHOLD10)) & 0x00001f00 ) >> 8)
++#define GET_CH14_LOWTHOLD (((REG32(ADR_MB_THRESHOLD10)) & 0x001f0000 ) >> 16)
++#define GET_CH15_LOWTHOLD (((REG32(ADR_MB_THRESHOLD10)) & 0x1f000000 ) >> 24)
++#define GET_TRASH_TIMEOUT_EN (((REG32(ADR_MB_TRASH_CFG)) & 0x00000001 ) >> 0)
++#define GET_TRASH_CAN_INT (((REG32(ADR_MB_TRASH_CFG)) & 0x00000002 ) >> 1)
++#define GET_TRASH_INT_ID (((REG32(ADR_MB_TRASH_CFG)) & 0x000007f0 ) >> 4)
++#define GET_TRASH_TIMEOUT (((REG32(ADR_MB_TRASH_CFG)) & 0x03ff0000 ) >> 16)
++#define GET_CH0_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000001 ) >> 0)
++#define GET_CH1_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000002 ) >> 1)
++#define GET_CH2_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000004 ) >> 2)
++#define GET_CH3_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000008 ) >> 3)
++#define GET_CH4_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000010 ) >> 4)
++#define GET_CH5_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000020 ) >> 5)
++#define GET_CH6_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000040 ) >> 6)
++#define GET_CH7_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000080 ) >> 7)
++#define GET_CH8_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000100 ) >> 8)
++#define GET_CH9_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000200 ) >> 9)
++#define GET_CH10_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000400 ) >> 10)
++#define GET_CH11_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000800 ) >> 11)
++#define GET_CH12_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00001000 ) >> 12)
++#define GET_CH13_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00002000 ) >> 13)
++#define GET_CH14_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00004000 ) >> 14)
++#define GET_CPU_ID_TB2 (((REG32(ADR_CPU_ID_TB2)) & 0xffffffff ) >> 0)
++#define GET_CPU_ID_TB3 (((REG32(ADR_CPU_ID_TB3)) & 0xffffffff ) >> 0)
++#define GET_IQ_LOG_EN (((REG32(ADR_PHY_IQ_LOG_CFG0)) & 0x00000001 ) >> 0)
++#define GET_IQ_LOG_STOP_MODE (((REG32(ADR_PHY_IQ_LOG_CFG1)) & 0x00000001 ) >> 0)
++#define GET_GPIO_STOP_EN (((REG32(ADR_PHY_IQ_LOG_CFG1)) & 0x00000010 ) >> 4)
++#define GET_GPIO_STOP_POL (((REG32(ADR_PHY_IQ_LOG_CFG1)) & 0x00000020 ) >> 5)
++#define GET_IQ_LOG_TIMER (((REG32(ADR_PHY_IQ_LOG_CFG1)) & 0xffff0000 ) >> 16)
++#define GET_IQ_LOG_LEN (((REG32(ADR_PHY_IQ_LOG_LEN)) & 0x0000ffff ) >> 0)
++#define GET_IQ_LOG_TAIL_ADR (((REG32(ADR_PHY_IQ_LOG_PTR)) & 0x0000ffff ) >> 0)
++#define GET_ALC_LENG (((REG32(ADR_WR_ALC)) & 0x0003ffff ) >> 0)
++#define GET_CH0_DYN_PRI (((REG32(ADR_WR_ALC)) & 0x00300000 ) >> 20)
++#define GET_MCU_PKTID (((REG32(ADR_GETID)) & 0xffffffff ) >> 0)
++#define GET_CH0_STA_PRI (((REG32(ADR_CH_STA_PRI)) & 0x00000003 ) >> 0)
++#define GET_CH1_STA_PRI (((REG32(ADR_CH_STA_PRI)) & 0x00000030 ) >> 4)
++#define GET_CH2_STA_PRI (((REG32(ADR_CH_STA_PRI)) & 0x00000300 ) >> 8)
++#define GET_CH3_STA_PRI (((REG32(ADR_CH_STA_PRI)) & 0x00003000 ) >> 12)
++#define GET_ID_TB0 (((REG32(ADR_RD_ID0)) & 0xffffffff ) >> 0)
++#define GET_ID_TB1 (((REG32(ADR_RD_ID1)) & 0xffffffff ) >> 0)
++#define GET_ID_MNG_HALT (((REG32(ADR_IMD_CFG)) & 0x00000010 ) >> 4)
++#define GET_ID_MNG_ERR_HALT_EN (((REG32(ADR_IMD_CFG)) & 0x00000020 ) >> 5)
++#define GET_ID_EXCEPT_FLG_CLR (((REG32(ADR_IMD_CFG)) & 0x00000040 ) >> 6)
++#define GET_ID_EXCEPT_FLG (((REG32(ADR_IMD_CFG)) & 0x00000080 ) >> 7)
++#define GET_ID_FULL (((REG32(ADR_IMD_STA)) & 0x00000001 ) >> 0)
++#define GET_ID_MNG_BUSY (((REG32(ADR_IMD_STA)) & 0x00000002 ) >> 1)
++#define GET_REQ_LOCK (((REG32(ADR_IMD_STA)) & 0x00000004 ) >> 2)
++#define GET_CH0_REQ_LOCK (((REG32(ADR_IMD_STA)) & 0x00000010 ) >> 4)
++#define GET_CH1_REQ_LOCK (((REG32(ADR_IMD_STA)) & 0x00000020 ) >> 5)
++#define GET_CH2_REQ_LOCK (((REG32(ADR_IMD_STA)) & 0x00000040 ) >> 6)
++#define GET_CH3_REQ_LOCK (((REG32(ADR_IMD_STA)) & 0x00000080 ) >> 7)
++#define GET_REQ_LOCK_INT_EN (((REG32(ADR_IMD_STA)) & 0x00000100 ) >> 8)
++#define GET_REQ_LOCK_INT (((REG32(ADR_IMD_STA)) & 0x00000200 ) >> 9)
++#define GET_MCU_ALC_READY (((REG32(ADR_ALC_STA)) & 0x00000001 ) >> 0)
++#define GET_ALC_FAIL (((REG32(ADR_ALC_STA)) & 0x00000002 ) >> 1)
++#define GET_ALC_BUSY (((REG32(ADR_ALC_STA)) & 0x00000004 ) >> 2)
++#define GET_CH0_NVLD (((REG32(ADR_ALC_STA)) & 0x00000010 ) >> 4)
++#define GET_CH1_NVLD (((REG32(ADR_ALC_STA)) & 0x00000020 ) >> 5)
++#define GET_CH2_NVLD (((REG32(ADR_ALC_STA)) & 0x00000040 ) >> 6)
++#define GET_CH3_NVLD (((REG32(ADR_ALC_STA)) & 0x00000080 ) >> 7)
++#define GET_ALC_INT_ID (((REG32(ADR_ALC_STA)) & 0x00007f00 ) >> 8)
++#define GET_ALC_TIMEOUT (((REG32(ADR_ALC_STA)) & 0x03ff0000 ) >> 16)
++#define GET_ALC_TIMEOUT_INT_EN (((REG32(ADR_ALC_STA)) & 0x40000000 ) >> 30)
++#define GET_ALC_TIMEOUT_INT (((REG32(ADR_ALC_STA)) & 0x80000000 ) >> 31)
++#define GET_TX_ID_COUNT (((REG32(ADR_TRX_ID_COUNT)) & 0x000000ff ) >> 0)
++#define GET_RX_ID_COUNT (((REG32(ADR_TRX_ID_COUNT)) & 0x0000ff00 ) >> 8)
++#define GET_TX_ID_THOLD (((REG32(ADR_TRX_ID_THRESHOLD)) & 0x000000ff ) >> 0)
++#define GET_RX_ID_THOLD (((REG32(ADR_TRX_ID_THRESHOLD)) & 0x0000ff00 ) >> 8)
++#define GET_ID_THOLD_RX_INT (((REG32(ADR_TRX_ID_THRESHOLD)) & 0x00010000 ) >> 16)
++#define GET_RX_INT_CH (((REG32(ADR_TRX_ID_THRESHOLD)) & 0x000e0000 ) >> 17)
++#define GET_ID_THOLD_TX_INT (((REG32(ADR_TRX_ID_THRESHOLD)) & 0x00100000 ) >> 20)
++#define GET_TX_INT_CH (((REG32(ADR_TRX_ID_THRESHOLD)) & 0x00e00000 ) >> 21)
++#define GET_ID_THOLD_INT_EN (((REG32(ADR_TRX_ID_THRESHOLD)) & 0x01000000 ) >> 24)
++#define GET_TX_ID_TB0 (((REG32(ADR_TX_ID0)) & 0xffffffff ) >> 0)
++#define GET_TX_ID_TB1 (((REG32(ADR_TX_ID1)) & 0xffffffff ) >> 0)
++#define GET_RX_ID_TB0 (((REG32(ADR_RX_ID0)) & 0xffffffff ) >> 0)
++#define GET_RX_ID_TB1 (((REG32(ADR_RX_ID1)) & 0xffffffff ) >> 0)
++#define GET_DOUBLE_RLS_INT_EN (((REG32(ADR_RTN_STA)) & 0x00000001 ) >> 0)
++#define GET_ID_DOUBLE_RLS_INT (((REG32(ADR_RTN_STA)) & 0x00000002 ) >> 1)
++#define GET_DOUBLE_RLS_ID (((REG32(ADR_RTN_STA)) & 0x00007f00 ) >> 8)
++#define GET_ID_LEN_THOLD_INT_EN (((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x00000001 ) >> 0)
++#define GET_ALL_ID_LEN_THOLD_INT (((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x00000002 ) >> 1)
++#define GET_TX_ID_LEN_THOLD_INT (((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x00000004 ) >> 2)
++#define GET_RX_ID_LEN_THOLD_INT (((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x00000008 ) >> 3)
++#define GET_ID_TX_LEN_THOLD (((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x00001ff0 ) >> 4)
++#define GET_ID_RX_LEN_THOLD (((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x003fe000 ) >> 13)
++#define GET_ID_LEN_THOLD (((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x7fc00000 ) >> 22)
++#define GET_ALL_ID_ALC_LEN (((REG32(ADR_ID_LEN_THREADSHOLD2)) & 0x000001ff ) >> 0)
++#define GET_TX_ID_ALC_LEN (((REG32(ADR_ID_LEN_THREADSHOLD2)) & 0x0003fe00 ) >> 9)
++#define GET_RX_ID_ALC_LEN (((REG32(ADR_ID_LEN_THREADSHOLD2)) & 0x07fc0000 ) >> 18)
++#define GET_CH_ARB_EN (((REG32(ADR_CH_ARB_PRI)) & 0x00000001 ) >> 0)
++#define GET_CH_PRI1 (((REG32(ADR_CH_ARB_PRI)) & 0x00000030 ) >> 4)
++#define GET_CH_PRI2 (((REG32(ADR_CH_ARB_PRI)) & 0x00000300 ) >> 8)
++#define GET_CH_PRI3 (((REG32(ADR_CH_ARB_PRI)) & 0x00003000 ) >> 12)
++#define GET_CH_PRI4 (((REG32(ADR_CH_ARB_PRI)) & 0x00030000 ) >> 16)
++#define GET_TX_ID_REMAIN (((REG32(ADR_TX_ID_REMAIN_STATUS)) & 0x0000007f ) >> 0)
++#define GET_TX_PAGE_REMAIN (((REG32(ADR_TX_ID_REMAIN_STATUS)) & 0x0001ff00 ) >> 8)
++#define GET_ID_PAGE_MAX_SIZE (((REG32(ADR_ID_INFO_STA)) & 0x000001ff ) >> 0)
++#define GET_TX_PAGE_LIMIT (((REG32(ADR_TX_LIMIT_INTR)) & 0x000001ff ) >> 0)
++#define GET_TX_COUNT_LIMIT (((REG32(ADR_TX_LIMIT_INTR)) & 0x00ff0000 ) >> 16)
++#define GET_TX_LIMIT_INT (((REG32(ADR_TX_LIMIT_INTR)) & 0x40000000 ) >> 30)
++#define GET_TX_LIMIT_INT_EN (((REG32(ADR_TX_LIMIT_INTR)) & 0x80000000 ) >> 31)
++#define GET_TX_PAGE_USE_7_0 (((REG32(ADR_TX_ID_ALL_INFO)) & 0x000000ff ) >> 0)
++#define GET_TX_ID_USE_5_0 (((REG32(ADR_TX_ID_ALL_INFO)) & 0x00003f00 ) >> 8)
++#define GET_EDCA0_FFO_CNT (((REG32(ADR_TX_ID_ALL_INFO)) & 0x0003c000 ) >> 14)
++#define GET_EDCA1_FFO_CNT_3_0 (((REG32(ADR_TX_ID_ALL_INFO)) & 0x003c0000 ) >> 18)
++#define GET_EDCA2_FFO_CNT (((REG32(ADR_TX_ID_ALL_INFO)) & 0x07c00000 ) >> 22)
++#define GET_EDCA3_FFO_CNT (((REG32(ADR_TX_ID_ALL_INFO)) & 0xf8000000 ) >> 27)
++#define GET_ID_TB2 (((REG32(ADR_RD_ID2)) & 0xffffffff ) >> 0)
++#define GET_ID_TB3 (((REG32(ADR_RD_ID3)) & 0xffffffff ) >> 0)
++#define GET_TX_ID_TB2 (((REG32(ADR_TX_ID2)) & 0xffffffff ) >> 0)
++#define GET_TX_ID_TB3 (((REG32(ADR_TX_ID3)) & 0xffffffff ) >> 0)
++#define GET_RX_ID_TB2 (((REG32(ADR_RX_ID2)) & 0xffffffff ) >> 0)
++#define GET_RX_ID_TB3 (((REG32(ADR_RX_ID3)) & 0xffffffff ) >> 0)
++#define GET_TX_PAGE_USE2 (((REG32(ADR_TX_ID_ALL_INFO2)) & 0x000001ff ) >> 0)
++#define GET_TX_ID_USE2 (((REG32(ADR_TX_ID_ALL_INFO2)) & 0x0001fe00 ) >> 9)
++#define GET_EDCA4_FFO_CNT (((REG32(ADR_TX_ID_ALL_INFO2)) & 0x001e0000 ) >> 17)
++#define GET_TX_PAGE_USE3 (((REG32(ADR_TX_ID_ALL_INFO_A)) & 0x000001ff ) >> 0)
++#define GET_TX_ID_USE3 (((REG32(ADR_TX_ID_ALL_INFO_A)) & 0x0001fe00 ) >> 9)
++#define GET_EDCA1_FFO_CNT2 (((REG32(ADR_TX_ID_ALL_INFO_A)) & 0x03e00000 ) >> 21)
++#define GET_EDCA4_FFO_CNT2 (((REG32(ADR_TX_ID_ALL_INFO_A)) & 0x3c000000 ) >> 26)
++#define GET_TX_PAGE_USE4 (((REG32(ADR_TX_ID_ALL_INFO_B)) & 0x000001ff ) >> 0)
++#define GET_TX_ID_USE4 (((REG32(ADR_TX_ID_ALL_INFO_B)) & 0x0001fe00 ) >> 9)
++#define GET_EDCA2_FFO_CNT2 (((REG32(ADR_TX_ID_ALL_INFO_B)) & 0x003e0000 ) >> 17)
++#define GET_EDCA3_FFO_CNT2 (((REG32(ADR_TX_ID_ALL_INFO_B)) & 0x07c00000 ) >> 22)
++#define GET_TX_ID_IFO_LEN (((REG32(ADR_TX_ID_REMAIN_STATUS2)) & 0x000001ff ) >> 0)
++#define GET_RX_ID_IFO_LEN (((REG32(ADR_TX_ID_REMAIN_STATUS2)) & 0x01ff0000 ) >> 16)
++#define GET_MAX_ALL_ALC_ID_CNT (((REG32(ADR_ALC_ID_INFO)) & 0x000000ff ) >> 0)
++#define GET_MAX_TX_ALC_ID_CNT (((REG32(ADR_ALC_ID_INFO)) & 0x0000ff00 ) >> 8)
++#define GET_MAX_RX_ALC_ID_CNT (((REG32(ADR_ALC_ID_INFO)) & 0x00ff0000 ) >> 16)
++#define GET_MAX_ALL_ID_ALC_LEN (((REG32(ADR_ALC_ID_INF1)) & 0x000001ff ) >> 0)
++#define GET_MAX_TX_ID_ALC_LEN (((REG32(ADR_ALC_ID_INF1)) & 0x0003fe00 ) >> 9)
++#define GET_MAX_RX_ID_ALC_LEN (((REG32(ADR_ALC_ID_INF1)) & 0x07fc0000 ) >> 18)
++#define GET_RG_PMDLBK (((REG32(ADR_PHY_EN_0)) & 0x00000001 ) >> 0)
++#define GET_RG_RDYACK_SEL (((REG32(ADR_PHY_EN_0)) & 0x00000006 ) >> 1)
++#define GET_RG_ADEDGE_SEL (((REG32(ADR_PHY_EN_0)) & 0x00000008 ) >> 3)
++#define GET_RG_SIGN_SWAP (((REG32(ADR_PHY_EN_0)) & 0x00000010 ) >> 4)
++#define GET_RG_IQ_SWAP (((REG32(ADR_PHY_EN_0)) & 0x00000020 ) >> 5)
++#define GET_RG_Q_INV (((REG32(ADR_PHY_EN_0)) & 0x00000040 ) >> 6)
++#define GET_RG_I_INV (((REG32(ADR_PHY_EN_0)) & 0x00000080 ) >> 7)
++#define GET_RG_BYPASS_ACI (((REG32(ADR_PHY_EN_0)) & 0x00000100 ) >> 8)
++#define GET_RG_LBK_ANA_PATH (((REG32(ADR_PHY_EN_0)) & 0x00000200 ) >> 9)
++#define GET_RG_SPECTRUM_LEAKY_FACTOR (((REG32(ADR_PHY_EN_0)) & 0x00000c00 ) >> 10)
++#define GET_RG_SPECTRUM_BW (((REG32(ADR_PHY_EN_0)) & 0x00003000 ) >> 12)
++#define GET_RG_SPECTRUM_FREQ_MANUAL (((REG32(ADR_PHY_EN_0)) & 0x00004000 ) >> 14)
++#define GET_RG_SPECTRUM_EN (((REG32(ADR_PHY_EN_0)) & 0x00008000 ) >> 15)
++#define GET_RG_TXPWRLVL_SET (((REG32(ADR_PHY_EN_0)) & 0x00ff0000 ) >> 16)
++#define GET_RG_TXPWRLVL_SEL (((REG32(ADR_PHY_EN_0)) & 0x01000000 ) >> 24)
++#define GET_RG_RF_BB_CLK_SEL (((REG32(ADR_PHY_EN_0)) & 0x80000000 ) >> 31)
++#define GET_RG_PHY_MD_EN (((REG32(ADR_PHY_EN_1)) & 0x00000001 ) >> 0)
++#define GET_RG_PHYRX_MD_EN (((REG32(ADR_PHY_EN_1)) & 0x00000002 ) >> 1)
++#define GET_RG_PHYTX_MD_EN (((REG32(ADR_PHY_EN_1)) & 0x00000004 ) >> 2)
++#define GET_RG_PHY11GN_MD_EN (((REG32(ADR_PHY_EN_1)) & 0x00000008 ) >> 3)
++#define GET_RG_PHY11B_MD_EN (((REG32(ADR_PHY_EN_1)) & 0x00000010 ) >> 4)
++#define GET_RG_PHYRXFIFO_MD_EN (((REG32(ADR_PHY_EN_1)) & 0x00000020 ) >> 5)
++#define GET_RG_PHYTXFIFO_MD_EN (((REG32(ADR_PHY_EN_1)) & 0x00000040 ) >> 6)
++#define GET_RG_PHY11BGN_MD_EN (((REG32(ADR_PHY_EN_1)) & 0x00000100 ) >> 8)
++#define GET_RG_FORCE_11GN_EN (((REG32(ADR_PHY_EN_1)) & 0x00001000 ) >> 12)
++#define GET_RG_FORCE_11B_EN (((REG32(ADR_PHY_EN_1)) & 0x00002000 ) >> 13)
++#define GET_RG_FFT_MEM_CLK_EN_RX (((REG32(ADR_PHY_EN_1)) & 0x00004000 ) >> 14)
++#define GET_RG_FFT_MEM_CLK_EN_TX (((REG32(ADR_PHY_EN_1)) & 0x00008000 ) >> 15)
++#define GET_RG_PHY_IQ_TRIG_SEL (((REG32(ADR_PHY_EN_1)) & 0x000f0000 ) >> 16)
++#define GET_RG_SPECTRUM_FREQ (((REG32(ADR_PHY_EN_1)) & 0x3ff00000 ) >> 20)
++#define GET_SVN_VERSION (((REG32(ADR_SVN_VERSION_REG)) & 0xffffffff ) >> 0)
++#define GET_RG_LENGTH (((REG32(ADR_PHY_PKT_GEN_0)) & 0x0000ffff ) >> 0)
++#define GET_RG_PKT_MODE (((REG32(ADR_PHY_PKT_GEN_0)) & 0x00070000 ) >> 16)
++#define GET_RG_CH_BW (((REG32(ADR_PHY_PKT_GEN_0)) & 0x00380000 ) >> 19)
++#define GET_RG_PRM (((REG32(ADR_PHY_PKT_GEN_0)) & 0x00400000 ) >> 22)
++#define GET_RG_SHORTGI (((REG32(ADR_PHY_PKT_GEN_0)) & 0x00800000 ) >> 23)
++#define GET_RG_RATE (((REG32(ADR_PHY_PKT_GEN_0)) & 0x7f000000 ) >> 24)
++#define GET_RG_L_LENGTH (((REG32(ADR_PHY_PKT_GEN_1)) & 0x00000fff ) >> 0)
++#define GET_RG_L_RATE (((REG32(ADR_PHY_PKT_GEN_1)) & 0x00007000 ) >> 12)
++#define GET_RG_SERVICE (((REG32(ADR_PHY_PKT_GEN_1)) & 0xffff0000 ) >> 16)
++#define GET_RG_SMOOTHING (((REG32(ADR_PHY_PKT_GEN_2)) & 0x00000001 ) >> 0)
++#define GET_RG_NO_SOUND (((REG32(ADR_PHY_PKT_GEN_2)) & 0x00000002 ) >> 1)
++#define GET_RG_AGGREGATE (((REG32(ADR_PHY_PKT_GEN_2)) & 0x00000004 ) >> 2)
++#define GET_RG_STBC (((REG32(ADR_PHY_PKT_GEN_2)) & 0x00000018 ) >> 3)
++#define GET_RG_FEC (((REG32(ADR_PHY_PKT_GEN_2)) & 0x00000020 ) >> 5)
++#define GET_RG_N_ESS (((REG32(ADR_PHY_PKT_GEN_2)) & 0x000000c0 ) >> 6)
++#define GET_RG_TXPWRLVL (((REG32(ADR_PHY_PKT_GEN_2)) & 0x0000ff00 ) >> 8)
++#define GET_RG_TX_START (((REG32(ADR_PHY_PKT_GEN_3)) & 0x00000001 ) >> 0)
++#define GET_RG_IFS_TIME (((REG32(ADR_PHY_PKT_GEN_3)) & 0x000000fc ) >> 2)
++#define GET_RG_CONTINUOUS_DATA (((REG32(ADR_PHY_PKT_GEN_3)) & 0x00000100 ) >> 8)
++#define GET_RG_DATA_SEL (((REG32(ADR_PHY_PKT_GEN_3)) & 0x00000600 ) >> 9)
++#define GET_RG_TX_D (((REG32(ADR_PHY_PKT_GEN_3)) & 0x00ff0000 ) >> 16)
++#define GET_RG_TX_CNT_TARGET (((REG32(ADR_PHY_PKT_GEN_4)) & 0xffffffff ) >> 0)
++#define GET_RG_FFT_IFFT_MODE (((REG32(ADR_PHY_REG_00)) & 0x000000c0 ) >> 6)
++#define GET_RG_DAC_DBG_MODE (((REG32(ADR_PHY_REG_00)) & 0x00000100 ) >> 8)
++#define GET_RG_DAC_SGN_SWAP (((REG32(ADR_PHY_REG_00)) & 0x00000200 ) >> 9)
++#define GET_RG_TXD_SEL (((REG32(ADR_PHY_REG_00)) & 0x00000c00 ) >> 10)
++#define GET_RG_UP8X (((REG32(ADR_PHY_REG_00)) & 0x00ff0000 ) >> 16)
++#define GET_RG_IQ_DC_BYP (((REG32(ADR_PHY_REG_00)) & 0x01000000 ) >> 24)
++#define GET_RG_IQ_DC_LEAKY_FACTOR (((REG32(ADR_PHY_REG_00)) & 0x30000000 ) >> 28)
++#define GET_RG_DAC_DCEN (((REG32(ADR_PHY_REG_01)) & 0x00000001 ) >> 0)
++#define GET_RG_DAC_DCQ (((REG32(ADR_PHY_REG_01)) & 0x00003ff0 ) >> 4)
++#define GET_RG_DAC_DCI (((REG32(ADR_PHY_REG_01)) & 0x03ff0000 ) >> 16)
++#define GET_RG_PGA_REFDB_SAT (((REG32(ADR_PHY_REG_02_AGC)) & 0x0000007f ) >> 0)
++#define GET_RG_PGA_REFDB_TOP (((REG32(ADR_PHY_REG_02_AGC)) & 0x00007f00 ) >> 8)
++#define GET_RG_PGA_REF_UND (((REG32(ADR_PHY_REG_02_AGC)) & 0x03ff0000 ) >> 16)
++#define GET_RG_RF_REF_SAT (((REG32(ADR_PHY_REG_02_AGC)) & 0xf0000000 ) >> 28)
++#define GET_RG_PGAGC_SET (((REG32(ADR_PHY_REG_03_AGC)) & 0x0000000f ) >> 0)
++#define GET_RG_PGAGC_OW (((REG32(ADR_PHY_REG_03_AGC)) & 0x00000010 ) >> 4)
++#define GET_RG_RFGC_SET (((REG32(ADR_PHY_REG_03_AGC)) & 0x00000060 ) >> 5)
++#define GET_RG_RFGC_OW (((REG32(ADR_PHY_REG_03_AGC)) & 0x00000080 ) >> 7)
++#define GET_RG_WAIT_T_RXAGC (((REG32(ADR_PHY_REG_03_AGC)) & 0x00003f00 ) >> 8)
++#define GET_RG_RXAGC_SET (((REG32(ADR_PHY_REG_03_AGC)) & 0x00004000 ) >> 14)
++#define GET_RG_RXAGC_OW (((REG32(ADR_PHY_REG_03_AGC)) & 0x00008000 ) >> 15)
++#define GET_RG_WAIT_T_FINAL (((REG32(ADR_PHY_REG_03_AGC)) & 0x003f0000 ) >> 16)
++#define GET_RG_WAIT_T (((REG32(ADR_PHY_REG_03_AGC)) & 0x3f000000 ) >> 24)
++#define GET_RG_ULG_PGA_SAT_PGA_GAIN (((REG32(ADR_PHY_REG_04_AGC)) & 0x0000000f ) >> 0)
++#define GET_RG_LG_PGA_UND_PGA_GAIN (((REG32(ADR_PHY_REG_04_AGC)) & 0x000000f0 ) >> 4)
++#define GET_RG_LG_PGA_SAT_PGA_GAIN (((REG32(ADR_PHY_REG_04_AGC)) & 0x00000f00 ) >> 8)
++#define GET_RG_LG_RF_SAT_PGA_GAIN (((REG32(ADR_PHY_REG_04_AGC)) & 0x0000f000 ) >> 12)
++#define GET_RG_MG_RF_SAT_PGANOREF_PGA_GAIN (((REG32(ADR_PHY_REG_04_AGC)) & 0x000f0000 ) >> 16)
++#define GET_RG_HG_PGA_SAT2_PGA_GAIN (((REG32(ADR_PHY_REG_04_AGC)) & 0x00f00000 ) >> 20)
++#define GET_RG_HG_PGA_SAT1_PGA_GAIN (((REG32(ADR_PHY_REG_04_AGC)) & 0x0f000000 ) >> 24)
++#define GET_RG_HG_RF_SAT_PGA_GAIN (((REG32(ADR_PHY_REG_04_AGC)) & 0xf0000000 ) >> 28)
++#define GET_RG_MG_PGA_JB_TH (((REG32(ADR_PHY_REG_05_AGC)) & 0x0000000f ) >> 0)
++#define GET_RG_MA_PGA_LOW_TH_CNT_LMT (((REG32(ADR_PHY_REG_05_AGC)) & 0x001f0000 ) >> 16)
++#define GET_RG_WR_RFGC_INIT_SET (((REG32(ADR_PHY_REG_05_AGC)) & 0x00600000 ) >> 21)
++#define GET_RG_WR_RFGC_INIT_EN (((REG32(ADR_PHY_REG_05_AGC)) & 0x00800000 ) >> 23)
++#define GET_RG_MA_PGA_HIGH_TH_CNT_LMT (((REG32(ADR_PHY_REG_05_AGC)) & 0x1f000000 ) >> 24)
++#define GET_RG_AGC_THRESHOLD (((REG32(ADR_PHY_REG_06_11B_DAGC)) & 0x00003fff ) >> 0)
++#define GET_RG_ACI_POINT_CNT_LMT_11B (((REG32(ADR_PHY_REG_06_11B_DAGC)) & 0x007f0000 ) >> 16)
++#define GET_RG_ACI_DAGC_LEAKY_FACTOR_11B (((REG32(ADR_PHY_REG_06_11B_DAGC)) & 0x03000000 ) >> 24)
++#define GET_RG_WR_ACI_GAIN_INI_SEL_11B (((REG32(ADR_PHY_REG_07_11B_DAGC)) & 0x000000ff ) >> 0)
++#define GET_RG_WR_ACI_GAIN_SEL_11B (((REG32(ADR_PHY_REG_07_11B_DAGC)) & 0x0000ff00 ) >> 8)
++#define GET_RG_ACI_DAGC_SET_VALUE_11B (((REG32(ADR_PHY_REG_07_11B_DAGC)) & 0x007f0000 ) >> 16)
++#define GET_RG_WR_ACI_GAIN_OW_11B (((REG32(ADR_PHY_REG_07_11B_DAGC)) & 0x80000000 ) >> 31)
++#define GET_RG_ACI_POINT_CNT_LMT_11GN (((REG32(ADR_PHY_REG_08_11GN_DAGC)) & 0x000000ff ) >> 0)
++#define GET_RG_ACI_DAGC_LEAKY_FACTOR_11GN (((REG32(ADR_PHY_REG_08_11GN_DAGC)) & 0x00000300 ) >> 8)
++#define GET_RG_ACI_DAGC_DONE_CNT_LMT_11GN (((REG32(ADR_PHY_REG_08_11GN_DAGC)) & 0xff000000 ) >> 24)
++#define GET_RG_ACI_DAGC_SET_VALUE_11GN (((REG32(ADR_PHY_REG_09_11GN_DAGC)) & 0x0000007f ) >> 0)
++#define GET_RG_ACI_GAIN_INI_VAL_11GN (((REG32(ADR_PHY_REG_09_11GN_DAGC)) & 0x0000ff00 ) >> 8)
++#define GET_RG_ACI_GAIN_OW_VAL_11GN (((REG32(ADR_PHY_REG_09_11GN_DAGC)) & 0x00ff0000 ) >> 16)
++#define GET_RG_ACI_GAIN_OW_11GN (((REG32(ADR_PHY_REG_09_11GN_DAGC)) & 0x80000000 ) >> 31)
++#define GET_RO_CCA_PWR_MA_11GN (((REG32(ADR_PHY_READ_REG_00_DIG_PWR)) & 0x0000007f ) >> 0)
++#define GET_RO_ED_STATE (((REG32(ADR_PHY_READ_REG_00_DIG_PWR)) & 0x00008000 ) >> 15)
++#define GET_RO_CCA_PWR_MA_11B (((REG32(ADR_PHY_READ_REG_00_DIG_PWR)) & 0x007f0000 ) >> 16)
++#define GET_RO_PGA_PWR_FF1 (((REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) & 0x00003fff ) >> 0)
++#define GET_RO_RF_PWR_FF1 (((REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) & 0x000f0000 ) >> 16)
++#define GET_RO_PGAGC_FF1 (((REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) & 0x0f000000 ) >> 24)
++#define GET_RO_RFGC_FF1 (((REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) & 0x30000000 ) >> 28)
++#define GET_RO_PGA_PWR_FF2 (((REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) & 0x00003fff ) >> 0)
++#define GET_RO_RF_PWR_FF2 (((REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) & 0x000f0000 ) >> 16)
++#define GET_RO_PGAGC_FF2 (((REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) & 0x0f000000 ) >> 24)
++#define GET_RO_RFGC_FF2 (((REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) & 0x30000000 ) >> 28)
++#define GET_RO_PGA_PWR_FF3 (((REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) & 0x00003fff ) >> 0)
++#define GET_RO_RF_PWR_FF3 (((REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) & 0x000f0000 ) >> 16)
++#define GET_RO_PGAGC_FF3 (((REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) & 0x0f000000 ) >> 24)
++#define GET_RO_RFGC_FF3 (((REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) & 0x30000000 ) >> 28)
++#define GET_RG_TX_DES_RATE (((REG32(ADR_PHY_REG_10_TX_DES)) & 0x0000001f ) >> 0)
++#define GET_RG_TX_DES_MODE (((REG32(ADR_PHY_REG_10_TX_DES)) & 0x00001f00 ) >> 8)
++#define GET_RG_TX_DES_LEN_LO (((REG32(ADR_PHY_REG_10_TX_DES)) & 0x001f0000 ) >> 16)
++#define GET_RG_TX_DES_LEN_UP (((REG32(ADR_PHY_REG_10_TX_DES)) & 0x1f000000 ) >> 24)
++#define GET_RG_TX_DES_SRVC_UP (((REG32(ADR_PHY_REG_11_TX_DES)) & 0x0000001f ) >> 0)
++#define GET_RG_TX_DES_L_LEN_LO (((REG32(ADR_PHY_REG_11_TX_DES)) & 0x00001f00 ) >> 8)
++#define GET_RG_TX_DES_L_LEN_UP (((REG32(ADR_PHY_REG_11_TX_DES)) & 0x001f0000 ) >> 16)
++#define GET_RG_TX_DES_TYPE (((REG32(ADR_PHY_REG_11_TX_DES)) & 0x1f000000 ) >> 24)
++#define GET_RG_TX_DES_L_LEN_UP_COMB (((REG32(ADR_PHY_REG_12_TX_DES)) & 0x00000001 ) >> 0)
++#define GET_RG_TX_DES_TYPE_COMB (((REG32(ADR_PHY_REG_12_TX_DES)) & 0x00000010 ) >> 4)
++#define GET_RG_TX_DES_RATE_COMB (((REG32(ADR_PHY_REG_12_TX_DES)) & 0x00000100 ) >> 8)
++#define GET_RG_TX_DES_MODE_COMB (((REG32(ADR_PHY_REG_12_TX_DES)) & 0x00001000 ) >> 12)
++#define GET_RG_TX_DES_PWRLVL (((REG32(ADR_PHY_REG_12_TX_DES)) & 0x001f0000 ) >> 16)
++#define GET_RG_TX_DES_SRVC_LO (((REG32(ADR_PHY_REG_12_TX_DES)) & 0x1f000000 ) >> 24)
++#define GET_RG_RX_DES_RATE (((REG32(ADR_PHY_REG_13_RX_DES)) & 0x0000003f ) >> 0)
++#define GET_RG_RX_DES_MODE (((REG32(ADR_PHY_REG_13_RX_DES)) & 0x00003f00 ) >> 8)
++#define GET_RG_RX_DES_LEN_LO (((REG32(ADR_PHY_REG_13_RX_DES)) & 0x003f0000 ) >> 16)
++#define GET_RG_RX_DES_LEN_UP (((REG32(ADR_PHY_REG_13_RX_DES)) & 0x3f000000 ) >> 24)
++#define GET_RG_RX_DES_SRVC_UP (((REG32(ADR_PHY_REG_14_RX_DES)) & 0x0000003f ) >> 0)
++#define GET_RG_RX_DES_L_LEN_LO (((REG32(ADR_PHY_REG_14_RX_DES)) & 0x00003f00 ) >> 8)
++#define GET_RG_RX_DES_L_LEN_UP (((REG32(ADR_PHY_REG_14_RX_DES)) & 0x003f0000 ) >> 16)
++#define GET_RG_RX_DES_TYPE (((REG32(ADR_PHY_REG_14_RX_DES)) & 0x3f000000 ) >> 24)
++#define GET_RG_RX_DES_L_LEN_UP_COMB (((REG32(ADR_PHY_REG_15_RX_DES)) & 0x00000001 ) >> 0)
++#define GET_RG_RX_DES_TYPE_COMB (((REG32(ADR_PHY_REG_15_RX_DES)) & 0x00000010 ) >> 4)
++#define GET_RG_RX_DES_RATE_COMB (((REG32(ADR_PHY_REG_15_RX_DES)) & 0x00000100 ) >> 8)
++#define GET_RG_RX_DES_MODE_COMB (((REG32(ADR_PHY_REG_15_RX_DES)) & 0x00001000 ) >> 12)
++#define GET_RG_RX_DES_SNR (((REG32(ADR_PHY_REG_15_RX_DES)) & 0x000f0000 ) >> 16)
++#define GET_RG_RX_DES_RCPI (((REG32(ADR_PHY_REG_15_RX_DES)) & 0x00f00000 ) >> 20)
++#define GET_RG_RX_DES_SRVC_LO (((REG32(ADR_PHY_REG_15_RX_DES)) & 0x3f000000 ) >> 24)
++#define GET_RO_TX_DES_EXCP_RATE_CNT (((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0x000000ff ) >> 0)
++#define GET_RO_TX_DES_EXCP_CH_BW_CNT (((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0x0000ff00 ) >> 8)
++#define GET_RO_TX_DES_EXCP_MODE_CNT (((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0x00ff0000 ) >> 16)
++#define GET_RG_TX_DES_EXCP_RATE_DEFAULT (((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0x07000000 ) >> 24)
++#define GET_RG_TX_DES_EXCP_MODE_DEFAULT (((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0x70000000 ) >> 28)
++#define GET_RG_TX_DES_EXCP_CLR (((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0x80000000 ) >> 31)
++#define GET_RG_TX_DES_ACK_WIDTH (((REG32(ADR_PHY_REG_17_TX_DES_EXCP)) & 0x00000001 ) >> 0)
++#define GET_RG_TX_DES_ACK_PRD (((REG32(ADR_PHY_REG_17_TX_DES_EXCP)) & 0x0000000e ) >> 1)
++#define GET_RG_RX_DES_SNR_GN (((REG32(ADR_PHY_REG_17_TX_DES_EXCP)) & 0x003f0000 ) >> 16)
++#define GET_RG_RX_DES_RCPI_GN (((REG32(ADR_PHY_REG_17_TX_DES_EXCP)) & 0x3f000000 ) >> 24)
++#define GET_RG_TST_TBUS_SEL (((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0x0000000f ) >> 0)
++#define GET_RG_RSSI_OFFSET (((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0x00ff0000 ) >> 16)
++#define GET_RG_RSSI_INV (((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0x01000000 ) >> 24)
++#define GET_RG_TST_ADC_ON (((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0x40000000 ) >> 30)
++#define GET_RG_TST_EXT_GAIN (((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0x80000000 ) >> 31)
++#define GET_RG_DAC_Q_SET (((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0x000003ff ) >> 0)
++#define GET_RG_DAC_I_SET (((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0x003ff000 ) >> 12)
++#define GET_RG_DAC_EN_MAN (((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0x10000000 ) >> 28)
++#define GET_RG_IQC_FFT_EN (((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0x20000000 ) >> 29)
++#define GET_RG_DAC_MAN_Q_EN (((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0x40000000 ) >> 30)
++#define GET_RG_DAC_MAN_I_EN (((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0x80000000 ) >> 31)
++#define GET_RO_MRX_EN_CNT (((REG32(ADR_PHY_REG_20_MRX_CNT)) & 0x0000ffff ) >> 0)
++#define GET_RG_MRX_EN_CNT_RST_N (((REG32(ADR_PHY_REG_20_MRX_CNT)) & 0x80000000 ) >> 31)
++#define GET_RG_PA_RISE_TIME (((REG32(ADR_PHY_REG_21_TRX_RAMP)) & 0x000000ff ) >> 0)
++#define GET_RG_RFTX_RISE_TIME (((REG32(ADR_PHY_REG_21_TRX_RAMP)) & 0x0000ff00 ) >> 8)
++#define GET_RG_DAC_RISE_TIME (((REG32(ADR_PHY_REG_21_TRX_RAMP)) & 0x00ff0000 ) >> 16)
++#define GET_RG_SW_RISE_TIME (((REG32(ADR_PHY_REG_21_TRX_RAMP)) & 0xff000000 ) >> 24)
++#define GET_RG_PA_FALL_TIME (((REG32(ADR_PHY_REG_22_TRX_RAMP)) & 0x000000ff ) >> 0)
++#define GET_RG_RFTX_FALL_TIME (((REG32(ADR_PHY_REG_22_TRX_RAMP)) & 0x0000ff00 ) >> 8)
++#define GET_RG_DAC_FALL_TIME (((REG32(ADR_PHY_REG_22_TRX_RAMP)) & 0x00ff0000 ) >> 16)
++#define GET_RG_SW_FALL_TIME (((REG32(ADR_PHY_REG_22_TRX_RAMP)) & 0xff000000 ) >> 24)
++#define GET_RG_ANT_SW_0 (((REG32(ADR_PHY_REG_23_ANT)) & 0x00000007 ) >> 0)
++#define GET_RG_ANT_SW_1 (((REG32(ADR_PHY_REG_23_ANT)) & 0x00000038 ) >> 3)
++#define GET_RG_MTX_LEN_LOWER_TH_0 (((REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) & 0x00001fff ) >> 0)
++#define GET_RG_MTX_LEN_UPPER_TH_0 (((REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) & 0x1fff0000 ) >> 16)
++#define GET_RG_MTX_LEN_CNT_EN_0 (((REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) & 0x80000000 ) >> 31)
++#define GET_RG_MTX_LEN_LOWER_TH_1 (((REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) & 0x00001fff ) >> 0)
++#define GET_RG_MTX_LEN_UPPER_TH_1 (((REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) & 0x1fff0000 ) >> 16)
++#define GET_RG_MTX_LEN_CNT_EN_1 (((REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) & 0x80000000 ) >> 31)
++#define GET_RG_MRX_LEN_LOWER_TH_0 (((REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) & 0x00001fff ) >> 0)
++#define GET_RG_MRX_LEN_UPPER_TH_0 (((REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) & 0x1fff0000 ) >> 16)
++#define GET_RG_MRX_LEN_CNT_EN_0 (((REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) & 0x80000000 ) >> 31)
++#define GET_RG_MRX_LEN_LOWER_TH_1 (((REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) & 0x00001fff ) >> 0)
++#define GET_RG_MRX_LEN_UPPER_TH_1 (((REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) & 0x1fff0000 ) >> 16)
++#define GET_RG_MRX_LEN_CNT_EN_1 (((REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) & 0x80000000 ) >> 31)
++#define GET_RO_MTX_LEN_CNT_1 (((REG32(ADR_PHY_READ_REG_04)) & 0x0000ffff ) >> 0)
++#define GET_RO_MTX_LEN_CNT_0 (((REG32(ADR_PHY_READ_REG_04)) & 0xffff0000 ) >> 16)
++#define GET_RO_MRX_LEN_CNT_1 (((REG32(ADR_PHY_READ_REG_05)) & 0x0000ffff ) >> 0)
++#define GET_RO_MRX_LEN_CNT_0 (((REG32(ADR_PHY_READ_REG_05)) & 0xffff0000 ) >> 16)
++#define GET_RG_MODE_REG_IN_16 (((REG32(ADR_PHY_REG_28_BIST)) & 0x0000ffff ) >> 0)
++#define GET_RG_PARALLEL_DR_16 (((REG32(ADR_PHY_REG_28_BIST)) & 0x00100000 ) >> 20)
++#define GET_RG_MBRUN_16 (((REG32(ADR_PHY_REG_28_BIST)) & 0x01000000 ) >> 24)
++#define GET_RG_SHIFT_DR_16 (((REG32(ADR_PHY_REG_28_BIST)) & 0x10000000 ) >> 28)
++#define GET_RG_MODE_REG_SI_16 (((REG32(ADR_PHY_REG_28_BIST)) & 0x20000000 ) >> 29)
++#define GET_RG_SIMULATION_MODE_16 (((REG32(ADR_PHY_REG_28_BIST)) & 0x40000000 ) >> 30)
++#define GET_RG_DBIST_MODE_16 (((REG32(ADR_PHY_REG_28_BIST)) & 0x80000000 ) >> 31)
++#define GET_RO_MODE_REG_OUT_16 (((REG32(ADR_PHY_READ_REG_06_BIST)) & 0x0000ffff ) >> 0)
++#define GET_RO_MODE_REG_SO_16 (((REG32(ADR_PHY_READ_REG_06_BIST)) & 0x01000000 ) >> 24)
++#define GET_RO_MONITOR_BUS_16 (((REG32(ADR_PHY_READ_REG_07_BIST)) & 0x0007ffff ) >> 0)
++#define GET_RG_MRX_TYPE_1 (((REG32(ADR_PHY_REG_29_MTRX_MAC)) & 0x000000ff ) >> 0)
++#define GET_RG_MRX_TYPE_0 (((REG32(ADR_PHY_REG_29_MTRX_MAC)) & 0x0000ff00 ) >> 8)
++#define GET_RG_MTX_TYPE_1 (((REG32(ADR_PHY_REG_29_MTRX_MAC)) & 0x00ff0000 ) >> 16)
++#define GET_RG_MTX_TYPE_0 (((REG32(ADR_PHY_REG_29_MTRX_MAC)) & 0xff000000 ) >> 24)
++#define GET_RO_MTX_TYPE_CNT_1 (((REG32(ADR_PHY_READ_REG_08_MTRX_MAC)) & 0x0000ffff ) >> 0)
++#define GET_RO_MTX_TYPE_CNT_0 (((REG32(ADR_PHY_READ_REG_08_MTRX_MAC)) & 0xffff0000 ) >> 16)
++#define GET_RO_MRX_TYPE_CNT_1 (((REG32(ADR_PHY_READ_REG_09_MTRX_MAC)) & 0x0000ffff ) >> 0)
++#define GET_RO_MRX_TYPE_CNT_0 (((REG32(ADR_PHY_READ_REG_09_MTRX_MAC)) & 0xffff0000 ) >> 16)
++#define GET_RG_HB_COEF0 (((REG32(ADR_PHY_REG_30_TX_UP_FIL)) & 0x00000fff ) >> 0)
++#define GET_RG_HB_COEF1 (((REG32(ADR_PHY_REG_30_TX_UP_FIL)) & 0x0fff0000 ) >> 16)
++#define GET_RG_HB_COEF2 (((REG32(ADR_PHY_REG_31_TX_UP_FIL)) & 0x00000fff ) >> 0)
++#define GET_RG_HB_COEF3 (((REG32(ADR_PHY_REG_31_TX_UP_FIL)) & 0x0fff0000 ) >> 16)
++#define GET_RG_HB_COEF4 (((REG32(ADR_PHY_REG_32_TX_UP_FIL)) & 0x00000fff ) >> 0)
++#define GET_RO_TBUS_O (((REG32(ADR_PHY_READ_TBUS)) & 0x000fffff ) >> 0)
++#define GET_RG_LPF4_00 (((REG32(ADR_TX_11B_FIL_COEF_00)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_01 (((REG32(ADR_TX_11B_FIL_COEF_01)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_02 (((REG32(ADR_TX_11B_FIL_COEF_02)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_03 (((REG32(ADR_TX_11B_FIL_COEF_03)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_04 (((REG32(ADR_TX_11B_FIL_COEF_04)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_05 (((REG32(ADR_TX_11B_FIL_COEF_05)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_06 (((REG32(ADR_TX_11B_FIL_COEF_06)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_07 (((REG32(ADR_TX_11B_FIL_COEF_07)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_08 (((REG32(ADR_TX_11B_FIL_COEF_08)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_09 (((REG32(ADR_TX_11B_FIL_COEF_09)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_10 (((REG32(ADR_TX_11B_FIL_COEF_10)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_11 (((REG32(ADR_TX_11B_FIL_COEF_11)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_12 (((REG32(ADR_TX_11B_FIL_COEF_12)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_13 (((REG32(ADR_TX_11B_FIL_COEF_13)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_14 (((REG32(ADR_TX_11B_FIL_COEF_14)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_15 (((REG32(ADR_TX_11B_FIL_COEF_15)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_16 (((REG32(ADR_TX_11B_FIL_COEF_16)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_17 (((REG32(ADR_TX_11B_FIL_COEF_17)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_18 (((REG32(ADR_TX_11B_FIL_COEF_18)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_19 (((REG32(ADR_TX_11B_FIL_COEF_19)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_20 (((REG32(ADR_TX_11B_FIL_COEF_20)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_21 (((REG32(ADR_TX_11B_FIL_COEF_21)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_22 (((REG32(ADR_TX_11B_FIL_COEF_22)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_23 (((REG32(ADR_TX_11B_FIL_COEF_23)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_24 (((REG32(ADR_TX_11B_FIL_COEF_24)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_25 (((REG32(ADR_TX_11B_FIL_COEF_25)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_26 (((REG32(ADR_TX_11B_FIL_COEF_26)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_27 (((REG32(ADR_TX_11B_FIL_COEF_27)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_28 (((REG32(ADR_TX_11B_FIL_COEF_28)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_29 (((REG32(ADR_TX_11B_FIL_COEF_29)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_30 (((REG32(ADR_TX_11B_FIL_COEF_30)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_31 (((REG32(ADR_TX_11B_FIL_COEF_31)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_32 (((REG32(ADR_TX_11B_FIL_COEF_32)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_33 (((REG32(ADR_TX_11B_FIL_COEF_33)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_34 (((REG32(ADR_TX_11B_FIL_COEF_34)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_35 (((REG32(ADR_TX_11B_FIL_COEF_35)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_36 (((REG32(ADR_TX_11B_FIL_COEF_36)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_37 (((REG32(ADR_TX_11B_FIL_COEF_37)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_38 (((REG32(ADR_TX_11B_FIL_COEF_38)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_39 (((REG32(ADR_TX_11B_FIL_COEF_39)) & 0x00001fff ) >> 0)
++#define GET_RG_LPF4_40 (((REG32(ADR_TX_11B_FIL_COEF_40)) & 0x00001fff ) >> 0)
++#define GET_RG_BP_SMB (((REG32(ADR_TX_11B_PLCP)) & 0x00002000 ) >> 13)
++#define GET_RG_EN_SRVC (((REG32(ADR_TX_11B_PLCP)) & 0x00004000 ) >> 14)
++#define GET_RG_DES_SPD (((REG32(ADR_TX_11B_PLCP)) & 0x00030000 ) >> 16)
++#define GET_RG_BB_11B_RISE_TIME (((REG32(ADR_TX_11B_RAMP)) & 0x000000ff ) >> 0)
++#define GET_RG_BB_11B_FALL_TIME (((REG32(ADR_TX_11B_RAMP)) & 0x0000ff00 ) >> 8)
++#define GET_RG_WR_TX_EN_CNT_RST_N (((REG32(ADR_TX_11B_EN_CNT_RST_N)) & 0x00000001 ) >> 0)
++#define GET_RO_TX_EN_CNT (((REG32(ADR_TX_11B_EN_CNT)) & 0x0000ffff ) >> 0)
++#define GET_RO_TX_CNT (((REG32(ADR_TX_11B_PKT_GEN_CNT)) & 0xffffffff ) >> 0)
++#define GET_RG_POS_DES_11B_L_EXT (((REG32(ADR_RX_11B_DES_DLY)) & 0x0000000f ) >> 0)
++#define GET_RG_PRE_DES_11B_DLY (((REG32(ADR_RX_11B_DES_DLY)) & 0x000000f0 ) >> 4)
++#define GET_RG_CNT_CCA_LMT (((REG32(ADR_RX_11B_CCA_0)) & 0x000f0000 ) >> 16)
++#define GET_RG_BYPASS_DESCRAMBLER (((REG32(ADR_RX_11B_CCA_0)) & 0x20000000 ) >> 29)
++#define GET_RG_BYPASS_AGC (((REG32(ADR_RX_11B_CCA_0)) & 0x80000000 ) >> 31)
++#define GET_RG_CCA_BIT_CNT_LMT_RX (((REG32(ADR_RX_11B_CCA_1)) & 0x000000f0 ) >> 4)
++#define GET_RG_CCA_SCALE_BF (((REG32(ADR_RX_11B_CCA_1)) & 0x007f0000 ) >> 16)
++#define GET_RG_PEAK_IDX_CNT_SEL (((REG32(ADR_RX_11B_CCA_1)) & 0x30000000 ) >> 28)
++#define GET_RG_TR_KI_T2 (((REG32(ADR_RX_11B_TR_KP_KI_0)) & 0x00000007 ) >> 0)
++#define GET_RG_TR_KP_T2 (((REG32(ADR_RX_11B_TR_KP_KI_0)) & 0x00000070 ) >> 4)
++#define GET_RG_TR_KI_T1 (((REG32(ADR_RX_11B_TR_KP_KI_0)) & 0x00000700 ) >> 8)
++#define GET_RG_TR_KP_T1 (((REG32(ADR_RX_11B_TR_KP_KI_0)) & 0x00007000 ) >> 12)
++#define GET_RG_CR_KI_T1 (((REG32(ADR_RX_11B_TR_KP_KI_1)) & 0x00070000 ) >> 16)
++#define GET_RG_CR_KP_T1 (((REG32(ADR_RX_11B_TR_KP_KI_1)) & 0x00700000 ) >> 20)
++#define GET_RG_CHIP_CNT_SLICER (((REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) & 0x0000001f ) >> 0)
++#define GET_RG_CE_T4_CNT_LMT (((REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) & 0x0000ff00 ) >> 8)
++#define GET_RG_CE_T3_CNT_LMT (((REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) & 0x00ff0000 ) >> 16)
++#define GET_RG_CE_T2_CNT_LMT (((REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) & 0xff000000 ) >> 24)
++#define GET_RG_CE_MU_T1 (((REG32(ADR_RX_11B_CE_MU_0)) & 0x00000007 ) >> 0)
++#define GET_RG_CE_DLY_SEL (((REG32(ADR_RX_11B_CE_MU_0)) & 0x003f0000 ) >> 16)
++#define GET_RG_CE_MU_T8 (((REG32(ADR_RX_11B_CE_MU_1)) & 0x00000007 ) >> 0)
++#define GET_RG_CE_MU_T7 (((REG32(ADR_RX_11B_CE_MU_1)) & 0x00000070 ) >> 4)
++#define GET_RG_CE_MU_T6 (((REG32(ADR_RX_11B_CE_MU_1)) & 0x00000700 ) >> 8)
++#define GET_RG_CE_MU_T5 (((REG32(ADR_RX_11B_CE_MU_1)) & 0x00007000 ) >> 12)
++#define GET_RG_CE_MU_T4 (((REG32(ADR_RX_11B_CE_MU_1)) & 0x00070000 ) >> 16)
++#define GET_RG_CE_MU_T3 (((REG32(ADR_RX_11B_CE_MU_1)) & 0x00700000 ) >> 20)
++#define GET_RG_CE_MU_T2 (((REG32(ADR_RX_11B_CE_MU_1)) & 0x07000000 ) >> 24)
++#define GET_RG_EQ_MU_FB_T2 (((REG32(ADR_RX_11B_EQ_MU_0)) & 0x0000000f ) >> 0)
++#define GET_RG_EQ_MU_FF_T2 (((REG32(ADR_RX_11B_EQ_MU_0)) & 0x000000f0 ) >> 4)
++#define GET_RG_EQ_MU_FB_T1 (((REG32(ADR_RX_11B_EQ_MU_0)) & 0x000f0000 ) >> 16)
++#define GET_RG_EQ_MU_FF_T1 (((REG32(ADR_RX_11B_EQ_MU_0)) & 0x00f00000 ) >> 20)
++#define GET_RG_EQ_MU_FB_T4 (((REG32(ADR_RX_11B_EQ_MU_1)) & 0x0000000f ) >> 0)
++#define GET_RG_EQ_MU_FF_T4 (((REG32(ADR_RX_11B_EQ_MU_1)) & 0x000000f0 ) >> 4)
++#define GET_RG_EQ_MU_FB_T3 (((REG32(ADR_RX_11B_EQ_MU_1)) & 0x000f0000 ) >> 16)
++#define GET_RG_EQ_MU_FF_T3 (((REG32(ADR_RX_11B_EQ_MU_1)) & 0x00f00000 ) >> 20)
++#define GET_RG_EQ_KI_T2 (((REG32(ADR_RX_11B_EQ_CR_KP_KI)) & 0x00000700 ) >> 8)
++#define GET_RG_EQ_KP_T2 (((REG32(ADR_RX_11B_EQ_CR_KP_KI)) & 0x00007000 ) >> 12)
++#define GET_RG_EQ_KI_T1 (((REG32(ADR_RX_11B_EQ_CR_KP_KI)) & 0x00070000 ) >> 16)
++#define GET_RG_EQ_KP_T1 (((REG32(ADR_RX_11B_EQ_CR_KP_KI)) & 0x00700000 ) >> 20)
++#define GET_RG_TR_LPF_RATE (((REG32(ADR_RX_11B_LPF_RATE)) & 0x003fffff ) >> 0)
++#define GET_RG_CE_BIT_CNT_LMT (((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0x0000007f ) >> 0)
++#define GET_RG_CE_CH_MAIN_SET (((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0x00000080 ) >> 7)
++#define GET_RG_TC_BIT_CNT_LMT (((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0x00007f00 ) >> 8)
++#define GET_RG_CR_BIT_CNT_LMT (((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0x007f0000 ) >> 16)
++#define GET_RG_TR_BIT_CNT_LMT (((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0x7f000000 ) >> 24)
++#define GET_RG_EQ_MAIN_TAP_MAN (((REG32(ADR_RX_11B_EQ_CH_MAIN_TAP)) & 0x00000001 ) >> 0)
++#define GET_RG_EQ_MAIN_TAP_COEF (((REG32(ADR_RX_11B_EQ_CH_MAIN_TAP)) & 0x07ff0000 ) >> 16)
++#define GET_RG_PWRON_DLY_TH_11B (((REG32(ADR_RX_11B_SEARCH_CNT_TH)) & 0x000000ff ) >> 0)
++#define GET_RG_SFD_BIT_CNT_LMT (((REG32(ADR_RX_11B_SEARCH_CNT_TH)) & 0x00ff0000 ) >> 16)
++#define GET_RG_CCA_PWR_TH_RX (((REG32(ADR_RX_11B_CCA_CONTROL)) & 0x00007fff ) >> 0)
++#define GET_RG_CCA_PWR_CNT_TH (((REG32(ADR_RX_11B_CCA_CONTROL)) & 0x001f0000 ) >> 16)
++#define GET_B_FREQ_OS (((REG32(ADR_RX_11B_FREQUENCY_OFFSET)) & 0x000007ff ) >> 0)
++#define GET_B_SNR (((REG32(ADR_RX_11B_SNR_RSSI)) & 0x0000007f ) >> 0)
++#define GET_B_RCPI (((REG32(ADR_RX_11B_SNR_RSSI)) & 0x007f0000 ) >> 16)
++#define GET_CRC_CNT (((REG32(ADR_RX_11B_SFD_CRC_CNT)) & 0x0000ffff ) >> 0)
++#define GET_SFD_CNT (((REG32(ADR_RX_11B_SFD_CRC_CNT)) & 0xffff0000 ) >> 16)
++#define GET_B_PACKET_ERR_CNT (((REG32(ADR_RX_11B_PKT_ERR_AND_PKT_ERR_CNT)) & 0x0000ffff ) >> 0)
++#define GET_PACKET_ERR (((REG32(ADR_RX_11B_PKT_ERR_AND_PKT_ERR_CNT)) & 0x00010000 ) >> 16)
++#define GET_B_PACKET_CNT (((REG32(ADR_RX_11B_PKT_CCA_AND_PKT_CNT)) & 0x0000ffff ) >> 0)
++#define GET_B_CCA_CNT (((REG32(ADR_RX_11B_PKT_CCA_AND_PKT_CNT)) & 0xffff0000 ) >> 16)
++#define GET_B_LENGTH_FIELD (((REG32(ADR_RX_11B_SFD_FILED_0)) & 0x0000ffff ) >> 0)
++#define GET_SFD_FIELD (((REG32(ADR_RX_11B_SFD_FILED_0)) & 0xffff0000 ) >> 16)
++#define GET_SIGNAL_FIELD (((REG32(ADR_RX_11B_SFD_FIELD_1)) & 0x000000ff ) >> 0)
++#define GET_B_SERVICE_FIELD (((REG32(ADR_RX_11B_SFD_FIELD_1)) & 0x0000ff00 ) >> 8)
++#define GET_CRC_CORRECT (((REG32(ADR_RX_11B_SFD_FIELD_1)) & 0x00010000 ) >> 16)
++#define GET_DEBUG_SEL (((REG32(ADR_RX_11B_PKT_STAT_EN)) & 0x0000000f ) >> 0)
++#define GET_RG_PACKET_STAT_EN_11B (((REG32(ADR_RX_11B_PKT_STAT_EN)) & 0x00100000 ) >> 20)
++#define GET_RG_BIT_REVERSE (((REG32(ADR_RX_11B_PKT_STAT_EN)) & 0x00200000 ) >> 21)
++#define GET_RX_PHY_11B_SOFT_RST_N (((REG32(ADR_RX_11B_SOFT_RST)) & 0x00000001 ) >> 0)
++#define GET_RG_CE_BYPASS_TAP (((REG32(ADR_RX_11B_SOFT_RST)) & 0x000000f0 ) >> 4)
++#define GET_RG_EQ_BYPASS_FBW_TAP (((REG32(ADR_RX_11B_SOFT_RST)) & 0x00000f00 ) >> 8)
++#define GET_RG_BB_11GN_RISE_TIME (((REG32(ADR_TX_11GN_RAMP)) & 0x000000ff ) >> 0)
++#define GET_RG_BB_11GN_FALL_TIME (((REG32(ADR_TX_11GN_RAMP)) & 0x0000ff00 ) >> 8)
++#define GET_RG_HTCARR52_FFT_SCALE (((REG32(ADR_TX_11GN_PLCP)) & 0x000003ff ) >> 0)
++#define GET_RG_HTCARR56_FFT_SCALE (((REG32(ADR_TX_11GN_PLCP)) & 0x003ff000 ) >> 12)
++#define GET_RG_PACKET_STAT_EN (((REG32(ADR_TX_11GN_PLCP)) & 0x00800000 ) >> 23)
++#define GET_RG_SMB_DEF (((REG32(ADR_TX_11GN_PLCP)) & 0x7f000000 ) >> 24)
++#define GET_RG_CONTINUOUS_DATA_11GN (((REG32(ADR_TX_11GN_PLCP)) & 0x80000000 ) >> 31)
++#define GET_RO_TX_CNT_R (((REG32(ADR_TX_11GN_PKT_GEN_CNT)) & 0xffffffff ) >> 0)
++#define GET_RO_PACKET_ERR_CNT (((REG32(ADR_TX_11GN_PLCP_CRC_ERR_CNT)) & 0x0000ffff ) >> 0)
++#define GET_RG_POS_DES_11GN_L_EXT (((REG32(ADR_RX_11GN_DES_DLY)) & 0x0000000f ) >> 0)
++#define GET_RG_PRE_DES_11GN_DLY (((REG32(ADR_RX_11GN_DES_DLY)) & 0x000000f0 ) >> 4)
++#define GET_RG_TR_LPF_KI_G_T1 (((REG32(ADR_RX_11GN_TR_0)) & 0x0000000f ) >> 0)
++#define GET_RG_TR_LPF_KP_G_T1 (((REG32(ADR_RX_11GN_TR_0)) & 0x000000f0 ) >> 4)
++#define GET_RG_TR_CNT_T1 (((REG32(ADR_RX_11GN_TR_0)) & 0x0000ff00 ) >> 8)
++#define GET_RG_TR_LPF_KI_G_T0 (((REG32(ADR_RX_11GN_TR_0)) & 0x000f0000 ) >> 16)
++#define GET_RG_TR_LPF_KP_G_T0 (((REG32(ADR_RX_11GN_TR_0)) & 0x00f00000 ) >> 20)
++#define GET_RG_TR_CNT_T0 (((REG32(ADR_RX_11GN_TR_0)) & 0xff000000 ) >> 24)
++#define GET_RG_TR_LPF_KI_G_T2 (((REG32(ADR_RX_11GN_TR_1)) & 0x0000000f ) >> 0)
++#define GET_RG_TR_LPF_KP_G_T2 (((REG32(ADR_RX_11GN_TR_1)) & 0x000000f0 ) >> 4)
++#define GET_RG_TR_CNT_T2 (((REG32(ADR_RX_11GN_TR_1)) & 0x0000ff00 ) >> 8)
++#define GET_RG_TR_LPF_KI_G (((REG32(ADR_RX_11GN_TR_2)) & 0x0000000f ) >> 0)
++#define GET_RG_TR_LPF_KP_G (((REG32(ADR_RX_11GN_TR_2)) & 0x000000f0 ) >> 4)
++#define GET_RG_TR_LPF_RATE_G (((REG32(ADR_RX_11GN_TR_2)) & 0x3fffff00 ) >> 8)
++#define GET_RG_CR_LPF_KI_G (((REG32(ADR_RX_11GN_CCA_0)) & 0x00000007 ) >> 0)
++#define GET_RG_SYM_BOUND_CNT (((REG32(ADR_RX_11GN_CCA_0)) & 0x00007f00 ) >> 8)
++#define GET_RG_XSCOR32_RATIO (((REG32(ADR_RX_11GN_CCA_0)) & 0x007f0000 ) >> 16)
++#define GET_RG_ATCOR64_CNT_LMT (((REG32(ADR_RX_11GN_CCA_0)) & 0x7f000000 ) >> 24)
++#define GET_RG_ATCOR16_CNT_LMT2 (((REG32(ADR_RX_11GN_CCA_1)) & 0x00007f00 ) >> 8)
++#define GET_RG_ATCOR16_CNT_LMT1 (((REG32(ADR_RX_11GN_CCA_1)) & 0x007f0000 ) >> 16)
++#define GET_RG_ATCOR16_RATIO_SB (((REG32(ADR_RX_11GN_CCA_1)) & 0x7f000000 ) >> 24)
++#define GET_RG_XSCOR64_CNT_LMT2 (((REG32(ADR_RX_11GN_CCA_2)) & 0x007f0000 ) >> 16)
++#define GET_RG_XSCOR64_CNT_LMT1 (((REG32(ADR_RX_11GN_CCA_2)) & 0x7f000000 ) >> 24)
++#define GET_RG_RX_FFT_SCALE (((REG32(ADR_RX_11GN_CCA_FFT_SCALE)) & 0x000003ff ) >> 0)
++#define GET_RG_VITERBI_AB_SWAP (((REG32(ADR_RX_11GN_CCA_FFT_SCALE)) & 0x00010000 ) >> 16)
++#define GET_RG_ATCOR16_CNT_TH (((REG32(ADR_RX_11GN_CCA_FFT_SCALE)) & 0x0f000000 ) >> 24)
++#define GET_RG_NORMSQUARE_LOW_SNR_7 (((REG32(ADR_RX_11GN_SOFT_DEMAP_0)) & 0x000000ff ) >> 0)
++#define GET_RG_NORMSQUARE_LOW_SNR_6 (((REG32(ADR_RX_11GN_SOFT_DEMAP_0)) & 0x0000ff00 ) >> 8)
++#define GET_RG_NORMSQUARE_LOW_SNR_5 (((REG32(ADR_RX_11GN_SOFT_DEMAP_0)) & 0x00ff0000 ) >> 16)
++#define GET_RG_NORMSQUARE_LOW_SNR_4 (((REG32(ADR_RX_11GN_SOFT_DEMAP_0)) & 0xff000000 ) >> 24)
++#define GET_RG_NORMSQUARE_LOW_SNR_8 (((REG32(ADR_RX_11GN_SOFT_DEMAP_1)) & 0xff000000 ) >> 24)
++#define GET_RG_NORMSQUARE_SNR_3 (((REG32(ADR_RX_11GN_SOFT_DEMAP_2)) & 0x000000ff ) >> 0)
++#define GET_RG_NORMSQUARE_SNR_2 (((REG32(ADR_RX_11GN_SOFT_DEMAP_2)) & 0x0000ff00 ) >> 8)
++#define GET_RG_NORMSQUARE_SNR_1 (((REG32(ADR_RX_11GN_SOFT_DEMAP_2)) & 0x00ff0000 ) >> 16)
++#define GET_RG_NORMSQUARE_SNR_0 (((REG32(ADR_RX_11GN_SOFT_DEMAP_2)) & 0xff000000 ) >> 24)
++#define GET_RG_NORMSQUARE_SNR_7 (((REG32(ADR_RX_11GN_SOFT_DEMAP_3)) & 0x000000ff ) >> 0)
++#define GET_RG_NORMSQUARE_SNR_6 (((REG32(ADR_RX_11GN_SOFT_DEMAP_3)) & 0x0000ff00 ) >> 8)
++#define GET_RG_NORMSQUARE_SNR_5 (((REG32(ADR_RX_11GN_SOFT_DEMAP_3)) & 0x00ff0000 ) >> 16)
++#define GET_RG_NORMSQUARE_SNR_4 (((REG32(ADR_RX_11GN_SOFT_DEMAP_3)) & 0xff000000 ) >> 24)
++#define GET_RG_NORMSQUARE_SNR_8 (((REG32(ADR_RX_11GN_SOFT_DEMAP_4)) & 0xff000000 ) >> 24)
++#define GET_RG_SNR_TH_64QAM (((REG32(ADR_RX_11GN_SOFT_DEMAP_5)) & 0x0000007f ) >> 0)
++#define GET_RG_SNR_TH_16QAM (((REG32(ADR_RX_11GN_SOFT_DEMAP_5)) & 0x00007f00 ) >> 8)
++#define GET_RG_ATCOR16_CNT_PLUS_LMT2 (((REG32(ADR_RX_11GN_SYM_BOUND_0)) & 0x0000007f ) >> 0)
++#define GET_RG_ATCOR16_CNT_PLUS_LMT1 (((REG32(ADR_RX_11GN_SYM_BOUND_0)) & 0x00007f00 ) >> 8)
++#define GET_RG_SYM_BOUND_METHOD (((REG32(ADR_RX_11GN_SYM_BOUND_0)) & 0x00030000 ) >> 16)
++#define GET_RG_PWRON_DLY_TH_11GN (((REG32(ADR_RX_11GN_SYM_BOUND_1)) & 0x000000ff ) >> 0)
++#define GET_RG_SB_START_CNT (((REG32(ADR_RX_11GN_SYM_BOUND_1)) & 0x00007f00 ) >> 8)
++#define GET_RG_POW16_CNT_TH (((REG32(ADR_RX_11GN_CCA_PWR)) & 0x000000f0 ) >> 4)
++#define GET_RG_POW16_SHORT_CNT_LMT (((REG32(ADR_RX_11GN_CCA_PWR)) & 0x00000700 ) >> 8)
++#define GET_RG_POW16_TH_L (((REG32(ADR_RX_11GN_CCA_PWR)) & 0x7f000000 ) >> 24)
++#define GET_RG_XSCOR16_SHORT_CNT_LMT (((REG32(ADR_RX_11GN_CCA_CNT)) & 0x00000007 ) >> 0)
++#define GET_RG_XSCOR16_RATIO (((REG32(ADR_RX_11GN_CCA_CNT)) & 0x00007f00 ) >> 8)
++#define GET_RG_ATCOR16_SHORT_CNT_LMT (((REG32(ADR_RX_11GN_CCA_CNT)) & 0x00070000 ) >> 16)
++#define GET_RG_ATCOR16_RATIO_CCD (((REG32(ADR_RX_11GN_CCA_CNT)) & 0x7f000000 ) >> 24)
++#define GET_RG_ATCOR64_ACC_LMT (((REG32(ADR_RX_11GN_CCA_ATCOR_RE_CHECK)) & 0x0000007f ) >> 0)
++#define GET_RG_ATCOR16_SHORT_CNT_LMT2 (((REG32(ADR_RX_11GN_CCA_ATCOR_RE_CHECK)) & 0x00070000 ) >> 16)
++#define GET_RG_VITERBI_TB_BITS (((REG32(ADR_RX_11GN_VTB_TB)) & 0xff000000 ) >> 24)
++#define GET_RG_CR_CNT_UPDATE (((REG32(ADR_RX_11GN_ERR_UPDATE)) & 0x000000ff ) >> 0)
++#define GET_RG_TR_CNT_UPDATE (((REG32(ADR_RX_11GN_ERR_UPDATE)) & 0x00ff0000 ) >> 16)
++#define GET_RG_BYPASS_CPE_MA (((REG32(ADR_RX_11GN_SHORT_GI)) & 0x00000010 ) >> 4)
++#define GET_RG_PILOT_BNDRY_SHIFT (((REG32(ADR_RX_11GN_SHORT_GI)) & 0x00000700 ) >> 8)
++#define GET_RG_EQ_SHORT_GI_SHIFT (((REG32(ADR_RX_11GN_SHORT_GI)) & 0x00007000 ) >> 12)
++#define GET_RG_FFT_WDW_SHORT_SHIFT (((REG32(ADR_RX_11GN_SHORT_GI)) & 0x00070000 ) >> 16)
++#define GET_RG_CHSMTH_COEF (((REG32(ADR_RX_11GN_CHANNEL_UPDATE)) & 0x00030000 ) >> 16)
++#define GET_RG_CHSMTH_EN (((REG32(ADR_RX_11GN_CHANNEL_UPDATE)) & 0x00040000 ) >> 18)
++#define GET_RG_CHEST_DD_FACTOR (((REG32(ADR_RX_11GN_CHANNEL_UPDATE)) & 0x07000000 ) >> 24)
++#define GET_RG_CH_UPDATE (((REG32(ADR_RX_11GN_CHANNEL_UPDATE)) & 0x80000000 ) >> 31)
++#define GET_RG_FMT_DET_MM_TH (((REG32(ADR_RX_11GN_PKT_FORMAT_0)) & 0x000000ff ) >> 0)
++#define GET_RG_FMT_DET_GF_TH (((REG32(ADR_RX_11GN_PKT_FORMAT_0)) & 0x0000ff00 ) >> 8)
++#define GET_RG_DO_NOT_CHECK_L_RATE (((REG32(ADR_RX_11GN_PKT_FORMAT_0)) & 0x02000000 ) >> 25)
++#define GET_RG_FMT_DET_LENGTH_TH (((REG32(ADR_RX_11GN_PKT_FORMAT_1)) & 0x0000ffff ) >> 0)
++#define GET_RG_L_LENGTH_MAX (((REG32(ADR_RX_11GN_PKT_FORMAT_1)) & 0xffff0000 ) >> 16)
++#define GET_RG_TX_TIME_EXT (((REG32(ADR_RX_11GN_TX_TIME)) & 0x000000ff ) >> 0)
++#define GET_RG_MAC_DES_SPACE (((REG32(ADR_RX_11GN_TX_TIME)) & 0x00f00000 ) >> 20)
++#define GET_RG_TR_LPF_STBC_GF_KI_G (((REG32(ADR_RX_11GN_STBC_TR_KP_KI)) & 0x0000000f ) >> 0)
++#define GET_RG_TR_LPF_STBC_GF_KP_G (((REG32(ADR_RX_11GN_STBC_TR_KP_KI)) & 0x000000f0 ) >> 4)
++#define GET_RG_TR_LPF_STBC_MF_KI_G (((REG32(ADR_RX_11GN_STBC_TR_KP_KI)) & 0x00000f00 ) >> 8)
++#define GET_RG_TR_LPF_STBC_MF_KP_G (((REG32(ADR_RX_11GN_STBC_TR_KP_KI)) & 0x0000f000 ) >> 12)
++#define GET_RG_MODE_REG_IN_80 (((REG32(ADR_RX_11GN_BIST_0)) & 0x0001ffff ) >> 0)
++#define GET_RG_PARALLEL_DR_80 (((REG32(ADR_RX_11GN_BIST_0)) & 0x00100000 ) >> 20)
++#define GET_RG_MBRUN_80 (((REG32(ADR_RX_11GN_BIST_0)) & 0x01000000 ) >> 24)
++#define GET_RG_SHIFT_DR_80 (((REG32(ADR_RX_11GN_BIST_0)) & 0x10000000 ) >> 28)
++#define GET_RG_MODE_REG_SI_80 (((REG32(ADR_RX_11GN_BIST_0)) & 0x20000000 ) >> 29)
++#define GET_RG_SIMULATION_MODE_80 (((REG32(ADR_RX_11GN_BIST_0)) & 0x40000000 ) >> 30)
++#define GET_RG_DBIST_MODE_80 (((REG32(ADR_RX_11GN_BIST_0)) & 0x80000000 ) >> 31)
++#define GET_RG_MODE_REG_IN_64 (((REG32(ADR_RX_11GN_BIST_1)) & 0x0000ffff ) >> 0)
++#define GET_RG_PARALLEL_DR_64 (((REG32(ADR_RX_11GN_BIST_1)) & 0x00100000 ) >> 20)
++#define GET_RG_MBRUN_64 (((REG32(ADR_RX_11GN_BIST_1)) & 0x01000000 ) >> 24)
++#define GET_RG_SHIFT_DR_64 (((REG32(ADR_RX_11GN_BIST_1)) & 0x10000000 ) >> 28)
++#define GET_RG_MODE_REG_SI_64 (((REG32(ADR_RX_11GN_BIST_1)) & 0x20000000 ) >> 29)
++#define GET_RG_SIMULATION_MODE_64 (((REG32(ADR_RX_11GN_BIST_1)) & 0x40000000 ) >> 30)
++#define GET_RG_DBIST_MODE_64 (((REG32(ADR_RX_11GN_BIST_1)) & 0x80000000 ) >> 31)
++#define GET_RO_MODE_REG_OUT_80 (((REG32(ADR_RX_11GN_BIST_2)) & 0x0001ffff ) >> 0)
++#define GET_RO_MODE_REG_SO_80 (((REG32(ADR_RX_11GN_BIST_2)) & 0x01000000 ) >> 24)
++#define GET_RO_MONITOR_BUS_80 (((REG32(ADR_RX_11GN_BIST_3)) & 0x003fffff ) >> 0)
++#define GET_RO_MODE_REG_OUT_64 (((REG32(ADR_RX_11GN_BIST_4)) & 0x0000ffff ) >> 0)
++#define GET_RO_MODE_REG_SO_64 (((REG32(ADR_RX_11GN_BIST_4)) & 0x01000000 ) >> 24)
++#define GET_RO_MONITOR_BUS_64 (((REG32(ADR_RX_11GN_BIST_5)) & 0x0007ffff ) >> 0)
++#define GET_RO_SPECTRUM_DATA (((REG32(ADR_RX_11GN_SPECTRUM_ANALYZER)) & 0xffffffff ) >> 0)
++#define GET_GN_SNR (((REG32(ADR_RX_11GN_READ_0)) & 0x0000007f ) >> 0)
++#define GET_GN_NOISE_PWR (((REG32(ADR_RX_11GN_READ_0)) & 0x00007f00 ) >> 8)
++#define GET_GN_RCPI (((REG32(ADR_RX_11GN_READ_0)) & 0x007f0000 ) >> 16)
++#define GET_GN_SIGNAL_PWR (((REG32(ADR_RX_11GN_READ_0)) & 0x7f000000 ) >> 24)
++#define GET_RO_FREQ_OS_LTS (((REG32(ADR_RX_11GN_FREQ_OFFSET)) & 0x00007fff ) >> 0)
++#define GET_CSTATE (((REG32(ADR_RX_11GN_FREQ_OFFSET)) & 0x000f0000 ) >> 16)
++#define GET_SIGNAL_FIELD0 (((REG32(ADR_RX_11GN_SIGNAL_FIELD_0)) & 0x00ffffff ) >> 0)
++#define GET_SIGNAL_FIELD1 (((REG32(ADR_RX_11GN_SIGNAL_FIELD_1)) & 0x00ffffff ) >> 0)
++#define GET_GN_PACKET_ERR_CNT (((REG32(ADR_RX_11GN_PKT_ERR_CNT)) & 0x0000ffff ) >> 0)
++#define GET_GN_PACKET_CNT (((REG32(ADR_RX_11GN_PKT_CCA_AND_PKT_CNT)) & 0x0000ffff ) >> 0)
++#define GET_GN_CCA_CNT (((REG32(ADR_RX_11GN_PKT_CCA_AND_PKT_CNT)) & 0xffff0000 ) >> 16)
++#define GET_GN_LENGTH_FIELD (((REG32(ADR_RX_11GN_SERVICE_LENGTH_FIELD)) & 0x0000ffff ) >> 0)
++#define GET_GN_SERVICE_FIELD (((REG32(ADR_RX_11GN_SERVICE_LENGTH_FIELD)) & 0xffff0000 ) >> 16)
++#define GET_RO_HT_MCS_40M (((REG32(ADR_RX_11GN_RATE)) & 0x0000007f ) >> 0)
++#define GET_RO_L_RATE_40M (((REG32(ADR_RX_11GN_RATE)) & 0x00003f00 ) >> 8)
++#define GET_RG_DAGC_CNT_TH (((REG32(ADR_RX_11GN_STAT_EN)) & 0x00000003 ) >> 0)
++#define GET_RG_PACKET_STAT_EN_11GN (((REG32(ADR_RX_11GN_STAT_EN)) & 0x00100000 ) >> 20)
++#define GET_RX_PHY_11GN_SOFT_RST_N (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000001 ) >> 0)
++#define GET_RG_RIFS_EN (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000002 ) >> 1)
++#define GET_RG_STBC_EN (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000004 ) >> 2)
++#define GET_RG_COR_SEL (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000008 ) >> 3)
++#define GET_RG_INI_PHASE (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000030 ) >> 4)
++#define GET_RG_HT_LTF_SEL_EQ (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000040 ) >> 6)
++#define GET_RG_HT_LTF_SEL_PILOT (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000080 ) >> 7)
++#define GET_RG_CCA_PWR_SEL (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000200 ) >> 9)
++#define GET_RG_CCA_XSCOR_PWR_SEL (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000400 ) >> 10)
++#define GET_RG_CCA_XSCOR_AVGPWR_SEL (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000800 ) >> 11)
++#define GET_RG_DEBUG_SEL (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x0000f000 ) >> 12)
++#define GET_RG_POST_CLK_EN (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00010000 ) >> 16)
++#define GET_IQCAL_RF_TX_EN (((REG32(ADR_RF_CONTROL_0)) & 0x00000001 ) >> 0)
++#define GET_IQCAL_RF_TX_PA_EN (((REG32(ADR_RF_CONTROL_0)) & 0x00000002 ) >> 1)
++#define GET_IQCAL_RF_TX_DAC_EN (((REG32(ADR_RF_CONTROL_0)) & 0x00000004 ) >> 2)
++#define GET_IQCAL_RF_RX_AGC (((REG32(ADR_RF_CONTROL_0)) & 0x00000008 ) >> 3)
++#define GET_IQCAL_RF_PGAG (((REG32(ADR_RF_CONTROL_0)) & 0x00000f00 ) >> 8)
++#define GET_IQCAL_RF_RFG (((REG32(ADR_RF_CONTROL_0)) & 0x00003000 ) >> 12)
++#define GET_RG_TONEGEN_FREQ (((REG32(ADR_RF_CONTROL_0)) & 0x007f0000 ) >> 16)
++#define GET_RG_TONEGEN_EN (((REG32(ADR_RF_CONTROL_0)) & 0x00800000 ) >> 23)
++#define GET_RG_TONEGEN_INIT_PH (((REG32(ADR_RF_CONTROL_0)) & 0x7f000000 ) >> 24)
++#define GET_RG_TONEGEN2_FREQ (((REG32(ADR_RF_CONTROL_1)) & 0x0000007f ) >> 0)
++#define GET_RG_TONEGEN2_EN (((REG32(ADR_RF_CONTROL_1)) & 0x00000080 ) >> 7)
++#define GET_RG_TONEGEN2_SCALE (((REG32(ADR_RF_CONTROL_1)) & 0x0000ff00 ) >> 8)
++#define GET_RG_TXIQ_CLP_THD_I (((REG32(ADR_TX_IQ_CONTROL_0)) & 0x000003ff ) >> 0)
++#define GET_RG_TXIQ_CLP_THD_Q (((REG32(ADR_TX_IQ_CONTROL_0)) & 0x03ff0000 ) >> 16)
++#define GET_RG_TX_I_SCALE (((REG32(ADR_TX_IQ_CONTROL_1)) & 0x000000ff ) >> 0)
++#define GET_RG_TX_Q_SCALE (((REG32(ADR_TX_IQ_CONTROL_1)) & 0x0000ff00 ) >> 8)
++#define GET_RG_TX_IQ_SWP (((REG32(ADR_TX_IQ_CONTROL_1)) & 0x00010000 ) >> 16)
++#define GET_RG_TX_SGN_OUT (((REG32(ADR_TX_IQ_CONTROL_1)) & 0x00020000 ) >> 17)
++#define GET_RG_TXIQ_EMU_IDX (((REG32(ADR_TX_IQ_CONTROL_1)) & 0x003c0000 ) >> 18)
++#define GET_RG_TX_IQ_SRC (((REG32(ADR_TX_IQ_CONTROL_1)) & 0x03000000 ) >> 24)
++#define GET_RG_TX_I_DC (((REG32(ADR_TX_IQ_CONTROL_2)) & 0x000003ff ) >> 0)
++#define GET_RG_TX_Q_DC (((REG32(ADR_TX_IQ_CONTROL_2)) & 0x03ff0000 ) >> 16)
++#define GET_RG_TX_IQ_THETA (((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0x0000001f ) >> 0)
++#define GET_RG_TX_IQ_ALPHA (((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0x00001f00 ) >> 8)
++#define GET_RG_TXIQ_NOSHRINK (((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0x00002000 ) >> 13)
++#define GET_RG_TX_I_OFFSET (((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0x00ff0000 ) >> 16)
++#define GET_RG_TX_Q_OFFSET (((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0xff000000 ) >> 24)
++#define GET_RG_RX_IQ_THETA (((REG32(ADR_RX_COMPENSATION_CONTROL)) & 0x0000001f ) >> 0)
++#define GET_RG_RX_IQ_ALPHA (((REG32(ADR_RX_COMPENSATION_CONTROL)) & 0x00001f00 ) >> 8)
++#define GET_RG_RXIQ_NOSHRINK (((REG32(ADR_RX_COMPENSATION_CONTROL)) & 0x00002000 ) >> 13)
++#define GET_RG_MA_DPTH (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x0000000f ) >> 0)
++#define GET_RG_INTG_PH (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x000003f0 ) >> 4)
++#define GET_RG_INTG_PRD (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x00001c00 ) >> 10)
++#define GET_RG_INTG_MU (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x00006000 ) >> 13)
++#define GET_RG_IQCAL_SPRM_SELQ (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x00010000 ) >> 16)
++#define GET_RG_IQCAL_SPRM_EN (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x00020000 ) >> 17)
++#define GET_RG_IQCAL_SPRM_FREQ (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x00fc0000 ) >> 18)
++#define GET_RG_IQCAL_IQCOL_EN (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x01000000 ) >> 24)
++#define GET_RG_IQCAL_ALPHA_ESTM_EN (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x02000000 ) >> 25)
++#define GET_RG_IQCAL_DC_EN (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x04000000 ) >> 26)
++#define GET_RG_PHEST_STBY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x08000000 ) >> 27)
++#define GET_RG_PHEST_EN (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x10000000 ) >> 28)
++#define GET_RG_GP_DIV_EN (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x20000000 ) >> 29)
++#define GET_RG_DPD_GAIN_EST_EN (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x40000000 ) >> 30)
++#define GET_RG_IQCAL_MULT_OP0 (((REG32(ADR_RX_OBSERVATION_CIRCUIT_1)) & 0x000003ff ) >> 0)
++#define GET_RG_IQCAL_MULT_OP1 (((REG32(ADR_RX_OBSERVATION_CIRCUIT_1)) & 0x03ff0000 ) >> 16)
++#define GET_RO_IQCAL_O (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x000fffff ) >> 0)
++#define GET_RO_IQCAL_SPRM_RDY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x00100000 ) >> 20)
++#define GET_RO_IQCAL_IQCOL_RDY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x00200000 ) >> 21)
++#define GET_RO_IQCAL_ALPHA_ESTM_RDY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x00400000 ) >> 22)
++#define GET_RO_IQCAL_DC_RDY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x00800000 ) >> 23)
++#define GET_RO_IQCAL_MULT_RDY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x01000000 ) >> 24)
++#define GET_RO_FFT_ENRG_RDY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x02000000 ) >> 25)
++#define GET_RO_PHEST_RDY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x04000000 ) >> 26)
++#define GET_RO_GP_DIV_RDY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x08000000 ) >> 27)
++#define GET_RO_GAIN_EST_RDY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x10000000 ) >> 28)
++#define GET_RO_AMP_O (((REG32(ADR_RX_OBSERVATION_CIRCUIT_3)) & 0x000001ff ) >> 0)
++#define GET_RG_RX_I_SCALE (((REG32(ADR_RF_IQ_CONTROL_0)) & 0x000000ff ) >> 0)
++#define GET_RG_RX_Q_SCALE (((REG32(ADR_RF_IQ_CONTROL_0)) & 0x0000ff00 ) >> 8)
++#define GET_RG_RX_I_OFFSET (((REG32(ADR_RF_IQ_CONTROL_0)) & 0x00ff0000 ) >> 16)
++#define GET_RG_RX_Q_OFFSET (((REG32(ADR_RF_IQ_CONTROL_0)) & 0xff000000 ) >> 24)
++#define GET_RG_RX_IQ_SWP (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x00000001 ) >> 0)
++#define GET_RG_RX_SGN_IN (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x00000002 ) >> 1)
++#define GET_RG_RX_IQ_SRC (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x0000000c ) >> 2)
++#define GET_RG_ACI_GAIN (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x00000ff0 ) >> 4)
++#define GET_RG_FFT_EN (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x00001000 ) >> 12)
++#define GET_RG_FFT_MOD (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x00002000 ) >> 13)
++#define GET_RG_FFT_SCALE (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x00ffc000 ) >> 14)
++#define GET_RG_FFT_ENRG_FREQ (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x3f000000 ) >> 24)
++#define GET_RG_FPGA_80M_PH_UP (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x40000000 ) >> 30)
++#define GET_RG_FPGA_80M_PH_STP (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x80000000 ) >> 31)
++#define GET_RG_ADC2LA_SEL (((REG32(ADR_RF_IQ_CONTROL_2)) & 0x00000001 ) >> 0)
++#define GET_RG_ADC2LA_CLKPH (((REG32(ADR_RF_IQ_CONTROL_2)) & 0x00000002 ) >> 1)
++#define GET_RG_RXIQ_EMU_IDX (((REG32(ADR_RF_IQ_CONTROL_3)) & 0x0000000f ) >> 0)
++#define GET_RG_IQCAL_BP_ACI (((REG32(ADR_RF_IQ_CONTROL_3)) & 0x00000010 ) >> 4)
++#define GET_RG_DPD_AM_EN (((REG32(ADR_DPD_CONTROL)) & 0x00000001 ) >> 0)
++#define GET_RG_DPD_PM_EN (((REG32(ADR_DPD_CONTROL)) & 0x00000002 ) >> 1)
++#define GET_RG_DPD_PM_AMSEL (((REG32(ADR_DPD_CONTROL)) & 0x00000004 ) >> 2)
++#define GET_RG_DPD_020_GAIN (((REG32(ADR_DPD_GAIN_TABLE_0)) & 0x000003ff ) >> 0)
++#define GET_RG_DPD_040_GAIN (((REG32(ADR_DPD_GAIN_TABLE_0)) & 0x03ff0000 ) >> 16)
++#define GET_RG_DPD_060_GAIN (((REG32(ADR_DPD_GAIN_TABLE_1)) & 0x000003ff ) >> 0)
++#define GET_RG_DPD_080_GAIN (((REG32(ADR_DPD_GAIN_TABLE_1)) & 0x03ff0000 ) >> 16)
++#define GET_RG_DPD_0A0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_2)) & 0x000003ff ) >> 0)
++#define GET_RG_DPD_0C0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_2)) & 0x03ff0000 ) >> 16)
++#define GET_RG_DPD_0D0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_3)) & 0x000003ff ) >> 0)
++#define GET_RG_DPD_0E0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_3)) & 0x03ff0000 ) >> 16)
++#define GET_RG_DPD_0F0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_4)) & 0x000003ff ) >> 0)
++#define GET_RG_DPD_100_GAIN (((REG32(ADR_DPD_GAIN_TABLE_4)) & 0x03ff0000 ) >> 16)
++#define GET_RG_DPD_110_GAIN (((REG32(ADR_DPD_GAIN_TABLE_5)) & 0x000003ff ) >> 0)
++#define GET_RG_DPD_120_GAIN (((REG32(ADR_DPD_GAIN_TABLE_5)) & 0x03ff0000 ) >> 16)
++#define GET_RG_DPD_130_GAIN (((REG32(ADR_DPD_GAIN_TABLE_6)) & 0x000003ff ) >> 0)
++#define GET_RG_DPD_140_GAIN (((REG32(ADR_DPD_GAIN_TABLE_6)) & 0x03ff0000 ) >> 16)
++#define GET_RG_DPD_150_GAIN (((REG32(ADR_DPD_GAIN_TABLE_7)) & 0x000003ff ) >> 0)
++#define GET_RG_DPD_160_GAIN (((REG32(ADR_DPD_GAIN_TABLE_7)) & 0x03ff0000 ) >> 16)
++#define GET_RG_DPD_170_GAIN (((REG32(ADR_DPD_GAIN_TABLE_8)) & 0x000003ff ) >> 0)
++#define GET_RG_DPD_180_GAIN (((REG32(ADR_DPD_GAIN_TABLE_8)) & 0x03ff0000 ) >> 16)
++#define GET_RG_DPD_190_GAIN (((REG32(ADR_DPD_GAIN_TABLE_9)) & 0x000003ff ) >> 0)
++#define GET_RG_DPD_1A0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_9)) & 0x03ff0000 ) >> 16)
++#define GET_RG_DPD_1B0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_A)) & 0x000003ff ) >> 0)
++#define GET_RG_DPD_1C0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_A)) & 0x03ff0000 ) >> 16)
++#define GET_RG_DPD_1D0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_B)) & 0x000003ff ) >> 0)
++#define GET_RG_DPD_1E0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_B)) & 0x03ff0000 ) >> 16)
++#define GET_RG_DPD_1F0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_C)) & 0x000003ff ) >> 0)
++#define GET_RG_DPD_200_GAIN (((REG32(ADR_DPD_GAIN_TABLE_C)) & 0x03ff0000 ) >> 16)
++#define GET_RG_DPD_020_PH (((REG32(ADR_DPD_PH_TABLE_0)) & 0x00001fff ) >> 0)
++#define GET_RG_DPD_040_PH (((REG32(ADR_DPD_PH_TABLE_0)) & 0x1fff0000 ) >> 16)
++#define GET_RG_DPD_060_PH (((REG32(ADR_DPD_PH_TABLE_1)) & 0x00001fff ) >> 0)
++#define GET_RG_DPD_080_PH (((REG32(ADR_DPD_PH_TABLE_1)) & 0x1fff0000 ) >> 16)
++#define GET_RG_DPD_0A0_PH (((REG32(ADR_DPD_PH_TABLE_2)) & 0x00001fff ) >> 0)
++#define GET_RG_DPD_0C0_PH (((REG32(ADR_DPD_PH_TABLE_2)) & 0x1fff0000 ) >> 16)
++#define GET_RG_DPD_0D0_PH (((REG32(ADR_DPD_PH_TABLE_3)) & 0x00001fff ) >> 0)
++#define GET_RG_DPD_0E0_PH (((REG32(ADR_DPD_PH_TABLE_3)) & 0x1fff0000 ) >> 16)
++#define GET_RG_DPD_0F0_PH (((REG32(ADR_DPD_PH_TABLE_4)) & 0x00001fff ) >> 0)
++#define GET_RG_DPD_100_PH (((REG32(ADR_DPD_PH_TABLE_4)) & 0x1fff0000 ) >> 16)
++#define GET_RG_DPD_110_PH (((REG32(ADR_DPD_PH_TABLE_5)) & 0x00001fff ) >> 0)
++#define GET_RG_DPD_120_PH (((REG32(ADR_DPD_PH_TABLE_5)) & 0x1fff0000 ) >> 16)
++#define GET_RG_DPD_130_PH (((REG32(ADR_DPD_PH_TABLE_6)) & 0x00001fff ) >> 0)
++#define GET_RG_DPD_140_PH (((REG32(ADR_DPD_PH_TABLE_6)) & 0x1fff0000 ) >> 16)
++#define GET_RG_DPD_150_PH (((REG32(ADR_DPD_PH_TABLE_7)) & 0x00001fff ) >> 0)
++#define GET_RG_DPD_160_PH (((REG32(ADR_DPD_PH_TABLE_7)) & 0x1fff0000 ) >> 16)
++#define GET_RG_DPD_170_PH (((REG32(ADR_DPD_PH_TABLE_8)) & 0x00001fff ) >> 0)
++#define GET_RG_DPD_180_PH (((REG32(ADR_DPD_PH_TABLE_8)) & 0x1fff0000 ) >> 16)
++#define GET_RG_DPD_190_PH (((REG32(ADR_DPD_PH_TABLE_9)) & 0x00001fff ) >> 0)
++#define GET_RG_DPD_1A0_PH (((REG32(ADR_DPD_PH_TABLE_9)) & 0x1fff0000 ) >> 16)
++#define GET_RG_DPD_1B0_PH (((REG32(ADR_DPD_PH_TABLE_A)) & 0x00001fff ) >> 0)
++#define GET_RG_DPD_1C0_PH (((REG32(ADR_DPD_PH_TABLE_A)) & 0x1fff0000 ) >> 16)
++#define GET_RG_DPD_1D0_PH (((REG32(ADR_DPD_PH_TABLE_B)) & 0x00001fff ) >> 0)
++#define GET_RG_DPD_1E0_PH (((REG32(ADR_DPD_PH_TABLE_B)) & 0x1fff0000 ) >> 16)
++#define GET_RG_DPD_1F0_PH (((REG32(ADR_DPD_PH_TABLE_C)) & 0x00001fff ) >> 0)
++#define GET_RG_DPD_200_PH (((REG32(ADR_DPD_PH_TABLE_C)) & 0x1fff0000 ) >> 16)
++#define GET_RG_DPD_GAIN_EST_Y0 (((REG32(ADR_DPD_GAIN_ESTIMATION_0)) & 0x000001ff ) >> 0)
++#define GET_RG_DPD_GAIN_EST_Y1 (((REG32(ADR_DPD_GAIN_ESTIMATION_0)) & 0x01ff0000 ) >> 16)
++#define GET_RG_DPD_LOOP_GAIN (((REG32(ADR_DPD_GAIN_ESTIMATION_1)) & 0x000003ff ) >> 0)
++#define GET_RG_DPD_GAIN_EST_X0 (((REG32(ADR_DPD_GAIN_ESTIMATION_2)) & 0x000001ff ) >> 0)
++#define GET_RO_DPD_GAIN (((REG32(ADR_DPD_GAIN_ESTIMATION_2)) & 0x03ff0000 ) >> 16)
++#define GET_TX_SCALE_11B (((REG32(ADR_TX_GAIN_FACTOR)) & 0x000000ff ) >> 0)
++#define GET_TX_SCALE_11B_P0D5 (((REG32(ADR_TX_GAIN_FACTOR)) & 0x0000ff00 ) >> 8)
++#define GET_TX_SCALE_11G (((REG32(ADR_TX_GAIN_FACTOR)) & 0x00ff0000 ) >> 16)
++#define GET_TX_SCALE_11G_P0D5 (((REG32(ADR_TX_GAIN_FACTOR)) & 0xff000000 ) >> 24)
++#define GET_RG_EN_MANUAL (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00000001 ) >> 0)
++#define GET_RG_TX_EN (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00000002 ) >> 1)
++#define GET_RG_TX_PA_EN (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00000004 ) >> 2)
++#define GET_RG_TX_DAC_EN (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00000008 ) >> 3)
++#define GET_RG_RX_AGC (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00000010 ) >> 4)
++#define GET_RG_RX_GAIN_MANUAL (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00000020 ) >> 5)
++#define GET_RG_RFG (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x000000c0 ) >> 6)
++#define GET_RG_PGAG (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00000f00 ) >> 8)
++#define GET_RG_MODE (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00003000 ) >> 12)
++#define GET_RG_EN_TX_TRSW (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00004000 ) >> 14)
++#define GET_RG_EN_SX (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00008000 ) >> 15)
++#define GET_RG_EN_RX_LNA (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00010000 ) >> 16)
++#define GET_RG_EN_RX_MIXER (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00020000 ) >> 17)
++#define GET_RG_EN_RX_DIV2 (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00040000 ) >> 18)
++#define GET_RG_EN_RX_LOBUF (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00080000 ) >> 19)
++#define GET_RG_EN_RX_TZ (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00100000 ) >> 20)
++#define GET_RG_EN_RX_FILTER (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00200000 ) >> 21)
++#define GET_RG_EN_RX_HPF (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00400000 ) >> 22)
++#define GET_RG_EN_RX_RSSI (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00800000 ) >> 23)
++#define GET_RG_EN_ADC (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x01000000 ) >> 24)
++#define GET_RG_EN_TX_MOD (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x02000000 ) >> 25)
++#define GET_RG_EN_TX_DIV2 (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x04000000 ) >> 26)
++#define GET_RG_EN_TX_DIV2_BUF (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x08000000 ) >> 27)
++#define GET_RG_EN_TX_LOBF (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x10000000 ) >> 28)
++#define GET_RG_EN_RX_LOBF (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x20000000 ) >> 29)
++#define GET_RG_SEL_DPLL_CLK (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x40000000 ) >> 30)
++#define GET_RG_EN_CLK_960MBY13_UART (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x80000000 ) >> 31)
++#define GET_RG_EN_TX_DPD (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000001 ) >> 0)
++#define GET_RG_EN_TX_TSSI (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000002 ) >> 1)
++#define GET_RG_EN_RX_IQCAL (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000004 ) >> 2)
++#define GET_RG_EN_TX_DAC_CAL (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000008 ) >> 3)
++#define GET_RG_EN_TX_SELF_MIXER (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000010 ) >> 4)
++#define GET_RG_EN_TX_DAC_OUT (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000020 ) >> 5)
++#define GET_RG_EN_LDO_RX_FE (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000040 ) >> 6)
++#define GET_RG_EN_LDO_ABB (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000080 ) >> 7)
++#define GET_RG_EN_LDO_AFE (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000100 ) >> 8)
++#define GET_RG_EN_SX_CHPLDO (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000200 ) >> 9)
++#define GET_RG_EN_SX_LOBFLDO (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000400 ) >> 10)
++#define GET_RG_EN_IREF_RX (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000800 ) >> 11)
++#define GET_RG_EN_TX_DAC_VOUT (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00002000 ) >> 13)
++#define GET_RG_EN_SX_LCK_BIN (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00004000 ) >> 14)
++#define GET_RG_RTC_CAL_MODE (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00010000 ) >> 16)
++#define GET_RG_EN_IQPAD_IOSW (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00020000 ) >> 17)
++#define GET_RG_EN_TESTPAD_IOSW (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00040000 ) >> 18)
++#define GET_RG_EN_TRXBF_BYPASS (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00080000 ) >> 19)
++#define GET_RG_LDO_LEVEL_RX_FE (((REG32(ADR_LDO_REGISTER)) & 0x00000007 ) >> 0)
++#define GET_RG_LDO_LEVEL_ABB (((REG32(ADR_LDO_REGISTER)) & 0x00000038 ) >> 3)
++#define GET_RG_LDO_LEVEL_AFE (((REG32(ADR_LDO_REGISTER)) & 0x000001c0 ) >> 6)
++#define GET_RG_SX_LDO_CHP_LEVEL (((REG32(ADR_LDO_REGISTER)) & 0x00000e00 ) >> 9)
++#define GET_RG_SX_LDO_LOBF_LEVEL (((REG32(ADR_LDO_REGISTER)) & 0x00007000 ) >> 12)
++#define GET_RG_SX_LDO_XOSC_LEVEL (((REG32(ADR_LDO_REGISTER)) & 0x00038000 ) >> 15)
++#define GET_RG_DP_LDO_LEVEL (((REG32(ADR_LDO_REGISTER)) & 0x001c0000 ) >> 18)
++#define GET_RG_SX_LDO_VCO_LEVEL (((REG32(ADR_LDO_REGISTER)) & 0x00e00000 ) >> 21)
++#define GET_RG_TX_LDO_TX_LEVEL (((REG32(ADR_LDO_REGISTER)) & 0x07000000 ) >> 24)
++#define GET_RG_EN_RX_PADSW (((REG32(ADR_ABB_REGISTER_1)) & 0x00000001 ) >> 0)
++#define GET_RG_EN_RX_TESTNODE (((REG32(ADR_ABB_REGISTER_1)) & 0x00000002 ) >> 1)
++#define GET_RG_RX_ABBCFIX (((REG32(ADR_ABB_REGISTER_1)) & 0x00000004 ) >> 2)
++#define GET_RG_RX_ABBCTUNE (((REG32(ADR_ABB_REGISTER_1)) & 0x000001f8 ) >> 3)
++#define GET_RG_RX_ABBOUT_TRI_STATE (((REG32(ADR_ABB_REGISTER_1)) & 0x00000200 ) >> 9)
++#define GET_RG_RX_ABB_N_MODE (((REG32(ADR_ABB_REGISTER_1)) & 0x00000400 ) >> 10)
++#define GET_RG_RX_EN_LOOPA (((REG32(ADR_ABB_REGISTER_1)) & 0x00000800 ) >> 11)
++#define GET_RG_RX_FILTERI1ST (((REG32(ADR_ABB_REGISTER_1)) & 0x00003000 ) >> 12)
++#define GET_RG_RX_FILTERI2ND (((REG32(ADR_ABB_REGISTER_1)) & 0x0000c000 ) >> 14)
++#define GET_RG_RX_FILTERI3RD (((REG32(ADR_ABB_REGISTER_1)) & 0x00030000 ) >> 16)
++#define GET_RG_RX_FILTERI_COURSE (((REG32(ADR_ABB_REGISTER_1)) & 0x000c0000 ) >> 18)
++#define GET_RG_RX_FILTERVCM (((REG32(ADR_ABB_REGISTER_1)) & 0x00300000 ) >> 20)
++#define GET_RG_RX_HPF3M (((REG32(ADR_ABB_REGISTER_1)) & 0x00400000 ) >> 22)
++#define GET_RG_RX_HPF300K (((REG32(ADR_ABB_REGISTER_1)) & 0x00800000 ) >> 23)
++#define GET_RG_RX_HPFI (((REG32(ADR_ABB_REGISTER_1)) & 0x03000000 ) >> 24)
++#define GET_RG_RX_HPF_FINALCORNER (((REG32(ADR_ABB_REGISTER_1)) & 0x0c000000 ) >> 26)
++#define GET_RG_RX_HPF_SETTLE1_C (((REG32(ADR_ABB_REGISTER_1)) & 0x30000000 ) >> 28)
++#define GET_RG_RX_HPF_SETTLE1_R (((REG32(ADR_ABB_REGISTER_2)) & 0x00000003 ) >> 0)
++#define GET_RG_RX_HPF_SETTLE2_C (((REG32(ADR_ABB_REGISTER_2)) & 0x0000000c ) >> 2)
++#define GET_RG_RX_HPF_SETTLE2_R (((REG32(ADR_ABB_REGISTER_2)) & 0x00000030 ) >> 4)
++#define GET_RG_RX_HPF_VCMCON2 (((REG32(ADR_ABB_REGISTER_2)) & 0x000000c0 ) >> 6)
++#define GET_RG_RX_HPF_VCMCON (((REG32(ADR_ABB_REGISTER_2)) & 0x00000300 ) >> 8)
++#define GET_RG_RX_OUTVCM (((REG32(ADR_ABB_REGISTER_2)) & 0x00000c00 ) >> 10)
++#define GET_RG_RX_TZI (((REG32(ADR_ABB_REGISTER_2)) & 0x00003000 ) >> 12)
++#define GET_RG_RX_TZ_OUT_TRISTATE (((REG32(ADR_ABB_REGISTER_2)) & 0x00004000 ) >> 14)
++#define GET_RG_RX_TZ_VCM (((REG32(ADR_ABB_REGISTER_2)) & 0x00018000 ) >> 15)
++#define GET_RG_EN_RX_RSSI_TESTNODE (((REG32(ADR_ABB_REGISTER_2)) & 0x000e0000 ) >> 17)
++#define GET_RG_RX_ADCRSSI_CLKSEL (((REG32(ADR_ABB_REGISTER_2)) & 0x00100000 ) >> 20)
++#define GET_RG_RX_ADCRSSI_VCM (((REG32(ADR_ABB_REGISTER_2)) & 0x00600000 ) >> 21)
++#define GET_RG_RX_REC_LPFCORNER (((REG32(ADR_ABB_REGISTER_2)) & 0x01800000 ) >> 23)
++#define GET_RG_RSSI_CLOCK_GATING (((REG32(ADR_ABB_REGISTER_2)) & 0x02000000 ) >> 25)
++#define GET_RG_TXPGA_CAPSW (((REG32(ADR_TX_FE_REGISTER)) & 0x00000003 ) >> 0)
++#define GET_RG_TXPGA_MAIN (((REG32(ADR_TX_FE_REGISTER)) & 0x000000fc ) >> 2)
++#define GET_RG_TXPGA_STEER (((REG32(ADR_TX_FE_REGISTER)) & 0x00003f00 ) >> 8)
++#define GET_RG_TXMOD_GMCELL (((REG32(ADR_TX_FE_REGISTER)) & 0x0000c000 ) >> 14)
++#define GET_RG_TXLPF_GMCELL (((REG32(ADR_TX_FE_REGISTER)) & 0x00030000 ) >> 16)
++#define GET_RG_PACELL_EN (((REG32(ADR_TX_FE_REGISTER)) & 0x001c0000 ) >> 18)
++#define GET_RG_PABIAS_CTRL (((REG32(ADR_TX_FE_REGISTER)) & 0x01e00000 ) >> 21)
++#define GET_RG_TX_DIV_VSET (((REG32(ADR_TX_FE_REGISTER)) & 0x0c000000 ) >> 26)
++#define GET_RG_TX_LOBUF_VSET (((REG32(ADR_TX_FE_REGISTER)) & 0x30000000 ) >> 28)
++#define GET_RG_RX_SQDC (((REG32(ADR_RX_FE_REGISTER_1)) & 0x00000007 ) >> 0)
++#define GET_RG_RX_DIV2_CORE (((REG32(ADR_RX_FE_REGISTER_1)) & 0x00000018 ) >> 3)
++#define GET_RG_RX_LOBUF (((REG32(ADR_RX_FE_REGISTER_1)) & 0x00000060 ) >> 5)
++#define GET_RG_TX_DPDGM_BIAS (((REG32(ADR_RX_FE_REGISTER_1)) & 0x00000780 ) >> 7)
++#define GET_RG_TX_DPD_DIV (((REG32(ADR_RX_FE_REGISTER_1)) & 0x00007800 ) >> 11)
++#define GET_RG_TX_TSSI_BIAS (((REG32(ADR_RX_FE_REGISTER_1)) & 0x00038000 ) >> 15)
++#define GET_RG_TX_TSSI_DIV (((REG32(ADR_RX_FE_REGISTER_1)) & 0x001c0000 ) >> 18)
++#define GET_RG_TX_TSSI_TESTMODE (((REG32(ADR_RX_FE_REGISTER_1)) & 0x00200000 ) >> 21)
++#define GET_RG_TX_TSSI_TEST (((REG32(ADR_RX_FE_REGISTER_1)) & 0x00c00000 ) >> 22)
++#define GET_RG_PACASCODE_CTRL (((REG32(ADR_RX_FE_REGISTER_1)) & 0x07000000 ) >> 24)
++#define GET_RG_RX_HG_LNA_GC (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x00000003 ) >> 0)
++#define GET_RG_RX_HG_LNAHGN_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x0000003c ) >> 2)
++#define GET_RG_RX_HG_LNAHGP_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x000003c0 ) >> 6)
++#define GET_RG_RX_HG_LNALG_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x00003c00 ) >> 10)
++#define GET_RG_RX_HG_TZ_GC (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x0000c000 ) >> 14)
++#define GET_RG_RX_HG_TZ_CAP (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x00070000 ) >> 16)
++#define GET_RG_RX_MG_LNA_GC (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x00000003 ) >> 0)
++#define GET_RG_RX_MG_LNAHGN_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x0000003c ) >> 2)
++#define GET_RG_RX_MG_LNAHGP_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x000003c0 ) >> 6)
++#define GET_RG_RX_MG_LNALG_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x00003c00 ) >> 10)
++#define GET_RG_RX_MG_TZ_GC (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x0000c000 ) >> 14)
++#define GET_RG_RX_MG_TZ_CAP (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x00070000 ) >> 16)
++#define GET_RG_RX_LG_LNA_GC (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x00000003 ) >> 0)
++#define GET_RG_RX_LG_LNAHGN_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x0000003c ) >> 2)
++#define GET_RG_RX_LG_LNAHGP_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x000003c0 ) >> 6)
++#define GET_RG_RX_LG_LNALG_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x00003c00 ) >> 10)
++#define GET_RG_RX_LG_TZ_GC (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x0000c000 ) >> 14)
++#define GET_RG_RX_LG_TZ_CAP (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x00070000 ) >> 16)
++#define GET_RG_RX_ULG_LNA_GC (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x00000003 ) >> 0)
++#define GET_RG_RX_ULG_LNAHGN_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x0000003c ) >> 2)
++#define GET_RG_RX_ULG_LNAHGP_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x000003c0 ) >> 6)
++#define GET_RG_RX_ULG_LNALG_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x00003c00 ) >> 10)
++#define GET_RG_RX_ULG_TZ_GC (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x0000c000 ) >> 14)
++#define GET_RG_RX_ULG_TZ_CAP (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x00070000 ) >> 16)
++#define GET_RG_HPF1_FAST_SET_X (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00000001 ) >> 0)
++#define GET_RG_HPF1_FAST_SET_Y (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00000002 ) >> 1)
++#define GET_RG_HPF1_FAST_SET_Z (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00000004 ) >> 2)
++#define GET_RG_HPF_T1A (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00000018 ) >> 3)
++#define GET_RG_HPF_T1B (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00000060 ) >> 5)
++#define GET_RG_HPF_T1C (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00000180 ) >> 7)
++#define GET_RG_RX_LNA_TRI_SEL (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00000600 ) >> 9)
++#define GET_RG_RX_LNA_SETTLE (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00001800 ) >> 11)
++#define GET_RG_TXGAIN_PHYCTRL (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00002000 ) >> 13)
++#define GET_RG_TX_GAIN (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x003fc000 ) >> 14)
++#define GET_RG_TXGAIN_MANUAL (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00400000 ) >> 22)
++#define GET_RG_TX_GAIN_OFFSET (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x07800000 ) >> 23)
++#define GET_RG_ADC_CLKSEL (((REG32(ADR_RX_ADC_REGISTER)) & 0x00000001 ) >> 0)
++#define GET_RG_ADC_DIBIAS (((REG32(ADR_RX_ADC_REGISTER)) & 0x00000006 ) >> 1)
++#define GET_RG_ADC_DIVR (((REG32(ADR_RX_ADC_REGISTER)) & 0x00000008 ) >> 3)
++#define GET_RG_ADC_DVCMI (((REG32(ADR_RX_ADC_REGISTER)) & 0x00000030 ) >> 4)
++#define GET_RG_ADC_SAMSEL (((REG32(ADR_RX_ADC_REGISTER)) & 0x000003c0 ) >> 6)
++#define GET_RG_ADC_STNBY (((REG32(ADR_RX_ADC_REGISTER)) & 0x00000400 ) >> 10)
++#define GET_RG_ADC_TESTMODE (((REG32(ADR_RX_ADC_REGISTER)) & 0x00000800 ) >> 11)
++#define GET_RG_ADC_TSEL (((REG32(ADR_RX_ADC_REGISTER)) & 0x0000f000 ) >> 12)
++#define GET_RG_ADC_VRSEL (((REG32(ADR_RX_ADC_REGISTER)) & 0x00030000 ) >> 16)
++#define GET_RG_DICMP (((REG32(ADR_RX_ADC_REGISTER)) & 0x000c0000 ) >> 18)
++#define GET_RG_DIOP (((REG32(ADR_RX_ADC_REGISTER)) & 0x00300000 ) >> 20)
++#define GET_RG_SARADC_VRSEL (((REG32(ADR_RX_ADC_REGISTER)) & 0x00c00000 ) >> 22)
++#define GET_RG_EN_SAR_TEST (((REG32(ADR_RX_ADC_REGISTER)) & 0x03000000 ) >> 24)
++#define GET_RG_SARADC_THERMAL (((REG32(ADR_RX_ADC_REGISTER)) & 0x04000000 ) >> 26)
++#define GET_RG_SARADC_TSSI (((REG32(ADR_RX_ADC_REGISTER)) & 0x08000000 ) >> 27)
++#define GET_RG_CLK_SAR_SEL (((REG32(ADR_RX_ADC_REGISTER)) & 0x30000000 ) >> 28)
++#define GET_RG_EN_SARADC (((REG32(ADR_RX_ADC_REGISTER)) & 0x40000000 ) >> 30)
++#define GET_RG_DACI1ST (((REG32(ADR_TX_DAC_REGISTER)) & 0x00000003 ) >> 0)
++#define GET_RG_TX_DACLPF_ICOURSE (((REG32(ADR_TX_DAC_REGISTER)) & 0x0000000c ) >> 2)
++#define GET_RG_TX_DACLPF_IFINE (((REG32(ADR_TX_DAC_REGISTER)) & 0x00000030 ) >> 4)
++#define GET_RG_TX_DACLPF_VCM (((REG32(ADR_TX_DAC_REGISTER)) & 0x000000c0 ) >> 6)
++#define GET_RG_TX_DAC_CKEDGE_SEL (((REG32(ADR_TX_DAC_REGISTER)) & 0x00000100 ) >> 8)
++#define GET_RG_TX_DAC_IBIAS (((REG32(ADR_TX_DAC_REGISTER)) & 0x00000600 ) >> 9)
++#define GET_RG_TX_DAC_OS (((REG32(ADR_TX_DAC_REGISTER)) & 0x00003800 ) >> 11)
++#define GET_RG_TX_DAC_RCAL (((REG32(ADR_TX_DAC_REGISTER)) & 0x0000c000 ) >> 14)
++#define GET_RG_TX_DAC_TSEL (((REG32(ADR_TX_DAC_REGISTER)) & 0x000f0000 ) >> 16)
++#define GET_RG_TX_EN_VOLTAGE_IN (((REG32(ADR_TX_DAC_REGISTER)) & 0x00100000 ) >> 20)
++#define GET_RG_TXLPF_BYPASS (((REG32(ADR_TX_DAC_REGISTER)) & 0x00200000 ) >> 21)
++#define GET_RG_TXLPF_BOOSTI (((REG32(ADR_TX_DAC_REGISTER)) & 0x00400000 ) >> 22)
++#define GET_RG_TX_DAC_IOFFSET (((REG32(ADR_TX_DAC_REGISTER)) & 0x07800000 ) >> 23)
++#define GET_RG_TX_DAC_QOFFSET (((REG32(ADR_TX_DAC_REGISTER)) & 0x78000000 ) >> 27)
++#define GET_RG_EN_SX_R3 (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00000001 ) >> 0)
++#define GET_RG_EN_SX_CH (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00000002 ) >> 1)
++#define GET_RG_EN_SX_CHP (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00000004 ) >> 2)
++#define GET_RG_EN_SX_DIVCK (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00000008 ) >> 3)
++#define GET_RG_EN_SX_VCOBF (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00000010 ) >> 4)
++#define GET_RG_EN_SX_VCO (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00000020 ) >> 5)
++#define GET_RG_EN_SX_MOD (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00000040 ) >> 6)
++#define GET_RG_EN_SX_DITHER (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00000100 ) >> 8)
++#define GET_RG_EN_SX_VT_MON (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00000800 ) >> 11)
++#define GET_RG_EN_SX_VT_MON_DG (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00001000 ) >> 12)
++#define GET_RG_EN_SX_DIV (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00002000 ) >> 13)
++#define GET_RG_EN_SX_LPF (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00004000 ) >> 14)
++#define GET_RG_EN_DPL_MOD (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00008000 ) >> 15)
++#define GET_RG_DPL_MOD_ORDER (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00030000 ) >> 16)
++#define GET_RG_SX_RFCTRL_F (((REG32(ADR_SYN_REGISTER_1)) & 0x00ffffff ) >> 0)
++#define GET_RG_SX_SEL_CP (((REG32(ADR_SYN_REGISTER_1)) & 0x0f000000 ) >> 24)
++#define GET_RG_SX_SEL_CS (((REG32(ADR_SYN_REGISTER_1)) & 0xf0000000 ) >> 28)
++#define GET_RG_SX_RFCTRL_CH (((REG32(ADR_SYN_REGISTER_2)) & 0x000007ff ) >> 0)
++#define GET_RG_SX_SEL_C3 (((REG32(ADR_SYN_REGISTER_2)) & 0x00007800 ) >> 11)
++#define GET_RG_SX_SEL_RS (((REG32(ADR_SYN_REGISTER_2)) & 0x000f8000 ) >> 15)
++#define GET_RG_SX_SEL_R3 (((REG32(ADR_SYN_REGISTER_2)) & 0x01f00000 ) >> 20)
++#define GET_RG_SX_SEL_ICHP (((REG32(ADR_SYN_PFD_CHP)) & 0x0000001f ) >> 0)
++#define GET_RG_SX_SEL_PCHP (((REG32(ADR_SYN_PFD_CHP)) & 0x000003e0 ) >> 5)
++#define GET_RG_SX_SEL_CHP_REGOP (((REG32(ADR_SYN_PFD_CHP)) & 0x00003c00 ) >> 10)
++#define GET_RG_SX_SEL_CHP_UNIOP (((REG32(ADR_SYN_PFD_CHP)) & 0x0003c000 ) >> 14)
++#define GET_RG_SX_CHP_IOST_POL (((REG32(ADR_SYN_PFD_CHP)) & 0x00040000 ) >> 18)
++#define GET_RG_SX_CHP_IOST (((REG32(ADR_SYN_PFD_CHP)) & 0x00380000 ) >> 19)
++#define GET_RG_SX_PFDSEL (((REG32(ADR_SYN_PFD_CHP)) & 0x00400000 ) >> 22)
++#define GET_RG_SX_PFD_SET (((REG32(ADR_SYN_PFD_CHP)) & 0x00800000 ) >> 23)
++#define GET_RG_SX_PFD_SET1 (((REG32(ADR_SYN_PFD_CHP)) & 0x01000000 ) >> 24)
++#define GET_RG_SX_PFD_SET2 (((REG32(ADR_SYN_PFD_CHP)) & 0x02000000 ) >> 25)
++#define GET_RG_SX_VBNCAS_SEL (((REG32(ADR_SYN_PFD_CHP)) & 0x04000000 ) >> 26)
++#define GET_RG_SX_PFD_RST_H (((REG32(ADR_SYN_PFD_CHP)) & 0x08000000 ) >> 27)
++#define GET_RG_SX_PFD_TRUP (((REG32(ADR_SYN_PFD_CHP)) & 0x10000000 ) >> 28)
++#define GET_RG_SX_PFD_TRDN (((REG32(ADR_SYN_PFD_CHP)) & 0x20000000 ) >> 29)
++#define GET_RG_SX_PFD_TRSEL (((REG32(ADR_SYN_PFD_CHP)) & 0x40000000 ) >> 30)
++#define GET_RG_SX_VCOBA_R (((REG32(ADR_SYN_VCO_LOBF)) & 0x00000007 ) >> 0)
++#define GET_RG_SX_VCORSEL (((REG32(ADR_SYN_VCO_LOBF)) & 0x000000f8 ) >> 3)
++#define GET_RG_SX_VCOCUSEL (((REG32(ADR_SYN_VCO_LOBF)) & 0x00000f00 ) >> 8)
++#define GET_RG_SX_RXBFSEL (((REG32(ADR_SYN_VCO_LOBF)) & 0x0000f000 ) >> 12)
++#define GET_RG_SX_TXBFSEL (((REG32(ADR_SYN_VCO_LOBF)) & 0x000f0000 ) >> 16)
++#define GET_RG_SX_VCOBFSEL (((REG32(ADR_SYN_VCO_LOBF)) & 0x00f00000 ) >> 20)
++#define GET_RG_SX_DIVBFSEL (((REG32(ADR_SYN_VCO_LOBF)) & 0x0f000000 ) >> 24)
++#define GET_RG_SX_GNDR_SEL (((REG32(ADR_SYN_VCO_LOBF)) & 0xf0000000 ) >> 28)
++#define GET_RG_SX_DITHER_WEIGHT (((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0x00000003 ) >> 0)
++#define GET_RG_SX_MOD_ORDER (((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0x00000030 ) >> 4)
++#define GET_RG_SX_RST_H_DIV (((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0x00000200 ) >> 9)
++#define GET_RG_SX_SDM_EDGE (((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0x00000400 ) >> 10)
++#define GET_RG_SX_XO_GM (((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0x00001800 ) >> 11)
++#define GET_RG_SX_REFBYTWO (((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0x00002000 ) >> 13)
++#define GET_RG_SX_LCKEN (((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0x00080000 ) >> 19)
++#define GET_RG_SX_PREVDD (((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0x00f00000 ) >> 20)
++#define GET_RG_SX_PSCONTERVDD (((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0x0f000000 ) >> 24)
++#define GET_RG_SX_PH (((REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) & 0x00002000 ) >> 13)
++#define GET_RG_SX_PL (((REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) & 0x00004000 ) >> 14)
++#define GET_RG_XOSC_CBANK_XO (((REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) & 0x00078000 ) >> 15)
++#define GET_RG_XOSC_CBANK_XI (((REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) & 0x00780000 ) >> 19)
++#define GET_RG_SX_VT_MON_MODE (((REG32(ADR_SYN_LCK_VT)) & 0x00000001 ) >> 0)
++#define GET_RG_SX_VT_TH_HI (((REG32(ADR_SYN_LCK_VT)) & 0x00000006 ) >> 1)
++#define GET_RG_SX_VT_TH_LO (((REG32(ADR_SYN_LCK_VT)) & 0x00000018 ) >> 3)
++#define GET_RG_SX_VT_SET (((REG32(ADR_SYN_LCK_VT)) & 0x00000020 ) >> 5)
++#define GET_RG_SX_VT_MON_TMR (((REG32(ADR_SYN_LCK_VT)) & 0x00007fc0 ) >> 6)
++#define GET_RG_EN_DP_VT_MON (((REG32(ADR_DPLL_VCO_REGISTER)) & 0x00000001 ) >> 0)
++#define GET_RG_DP_VT_TH_HI (((REG32(ADR_DPLL_VCO_REGISTER)) & 0x00000006 ) >> 1)
++#define GET_RG_DP_VT_TH_LO (((REG32(ADR_DPLL_VCO_REGISTER)) & 0x00000018 ) >> 3)
++#define GET_RG_DP_CK320BY2 (((REG32(ADR_DPLL_VCO_REGISTER)) & 0x00004000 ) >> 14)
++#define GET_RG_DP_OD_TEST (((REG32(ADR_DPLL_VCO_REGISTER)) & 0x00200000 ) >> 21)
++#define GET_RG_DP_BBPLL_BP (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x00000001 ) >> 0)
++#define GET_RG_DP_BBPLL_ICP (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x00000006 ) >> 1)
++#define GET_RG_DP_BBPLL_IDUAL (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x00000018 ) >> 3)
++#define GET_RG_DP_BBPLL_OD_TEST (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x000001e0 ) >> 5)
++#define GET_RG_DP_BBPLL_PD (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x00000200 ) >> 9)
++#define GET_RG_DP_BBPLL_TESTSEL (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x00001c00 ) >> 10)
++#define GET_RG_DP_BBPLL_PFD_DLY (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x00006000 ) >> 13)
++#define GET_RG_DP_RP (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x00038000 ) >> 15)
++#define GET_RG_DP_RHP (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x000c0000 ) >> 18)
++#define GET_RG_DP_BBPLL_SDM_EDGE (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x80000000 ) >> 31)
++#define GET_RG_DP_FODIV (((REG32(ADR_DPLL_DIVIDER_REGISTER)) & 0x0007f000 ) >> 12)
++#define GET_RG_DP_REFDIV (((REG32(ADR_DPLL_DIVIDER_REGISTER)) & 0x1fc00000 ) >> 22)
++#define GET_RG_IDACAI_PGAG15 (((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0x0000003f ) >> 0)
++#define GET_RG_IDACAQ_PGAG15 (((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0x00000fc0 ) >> 6)
++#define GET_RG_IDACAI_PGAG14 (((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0x0003f000 ) >> 12)
++#define GET_RG_IDACAQ_PGAG14 (((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0x00fc0000 ) >> 18)
++#define GET_RG_DP_BBPLL_BS (((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0x3f000000 ) >> 24)
++#define GET_RG_IDACAI_PGAG13 (((REG32(ADR_DCOC_IDAC_REGISTER2)) & 0x0000003f ) >> 0)
++#define GET_RG_IDACAQ_PGAG13 (((REG32(ADR_DCOC_IDAC_REGISTER2)) & 0x00000fc0 ) >> 6)
++#define GET_RG_IDACAI_PGAG12 (((REG32(ADR_DCOC_IDAC_REGISTER2)) & 0x0003f000 ) >> 12)
++#define GET_RG_IDACAQ_PGAG12 (((REG32(ADR_DCOC_IDAC_REGISTER2)) & 0x00fc0000 ) >> 18)
++#define GET_RG_IDACAI_PGAG11 (((REG32(ADR_DCOC_IDAC_REGISTER3)) & 0x0000003f ) >> 0)
++#define GET_RG_IDACAQ_PGAG11 (((REG32(ADR_DCOC_IDAC_REGISTER3)) & 0x00000fc0 ) >> 6)
++#define GET_RG_IDACAI_PGAG10 (((REG32(ADR_DCOC_IDAC_REGISTER3)) & 0x0003f000 ) >> 12)
++#define GET_RG_IDACAQ_PGAG10 (((REG32(ADR_DCOC_IDAC_REGISTER3)) & 0x00fc0000 ) >> 18)
++#define GET_RG_IDACAI_PGAG9 (((REG32(ADR_DCOC_IDAC_REGISTER4)) & 0x0000003f ) >> 0)
++#define GET_RG_IDACAQ_PGAG9 (((REG32(ADR_DCOC_IDAC_REGISTER4)) & 0x00000fc0 ) >> 6)
++#define GET_RG_IDACAI_PGAG8 (((REG32(ADR_DCOC_IDAC_REGISTER4)) & 0x0003f000 ) >> 12)
++#define GET_RG_IDACAQ_PGAG8 (((REG32(ADR_DCOC_IDAC_REGISTER4)) & 0x00fc0000 ) >> 18)
++#define GET_RG_IDACAI_PGAG7 (((REG32(ADR_DCOC_IDAC_REGISTER5)) & 0x0000003f ) >> 0)
++#define GET_RG_IDACAQ_PGAG7 (((REG32(ADR_DCOC_IDAC_REGISTER5)) & 0x00000fc0 ) >> 6)
++#define GET_RG_IDACAI_PGAG6 (((REG32(ADR_DCOC_IDAC_REGISTER5)) & 0x0003f000 ) >> 12)
++#define GET_RG_IDACAQ_PGAG6 (((REG32(ADR_DCOC_IDAC_REGISTER5)) & 0x00fc0000 ) >> 18)
++#define GET_RG_IDACAI_PGAG5 (((REG32(ADR_DCOC_IDAC_REGISTER6)) & 0x0000003f ) >> 0)
++#define GET_RG_IDACAQ_PGAG5 (((REG32(ADR_DCOC_IDAC_REGISTER6)) & 0x00000fc0 ) >> 6)
++#define GET_RG_IDACAI_PGAG4 (((REG32(ADR_DCOC_IDAC_REGISTER6)) & 0x0003f000 ) >> 12)
++#define GET_RG_IDACAQ_PGAG4 (((REG32(ADR_DCOC_IDAC_REGISTER6)) & 0x00fc0000 ) >> 18)
++#define GET_RG_IDACAI_PGAG3 (((REG32(ADR_DCOC_IDAC_REGISTER7)) & 0x0000003f ) >> 0)
++#define GET_RG_IDACAQ_PGAG3 (((REG32(ADR_DCOC_IDAC_REGISTER7)) & 0x00000fc0 ) >> 6)
++#define GET_RG_IDACAI_PGAG2 (((REG32(ADR_DCOC_IDAC_REGISTER7)) & 0x0003f000 ) >> 12)
++#define GET_RG_IDACAQ_PGAG2 (((REG32(ADR_DCOC_IDAC_REGISTER7)) & 0x00fc0000 ) >> 18)
++#define GET_RG_IDACAI_PGAG1 (((REG32(ADR_DCOC_IDAC_REGISTER8)) & 0x0000003f ) >> 0)
++#define GET_RG_IDACAQ_PGAG1 (((REG32(ADR_DCOC_IDAC_REGISTER8)) & 0x00000fc0 ) >> 6)
++#define GET_RG_IDACAI_PGAG0 (((REG32(ADR_DCOC_IDAC_REGISTER8)) & 0x0003f000 ) >> 12)
++#define GET_RG_IDACAQ_PGAG0 (((REG32(ADR_DCOC_IDAC_REGISTER8)) & 0x00fc0000 ) >> 18)
++#define GET_RG_EN_RCAL (((REG32(ADR_RCAL_REGISTER)) & 0x00000001 ) >> 0)
++#define GET_RG_RCAL_SPD (((REG32(ADR_RCAL_REGISTER)) & 0x00000002 ) >> 1)
++#define GET_RG_RCAL_TMR (((REG32(ADR_RCAL_REGISTER)) & 0x000001fc ) >> 2)
++#define GET_RG_RCAL_CODE_CWR (((REG32(ADR_RCAL_REGISTER)) & 0x00000200 ) >> 9)
++#define GET_RG_RCAL_CODE_CWD (((REG32(ADR_RCAL_REGISTER)) & 0x00007c00 ) >> 10)
++#define GET_RG_SX_SUB_SEL_CWR (((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0x00000001 ) >> 0)
++#define GET_RG_SX_SUB_SEL_CWD (((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0x000000fe ) >> 1)
++#define GET_RG_SX_LCK_BIN_OFFSET (((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0x00078000 ) >> 15)
++#define GET_RG_SX_LCK_BIN_PRECISION (((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0x00080000 ) >> 19)
++#define GET_RG_SX_LOCK_EN_N (((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0x00100000 ) >> 20)
++#define GET_RG_SX_LOCK_MANUAL (((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0x00200000 ) >> 21)
++#define GET_RG_SX_SUB_MANUAL (((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0x00400000 ) >> 22)
++#define GET_RG_SX_SUB_SEL (((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0x3f800000 ) >> 23)
++#define GET_RG_SX_MUX_SEL_VTH_BINL (((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0x40000000 ) >> 30)
++#define GET_RG_TRX_DUMMMY (((REG32(ADR_TRX_DUMMY_REGISTER)) & 0xffffffff ) >> 0)
++#define GET_RG_SX_DUMMMY (((REG32(ADR_SX_DUMMY_REGISTER)) & 0xffffffff ) >> 0)
++#define GET_RCAL_RDY (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x00000001 ) >> 0)
++#define GET_LCK_BIN_RDY (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x00000002 ) >> 1)
++#define GET_VT_MON_RDY (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x00000004 ) >> 2)
++#define GET_DA_R_CODE_LUT (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x000007c0 ) >> 6)
++#define GET_AD_SX_VT_MON_Q (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x00001800 ) >> 11)
++#define GET_AD_DP_VT_MON_Q (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x00006000 ) >> 13)
++#define GET_RTC_CAL_RDY (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x00008000 ) >> 15)
++#define GET_RG_SARADC_BIT (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x003f0000 ) >> 16)
++#define GET_SAR_ADC_FSM_RDY (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x00400000 ) >> 22)
++#define GET_AD_CIRCUIT_VERSION (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x07800000 ) >> 23)
++#define GET_DA_R_CAL_CODE (((REG32(ADR_READ_ONLY_FLAGS_2)) & 0x0000001f ) >> 0)
++#define GET_DA_SX_SUB_SEL (((REG32(ADR_READ_ONLY_FLAGS_2)) & 0x00000fe0 ) >> 5)
++#define GET_RG_DPL_RFCTRL_CH (((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) & 0x000007ff ) >> 0)
++#define GET_RG_RSSIADC_RO_BIT (((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) & 0x00007800 ) >> 11)
++#define GET_RG_RX_ADC_I_RO_BIT (((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) & 0x007f8000 ) >> 15)
++#define GET_RG_RX_ADC_Q_RO_BIT (((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) & 0x7f800000 ) >> 23)
++#define GET_RG_DPL_RFCTRL_F (((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_II)) & 0x00ffffff ) >> 0)
++#define GET_RG_SX_TARGET_CNT (((REG32(ADR_SX_LCK_BIN_REGISTERS_II)) & 0x00001fff ) >> 0)
++#define GET_RG_RTC_OFFSET (((REG32(ADR_RC_OSC_32K_CAL_REGISTERS)) & 0x000000ff ) >> 0)
++#define GET_RG_RTC_CAL_TARGET_COUNT (((REG32(ADR_RC_OSC_32K_CAL_REGISTERS)) & 0x000fff00 ) >> 8)
++#define GET_RG_RF_D_REG (((REG32(ADR_RF_D_DIGITAL_DEBUG_PORT_REGISTER)) & 0x0000ffff ) >> 0)
++#define GET_DIRECT_MODE (((REG32(ADR_MMU_CTRL)) & 0x00000001 ) >> 0)
++#define GET_TAG_INTERLEAVE_MD (((REG32(ADR_MMU_CTRL)) & 0x00000002 ) >> 1)
++#define GET_DIS_DEMAND (((REG32(ADR_MMU_CTRL)) & 0x00000004 ) >> 2)
++#define GET_SAME_ID_ALLOC_MD (((REG32(ADR_MMU_CTRL)) & 0x00000008 ) >> 3)
++#define GET_HS_ACCESS_MD (((REG32(ADR_MMU_CTRL)) & 0x00000010 ) >> 4)
++#define GET_SRAM_ACCESS_MD (((REG32(ADR_MMU_CTRL)) & 0x00000020 ) >> 5)
++#define GET_NOHIT_RPASS_MD (((REG32(ADR_MMU_CTRL)) & 0x00000040 ) >> 6)
++#define GET_DMN_FLAG_CLR (((REG32(ADR_MMU_CTRL)) & 0x00000080 ) >> 7)
++#define GET_ERR_SW_RST_N (((REG32(ADR_MMU_CTRL)) & 0x00000100 ) >> 8)
++#define GET_ALR_SW_RST_N (((REG32(ADR_MMU_CTRL)) & 0x00000200 ) >> 9)
++#define GET_MCH_SW_RST_N (((REG32(ADR_MMU_CTRL)) & 0x00000400 ) >> 10)
++#define GET_TAG_SW_RST_N (((REG32(ADR_MMU_CTRL)) & 0x00000800 ) >> 11)
++#define GET_ABT_SW_RST_N (((REG32(ADR_MMU_CTRL)) & 0x00001000 ) >> 12)
++#define GET_MMU_VER (((REG32(ADR_MMU_CTRL)) & 0x0000e000 ) >> 13)
++#define GET_MMU_SHARE_MCU (((REG32(ADR_MMU_CTRL)) & 0x00ff0000 ) >> 16)
++#define GET_HS_WR (((REG32(ADR_HS_CTRL)) & 0x00000001 ) >> 0)
++#define GET_HS_FLAG (((REG32(ADR_HS_CTRL)) & 0x00000010 ) >> 4)
++#define GET_HS_ID (((REG32(ADR_HS_CTRL)) & 0x00007f00 ) >> 8)
++#define GET_HS_CHANNEL (((REG32(ADR_HS_CTRL)) & 0x000f0000 ) >> 16)
++#define GET_HS_PAGE (((REG32(ADR_HS_CTRL)) & 0x00f00000 ) >> 20)
++#define GET_HS_DATA (((REG32(ADR_HS_CTRL)) & 0xff000000 ) >> 24)
++#define GET_CPU_POR0 (((REG32(ADR_CPU_POR0_7)) & 0x0000000f ) >> 0)
++#define GET_CPU_POR1 (((REG32(ADR_CPU_POR0_7)) & 0x000000f0 ) >> 4)
++#define GET_CPU_POR2 (((REG32(ADR_CPU_POR0_7)) & 0x00000f00 ) >> 8)
++#define GET_CPU_POR3 (((REG32(ADR_CPU_POR0_7)) & 0x0000f000 ) >> 12)
++#define GET_CPU_POR4 (((REG32(ADR_CPU_POR0_7)) & 0x000f0000 ) >> 16)
++#define GET_CPU_POR5 (((REG32(ADR_CPU_POR0_7)) & 0x00f00000 ) >> 20)
++#define GET_CPU_POR6 (((REG32(ADR_CPU_POR0_7)) & 0x0f000000 ) >> 24)
++#define GET_CPU_POR7 (((REG32(ADR_CPU_POR0_7)) & 0xf0000000 ) >> 28)
++#define GET_CPU_POR8 (((REG32(ADR_CPU_POR8_F)) & 0x0000000f ) >> 0)
++#define GET_CPU_POR9 (((REG32(ADR_CPU_POR8_F)) & 0x000000f0 ) >> 4)
++#define GET_CPU_PORA (((REG32(ADR_CPU_POR8_F)) & 0x00000f00 ) >> 8)
++#define GET_CPU_PORB (((REG32(ADR_CPU_POR8_F)) & 0x0000f000 ) >> 12)
++#define GET_CPU_PORC (((REG32(ADR_CPU_POR8_F)) & 0x000f0000 ) >> 16)
++#define GET_CPU_PORD (((REG32(ADR_CPU_POR8_F)) & 0x00f00000 ) >> 20)
++#define GET_CPU_PORE (((REG32(ADR_CPU_POR8_F)) & 0x0f000000 ) >> 24)
++#define GET_CPU_PORF (((REG32(ADR_CPU_POR8_F)) & 0xf0000000 ) >> 28)
++#define GET_ACC_WR_LEN (((REG32(ADR_REG_LEN_CTRL)) & 0x0000003f ) >> 0)
++#define GET_ACC_RD_LEN (((REG32(ADR_REG_LEN_CTRL)) & 0x00003f00 ) >> 8)
++#define GET_REQ_NACK_CLR (((REG32(ADR_REG_LEN_CTRL)) & 0x00008000 ) >> 15)
++#define GET_NACK_FLAG_BUS (((REG32(ADR_REG_LEN_CTRL)) & 0xffff0000 ) >> 16)
++#define GET_DMN_R_PASS (((REG32(ADR_DMN_READ_BYPASS)) & 0x0000ffff ) >> 0)
++#define GET_PARA_ALC_RLS (((REG32(ADR_DMN_READ_BYPASS)) & 0x00010000 ) >> 16)
++#define GET_REQ_PORNS_CHGEN (((REG32(ADR_DMN_READ_BYPASS)) & 0x01000000 ) >> 24)
++#define GET_ALC_ABT_ID (((REG32(ADR_ALC_RLS_ABORT)) & 0x0000007f ) >> 0)
++#define GET_ALC_ABT_INT (((REG32(ADR_ALC_RLS_ABORT)) & 0x00008000 ) >> 15)
++#define GET_RLS_ABT_ID (((REG32(ADR_ALC_RLS_ABORT)) & 0x007f0000 ) >> 16)
++#define GET_RLS_ABT_INT (((REG32(ADR_ALC_RLS_ABORT)) & 0x80000000 ) >> 31)
++#define GET_DEBUG_CTL (((REG32(ADR_DEBUG_CTL)) & 0x000000ff ) >> 0)
++#define GET_DEBUG_H16 (((REG32(ADR_DEBUG_CTL)) & 0x00000100 ) >> 8)
++#define GET_DEBUG_OUT (((REG32(ADR_DEBUG_OUT)) & 0xffffffff ) >> 0)
++#define GET_ALC_ERR (((REG32(ADR_MMU_STATUS)) & 0x00000001 ) >> 0)
++#define GET_RLS_ERR (((REG32(ADR_MMU_STATUS)) & 0x00000002 ) >> 1)
++#define GET_AL_STATE (((REG32(ADR_MMU_STATUS)) & 0x00000700 ) >> 8)
++#define GET_RL_STATE (((REG32(ADR_MMU_STATUS)) & 0x00007000 ) >> 12)
++#define GET_ALC_ERR_ID (((REG32(ADR_MMU_STATUS)) & 0x007f0000 ) >> 16)
++#define GET_RLS_ERR_ID (((REG32(ADR_MMU_STATUS)) & 0x7f000000 ) >> 24)
++#define GET_DMN_NOHIT_FLAG (((REG32(ADR_DMN_STATUS)) & 0x00000001 ) >> 0)
++#define GET_DMN_FLAG (((REG32(ADR_DMN_STATUS)) & 0x00000002 ) >> 1)
++#define GET_DMN_WR (((REG32(ADR_DMN_STATUS)) & 0x00000008 ) >> 3)
++#define GET_DMN_PORT (((REG32(ADR_DMN_STATUS)) & 0x000000f0 ) >> 4)
++#define GET_DMN_NHIT_ID (((REG32(ADR_DMN_STATUS)) & 0x00007f00 ) >> 8)
++#define GET_DMN_NHIT_ADDR (((REG32(ADR_DMN_STATUS)) & 0xffff0000 ) >> 16)
++#define GET_TX_MOUNT (((REG32(ADR_TAG_STATUS)) & 0x000000ff ) >> 0)
++#define GET_RX_MOUNT (((REG32(ADR_TAG_STATUS)) & 0x0000ff00 ) >> 8)
++#define GET_AVA_TAG (((REG32(ADR_TAG_STATUS)) & 0x01ff0000 ) >> 16)
++#define GET_PKTBUF_FULL (((REG32(ADR_TAG_STATUS)) & 0x80000000 ) >> 31)
++#define GET_DMN_NOHIT_MCU (((REG32(ADR_DMN_MCU_STATUS)) & 0x00000001 ) >> 0)
++#define GET_DMN_MCU_FLAG (((REG32(ADR_DMN_MCU_STATUS)) & 0x00000002 ) >> 1)
++#define GET_DMN_MCU_WR (((REG32(ADR_DMN_MCU_STATUS)) & 0x00000008 ) >> 3)
++#define GET_DMN_MCU_PORT (((REG32(ADR_DMN_MCU_STATUS)) & 0x000000f0 ) >> 4)
++#define GET_DMN_MCU_ID (((REG32(ADR_DMN_MCU_STATUS)) & 0x00007f00 ) >> 8)
++#define GET_DMN_MCU_ADDR (((REG32(ADR_DMN_MCU_STATUS)) & 0xffff0000 ) >> 16)
++#define GET_MB_IDTBL_31_0 (((REG32(ADR_MB_IDTBL_0_STATUS)) & 0xffffffff ) >> 0)
++#define GET_MB_IDTBL_63_32 (((REG32(ADR_MB_IDTBL_1_STATUS)) & 0xffffffff ) >> 0)
++#define GET_MB_IDTBL_95_64 (((REG32(ADR_MB_IDTBL_2_STATUS)) & 0xffffffff ) >> 0)
++#define GET_MB_IDTBL_127_96 (((REG32(ADR_MB_IDTBL_3_STATUS)) & 0xffffffff ) >> 0)
++#define GET_PKT_IDTBL_31_0 (((REG32(ADR_PKT_IDTBL_0_STATUS)) & 0xffffffff ) >> 0)
++#define GET_PKT_IDTBL_63_32 (((REG32(ADR_PKT_IDTBL_1_STATUS)) & 0xffffffff ) >> 0)
++#define GET_PKT_IDTBL_95_64 (((REG32(ADR_PKT_IDTBL_2_STATUS)) & 0xffffffff ) >> 0)
++#define GET_PKT_IDTBL_127_96 (((REG32(ADR_PKT_IDTBL_3_STATUS)) & 0xffffffff ) >> 0)
++#define GET_DMN_IDTBL_31_0 (((REG32(ADR_DMN_IDTBL_0_STATUS)) & 0xffffffff ) >> 0)
++#define GET_DMN_IDTBL_63_32 (((REG32(ADR_DMN_IDTBL_1_STATUS)) & 0xffffffff ) >> 0)
++#define GET_DMN_IDTBL_95_64 (((REG32(ADR_DMN_IDTBL_2_STATUS)) & 0xffffffff ) >> 0)
++#define GET_DMN_IDTBL_127_96 (((REG32(ADR_DMN_IDTBL_3_STATUS)) & 0xffffffff ) >> 0)
++#define GET_NEQ_MB_ID_31_0 (((REG32(ADR_MB_NEQID_0_STATUS)) & 0xffffffff ) >> 0)
++#define GET_NEQ_MB_ID_63_32 (((REG32(ADR_MB_NEQID_1_STATUS)) & 0xffffffff ) >> 0)
++#define GET_NEQ_MB_ID_95_64 (((REG32(ADR_MB_NEQID_2_STATUS)) & 0xffffffff ) >> 0)
++#define GET_NEQ_MB_ID_127_96 (((REG32(ADR_MB_NEQID_3_STATUS)) & 0xffffffff ) >> 0)
++#define GET_NEQ_PKT_ID_31_0 (((REG32(ADR_PKT_NEQID_0_STATUS)) & 0xffffffff ) >> 0)
++#define GET_NEQ_PKT_ID_63_32 (((REG32(ADR_PKT_NEQID_1_STATUS)) & 0xffffffff ) >> 0)
++#define GET_NEQ_PKT_ID_95_64 (((REG32(ADR_PKT_NEQID_2_STATUS)) & 0xffffffff ) >> 0)
++#define GET_NEQ_PKT_ID_127_96 (((REG32(ADR_PKT_NEQID_3_STATUS)) & 0xffffffff ) >> 0)
++#define GET_ALC_NOCHG_ID (((REG32(ADR_ALC_NOCHG_ID_STATUS)) & 0x0000007f ) >> 0)
++#define GET_ALC_NOCHG_INT (((REG32(ADR_ALC_NOCHG_ID_STATUS)) & 0x00008000 ) >> 15)
++#define GET_NEQ_PKT_FLAG (((REG32(ADR_ALC_NOCHG_ID_STATUS)) & 0x00010000 ) >> 16)
++#define GET_NEQ_MB_FLAG (((REG32(ADR_ALC_NOCHG_ID_STATUS)) & 0x01000000 ) >> 24)
++#define GET_SRAM_TAG_0 (((REG32(ADR_TAG_SRAM0_F_STATUS_0)) & 0x0000ffff ) >> 0)
++#define GET_SRAM_TAG_1 (((REG32(ADR_TAG_SRAM0_F_STATUS_0)) & 0xffff0000 ) >> 16)
++#define GET_SRAM_TAG_2 (((REG32(ADR_TAG_SRAM0_F_STATUS_1)) & 0x0000ffff ) >> 0)
++#define GET_SRAM_TAG_3 (((REG32(ADR_TAG_SRAM0_F_STATUS_1)) & 0xffff0000 ) >> 16)
++#define GET_SRAM_TAG_4 (((REG32(ADR_TAG_SRAM0_F_STATUS_2)) & 0x0000ffff ) >> 0)
++#define GET_SRAM_TAG_5 (((REG32(ADR_TAG_SRAM0_F_STATUS_2)) & 0xffff0000 ) >> 16)
++#define GET_SRAM_TAG_6 (((REG32(ADR_TAG_SRAM0_F_STATUS_3)) & 0x0000ffff ) >> 0)
++#define GET_SRAM_TAG_7 (((REG32(ADR_TAG_SRAM0_F_STATUS_3)) & 0xffff0000 ) >> 16)
++#define GET_SRAM_TAG_8 (((REG32(ADR_TAG_SRAM0_F_STATUS_4)) & 0x0000ffff ) >> 0)
++#define GET_SRAM_TAG_9 (((REG32(ADR_TAG_SRAM0_F_STATUS_4)) & 0xffff0000 ) >> 16)
++#define GET_SRAM_TAG_10 (((REG32(ADR_TAG_SRAM0_F_STATUS_5)) & 0x0000ffff ) >> 0)
++#define GET_SRAM_TAG_11 (((REG32(ADR_TAG_SRAM0_F_STATUS_5)) & 0xffff0000 ) >> 16)
++#define GET_SRAM_TAG_12 (((REG32(ADR_TAG_SRAM0_F_STATUS_6)) & 0x0000ffff ) >> 0)
++#define GET_SRAM_TAG_13 (((REG32(ADR_TAG_SRAM0_F_STATUS_6)) & 0xffff0000 ) >> 16)
++#define GET_SRAM_TAG_14 (((REG32(ADR_TAG_SRAM0_F_STATUS_7)) & 0x0000ffff ) >> 0)
++#define GET_SRAM_TAG_15 (((REG32(ADR_TAG_SRAM0_F_STATUS_7)) & 0xffff0000 ) >> 16)
++#define SET_MCU_ENABLE(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 0) | ((REG32(ADR_BRG_SW_RST)) & 0xfffffffe))
++#define SET_MAC_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 1) | ((REG32(ADR_BRG_SW_RST)) & 0xfffffffd))
++#define SET_MCU_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 2) | ((REG32(ADR_BRG_SW_RST)) & 0xfffffffb))
++#define SET_SDIO_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 3) | ((REG32(ADR_BRG_SW_RST)) & 0xfffffff7))
++#define SET_SPI_SLV_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 4) | ((REG32(ADR_BRG_SW_RST)) & 0xffffffef))
++#define SET_UART_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 5) | ((REG32(ADR_BRG_SW_RST)) & 0xffffffdf))
++#define SET_DMA_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 6) | ((REG32(ADR_BRG_SW_RST)) & 0xffffffbf))
++#define SET_WDT_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 7) | ((REG32(ADR_BRG_SW_RST)) & 0xffffff7f))
++#define SET_I2C_SLV_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 8) | ((REG32(ADR_BRG_SW_RST)) & 0xfffffeff))
++#define SET_INT_CTL_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 9) | ((REG32(ADR_BRG_SW_RST)) & 0xfffffdff))
++#define SET_BTCX_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 10) | ((REG32(ADR_BRG_SW_RST)) & 0xfffffbff))
++#define SET_GPIO_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 11) | ((REG32(ADR_BRG_SW_RST)) & 0xfffff7ff))
++#define SET_US0TMR_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 12) | ((REG32(ADR_BRG_SW_RST)) & 0xffffefff))
++#define SET_US1TMR_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 13) | ((REG32(ADR_BRG_SW_RST)) & 0xffffdfff))
++#define SET_US2TMR_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 14) | ((REG32(ADR_BRG_SW_RST)) & 0xffffbfff))
++#define SET_US3TMR_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 15) | ((REG32(ADR_BRG_SW_RST)) & 0xffff7fff))
++#define SET_MS0TMR_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 16) | ((REG32(ADR_BRG_SW_RST)) & 0xfffeffff))
++#define SET_MS1TMR_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 17) | ((REG32(ADR_BRG_SW_RST)) & 0xfffdffff))
++#define SET_MS2TMR_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 18) | ((REG32(ADR_BRG_SW_RST)) & 0xfffbffff))
++#define SET_MS3TMR_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 19) | ((REG32(ADR_BRG_SW_RST)) & 0xfff7ffff))
++#define SET_RF_BB_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 20) | ((REG32(ADR_BRG_SW_RST)) & 0xffefffff))
++#define SET_SYS_ALL_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 21) | ((REG32(ADR_BRG_SW_RST)) & 0xffdfffff))
++#define SET_DAT_UART_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 22) | ((REG32(ADR_BRG_SW_RST)) & 0xffbfffff))
++#define SET_I2C_MST_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 23) | ((REG32(ADR_BRG_SW_RST)) & 0xff7fffff))
++#define SET_RG_REBOOT(_VAL_) (REG32(ADR_BOOT)) = (((_VAL_) << 0) | ((REG32(ADR_BOOT)) & 0xfffffffe))
++#define SET_TRAP_IMG_FLS(_VAL_) (REG32(ADR_BOOT)) = (((_VAL_) << 16) | ((REG32(ADR_BOOT)) & 0xfffeffff))
++#define SET_TRAP_REBOOT(_VAL_) (REG32(ADR_BOOT)) = (((_VAL_) << 17) | ((REG32(ADR_BOOT)) & 0xfffdffff))
++#define SET_TRAP_BOOT_FLS(_VAL_) (REG32(ADR_BOOT)) = (((_VAL_) << 18) | ((REG32(ADR_BOOT)) & 0xfffbffff))
++#define SET_CHIP_ID_31_0(_VAL_) (REG32(ADR_CHIP_ID_0)) = (((_VAL_) << 0) | ((REG32(ADR_CHIP_ID_0)) & 0x00000000))
++#define SET_CHIP_ID_63_32(_VAL_) (REG32(ADR_CHIP_ID_1)) = (((_VAL_) << 0) | ((REG32(ADR_CHIP_ID_1)) & 0x00000000))
++#define SET_CHIP_ID_95_64(_VAL_) (REG32(ADR_CHIP_ID_2)) = (((_VAL_) << 0) | ((REG32(ADR_CHIP_ID_2)) & 0x00000000))
++#define SET_CHIP_ID_127_96(_VAL_) (REG32(ADR_CHIP_ID_3)) = (((_VAL_) << 0) | ((REG32(ADR_CHIP_ID_3)) & 0x00000000))
++#define SET_CK_SEL_1_0(_VAL_) (REG32(ADR_CLOCK_SELECTION)) = (((_VAL_) << 0) | ((REG32(ADR_CLOCK_SELECTION)) & 0xfffffffc))
++#define SET_CK_SEL_2(_VAL_) (REG32(ADR_CLOCK_SELECTION)) = (((_VAL_) << 2) | ((REG32(ADR_CLOCK_SELECTION)) & 0xfffffffb))
++#define SET_SYS_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 0) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffffffe))
++#define SET_MAC_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 1) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffffffd))
++#define SET_MCU_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 2) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffffffb))
++#define SET_SDIO_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 3) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffffff7))
++#define SET_SPI_SLV_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 4) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xffffffef))
++#define SET_UART_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 5) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xffffffdf))
++#define SET_DMA_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 6) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xffffffbf))
++#define SET_WDT_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 7) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xffffff7f))
++#define SET_I2C_SLV_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 8) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffffeff))
++#define SET_INT_CTL_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 9) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffffdff))
++#define SET_BTCX_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 10) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffffbff))
++#define SET_GPIO_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 11) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffff7ff))
++#define SET_US0TMR_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 12) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xffffefff))
++#define SET_US1TMR_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 13) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xffffdfff))
++#define SET_US2TMR_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 14) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xffffbfff))
++#define SET_US3TMR_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 15) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xffff7fff))
++#define SET_MS0TMR_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 16) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffeffff))
++#define SET_MS1TMR_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 17) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffdffff))
++#define SET_MS2TMR_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 18) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffbffff))
++#define SET_MS3TMR_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 19) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfff7ffff))
++#define SET_BIST_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 20) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xffefffff))
++#define SET_I2C_MST_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 23) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xff7fffff))
++#define SET_BTCX_CSR_CLK_EN(_VAL_) (REG32(ADR_SYS_CSR_CLOCK_ENABLE)) = (((_VAL_) << 10) | ((REG32(ADR_SYS_CSR_CLOCK_ENABLE)) & 0xfffffbff))
++#define SET_MCU_DBG_SEL(_VAL_) (REG32(ADR_MCU_DBG_SEL)) = (((_VAL_) << 0) | ((REG32(ADR_MCU_DBG_SEL)) & 0xffffffc0))
++#define SET_MCU_STOP_NOGRANT(_VAL_) (REG32(ADR_MCU_DBG_SEL)) = (((_VAL_) << 8) | ((REG32(ADR_MCU_DBG_SEL)) & 0xfffffeff))
++#define SET_MCU_STOP_ANYTIME(_VAL_) (REG32(ADR_MCU_DBG_SEL)) = (((_VAL_) << 9) | ((REG32(ADR_MCU_DBG_SEL)) & 0xfffffdff))
++#define SET_MCU_DBG_DATA(_VAL_) (REG32(ADR_MCU_DBG_DATA)) = (((_VAL_) << 0) | ((REG32(ADR_MCU_DBG_DATA)) & 0x00000000))
++#define SET_AHB_SW_RST(_VAL_) (REG32(ADR_AHB_BRG_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_AHB_BRG_STATUS)) & 0xfffffffe))
++#define SET_AHB_ERR_RST(_VAL_) (REG32(ADR_AHB_BRG_STATUS)) = (((_VAL_) << 1) | ((REG32(ADR_AHB_BRG_STATUS)) & 0xfffffffd))
++#define SET_REG_AHB_DEBUG_MX(_VAL_) (REG32(ADR_AHB_BRG_STATUS)) = (((_VAL_) << 4) | ((REG32(ADR_AHB_BRG_STATUS)) & 0xffffffcf))
++#define SET_REG_PKT_W_NBRT(_VAL_) (REG32(ADR_AHB_BRG_STATUS)) = (((_VAL_) << 8) | ((REG32(ADR_AHB_BRG_STATUS)) & 0xfffffeff))
++#define SET_REG_PKT_R_NBRT(_VAL_) (REG32(ADR_AHB_BRG_STATUS)) = (((_VAL_) << 9) | ((REG32(ADR_AHB_BRG_STATUS)) & 0xfffffdff))
++#define SET_IQ_SRAM_SEL_0(_VAL_) (REG32(ADR_AHB_BRG_STATUS)) = (((_VAL_) << 12) | ((REG32(ADR_AHB_BRG_STATUS)) & 0xffffefff))
++#define SET_IQ_SRAM_SEL_1(_VAL_) (REG32(ADR_AHB_BRG_STATUS)) = (((_VAL_) << 13) | ((REG32(ADR_AHB_BRG_STATUS)) & 0xffffdfff))
++#define SET_IQ_SRAM_SEL_2(_VAL_) (REG32(ADR_AHB_BRG_STATUS)) = (((_VAL_) << 14) | ((REG32(ADR_AHB_BRG_STATUS)) & 0xffffbfff))
++#define SET_AHB_STATUS(_VAL_) (REG32(ADR_AHB_BRG_STATUS)) = (((_VAL_) << 16) | ((REG32(ADR_AHB_BRG_STATUS)) & 0x0000ffff))
++#define SET_PARALLEL_DR(_VAL_) (REG32(ADR_BIST_BIST_CTRL)) = (((_VAL_) << 0) | ((REG32(ADR_BIST_BIST_CTRL)) & 0xfffffffe))
++#define SET_MBRUN(_VAL_) (REG32(ADR_BIST_BIST_CTRL)) = (((_VAL_) << 4) | ((REG32(ADR_BIST_BIST_CTRL)) & 0xffffffef))
++#define SET_SHIFT_DR(_VAL_) (REG32(ADR_BIST_BIST_CTRL)) = (((_VAL_) << 8) | ((REG32(ADR_BIST_BIST_CTRL)) & 0xfffffeff))
++#define SET_MODE_REG_SI(_VAL_) (REG32(ADR_BIST_BIST_CTRL)) = (((_VAL_) << 9) | ((REG32(ADR_BIST_BIST_CTRL)) & 0xfffffdff))
++#define SET_SIMULATION_MODE(_VAL_) (REG32(ADR_BIST_BIST_CTRL)) = (((_VAL_) << 10) | ((REG32(ADR_BIST_BIST_CTRL)) & 0xfffffbff))
++#define SET_DBIST_MODE(_VAL_) (REG32(ADR_BIST_BIST_CTRL)) = (((_VAL_) << 11) | ((REG32(ADR_BIST_BIST_CTRL)) & 0xfffff7ff))
++#define SET_MODE_REG_IN(_VAL_) (REG32(ADR_BIST_MODE_REG_IN)) = (((_VAL_) << 0) | ((REG32(ADR_BIST_MODE_REG_IN)) & 0xffe00000))
++#define SET_MODE_REG_OUT_MCU(_VAL_) (REG32(ADR_BIST_MODE_REG_OUT)) = (((_VAL_) << 0) | ((REG32(ADR_BIST_MODE_REG_OUT)) & 0xffe00000))
++#define SET_MODE_REG_SO_MCU(_VAL_) (REG32(ADR_BIST_MODE_REG_OUT)) = (((_VAL_) << 31) | ((REG32(ADR_BIST_MODE_REG_OUT)) & 0x7fffffff))
++#define SET_MONITOR_BUS_MCU_31_0(_VAL_) (REG32(ADR_BIST_MONITOR_BUS_LSB)) = (((_VAL_) << 0) | ((REG32(ADR_BIST_MONITOR_BUS_LSB)) & 0x00000000))
++#define SET_MONITOR_BUS_MCU_33_32(_VAL_) (REG32(ADR_BIST_MONITOR_BUS_MSB)) = (((_VAL_) << 0) | ((REG32(ADR_BIST_MONITOR_BUS_MSB)) & 0xfffffffc))
++#define SET_TB_ADR_SEL(_VAL_) (REG32(ADR_TB_ADR_SEL)) = (((_VAL_) << 0) | ((REG32(ADR_TB_ADR_SEL)) & 0xffff0000))
++#define SET_TB_CS(_VAL_) (REG32(ADR_TB_ADR_SEL)) = (((_VAL_) << 31) | ((REG32(ADR_TB_ADR_SEL)) & 0x7fffffff))
++#define SET_TB_RDATA(_VAL_) (REG32(ADR_TB_RDATA)) = (((_VAL_) << 0) | ((REG32(ADR_TB_RDATA)) & 0x00000000))
++#define SET_UART_W2B_EN(_VAL_) (REG32(ADR_UART_W2B)) = (((_VAL_) << 0) | ((REG32(ADR_UART_W2B)) & 0xfffffffe))
++#define SET_DATA_UART_W2B_EN(_VAL_) (REG32(ADR_UART_W2B)) = (((_VAL_) << 4) | ((REG32(ADR_UART_W2B)) & 0xffffffef))
++#define SET_AHB_ILL_ADDR(_VAL_) (REG32(ADR_AHB_ILL_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_AHB_ILL_ADDR)) & 0x00000000))
++#define SET_AHB_FEN_ADDR(_VAL_) (REG32(ADR_AHB_FEN_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_AHB_FEN_ADDR)) & 0x00000000))
++#define SET_ILL_ADDR_CLR(_VAL_) (REG32(ADR_AHB_ILLFEN_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_AHB_ILLFEN_STATUS)) & 0xfffffffe))
++#define SET_FENCE_HIT_CLR(_VAL_) (REG32(ADR_AHB_ILLFEN_STATUS)) = (((_VAL_) << 1) | ((REG32(ADR_AHB_ILLFEN_STATUS)) & 0xfffffffd))
++#define SET_ILL_ADDR_INT(_VAL_) (REG32(ADR_AHB_ILLFEN_STATUS)) = (((_VAL_) << 4) | ((REG32(ADR_AHB_ILLFEN_STATUS)) & 0xffffffef))
++#define SET_FENCE_HIT_INT(_VAL_) (REG32(ADR_AHB_ILLFEN_STATUS)) = (((_VAL_) << 5) | ((REG32(ADR_AHB_ILLFEN_STATUS)) & 0xffffffdf))
++#define SET_PWM_INI_VALUE_P_A(_VAL_) (REG32(ADR_PWM_A)) = (((_VAL_) << 0) | ((REG32(ADR_PWM_A)) & 0xffffff00))
++#define SET_PWM_INI_VALUE_N_A(_VAL_) (REG32(ADR_PWM_A)) = (((_VAL_) << 8) | ((REG32(ADR_PWM_A)) & 0xffff00ff))
++#define SET_PWM_POST_SCALER_A(_VAL_) (REG32(ADR_PWM_A)) = (((_VAL_) << 16) | ((REG32(ADR_PWM_A)) & 0xfff0ffff))
++#define SET_PWM_ALWAYSON_A(_VAL_) (REG32(ADR_PWM_A)) = (((_VAL_) << 29) | ((REG32(ADR_PWM_A)) & 0xdfffffff))
++#define SET_PWM_INVERT_A(_VAL_) (REG32(ADR_PWM_A)) = (((_VAL_) << 30) | ((REG32(ADR_PWM_A)) & 0xbfffffff))
++#define SET_PWM_ENABLE_A(_VAL_) (REG32(ADR_PWM_A)) = (((_VAL_) << 31) | ((REG32(ADR_PWM_A)) & 0x7fffffff))
++#define SET_PWM_INI_VALUE_P_B(_VAL_) (REG32(ADR_PWM_B)) = (((_VAL_) << 0) | ((REG32(ADR_PWM_B)) & 0xffffff00))
++#define SET_PWM_INI_VALUE_N_B(_VAL_) (REG32(ADR_PWM_B)) = (((_VAL_) << 8) | ((REG32(ADR_PWM_B)) & 0xffff00ff))
++#define SET_PWM_POST_SCALER_B(_VAL_) (REG32(ADR_PWM_B)) = (((_VAL_) << 16) | ((REG32(ADR_PWM_B)) & 0xfff0ffff))
++#define SET_PWM_ALWAYSON_B(_VAL_) (REG32(ADR_PWM_B)) = (((_VAL_) << 29) | ((REG32(ADR_PWM_B)) & 0xdfffffff))
++#define SET_PWM_INVERT_B(_VAL_) (REG32(ADR_PWM_B)) = (((_VAL_) << 30) | ((REG32(ADR_PWM_B)) & 0xbfffffff))
++#define SET_PWM_ENABLE_B(_VAL_) (REG32(ADR_PWM_B)) = (((_VAL_) << 31) | ((REG32(ADR_PWM_B)) & 0x7fffffff))
++#define SET_HBUSREQ_LOCK(_VAL_) (REG32(ADR_HBUSREQ_LOCK)) = (((_VAL_) << 0) | ((REG32(ADR_HBUSREQ_LOCK)) & 0xffffe000))
++#define SET_HBURST_LOCK(_VAL_) (REG32(ADR_HBURST_LOCK)) = (((_VAL_) << 0) | ((REG32(ADR_HBURST_LOCK)) & 0xffffe000))
++#define SET_PRESCALER_USTIMER(_VAL_) (REG32(ADR_PRESCALER_USTIMER)) = (((_VAL_) << 0) | ((REG32(ADR_PRESCALER_USTIMER)) & 0xfffffe00))
++#define SET_MODE_REG_IN_MMU(_VAL_) (REG32(ADR_BIST_MODE_REG_IN_MMU)) = (((_VAL_) << 0) | ((REG32(ADR_BIST_MODE_REG_IN_MMU)) & 0xffff0000))
++#define SET_MODE_REG_OUT_MMU(_VAL_) (REG32(ADR_BIST_MODE_REG_OUT_MMU)) = (((_VAL_) << 0) | ((REG32(ADR_BIST_MODE_REG_OUT_MMU)) & 0xffff0000))
++#define SET_MODE_REG_SO_MMU(_VAL_) (REG32(ADR_BIST_MODE_REG_OUT_MMU)) = (((_VAL_) << 31) | ((REG32(ADR_BIST_MODE_REG_OUT_MMU)) & 0x7fffffff))
++#define SET_MONITOR_BUS_MMU(_VAL_) (REG32(ADR_BIST_MONITOR_BUS_MMU)) = (((_VAL_) << 0) | ((REG32(ADR_BIST_MONITOR_BUS_MMU)) & 0xfff80000))
++#define SET_TEST_MODE0(_VAL_) (REG32(ADR_TEST_MODE)) = (((_VAL_) << 0) | ((REG32(ADR_TEST_MODE)) & 0xfffffffe))
++#define SET_TEST_MODE1(_VAL_) (REG32(ADR_TEST_MODE)) = (((_VAL_) << 1) | ((REG32(ADR_TEST_MODE)) & 0xfffffffd))
++#define SET_TEST_MODE2(_VAL_) (REG32(ADR_TEST_MODE)) = (((_VAL_) << 2) | ((REG32(ADR_TEST_MODE)) & 0xfffffffb))
++#define SET_TEST_MODE3(_VAL_) (REG32(ADR_TEST_MODE)) = (((_VAL_) << 3) | ((REG32(ADR_TEST_MODE)) & 0xfffffff7))
++#define SET_TEST_MODE4(_VAL_) (REG32(ADR_TEST_MODE)) = (((_VAL_) << 4) | ((REG32(ADR_TEST_MODE)) & 0xffffffef))
++#define SET_TEST_MODE_ALL(_VAL_) (REG32(ADR_TEST_MODE)) = (((_VAL_) << 5) | ((REG32(ADR_TEST_MODE)) & 0xffffffdf))
++#define SET_WDT_INIT(_VAL_) (REG32(ADR_BOOT_INFO)) = (((_VAL_) << 0) | ((REG32(ADR_BOOT_INFO)) & 0xfffffffe))
++#define SET_SD_HOST_INIT(_VAL_) (REG32(ADR_BOOT_INFO)) = (((_VAL_) << 1) | ((REG32(ADR_BOOT_INFO)) & 0xfffffffd))
++#define SET_ALLOW_SD_RESET(_VAL_) (REG32(ADR_SD_INIT_CFG)) = (((_VAL_) << 0) | ((REG32(ADR_SD_INIT_CFG)) & 0xfffffffe))
++#define SET_UART_NRTS(_VAL_) (REG32(ADR_SPARE_UART_INFO)) = (((_VAL_) << 0) | ((REG32(ADR_SPARE_UART_INFO)) & 0xfffffffe))
++#define SET_UART_NCTS(_VAL_) (REG32(ADR_SPARE_UART_INFO)) = (((_VAL_) << 1) | ((REG32(ADR_SPARE_UART_INFO)) & 0xfffffffd))
++#define SET_TU0_TM_INIT_VALUE(_VAL_) (REG32(ADR_TU0_MICROSECOND_TIMER)) = (((_VAL_) << 0) | ((REG32(ADR_TU0_MICROSECOND_TIMER)) & 0xffff0000))
++#define SET_TU0_TM_MODE(_VAL_) (REG32(ADR_TU0_MICROSECOND_TIMER)) = (((_VAL_) << 16) | ((REG32(ADR_TU0_MICROSECOND_TIMER)) & 0xfffeffff))
++#define SET_TU0_TM_INT_STS_DONE(_VAL_) (REG32(ADR_TU0_MICROSECOND_TIMER)) = (((_VAL_) << 17) | ((REG32(ADR_TU0_MICROSECOND_TIMER)) & 0xfffdffff))
++#define SET_TU0_TM_INT_MASK(_VAL_) (REG32(ADR_TU0_MICROSECOND_TIMER)) = (((_VAL_) << 18) | ((REG32(ADR_TU0_MICROSECOND_TIMER)) & 0xfffbffff))
++#define SET_TU0_TM_CUR_VALUE(_VAL_) (REG32(ADR_TU0_CURRENT_MICROSECOND_TIME_VALUE)) = (((_VAL_) << 0) | ((REG32(ADR_TU0_CURRENT_MICROSECOND_TIME_VALUE)) & 0xffff0000))
++#define SET_TU1_TM_INIT_VALUE(_VAL_) (REG32(ADR_TU1_MICROSECOND_TIMER)) = (((_VAL_) << 0) | ((REG32(ADR_TU1_MICROSECOND_TIMER)) & 0xffff0000))
++#define SET_TU1_TM_MODE(_VAL_) (REG32(ADR_TU1_MICROSECOND_TIMER)) = (((_VAL_) << 16) | ((REG32(ADR_TU1_MICROSECOND_TIMER)) & 0xfffeffff))
++#define SET_TU1_TM_INT_STS_DONE(_VAL_) (REG32(ADR_TU1_MICROSECOND_TIMER)) = (((_VAL_) << 17) | ((REG32(ADR_TU1_MICROSECOND_TIMER)) & 0xfffdffff))
++#define SET_TU1_TM_INT_MASK(_VAL_) (REG32(ADR_TU1_MICROSECOND_TIMER)) = (((_VAL_) << 18) | ((REG32(ADR_TU1_MICROSECOND_TIMER)) & 0xfffbffff))
++#define SET_TU1_TM_CUR_VALUE(_VAL_) (REG32(ADR_TU1_CURRENT_MICROSECOND_TIME_VALUE)) = (((_VAL_) << 0) | ((REG32(ADR_TU1_CURRENT_MICROSECOND_TIME_VALUE)) & 0xffff0000))
++#define SET_TU2_TM_INIT_VALUE(_VAL_) (REG32(ADR_TU2_MICROSECOND_TIMER)) = (((_VAL_) << 0) | ((REG32(ADR_TU2_MICROSECOND_TIMER)) & 0xffff0000))
++#define SET_TU2_TM_MODE(_VAL_) (REG32(ADR_TU2_MICROSECOND_TIMER)) = (((_VAL_) << 16) | ((REG32(ADR_TU2_MICROSECOND_TIMER)) & 0xfffeffff))
++#define SET_TU2_TM_INT_STS_DONE(_VAL_) (REG32(ADR_TU2_MICROSECOND_TIMER)) = (((_VAL_) << 17) | ((REG32(ADR_TU2_MICROSECOND_TIMER)) & 0xfffdffff))
++#define SET_TU2_TM_INT_MASK(_VAL_) (REG32(ADR_TU2_MICROSECOND_TIMER)) = (((_VAL_) << 18) | ((REG32(ADR_TU2_MICROSECOND_TIMER)) & 0xfffbffff))
++#define SET_TU2_TM_CUR_VALUE(_VAL_) (REG32(ADR_TU2_CURRENT_MICROSECOND_TIME_VALUE)) = (((_VAL_) << 0) | ((REG32(ADR_TU2_CURRENT_MICROSECOND_TIME_VALUE)) & 0xffff0000))
++#define SET_TU3_TM_INIT_VALUE(_VAL_) (REG32(ADR_TU3_MICROSECOND_TIMER)) = (((_VAL_) << 0) | ((REG32(ADR_TU3_MICROSECOND_TIMER)) & 0xffff0000))
++#define SET_TU3_TM_MODE(_VAL_) (REG32(ADR_TU3_MICROSECOND_TIMER)) = (((_VAL_) << 16) | ((REG32(ADR_TU3_MICROSECOND_TIMER)) & 0xfffeffff))
++#define SET_TU3_TM_INT_STS_DONE(_VAL_) (REG32(ADR_TU3_MICROSECOND_TIMER)) = (((_VAL_) << 17) | ((REG32(ADR_TU3_MICROSECOND_TIMER)) & 0xfffdffff))
++#define SET_TU3_TM_INT_MASK(_VAL_) (REG32(ADR_TU3_MICROSECOND_TIMER)) = (((_VAL_) << 18) | ((REG32(ADR_TU3_MICROSECOND_TIMER)) & 0xfffbffff))
++#define SET_TU3_TM_CUR_VALUE(_VAL_) (REG32(ADR_TU3_CURRENT_MICROSECOND_TIME_VALUE)) = (((_VAL_) << 0) | ((REG32(ADR_TU3_CURRENT_MICROSECOND_TIME_VALUE)) & 0xffff0000))
++#define SET_TM0_TM_INIT_VALUE(_VAL_) (REG32(ADR_TM0_MILISECOND_TIMER)) = (((_VAL_) << 0) | ((REG32(ADR_TM0_MILISECOND_TIMER)) & 0xffff0000))
++#define SET_TM0_TM_MODE(_VAL_) (REG32(ADR_TM0_MILISECOND_TIMER)) = (((_VAL_) << 16) | ((REG32(ADR_TM0_MILISECOND_TIMER)) & 0xfffeffff))
++#define SET_TM0_TM_INT_STS_DONE(_VAL_) (REG32(ADR_TM0_MILISECOND_TIMER)) = (((_VAL_) << 17) | ((REG32(ADR_TM0_MILISECOND_TIMER)) & 0xfffdffff))
++#define SET_TM0_TM_INT_MASK(_VAL_) (REG32(ADR_TM0_MILISECOND_TIMER)) = (((_VAL_) << 18) | ((REG32(ADR_TM0_MILISECOND_TIMER)) & 0xfffbffff))
++#define SET_TM0_TM_CUR_VALUE(_VAL_) (REG32(ADR_TM0_CURRENT_MILISECOND_TIME_VALUE)) = (((_VAL_) << 0) | ((REG32(ADR_TM0_CURRENT_MILISECOND_TIME_VALUE)) & 0xffff0000))
++#define SET_TM1_TM_INIT_VALUE(_VAL_) (REG32(ADR_TM1_MILISECOND_TIMER)) = (((_VAL_) << 0) | ((REG32(ADR_TM1_MILISECOND_TIMER)) & 0xffff0000))
++#define SET_TM1_TM_MODE(_VAL_) (REG32(ADR_TM1_MILISECOND_TIMER)) = (((_VAL_) << 16) | ((REG32(ADR_TM1_MILISECOND_TIMER)) & 0xfffeffff))
++#define SET_TM1_TM_INT_STS_DONE(_VAL_) (REG32(ADR_TM1_MILISECOND_TIMER)) = (((_VAL_) << 17) | ((REG32(ADR_TM1_MILISECOND_TIMER)) & 0xfffdffff))
++#define SET_TM1_TM_INT_MASK(_VAL_) (REG32(ADR_TM1_MILISECOND_TIMER)) = (((_VAL_) << 18) | ((REG32(ADR_TM1_MILISECOND_TIMER)) & 0xfffbffff))
++#define SET_TM1_TM_CUR_VALUE(_VAL_) (REG32(ADR_TM1_CURRENT_MILISECOND_TIME_VALUE)) = (((_VAL_) << 0) | ((REG32(ADR_TM1_CURRENT_MILISECOND_TIME_VALUE)) & 0xffff0000))
++#define SET_TM2_TM_INIT_VALUE(_VAL_) (REG32(ADR_TM2_MILISECOND_TIMER)) = (((_VAL_) << 0) | ((REG32(ADR_TM2_MILISECOND_TIMER)) & 0xffff0000))
++#define SET_TM2_TM_MODE(_VAL_) (REG32(ADR_TM2_MILISECOND_TIMER)) = (((_VAL_) << 16) | ((REG32(ADR_TM2_MILISECOND_TIMER)) & 0xfffeffff))
++#define SET_TM2_TM_INT_STS_DONE(_VAL_) (REG32(ADR_TM2_MILISECOND_TIMER)) = (((_VAL_) << 17) | ((REG32(ADR_TM2_MILISECOND_TIMER)) & 0xfffdffff))
++#define SET_TM2_TM_INT_MASK(_VAL_) (REG32(ADR_TM2_MILISECOND_TIMER)) = (((_VAL_) << 18) | ((REG32(ADR_TM2_MILISECOND_TIMER)) & 0xfffbffff))
++#define SET_TM2_TM_CUR_VALUE(_VAL_) (REG32(ADR_TM2_CURRENT_MILISECOND_TIME_VALUE)) = (((_VAL_) << 0) | ((REG32(ADR_TM2_CURRENT_MILISECOND_TIME_VALUE)) & 0xffff0000))
++#define SET_TM3_TM_INIT_VALUE(_VAL_) (REG32(ADR_TM3_MILISECOND_TIMER)) = (((_VAL_) << 0) | ((REG32(ADR_TM3_MILISECOND_TIMER)) & 0xffff0000))
++#define SET_TM3_TM_MODE(_VAL_) (REG32(ADR_TM3_MILISECOND_TIMER)) = (((_VAL_) << 16) | ((REG32(ADR_TM3_MILISECOND_TIMER)) & 0xfffeffff))
++#define SET_TM3_TM_INT_STS_DONE(_VAL_) (REG32(ADR_TM3_MILISECOND_TIMER)) = (((_VAL_) << 17) | ((REG32(ADR_TM3_MILISECOND_TIMER)) & 0xfffdffff))
++#define SET_TM3_TM_INT_MASK(_VAL_) (REG32(ADR_TM3_MILISECOND_TIMER)) = (((_VAL_) << 18) | ((REG32(ADR_TM3_MILISECOND_TIMER)) & 0xfffbffff))
++#define SET_TM3_TM_CUR_VALUE(_VAL_) (REG32(ADR_TM3_CURRENT_MILISECOND_TIME_VALUE)) = (((_VAL_) << 0) | ((REG32(ADR_TM3_CURRENT_MILISECOND_TIME_VALUE)) & 0xffff0000))
++#define SET_MCU_WDT_TIME_CNT(_VAL_) (REG32(ADR_MCU_WDOG_REG)) = (((_VAL_) << 0) | ((REG32(ADR_MCU_WDOG_REG)) & 0xffff0000))
++#define SET_MCU_WDT_STATUS(_VAL_) (REG32(ADR_MCU_WDOG_REG)) = (((_VAL_) << 17) | ((REG32(ADR_MCU_WDOG_REG)) & 0xfffdffff))
++#define SET_MCU_WDOG_ENA(_VAL_) (REG32(ADR_MCU_WDOG_REG)) = (((_VAL_) << 31) | ((REG32(ADR_MCU_WDOG_REG)) & 0x7fffffff))
++#define SET_SYS_WDT_TIME_CNT(_VAL_) (REG32(ADR_SYS_WDOG_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SYS_WDOG_REG)) & 0xffff0000))
++#define SET_SYS_WDT_STATUS(_VAL_) (REG32(ADR_SYS_WDOG_REG)) = (((_VAL_) << 17) | ((REG32(ADR_SYS_WDOG_REG)) & 0xfffdffff))
++#define SET_SYS_WDOG_ENA(_VAL_) (REG32(ADR_SYS_WDOG_REG)) = (((_VAL_) << 31) | ((REG32(ADR_SYS_WDOG_REG)) & 0x7fffffff))
++#define SET_XLNA_EN_O_OE(_VAL_) (REG32(ADR_PAD6)) = (((_VAL_) << 0) | ((REG32(ADR_PAD6)) & 0xfffffffe))
++#define SET_XLNA_EN_O_PE(_VAL_) (REG32(ADR_PAD6)) = (((_VAL_) << 1) | ((REG32(ADR_PAD6)) & 0xfffffffd))
++#define SET_PAD6_IE(_VAL_) (REG32(ADR_PAD6)) = (((_VAL_) << 3) | ((REG32(ADR_PAD6)) & 0xfffffff7))
++#define SET_PAD6_SEL_I(_VAL_) (REG32(ADR_PAD6)) = (((_VAL_) << 4) | ((REG32(ADR_PAD6)) & 0xffffffcf))
++#define SET_PAD6_OD(_VAL_) (REG32(ADR_PAD6)) = (((_VAL_) << 8) | ((REG32(ADR_PAD6)) & 0xfffffeff))
++#define SET_PAD6_SEL_O(_VAL_) (REG32(ADR_PAD6)) = (((_VAL_) << 12) | ((REG32(ADR_PAD6)) & 0xffffefff))
++#define SET_XLNA_EN_O_C(_VAL_) (REG32(ADR_PAD6)) = (((_VAL_) << 28) | ((REG32(ADR_PAD6)) & 0xefffffff))
++#define SET_WIFI_TX_SW_O_OE(_VAL_) (REG32(ADR_PAD7)) = (((_VAL_) << 0) | ((REG32(ADR_PAD7)) & 0xfffffffe))
++#define SET_WIFI_TX_SW_O_PE(_VAL_) (REG32(ADR_PAD7)) = (((_VAL_) << 1) | ((REG32(ADR_PAD7)) & 0xfffffffd))
++#define SET_PAD7_IE(_VAL_) (REG32(ADR_PAD7)) = (((_VAL_) << 3) | ((REG32(ADR_PAD7)) & 0xfffffff7))
++#define SET_PAD7_SEL_I(_VAL_) (REG32(ADR_PAD7)) = (((_VAL_) << 4) | ((REG32(ADR_PAD7)) & 0xffffffcf))
++#define SET_PAD7_OD(_VAL_) (REG32(ADR_PAD7)) = (((_VAL_) << 8) | ((REG32(ADR_PAD7)) & 0xfffffeff))
++#define SET_PAD7_SEL_O(_VAL_) (REG32(ADR_PAD7)) = (((_VAL_) << 12) | ((REG32(ADR_PAD7)) & 0xffffefff))
++#define SET_WIFI_TX_SW_O_C(_VAL_) (REG32(ADR_PAD7)) = (((_VAL_) << 28) | ((REG32(ADR_PAD7)) & 0xefffffff))
++#define SET_WIFI_RX_SW_O_OE(_VAL_) (REG32(ADR_PAD8)) = (((_VAL_) << 0) | ((REG32(ADR_PAD8)) & 0xfffffffe))
++#define SET_WIFI_RX_SW_O_PE(_VAL_) (REG32(ADR_PAD8)) = (((_VAL_) << 1) | ((REG32(ADR_PAD8)) & 0xfffffffd))
++#define SET_PAD8_IE(_VAL_) (REG32(ADR_PAD8)) = (((_VAL_) << 3) | ((REG32(ADR_PAD8)) & 0xfffffff7))
++#define SET_PAD8_SEL_I(_VAL_) (REG32(ADR_PAD8)) = (((_VAL_) << 4) | ((REG32(ADR_PAD8)) & 0xffffffcf))
++#define SET_PAD8_OD(_VAL_) (REG32(ADR_PAD8)) = (((_VAL_) << 8) | ((REG32(ADR_PAD8)) & 0xfffffeff))
++#define SET_WIFI_RX_SW_O_C(_VAL_) (REG32(ADR_PAD8)) = (((_VAL_) << 28) | ((REG32(ADR_PAD8)) & 0xefffffff))
++#define SET_BT_SW_O_OE(_VAL_) (REG32(ADR_PAD9)) = (((_VAL_) << 0) | ((REG32(ADR_PAD9)) & 0xfffffffe))
++#define SET_BT_SW_O_PE(_VAL_) (REG32(ADR_PAD9)) = (((_VAL_) << 1) | ((REG32(ADR_PAD9)) & 0xfffffffd))
++#define SET_PAD9_IE(_VAL_) (REG32(ADR_PAD9)) = (((_VAL_) << 3) | ((REG32(ADR_PAD9)) & 0xfffffff7))
++#define SET_PAD9_SEL_I(_VAL_) (REG32(ADR_PAD9)) = (((_VAL_) << 4) | ((REG32(ADR_PAD9)) & 0xffffffcf))
++#define SET_PAD9_OD(_VAL_) (REG32(ADR_PAD9)) = (((_VAL_) << 8) | ((REG32(ADR_PAD9)) & 0xfffffeff))
++#define SET_PAD9_SEL_O(_VAL_) (REG32(ADR_PAD9)) = (((_VAL_) << 12) | ((REG32(ADR_PAD9)) & 0xffffefff))
++#define SET_BT_SW_O_C(_VAL_) (REG32(ADR_PAD9)) = (((_VAL_) << 28) | ((REG32(ADR_PAD9)) & 0xefffffff))
++#define SET_XPA_EN_O_OE(_VAL_) (REG32(ADR_PAD11)) = (((_VAL_) << 0) | ((REG32(ADR_PAD11)) & 0xfffffffe))
++#define SET_XPA_EN_O_PE(_VAL_) (REG32(ADR_PAD11)) = (((_VAL_) << 1) | ((REG32(ADR_PAD11)) & 0xfffffffd))
++#define SET_PAD11_IE(_VAL_) (REG32(ADR_PAD11)) = (((_VAL_) << 3) | ((REG32(ADR_PAD11)) & 0xfffffff7))
++#define SET_PAD11_SEL_I(_VAL_) (REG32(ADR_PAD11)) = (((_VAL_) << 4) | ((REG32(ADR_PAD11)) & 0xffffffcf))
++#define SET_PAD11_OD(_VAL_) (REG32(ADR_PAD11)) = (((_VAL_) << 8) | ((REG32(ADR_PAD11)) & 0xfffffeff))
++#define SET_PAD11_SEL_O(_VAL_) (REG32(ADR_PAD11)) = (((_VAL_) << 12) | ((REG32(ADR_PAD11)) & 0xffffefff))
++#define SET_XPA_EN_O_C(_VAL_) (REG32(ADR_PAD11)) = (((_VAL_) << 28) | ((REG32(ADR_PAD11)) & 0xefffffff))
++#define SET_PAD15_OE(_VAL_) (REG32(ADR_PAD15)) = (((_VAL_) << 0) | ((REG32(ADR_PAD15)) & 0xfffffffe))
++#define SET_PAD15_PE(_VAL_) (REG32(ADR_PAD15)) = (((_VAL_) << 1) | ((REG32(ADR_PAD15)) & 0xfffffffd))
++#define SET_PAD15_DS(_VAL_) (REG32(ADR_PAD15)) = (((_VAL_) << 2) | ((REG32(ADR_PAD15)) & 0xfffffffb))
++#define SET_PAD15_IE(_VAL_) (REG32(ADR_PAD15)) = (((_VAL_) << 3) | ((REG32(ADR_PAD15)) & 0xfffffff7))
++#define SET_PAD15_SEL_I(_VAL_) (REG32(ADR_PAD15)) = (((_VAL_) << 4) | ((REG32(ADR_PAD15)) & 0xffffffcf))
++#define SET_PAD15_OD(_VAL_) (REG32(ADR_PAD15)) = (((_VAL_) << 8) | ((REG32(ADR_PAD15)) & 0xfffffeff))
++#define SET_PAD15_SEL_O(_VAL_) (REG32(ADR_PAD15)) = (((_VAL_) << 12) | ((REG32(ADR_PAD15)) & 0xffffefff))
++#define SET_TEST_1_ID(_VAL_) (REG32(ADR_PAD15)) = (((_VAL_) << 28) | ((REG32(ADR_PAD15)) & 0xefffffff))
++#define SET_PAD16_OE(_VAL_) (REG32(ADR_PAD16)) = (((_VAL_) << 0) | ((REG32(ADR_PAD16)) & 0xfffffffe))
++#define SET_PAD16_PE(_VAL_) (REG32(ADR_PAD16)) = (((_VAL_) << 1) | ((REG32(ADR_PAD16)) & 0xfffffffd))
++#define SET_PAD16_DS(_VAL_) (REG32(ADR_PAD16)) = (((_VAL_) << 2) | ((REG32(ADR_PAD16)) & 0xfffffffb))
++#define SET_PAD16_IE(_VAL_) (REG32(ADR_PAD16)) = (((_VAL_) << 3) | ((REG32(ADR_PAD16)) & 0xfffffff7))
++#define SET_PAD16_SEL_I(_VAL_) (REG32(ADR_PAD16)) = (((_VAL_) << 4) | ((REG32(ADR_PAD16)) & 0xffffffcf))
++#define SET_PAD16_OD(_VAL_) (REG32(ADR_PAD16)) = (((_VAL_) << 8) | ((REG32(ADR_PAD16)) & 0xfffffeff))
++#define SET_PAD16_SEL_O(_VAL_) (REG32(ADR_PAD16)) = (((_VAL_) << 12) | ((REG32(ADR_PAD16)) & 0xffffefff))
++#define SET_TEST_2_ID(_VAL_) (REG32(ADR_PAD16)) = (((_VAL_) << 28) | ((REG32(ADR_PAD16)) & 0xefffffff))
++#define SET_PAD17_OE(_VAL_) (REG32(ADR_PAD17)) = (((_VAL_) << 0) | ((REG32(ADR_PAD17)) & 0xfffffffe))
++#define SET_PAD17_PE(_VAL_) (REG32(ADR_PAD17)) = (((_VAL_) << 1) | ((REG32(ADR_PAD17)) & 0xfffffffd))
++#define SET_PAD17_DS(_VAL_) (REG32(ADR_PAD17)) = (((_VAL_) << 2) | ((REG32(ADR_PAD17)) & 0xfffffffb))
++#define SET_PAD17_IE(_VAL_) (REG32(ADR_PAD17)) = (((_VAL_) << 3) | ((REG32(ADR_PAD17)) & 0xfffffff7))
++#define SET_PAD17_SEL_I(_VAL_) (REG32(ADR_PAD17)) = (((_VAL_) << 4) | ((REG32(ADR_PAD17)) & 0xffffffcf))
++#define SET_PAD17_OD(_VAL_) (REG32(ADR_PAD17)) = (((_VAL_) << 8) | ((REG32(ADR_PAD17)) & 0xfffffeff))
++#define SET_PAD17_SEL_O(_VAL_) (REG32(ADR_PAD17)) = (((_VAL_) << 12) | ((REG32(ADR_PAD17)) & 0xffffefff))
++#define SET_TEST_3_ID(_VAL_) (REG32(ADR_PAD17)) = (((_VAL_) << 28) | ((REG32(ADR_PAD17)) & 0xefffffff))
++#define SET_PAD18_OE(_VAL_) (REG32(ADR_PAD18)) = (((_VAL_) << 0) | ((REG32(ADR_PAD18)) & 0xfffffffe))
++#define SET_PAD18_PE(_VAL_) (REG32(ADR_PAD18)) = (((_VAL_) << 1) | ((REG32(ADR_PAD18)) & 0xfffffffd))
++#define SET_PAD18_DS(_VAL_) (REG32(ADR_PAD18)) = (((_VAL_) << 2) | ((REG32(ADR_PAD18)) & 0xfffffffb))
++#define SET_PAD18_IE(_VAL_) (REG32(ADR_PAD18)) = (((_VAL_) << 3) | ((REG32(ADR_PAD18)) & 0xfffffff7))
++#define SET_PAD18_SEL_I(_VAL_) (REG32(ADR_PAD18)) = (((_VAL_) << 4) | ((REG32(ADR_PAD18)) & 0xffffffcf))
++#define SET_PAD18_OD(_VAL_) (REG32(ADR_PAD18)) = (((_VAL_) << 8) | ((REG32(ADR_PAD18)) & 0xfffffeff))
++#define SET_PAD18_SEL_O(_VAL_) (REG32(ADR_PAD18)) = (((_VAL_) << 12) | ((REG32(ADR_PAD18)) & 0xffffcfff))
++#define SET_TEST_4_ID(_VAL_) (REG32(ADR_PAD18)) = (((_VAL_) << 28) | ((REG32(ADR_PAD18)) & 0xefffffff))
++#define SET_PAD19_OE(_VAL_) (REG32(ADR_PAD19)) = (((_VAL_) << 0) | ((REG32(ADR_PAD19)) & 0xfffffffe))
++#define SET_PAD19_PE(_VAL_) (REG32(ADR_PAD19)) = (((_VAL_) << 1) | ((REG32(ADR_PAD19)) & 0xfffffffd))
++#define SET_PAD19_DS(_VAL_) (REG32(ADR_PAD19)) = (((_VAL_) << 2) | ((REG32(ADR_PAD19)) & 0xfffffffb))
++#define SET_PAD19_IE(_VAL_) (REG32(ADR_PAD19)) = (((_VAL_) << 3) | ((REG32(ADR_PAD19)) & 0xfffffff7))
++#define SET_PAD19_SEL_I(_VAL_) (REG32(ADR_PAD19)) = (((_VAL_) << 4) | ((REG32(ADR_PAD19)) & 0xffffffcf))
++#define SET_PAD19_OD(_VAL_) (REG32(ADR_PAD19)) = (((_VAL_) << 8) | ((REG32(ADR_PAD19)) & 0xfffffeff))
++#define SET_PAD19_SEL_O(_VAL_) (REG32(ADR_PAD19)) = (((_VAL_) << 12) | ((REG32(ADR_PAD19)) & 0xffff8fff))
++#define SET_SHORT_TO_20_ID(_VAL_) (REG32(ADR_PAD19)) = (((_VAL_) << 28) | ((REG32(ADR_PAD19)) & 0xefffffff))
++#define SET_PAD20_OE(_VAL_) (REG32(ADR_PAD20)) = (((_VAL_) << 0) | ((REG32(ADR_PAD20)) & 0xfffffffe))
++#define SET_PAD20_PE(_VAL_) (REG32(ADR_PAD20)) = (((_VAL_) << 1) | ((REG32(ADR_PAD20)) & 0xfffffffd))
++#define SET_PAD20_DS(_VAL_) (REG32(ADR_PAD20)) = (((_VAL_) << 2) | ((REG32(ADR_PAD20)) & 0xfffffffb))
++#define SET_PAD20_IE(_VAL_) (REG32(ADR_PAD20)) = (((_VAL_) << 3) | ((REG32(ADR_PAD20)) & 0xfffffff7))
++#define SET_PAD20_SEL_I(_VAL_) (REG32(ADR_PAD20)) = (((_VAL_) << 4) | ((REG32(ADR_PAD20)) & 0xffffff0f))
++#define SET_PAD20_OD(_VAL_) (REG32(ADR_PAD20)) = (((_VAL_) << 8) | ((REG32(ADR_PAD20)) & 0xfffffeff))
++#define SET_PAD20_SEL_O(_VAL_) (REG32(ADR_PAD20)) = (((_VAL_) << 12) | ((REG32(ADR_PAD20)) & 0xffffcfff))
++#define SET_STRAP0(_VAL_) (REG32(ADR_PAD20)) = (((_VAL_) << 27) | ((REG32(ADR_PAD20)) & 0xf7ffffff))
++#define SET_GPIO_TEST_1_ID(_VAL_) (REG32(ADR_PAD20)) = (((_VAL_) << 28) | ((REG32(ADR_PAD20)) & 0xefffffff))
++#define SET_PAD21_OE(_VAL_) (REG32(ADR_PAD21)) = (((_VAL_) << 0) | ((REG32(ADR_PAD21)) & 0xfffffffe))
++#define SET_PAD21_PE(_VAL_) (REG32(ADR_PAD21)) = (((_VAL_) << 1) | ((REG32(ADR_PAD21)) & 0xfffffffd))
++#define SET_PAD21_DS(_VAL_) (REG32(ADR_PAD21)) = (((_VAL_) << 2) | ((REG32(ADR_PAD21)) & 0xfffffffb))
++#define SET_PAD21_IE(_VAL_) (REG32(ADR_PAD21)) = (((_VAL_) << 3) | ((REG32(ADR_PAD21)) & 0xfffffff7))
++#define SET_PAD21_SEL_I(_VAL_) (REG32(ADR_PAD21)) = (((_VAL_) << 4) | ((REG32(ADR_PAD21)) & 0xffffff8f))
++#define SET_PAD21_OD(_VAL_) (REG32(ADR_PAD21)) = (((_VAL_) << 8) | ((REG32(ADR_PAD21)) & 0xfffffeff))
++#define SET_PAD21_SEL_O(_VAL_) (REG32(ADR_PAD21)) = (((_VAL_) << 12) | ((REG32(ADR_PAD21)) & 0xffffcfff))
++#define SET_STRAP3(_VAL_) (REG32(ADR_PAD21)) = (((_VAL_) << 27) | ((REG32(ADR_PAD21)) & 0xf7ffffff))
++#define SET_GPIO_TEST_2_ID(_VAL_) (REG32(ADR_PAD21)) = (((_VAL_) << 28) | ((REG32(ADR_PAD21)) & 0xefffffff))
++#define SET_PAD22_OE(_VAL_) (REG32(ADR_PAD22)) = (((_VAL_) << 0) | ((REG32(ADR_PAD22)) & 0xfffffffe))
++#define SET_PAD22_PE(_VAL_) (REG32(ADR_PAD22)) = (((_VAL_) << 1) | ((REG32(ADR_PAD22)) & 0xfffffffd))
++#define SET_PAD22_DS(_VAL_) (REG32(ADR_PAD22)) = (((_VAL_) << 2) | ((REG32(ADR_PAD22)) & 0xfffffffb))
++#define SET_PAD22_IE(_VAL_) (REG32(ADR_PAD22)) = (((_VAL_) << 3) | ((REG32(ADR_PAD22)) & 0xfffffff7))
++#define SET_PAD22_SEL_I(_VAL_) (REG32(ADR_PAD22)) = (((_VAL_) << 4) | ((REG32(ADR_PAD22)) & 0xffffff8f))
++#define SET_PAD22_OD(_VAL_) (REG32(ADR_PAD22)) = (((_VAL_) << 8) | ((REG32(ADR_PAD22)) & 0xfffffeff))
++#define SET_PAD22_SEL_O(_VAL_) (REG32(ADR_PAD22)) = (((_VAL_) << 12) | ((REG32(ADR_PAD22)) & 0xffff8fff))
++#define SET_PAD22_SEL_OE(_VAL_) (REG32(ADR_PAD22)) = (((_VAL_) << 20) | ((REG32(ADR_PAD22)) & 0xffefffff))
++#define SET_GPIO_TEST_3_ID(_VAL_) (REG32(ADR_PAD22)) = (((_VAL_) << 28) | ((REG32(ADR_PAD22)) & 0xefffffff))
++#define SET_PAD24_OE(_VAL_) (REG32(ADR_PAD24)) = (((_VAL_) << 0) | ((REG32(ADR_PAD24)) & 0xfffffffe))
++#define SET_PAD24_PE(_VAL_) (REG32(ADR_PAD24)) = (((_VAL_) << 1) | ((REG32(ADR_PAD24)) & 0xfffffffd))
++#define SET_PAD24_DS(_VAL_) (REG32(ADR_PAD24)) = (((_VAL_) << 2) | ((REG32(ADR_PAD24)) & 0xfffffffb))
++#define SET_PAD24_IE(_VAL_) (REG32(ADR_PAD24)) = (((_VAL_) << 3) | ((REG32(ADR_PAD24)) & 0xfffffff7))
++#define SET_PAD24_SEL_I(_VAL_) (REG32(ADR_PAD24)) = (((_VAL_) << 4) | ((REG32(ADR_PAD24)) & 0xffffffcf))
++#define SET_PAD24_OD(_VAL_) (REG32(ADR_PAD24)) = (((_VAL_) << 8) | ((REG32(ADR_PAD24)) & 0xfffffeff))
++#define SET_PAD24_SEL_O(_VAL_) (REG32(ADR_PAD24)) = (((_VAL_) << 12) | ((REG32(ADR_PAD24)) & 0xffff8fff))
++#define SET_GPIO_TEST_4_ID(_VAL_) (REG32(ADR_PAD24)) = (((_VAL_) << 28) | ((REG32(ADR_PAD24)) & 0xefffffff))
++#define SET_PAD25_OE(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 0) | ((REG32(ADR_PAD25)) & 0xfffffffe))
++#define SET_PAD25_PE(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 1) | ((REG32(ADR_PAD25)) & 0xfffffffd))
++#define SET_PAD25_DS(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 2) | ((REG32(ADR_PAD25)) & 0xfffffffb))
++#define SET_PAD25_IE(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 3) | ((REG32(ADR_PAD25)) & 0xfffffff7))
++#define SET_PAD25_SEL_I(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 4) | ((REG32(ADR_PAD25)) & 0xffffff8f))
++#define SET_PAD25_OD(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 8) | ((REG32(ADR_PAD25)) & 0xfffffeff))
++#define SET_PAD25_SEL_O(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 12) | ((REG32(ADR_PAD25)) & 0xffff8fff))
++#define SET_PAD25_SEL_OE(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 20) | ((REG32(ADR_PAD25)) & 0xffefffff))
++#define SET_STRAP1(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 27) | ((REG32(ADR_PAD25)) & 0xf7ffffff))
++#define SET_GPIO_1_ID(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 28) | ((REG32(ADR_PAD25)) & 0xefffffff))
++#define SET_PAD27_OE(_VAL_) (REG32(ADR_PAD27)) = (((_VAL_) << 0) | ((REG32(ADR_PAD27)) & 0xfffffffe))
++#define SET_PAD27_PE(_VAL_) (REG32(ADR_PAD27)) = (((_VAL_) << 1) | ((REG32(ADR_PAD27)) & 0xfffffffd))
++#define SET_PAD27_DS(_VAL_) (REG32(ADR_PAD27)) = (((_VAL_) << 2) | ((REG32(ADR_PAD27)) & 0xfffffffb))
++#define SET_PAD27_IE(_VAL_) (REG32(ADR_PAD27)) = (((_VAL_) << 3) | ((REG32(ADR_PAD27)) & 0xfffffff7))
++#define SET_PAD27_SEL_I(_VAL_) (REG32(ADR_PAD27)) = (((_VAL_) << 4) | ((REG32(ADR_PAD27)) & 0xffffff8f))
++#define SET_PAD27_OD(_VAL_) (REG32(ADR_PAD27)) = (((_VAL_) << 8) | ((REG32(ADR_PAD27)) & 0xfffffeff))
++#define SET_PAD27_SEL_O(_VAL_) (REG32(ADR_PAD27)) = (((_VAL_) << 12) | ((REG32(ADR_PAD27)) & 0xffff8fff))
++#define SET_GPIO_2_ID(_VAL_) (REG32(ADR_PAD27)) = (((_VAL_) << 28) | ((REG32(ADR_PAD27)) & 0xefffffff))
++#define SET_PAD28_OE(_VAL_) (REG32(ADR_PAD28)) = (((_VAL_) << 0) | ((REG32(ADR_PAD28)) & 0xfffffffe))
++#define SET_PAD28_PE(_VAL_) (REG32(ADR_PAD28)) = (((_VAL_) << 1) | ((REG32(ADR_PAD28)) & 0xfffffffd))
++#define SET_PAD28_DS(_VAL_) (REG32(ADR_PAD28)) = (((_VAL_) << 2) | ((REG32(ADR_PAD28)) & 0xfffffffb))
++#define SET_PAD28_IE(_VAL_) (REG32(ADR_PAD28)) = (((_VAL_) << 3) | ((REG32(ADR_PAD28)) & 0xfffffff7))
++#define SET_PAD28_SEL_I(_VAL_) (REG32(ADR_PAD28)) = (((_VAL_) << 4) | ((REG32(ADR_PAD28)) & 0xffffff8f))
++#define SET_PAD28_OD(_VAL_) (REG32(ADR_PAD28)) = (((_VAL_) << 8) | ((REG32(ADR_PAD28)) & 0xfffffeff))
++#define SET_PAD28_SEL_O(_VAL_) (REG32(ADR_PAD28)) = (((_VAL_) << 12) | ((REG32(ADR_PAD28)) & 0xffff0fff))
++#define SET_PAD28_SEL_OE(_VAL_) (REG32(ADR_PAD28)) = (((_VAL_) << 20) | ((REG32(ADR_PAD28)) & 0xffefffff))
++#define SET_GPIO_3_ID(_VAL_) (REG32(ADR_PAD28)) = (((_VAL_) << 28) | ((REG32(ADR_PAD28)) & 0xefffffff))
++#define SET_PAD29_OE(_VAL_) (REG32(ADR_PAD29)) = (((_VAL_) << 0) | ((REG32(ADR_PAD29)) & 0xfffffffe))
++#define SET_PAD29_PE(_VAL_) (REG32(ADR_PAD29)) = (((_VAL_) << 1) | ((REG32(ADR_PAD29)) & 0xfffffffd))
++#define SET_PAD29_DS(_VAL_) (REG32(ADR_PAD29)) = (((_VAL_) << 2) | ((REG32(ADR_PAD29)) & 0xfffffffb))
++#define SET_PAD29_IE(_VAL_) (REG32(ADR_PAD29)) = (((_VAL_) << 3) | ((REG32(ADR_PAD29)) & 0xfffffff7))
++#define SET_PAD29_SEL_I(_VAL_) (REG32(ADR_PAD29)) = (((_VAL_) << 4) | ((REG32(ADR_PAD29)) & 0xffffff8f))
++#define SET_PAD29_OD(_VAL_) (REG32(ADR_PAD29)) = (((_VAL_) << 8) | ((REG32(ADR_PAD29)) & 0xfffffeff))
++#define SET_PAD29_SEL_O(_VAL_) (REG32(ADR_PAD29)) = (((_VAL_) << 12) | ((REG32(ADR_PAD29)) & 0xffff8fff))
++#define SET_GPIO_TEST_5_ID(_VAL_) (REG32(ADR_PAD29)) = (((_VAL_) << 28) | ((REG32(ADR_PAD29)) & 0xefffffff))
++#define SET_PAD30_OE(_VAL_) (REG32(ADR_PAD30)) = (((_VAL_) << 0) | ((REG32(ADR_PAD30)) & 0xfffffffe))
++#define SET_PAD30_PE(_VAL_) (REG32(ADR_PAD30)) = (((_VAL_) << 1) | ((REG32(ADR_PAD30)) & 0xfffffffd))
++#define SET_PAD30_DS(_VAL_) (REG32(ADR_PAD30)) = (((_VAL_) << 2) | ((REG32(ADR_PAD30)) & 0xfffffffb))
++#define SET_PAD30_IE(_VAL_) (REG32(ADR_PAD30)) = (((_VAL_) << 3) | ((REG32(ADR_PAD30)) & 0xfffffff7))
++#define SET_PAD30_SEL_I(_VAL_) (REG32(ADR_PAD30)) = (((_VAL_) << 4) | ((REG32(ADR_PAD30)) & 0xffffffcf))
++#define SET_PAD30_OD(_VAL_) (REG32(ADR_PAD30)) = (((_VAL_) << 8) | ((REG32(ADR_PAD30)) & 0xfffffeff))
++#define SET_PAD30_SEL_O(_VAL_) (REG32(ADR_PAD30)) = (((_VAL_) << 12) | ((REG32(ADR_PAD30)) & 0xffffcfff))
++#define SET_TEST_6_ID(_VAL_) (REG32(ADR_PAD30)) = (((_VAL_) << 28) | ((REG32(ADR_PAD30)) & 0xefffffff))
++#define SET_PAD31_OE(_VAL_) (REG32(ADR_PAD31)) = (((_VAL_) << 0) | ((REG32(ADR_PAD31)) & 0xfffffffe))
++#define SET_PAD31_PE(_VAL_) (REG32(ADR_PAD31)) = (((_VAL_) << 1) | ((REG32(ADR_PAD31)) & 0xfffffffd))
++#define SET_PAD31_DS(_VAL_) (REG32(ADR_PAD31)) = (((_VAL_) << 2) | ((REG32(ADR_PAD31)) & 0xfffffffb))
++#define SET_PAD31_IE(_VAL_) (REG32(ADR_PAD31)) = (((_VAL_) << 3) | ((REG32(ADR_PAD31)) & 0xfffffff7))
++#define SET_PAD31_SEL_I(_VAL_) (REG32(ADR_PAD31)) = (((_VAL_) << 4) | ((REG32(ADR_PAD31)) & 0xffffffcf))
++#define SET_PAD31_OD(_VAL_) (REG32(ADR_PAD31)) = (((_VAL_) << 8) | ((REG32(ADR_PAD31)) & 0xfffffeff))
++#define SET_PAD31_SEL_O(_VAL_) (REG32(ADR_PAD31)) = (((_VAL_) << 12) | ((REG32(ADR_PAD31)) & 0xffffcfff))
++#define SET_TEST_7_ID(_VAL_) (REG32(ADR_PAD31)) = (((_VAL_) << 28) | ((REG32(ADR_PAD31)) & 0xefffffff))
++#define SET_PAD32_OE(_VAL_) (REG32(ADR_PAD32)) = (((_VAL_) << 0) | ((REG32(ADR_PAD32)) & 0xfffffffe))
++#define SET_PAD32_PE(_VAL_) (REG32(ADR_PAD32)) = (((_VAL_) << 1) | ((REG32(ADR_PAD32)) & 0xfffffffd))
++#define SET_PAD32_DS(_VAL_) (REG32(ADR_PAD32)) = (((_VAL_) << 2) | ((REG32(ADR_PAD32)) & 0xfffffffb))
++#define SET_PAD32_IE(_VAL_) (REG32(ADR_PAD32)) = (((_VAL_) << 3) | ((REG32(ADR_PAD32)) & 0xfffffff7))
++#define SET_PAD32_SEL_I(_VAL_) (REG32(ADR_PAD32)) = (((_VAL_) << 4) | ((REG32(ADR_PAD32)) & 0xffffffcf))
++#define SET_PAD32_OD(_VAL_) (REG32(ADR_PAD32)) = (((_VAL_) << 8) | ((REG32(ADR_PAD32)) & 0xfffffeff))
++#define SET_PAD32_SEL_O(_VAL_) (REG32(ADR_PAD32)) = (((_VAL_) << 12) | ((REG32(ADR_PAD32)) & 0xffffcfff))
++#define SET_TEST_8_ID(_VAL_) (REG32(ADR_PAD32)) = (((_VAL_) << 28) | ((REG32(ADR_PAD32)) & 0xefffffff))
++#define SET_PAD33_OE(_VAL_) (REG32(ADR_PAD33)) = (((_VAL_) << 0) | ((REG32(ADR_PAD33)) & 0xfffffffe))
++#define SET_PAD33_PE(_VAL_) (REG32(ADR_PAD33)) = (((_VAL_) << 1) | ((REG32(ADR_PAD33)) & 0xfffffffd))
++#define SET_PAD33_DS(_VAL_) (REG32(ADR_PAD33)) = (((_VAL_) << 2) | ((REG32(ADR_PAD33)) & 0xfffffffb))
++#define SET_PAD33_IE(_VAL_) (REG32(ADR_PAD33)) = (((_VAL_) << 3) | ((REG32(ADR_PAD33)) & 0xfffffff7))
++#define SET_PAD33_SEL_I(_VAL_) (REG32(ADR_PAD33)) = (((_VAL_) << 4) | ((REG32(ADR_PAD33)) & 0xffffffcf))
++#define SET_PAD33_OD(_VAL_) (REG32(ADR_PAD33)) = (((_VAL_) << 8) | ((REG32(ADR_PAD33)) & 0xfffffeff))
++#define SET_PAD33_SEL_O(_VAL_) (REG32(ADR_PAD33)) = (((_VAL_) << 12) | ((REG32(ADR_PAD33)) & 0xffffcfff))
++#define SET_TEST_9_ID(_VAL_) (REG32(ADR_PAD33)) = (((_VAL_) << 28) | ((REG32(ADR_PAD33)) & 0xefffffff))
++#define SET_PAD34_OE(_VAL_) (REG32(ADR_PAD34)) = (((_VAL_) << 0) | ((REG32(ADR_PAD34)) & 0xfffffffe))
++#define SET_PAD34_PE(_VAL_) (REG32(ADR_PAD34)) = (((_VAL_) << 1) | ((REG32(ADR_PAD34)) & 0xfffffffd))
++#define SET_PAD34_DS(_VAL_) (REG32(ADR_PAD34)) = (((_VAL_) << 2) | ((REG32(ADR_PAD34)) & 0xfffffffb))
++#define SET_PAD34_IE(_VAL_) (REG32(ADR_PAD34)) = (((_VAL_) << 3) | ((REG32(ADR_PAD34)) & 0xfffffff7))
++#define SET_PAD34_SEL_I(_VAL_) (REG32(ADR_PAD34)) = (((_VAL_) << 4) | ((REG32(ADR_PAD34)) & 0xffffffcf))
++#define SET_PAD34_OD(_VAL_) (REG32(ADR_PAD34)) = (((_VAL_) << 8) | ((REG32(ADR_PAD34)) & 0xfffffeff))
++#define SET_PAD34_SEL_O(_VAL_) (REG32(ADR_PAD34)) = (((_VAL_) << 12) | ((REG32(ADR_PAD34)) & 0xffffcfff))
++#define SET_TEST_10_ID(_VAL_) (REG32(ADR_PAD34)) = (((_VAL_) << 28) | ((REG32(ADR_PAD34)) & 0xefffffff))
++#define SET_PAD42_OE(_VAL_) (REG32(ADR_PAD42)) = (((_VAL_) << 0) | ((REG32(ADR_PAD42)) & 0xfffffffe))
++#define SET_PAD42_PE(_VAL_) (REG32(ADR_PAD42)) = (((_VAL_) << 1) | ((REG32(ADR_PAD42)) & 0xfffffffd))
++#define SET_PAD42_DS(_VAL_) (REG32(ADR_PAD42)) = (((_VAL_) << 2) | ((REG32(ADR_PAD42)) & 0xfffffffb))
++#define SET_PAD42_IE(_VAL_) (REG32(ADR_PAD42)) = (((_VAL_) << 3) | ((REG32(ADR_PAD42)) & 0xfffffff7))
++#define SET_PAD42_SEL_I(_VAL_) (REG32(ADR_PAD42)) = (((_VAL_) << 4) | ((REG32(ADR_PAD42)) & 0xffffffcf))
++#define SET_PAD42_OD(_VAL_) (REG32(ADR_PAD42)) = (((_VAL_) << 8) | ((REG32(ADR_PAD42)) & 0xfffffeff))
++#define SET_PAD42_SEL_O(_VAL_) (REG32(ADR_PAD42)) = (((_VAL_) << 12) | ((REG32(ADR_PAD42)) & 0xffffefff))
++#define SET_TEST_11_ID(_VAL_) (REG32(ADR_PAD42)) = (((_VAL_) << 28) | ((REG32(ADR_PAD42)) & 0xefffffff))
++#define SET_PAD43_OE(_VAL_) (REG32(ADR_PAD43)) = (((_VAL_) << 0) | ((REG32(ADR_PAD43)) & 0xfffffffe))
++#define SET_PAD43_PE(_VAL_) (REG32(ADR_PAD43)) = (((_VAL_) << 1) | ((REG32(ADR_PAD43)) & 0xfffffffd))
++#define SET_PAD43_DS(_VAL_) (REG32(ADR_PAD43)) = (((_VAL_) << 2) | ((REG32(ADR_PAD43)) & 0xfffffffb))
++#define SET_PAD43_IE(_VAL_) (REG32(ADR_PAD43)) = (((_VAL_) << 3) | ((REG32(ADR_PAD43)) & 0xfffffff7))
++#define SET_PAD43_SEL_I(_VAL_) (REG32(ADR_PAD43)) = (((_VAL_) << 4) | ((REG32(ADR_PAD43)) & 0xffffffcf))
++#define SET_PAD43_OD(_VAL_) (REG32(ADR_PAD43)) = (((_VAL_) << 8) | ((REG32(ADR_PAD43)) & 0xfffffeff))
++#define SET_PAD43_SEL_O(_VAL_) (REG32(ADR_PAD43)) = (((_VAL_) << 12) | ((REG32(ADR_PAD43)) & 0xffffefff))
++#define SET_TEST_12_ID(_VAL_) (REG32(ADR_PAD43)) = (((_VAL_) << 28) | ((REG32(ADR_PAD43)) & 0xefffffff))
++#define SET_PAD44_OE(_VAL_) (REG32(ADR_PAD44)) = (((_VAL_) << 0) | ((REG32(ADR_PAD44)) & 0xfffffffe))
++#define SET_PAD44_PE(_VAL_) (REG32(ADR_PAD44)) = (((_VAL_) << 1) | ((REG32(ADR_PAD44)) & 0xfffffffd))
++#define SET_PAD44_DS(_VAL_) (REG32(ADR_PAD44)) = (((_VAL_) << 2) | ((REG32(ADR_PAD44)) & 0xfffffffb))
++#define SET_PAD44_IE(_VAL_) (REG32(ADR_PAD44)) = (((_VAL_) << 3) | ((REG32(ADR_PAD44)) & 0xfffffff7))
++#define SET_PAD44_SEL_I(_VAL_) (REG32(ADR_PAD44)) = (((_VAL_) << 4) | ((REG32(ADR_PAD44)) & 0xffffffcf))
++#define SET_PAD44_OD(_VAL_) (REG32(ADR_PAD44)) = (((_VAL_) << 8) | ((REG32(ADR_PAD44)) & 0xfffffeff))
++#define SET_PAD44_SEL_O(_VAL_) (REG32(ADR_PAD44)) = (((_VAL_) << 12) | ((REG32(ADR_PAD44)) & 0xffffcfff))
++#define SET_TEST_13_ID(_VAL_) (REG32(ADR_PAD44)) = (((_VAL_) << 28) | ((REG32(ADR_PAD44)) & 0xefffffff))
++#define SET_PAD45_OE(_VAL_) (REG32(ADR_PAD45)) = (((_VAL_) << 0) | ((REG32(ADR_PAD45)) & 0xfffffffe))
++#define SET_PAD45_PE(_VAL_) (REG32(ADR_PAD45)) = (((_VAL_) << 1) | ((REG32(ADR_PAD45)) & 0xfffffffd))
++#define SET_PAD45_DS(_VAL_) (REG32(ADR_PAD45)) = (((_VAL_) << 2) | ((REG32(ADR_PAD45)) & 0xfffffffb))
++#define SET_PAD45_IE(_VAL_) (REG32(ADR_PAD45)) = (((_VAL_) << 3) | ((REG32(ADR_PAD45)) & 0xfffffff7))
++#define SET_PAD45_SEL_I(_VAL_) (REG32(ADR_PAD45)) = (((_VAL_) << 4) | ((REG32(ADR_PAD45)) & 0xffffffcf))
++#define SET_PAD45_OD(_VAL_) (REG32(ADR_PAD45)) = (((_VAL_) << 8) | ((REG32(ADR_PAD45)) & 0xfffffeff))
++#define SET_PAD45_SEL_O(_VAL_) (REG32(ADR_PAD45)) = (((_VAL_) << 12) | ((REG32(ADR_PAD45)) & 0xffffcfff))
++#define SET_TEST_14_ID(_VAL_) (REG32(ADR_PAD45)) = (((_VAL_) << 28) | ((REG32(ADR_PAD45)) & 0xefffffff))
++#define SET_PAD46_OE(_VAL_) (REG32(ADR_PAD46)) = (((_VAL_) << 0) | ((REG32(ADR_PAD46)) & 0xfffffffe))
++#define SET_PAD46_PE(_VAL_) (REG32(ADR_PAD46)) = (((_VAL_) << 1) | ((REG32(ADR_PAD46)) & 0xfffffffd))
++#define SET_PAD46_DS(_VAL_) (REG32(ADR_PAD46)) = (((_VAL_) << 2) | ((REG32(ADR_PAD46)) & 0xfffffffb))
++#define SET_PAD46_IE(_VAL_) (REG32(ADR_PAD46)) = (((_VAL_) << 3) | ((REG32(ADR_PAD46)) & 0xfffffff7))
++#define SET_PAD46_SEL_I(_VAL_) (REG32(ADR_PAD46)) = (((_VAL_) << 4) | ((REG32(ADR_PAD46)) & 0xffffffcf))
++#define SET_PAD46_OD(_VAL_) (REG32(ADR_PAD46)) = (((_VAL_) << 8) | ((REG32(ADR_PAD46)) & 0xfffffeff))
++#define SET_PAD46_SEL_O(_VAL_) (REG32(ADR_PAD46)) = (((_VAL_) << 12) | ((REG32(ADR_PAD46)) & 0xffffcfff))
++#define SET_TEST_15_ID(_VAL_) (REG32(ADR_PAD46)) = (((_VAL_) << 28) | ((REG32(ADR_PAD46)) & 0xefffffff))
++#define SET_PAD47_OE(_VAL_) (REG32(ADR_PAD47)) = (((_VAL_) << 0) | ((REG32(ADR_PAD47)) & 0xfffffffe))
++#define SET_PAD47_PE(_VAL_) (REG32(ADR_PAD47)) = (((_VAL_) << 1) | ((REG32(ADR_PAD47)) & 0xfffffffd))
++#define SET_PAD47_DS(_VAL_) (REG32(ADR_PAD47)) = (((_VAL_) << 2) | ((REG32(ADR_PAD47)) & 0xfffffffb))
++#define SET_PAD47_SEL_I(_VAL_) (REG32(ADR_PAD47)) = (((_VAL_) << 4) | ((REG32(ADR_PAD47)) & 0xffffffcf))
++#define SET_PAD47_OD(_VAL_) (REG32(ADR_PAD47)) = (((_VAL_) << 8) | ((REG32(ADR_PAD47)) & 0xfffffeff))
++#define SET_PAD47_SEL_O(_VAL_) (REG32(ADR_PAD47)) = (((_VAL_) << 12) | ((REG32(ADR_PAD47)) & 0xffffcfff))
++#define SET_PAD47_SEL_OE(_VAL_) (REG32(ADR_PAD47)) = (((_VAL_) << 20) | ((REG32(ADR_PAD47)) & 0xffefffff))
++#define SET_GPIO_9_ID(_VAL_) (REG32(ADR_PAD47)) = (((_VAL_) << 28) | ((REG32(ADR_PAD47)) & 0xefffffff))
++#define SET_PAD48_OE(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 0) | ((REG32(ADR_PAD48)) & 0xfffffffe))
++#define SET_PAD48_PE(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 1) | ((REG32(ADR_PAD48)) & 0xfffffffd))
++#define SET_PAD48_DS(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 2) | ((REG32(ADR_PAD48)) & 0xfffffffb))
++#define SET_PAD48_IE(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 3) | ((REG32(ADR_PAD48)) & 0xfffffff7))
++#define SET_PAD48_SEL_I(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 4) | ((REG32(ADR_PAD48)) & 0xffffff8f))
++#define SET_PAD48_OD(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 8) | ((REG32(ADR_PAD48)) & 0xfffffeff))
++#define SET_PAD48_PE_SEL(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 11) | ((REG32(ADR_PAD48)) & 0xfffff7ff))
++#define SET_PAD48_SEL_O(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 12) | ((REG32(ADR_PAD48)) & 0xffffcfff))
++#define SET_PAD48_SEL_OE(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 20) | ((REG32(ADR_PAD48)) & 0xffefffff))
++#define SET_GPIO_10_ID(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 28) | ((REG32(ADR_PAD48)) & 0xefffffff))
++#define SET_PAD49_OE(_VAL_) (REG32(ADR_PAD49)) = (((_VAL_) << 0) | ((REG32(ADR_PAD49)) & 0xfffffffe))
++#define SET_PAD49_PE(_VAL_) (REG32(ADR_PAD49)) = (((_VAL_) << 1) | ((REG32(ADR_PAD49)) & 0xfffffffd))
++#define SET_PAD49_DS(_VAL_) (REG32(ADR_PAD49)) = (((_VAL_) << 2) | ((REG32(ADR_PAD49)) & 0xfffffffb))
++#define SET_PAD49_IE(_VAL_) (REG32(ADR_PAD49)) = (((_VAL_) << 3) | ((REG32(ADR_PAD49)) & 0xfffffff7))
++#define SET_PAD49_SEL_I(_VAL_) (REG32(ADR_PAD49)) = (((_VAL_) << 4) | ((REG32(ADR_PAD49)) & 0xffffff8f))
++#define SET_PAD49_OD(_VAL_) (REG32(ADR_PAD49)) = (((_VAL_) << 8) | ((REG32(ADR_PAD49)) & 0xfffffeff))
++#define SET_PAD49_SEL_O(_VAL_) (REG32(ADR_PAD49)) = (((_VAL_) << 12) | ((REG32(ADR_PAD49)) & 0xffffcfff))
++#define SET_PAD49_SEL_OE(_VAL_) (REG32(ADR_PAD49)) = (((_VAL_) << 20) | ((REG32(ADR_PAD49)) & 0xffefffff))
++#define SET_GPIO_11_ID(_VAL_) (REG32(ADR_PAD49)) = (((_VAL_) << 28) | ((REG32(ADR_PAD49)) & 0xefffffff))
++#define SET_PAD50_OE(_VAL_) (REG32(ADR_PAD50)) = (((_VAL_) << 0) | ((REG32(ADR_PAD50)) & 0xfffffffe))
++#define SET_PAD50_PE(_VAL_) (REG32(ADR_PAD50)) = (((_VAL_) << 1) | ((REG32(ADR_PAD50)) & 0xfffffffd))
++#define SET_PAD50_DS(_VAL_) (REG32(ADR_PAD50)) = (((_VAL_) << 2) | ((REG32(ADR_PAD50)) & 0xfffffffb))
++#define SET_PAD50_IE(_VAL_) (REG32(ADR_PAD50)) = (((_VAL_) << 3) | ((REG32(ADR_PAD50)) & 0xfffffff7))
++#define SET_PAD50_SEL_I(_VAL_) (REG32(ADR_PAD50)) = (((_VAL_) << 4) | ((REG32(ADR_PAD50)) & 0xffffff8f))
++#define SET_PAD50_OD(_VAL_) (REG32(ADR_PAD50)) = (((_VAL_) << 8) | ((REG32(ADR_PAD50)) & 0xfffffeff))
++#define SET_PAD50_SEL_O(_VAL_) (REG32(ADR_PAD50)) = (((_VAL_) << 12) | ((REG32(ADR_PAD50)) & 0xffffcfff))
++#define SET_PAD50_SEL_OE(_VAL_) (REG32(ADR_PAD50)) = (((_VAL_) << 20) | ((REG32(ADR_PAD50)) & 0xffefffff))
++#define SET_GPIO_12_ID(_VAL_) (REG32(ADR_PAD50)) = (((_VAL_) << 28) | ((REG32(ADR_PAD50)) & 0xefffffff))
++#define SET_PAD51_OE(_VAL_) (REG32(ADR_PAD51)) = (((_VAL_) << 0) | ((REG32(ADR_PAD51)) & 0xfffffffe))
++#define SET_PAD51_PE(_VAL_) (REG32(ADR_PAD51)) = (((_VAL_) << 1) | ((REG32(ADR_PAD51)) & 0xfffffffd))
++#define SET_PAD51_DS(_VAL_) (REG32(ADR_PAD51)) = (((_VAL_) << 2) | ((REG32(ADR_PAD51)) & 0xfffffffb))
++#define SET_PAD51_IE(_VAL_) (REG32(ADR_PAD51)) = (((_VAL_) << 3) | ((REG32(ADR_PAD51)) & 0xfffffff7))
++#define SET_PAD51_SEL_I(_VAL_) (REG32(ADR_PAD51)) = (((_VAL_) << 4) | ((REG32(ADR_PAD51)) & 0xffffffcf))
++#define SET_PAD51_OD(_VAL_) (REG32(ADR_PAD51)) = (((_VAL_) << 8) | ((REG32(ADR_PAD51)) & 0xfffffeff))
++#define SET_PAD51_SEL_O(_VAL_) (REG32(ADR_PAD51)) = (((_VAL_) << 12) | ((REG32(ADR_PAD51)) & 0xffffefff))
++#define SET_PAD51_SEL_OE(_VAL_) (REG32(ADR_PAD51)) = (((_VAL_) << 20) | ((REG32(ADR_PAD51)) & 0xffefffff))
++#define SET_GPIO_13_ID(_VAL_) (REG32(ADR_PAD51)) = (((_VAL_) << 28) | ((REG32(ADR_PAD51)) & 0xefffffff))
++#define SET_PAD52_OE(_VAL_) (REG32(ADR_PAD52)) = (((_VAL_) << 0) | ((REG32(ADR_PAD52)) & 0xfffffffe))
++#define SET_PAD52_PE(_VAL_) (REG32(ADR_PAD52)) = (((_VAL_) << 1) | ((REG32(ADR_PAD52)) & 0xfffffffd))
++#define SET_PAD52_DS(_VAL_) (REG32(ADR_PAD52)) = (((_VAL_) << 2) | ((REG32(ADR_PAD52)) & 0xfffffffb))
++#define SET_PAD52_SEL_I(_VAL_) (REG32(ADR_PAD52)) = (((_VAL_) << 4) | ((REG32(ADR_PAD52)) & 0xffffffcf))
++#define SET_PAD52_OD(_VAL_) (REG32(ADR_PAD52)) = (((_VAL_) << 8) | ((REG32(ADR_PAD52)) & 0xfffffeff))
++#define SET_PAD52_SEL_O(_VAL_) (REG32(ADR_PAD52)) = (((_VAL_) << 12) | ((REG32(ADR_PAD52)) & 0xffffefff))
++#define SET_PAD52_SEL_OE(_VAL_) (REG32(ADR_PAD52)) = (((_VAL_) << 20) | ((REG32(ADR_PAD52)) & 0xffefffff))
++#define SET_GPIO_14_ID(_VAL_) (REG32(ADR_PAD52)) = (((_VAL_) << 28) | ((REG32(ADR_PAD52)) & 0xefffffff))
++#define SET_PAD53_OE(_VAL_) (REG32(ADR_PAD53)) = (((_VAL_) << 0) | ((REG32(ADR_PAD53)) & 0xfffffffe))
++#define SET_PAD53_PE(_VAL_) (REG32(ADR_PAD53)) = (((_VAL_) << 1) | ((REG32(ADR_PAD53)) & 0xfffffffd))
++#define SET_PAD53_DS(_VAL_) (REG32(ADR_PAD53)) = (((_VAL_) << 2) | ((REG32(ADR_PAD53)) & 0xfffffffb))
++#define SET_PAD53_IE(_VAL_) (REG32(ADR_PAD53)) = (((_VAL_) << 3) | ((REG32(ADR_PAD53)) & 0xfffffff7))
++#define SET_PAD53_SEL_I(_VAL_) (REG32(ADR_PAD53)) = (((_VAL_) << 4) | ((REG32(ADR_PAD53)) & 0xffffffcf))
++#define SET_PAD53_OD(_VAL_) (REG32(ADR_PAD53)) = (((_VAL_) << 8) | ((REG32(ADR_PAD53)) & 0xfffffeff))
++#define SET_PAD53_SEL_O(_VAL_) (REG32(ADR_PAD53)) = (((_VAL_) << 12) | ((REG32(ADR_PAD53)) & 0xffffefff))
++#define SET_JTAG_TMS_ID(_VAL_) (REG32(ADR_PAD53)) = (((_VAL_) << 28) | ((REG32(ADR_PAD53)) & 0xefffffff))
++#define SET_PAD54_OE(_VAL_) (REG32(ADR_PAD54)) = (((_VAL_) << 0) | ((REG32(ADR_PAD54)) & 0xfffffffe))
++#define SET_PAD54_PE(_VAL_) (REG32(ADR_PAD54)) = (((_VAL_) << 1) | ((REG32(ADR_PAD54)) & 0xfffffffd))
++#define SET_PAD54_DS(_VAL_) (REG32(ADR_PAD54)) = (((_VAL_) << 2) | ((REG32(ADR_PAD54)) & 0xfffffffb))
++#define SET_PAD54_OD(_VAL_) (REG32(ADR_PAD54)) = (((_VAL_) << 8) | ((REG32(ADR_PAD54)) & 0xfffffeff))
++#define SET_PAD54_SEL_O(_VAL_) (REG32(ADR_PAD54)) = (((_VAL_) << 12) | ((REG32(ADR_PAD54)) & 0xffffcfff))
++#define SET_JTAG_TCK_ID(_VAL_) (REG32(ADR_PAD54)) = (((_VAL_) << 28) | ((REG32(ADR_PAD54)) & 0xefffffff))
++#define SET_PAD56_PE(_VAL_) (REG32(ADR_PAD56)) = (((_VAL_) << 1) | ((REG32(ADR_PAD56)) & 0xfffffffd))
++#define SET_PAD56_DS(_VAL_) (REG32(ADR_PAD56)) = (((_VAL_) << 2) | ((REG32(ADR_PAD56)) & 0xfffffffb))
++#define SET_PAD56_SEL_I(_VAL_) (REG32(ADR_PAD56)) = (((_VAL_) << 4) | ((REG32(ADR_PAD56)) & 0xffffffef))
++#define SET_PAD56_OD(_VAL_) (REG32(ADR_PAD56)) = (((_VAL_) << 8) | ((REG32(ADR_PAD56)) & 0xfffffeff))
++#define SET_JTAG_TDI_ID(_VAL_) (REG32(ADR_PAD56)) = (((_VAL_) << 28) | ((REG32(ADR_PAD56)) & 0xefffffff))
++#define SET_PAD57_OE(_VAL_) (REG32(ADR_PAD57)) = (((_VAL_) << 0) | ((REG32(ADR_PAD57)) & 0xfffffffe))
++#define SET_PAD57_PE(_VAL_) (REG32(ADR_PAD57)) = (((_VAL_) << 1) | ((REG32(ADR_PAD57)) & 0xfffffffd))
++#define SET_PAD57_DS(_VAL_) (REG32(ADR_PAD57)) = (((_VAL_) << 2) | ((REG32(ADR_PAD57)) & 0xfffffffb))
++#define SET_PAD57_IE(_VAL_) (REG32(ADR_PAD57)) = (((_VAL_) << 3) | ((REG32(ADR_PAD57)) & 0xfffffff7))
++#define SET_PAD57_SEL_I(_VAL_) (REG32(ADR_PAD57)) = (((_VAL_) << 4) | ((REG32(ADR_PAD57)) & 0xffffffcf))
++#define SET_PAD57_OD(_VAL_) (REG32(ADR_PAD57)) = (((_VAL_) << 8) | ((REG32(ADR_PAD57)) & 0xfffffeff))
++#define SET_PAD57_SEL_O(_VAL_) (REG32(ADR_PAD57)) = (((_VAL_) << 12) | ((REG32(ADR_PAD57)) & 0xffffcfff))
++#define SET_PAD57_SEL_OE(_VAL_) (REG32(ADR_PAD57)) = (((_VAL_) << 20) | ((REG32(ADR_PAD57)) & 0xffefffff))
++#define SET_JTAG_TDO_ID(_VAL_) (REG32(ADR_PAD57)) = (((_VAL_) << 28) | ((REG32(ADR_PAD57)) & 0xefffffff))
++#define SET_PAD58_OE(_VAL_) (REG32(ADR_PAD58)) = (((_VAL_) << 0) | ((REG32(ADR_PAD58)) & 0xfffffffe))
++#define SET_PAD58_PE(_VAL_) (REG32(ADR_PAD58)) = (((_VAL_) << 1) | ((REG32(ADR_PAD58)) & 0xfffffffd))
++#define SET_PAD58_DS(_VAL_) (REG32(ADR_PAD58)) = (((_VAL_) << 2) | ((REG32(ADR_PAD58)) & 0xfffffffb))
++#define SET_PAD58_IE(_VAL_) (REG32(ADR_PAD58)) = (((_VAL_) << 3) | ((REG32(ADR_PAD58)) & 0xfffffff7))
++#define SET_PAD58_SEL_I(_VAL_) (REG32(ADR_PAD58)) = (((_VAL_) << 4) | ((REG32(ADR_PAD58)) & 0xffffffcf))
++#define SET_PAD58_OD(_VAL_) (REG32(ADR_PAD58)) = (((_VAL_) << 8) | ((REG32(ADR_PAD58)) & 0xfffffeff))
++#define SET_PAD58_SEL_O(_VAL_) (REG32(ADR_PAD58)) = (((_VAL_) << 12) | ((REG32(ADR_PAD58)) & 0xffffefff))
++#define SET_TEST_16_ID(_VAL_) (REG32(ADR_PAD58)) = (((_VAL_) << 28) | ((REG32(ADR_PAD58)) & 0xefffffff))
++#define SET_PAD59_OE(_VAL_) (REG32(ADR_PAD59)) = (((_VAL_) << 0) | ((REG32(ADR_PAD59)) & 0xfffffffe))
++#define SET_PAD59_PE(_VAL_) (REG32(ADR_PAD59)) = (((_VAL_) << 1) | ((REG32(ADR_PAD59)) & 0xfffffffd))
++#define SET_PAD59_DS(_VAL_) (REG32(ADR_PAD59)) = (((_VAL_) << 2) | ((REG32(ADR_PAD59)) & 0xfffffffb))
++#define SET_PAD59_IE(_VAL_) (REG32(ADR_PAD59)) = (((_VAL_) << 3) | ((REG32(ADR_PAD59)) & 0xfffffff7))
++#define SET_PAD59_SEL_I(_VAL_) (REG32(ADR_PAD59)) = (((_VAL_) << 4) | ((REG32(ADR_PAD59)) & 0xffffffcf))
++#define SET_PAD59_OD(_VAL_) (REG32(ADR_PAD59)) = (((_VAL_) << 8) | ((REG32(ADR_PAD59)) & 0xfffffeff))
++#define SET_PAD59_SEL_O(_VAL_) (REG32(ADR_PAD59)) = (((_VAL_) << 12) | ((REG32(ADR_PAD59)) & 0xffffefff))
++#define SET_TEST_17_ID(_VAL_) (REG32(ADR_PAD59)) = (((_VAL_) << 28) | ((REG32(ADR_PAD59)) & 0xefffffff))
++#define SET_PAD60_OE(_VAL_) (REG32(ADR_PAD60)) = (((_VAL_) << 0) | ((REG32(ADR_PAD60)) & 0xfffffffe))
++#define SET_PAD60_PE(_VAL_) (REG32(ADR_PAD60)) = (((_VAL_) << 1) | ((REG32(ADR_PAD60)) & 0xfffffffd))
++#define SET_PAD60_DS(_VAL_) (REG32(ADR_PAD60)) = (((_VAL_) << 2) | ((REG32(ADR_PAD60)) & 0xfffffffb))
++#define SET_PAD60_IE(_VAL_) (REG32(ADR_PAD60)) = (((_VAL_) << 3) | ((REG32(ADR_PAD60)) & 0xfffffff7))
++#define SET_PAD60_SEL_I(_VAL_) (REG32(ADR_PAD60)) = (((_VAL_) << 4) | ((REG32(ADR_PAD60)) & 0xffffffcf))
++#define SET_PAD60_OD(_VAL_) (REG32(ADR_PAD60)) = (((_VAL_) << 8) | ((REG32(ADR_PAD60)) & 0xfffffeff))
++#define SET_PAD60_SEL_O(_VAL_) (REG32(ADR_PAD60)) = (((_VAL_) << 12) | ((REG32(ADR_PAD60)) & 0xffffefff))
++#define SET_TEST_18_ID(_VAL_) (REG32(ADR_PAD60)) = (((_VAL_) << 28) | ((REG32(ADR_PAD60)) & 0xefffffff))
++#define SET_PAD61_OE(_VAL_) (REG32(ADR_PAD61)) = (((_VAL_) << 0) | ((REG32(ADR_PAD61)) & 0xfffffffe))
++#define SET_PAD61_PE(_VAL_) (REG32(ADR_PAD61)) = (((_VAL_) << 1) | ((REG32(ADR_PAD61)) & 0xfffffffd))
++#define SET_PAD61_DS(_VAL_) (REG32(ADR_PAD61)) = (((_VAL_) << 2) | ((REG32(ADR_PAD61)) & 0xfffffffb))
++#define SET_PAD61_IE(_VAL_) (REG32(ADR_PAD61)) = (((_VAL_) << 3) | ((REG32(ADR_PAD61)) & 0xfffffff7))
++#define SET_PAD61_SEL_I(_VAL_) (REG32(ADR_PAD61)) = (((_VAL_) << 4) | ((REG32(ADR_PAD61)) & 0xffffffef))
++#define SET_PAD61_OD(_VAL_) (REG32(ADR_PAD61)) = (((_VAL_) << 8) | ((REG32(ADR_PAD61)) & 0xfffffeff))
++#define SET_PAD61_SEL_O(_VAL_) (REG32(ADR_PAD61)) = (((_VAL_) << 12) | ((REG32(ADR_PAD61)) & 0xffffcfff))
++#define SET_TEST_19_ID(_VAL_) (REG32(ADR_PAD61)) = (((_VAL_) << 28) | ((REG32(ADR_PAD61)) & 0xefffffff))
++#define SET_PAD62_OE(_VAL_) (REG32(ADR_PAD62)) = (((_VAL_) << 0) | ((REG32(ADR_PAD62)) & 0xfffffffe))
++#define SET_PAD62_PE(_VAL_) (REG32(ADR_PAD62)) = (((_VAL_) << 1) | ((REG32(ADR_PAD62)) & 0xfffffffd))
++#define SET_PAD62_DS(_VAL_) (REG32(ADR_PAD62)) = (((_VAL_) << 2) | ((REG32(ADR_PAD62)) & 0xfffffffb))
++#define SET_PAD62_IE(_VAL_) (REG32(ADR_PAD62)) = (((_VAL_) << 3) | ((REG32(ADR_PAD62)) & 0xfffffff7))
++#define SET_PAD62_SEL_I(_VAL_) (REG32(ADR_PAD62)) = (((_VAL_) << 4) | ((REG32(ADR_PAD62)) & 0xffffffef))
++#define SET_PAD62_OD(_VAL_) (REG32(ADR_PAD62)) = (((_VAL_) << 8) | ((REG32(ADR_PAD62)) & 0xfffffeff))
++#define SET_PAD62_SEL_O(_VAL_) (REG32(ADR_PAD62)) = (((_VAL_) << 12) | ((REG32(ADR_PAD62)) & 0xffffefff))
++#define SET_TEST_20_ID(_VAL_) (REG32(ADR_PAD62)) = (((_VAL_) << 28) | ((REG32(ADR_PAD62)) & 0xefffffff))
++#define SET_PAD64_OE(_VAL_) (REG32(ADR_PAD64)) = (((_VAL_) << 0) | ((REG32(ADR_PAD64)) & 0xfffffffe))
++#define SET_PAD64_PE(_VAL_) (REG32(ADR_PAD64)) = (((_VAL_) << 1) | ((REG32(ADR_PAD64)) & 0xfffffffd))
++#define SET_PAD64_DS(_VAL_) (REG32(ADR_PAD64)) = (((_VAL_) << 2) | ((REG32(ADR_PAD64)) & 0xfffffffb))
++#define SET_PAD64_IE(_VAL_) (REG32(ADR_PAD64)) = (((_VAL_) << 3) | ((REG32(ADR_PAD64)) & 0xfffffff7))
++#define SET_PAD64_SEL_I(_VAL_) (REG32(ADR_PAD64)) = (((_VAL_) << 4) | ((REG32(ADR_PAD64)) & 0xffffff8f))
++#define SET_PAD64_OD(_VAL_) (REG32(ADR_PAD64)) = (((_VAL_) << 8) | ((REG32(ADR_PAD64)) & 0xfffffeff))
++#define SET_PAD64_SEL_O(_VAL_) (REG32(ADR_PAD64)) = (((_VAL_) << 12) | ((REG32(ADR_PAD64)) & 0xffffcfff))
++#define SET_PAD64_SEL_OE(_VAL_) (REG32(ADR_PAD64)) = (((_VAL_) << 20) | ((REG32(ADR_PAD64)) & 0xffefffff))
++#define SET_GPIO_15_IP_ID(_VAL_) (REG32(ADR_PAD64)) = (((_VAL_) << 28) | ((REG32(ADR_PAD64)) & 0xefffffff))
++#define SET_PAD65_OE(_VAL_) (REG32(ADR_PAD65)) = (((_VAL_) << 0) | ((REG32(ADR_PAD65)) & 0xfffffffe))
++#define SET_PAD65_PE(_VAL_) (REG32(ADR_PAD65)) = (((_VAL_) << 1) | ((REG32(ADR_PAD65)) & 0xfffffffd))
++#define SET_PAD65_DS(_VAL_) (REG32(ADR_PAD65)) = (((_VAL_) << 2) | ((REG32(ADR_PAD65)) & 0xfffffffb))
++#define SET_PAD65_IE(_VAL_) (REG32(ADR_PAD65)) = (((_VAL_) << 3) | ((REG32(ADR_PAD65)) & 0xfffffff7))
++#define SET_PAD65_SEL_I(_VAL_) (REG32(ADR_PAD65)) = (((_VAL_) << 4) | ((REG32(ADR_PAD65)) & 0xffffff8f))
++#define SET_PAD65_OD(_VAL_) (REG32(ADR_PAD65)) = (((_VAL_) << 8) | ((REG32(ADR_PAD65)) & 0xfffffeff))
++#define SET_PAD65_SEL_O(_VAL_) (REG32(ADR_PAD65)) = (((_VAL_) << 12) | ((REG32(ADR_PAD65)) & 0xffffefff))
++#define SET_GPIO_TEST_7_IN_ID(_VAL_) (REG32(ADR_PAD65)) = (((_VAL_) << 28) | ((REG32(ADR_PAD65)) & 0xefffffff))
++#define SET_PAD66_OE(_VAL_) (REG32(ADR_PAD66)) = (((_VAL_) << 0) | ((REG32(ADR_PAD66)) & 0xfffffffe))
++#define SET_PAD66_PE(_VAL_) (REG32(ADR_PAD66)) = (((_VAL_) << 1) | ((REG32(ADR_PAD66)) & 0xfffffffd))
++#define SET_PAD66_DS(_VAL_) (REG32(ADR_PAD66)) = (((_VAL_) << 2) | ((REG32(ADR_PAD66)) & 0xfffffffb))
++#define SET_PAD66_IE(_VAL_) (REG32(ADR_PAD66)) = (((_VAL_) << 3) | ((REG32(ADR_PAD66)) & 0xfffffff7))
++#define SET_PAD66_SEL_I(_VAL_) (REG32(ADR_PAD66)) = (((_VAL_) << 4) | ((REG32(ADR_PAD66)) & 0xffffffcf))
++#define SET_PAD66_OD(_VAL_) (REG32(ADR_PAD66)) = (((_VAL_) << 8) | ((REG32(ADR_PAD66)) & 0xfffffeff))
++#define SET_PAD66_SEL_O(_VAL_) (REG32(ADR_PAD66)) = (((_VAL_) << 12) | ((REG32(ADR_PAD66)) & 0xffffcfff))
++#define SET_GPIO_17_QP_ID(_VAL_) (REG32(ADR_PAD66)) = (((_VAL_) << 28) | ((REG32(ADR_PAD66)) & 0xefffffff))
++#define SET_PAD68_OE(_VAL_) (REG32(ADR_PAD68)) = (((_VAL_) << 0) | ((REG32(ADR_PAD68)) & 0xfffffffe))
++#define SET_PAD68_PE(_VAL_) (REG32(ADR_PAD68)) = (((_VAL_) << 1) | ((REG32(ADR_PAD68)) & 0xfffffffd))
++#define SET_PAD68_DS(_VAL_) (REG32(ADR_PAD68)) = (((_VAL_) << 2) | ((REG32(ADR_PAD68)) & 0xfffffffb))
++#define SET_PAD68_IE(_VAL_) (REG32(ADR_PAD68)) = (((_VAL_) << 3) | ((REG32(ADR_PAD68)) & 0xfffffff7))
++#define SET_PAD68_OD(_VAL_) (REG32(ADR_PAD68)) = (((_VAL_) << 8) | ((REG32(ADR_PAD68)) & 0xfffffeff))
++#define SET_PAD68_SEL_O(_VAL_) (REG32(ADR_PAD68)) = (((_VAL_) << 12) | ((REG32(ADR_PAD68)) & 0xffffefff))
++#define SET_GPIO_19_ID(_VAL_) (REG32(ADR_PAD68)) = (((_VAL_) << 28) | ((REG32(ADR_PAD68)) & 0xefffffff))
++#define SET_PAD67_OE(_VAL_) (REG32(ADR_PAD67)) = (((_VAL_) << 0) | ((REG32(ADR_PAD67)) & 0xfffffffe))
++#define SET_PAD67_PE(_VAL_) (REG32(ADR_PAD67)) = (((_VAL_) << 1) | ((REG32(ADR_PAD67)) & 0xfffffffd))
++#define SET_PAD67_DS(_VAL_) (REG32(ADR_PAD67)) = (((_VAL_) << 2) | ((REG32(ADR_PAD67)) & 0xfffffffb))
++#define SET_PAD67_IE(_VAL_) (REG32(ADR_PAD67)) = (((_VAL_) << 3) | ((REG32(ADR_PAD67)) & 0xfffffff7))
++#define SET_PAD67_SEL_I(_VAL_) (REG32(ADR_PAD67)) = (((_VAL_) << 4) | ((REG32(ADR_PAD67)) & 0xffffff8f))
++#define SET_PAD67_OD(_VAL_) (REG32(ADR_PAD67)) = (((_VAL_) << 8) | ((REG32(ADR_PAD67)) & 0xfffffeff))
++#define SET_PAD67_SEL_O(_VAL_) (REG32(ADR_PAD67)) = (((_VAL_) << 12) | ((REG32(ADR_PAD67)) & 0xffffcfff))
++#define SET_GPIO_TEST_8_QN_ID(_VAL_) (REG32(ADR_PAD67)) = (((_VAL_) << 28) | ((REG32(ADR_PAD67)) & 0xefffffff))
++#define SET_PAD69_OE(_VAL_) (REG32(ADR_PAD69)) = (((_VAL_) << 0) | ((REG32(ADR_PAD69)) & 0xfffffffe))
++#define SET_PAD69_PE(_VAL_) (REG32(ADR_PAD69)) = (((_VAL_) << 1) | ((REG32(ADR_PAD69)) & 0xfffffffd))
++#define SET_PAD69_DS(_VAL_) (REG32(ADR_PAD69)) = (((_VAL_) << 2) | ((REG32(ADR_PAD69)) & 0xfffffffb))
++#define SET_PAD69_IE(_VAL_) (REG32(ADR_PAD69)) = (((_VAL_) << 3) | ((REG32(ADR_PAD69)) & 0xfffffff7))
++#define SET_PAD69_SEL_I(_VAL_) (REG32(ADR_PAD69)) = (((_VAL_) << 4) | ((REG32(ADR_PAD69)) & 0xffffffcf))
++#define SET_PAD69_OD(_VAL_) (REG32(ADR_PAD69)) = (((_VAL_) << 8) | ((REG32(ADR_PAD69)) & 0xfffffeff))
++#define SET_PAD69_SEL_O(_VAL_) (REG32(ADR_PAD69)) = (((_VAL_) << 12) | ((REG32(ADR_PAD69)) & 0xffffefff))
++#define SET_STRAP2(_VAL_) (REG32(ADR_PAD69)) = (((_VAL_) << 27) | ((REG32(ADR_PAD69)) & 0xf7ffffff))
++#define SET_GPIO_20_ID(_VAL_) (REG32(ADR_PAD69)) = (((_VAL_) << 28) | ((REG32(ADR_PAD69)) & 0xefffffff))
++#define SET_PAD70_OE(_VAL_) (REG32(ADR_PAD70)) = (((_VAL_) << 0) | ((REG32(ADR_PAD70)) & 0xfffffffe))
++#define SET_PAD70_PE(_VAL_) (REG32(ADR_PAD70)) = (((_VAL_) << 1) | ((REG32(ADR_PAD70)) & 0xfffffffd))
++#define SET_PAD70_DS(_VAL_) (REG32(ADR_PAD70)) = (((_VAL_) << 2) | ((REG32(ADR_PAD70)) & 0xfffffffb))
++#define SET_PAD70_IE(_VAL_) (REG32(ADR_PAD70)) = (((_VAL_) << 3) | ((REG32(ADR_PAD70)) & 0xfffffff7))
++#define SET_PAD70_SEL_I(_VAL_) (REG32(ADR_PAD70)) = (((_VAL_) << 4) | ((REG32(ADR_PAD70)) & 0xffffffcf))
++#define SET_PAD70_OD(_VAL_) (REG32(ADR_PAD70)) = (((_VAL_) << 8) | ((REG32(ADR_PAD70)) & 0xfffffeff))
++#define SET_PAD70_SEL_O(_VAL_) (REG32(ADR_PAD70)) = (((_VAL_) << 12) | ((REG32(ADR_PAD70)) & 0xffff8fff))
++#define SET_GPIO_21_ID(_VAL_) (REG32(ADR_PAD70)) = (((_VAL_) << 28) | ((REG32(ADR_PAD70)) & 0xefffffff))
++#define SET_PAD231_OE(_VAL_) (REG32(ADR_PAD231)) = (((_VAL_) << 0) | ((REG32(ADR_PAD231)) & 0xfffffffe))
++#define SET_PAD231_PE(_VAL_) (REG32(ADR_PAD231)) = (((_VAL_) << 1) | ((REG32(ADR_PAD231)) & 0xfffffffd))
++#define SET_PAD231_DS(_VAL_) (REG32(ADR_PAD231)) = (((_VAL_) << 2) | ((REG32(ADR_PAD231)) & 0xfffffffb))
++#define SET_PAD231_IE(_VAL_) (REG32(ADR_PAD231)) = (((_VAL_) << 3) | ((REG32(ADR_PAD231)) & 0xfffffff7))
++#define SET_PAD231_OD(_VAL_) (REG32(ADR_PAD231)) = (((_VAL_) << 8) | ((REG32(ADR_PAD231)) & 0xfffffeff))
++#define SET_PIN_40_OR_56_ID(_VAL_) (REG32(ADR_PAD231)) = (((_VAL_) << 28) | ((REG32(ADR_PAD231)) & 0xefffffff))
++#define SET_MP_PHY2RX_DATA__0_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 0) | ((REG32(ADR_PIN_SEL_0)) & 0xfffffffe))
++#define SET_MP_PHY2RX_DATA__1_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 1) | ((REG32(ADR_PIN_SEL_0)) & 0xfffffffd))
++#define SET_MP_TX_FF_RPTR__1_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 2) | ((REG32(ADR_PIN_SEL_0)) & 0xfffffffb))
++#define SET_MP_RX_FF_WPTR__2_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 3) | ((REG32(ADR_PIN_SEL_0)) & 0xfffffff7))
++#define SET_MP_RX_FF_WPTR__1_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 4) | ((REG32(ADR_PIN_SEL_0)) & 0xffffffef))
++#define SET_MP_RX_FF_WPTR__0_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 5) | ((REG32(ADR_PIN_SEL_0)) & 0xffffffdf))
++#define SET_MP_PHY2RX_DATA__2_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 6) | ((REG32(ADR_PIN_SEL_0)) & 0xffffffbf))
++#define SET_MP_PHY2RX_DATA__4_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 7) | ((REG32(ADR_PIN_SEL_0)) & 0xffffff7f))
++#define SET_I2CM_SDA_ID_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 8) | ((REG32(ADR_PIN_SEL_0)) & 0xfffffcff))
++#define SET_CRYSTAL_OUT_REQ_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 10) | ((REG32(ADR_PIN_SEL_0)) & 0xfffffbff))
++#define SET_MP_PHY2RX_DATA__5_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 11) | ((REG32(ADR_PIN_SEL_0)) & 0xfffff7ff))
++#define SET_MP_PHY2RX_DATA__3_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 12) | ((REG32(ADR_PIN_SEL_0)) & 0xffffefff))
++#define SET_UART_RXD_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 13) | ((REG32(ADR_PIN_SEL_0)) & 0xffff9fff))
++#define SET_MP_PHY2RX_DATA__6_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 15) | ((REG32(ADR_PIN_SEL_0)) & 0xffff7fff))
++#define SET_DAT_UART_NCTS_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 16) | ((REG32(ADR_PIN_SEL_0)) & 0xfffeffff))
++#define SET_GPIO_LOG_STOP_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 17) | ((REG32(ADR_PIN_SEL_0)) & 0xfff1ffff))
++#define SET_MP_TX_FF_RPTR__0_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 20) | ((REG32(ADR_PIN_SEL_0)) & 0xffefffff))
++#define SET_MP_PHY_RX_WRST_N_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 21) | ((REG32(ADR_PIN_SEL_0)) & 0xffdfffff))
++#define SET_EXT_32K_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 22) | ((REG32(ADR_PIN_SEL_0)) & 0xff3fffff))
++#define SET_MP_PHY2RX_DATA__7_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 24) | ((REG32(ADR_PIN_SEL_0)) & 0xfeffffff))
++#define SET_MP_TX_FF_RPTR__2_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 25) | ((REG32(ADR_PIN_SEL_0)) & 0xfdffffff))
++#define SET_PMUINT_WAKE_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 26) | ((REG32(ADR_PIN_SEL_0)) & 0xe3ffffff))
++#define SET_I2CM_SCL_ID_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 29) | ((REG32(ADR_PIN_SEL_0)) & 0xdfffffff))
++#define SET_MP_MRX_RX_EN_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 30) | ((REG32(ADR_PIN_SEL_0)) & 0xbfffffff))
++#define SET_DAT_UART_RXD_SEL_0(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 31) | ((REG32(ADR_PIN_SEL_0)) & 0x7fffffff))
++#define SET_DAT_UART_RXD_SEL_1(_VAL_) (REG32(ADR_PIN_SEL_1)) = (((_VAL_) << 0) | ((REG32(ADR_PIN_SEL_1)) & 0xfffffffe))
++#define SET_SPI_DI_SEL(_VAL_) (REG32(ADR_PIN_SEL_1)) = (((_VAL_) << 1) | ((REG32(ADR_PIN_SEL_1)) & 0xfffffffd))
++#define SET_IO_PORT_REG(_VAL_) (REG32(ADR_IO_PORT_REG)) = (((_VAL_) << 0) | ((REG32(ADR_IO_PORT_REG)) & 0xfffe0000))
++#define SET_MASK_RX_INT(_VAL_) (REG32(ADR_INT_MASK_REG)) = (((_VAL_) << 0) | ((REG32(ADR_INT_MASK_REG)) & 0xfffffffe))
++#define SET_MASK_TX_INT(_VAL_) (REG32(ADR_INT_MASK_REG)) = (((_VAL_) << 1) | ((REG32(ADR_INT_MASK_REG)) & 0xfffffffd))
++#define SET_MASK_SOC_SYSTEM_INT(_VAL_) (REG32(ADR_INT_MASK_REG)) = (((_VAL_) << 2) | ((REG32(ADR_INT_MASK_REG)) & 0xfffffffb))
++#define SET_EDCA0_LOW_THR_INT_MASK(_VAL_) (REG32(ADR_INT_MASK_REG)) = (((_VAL_) << 3) | ((REG32(ADR_INT_MASK_REG)) & 0xfffffff7))
++#define SET_EDCA1_LOW_THR_INT_MASK(_VAL_) (REG32(ADR_INT_MASK_REG)) = (((_VAL_) << 4) | ((REG32(ADR_INT_MASK_REG)) & 0xffffffef))
++#define SET_EDCA2_LOW_THR_INT_MASK(_VAL_) (REG32(ADR_INT_MASK_REG)) = (((_VAL_) << 5) | ((REG32(ADR_INT_MASK_REG)) & 0xffffffdf))
++#define SET_EDCA3_LOW_THR_INT_MASK(_VAL_) (REG32(ADR_INT_MASK_REG)) = (((_VAL_) << 6) | ((REG32(ADR_INT_MASK_REG)) & 0xffffffbf))
++#define SET_TX_LIMIT_INT_MASK(_VAL_) (REG32(ADR_INT_MASK_REG)) = (((_VAL_) << 7) | ((REG32(ADR_INT_MASK_REG)) & 0xffffff7f))
++#define SET_RX_INT(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 0) | ((REG32(ADR_INT_STATUS_REG)) & 0xfffffffe))
++#define SET_TX_COMPLETE_INT(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 1) | ((REG32(ADR_INT_STATUS_REG)) & 0xfffffffd))
++#define SET_SOC_SYSTEM_INT_STATUS(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 2) | ((REG32(ADR_INT_STATUS_REG)) & 0xfffffffb))
++#define SET_EDCA0_LOW_THR_INT_STS(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 3) | ((REG32(ADR_INT_STATUS_REG)) & 0xfffffff7))
++#define SET_EDCA1_LOW_THR_INT_STS(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 4) | ((REG32(ADR_INT_STATUS_REG)) & 0xffffffef))
++#define SET_EDCA2_LOW_THR_INT_STS(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 5) | ((REG32(ADR_INT_STATUS_REG)) & 0xffffffdf))
++#define SET_EDCA3_LOW_THR_INT_STS(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 6) | ((REG32(ADR_INT_STATUS_REG)) & 0xffffffbf))
++#define SET_TX_LIMIT_INT_STS(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 7) | ((REG32(ADR_INT_STATUS_REG)) & 0xffffff7f))
++#define SET_HOST_TRIGGERED_RX_INT(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 8) | ((REG32(ADR_INT_STATUS_REG)) & 0xfffffeff))
++#define SET_HOST_TRIGGERED_TX_INT(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 9) | ((REG32(ADR_INT_STATUS_REG)) & 0xfffffdff))
++#define SET_SOC_TRIGGER_RX_INT(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 10) | ((REG32(ADR_INT_STATUS_REG)) & 0xfffffbff))
++#define SET_SOC_TRIGGER_TX_INT(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 11) | ((REG32(ADR_INT_STATUS_REG)) & 0xfffff7ff))
++#define SET_RDY_FOR_TX_RX(_VAL_) (REG32(ADR_FN1_STATUS_REG)) = (((_VAL_) << 0) | ((REG32(ADR_FN1_STATUS_REG)) & 0xfffffffe))
++#define SET_RDY_FOR_FW_DOWNLOAD(_VAL_) (REG32(ADR_FN1_STATUS_REG)) = (((_VAL_) << 1) | ((REG32(ADR_FN1_STATUS_REG)) & 0xfffffffd))
++#define SET_ILLEGAL_CMD_RESP_OPTION(_VAL_) (REG32(ADR_FN1_STATUS_REG)) = (((_VAL_) << 2) | ((REG32(ADR_FN1_STATUS_REG)) & 0xfffffffb))
++#define SET_SDIO_TRX_DATA_SEQUENCE(_VAL_) (REG32(ADR_FN1_STATUS_REG)) = (((_VAL_) << 3) | ((REG32(ADR_FN1_STATUS_REG)) & 0xfffffff7))
++#define SET_GPIO_INT_TRIGGER_OPTION(_VAL_) (REG32(ADR_FN1_STATUS_REG)) = (((_VAL_) << 4) | ((REG32(ADR_FN1_STATUS_REG)) & 0xffffffef))
++#define SET_TRIGGER_FUNCTION_SETTING(_VAL_) (REG32(ADR_FN1_STATUS_REG)) = (((_VAL_) << 5) | ((REG32(ADR_FN1_STATUS_REG)) & 0xffffff9f))
++#define SET_CMD52_ABORT_RESPONSE(_VAL_) (REG32(ADR_FN1_STATUS_REG)) = (((_VAL_) << 7) | ((REG32(ADR_FN1_STATUS_REG)) & 0xffffff7f))
++#define SET_RX_PACKET_LENGTH(_VAL_) (REG32(ADR_CARD_PKT_STATUS_TEST)) = (((_VAL_) << 0) | ((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0xffff0000))
++#define SET_CARD_FW_DL_STATUS(_VAL_) (REG32(ADR_CARD_PKT_STATUS_TEST)) = (((_VAL_) << 16) | ((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0xff00ffff))
++#define SET_TX_RX_LOOP_BACK_TEST(_VAL_) (REG32(ADR_CARD_PKT_STATUS_TEST)) = (((_VAL_) << 24) | ((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0xfeffffff))
++#define SET_SDIO_LOOP_BACK_TEST(_VAL_) (REG32(ADR_CARD_PKT_STATUS_TEST)) = (((_VAL_) << 25) | ((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0xfdffffff))
++#define SET_CMD52_ABORT_ACTIVE(_VAL_) (REG32(ADR_CARD_PKT_STATUS_TEST)) = (((_VAL_) << 28) | ((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0xefffffff))
++#define SET_CMD52_RESET_ACTIVE(_VAL_) (REG32(ADR_CARD_PKT_STATUS_TEST)) = (((_VAL_) << 29) | ((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0xdfffffff))
++#define SET_SDIO_PARTIAL_RESET_ACTIVE(_VAL_) (REG32(ADR_CARD_PKT_STATUS_TEST)) = (((_VAL_) << 30) | ((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0xbfffffff))
++#define SET_SDIO_ALL_RESE_ACTIVE(_VAL_) (REG32(ADR_CARD_PKT_STATUS_TEST)) = (((_VAL_) << 31) | ((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0x7fffffff))
++#define SET_RX_PACKET_LENGTH2(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0xffff0000))
++#define SET_RX_INT1(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 16) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0xfffeffff))
++#define SET_TX_DONE(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 17) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0xfffdffff))
++#define SET_HCI_TRX_FINISH(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 18) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0xfffbffff))
++#define SET_ALLOCATE_STATUS(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 19) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0xfff7ffff))
++#define SET_HCI_INPUT_FF_CNT(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 20) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0xff0fffff))
++#define SET_HCI_OUTPUT_FF_CNT(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 24) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0xe0ffffff))
++#define SET_AHB_HANG4(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 29) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0xdfffffff))
++#define SET_HCI_IN_QUE_EMPTY(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 30) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0xbfffffff))
++#define SET_SYSTEM_INT(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 31) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x7fffffff))
++#define SET_CARD_RCA_REG(_VAL_) (REG32(ADR_CARD_RCA_REG)) = (((_VAL_) << 0) | ((REG32(ADR_CARD_RCA_REG)) & 0xffff0000))
++#define SET_SDIO_FIFO_WR_THLD_REG(_VAL_) (REG32(ADR_SDIO_FIFO_WR_THLD_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_FIFO_WR_THLD_REG)) & 0xfffffe00))
++#define SET_SDIO_FIFO_WR_LIMIT_REG(_VAL_) (REG32(ADR_SDIO_FIFO_WR_LIMIT_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_FIFO_WR_LIMIT_REG)) & 0xfffffe00))
++#define SET_SDIO_TX_DATA_BATCH_SIZE_REG(_VAL_) (REG32(ADR_SDIO_TX_DATA_BATCH_SIZE_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_TX_DATA_BATCH_SIZE_REG)) & 0xfffffe00))
++#define SET_SDIO_THLD_FOR_CMD53RD_REG(_VAL_) (REG32(ADR_SDIO_THLD_FOR_CMD53RD_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_THLD_FOR_CMD53RD_REG)) & 0xfffffe00))
++#define SET_SDIO_RX_DATA_BATCH_SIZE_REG(_VAL_) (REG32(ADR_SDIO_RX_DATA_BATCH_SIZE_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_RX_DATA_BATCH_SIZE_REG)) & 0xfffffe00))
++#define SET_START_BYTE_VALUE(_VAL_) (REG32(ADR_SDIO_LOG_START_END_DATA_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_LOG_START_END_DATA_REG)) & 0xffffff00))
++#define SET_END_BYTE_VALUE(_VAL_) (REG32(ADR_SDIO_LOG_START_END_DATA_REG)) = (((_VAL_) << 8) | ((REG32(ADR_SDIO_LOG_START_END_DATA_REG)) & 0xffff00ff))
++#define SET_SDIO_BYTE_MODE_BATCH_SIZE_REG(_VAL_) (REG32(ADR_SDIO_BYTE_MODE_BATCH_SIZE_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_BYTE_MODE_BATCH_SIZE_REG)) & 0xffffff00))
++#define SET_SDIO_LAST_CMD_INDEX_REG(_VAL_) (REG32(ADR_SDIO_LAST_CMD_INDEX_CRC_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_LAST_CMD_INDEX_CRC_REG)) & 0xffffffc0))
++#define SET_SDIO_LAST_CMD_CRC_REG(_VAL_) (REG32(ADR_SDIO_LAST_CMD_INDEX_CRC_REG)) = (((_VAL_) << 8) | ((REG32(ADR_SDIO_LAST_CMD_INDEX_CRC_REG)) & 0xffff80ff))
++#define SET_SDIO_LAST_CMD_ARG_REG(_VAL_) (REG32(ADR_SDIO_LAST_CMD_ARG_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_LAST_CMD_ARG_REG)) & 0x00000000))
++#define SET_SDIO_BUS_STATE_REG(_VAL_) (REG32(ADR_SDIO_BUS_STATE_DEBUG_MONITOR)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_BUS_STATE_DEBUG_MONITOR)) & 0xffffffe0))
++#define SET_SDIO_BUSY_LONG_CNT(_VAL_) (REG32(ADR_SDIO_BUS_STATE_DEBUG_MONITOR)) = (((_VAL_) << 16) | ((REG32(ADR_SDIO_BUS_STATE_DEBUG_MONITOR)) & 0x0000ffff))
++#define SET_SDIO_CARD_STATUS_REG(_VAL_) (REG32(ADR_SDIO_CARD_STATUS_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_CARD_STATUS_REG)) & 0x00000000))
++#define SET_R5_RESPONSE_FLAG(_VAL_) (REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) = (((_VAL_) << 0) | ((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0xffffff00))
++#define SET_RESP_OUT_EDGE(_VAL_) (REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) = (((_VAL_) << 8) | ((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0xfffffeff))
++#define SET_DAT_OUT_EDGE(_VAL_) (REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) = (((_VAL_) << 9) | ((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0xfffffdff))
++#define SET_MCU_TO_SDIO_INFO_MASK(_VAL_) (REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) = (((_VAL_) << 16) | ((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0xfffeffff))
++#define SET_INT_THROUGH_PIN(_VAL_) (REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) = (((_VAL_) << 17) | ((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0xfffdffff))
++#define SET_WRITE_DATA(_VAL_) (REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) = (((_VAL_) << 0) | ((REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) & 0xffffff00))
++#define SET_WRITE_ADDRESS(_VAL_) (REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) = (((_VAL_) << 8) | ((REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) & 0xffff00ff))
++#define SET_READ_DATA(_VAL_) (REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) = (((_VAL_) << 16) | ((REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) & 0xff00ffff))
++#define SET_READ_ADDRESS(_VAL_) (REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) = (((_VAL_) << 24) | ((REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) & 0x00ffffff))
++#define SET_FN1_DMA_START_ADDR_REG(_VAL_) (REG32(ADR_FN1_DMA_START_ADDR_REG)) = (((_VAL_) << 0) | ((REG32(ADR_FN1_DMA_START_ADDR_REG)) & 0x00000000))
++#define SET_SDIO_TO_MCU_INFO(_VAL_) (REG32(ADR_FN1_INT_CTRL_RESET)) = (((_VAL_) << 0) | ((REG32(ADR_FN1_INT_CTRL_RESET)) & 0xffffff00))
++#define SET_SDIO_PARTIAL_RESET(_VAL_) (REG32(ADR_FN1_INT_CTRL_RESET)) = (((_VAL_) << 8) | ((REG32(ADR_FN1_INT_CTRL_RESET)) & 0xfffffeff))
++#define SET_SDIO_ALL_RESET(_VAL_) (REG32(ADR_FN1_INT_CTRL_RESET)) = (((_VAL_) << 9) | ((REG32(ADR_FN1_INT_CTRL_RESET)) & 0xfffffdff))
++#define SET_PERI_MAC_ALL_RESET(_VAL_) (REG32(ADR_FN1_INT_CTRL_RESET)) = (((_VAL_) << 10) | ((REG32(ADR_FN1_INT_CTRL_RESET)) & 0xfffffbff))
++#define SET_MAC_ALL_RESET(_VAL_) (REG32(ADR_FN1_INT_CTRL_RESET)) = (((_VAL_) << 11) | ((REG32(ADR_FN1_INT_CTRL_RESET)) & 0xfffff7ff))
++#define SET_AHB_BRIDGE_RESET(_VAL_) (REG32(ADR_FN1_INT_CTRL_RESET)) = (((_VAL_) << 12) | ((REG32(ADR_FN1_INT_CTRL_RESET)) & 0xffffefff))
++#define SET_IO_REG_PORT_REG(_VAL_) (REG32(ADR_IO_REG_PORT_REG)) = (((_VAL_) << 0) | ((REG32(ADR_IO_REG_PORT_REG)) & 0xfffe0000))
++#define SET_SDIO_FIFO_EMPTY_CNT(_VAL_) (REG32(ADR_SDIO_FIFO_ERROR_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_FIFO_ERROR_CNT)) & 0xffff0000))
++#define SET_SDIO_FIFO_FULL_CNT(_VAL_) (REG32(ADR_SDIO_FIFO_ERROR_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_SDIO_FIFO_ERROR_CNT)) & 0x0000ffff))
++#define SET_SDIO_CRC7_ERROR_CNT(_VAL_) (REG32(ADR_SDIO_CRC7_CRC16_ERROR_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_CRC7_CRC16_ERROR_REG)) & 0xffff0000))
++#define SET_SDIO_CRC16_ERROR_CNT(_VAL_) (REG32(ADR_SDIO_CRC7_CRC16_ERROR_REG)) = (((_VAL_) << 16) | ((REG32(ADR_SDIO_CRC7_CRC16_ERROR_REG)) & 0x0000ffff))
++#define SET_SDIO_RD_BLOCK_CNT(_VAL_) (REG32(ADR_SDIO_BLOCK_CNT_INFO)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_BLOCK_CNT_INFO)) & 0xfffffe00))
++#define SET_SDIO_WR_BLOCK_CNT(_VAL_) (REG32(ADR_SDIO_BLOCK_CNT_INFO)) = (((_VAL_) << 16) | ((REG32(ADR_SDIO_BLOCK_CNT_INFO)) & 0xfe00ffff))
++#define SET_CMD52_RD_ABORT_CNT(_VAL_) (REG32(ADR_RX_DATA_CMD52_ABORT_COUNT)) = (((_VAL_) << 16) | ((REG32(ADR_RX_DATA_CMD52_ABORT_COUNT)) & 0xfff0ffff))
++#define SET_CMD52_WR_ABORT_CNT(_VAL_) (REG32(ADR_RX_DATA_CMD52_ABORT_COUNT)) = (((_VAL_) << 20) | ((REG32(ADR_RX_DATA_CMD52_ABORT_COUNT)) & 0xff0fffff))
++#define SET_SDIO_FIFO_WR_PTR_REG(_VAL_) (REG32(ADR_FIFO_PTR_READ_BLOCK_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_FIFO_PTR_READ_BLOCK_CNT)) & 0xffffff00))
++#define SET_SDIO_FIFO_RD_PTR_REG(_VAL_) (REG32(ADR_FIFO_PTR_READ_BLOCK_CNT)) = (((_VAL_) << 8) | ((REG32(ADR_FIFO_PTR_READ_BLOCK_CNT)) & 0xffff00ff))
++#define SET_SDIO_READ_DATA_CTRL(_VAL_) (REG32(ADR_TX_TIME_OUT_READ_CTRL)) = (((_VAL_) << 16) | ((REG32(ADR_TX_TIME_OUT_READ_CTRL)) & 0xfffeffff))
++#define SET_TX_SIZE_BEFORE_SHIFT(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xffffff00))
++#define SET_TX_SIZE_SHIFT_BITS(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 8) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xfffff8ff))
++#define SET_SDIO_TX_ALLOC_STATE(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 12) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xffffefff))
++#define SET_ALLOCATE_STATUS2(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 16) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xfffeffff))
++#define SET_NO_ALLOCATE_SEND_ERROR(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 17) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xfffdffff))
++#define SET_DOUBLE_ALLOCATE_ERROR(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 18) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xfffbffff))
++#define SET_TX_DONE_STATUS(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 19) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xfff7ffff))
++#define SET_AHB_HANG2(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 20) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xffefffff))
++#define SET_HCI_TRX_FINISH2(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 21) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xffdfffff))
++#define SET_INTR_RX(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 22) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xffbfffff))
++#define SET_HCI_INPUT_QUEUE_FULL(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 23) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xff7fffff))
++#define SET_ALLOCATESTATUS(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xfffffffe))
++#define SET_HCI_TRX_FINISH3(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 1) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xfffffffd))
++#define SET_HCI_IN_QUE_EMPTY2(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 2) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xfffffffb))
++#define SET_MTX_MNG_UPTHOLD_INT(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 3) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xfffffff7))
++#define SET_EDCA0_UPTHOLD_INT(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 4) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xffffffef))
++#define SET_EDCA1_UPTHOLD_INT(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 5) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xffffffdf))
++#define SET_EDCA2_UPTHOLD_INT(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 6) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xffffffbf))
++#define SET_EDCA3_UPTHOLD_INT(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 7) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xffffff7f))
++#define SET_TX_PAGE_REMAIN2(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 8) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xffff00ff))
++#define SET_TX_ID_REMAIN3(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 16) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xff80ffff))
++#define SET_HCI_OUTPUT_FF_CNT_0(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 23) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xff7fffff))
++#define SET_HCI_OUTPUT_FF_CNT2(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 24) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xf0ffffff))
++#define SET_HCI_INPUT_FF_CNT2(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 28) | ((REG32(ADR_SDIO_TX_INFORM)) & 0x0fffffff))
++#define SET_F1_BLOCK_SIZE_0_REG(_VAL_) (REG32(ADR_F1_BLOCK_SIZE_0_REG)) = (((_VAL_) << 0) | ((REG32(ADR_F1_BLOCK_SIZE_0_REG)) & 0xfffff000))
++#define SET_START_BYTE_VALUE2(_VAL_) (REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) & 0xffffff00))
++#define SET_COMMAND_COUNTER(_VAL_) (REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) = (((_VAL_) << 8) | ((REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) & 0xffff00ff))
++#define SET_CMD_LOG_PART1(_VAL_) (REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) = (((_VAL_) << 16) | ((REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) & 0x0000ffff))
++#define SET_CMD_LOG_PART2(_VAL_) (REG32(ADR_SDIO_COMMAND_LOG_DATA_63_32)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_COMMAND_LOG_DATA_63_32)) & 0xff000000))
++#define SET_END_BYTE_VALUE2(_VAL_) (REG32(ADR_SDIO_COMMAND_LOG_DATA_63_32)) = (((_VAL_) << 24) | ((REG32(ADR_SDIO_COMMAND_LOG_DATA_63_32)) & 0x00ffffff))
++#define SET_RX_PACKET_LENGTH3(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_SYSTEM_INFORMATION_REGISTER)) & 0xffff0000))
++#define SET_RX_INT3(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_SYSTEM_INFORMATION_REGISTER)) & 0xfffeffff))
++#define SET_TX_ID_REMAIN2(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REGISTER)) = (((_VAL_) << 17) | ((REG32(ADR_SYSTEM_INFORMATION_REGISTER)) & 0xff01ffff))
++#define SET_TX_PAGE_REMAIN3(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REGISTER)) = (((_VAL_) << 24) | ((REG32(ADR_SYSTEM_INFORMATION_REGISTER)) & 0x00ffffff))
++#define SET_CCCR_00H_REG(_VAL_) (REG32(ADR_CCCR_00H_REG)) = (((_VAL_) << 0) | ((REG32(ADR_CCCR_00H_REG)) & 0xffffff00))
++#define SET_CCCR_02H_REG(_VAL_) (REG32(ADR_CCCR_00H_REG)) = (((_VAL_) << 16) | ((REG32(ADR_CCCR_00H_REG)) & 0xff00ffff))
++#define SET_CCCR_03H_REG(_VAL_) (REG32(ADR_CCCR_00H_REG)) = (((_VAL_) << 24) | ((REG32(ADR_CCCR_00H_REG)) & 0x00ffffff))
++#define SET_CCCR_04H_REG(_VAL_) (REG32(ADR_CCCR_04H_REG)) = (((_VAL_) << 0) | ((REG32(ADR_CCCR_04H_REG)) & 0xffffff00))
++#define SET_CCCR_05H_REG(_VAL_) (REG32(ADR_CCCR_04H_REG)) = (((_VAL_) << 8) | ((REG32(ADR_CCCR_04H_REG)) & 0xffff00ff))
++#define SET_CCCR_06H_REG(_VAL_) (REG32(ADR_CCCR_04H_REG)) = (((_VAL_) << 16) | ((REG32(ADR_CCCR_04H_REG)) & 0xfff0ffff))
++#define SET_CCCR_07H_REG(_VAL_) (REG32(ADR_CCCR_04H_REG)) = (((_VAL_) << 24) | ((REG32(ADR_CCCR_04H_REG)) & 0x00ffffff))
++#define SET_SUPPORT_DIRECT_COMMAND_SDIO(_VAL_) (REG32(ADR_CCCR_08H_REG)) = (((_VAL_) << 0) | ((REG32(ADR_CCCR_08H_REG)) & 0xfffffffe))
++#define SET_SUPPORT_MULTIPLE_BLOCK_TRANSFER(_VAL_) (REG32(ADR_CCCR_08H_REG)) = (((_VAL_) << 1) | ((REG32(ADR_CCCR_08H_REG)) & 0xfffffffd))
++#define SET_SUPPORT_READ_WAIT(_VAL_) (REG32(ADR_CCCR_08H_REG)) = (((_VAL_) << 2) | ((REG32(ADR_CCCR_08H_REG)) & 0xfffffffb))
++#define SET_SUPPORT_BUS_CONTROL(_VAL_) (REG32(ADR_CCCR_08H_REG)) = (((_VAL_) << 3) | ((REG32(ADR_CCCR_08H_REG)) & 0xfffffff7))
++#define SET_SUPPORT_BLOCK_GAP_INTERRUPT(_VAL_) (REG32(ADR_CCCR_08H_REG)) = (((_VAL_) << 4) | ((REG32(ADR_CCCR_08H_REG)) & 0xffffffef))
++#define SET_ENABLE_BLOCK_GAP_INTERRUPT(_VAL_) (REG32(ADR_CCCR_08H_REG)) = (((_VAL_) << 5) | ((REG32(ADR_CCCR_08H_REG)) & 0xffffffdf))
++#define SET_LOW_SPEED_CARD(_VAL_) (REG32(ADR_CCCR_08H_REG)) = (((_VAL_) << 6) | ((REG32(ADR_CCCR_08H_REG)) & 0xffffffbf))
++#define SET_LOW_SPEED_CARD_4BIT(_VAL_) (REG32(ADR_CCCR_08H_REG)) = (((_VAL_) << 7) | ((REG32(ADR_CCCR_08H_REG)) & 0xffffff7f))
++#define SET_COMMON_CIS_PONTER(_VAL_) (REG32(ADR_CCCR_08H_REG)) = (((_VAL_) << 8) | ((REG32(ADR_CCCR_08H_REG)) & 0xfe0000ff))
++#define SET_SUPPORT_HIGH_SPEED(_VAL_) (REG32(ADR_CCCR_13H_REG)) = (((_VAL_) << 24) | ((REG32(ADR_CCCR_13H_REG)) & 0xfeffffff))
++#define SET_BSS(_VAL_) (REG32(ADR_CCCR_13H_REG)) = (((_VAL_) << 25) | ((REG32(ADR_CCCR_13H_REG)) & 0xf1ffffff))
++#define SET_FBR_100H_REG(_VAL_) (REG32(ADR_FBR_100H_REG)) = (((_VAL_) << 0) | ((REG32(ADR_FBR_100H_REG)) & 0xfffffff0))
++#define SET_CSASUPPORT(_VAL_) (REG32(ADR_FBR_100H_REG)) = (((_VAL_) << 6) | ((REG32(ADR_FBR_100H_REG)) & 0xffffffbf))
++#define SET_ENABLECSA(_VAL_) (REG32(ADR_FBR_100H_REG)) = (((_VAL_) << 7) | ((REG32(ADR_FBR_100H_REG)) & 0xffffff7f))
++#define SET_FBR_101H_REG(_VAL_) (REG32(ADR_FBR_100H_REG)) = (((_VAL_) << 8) | ((REG32(ADR_FBR_100H_REG)) & 0xffff00ff))
++#define SET_FBR_109H_REG(_VAL_) (REG32(ADR_FBR_109H_REG)) = (((_VAL_) << 8) | ((REG32(ADR_FBR_109H_REG)) & 0xfe0000ff))
++#define SET_F0_CIS_CONTENT_REG_31_0(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_0)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_0)) & 0x00000000))
++#define SET_F0_CIS_CONTENT_REG_63_32(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_1)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_1)) & 0x00000000))
++#define SET_F0_CIS_CONTENT_REG_95_64(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_2)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_2)) & 0x00000000))
++#define SET_F0_CIS_CONTENT_REG_127_96(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_3)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_3)) & 0x00000000))
++#define SET_F0_CIS_CONTENT_REG_159_128(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_4)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_4)) & 0x00000000))
++#define SET_F0_CIS_CONTENT_REG_191_160(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_5)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_5)) & 0x00000000))
++#define SET_F0_CIS_CONTENT_REG_223_192(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_6)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_6)) & 0x00000000))
++#define SET_F0_CIS_CONTENT_REG_255_224(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_7)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_7)) & 0x00000000))
++#define SET_F0_CIS_CONTENT_REG_287_256(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_8)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_8)) & 0x00000000))
++#define SET_F0_CIS_CONTENT_REG_319_288(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_9)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_9)) & 0x00000000))
++#define SET_F0_CIS_CONTENT_REG_351_320(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_10)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_10)) & 0x00000000))
++#define SET_F0_CIS_CONTENT_REG_383_352(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_11)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_11)) & 0x00000000))
++#define SET_F0_CIS_CONTENT_REG_415_384(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_12)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_12)) & 0x00000000))
++#define SET_F0_CIS_CONTENT_REG_447_416(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_13)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_13)) & 0x00000000))
++#define SET_F0_CIS_CONTENT_REG_479_448(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_14)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_14)) & 0x00000000))
++#define SET_F0_CIS_CONTENT_REG_511_480(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_15)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_15)) & 0x00000000))
++#define SET_F1_CIS_CONTENT_REG_31_0(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_0)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_0)) & 0x00000000))
++#define SET_F1_CIS_CONTENT_REG_63_32(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_1)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_1)) & 0x00000000))
++#define SET_F1_CIS_CONTENT_REG_95_64(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_2)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_2)) & 0x00000000))
++#define SET_F1_CIS_CONTENT_REG_127_96(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_3)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_3)) & 0x00000000))
++#define SET_F1_CIS_CONTENT_REG_159_128(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_4)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_4)) & 0x00000000))
++#define SET_F1_CIS_CONTENT_REG_191_160(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_5)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_5)) & 0x00000000))
++#define SET_F1_CIS_CONTENT_REG_223_192(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_6)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_6)) & 0x00000000))
++#define SET_F1_CIS_CONTENT_REG_255_224(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_7)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_7)) & 0x00000000))
++#define SET_F1_CIS_CONTENT_REG_287_256(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_8)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_8)) & 0x00000000))
++#define SET_F1_CIS_CONTENT_REG_319_288(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_9)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_9)) & 0x00000000))
++#define SET_F1_CIS_CONTENT_REG_351_320(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_10)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_10)) & 0x00000000))
++#define SET_F1_CIS_CONTENT_REG_383_352(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_11)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_11)) & 0x00000000))
++#define SET_F1_CIS_CONTENT_REG_415_384(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_12)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_12)) & 0x00000000))
++#define SET_F1_CIS_CONTENT_REG_447_416(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_13)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_13)) & 0x00000000))
++#define SET_F1_CIS_CONTENT_REG_479_448(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_14)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_14)) & 0x00000000))
++#define SET_F1_CIS_CONTENT_REG_511_480(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_15)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_15)) & 0x00000000))
++#define SET_SPI_MODE(_VAL_) (REG32(ADR_SPI_MODE)) = (((_VAL_) << 0) | ((REG32(ADR_SPI_MODE)) & 0x00000000))
++#define SET_RX_QUOTA(_VAL_) (REG32(ADR_RX_QUOTA)) = (((_VAL_) << 0) | ((REG32(ADR_RX_QUOTA)) & 0xffff0000))
++#define SET_CONDI_NUM(_VAL_) (REG32(ADR_CONDITION_NUMBER)) = (((_VAL_) << 0) | ((REG32(ADR_CONDITION_NUMBER)) & 0xffffff00))
++#define SET_HOST_PATH(_VAL_) (REG32(ADR_HOST_PATH)) = (((_VAL_) << 0) | ((REG32(ADR_HOST_PATH)) & 0xfffffffe))
++#define SET_TX_SEG(_VAL_) (REG32(ADR_TX_SEG)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEG)) & 0x00000000))
++#define SET_BRST_MODE(_VAL_) (REG32(ADR_DEBUG_BURST_MODE)) = (((_VAL_) << 0) | ((REG32(ADR_DEBUG_BURST_MODE)) & 0xfffffffe))
++#define SET_CLK_WIDTH(_VAL_) (REG32(ADR_SPI_TO_PHY_PARAM1)) = (((_VAL_) << 0) | ((REG32(ADR_SPI_TO_PHY_PARAM1)) & 0xffff0000))
++#define SET_CSN_INTER(_VAL_) (REG32(ADR_SPI_TO_PHY_PARAM1)) = (((_VAL_) << 16) | ((REG32(ADR_SPI_TO_PHY_PARAM1)) & 0x0000ffff))
++#define SET_BACK_DLY(_VAL_) (REG32(ADR_SPI_TO_PHY_PARAM2)) = (((_VAL_) << 0) | ((REG32(ADR_SPI_TO_PHY_PARAM2)) & 0xffff0000))
++#define SET_FRONT_DLY(_VAL_) (REG32(ADR_SPI_TO_PHY_PARAM2)) = (((_VAL_) << 16) | ((REG32(ADR_SPI_TO_PHY_PARAM2)) & 0x0000ffff))
++#define SET_RX_FIFO_FAIL(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 1) | ((REG32(ADR_SPI_STS)) & 0xfffffffd))
++#define SET_RX_HOST_FAIL(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 2) | ((REG32(ADR_SPI_STS)) & 0xfffffffb))
++#define SET_TX_FIFO_FAIL(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 3) | ((REG32(ADR_SPI_STS)) & 0xfffffff7))
++#define SET_TX_HOST_FAIL(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 4) | ((REG32(ADR_SPI_STS)) & 0xffffffef))
++#define SET_SPI_DOUBLE_ALLOC(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 5) | ((REG32(ADR_SPI_STS)) & 0xffffffdf))
++#define SET_SPI_TX_NO_ALLOC(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 6) | ((REG32(ADR_SPI_STS)) & 0xffffffbf))
++#define SET_RDATA_RDY(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 7) | ((REG32(ADR_SPI_STS)) & 0xffffff7f))
++#define SET_SPI_ALLOC_STATUS(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 8) | ((REG32(ADR_SPI_STS)) & 0xfffffeff))
++#define SET_SPI_DBG_WR_FIFO_FULL(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 9) | ((REG32(ADR_SPI_STS)) & 0xfffffdff))
++#define SET_RX_LEN(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 16) | ((REG32(ADR_SPI_STS)) & 0x0000ffff))
++#define SET_SPI_TX_ALLOC_SIZE_SHIFT_BITS(_VAL_) (REG32(ADR_TX_ALLOC_SET)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ALLOC_SET)) & 0xfffffff8))
++#define SET_SPI_HOST_TX_ALLOC_PKBUF(_VAL_) (REG32(ADR_TX_ALLOC_SET)) = (((_VAL_) << 8) | ((REG32(ADR_TX_ALLOC_SET)) & 0xfffffeff))
++#define SET_SPI_TX_ALLOC_SIZE(_VAL_) (REG32(ADR_TX_ALLOC)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ALLOC)) & 0xffffff00))
++#define SET_RD_DAT_CNT(_VAL_) (REG32(ADR_DBG_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_CNT)) & 0xffff0000))
++#define SET_RD_STS_CNT(_VAL_) (REG32(ADR_DBG_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_CNT)) & 0x0000ffff))
++#define SET_JUDGE_CNT(_VAL_) (REG32(ADR_DBG_CNT2)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_CNT2)) & 0xffff0000))
++#define SET_RD_STS_CNT_CLR(_VAL_) (REG32(ADR_DBG_CNT2)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_CNT2)) & 0xfffeffff))
++#define SET_RD_DAT_CNT_CLR(_VAL_) (REG32(ADR_DBG_CNT2)) = (((_VAL_) << 17) | ((REG32(ADR_DBG_CNT2)) & 0xfffdffff))
++#define SET_JUDGE_CNT_CLR(_VAL_) (REG32(ADR_DBG_CNT2)) = (((_VAL_) << 18) | ((REG32(ADR_DBG_CNT2)) & 0xfffbffff))
++#define SET_TX_DONE_CNT(_VAL_) (REG32(ADR_DBG_CNT3)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_CNT3)) & 0xffff0000))
++#define SET_TX_DISCARD_CNT(_VAL_) (REG32(ADR_DBG_CNT3)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_CNT3)) & 0x0000ffff))
++#define SET_TX_SET_CNT(_VAL_) (REG32(ADR_DBG_CNT4)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_CNT4)) & 0xffff0000))
++#define SET_TX_DISCARD_CNT_CLR(_VAL_) (REG32(ADR_DBG_CNT4)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_CNT4)) & 0xfffeffff))
++#define SET_TX_DONE_CNT_CLR(_VAL_) (REG32(ADR_DBG_CNT4)) = (((_VAL_) << 17) | ((REG32(ADR_DBG_CNT4)) & 0xfffdffff))
++#define SET_TX_SET_CNT_CLR(_VAL_) (REG32(ADR_DBG_CNT4)) = (((_VAL_) << 18) | ((REG32(ADR_DBG_CNT4)) & 0xfffbffff))
++#define SET_DAT_MODE_OFF(_VAL_) (REG32(ADR_DBG_CNT4)) = (((_VAL_) << 19) | ((REG32(ADR_DBG_CNT4)) & 0xfff7ffff))
++#define SET_TX_FIFO_RESIDUE(_VAL_) (REG32(ADR_DBG_CNT4)) = (((_VAL_) << 20) | ((REG32(ADR_DBG_CNT4)) & 0xff8fffff))
++#define SET_RX_FIFO_RESIDUE(_VAL_) (REG32(ADR_DBG_CNT4)) = (((_VAL_) << 24) | ((REG32(ADR_DBG_CNT4)) & 0xf8ffffff))
++#define SET_RX_RDY(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 0) | ((REG32(ADR_INT_TAG)) & 0xfffffffe))
++#define SET_SDIO_SYS_INT(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 2) | ((REG32(ADR_INT_TAG)) & 0xfffffffb))
++#define SET_EDCA0_LOWTHOLD_INT(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 3) | ((REG32(ADR_INT_TAG)) & 0xfffffff7))
++#define SET_EDCA1_LOWTHOLD_INT(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 4) | ((REG32(ADR_INT_TAG)) & 0xffffffef))
++#define SET_EDCA2_LOWTHOLD_INT(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 5) | ((REG32(ADR_INT_TAG)) & 0xffffffdf))
++#define SET_EDCA3_LOWTHOLD_INT(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 6) | ((REG32(ADR_INT_TAG)) & 0xffffffbf))
++#define SET_TX_LIMIT_INT_IN(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 7) | ((REG32(ADR_INT_TAG)) & 0xffffff7f))
++#define SET_SPI_FN1(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 8) | ((REG32(ADR_INT_TAG)) & 0xffff80ff))
++#define SET_SPI_CLK_EN_INT(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 15) | ((REG32(ADR_INT_TAG)) & 0xffff7fff))
++#define SET_SPI_HOST_MASK(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 16) | ((REG32(ADR_INT_TAG)) & 0xff00ffff))
++#define SET_I2CM_INT_WDONE(_VAL_) (REG32(ADR_I2CM_EN)) = (((_VAL_) << 0) | ((REG32(ADR_I2CM_EN)) & 0xfffffffe))
++#define SET_I2CM_INT_RDONE(_VAL_) (REG32(ADR_I2CM_EN)) = (((_VAL_) << 1) | ((REG32(ADR_I2CM_EN)) & 0xfffffffd))
++#define SET_I2CM_IDLE(_VAL_) (REG32(ADR_I2CM_EN)) = (((_VAL_) << 2) | ((REG32(ADR_I2CM_EN)) & 0xfffffffb))
++#define SET_I2CM_INT_MISMATCH(_VAL_) (REG32(ADR_I2CM_EN)) = (((_VAL_) << 3) | ((REG32(ADR_I2CM_EN)) & 0xfffffff7))
++#define SET_I2CM_PSCL(_VAL_) (REG32(ADR_I2CM_EN)) = (((_VAL_) << 4) | ((REG32(ADR_I2CM_EN)) & 0xffffc00f))
++#define SET_I2CM_MANUAL_MODE(_VAL_) (REG32(ADR_I2CM_EN)) = (((_VAL_) << 16) | ((REG32(ADR_I2CM_EN)) & 0xfffeffff))
++#define SET_I2CM_INT_WDATA_NEED(_VAL_) (REG32(ADR_I2CM_EN)) = (((_VAL_) << 17) | ((REG32(ADR_I2CM_EN)) & 0xfffdffff))
++#define SET_I2CM_INT_RDATA_NEED(_VAL_) (REG32(ADR_I2CM_EN)) = (((_VAL_) << 18) | ((REG32(ADR_I2CM_EN)) & 0xfffbffff))
++#define SET_I2CM_DEV_A(_VAL_) (REG32(ADR_I2CM_DEV_A)) = (((_VAL_) << 0) | ((REG32(ADR_I2CM_DEV_A)) & 0xfffffc00))
++#define SET_I2CM_DEV_A10B(_VAL_) (REG32(ADR_I2CM_DEV_A)) = (((_VAL_) << 14) | ((REG32(ADR_I2CM_DEV_A)) & 0xffffbfff))
++#define SET_I2CM_RX(_VAL_) (REG32(ADR_I2CM_DEV_A)) = (((_VAL_) << 15) | ((REG32(ADR_I2CM_DEV_A)) & 0xffff7fff))
++#define SET_I2CM_LEN(_VAL_) (REG32(ADR_I2CM_LEN)) = (((_VAL_) << 0) | ((REG32(ADR_I2CM_LEN)) & 0xffff0000))
++#define SET_I2CM_T_LEFT(_VAL_) (REG32(ADR_I2CM_LEN)) = (((_VAL_) << 16) | ((REG32(ADR_I2CM_LEN)) & 0xfff8ffff))
++#define SET_I2CM_R_GET(_VAL_) (REG32(ADR_I2CM_LEN)) = (((_VAL_) << 24) | ((REG32(ADR_I2CM_LEN)) & 0xf8ffffff))
++#define SET_I2CM_WDAT(_VAL_) (REG32(ADR_I2CM_WDAT)) = (((_VAL_) << 0) | ((REG32(ADR_I2CM_WDAT)) & 0x00000000))
++#define SET_I2CM_RDAT(_VAL_) (REG32(ADR_I2CM_RDAT)) = (((_VAL_) << 0) | ((REG32(ADR_I2CM_RDAT)) & 0x00000000))
++#define SET_I2CM_SR_LEN(_VAL_) (REG32(ADR_I2CM_EN_2)) = (((_VAL_) << 0) | ((REG32(ADR_I2CM_EN_2)) & 0xffff0000))
++#define SET_I2CM_SR_RX(_VAL_) (REG32(ADR_I2CM_EN_2)) = (((_VAL_) << 16) | ((REG32(ADR_I2CM_EN_2)) & 0xfffeffff))
++#define SET_I2CM_REPEAT_START(_VAL_) (REG32(ADR_I2CM_EN_2)) = (((_VAL_) << 17) | ((REG32(ADR_I2CM_EN_2)) & 0xfffdffff))
++#define SET_UART_DATA(_VAL_) (REG32(ADR_UART_DATA)) = (((_VAL_) << 0) | ((REG32(ADR_UART_DATA)) & 0xffffff00))
++#define SET_DATA_RDY_IE(_VAL_) (REG32(ADR_UART_IER)) = (((_VAL_) << 0) | ((REG32(ADR_UART_IER)) & 0xfffffffe))
++#define SET_THR_EMPTY_IE(_VAL_) (REG32(ADR_UART_IER)) = (((_VAL_) << 1) | ((REG32(ADR_UART_IER)) & 0xfffffffd))
++#define SET_RX_LINESTS_IE(_VAL_) (REG32(ADR_UART_IER)) = (((_VAL_) << 2) | ((REG32(ADR_UART_IER)) & 0xfffffffb))
++#define SET_MDM_STS_IE(_VAL_) (REG32(ADR_UART_IER)) = (((_VAL_) << 3) | ((REG32(ADR_UART_IER)) & 0xfffffff7))
++#define SET_DMA_RXEND_IE(_VAL_) (REG32(ADR_UART_IER)) = (((_VAL_) << 6) | ((REG32(ADR_UART_IER)) & 0xffffffbf))
++#define SET_DMA_TXEND_IE(_VAL_) (REG32(ADR_UART_IER)) = (((_VAL_) << 7) | ((REG32(ADR_UART_IER)) & 0xffffff7f))
++#define SET_FIFO_EN(_VAL_) (REG32(ADR_UART_FCR)) = (((_VAL_) << 0) | ((REG32(ADR_UART_FCR)) & 0xfffffffe))
++#define SET_RXFIFO_RST(_VAL_) (REG32(ADR_UART_FCR)) = (((_VAL_) << 1) | ((REG32(ADR_UART_FCR)) & 0xfffffffd))
++#define SET_TXFIFO_RST(_VAL_) (REG32(ADR_UART_FCR)) = (((_VAL_) << 2) | ((REG32(ADR_UART_FCR)) & 0xfffffffb))
++#define SET_DMA_MODE(_VAL_) (REG32(ADR_UART_FCR)) = (((_VAL_) << 3) | ((REG32(ADR_UART_FCR)) & 0xfffffff7))
++#define SET_EN_AUTO_RTS(_VAL_) (REG32(ADR_UART_FCR)) = (((_VAL_) << 4) | ((REG32(ADR_UART_FCR)) & 0xffffffef))
++#define SET_EN_AUTO_CTS(_VAL_) (REG32(ADR_UART_FCR)) = (((_VAL_) << 5) | ((REG32(ADR_UART_FCR)) & 0xffffffdf))
++#define SET_RXFIFO_TRGLVL(_VAL_) (REG32(ADR_UART_FCR)) = (((_VAL_) << 6) | ((REG32(ADR_UART_FCR)) & 0xffffff3f))
++#define SET_WORD_LEN(_VAL_) (REG32(ADR_UART_LCR)) = (((_VAL_) << 0) | ((REG32(ADR_UART_LCR)) & 0xfffffffc))
++#define SET_STOP_BIT(_VAL_) (REG32(ADR_UART_LCR)) = (((_VAL_) << 2) | ((REG32(ADR_UART_LCR)) & 0xfffffffb))
++#define SET_PARITY_EN(_VAL_) (REG32(ADR_UART_LCR)) = (((_VAL_) << 3) | ((REG32(ADR_UART_LCR)) & 0xfffffff7))
++#define SET_EVEN_PARITY(_VAL_) (REG32(ADR_UART_LCR)) = (((_VAL_) << 4) | ((REG32(ADR_UART_LCR)) & 0xffffffef))
++#define SET_FORCE_PARITY(_VAL_) (REG32(ADR_UART_LCR)) = (((_VAL_) << 5) | ((REG32(ADR_UART_LCR)) & 0xffffffdf))
++#define SET_SET_BREAK(_VAL_) (REG32(ADR_UART_LCR)) = (((_VAL_) << 6) | ((REG32(ADR_UART_LCR)) & 0xffffffbf))
++#define SET_DLAB(_VAL_) (REG32(ADR_UART_LCR)) = (((_VAL_) << 7) | ((REG32(ADR_UART_LCR)) & 0xffffff7f))
++#define SET_DTR(_VAL_) (REG32(ADR_UART_MCR)) = (((_VAL_) << 0) | ((REG32(ADR_UART_MCR)) & 0xfffffffe))
++#define SET_RTS(_VAL_) (REG32(ADR_UART_MCR)) = (((_VAL_) << 1) | ((REG32(ADR_UART_MCR)) & 0xfffffffd))
++#define SET_OUT_1(_VAL_) (REG32(ADR_UART_MCR)) = (((_VAL_) << 2) | ((REG32(ADR_UART_MCR)) & 0xfffffffb))
++#define SET_OUT_2(_VAL_) (REG32(ADR_UART_MCR)) = (((_VAL_) << 3) | ((REG32(ADR_UART_MCR)) & 0xfffffff7))
++#define SET_LOOP_BACK(_VAL_) (REG32(ADR_UART_MCR)) = (((_VAL_) << 4) | ((REG32(ADR_UART_MCR)) & 0xffffffef))
++#define SET_DATA_RDY(_VAL_) (REG32(ADR_UART_LSR)) = (((_VAL_) << 0) | ((REG32(ADR_UART_LSR)) & 0xfffffffe))
++#define SET_OVERRUN_ERR(_VAL_) (REG32(ADR_UART_LSR)) = (((_VAL_) << 1) | ((REG32(ADR_UART_LSR)) & 0xfffffffd))
++#define SET_PARITY_ERR(_VAL_) (REG32(ADR_UART_LSR)) = (((_VAL_) << 2) | ((REG32(ADR_UART_LSR)) & 0xfffffffb))
++#define SET_FRAMING_ERR(_VAL_) (REG32(ADR_UART_LSR)) = (((_VAL_) << 3) | ((REG32(ADR_UART_LSR)) & 0xfffffff7))
++#define SET_BREAK_INT(_VAL_) (REG32(ADR_UART_LSR)) = (((_VAL_) << 4) | ((REG32(ADR_UART_LSR)) & 0xffffffef))
++#define SET_THR_EMPTY(_VAL_) (REG32(ADR_UART_LSR)) = (((_VAL_) << 5) | ((REG32(ADR_UART_LSR)) & 0xffffffdf))
++#define SET_TX_EMPTY(_VAL_) (REG32(ADR_UART_LSR)) = (((_VAL_) << 6) | ((REG32(ADR_UART_LSR)) & 0xffffffbf))
++#define SET_FIFODATA_ERR(_VAL_) (REG32(ADR_UART_LSR)) = (((_VAL_) << 7) | ((REG32(ADR_UART_LSR)) & 0xffffff7f))
++#define SET_DELTA_CTS(_VAL_) (REG32(ADR_UART_MSR)) = (((_VAL_) << 0) | ((REG32(ADR_UART_MSR)) & 0xfffffffe))
++#define SET_DELTA_DSR(_VAL_) (REG32(ADR_UART_MSR)) = (((_VAL_) << 1) | ((REG32(ADR_UART_MSR)) & 0xfffffffd))
++#define SET_TRAILEDGE_RI(_VAL_) (REG32(ADR_UART_MSR)) = (((_VAL_) << 2) | ((REG32(ADR_UART_MSR)) & 0xfffffffb))
++#define SET_DELTA_CD(_VAL_) (REG32(ADR_UART_MSR)) = (((_VAL_) << 3) | ((REG32(ADR_UART_MSR)) & 0xfffffff7))
++#define SET_CTS(_VAL_) (REG32(ADR_UART_MSR)) = (((_VAL_) << 4) | ((REG32(ADR_UART_MSR)) & 0xffffffef))
++#define SET_DSR(_VAL_) (REG32(ADR_UART_MSR)) = (((_VAL_) << 5) | ((REG32(ADR_UART_MSR)) & 0xffffffdf))
++#define SET_RI(_VAL_) (REG32(ADR_UART_MSR)) = (((_VAL_) << 6) | ((REG32(ADR_UART_MSR)) & 0xffffffbf))
++#define SET_CD(_VAL_) (REG32(ADR_UART_MSR)) = (((_VAL_) << 7) | ((REG32(ADR_UART_MSR)) & 0xffffff7f))
++#define SET_BRDC_DIV(_VAL_) (REG32(ADR_UART_SPR)) = (((_VAL_) << 0) | ((REG32(ADR_UART_SPR)) & 0xffff0000))
++#define SET_RTHR_L(_VAL_) (REG32(ADR_UART_RTHR)) = (((_VAL_) << 0) | ((REG32(ADR_UART_RTHR)) & 0xfffffff0))
++#define SET_RTHR_H(_VAL_) (REG32(ADR_UART_RTHR)) = (((_VAL_) << 4) | ((REG32(ADR_UART_RTHR)) & 0xffffff0f))
++#define SET_INT_IDCODE(_VAL_) (REG32(ADR_UART_ISR)) = (((_VAL_) << 0) | ((REG32(ADR_UART_ISR)) & 0xfffffff0))
++#define SET_FIFOS_ENABLED(_VAL_) (REG32(ADR_UART_ISR)) = (((_VAL_) << 6) | ((REG32(ADR_UART_ISR)) & 0xffffff3f))
++#define SET_DAT_UART_DATA(_VAL_) (REG32(ADR_DAT_UART_DATA)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_DATA)) & 0xffffff00))
++#define SET_DAT_DATA_RDY_IE(_VAL_) (REG32(ADR_DAT_UART_IER)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_IER)) & 0xfffffffe))
++#define SET_DAT_THR_EMPTY_IE(_VAL_) (REG32(ADR_DAT_UART_IER)) = (((_VAL_) << 1) | ((REG32(ADR_DAT_UART_IER)) & 0xfffffffd))
++#define SET_DAT_RX_LINESTS_IE(_VAL_) (REG32(ADR_DAT_UART_IER)) = (((_VAL_) << 2) | ((REG32(ADR_DAT_UART_IER)) & 0xfffffffb))
++#define SET_DAT_MDM_STS_IE(_VAL_) (REG32(ADR_DAT_UART_IER)) = (((_VAL_) << 3) | ((REG32(ADR_DAT_UART_IER)) & 0xfffffff7))
++#define SET_DAT_DMA_RXEND_IE(_VAL_) (REG32(ADR_DAT_UART_IER)) = (((_VAL_) << 6) | ((REG32(ADR_DAT_UART_IER)) & 0xffffffbf))
++#define SET_DAT_DMA_TXEND_IE(_VAL_) (REG32(ADR_DAT_UART_IER)) = (((_VAL_) << 7) | ((REG32(ADR_DAT_UART_IER)) & 0xffffff7f))
++#define SET_DAT_FIFO_EN(_VAL_) (REG32(ADR_DAT_UART_FCR)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_FCR)) & 0xfffffffe))
++#define SET_DAT_RXFIFO_RST(_VAL_) (REG32(ADR_DAT_UART_FCR)) = (((_VAL_) << 1) | ((REG32(ADR_DAT_UART_FCR)) & 0xfffffffd))
++#define SET_DAT_TXFIFO_RST(_VAL_) (REG32(ADR_DAT_UART_FCR)) = (((_VAL_) << 2) | ((REG32(ADR_DAT_UART_FCR)) & 0xfffffffb))
++#define SET_DAT_DMA_MODE(_VAL_) (REG32(ADR_DAT_UART_FCR)) = (((_VAL_) << 3) | ((REG32(ADR_DAT_UART_FCR)) & 0xfffffff7))
++#define SET_DAT_EN_AUTO_RTS(_VAL_) (REG32(ADR_DAT_UART_FCR)) = (((_VAL_) << 4) | ((REG32(ADR_DAT_UART_FCR)) & 0xffffffef))
++#define SET_DAT_EN_AUTO_CTS(_VAL_) (REG32(ADR_DAT_UART_FCR)) = (((_VAL_) << 5) | ((REG32(ADR_DAT_UART_FCR)) & 0xffffffdf))
++#define SET_DAT_RXFIFO_TRGLVL(_VAL_) (REG32(ADR_DAT_UART_FCR)) = (((_VAL_) << 6) | ((REG32(ADR_DAT_UART_FCR)) & 0xffffff3f))
++#define SET_DAT_WORD_LEN(_VAL_) (REG32(ADR_DAT_UART_LCR)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_LCR)) & 0xfffffffc))
++#define SET_DAT_STOP_BIT(_VAL_) (REG32(ADR_DAT_UART_LCR)) = (((_VAL_) << 2) | ((REG32(ADR_DAT_UART_LCR)) & 0xfffffffb))
++#define SET_DAT_PARITY_EN(_VAL_) (REG32(ADR_DAT_UART_LCR)) = (((_VAL_) << 3) | ((REG32(ADR_DAT_UART_LCR)) & 0xfffffff7))
++#define SET_DAT_EVEN_PARITY(_VAL_) (REG32(ADR_DAT_UART_LCR)) = (((_VAL_) << 4) | ((REG32(ADR_DAT_UART_LCR)) & 0xffffffef))
++#define SET_DAT_FORCE_PARITY(_VAL_) (REG32(ADR_DAT_UART_LCR)) = (((_VAL_) << 5) | ((REG32(ADR_DAT_UART_LCR)) & 0xffffffdf))
++#define SET_DAT_SET_BREAK(_VAL_) (REG32(ADR_DAT_UART_LCR)) = (((_VAL_) << 6) | ((REG32(ADR_DAT_UART_LCR)) & 0xffffffbf))
++#define SET_DAT_DLAB(_VAL_) (REG32(ADR_DAT_UART_LCR)) = (((_VAL_) << 7) | ((REG32(ADR_DAT_UART_LCR)) & 0xffffff7f))
++#define SET_DAT_DTR(_VAL_) (REG32(ADR_DAT_UART_MCR)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_MCR)) & 0xfffffffe))
++#define SET_DAT_RTS(_VAL_) (REG32(ADR_DAT_UART_MCR)) = (((_VAL_) << 1) | ((REG32(ADR_DAT_UART_MCR)) & 0xfffffffd))
++#define SET_DAT_OUT_1(_VAL_) (REG32(ADR_DAT_UART_MCR)) = (((_VAL_) << 2) | ((REG32(ADR_DAT_UART_MCR)) & 0xfffffffb))
++#define SET_DAT_OUT_2(_VAL_) (REG32(ADR_DAT_UART_MCR)) = (((_VAL_) << 3) | ((REG32(ADR_DAT_UART_MCR)) & 0xfffffff7))
++#define SET_DAT_LOOP_BACK(_VAL_) (REG32(ADR_DAT_UART_MCR)) = (((_VAL_) << 4) | ((REG32(ADR_DAT_UART_MCR)) & 0xffffffef))
++#define SET_DAT_DATA_RDY(_VAL_) (REG32(ADR_DAT_UART_LSR)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_LSR)) & 0xfffffffe))
++#define SET_DAT_OVERRUN_ERR(_VAL_) (REG32(ADR_DAT_UART_LSR)) = (((_VAL_) << 1) | ((REG32(ADR_DAT_UART_LSR)) & 0xfffffffd))
++#define SET_DAT_PARITY_ERR(_VAL_) (REG32(ADR_DAT_UART_LSR)) = (((_VAL_) << 2) | ((REG32(ADR_DAT_UART_LSR)) & 0xfffffffb))
++#define SET_DAT_FRAMING_ERR(_VAL_) (REG32(ADR_DAT_UART_LSR)) = (((_VAL_) << 3) | ((REG32(ADR_DAT_UART_LSR)) & 0xfffffff7))
++#define SET_DAT_BREAK_INT(_VAL_) (REG32(ADR_DAT_UART_LSR)) = (((_VAL_) << 4) | ((REG32(ADR_DAT_UART_LSR)) & 0xffffffef))
++#define SET_DAT_THR_EMPTY(_VAL_) (REG32(ADR_DAT_UART_LSR)) = (((_VAL_) << 5) | ((REG32(ADR_DAT_UART_LSR)) & 0xffffffdf))
++#define SET_DAT_TX_EMPTY(_VAL_) (REG32(ADR_DAT_UART_LSR)) = (((_VAL_) << 6) | ((REG32(ADR_DAT_UART_LSR)) & 0xffffffbf))
++#define SET_DAT_FIFODATA_ERR(_VAL_) (REG32(ADR_DAT_UART_LSR)) = (((_VAL_) << 7) | ((REG32(ADR_DAT_UART_LSR)) & 0xffffff7f))
++#define SET_DAT_DELTA_CTS(_VAL_) (REG32(ADR_DAT_UART_MSR)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_MSR)) & 0xfffffffe))
++#define SET_DAT_DELTA_DSR(_VAL_) (REG32(ADR_DAT_UART_MSR)) = (((_VAL_) << 1) | ((REG32(ADR_DAT_UART_MSR)) & 0xfffffffd))
++#define SET_DAT_TRAILEDGE_RI(_VAL_) (REG32(ADR_DAT_UART_MSR)) = (((_VAL_) << 2) | ((REG32(ADR_DAT_UART_MSR)) & 0xfffffffb))
++#define SET_DAT_DELTA_CD(_VAL_) (REG32(ADR_DAT_UART_MSR)) = (((_VAL_) << 3) | ((REG32(ADR_DAT_UART_MSR)) & 0xfffffff7))
++#define SET_DAT_CTS(_VAL_) (REG32(ADR_DAT_UART_MSR)) = (((_VAL_) << 4) | ((REG32(ADR_DAT_UART_MSR)) & 0xffffffef))
++#define SET_DAT_DSR(_VAL_) (REG32(ADR_DAT_UART_MSR)) = (((_VAL_) << 5) | ((REG32(ADR_DAT_UART_MSR)) & 0xffffffdf))
++#define SET_DAT_RI(_VAL_) (REG32(ADR_DAT_UART_MSR)) = (((_VAL_) << 6) | ((REG32(ADR_DAT_UART_MSR)) & 0xffffffbf))
++#define SET_DAT_CD(_VAL_) (REG32(ADR_DAT_UART_MSR)) = (((_VAL_) << 7) | ((REG32(ADR_DAT_UART_MSR)) & 0xffffff7f))
++#define SET_DAT_BRDC_DIV(_VAL_) (REG32(ADR_DAT_UART_SPR)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_SPR)) & 0xffff0000))
++#define SET_DAT_RTHR_L(_VAL_) (REG32(ADR_DAT_UART_RTHR)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_RTHR)) & 0xfffffff0))
++#define SET_DAT_RTHR_H(_VAL_) (REG32(ADR_DAT_UART_RTHR)) = (((_VAL_) << 4) | ((REG32(ADR_DAT_UART_RTHR)) & 0xffffff0f))
++#define SET_DAT_INT_IDCODE(_VAL_) (REG32(ADR_DAT_UART_ISR)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_ISR)) & 0xfffffff0))
++#define SET_DAT_FIFOS_ENABLED(_VAL_) (REG32(ADR_DAT_UART_ISR)) = (((_VAL_) << 6) | ((REG32(ADR_DAT_UART_ISR)) & 0xffffff3f))
++#define SET_MASK_TOP(_VAL_) (REG32(ADR_INT_MASK)) = (((_VAL_) << 0) | ((REG32(ADR_INT_MASK)) & 0x00000000))
++#define SET_INT_MODE(_VAL_) (REG32(ADR_INT_MODE)) = (((_VAL_) << 0) | ((REG32(ADR_INT_MODE)) & 0x00000000))
++#define SET_IRQ_PHY_0(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 0) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffffffe))
++#define SET_IRQ_PHY_1(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 1) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffffffd))
++#define SET_IRQ_SDIO(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 2) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffffffb))
++#define SET_IRQ_BEACON_DONE(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 3) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffffff7))
++#define SET_IRQ_BEACON(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 4) | ((REG32(ADR_INT_IRQ_STS)) & 0xffffffef))
++#define SET_IRQ_PRE_BEACON(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 5) | ((REG32(ADR_INT_IRQ_STS)) & 0xffffffdf))
++#define SET_IRQ_EDCA0_TX_DONE(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 6) | ((REG32(ADR_INT_IRQ_STS)) & 0xffffffbf))
++#define SET_IRQ_EDCA1_TX_DONE(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 7) | ((REG32(ADR_INT_IRQ_STS)) & 0xffffff7f))
++#define SET_IRQ_EDCA2_TX_DONE(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 8) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffffeff))
++#define SET_IRQ_EDCA3_TX_DONE(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 9) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffffdff))
++#define SET_IRQ_EDCA4_TX_DONE(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 10) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffffbff))
++#define SET_IRQ_BEACON_DTIM(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 12) | ((REG32(ADR_INT_IRQ_STS)) & 0xffffefff))
++#define SET_IRQ_EDCA0_LOWTHOLD_INT(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 13) | ((REG32(ADR_INT_IRQ_STS)) & 0xffffdfff))
++#define SET_IRQ_EDCA1_LOWTHOLD_INT(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 14) | ((REG32(ADR_INT_IRQ_STS)) & 0xffffbfff))
++#define SET_IRQ_EDCA2_LOWTHOLD_INT(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 15) | ((REG32(ADR_INT_IRQ_STS)) & 0xffff7fff))
++#define SET_IRQ_EDCA3_LOWTHOLD_INT(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 16) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffeffff))
++#define SET_IRQ_FENCE_HIT_INT(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 17) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffdffff))
++#define SET_IRQ_ILL_ADDR_INT(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 18) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffbffff))
++#define SET_IRQ_MBOX(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 19) | ((REG32(ADR_INT_IRQ_STS)) & 0xfff7ffff))
++#define SET_IRQ_US_TIMER0(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 20) | ((REG32(ADR_INT_IRQ_STS)) & 0xffefffff))
++#define SET_IRQ_US_TIMER1(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 21) | ((REG32(ADR_INT_IRQ_STS)) & 0xffdfffff))
++#define SET_IRQ_US_TIMER2(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 22) | ((REG32(ADR_INT_IRQ_STS)) & 0xffbfffff))
++#define SET_IRQ_US_TIMER3(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 23) | ((REG32(ADR_INT_IRQ_STS)) & 0xff7fffff))
++#define SET_IRQ_MS_TIMER0(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 24) | ((REG32(ADR_INT_IRQ_STS)) & 0xfeffffff))
++#define SET_IRQ_MS_TIMER1(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 25) | ((REG32(ADR_INT_IRQ_STS)) & 0xfdffffff))
++#define SET_IRQ_MS_TIMER2(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 26) | ((REG32(ADR_INT_IRQ_STS)) & 0xfbffffff))
++#define SET_IRQ_MS_TIMER3(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 27) | ((REG32(ADR_INT_IRQ_STS)) & 0xf7ffffff))
++#define SET_IRQ_TX_LIMIT_INT(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 28) | ((REG32(ADR_INT_IRQ_STS)) & 0xefffffff))
++#define SET_IRQ_DMA0(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 29) | ((REG32(ADR_INT_IRQ_STS)) & 0xdfffffff))
++#define SET_IRQ_CO_DMA(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 30) | ((REG32(ADR_INT_IRQ_STS)) & 0xbfffffff))
++#define SET_IRQ_PERI_GROUP(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 31) | ((REG32(ADR_INT_IRQ_STS)) & 0x7fffffff))
++#define SET_FIQ_STATUS(_VAL_) (REG32(ADR_INT_FIQ_STS)) = (((_VAL_) << 0) | ((REG32(ADR_INT_FIQ_STS)) & 0x00000000))
++#define SET_IRQ_RAW(_VAL_) (REG32(ADR_INT_IRQ_RAW)) = (((_VAL_) << 0) | ((REG32(ADR_INT_IRQ_RAW)) & 0x00000000))
++#define SET_FIQ_RAW(_VAL_) (REG32(ADR_INT_FIQ_RAW)) = (((_VAL_) << 0) | ((REG32(ADR_INT_FIQ_RAW)) & 0x00000000))
++#define SET_INT_PERI_MASK(_VAL_) (REG32(ADR_INT_PERI_MASK)) = (((_VAL_) << 0) | ((REG32(ADR_INT_PERI_MASK)) & 0x00000000))
++#define SET_PERI_RTC(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 0) | ((REG32(ADR_INT_PERI_STS)) & 0xfffffffe))
++#define SET_IRQ_UART0_TX(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 1) | ((REG32(ADR_INT_PERI_STS)) & 0xfffffffd))
++#define SET_IRQ_UART0_RX(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 2) | ((REG32(ADR_INT_PERI_STS)) & 0xfffffffb))
++#define SET_PERI_GPI_2(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 3) | ((REG32(ADR_INT_PERI_STS)) & 0xfffffff7))
++#define SET_IRQ_SPI_IPC(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 4) | ((REG32(ADR_INT_PERI_STS)) & 0xffffffef))
++#define SET_PERI_GPI_1_0(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 5) | ((REG32(ADR_INT_PERI_STS)) & 0xffffff9f))
++#define SET_SCRT_INT_1(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 7) | ((REG32(ADR_INT_PERI_STS)) & 0xffffff7f))
++#define SET_MMU_ALC_ERR(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 8) | ((REG32(ADR_INT_PERI_STS)) & 0xfffffeff))
++#define SET_MMU_RLS_ERR(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 9) | ((REG32(ADR_INT_PERI_STS)) & 0xfffffdff))
++#define SET_ID_MNG_INT_1(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 10) | ((REG32(ADR_INT_PERI_STS)) & 0xfffffbff))
++#define SET_MBOX_INT_1(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 11) | ((REG32(ADR_INT_PERI_STS)) & 0xfffff7ff))
++#define SET_MBOX_INT_2(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 12) | ((REG32(ADR_INT_PERI_STS)) & 0xffffefff))
++#define SET_MBOX_INT_3(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 13) | ((REG32(ADR_INT_PERI_STS)) & 0xffffdfff))
++#define SET_HCI_INT_1(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 14) | ((REG32(ADR_INT_PERI_STS)) & 0xffffbfff))
++#define SET_UART_RX_TIMEOUT(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 15) | ((REG32(ADR_INT_PERI_STS)) & 0xffff7fff))
++#define SET_UART_MULTI_IRQ(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 16) | ((REG32(ADR_INT_PERI_STS)) & 0xfffeffff))
++#define SET_ID_MNG_INT_2(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 17) | ((REG32(ADR_INT_PERI_STS)) & 0xfffdffff))
++#define SET_DMN_NOHIT_INT(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 18) | ((REG32(ADR_INT_PERI_STS)) & 0xfffbffff))
++#define SET_ID_THOLD_RX(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 19) | ((REG32(ADR_INT_PERI_STS)) & 0xfff7ffff))
++#define SET_ID_THOLD_TX(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 20) | ((REG32(ADR_INT_PERI_STS)) & 0xffefffff))
++#define SET_ID_DOUBLE_RLS(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 21) | ((REG32(ADR_INT_PERI_STS)) & 0xffdfffff))
++#define SET_RX_ID_LEN_THOLD(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 22) | ((REG32(ADR_INT_PERI_STS)) & 0xffbfffff))
++#define SET_TX_ID_LEN_THOLD(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 23) | ((REG32(ADR_INT_PERI_STS)) & 0xff7fffff))
++#define SET_ALL_ID_LEN_THOLD(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 24) | ((REG32(ADR_INT_PERI_STS)) & 0xfeffffff))
++#define SET_DMN_MCU_INT(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 25) | ((REG32(ADR_INT_PERI_STS)) & 0xfdffffff))
++#define SET_IRQ_DAT_UART_TX(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 26) | ((REG32(ADR_INT_PERI_STS)) & 0xfbffffff))
++#define SET_IRQ_DAT_UART_RX(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 27) | ((REG32(ADR_INT_PERI_STS)) & 0xf7ffffff))
++#define SET_DAT_UART_RX_TIMEOUT(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 28) | ((REG32(ADR_INT_PERI_STS)) & 0xefffffff))
++#define SET_DAT_UART_MULTI_IRQ(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 29) | ((REG32(ADR_INT_PERI_STS)) & 0xdfffffff))
++#define SET_ALR_ABT_NOCHG_INT_IRQ(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 30) | ((REG32(ADR_INT_PERI_STS)) & 0xbfffffff))
++#define SET_TBLNEQ_MNGPKT_INT_IRQ(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 31) | ((REG32(ADR_INT_PERI_STS)) & 0x7fffffff))
++#define SET_INTR_PERI_RAW(_VAL_) (REG32(ADR_INT_PERI_RAW)) = (((_VAL_) << 0) | ((REG32(ADR_INT_PERI_RAW)) & 0x00000000))
++#define SET_INTR_GPI00_CFG(_VAL_) (REG32(ADR_INT_GPI_CFG)) = (((_VAL_) << 0) | ((REG32(ADR_INT_GPI_CFG)) & 0xfffffffc))
++#define SET_INTR_GPI01_CFG(_VAL_) (REG32(ADR_INT_GPI_CFG)) = (((_VAL_) << 2) | ((REG32(ADR_INT_GPI_CFG)) & 0xfffffff3))
++#define SET_SYS_RST_INT(_VAL_) (REG32(ADR_SYS_INT_FOR_HOST)) = (((_VAL_) << 0) | ((REG32(ADR_SYS_INT_FOR_HOST)) & 0xfffffffe))
++#define SET_SPI_IPC_ADDR(_VAL_) (REG32(ADR_SPI_IPC)) = (((_VAL_) << 0) | ((REG32(ADR_SPI_IPC)) & 0x00000000))
++#define SET_SD_MASK_TOP(_VAL_) (REG32(ADR_SDIO_MASK)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_MASK)) & 0x00000000))
++#define SET_IRQ_PHY_0_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffffffe))
++#define SET_IRQ_PHY_1_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 1) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffffffd))
++#define SET_IRQ_SDIO_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 2) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffffffb))
++#define SET_IRQ_BEACON_DONE_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 3) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffffff7))
++#define SET_IRQ_BEACON_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 4) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffffffef))
++#define SET_IRQ_PRE_BEACON_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 5) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffffffdf))
++#define SET_IRQ_EDCA0_TX_DONE_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 6) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffffffbf))
++#define SET_IRQ_EDCA1_TX_DONE_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 7) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffffff7f))
++#define SET_IRQ_EDCA2_TX_DONE_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 8) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffffeff))
++#define SET_IRQ_EDCA3_TX_DONE_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 9) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffffdff))
++#define SET_IRQ_EDCA4_TX_DONE_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 10) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffffbff))
++#define SET_IRQ_BEACON_DTIM_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 12) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffffefff))
++#define SET_IRQ_EDCA0_LOWTHOLD_INT_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 13) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffffdfff))
++#define SET_IRQ_EDCA1_LOWTHOLD_INT_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 14) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffffbfff))
++#define SET_IRQ_EDCA2_LOWTHOLD_INT_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 15) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffff7fff))
++#define SET_IRQ_EDCA3_LOWTHOLD_INT_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 16) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffeffff))
++#define SET_IRQ_FENCE_HIT_INT_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 17) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffdffff))
++#define SET_IRQ_ILL_ADDR_INT_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 18) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffbffff))
++#define SET_IRQ_MBOX_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 19) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfff7ffff))
++#define SET_IRQ_US_TIMER0_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 20) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffefffff))
++#define SET_IRQ_US_TIMER1_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 21) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffdfffff))
++#define SET_IRQ_US_TIMER2_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 22) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffbfffff))
++#define SET_IRQ_US_TIMER3_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 23) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xff7fffff))
++#define SET_IRQ_MS_TIMER0_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 24) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfeffffff))
++#define SET_IRQ_MS_TIMER1_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 25) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfdffffff))
++#define SET_IRQ_MS_TIMER2_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 26) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfbffffff))
++#define SET_IRQ_MS_TIMER3_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 27) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xf7ffffff))
++#define SET_IRQ_TX_LIMIT_INT_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 28) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xefffffff))
++#define SET_IRQ_DMA0_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 29) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xdfffffff))
++#define SET_IRQ_CO_DMA_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 30) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xbfffffff))
++#define SET_IRQ_PERI_GROUP_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 31) | ((REG32(ADR_SDIO_IRQ_STS)) & 0x7fffffff))
++#define SET_INT_PERI_MASK_SD(_VAL_) (REG32(ADR_SD_PERI_MASK)) = (((_VAL_) << 0) | ((REG32(ADR_SD_PERI_MASK)) & 0x00000000))
++#define SET_PERI_RTC_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 0) | ((REG32(ADR_SD_PERI_STS)) & 0xfffffffe))
++#define SET_IRQ_UART0_TX_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 1) | ((REG32(ADR_SD_PERI_STS)) & 0xfffffffd))
++#define SET_IRQ_UART0_RX_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 2) | ((REG32(ADR_SD_PERI_STS)) & 0xfffffffb))
++#define SET_PERI_GPI_SD_2(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 3) | ((REG32(ADR_SD_PERI_STS)) & 0xfffffff7))
++#define SET_IRQ_SPI_IPC_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 4) | ((REG32(ADR_SD_PERI_STS)) & 0xffffffef))
++#define SET_PERI_GPI_SD_1_0(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 5) | ((REG32(ADR_SD_PERI_STS)) & 0xffffff9f))
++#define SET_SCRT_INT_1_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 7) | ((REG32(ADR_SD_PERI_STS)) & 0xffffff7f))
++#define SET_MMU_ALC_ERR_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 8) | ((REG32(ADR_SD_PERI_STS)) & 0xfffffeff))
++#define SET_MMU_RLS_ERR_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 9) | ((REG32(ADR_SD_PERI_STS)) & 0xfffffdff))
++#define SET_ID_MNG_INT_1_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 10) | ((REG32(ADR_SD_PERI_STS)) & 0xfffffbff))
++#define SET_MBOX_INT_1_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 11) | ((REG32(ADR_SD_PERI_STS)) & 0xfffff7ff))
++#define SET_MBOX_INT_2_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 12) | ((REG32(ADR_SD_PERI_STS)) & 0xffffefff))
++#define SET_MBOX_INT_3_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 13) | ((REG32(ADR_SD_PERI_STS)) & 0xffffdfff))
++#define SET_HCI_INT_1_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 14) | ((REG32(ADR_SD_PERI_STS)) & 0xffffbfff))
++#define SET_UART_RX_TIMEOUT_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 15) | ((REG32(ADR_SD_PERI_STS)) & 0xffff7fff))
++#define SET_UART_MULTI_IRQ_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 16) | ((REG32(ADR_SD_PERI_STS)) & 0xfffeffff))
++#define SET_ID_MNG_INT_2_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 17) | ((REG32(ADR_SD_PERI_STS)) & 0xfffdffff))
++#define SET_DMN_NOHIT_INT_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 18) | ((REG32(ADR_SD_PERI_STS)) & 0xfffbffff))
++#define SET_ID_THOLD_RX_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 19) | ((REG32(ADR_SD_PERI_STS)) & 0xfff7ffff))
++#define SET_ID_THOLD_TX_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 20) | ((REG32(ADR_SD_PERI_STS)) & 0xffefffff))
++#define SET_ID_DOUBLE_RLS_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 21) | ((REG32(ADR_SD_PERI_STS)) & 0xffdfffff))
++#define SET_RX_ID_LEN_THOLD_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 22) | ((REG32(ADR_SD_PERI_STS)) & 0xffbfffff))
++#define SET_TX_ID_LEN_THOLD_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 23) | ((REG32(ADR_SD_PERI_STS)) & 0xff7fffff))
++#define SET_ALL_ID_LEN_THOLD_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 24) | ((REG32(ADR_SD_PERI_STS)) & 0xfeffffff))
++#define SET_DMN_MCU_INT_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 25) | ((REG32(ADR_SD_PERI_STS)) & 0xfdffffff))
++#define SET_IRQ_DAT_UART_TX_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 26) | ((REG32(ADR_SD_PERI_STS)) & 0xfbffffff))
++#define SET_IRQ_DAT_UART_RX_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 27) | ((REG32(ADR_SD_PERI_STS)) & 0xf7ffffff))
++#define SET_DAT_UART_RX_TIMEOUT_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 28) | ((REG32(ADR_SD_PERI_STS)) & 0xefffffff))
++#define SET_DAT_UART_MULTI_IRQ_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 29) | ((REG32(ADR_SD_PERI_STS)) & 0xdfffffff))
++#define SET_ALR_ABT_NOCHG_INT_IRQ_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 30) | ((REG32(ADR_SD_PERI_STS)) & 0xbfffffff))
++#define SET_TBLNEQ_MNGPKT_INT_IRQ_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 31) | ((REG32(ADR_SD_PERI_STS)) & 0x7fffffff))
++#define SET_DBG_SPI_MODE(_VAL_) (REG32(ADR_DBG_SPI_MODE)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_SPI_MODE)) & 0x00000000))
++#define SET_DBG_RX_QUOTA(_VAL_) (REG32(ADR_DBG_RX_QUOTA)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_RX_QUOTA)) & 0xffff0000))
++#define SET_DBG_CONDI_NUM(_VAL_) (REG32(ADR_DBG_CONDITION_NUMBER)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_CONDITION_NUMBER)) & 0xffffff00))
++#define SET_DBG_HOST_PATH(_VAL_) (REG32(ADR_DBG_HOST_PATH)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_HOST_PATH)) & 0xfffffffe))
++#define SET_DBG_TX_SEG(_VAL_) (REG32(ADR_DBG_TX_SEG)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_TX_SEG)) & 0x00000000))
++#define SET_DBG_BRST_MODE(_VAL_) (REG32(ADR_DBG_DEBUG_BURST_MODE)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_DEBUG_BURST_MODE)) & 0xfffffffe))
++#define SET_DBG_CLK_WIDTH(_VAL_) (REG32(ADR_DBG_SPI_TO_PHY_PARAM1)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_SPI_TO_PHY_PARAM1)) & 0xffff0000))
++#define SET_DBG_CSN_INTER(_VAL_) (REG32(ADR_DBG_SPI_TO_PHY_PARAM1)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_SPI_TO_PHY_PARAM1)) & 0x0000ffff))
++#define SET_DBG_BACK_DLY(_VAL_) (REG32(ADR_DBG_SPI_TO_PHY_PARAM2)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_SPI_TO_PHY_PARAM2)) & 0xffff0000))
++#define SET_DBG_FRONT_DLY(_VAL_) (REG32(ADR_DBG_SPI_TO_PHY_PARAM2)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_SPI_TO_PHY_PARAM2)) & 0x0000ffff))
++#define SET_DBG_RX_FIFO_FAIL(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 1) | ((REG32(ADR_DBG_SPI_STS)) & 0xfffffffd))
++#define SET_DBG_RX_HOST_FAIL(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 2) | ((REG32(ADR_DBG_SPI_STS)) & 0xfffffffb))
++#define SET_DBG_TX_FIFO_FAIL(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 3) | ((REG32(ADR_DBG_SPI_STS)) & 0xfffffff7))
++#define SET_DBG_TX_HOST_FAIL(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 4) | ((REG32(ADR_DBG_SPI_STS)) & 0xffffffef))
++#define SET_DBG_SPI_DOUBLE_ALLOC(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 5) | ((REG32(ADR_DBG_SPI_STS)) & 0xffffffdf))
++#define SET_DBG_SPI_TX_NO_ALLOC(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 6) | ((REG32(ADR_DBG_SPI_STS)) & 0xffffffbf))
++#define SET_DBG_RDATA_RDY(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 7) | ((REG32(ADR_DBG_SPI_STS)) & 0xffffff7f))
++#define SET_DBG_SPI_ALLOC_STATUS(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 8) | ((REG32(ADR_DBG_SPI_STS)) & 0xfffffeff))
++#define SET_DBG_SPI_DBG_WR_FIFO_FULL(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 9) | ((REG32(ADR_DBG_SPI_STS)) & 0xfffffdff))
++#define SET_DBG_RX_LEN(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_SPI_STS)) & 0x0000ffff))
++#define SET_DBG_SPI_TX_ALLOC_SIZE_SHIFT_BITS(_VAL_) (REG32(ADR_DBG_TX_ALLOC_SET)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_TX_ALLOC_SET)) & 0xfffffff8))
++#define SET_DBG_SPI_HOST_TX_ALLOC_PKBUF(_VAL_) (REG32(ADR_DBG_TX_ALLOC_SET)) = (((_VAL_) << 8) | ((REG32(ADR_DBG_TX_ALLOC_SET)) & 0xfffffeff))
++#define SET_DBG_SPI_TX_ALLOC_SIZE(_VAL_) (REG32(ADR_DBG_TX_ALLOC)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_TX_ALLOC)) & 0xffffff00))
++#define SET_DBG_RD_DAT_CNT(_VAL_) (REG32(ADR_DBG_DBG_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_DBG_CNT)) & 0xffff0000))
++#define SET_DBG_RD_STS_CNT(_VAL_) (REG32(ADR_DBG_DBG_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_DBG_CNT)) & 0x0000ffff))
++#define SET_DBG_JUDGE_CNT(_VAL_) (REG32(ADR_DBG_DBG_CNT2)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_DBG_CNT2)) & 0xffff0000))
++#define SET_DBG_RD_STS_CNT_CLR(_VAL_) (REG32(ADR_DBG_DBG_CNT2)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_DBG_CNT2)) & 0xfffeffff))
++#define SET_DBG_RD_DAT_CNT_CLR(_VAL_) (REG32(ADR_DBG_DBG_CNT2)) = (((_VAL_) << 17) | ((REG32(ADR_DBG_DBG_CNT2)) & 0xfffdffff))
++#define SET_DBG_JUDGE_CNT_CLR(_VAL_) (REG32(ADR_DBG_DBG_CNT2)) = (((_VAL_) << 18) | ((REG32(ADR_DBG_DBG_CNT2)) & 0xfffbffff))
++#define SET_DBG_TX_DONE_CNT(_VAL_) (REG32(ADR_DBG_DBG_CNT3)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_DBG_CNT3)) & 0xffff0000))
++#define SET_DBG_TX_DISCARD_CNT(_VAL_) (REG32(ADR_DBG_DBG_CNT3)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_DBG_CNT3)) & 0x0000ffff))
++#define SET_DBG_TX_SET_CNT(_VAL_) (REG32(ADR_DBG_DBG_CNT4)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_DBG_CNT4)) & 0xffff0000))
++#define SET_DBG_TX_DISCARD_CNT_CLR(_VAL_) (REG32(ADR_DBG_DBG_CNT4)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_DBG_CNT4)) & 0xfffeffff))
++#define SET_DBG_TX_DONE_CNT_CLR(_VAL_) (REG32(ADR_DBG_DBG_CNT4)) = (((_VAL_) << 17) | ((REG32(ADR_DBG_DBG_CNT4)) & 0xfffdffff))
++#define SET_DBG_TX_SET_CNT_CLR(_VAL_) (REG32(ADR_DBG_DBG_CNT4)) = (((_VAL_) << 18) | ((REG32(ADR_DBG_DBG_CNT4)) & 0xfffbffff))
++#define SET_DBG_DAT_MODE_OFF(_VAL_) (REG32(ADR_DBG_DBG_CNT4)) = (((_VAL_) << 19) | ((REG32(ADR_DBG_DBG_CNT4)) & 0xfff7ffff))
++#define SET_DBG_TX_FIFO_RESIDUE(_VAL_) (REG32(ADR_DBG_DBG_CNT4)) = (((_VAL_) << 20) | ((REG32(ADR_DBG_DBG_CNT4)) & 0xff8fffff))
++#define SET_DBG_RX_FIFO_RESIDUE(_VAL_) (REG32(ADR_DBG_DBG_CNT4)) = (((_VAL_) << 24) | ((REG32(ADR_DBG_DBG_CNT4)) & 0xf8ffffff))
++#define SET_DBG_RX_RDY(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_INT_TAG)) & 0xfffffffe))
++#define SET_DBG_SDIO_SYS_INT(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 2) | ((REG32(ADR_DBG_INT_TAG)) & 0xfffffffb))
++#define SET_DBG_EDCA0_LOWTHOLD_INT(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 3) | ((REG32(ADR_DBG_INT_TAG)) & 0xfffffff7))
++#define SET_DBG_EDCA1_LOWTHOLD_INT(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 4) | ((REG32(ADR_DBG_INT_TAG)) & 0xffffffef))
++#define SET_DBG_EDCA2_LOWTHOLD_INT(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 5) | ((REG32(ADR_DBG_INT_TAG)) & 0xffffffdf))
++#define SET_DBG_EDCA3_LOWTHOLD_INT(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 6) | ((REG32(ADR_DBG_INT_TAG)) & 0xffffffbf))
++#define SET_DBG_TX_LIMIT_INT_IN(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 7) | ((REG32(ADR_DBG_INT_TAG)) & 0xffffff7f))
++#define SET_DBG_SPI_FN1(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 8) | ((REG32(ADR_DBG_INT_TAG)) & 0xffff80ff))
++#define SET_DBG_SPI_CLK_EN_INT(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 15) | ((REG32(ADR_DBG_INT_TAG)) & 0xffff7fff))
++#define SET_DBG_SPI_HOST_MASK(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_INT_TAG)) & 0xff00ffff))
++#define SET_BOOT_ADDR(_VAL_) (REG32(ADR_BOOT_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_BOOT_ADDR)) & 0xff000000))
++#define SET_CHECK_SUM_FAIL(_VAL_) (REG32(ADR_BOOT_ADDR)) = (((_VAL_) << 31) | ((REG32(ADR_BOOT_ADDR)) & 0x7fffffff))
++#define SET_VERIFY_DATA(_VAL_) (REG32(ADR_VERIFY_DATA)) = (((_VAL_) << 0) | ((REG32(ADR_VERIFY_DATA)) & 0x00000000))
++#define SET_FLASH_ADDR(_VAL_) (REG32(ADR_FLASH_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_FLASH_ADDR)) & 0xff000000))
++#define SET_FLASH_CMD_CLR(_VAL_) (REG32(ADR_FLASH_ADDR)) = (((_VAL_) << 28) | ((REG32(ADR_FLASH_ADDR)) & 0xefffffff))
++#define SET_FLASH_DMA_CLR(_VAL_) (REG32(ADR_FLASH_ADDR)) = (((_VAL_) << 29) | ((REG32(ADR_FLASH_ADDR)) & 0xdfffffff))
++#define SET_DMA_EN(_VAL_) (REG32(ADR_FLASH_ADDR)) = (((_VAL_) << 30) | ((REG32(ADR_FLASH_ADDR)) & 0xbfffffff))
++#define SET_DMA_BUSY(_VAL_) (REG32(ADR_FLASH_ADDR)) = (((_VAL_) << 31) | ((REG32(ADR_FLASH_ADDR)) & 0x7fffffff))
++#define SET_SRAM_ADDR(_VAL_) (REG32(ADR_SRAM_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_SRAM_ADDR)) & 0x00000000))
++#define SET_FLASH_DMA_LEN(_VAL_) (REG32(ADR_LEN)) = (((_VAL_) << 0) | ((REG32(ADR_LEN)) & 0x00000000))
++#define SET_FLASH_FRONT_DLY(_VAL_) (REG32(ADR_SPI_PARAM)) = (((_VAL_) << 0) | ((REG32(ADR_SPI_PARAM)) & 0xffff0000))
++#define SET_FLASH_BACK_DLY(_VAL_) (REG32(ADR_SPI_PARAM)) = (((_VAL_) << 16) | ((REG32(ADR_SPI_PARAM)) & 0x0000ffff))
++#define SET_FLASH_CLK_WIDTH(_VAL_) (REG32(ADR_SPI_PARAM2)) = (((_VAL_) << 0) | ((REG32(ADR_SPI_PARAM2)) & 0xffff0000))
++#define SET_SPI_BUSY(_VAL_) (REG32(ADR_SPI_PARAM2)) = (((_VAL_) << 16) | ((REG32(ADR_SPI_PARAM2)) & 0xfffeffff))
++#define SET_FLS_REMAP(_VAL_) (REG32(ADR_SPI_PARAM2)) = (((_VAL_) << 17) | ((REG32(ADR_SPI_PARAM2)) & 0xfffdffff))
++#define SET_PBUS_SWP(_VAL_) (REG32(ADR_SPI_PARAM2)) = (((_VAL_) << 18) | ((REG32(ADR_SPI_PARAM2)) & 0xfffbffff))
++#define SET_BIT_MODE1(_VAL_) (REG32(ADR_SPI_PARAM2)) = (((_VAL_) << 19) | ((REG32(ADR_SPI_PARAM2)) & 0xfff7ffff))
++#define SET_BIT_MODE2(_VAL_) (REG32(ADR_SPI_PARAM2)) = (((_VAL_) << 20) | ((REG32(ADR_SPI_PARAM2)) & 0xffefffff))
++#define SET_BIT_MODE4(_VAL_) (REG32(ADR_SPI_PARAM2)) = (((_VAL_) << 21) | ((REG32(ADR_SPI_PARAM2)) & 0xffdfffff))
++#define SET_BOOT_CHECK_SUM(_VAL_) (REG32(ADR_CHECK_SUM_RESULT)) = (((_VAL_) << 0) | ((REG32(ADR_CHECK_SUM_RESULT)) & 0x00000000))
++#define SET_CHECK_SUM_TAG(_VAL_) (REG32(ADR_CHECK_SUM_IN_FILE)) = (((_VAL_) << 0) | ((REG32(ADR_CHECK_SUM_IN_FILE)) & 0x00000000))
++#define SET_CMD_LEN(_VAL_) (REG32(ADR_COMMAND_LEN)) = (((_VAL_) << 0) | ((REG32(ADR_COMMAND_LEN)) & 0xffff0000))
++#define SET_CMD_ADDR(_VAL_) (REG32(ADR_COMMAND_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_COMMAND_ADDR)) & 0x00000000))
++#define SET_DMA_ADR_SRC(_VAL_) (REG32(ADR_DMA_ADR_SRC)) = (((_VAL_) << 0) | ((REG32(ADR_DMA_ADR_SRC)) & 0x00000000))
++#define SET_DMA_ADR_DST(_VAL_) (REG32(ADR_DMA_ADR_DST)) = (((_VAL_) << 0) | ((REG32(ADR_DMA_ADR_DST)) & 0x00000000))
++#define SET_DMA_SRC_SIZE(_VAL_) (REG32(ADR_DMA_CTRL)) = (((_VAL_) << 0) | ((REG32(ADR_DMA_CTRL)) & 0xfffffff8))
++#define SET_DMA_SRC_INC(_VAL_) (REG32(ADR_DMA_CTRL)) = (((_VAL_) << 3) | ((REG32(ADR_DMA_CTRL)) & 0xfffffff7))
++#define SET_DMA_DST_SIZE(_VAL_) (REG32(ADR_DMA_CTRL)) = (((_VAL_) << 4) | ((REG32(ADR_DMA_CTRL)) & 0xffffff8f))
++#define SET_DMA_DST_INC(_VAL_) (REG32(ADR_DMA_CTRL)) = (((_VAL_) << 7) | ((REG32(ADR_DMA_CTRL)) & 0xffffff7f))
++#define SET_DMA_FAST_FILL(_VAL_) (REG32(ADR_DMA_CTRL)) = (((_VAL_) << 8) | ((REG32(ADR_DMA_CTRL)) & 0xfffffeff))
++#define SET_DMA_SDIO_KICK(_VAL_) (REG32(ADR_DMA_CTRL)) = (((_VAL_) << 12) | ((REG32(ADR_DMA_CTRL)) & 0xffffefff))
++#define SET_DMA_BADR_EN(_VAL_) (REG32(ADR_DMA_CTRL)) = (((_VAL_) << 13) | ((REG32(ADR_DMA_CTRL)) & 0xffffdfff))
++#define SET_DMA_LEN(_VAL_) (REG32(ADR_DMA_CTRL)) = (((_VAL_) << 16) | ((REG32(ADR_DMA_CTRL)) & 0x0000ffff))
++#define SET_DMA_INT_MASK(_VAL_) (REG32(ADR_DMA_INT)) = (((_VAL_) << 0) | ((REG32(ADR_DMA_INT)) & 0xfffffffe))
++#define SET_DMA_STS(_VAL_) (REG32(ADR_DMA_INT)) = (((_VAL_) << 8) | ((REG32(ADR_DMA_INT)) & 0xfffffeff))
++#define SET_DMA_FINISH(_VAL_) (REG32(ADR_DMA_INT)) = (((_VAL_) << 31) | ((REG32(ADR_DMA_INT)) & 0x7fffffff))
++#define SET_DMA_CONST(_VAL_) (REG32(ADR_DMA_FILL_CONST)) = (((_VAL_) << 0) | ((REG32(ADR_DMA_FILL_CONST)) & 0x00000000))
++#define SET_SLEEP_WAKE_CNT(_VAL_) (REG32(ADR_PMU_0)) = (((_VAL_) << 0) | ((REG32(ADR_PMU_0)) & 0xff000000))
++#define SET_RG_DLDO_LEVEL(_VAL_) (REG32(ADR_PMU_0)) = (((_VAL_) << 24) | ((REG32(ADR_PMU_0)) & 0xf8ffffff))
++#define SET_RG_DLDO_BOOST_IQ(_VAL_) (REG32(ADR_PMU_0)) = (((_VAL_) << 27) | ((REG32(ADR_PMU_0)) & 0xf7ffffff))
++#define SET_RG_BUCK_LEVEL(_VAL_) (REG32(ADR_PMU_0)) = (((_VAL_) << 28) | ((REG32(ADR_PMU_0)) & 0x8fffffff))
++#define SET_RG_BUCK_VREF_SEL(_VAL_) (REG32(ADR_PMU_0)) = (((_VAL_) << 31) | ((REG32(ADR_PMU_0)) & 0x7fffffff))
++#define SET_RG_RTC_OSC_RES_SW_MANUAL(_VAL_) (REG32(ADR_PMU_1)) = (((_VAL_) << 0) | ((REG32(ADR_PMU_1)) & 0xfffffc00))
++#define SET_RG_RTC_OSC_RES_SW(_VAL_) (REG32(ADR_PMU_1)) = (((_VAL_) << 16) | ((REG32(ADR_PMU_1)) & 0xfc00ffff))
++#define SET_RTC_OSC_CAL_RES_RDY(_VAL_) (REG32(ADR_PMU_1)) = (((_VAL_) << 31) | ((REG32(ADR_PMU_1)) & 0x7fffffff))
++#define SET_RG_DCDC_MODE(_VAL_) (REG32(ADR_PMU_2)) = (((_VAL_) << 0) | ((REG32(ADR_PMU_2)) & 0xfffffffe))
++#define SET_RG_BUCK_EN_PSM(_VAL_) (REG32(ADR_PMU_2)) = (((_VAL_) << 4) | ((REG32(ADR_PMU_2)) & 0xffffffef))
++#define SET_RG_BUCK_PSM_VTH(_VAL_) (REG32(ADR_PMU_2)) = (((_VAL_) << 8) | ((REG32(ADR_PMU_2)) & 0xfffffeff))
++#define SET_RG_RTC_OSC_RES_SW_MANUAL_EN(_VAL_) (REG32(ADR_PMU_2)) = (((_VAL_) << 12) | ((REG32(ADR_PMU_2)) & 0xffffefff))
++#define SET_RG_RTC_RDY_DEGLITCH_TIMER(_VAL_) (REG32(ADR_PMU_2)) = (((_VAL_) << 13) | ((REG32(ADR_PMU_2)) & 0xffff9fff))
++#define SET_RTC_CAL_ENA(_VAL_) (REG32(ADR_PMU_2)) = (((_VAL_) << 16) | ((REG32(ADR_PMU_2)) & 0xfffeffff))
++#define SET_PMU_WAKE_TRIG_EVENT(_VAL_) (REG32(ADR_PMU_3)) = (((_VAL_) << 0) | ((REG32(ADR_PMU_3)) & 0xfffffffc))
++#define SET_DIGI_TOP_POR_MASK(_VAL_) (REG32(ADR_PMU_3)) = (((_VAL_) << 4) | ((REG32(ADR_PMU_3)) & 0xffffffef))
++#define SET_PMU_ENTER_SLEEP_MODE(_VAL_) (REG32(ADR_PMU_3)) = (((_VAL_) << 8) | ((REG32(ADR_PMU_3)) & 0xfffffeff))
++#define SET_RG_RTC_DUMMIES(_VAL_) (REG32(ADR_PMU_3)) = (((_VAL_) << 16) | ((REG32(ADR_PMU_3)) & 0x0000ffff))
++#define SET_RTC_EN(_VAL_) (REG32(ADR_RTC_1)) = (((_VAL_) << 0) | ((REG32(ADR_RTC_1)) & 0xfffffffe))
++#define SET_RTC_SRC(_VAL_) (REG32(ADR_RTC_1)) = (((_VAL_) << 1) | ((REG32(ADR_RTC_1)) & 0xfffffffd))
++#define SET_RTC_TICK_CNT(_VAL_) (REG32(ADR_RTC_1)) = (((_VAL_) << 16) | ((REG32(ADR_RTC_1)) & 0x8000ffff))
++#define SET_RTC_INT_SEC_MASK(_VAL_) (REG32(ADR_RTC_2)) = (((_VAL_) << 0) | ((REG32(ADR_RTC_2)) & 0xfffffffe))
++#define SET_RTC_INT_ALARM_MASK(_VAL_) (REG32(ADR_RTC_2)) = (((_VAL_) << 1) | ((REG32(ADR_RTC_2)) & 0xfffffffd))
++#define SET_RTC_INT_SEC(_VAL_) (REG32(ADR_RTC_2)) = (((_VAL_) << 16) | ((REG32(ADR_RTC_2)) & 0xfffeffff))
++#define SET_RTC_INT_ALARM(_VAL_) (REG32(ADR_RTC_2)) = (((_VAL_) << 17) | ((REG32(ADR_RTC_2)) & 0xfffdffff))
++#define SET_RTC_SEC_START_CNT(_VAL_) (REG32(ADR_RTC_3W)) = (((_VAL_) << 0) | ((REG32(ADR_RTC_3W)) & 0x00000000))
++#define SET_RTC_SEC_CNT(_VAL_) (REG32(ADR_RTC_3R)) = (((_VAL_) << 0) | ((REG32(ADR_RTC_3R)) & 0x00000000))
++#define SET_RTC_SEC_ALARM_VALUE(_VAL_) (REG32(ADR_RTC_4)) = (((_VAL_) << 0) | ((REG32(ADR_RTC_4)) & 0x00000000))
++#define SET_D2_DMA_ADR_SRC(_VAL_) (REG32(ADR_D2_DMA_ADR_SRC)) = (((_VAL_) << 0) | ((REG32(ADR_D2_DMA_ADR_SRC)) & 0x00000000))
++#define SET_D2_DMA_ADR_DST(_VAL_) (REG32(ADR_D2_DMA_ADR_DST)) = (((_VAL_) << 0) | ((REG32(ADR_D2_DMA_ADR_DST)) & 0x00000000))
++#define SET_D2_DMA_SRC_SIZE(_VAL_) (REG32(ADR_D2_DMA_CTRL)) = (((_VAL_) << 0) | ((REG32(ADR_D2_DMA_CTRL)) & 0xfffffff8))
++#define SET_D2_DMA_SRC_INC(_VAL_) (REG32(ADR_D2_DMA_CTRL)) = (((_VAL_) << 3) | ((REG32(ADR_D2_DMA_CTRL)) & 0xfffffff7))
++#define SET_D2_DMA_DST_SIZE(_VAL_) (REG32(ADR_D2_DMA_CTRL)) = (((_VAL_) << 4) | ((REG32(ADR_D2_DMA_CTRL)) & 0xffffff8f))
++#define SET_D2_DMA_DST_INC(_VAL_) (REG32(ADR_D2_DMA_CTRL)) = (((_VAL_) << 7) | ((REG32(ADR_D2_DMA_CTRL)) & 0xffffff7f))
++#define SET_D2_DMA_FAST_FILL(_VAL_) (REG32(ADR_D2_DMA_CTRL)) = (((_VAL_) << 8) | ((REG32(ADR_D2_DMA_CTRL)) & 0xfffffeff))
++#define SET_D2_DMA_SDIO_KICK(_VAL_) (REG32(ADR_D2_DMA_CTRL)) = (((_VAL_) << 12) | ((REG32(ADR_D2_DMA_CTRL)) & 0xffffefff))
++#define SET_D2_DMA_BADR_EN(_VAL_) (REG32(ADR_D2_DMA_CTRL)) = (((_VAL_) << 13) | ((REG32(ADR_D2_DMA_CTRL)) & 0xffffdfff))
++#define SET_D2_DMA_LEN(_VAL_) (REG32(ADR_D2_DMA_CTRL)) = (((_VAL_) << 16) | ((REG32(ADR_D2_DMA_CTRL)) & 0x0000ffff))
++#define SET_D2_DMA_INT_MASK(_VAL_) (REG32(ADR_D2_DMA_INT)) = (((_VAL_) << 0) | ((REG32(ADR_D2_DMA_INT)) & 0xfffffffe))
++#define SET_D2_DMA_STS(_VAL_) (REG32(ADR_D2_DMA_INT)) = (((_VAL_) << 8) | ((REG32(ADR_D2_DMA_INT)) & 0xfffffeff))
++#define SET_D2_DMA_FINISH(_VAL_) (REG32(ADR_D2_DMA_INT)) = (((_VAL_) << 31) | ((REG32(ADR_D2_DMA_INT)) & 0x7fffffff))
++#define SET_D2_DMA_CONST(_VAL_) (REG32(ADR_D2_DMA_FILL_CONST)) = (((_VAL_) << 0) | ((REG32(ADR_D2_DMA_FILL_CONST)) & 0x00000000))
++#define SET_TRAP_UNKNOWN_TYPE(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 0) | ((REG32(ADR_CONTROL)) & 0xfffffffe))
++#define SET_TX_ON_DEMAND_ENA(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 1) | ((REG32(ADR_CONTROL)) & 0xfffffffd))
++#define SET_RX_2_HOST(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 2) | ((REG32(ADR_CONTROL)) & 0xfffffffb))
++#define SET_AUTO_SEQNO(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 3) | ((REG32(ADR_CONTROL)) & 0xfffffff7))
++#define SET_BYPASSS_TX_PARSER_ENCAP(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 4) | ((REG32(ADR_CONTROL)) & 0xffffffef))
++#define SET_HDR_STRIP(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 5) | ((REG32(ADR_CONTROL)) & 0xffffffdf))
++#define SET_ERP_PROTECT(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 6) | ((REG32(ADR_CONTROL)) & 0xffffff3f))
++#define SET_PRO_VER(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 8) | ((REG32(ADR_CONTROL)) & 0xfffffcff))
++#define SET_TXQ_ID0(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 12) | ((REG32(ADR_CONTROL)) & 0xffff8fff))
++#define SET_TXQ_ID1(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 16) | ((REG32(ADR_CONTROL)) & 0xfff8ffff))
++#define SET_TX_ETHER_TRAP_EN(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 20) | ((REG32(ADR_CONTROL)) & 0xffefffff))
++#define SET_RX_ETHER_TRAP_EN(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 21) | ((REG32(ADR_CONTROL)) & 0xffdfffff))
++#define SET_RX_NULL_TRAP_EN(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 22) | ((REG32(ADR_CONTROL)) & 0xffbfffff))
++#define SET_RX_GET_TX_QUEUE_EN(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 25) | ((REG32(ADR_CONTROL)) & 0xfdffffff))
++#define SET_HCI_INQ_SEL(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 26) | ((REG32(ADR_CONTROL)) & 0xfbffffff))
++#define SET_TRX_DEBUG_CNT_ENA(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 28) | ((REG32(ADR_CONTROL)) & 0xefffffff))
++#define SET_WAKE_SOON_WITH_SCK(_VAL_) (REG32(ADR_SDIO_WAKE_MODE)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_WAKE_MODE)) & 0xfffffffe))
++#define SET_TX_FLOW_CTRL(_VAL_) (REG32(ADR_TX_FLOW_0)) = (((_VAL_) << 0) | ((REG32(ADR_TX_FLOW_0)) & 0xffff0000))
++#define SET_TX_FLOW_MGMT(_VAL_) (REG32(ADR_TX_FLOW_0)) = (((_VAL_) << 16) | ((REG32(ADR_TX_FLOW_0)) & 0x0000ffff))
++#define SET_TX_FLOW_DATA(_VAL_) (REG32(ADR_TX_FLOW_1)) = (((_VAL_) << 0) | ((REG32(ADR_TX_FLOW_1)) & 0x00000000))
++#define SET_DOT11RTSTHRESHOLD(_VAL_) (REG32(ADR_THREASHOLD)) = (((_VAL_) << 16) | ((REG32(ADR_THREASHOLD)) & 0x0000ffff))
++#define SET_TXF_ID(_VAL_) (REG32(ADR_TXFID_INCREASE)) = (((_VAL_) << 0) | ((REG32(ADR_TXFID_INCREASE)) & 0xffffffc0))
++#define SET_SEQ_CTRL(_VAL_) (REG32(ADR_GLOBAL_SEQUENCE)) = (((_VAL_) << 0) | ((REG32(ADR_GLOBAL_SEQUENCE)) & 0xffff0000))
++#define SET_TX_PBOFFSET(_VAL_) (REG32(ADR_HCI_TX_RX_INFO_SIZE)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_TX_RX_INFO_SIZE)) & 0xffffff00))
++#define SET_TX_INFO_SIZE(_VAL_) (REG32(ADR_HCI_TX_RX_INFO_SIZE)) = (((_VAL_) << 8) | ((REG32(ADR_HCI_TX_RX_INFO_SIZE)) & 0xffff00ff))
++#define SET_RX_INFO_SIZE(_VAL_) (REG32(ADR_HCI_TX_RX_INFO_SIZE)) = (((_VAL_) << 16) | ((REG32(ADR_HCI_TX_RX_INFO_SIZE)) & 0xff00ffff))
++#define SET_RX_LAST_PHY_SIZE(_VAL_) (REG32(ADR_HCI_TX_RX_INFO_SIZE)) = (((_VAL_) << 24) | ((REG32(ADR_HCI_TX_RX_INFO_SIZE)) & 0x00ffffff))
++#define SET_TX_INFO_CLEAR_SIZE(_VAL_) (REG32(ADR_HCI_TX_INFO_CLEAR)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_TX_INFO_CLEAR)) & 0xffffffc0))
++#define SET_TX_INFO_CLEAR_ENABLE(_VAL_) (REG32(ADR_HCI_TX_INFO_CLEAR)) = (((_VAL_) << 8) | ((REG32(ADR_HCI_TX_INFO_CLEAR)) & 0xfffffeff))
++#define SET_TXTRAP_ETHTYPE1(_VAL_) (REG32(ADR_TX_ETHER_TYPE_1)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ETHER_TYPE_1)) & 0xffff0000))
++#define SET_TXTRAP_ETHTYPE0(_VAL_) (REG32(ADR_TX_ETHER_TYPE_1)) = (((_VAL_) << 16) | ((REG32(ADR_TX_ETHER_TYPE_1)) & 0x0000ffff))
++#define SET_RXTRAP_ETHTYPE1(_VAL_) (REG32(ADR_RX_ETHER_TYPE_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_ETHER_TYPE_1)) & 0xffff0000))
++#define SET_RXTRAP_ETHTYPE0(_VAL_) (REG32(ADR_RX_ETHER_TYPE_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_ETHER_TYPE_1)) & 0x0000ffff))
++#define SET_TX_PKT_COUNTER(_VAL_) (REG32(ADR_PACKET_COUNTER_INFO_0)) = (((_VAL_) << 0) | ((REG32(ADR_PACKET_COUNTER_INFO_0)) & 0x00000000))
++#define SET_RX_PKT_COUNTER(_VAL_) (REG32(ADR_PACKET_COUNTER_INFO_1)) = (((_VAL_) << 0) | ((REG32(ADR_PACKET_COUNTER_INFO_1)) & 0x00000000))
++#define SET_HOST_CMD_COUNTER(_VAL_) (REG32(ADR_PACKET_COUNTER_INFO_2)) = (((_VAL_) << 0) | ((REG32(ADR_PACKET_COUNTER_INFO_2)) & 0xffffff00))
++#define SET_HOST_EVENT_COUNTER(_VAL_) (REG32(ADR_PACKET_COUNTER_INFO_3)) = (((_VAL_) << 0) | ((REG32(ADR_PACKET_COUNTER_INFO_3)) & 0xffffff00))
++#define SET_TX_PKT_DROP_COUNTER(_VAL_) (REG32(ADR_PACKET_COUNTER_INFO_4)) = (((_VAL_) << 0) | ((REG32(ADR_PACKET_COUNTER_INFO_4)) & 0xffffff00))
++#define SET_RX_PKT_DROP_COUNTER(_VAL_) (REG32(ADR_PACKET_COUNTER_INFO_5)) = (((_VAL_) << 0) | ((REG32(ADR_PACKET_COUNTER_INFO_5)) & 0xffffff00))
++#define SET_TX_PKT_TRAP_COUNTER(_VAL_) (REG32(ADR_PACKET_COUNTER_INFO_6)) = (((_VAL_) << 0) | ((REG32(ADR_PACKET_COUNTER_INFO_6)) & 0xffffff00))
++#define SET_RX_PKT_TRAP_COUNTER(_VAL_) (REG32(ADR_PACKET_COUNTER_INFO_7)) = (((_VAL_) << 0) | ((REG32(ADR_PACKET_COUNTER_INFO_7)) & 0xffffff00))
++#define SET_HOST_TX_FAIL_COUNTER(_VAL_) (REG32(ADR_SDIO_TX_RX_FAIL_COUNTER_0)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_TX_RX_FAIL_COUNTER_0)) & 0xffffff00))
++#define SET_HOST_RX_FAIL_COUNTER(_VAL_) (REG32(ADR_SDIO_TX_RX_FAIL_COUNTER_1)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_TX_RX_FAIL_COUNTER_1)) & 0xffffff00))
++#define SET_HCI_STATE_MONITOR(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_0)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_0)) & 0x00000000))
++#define SET_HCI_ST_TIMEOUT_MONITOR(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_1)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_1)) & 0x00000000))
++#define SET_TX_ON_DEMAND_LENGTH(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_2)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_2)) & 0x00000000))
++#define SET_HCI_MONITOR_REG1(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_3)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_3)) & 0x00000000))
++#define SET_HCI_MONITOR_REG2(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_4)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_4)) & 0x00000000))
++#define SET_HCI_TX_ALLOC_TIME_31_0(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_5)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_5)) & 0x00000000))
++#define SET_HCI_TX_ALLOC_TIME_47_32(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_6)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_6)) & 0xffff0000))
++#define SET_HCI_MB_MAX_CNT(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_6)) = (((_VAL_) << 16) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_6)) & 0xff00ffff))
++#define SET_HCI_TX_ALLOC_CNT_31_0(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_7)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_7)) & 0x00000000))
++#define SET_HCI_TX_ALLOC_CNT_47_32(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_8)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_8)) & 0xffff0000))
++#define SET_HCI_PROC_CNT(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_8)) = (((_VAL_) << 16) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_8)) & 0xff00ffff))
++#define SET_SDIO_TRANS_CNT(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_8)) = (((_VAL_) << 24) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_8)) & 0x00ffffff))
++#define SET_SDIO_TX_INVALID_CNT_31_0(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_9)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_9)) & 0x00000000))
++#define SET_SDIO_TX_INVALID_CNT_47_32(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_10)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_10)) & 0xffff0000))
++#define SET_CS_START_ADDR(_VAL_) (REG32(ADR_CS_START_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_CS_START_ADDR)) & 0xffff0000))
++#define SET_CS_PKT_ID(_VAL_) (REG32(ADR_CS_START_ADDR)) = (((_VAL_) << 16) | ((REG32(ADR_CS_START_ADDR)) & 0xff80ffff))
++#define SET_ADD_LEN(_VAL_) (REG32(ADR_CS_ADD_LEN)) = (((_VAL_) << 0) | ((REG32(ADR_CS_ADD_LEN)) & 0xffff0000))
++#define SET_CS_ADDER_EN(_VAL_) (REG32(ADR_CS_CMD)) = (((_VAL_) << 0) | ((REG32(ADR_CS_CMD)) & 0xfffffffe))
++#define SET_PSEUDO(_VAL_) (REG32(ADR_CS_CMD)) = (((_VAL_) << 1) | ((REG32(ADR_CS_CMD)) & 0xfffffffd))
++#define SET_CALCULATE(_VAL_) (REG32(ADR_CS_INI_BUF)) = (((_VAL_) << 0) | ((REG32(ADR_CS_INI_BUF)) & 0x00000000))
++#define SET_L4_LEN(_VAL_) (REG32(ADR_CS_PSEUDO_BUF)) = (((_VAL_) << 0) | ((REG32(ADR_CS_PSEUDO_BUF)) & 0xffff0000))
++#define SET_L4_PROTOL(_VAL_) (REG32(ADR_CS_PSEUDO_BUF)) = (((_VAL_) << 16) | ((REG32(ADR_CS_PSEUDO_BUF)) & 0xff00ffff))
++#define SET_CHECK_SUM(_VAL_) (REG32(ADR_CS_CHECK_SUM)) = (((_VAL_) << 0) | ((REG32(ADR_CS_CHECK_SUM)) & 0xffff0000))
++#define SET_RAND_EN(_VAL_) (REG32(ADR_RAND_EN)) = (((_VAL_) << 0) | ((REG32(ADR_RAND_EN)) & 0xfffffffe))
++#define SET_RAND_NUM(_VAL_) (REG32(ADR_RAND_NUM)) = (((_VAL_) << 0) | ((REG32(ADR_RAND_NUM)) & 0x00000000))
++#define SET_MUL_OP1(_VAL_) (REG32(ADR_MUL_OP1)) = (((_VAL_) << 0) | ((REG32(ADR_MUL_OP1)) & 0x00000000))
++#define SET_MUL_OP2(_VAL_) (REG32(ADR_MUL_OP2)) = (((_VAL_) << 0) | ((REG32(ADR_MUL_OP2)) & 0x00000000))
++#define SET_MUL_ANS0(_VAL_) (REG32(ADR_MUL_ANS0)) = (((_VAL_) << 0) | ((REG32(ADR_MUL_ANS0)) & 0x00000000))
++#define SET_MUL_ANS1(_VAL_) (REG32(ADR_MUL_ANS1)) = (((_VAL_) << 0) | ((REG32(ADR_MUL_ANS1)) & 0x00000000))
++#define SET_RD_ADDR(_VAL_) (REG32(ADR_DMA_RDATA)) = (((_VAL_) << 0) | ((REG32(ADR_DMA_RDATA)) & 0xffff0000))
++#define SET_RD_ID(_VAL_) (REG32(ADR_DMA_RDATA)) = (((_VAL_) << 16) | ((REG32(ADR_DMA_RDATA)) & 0xff80ffff))
++#define SET_WR_ADDR(_VAL_) (REG32(ADR_DMA_WDATA)) = (((_VAL_) << 0) | ((REG32(ADR_DMA_WDATA)) & 0xffff0000))
++#define SET_WR_ID(_VAL_) (REG32(ADR_DMA_WDATA)) = (((_VAL_) << 16) | ((REG32(ADR_DMA_WDATA)) & 0xff80ffff))
++#define SET_LEN(_VAL_) (REG32(ADR_DMA_LEN)) = (((_VAL_) << 0) | ((REG32(ADR_DMA_LEN)) & 0xffff0000))
++#define SET_CLR(_VAL_) (REG32(ADR_DMA_CLR)) = (((_VAL_) << 0) | ((REG32(ADR_DMA_CLR)) & 0xfffffffe))
++#define SET_PHY_MODE(_VAL_) (REG32(ADR_NAV_DATA)) = (((_VAL_) << 0) | ((REG32(ADR_NAV_DATA)) & 0xfffffffc))
++#define SET_SHRT_PREAM(_VAL_) (REG32(ADR_NAV_DATA)) = (((_VAL_) << 2) | ((REG32(ADR_NAV_DATA)) & 0xfffffffb))
++#define SET_SHRT_GI(_VAL_) (REG32(ADR_NAV_DATA)) = (((_VAL_) << 3) | ((REG32(ADR_NAV_DATA)) & 0xfffffff7))
++#define SET_DATA_RATE(_VAL_) (REG32(ADR_NAV_DATA)) = (((_VAL_) << 4) | ((REG32(ADR_NAV_DATA)) & 0xfffff80f))
++#define SET_MCS(_VAL_) (REG32(ADR_NAV_DATA)) = (((_VAL_) << 12) | ((REG32(ADR_NAV_DATA)) & 0xffff8fff))
++#define SET_FRAME_LEN(_VAL_) (REG32(ADR_NAV_DATA)) = (((_VAL_) << 16) | ((REG32(ADR_NAV_DATA)) & 0x0000ffff))
++#define SET_DURATION(_VAL_) (REG32(ADR_CO_NAV)) = (((_VAL_) << 0) | ((REG32(ADR_CO_NAV)) & 0xffff0000))
++#define SET_SHA_DST_ADDR(_VAL_) (REG32(ADR_SHA_DST_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_SHA_DST_ADDR)) & 0x00000000))
++#define SET_SHA_SRC_ADDR(_VAL_) (REG32(ADR_SHA_SRC_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_SHA_SRC_ADDR)) & 0x00000000))
++#define SET_SHA_BUSY(_VAL_) (REG32(ADR_SHA_SETTING)) = (((_VAL_) << 0) | ((REG32(ADR_SHA_SETTING)) & 0xfffffffe))
++#define SET_SHA_ENDIAN(_VAL_) (REG32(ADR_SHA_SETTING)) = (((_VAL_) << 1) | ((REG32(ADR_SHA_SETTING)) & 0xfffffffd))
++#define SET_EFS_CLKFREQ(_VAL_) (REG32(ADR_EFUSE_CLK_FREQ)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_CLK_FREQ)) & 0xfffff000))
++#define SET_LOW_ACTIVE(_VAL_) (REG32(ADR_EFUSE_CLK_FREQ)) = (((_VAL_) << 16) | ((REG32(ADR_EFUSE_CLK_FREQ)) & 0xfffeffff))
++#define SET_EFS_CLKFREQ_RD(_VAL_) (REG32(ADR_EFUSE_CLK_FREQ)) = (((_VAL_) << 20) | ((REG32(ADR_EFUSE_CLK_FREQ)) & 0xf00fffff))
++#define SET_EFS_PRE_RD(_VAL_) (REG32(ADR_EFUSE_CLK_FREQ)) = (((_VAL_) << 28) | ((REG32(ADR_EFUSE_CLK_FREQ)) & 0x0fffffff))
++#define SET_EFS_LDO_ON(_VAL_) (REG32(ADR_EFUSE_LDO_TIME)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_LDO_TIME)) & 0xffff0000))
++#define SET_EFS_LDO_OFF(_VAL_) (REG32(ADR_EFUSE_LDO_TIME)) = (((_VAL_) << 16) | ((REG32(ADR_EFUSE_LDO_TIME)) & 0x0000ffff))
++#define SET_EFS_RDATA_0(_VAL_) (REG32(ADR_EFUSE_AHB_RDATA_0)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_AHB_RDATA_0)) & 0x00000000))
++#define SET_EFS_WDATA_0(_VAL_) (REG32(ADR_EFUSE_WDATA_0)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_WDATA_0)) & 0x00000000))
++#define SET_EFS_RDATA_1(_VAL_) (REG32(ADR_EFUSE_AHB_RDATA_1)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_AHB_RDATA_1)) & 0x00000000))
++#define SET_EFS_WDATA_1(_VAL_) (REG32(ADR_EFUSE_WDATA_1)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_WDATA_1)) & 0x00000000))
++#define SET_EFS_RDATA_2(_VAL_) (REG32(ADR_EFUSE_AHB_RDATA_2)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_AHB_RDATA_2)) & 0x00000000))
++#define SET_EFS_WDATA_2(_VAL_) (REG32(ADR_EFUSE_WDATA_2)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_WDATA_2)) & 0x00000000))
++#define SET_EFS_RDATA_3(_VAL_) (REG32(ADR_EFUSE_AHB_RDATA_3)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_AHB_RDATA_3)) & 0x00000000))
++#define SET_EFS_WDATA_3(_VAL_) (REG32(ADR_EFUSE_WDATA_3)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_WDATA_3)) & 0x00000000))
++#define SET_EFS_RDATA_4(_VAL_) (REG32(ADR_EFUSE_AHB_RDATA_4)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_AHB_RDATA_4)) & 0x00000000))
++#define SET_EFS_WDATA_4(_VAL_) (REG32(ADR_EFUSE_WDATA_4)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_WDATA_4)) & 0x00000000))
++#define SET_EFS_RDATA_5(_VAL_) (REG32(ADR_EFUSE_AHB_RDATA_5)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_AHB_RDATA_5)) & 0x00000000))
++#define SET_EFS_WDATA_5(_VAL_) (REG32(ADR_EFUSE_WDATA_5)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_WDATA_5)) & 0x00000000))
++#define SET_EFS_RDATA_6(_VAL_) (REG32(ADR_EFUSE_AHB_RDATA_6)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_AHB_RDATA_6)) & 0x00000000))
++#define SET_EFS_WDATA_6(_VAL_) (REG32(ADR_EFUSE_WDATA_6)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_WDATA_6)) & 0x00000000))
++#define SET_EFS_RDATA_7(_VAL_) (REG32(ADR_EFUSE_AHB_RDATA_7)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_AHB_RDATA_7)) & 0x00000000))
++#define SET_EFS_WDATA_7(_VAL_) (REG32(ADR_EFUSE_WDATA_7)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_WDATA_7)) & 0x00000000))
++#define SET_EFS_SPI_RD0_EN(_VAL_) (REG32(ADR_EFUSE_SPI_RD0_EN)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RD0_EN)) & 0xfffffffe))
++#define SET_EFS_SPI_RD1_EN(_VAL_) (REG32(ADR_EFUSE_SPI_RD1_EN)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RD1_EN)) & 0xfffffffe))
++#define SET_EFS_SPI_RD2_EN(_VAL_) (REG32(ADR_EFUSE_SPI_RD2_EN)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RD2_EN)) & 0xfffffffe))
++#define SET_EFS_SPI_RD3_EN(_VAL_) (REG32(ADR_EFUSE_SPI_RD3_EN)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RD3_EN)) & 0xfffffffe))
++#define SET_EFS_SPI_RD4_EN(_VAL_) (REG32(ADR_EFUSE_SPI_RD4_EN)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RD4_EN)) & 0xfffffffe))
++#define SET_EFS_SPI_RD5_EN(_VAL_) (REG32(ADR_EFUSE_SPI_RD5_EN)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RD5_EN)) & 0xfffffffe))
++#define SET_EFS_SPI_RD6_EN(_VAL_) (REG32(ADR_EFUSE_SPI_RD6_EN)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RD6_EN)) & 0xfffffffe))
++#define SET_EFS_SPI_RD7_EN(_VAL_) (REG32(ADR_EFUSE_SPI_RD7_EN)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RD7_EN)) & 0xfffffffe))
++#define SET_EFS_SPI_RBUSY(_VAL_) (REG32(ADR_EFUSE_SPI_BUSY)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_BUSY)) & 0xfffffffe))
++#define SET_EFS_SPI_RDATA_0(_VAL_) (REG32(ADR_EFUSE_SPI_RDATA_0)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RDATA_0)) & 0x00000000))
++#define SET_EFS_SPI_RDATA_1(_VAL_) (REG32(ADR_EFUSE_SPI_RDATA_1)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RDATA_1)) & 0x00000000))
++#define SET_EFS_SPI_RDATA_2(_VAL_) (REG32(ADR_EFUSE_SPI_RDATA_2)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RDATA_2)) & 0x00000000))
++#define SET_EFS_SPI_RDATA_3(_VAL_) (REG32(ADR_EFUSE_SPI_RDATA_3)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RDATA_3)) & 0x00000000))
++#define SET_EFS_SPI_RDATA_4(_VAL_) (REG32(ADR_EFUSE_SPI_RDATA_4)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RDATA_4)) & 0x00000000))
++#define SET_EFS_SPI_RDATA_5(_VAL_) (REG32(ADR_EFUSE_SPI_RDATA_5)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RDATA_5)) & 0x00000000))
++#define SET_EFS_SPI_RDATA_6(_VAL_) (REG32(ADR_EFUSE_SPI_RDATA_6)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RDATA_6)) & 0x00000000))
++#define SET_EFS_SPI_RDATA_7(_VAL_) (REG32(ADR_EFUSE_SPI_RDATA_7)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RDATA_7)) & 0x00000000))
++#define SET_GET_RK(_VAL_) (REG32(ADR_SMS4_CFG1)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_CFG1)) & 0xfffffffe))
++#define SET_FORCE_GET_RK(_VAL_) (REG32(ADR_SMS4_CFG1)) = (((_VAL_) << 1) | ((REG32(ADR_SMS4_CFG1)) & 0xfffffffd))
++#define SET_SMS4_DESCRY_EN(_VAL_) (REG32(ADR_SMS4_CFG1)) = (((_VAL_) << 4) | ((REG32(ADR_SMS4_CFG1)) & 0xffffffef))
++#define SET_DEC_DOUT_MSB(_VAL_) (REG32(ADR_SMS4_CFG2)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_CFG2)) & 0xfffffffe))
++#define SET_DEC_DIN_MSB(_VAL_) (REG32(ADR_SMS4_CFG2)) = (((_VAL_) << 1) | ((REG32(ADR_SMS4_CFG2)) & 0xfffffffd))
++#define SET_ENC_DOUT_MSB(_VAL_) (REG32(ADR_SMS4_CFG2)) = (((_VAL_) << 2) | ((REG32(ADR_SMS4_CFG2)) & 0xfffffffb))
++#define SET_ENC_DIN_MSB(_VAL_) (REG32(ADR_SMS4_CFG2)) = (((_VAL_) << 3) | ((REG32(ADR_SMS4_CFG2)) & 0xfffffff7))
++#define SET_KEY_DIN_MSB(_VAL_) (REG32(ADR_SMS4_CFG2)) = (((_VAL_) << 4) | ((REG32(ADR_SMS4_CFG2)) & 0xffffffef))
++#define SET_SMS4_CBC_EN(_VAL_) (REG32(ADR_SMS4_MODE1)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_MODE1)) & 0xfffffffe))
++#define SET_SMS4_CFB_EN(_VAL_) (REG32(ADR_SMS4_MODE1)) = (((_VAL_) << 1) | ((REG32(ADR_SMS4_MODE1)) & 0xfffffffd))
++#define SET_SMS4_OFB_EN(_VAL_) (REG32(ADR_SMS4_MODE1)) = (((_VAL_) << 2) | ((REG32(ADR_SMS4_MODE1)) & 0xfffffffb))
++#define SET_SMS4_START_TRIG(_VAL_) (REG32(ADR_SMS4_TRIG)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_TRIG)) & 0xfffffffe))
++#define SET_SMS4_BUSY(_VAL_) (REG32(ADR_SMS4_STATUS1)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_STATUS1)) & 0xfffffffe))
++#define SET_SMS4_DONE(_VAL_) (REG32(ADR_SMS4_STATUS2)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_STATUS2)) & 0xfffffffe))
++#define SET_SMS4_DATAIN_0(_VAL_) (REG32(ADR_SMS4_DATA_IN0)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_DATA_IN0)) & 0x00000000))
++#define SET_SMS4_DATAIN_1(_VAL_) (REG32(ADR_SMS4_DATA_IN1)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_DATA_IN1)) & 0x00000000))
++#define SET_SMS4_DATAIN_2(_VAL_) (REG32(ADR_SMS4_DATA_IN2)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_DATA_IN2)) & 0x00000000))
++#define SET_SMS4_DATAIN_3(_VAL_) (REG32(ADR_SMS4_DATA_IN3)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_DATA_IN3)) & 0x00000000))
++#define SET_SMS4_DATAOUT_0(_VAL_) (REG32(ADR_SMS4_DATA_OUT0)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_DATA_OUT0)) & 0x00000000))
++#define SET_SMS4_DATAOUT_1(_VAL_) (REG32(ADR_SMS4_DATA_OUT1)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_DATA_OUT1)) & 0x00000000))
++#define SET_SMS4_DATAOUT_2(_VAL_) (REG32(ADR_SMS4_DATA_OUT2)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_DATA_OUT2)) & 0x00000000))
++#define SET_SMS4_DATAOUT_3(_VAL_) (REG32(ADR_SMS4_DATA_OUT3)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_DATA_OUT3)) & 0x00000000))
++#define SET_SMS4_KEY_0(_VAL_) (REG32(ADR_SMS4_KEY_0)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_KEY_0)) & 0x00000000))
++#define SET_SMS4_KEY_1(_VAL_) (REG32(ADR_SMS4_KEY_1)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_KEY_1)) & 0x00000000))
++#define SET_SMS4_KEY_2(_VAL_) (REG32(ADR_SMS4_KEY_2)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_KEY_2)) & 0x00000000))
++#define SET_SMS4_KEY_3(_VAL_) (REG32(ADR_SMS4_KEY_3)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_KEY_3)) & 0x00000000))
++#define SET_SMS4_MODE_IV0(_VAL_) (REG32(ADR_SMS4_MODE_IV0)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_MODE_IV0)) & 0x00000000))
++#define SET_SMS4_MODE_IV1(_VAL_) (REG32(ADR_SMS4_MODE_IV1)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_MODE_IV1)) & 0x00000000))
++#define SET_SMS4_MODE_IV2(_VAL_) (REG32(ADR_SMS4_MODE_IV2)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_MODE_IV2)) & 0x00000000))
++#define SET_SMS4_MODE_IV3(_VAL_) (REG32(ADR_SMS4_MODE_IV3)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_MODE_IV3)) & 0x00000000))
++#define SET_SMS4_OFB_ENC0(_VAL_) (REG32(ADR_SMS4_OFB_ENC0)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_OFB_ENC0)) & 0x00000000))
++#define SET_SMS4_OFB_ENC1(_VAL_) (REG32(ADR_SMS4_OFB_ENC1)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_OFB_ENC1)) & 0x00000000))
++#define SET_SMS4_OFB_ENC2(_VAL_) (REG32(ADR_SMS4_OFB_ENC2)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_OFB_ENC2)) & 0x00000000))
++#define SET_SMS4_OFB_ENC3(_VAL_) (REG32(ADR_SMS4_OFB_ENC3)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_OFB_ENC3)) & 0x00000000))
++#define SET_MRX_MCAST_TB0_31_0(_VAL_) (REG32(ADR_MRX_MCAST_TB0_0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_TB0_0)) & 0x00000000))
++#define SET_MRX_MCAST_TB0_47_32(_VAL_) (REG32(ADR_MRX_MCAST_TB0_1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_TB0_1)) & 0xffff0000))
++#define SET_MRX_MCAST_MASK0_31_0(_VAL_) (REG32(ADR_MRX_MCAST_MK0_0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_MK0_0)) & 0x00000000))
++#define SET_MRX_MCAST_MASK0_47_32(_VAL_) (REG32(ADR_MRX_MCAST_MK0_1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_MK0_1)) & 0xffff0000))
++#define SET_MRX_MCAST_CTRL_0(_VAL_) (REG32(ADR_MRX_MCAST_CTRL0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_CTRL0)) & 0xfffffffc))
++#define SET_MRX_MCAST_TB1_31_0(_VAL_) (REG32(ADR_MRX_MCAST_TB1_0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_TB1_0)) & 0x00000000))
++#define SET_MRX_MCAST_TB1_47_32(_VAL_) (REG32(ADR_MRX_MCAST_TB1_1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_TB1_1)) & 0xffff0000))
++#define SET_MRX_MCAST_MASK1_31_0(_VAL_) (REG32(ADR_MRX_MCAST_MK1_0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_MK1_0)) & 0x00000000))
++#define SET_MRX_MCAST_MASK1_47_32(_VAL_) (REG32(ADR_MRX_MCAST_MK1_1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_MK1_1)) & 0xffff0000))
++#define SET_MRX_MCAST_CTRL_1(_VAL_) (REG32(ADR_MRX_MCAST_CTRL1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_CTRL1)) & 0xfffffffc))
++#define SET_MRX_MCAST_TB2_31_0(_VAL_) (REG32(ADR_MRX_MCAST_TB2_0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_TB2_0)) & 0x00000000))
++#define SET_MRX_MCAST_TB2_47_32(_VAL_) (REG32(ADR_MRX_MCAST_TB2_1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_TB2_1)) & 0xffff0000))
++#define SET_MRX_MCAST_MASK2_31_0(_VAL_) (REG32(ADR_MRX_MCAST_MK2_0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_MK2_0)) & 0x00000000))
++#define SET_MRX_MCAST_MASK2_47_32(_VAL_) (REG32(ADR_MRX_MCAST_MK2_1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_MK2_1)) & 0xffff0000))
++#define SET_MRX_MCAST_CTRL_2(_VAL_) (REG32(ADR_MRX_MCAST_CTRL2)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_CTRL2)) & 0xfffffffc))
++#define SET_MRX_MCAST_TB3_31_0(_VAL_) (REG32(ADR_MRX_MCAST_TB3_0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_TB3_0)) & 0x00000000))
++#define SET_MRX_MCAST_TB3_47_32(_VAL_) (REG32(ADR_MRX_MCAST_TB3_1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_TB3_1)) & 0xffff0000))
++#define SET_MRX_MCAST_MASK3_31_0(_VAL_) (REG32(ADR_MRX_MCAST_MK3_0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_MK3_0)) & 0x00000000))
++#define SET_MRX_MCAST_MASK3_47_32(_VAL_) (REG32(ADR_MRX_MCAST_MK3_1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_MK3_1)) & 0xffff0000))
++#define SET_MRX_MCAST_CTRL_3(_VAL_) (REG32(ADR_MRX_MCAST_CTRL3)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_CTRL3)) & 0xfffffffc))
++#define SET_MRX_PHY_INFO(_VAL_) (REG32(ADR_MRX_PHY_INFO)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_PHY_INFO)) & 0x00000000))
++#define SET_DBG_BA_TYPE(_VAL_) (REG32(ADR_MRX_BA_DBG)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_BA_DBG)) & 0xffffffc0))
++#define SET_DBG_BA_SEQ(_VAL_) (REG32(ADR_MRX_BA_DBG)) = (((_VAL_) << 8) | ((REG32(ADR_MRX_BA_DBG)) & 0xfff000ff))
++#define SET_MRX_FLT_TB0(_VAL_) (REG32(ADR_MRX_FLT_TB0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB0)) & 0xffff8000))
++#define SET_MRX_FLT_TB1(_VAL_) (REG32(ADR_MRX_FLT_TB1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB1)) & 0xffff8000))
++#define SET_MRX_FLT_TB2(_VAL_) (REG32(ADR_MRX_FLT_TB2)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB2)) & 0xffff8000))
++#define SET_MRX_FLT_TB3(_VAL_) (REG32(ADR_MRX_FLT_TB3)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB3)) & 0xffff8000))
++#define SET_MRX_FLT_TB4(_VAL_) (REG32(ADR_MRX_FLT_TB4)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB4)) & 0xffff8000))
++#define SET_MRX_FLT_TB5(_VAL_) (REG32(ADR_MRX_FLT_TB5)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB5)) & 0xffff8000))
++#define SET_MRX_FLT_TB6(_VAL_) (REG32(ADR_MRX_FLT_TB6)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB6)) & 0xffff8000))
++#define SET_MRX_FLT_TB7(_VAL_) (REG32(ADR_MRX_FLT_TB7)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB7)) & 0xffff8000))
++#define SET_MRX_FLT_TB8(_VAL_) (REG32(ADR_MRX_FLT_TB8)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB8)) & 0xffff8000))
++#define SET_MRX_FLT_TB9(_VAL_) (REG32(ADR_MRX_FLT_TB9)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB9)) & 0xffff8000))
++#define SET_MRX_FLT_TB10(_VAL_) (REG32(ADR_MRX_FLT_TB10)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB10)) & 0xffff8000))
++#define SET_MRX_FLT_TB11(_VAL_) (REG32(ADR_MRX_FLT_TB11)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB11)) & 0xffff8000))
++#define SET_MRX_FLT_TB12(_VAL_) (REG32(ADR_MRX_FLT_TB12)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB12)) & 0xffff8000))
++#define SET_MRX_FLT_TB13(_VAL_) (REG32(ADR_MRX_FLT_TB13)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB13)) & 0xffff8000))
++#define SET_MRX_FLT_TB14(_VAL_) (REG32(ADR_MRX_FLT_TB14)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB14)) & 0xffff8000))
++#define SET_MRX_FLT_TB15(_VAL_) (REG32(ADR_MRX_FLT_TB15)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB15)) & 0xffff8000))
++#define SET_MRX_FLT_EN0(_VAL_) (REG32(ADR_MRX_FLT_EN0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_EN0)) & 0xffff0000))
++#define SET_MRX_FLT_EN1(_VAL_) (REG32(ADR_MRX_FLT_EN1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_EN1)) & 0xffff0000))
++#define SET_MRX_FLT_EN2(_VAL_) (REG32(ADR_MRX_FLT_EN2)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_EN2)) & 0xffff0000))
++#define SET_MRX_FLT_EN3(_VAL_) (REG32(ADR_MRX_FLT_EN3)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_EN3)) & 0xffff0000))
++#define SET_MRX_FLT_EN4(_VAL_) (REG32(ADR_MRX_FLT_EN4)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_EN4)) & 0xffff0000))
++#define SET_MRX_FLT_EN5(_VAL_) (REG32(ADR_MRX_FLT_EN5)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_EN5)) & 0xffff0000))
++#define SET_MRX_FLT_EN6(_VAL_) (REG32(ADR_MRX_FLT_EN6)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_EN6)) & 0xffff0000))
++#define SET_MRX_FLT_EN7(_VAL_) (REG32(ADR_MRX_FLT_EN7)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_EN7)) & 0xffff0000))
++#define SET_MRX_FLT_EN8(_VAL_) (REG32(ADR_MRX_FLT_EN8)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_EN8)) & 0xffff0000))
++#define SET_MRX_LEN_FLT(_VAL_) (REG32(ADR_MRX_LEN_FLT)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_LEN_FLT)) & 0xffff0000))
++#define SET_RX_FLOW_DATA(_VAL_) (REG32(ADR_RX_FLOW_DATA)) = (((_VAL_) << 0) | ((REG32(ADR_RX_FLOW_DATA)) & 0x00000000))
++#define SET_RX_FLOW_MNG(_VAL_) (REG32(ADR_RX_FLOW_MNG)) = (((_VAL_) << 0) | ((REG32(ADR_RX_FLOW_MNG)) & 0xffff0000))
++#define SET_RX_FLOW_CTRL(_VAL_) (REG32(ADR_RX_FLOW_CTRL)) = (((_VAL_) << 0) | ((REG32(ADR_RX_FLOW_CTRL)) & 0xffff0000))
++#define SET_MRX_STP_EN(_VAL_) (REG32(ADR_RX_TIME_STAMP_CFG)) = (((_VAL_) << 0) | ((REG32(ADR_RX_TIME_STAMP_CFG)) & 0xfffffffe))
++#define SET_MRX_STP_OFST(_VAL_) (REG32(ADR_RX_TIME_STAMP_CFG)) = (((_VAL_) << 8) | ((REG32(ADR_RX_TIME_STAMP_CFG)) & 0xffff00ff))
++#define SET_DBG_FF_FULL(_VAL_) (REG32(ADR_DBG_FF_FULL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_FF_FULL)) & 0xffff0000))
++#define SET_DBG_FF_FULL_CLR(_VAL_) (REG32(ADR_DBG_FF_FULL)) = (((_VAL_) << 31) | ((REG32(ADR_DBG_FF_FULL)) & 0x7fffffff))
++#define SET_DBG_WFF_FULL(_VAL_) (REG32(ADR_DBG_WFF_FULL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_WFF_FULL)) & 0xffff0000))
++#define SET_DBG_WFF_FULL_CLR(_VAL_) (REG32(ADR_DBG_WFF_FULL)) = (((_VAL_) << 31) | ((REG32(ADR_DBG_WFF_FULL)) & 0x7fffffff))
++#define SET_DBG_MB_FULL(_VAL_) (REG32(ADR_DBG_MB_FULL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_MB_FULL)) & 0xffff0000))
++#define SET_DBG_MB_FULL_CLR(_VAL_) (REG32(ADR_DBG_MB_FULL)) = (((_VAL_) << 31) | ((REG32(ADR_DBG_MB_FULL)) & 0x7fffffff))
++#define SET_BA_CTRL(_VAL_) (REG32(ADR_BA_CTRL)) = (((_VAL_) << 0) | ((REG32(ADR_BA_CTRL)) & 0xfffffffc))
++#define SET_BA_DBG_EN(_VAL_) (REG32(ADR_BA_CTRL)) = (((_VAL_) << 2) | ((REG32(ADR_BA_CTRL)) & 0xfffffffb))
++#define SET_BA_AGRE_EN(_VAL_) (REG32(ADR_BA_CTRL)) = (((_VAL_) << 3) | ((REG32(ADR_BA_CTRL)) & 0xfffffff7))
++#define SET_BA_TA_31_0(_VAL_) (REG32(ADR_BA_TA_0)) = (((_VAL_) << 0) | ((REG32(ADR_BA_TA_0)) & 0x00000000))
++#define SET_BA_TA_47_32(_VAL_) (REG32(ADR_BA_TA_1)) = (((_VAL_) << 0) | ((REG32(ADR_BA_TA_1)) & 0xffff0000))
++#define SET_BA_TID(_VAL_) (REG32(ADR_BA_TID)) = (((_VAL_) << 0) | ((REG32(ADR_BA_TID)) & 0xfffffff0))
++#define SET_BA_ST_SEQ(_VAL_) (REG32(ADR_BA_ST_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_BA_ST_SEQ)) & 0xfffff000))
++#define SET_BA_SB0(_VAL_) (REG32(ADR_BA_SB0)) = (((_VAL_) << 0) | ((REG32(ADR_BA_SB0)) & 0x00000000))
++#define SET_BA_SB1(_VAL_) (REG32(ADR_BA_SB1)) = (((_VAL_) << 0) | ((REG32(ADR_BA_SB1)) & 0x00000000))
++#define SET_MRX_WD(_VAL_) (REG32(ADR_MRX_WATCH_DOG)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_WATCH_DOG)) & 0xfffe0000))
++#define SET_ACK_GEN_EN(_VAL_) (REG32(ADR_ACK_GEN_EN)) = (((_VAL_) << 0) | ((REG32(ADR_ACK_GEN_EN)) & 0xfffffffe))
++#define SET_BA_GEN_EN(_VAL_) (REG32(ADR_ACK_GEN_EN)) = (((_VAL_) << 1) | ((REG32(ADR_ACK_GEN_EN)) & 0xfffffffd))
++#define SET_ACK_GEN_DUR(_VAL_) (REG32(ADR_ACK_GEN_PARA)) = (((_VAL_) << 0) | ((REG32(ADR_ACK_GEN_PARA)) & 0xffff0000))
++#define SET_ACK_GEN_INFO(_VAL_) (REG32(ADR_ACK_GEN_PARA)) = (((_VAL_) << 16) | ((REG32(ADR_ACK_GEN_PARA)) & 0xffc0ffff))
++#define SET_ACK_GEN_RA_31_0(_VAL_) (REG32(ADR_ACK_GEN_RA_0)) = (((_VAL_) << 0) | ((REG32(ADR_ACK_GEN_RA_0)) & 0x00000000))
++#define SET_ACK_GEN_RA_47_32(_VAL_) (REG32(ADR_ACK_GEN_RA_1)) = (((_VAL_) << 0) | ((REG32(ADR_ACK_GEN_RA_1)) & 0xffff0000))
++#define SET_MIB_LEN_FAIL(_VAL_) (REG32(ADR_MIB_LEN_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_MIB_LEN_FAIL)) & 0xffff0000))
++#define SET_TRAP_HW_ID(_VAL_) (REG32(ADR_TRAP_HW_ID)) = (((_VAL_) << 0) | ((REG32(ADR_TRAP_HW_ID)) & 0xfffffff0))
++#define SET_ID_IN_USE(_VAL_) (REG32(ADR_ID_IN_USE)) = (((_VAL_) << 0) | ((REG32(ADR_ID_IN_USE)) & 0xffffff00))
++#define SET_MRX_ERR(_VAL_) (REG32(ADR_MRX_ERR)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_ERR)) & 0x00000000))
++#define SET_W0_T0_SEQ(_VAL_) (REG32(ADR_WSID0_TID0_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID0_TID0_RX_SEQ)) & 0xffff0000))
++#define SET_W0_T1_SEQ(_VAL_) (REG32(ADR_WSID0_TID1_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID0_TID1_RX_SEQ)) & 0xffff0000))
++#define SET_W0_T2_SEQ(_VAL_) (REG32(ADR_WSID0_TID2_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID0_TID2_RX_SEQ)) & 0xffff0000))
++#define SET_W0_T3_SEQ(_VAL_) (REG32(ADR_WSID0_TID3_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID0_TID3_RX_SEQ)) & 0xffff0000))
++#define SET_W0_T4_SEQ(_VAL_) (REG32(ADR_WSID0_TID4_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID0_TID4_RX_SEQ)) & 0xffff0000))
++#define SET_W0_T5_SEQ(_VAL_) (REG32(ADR_WSID0_TID5_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID0_TID5_RX_SEQ)) & 0xffff0000))
++#define SET_W0_T6_SEQ(_VAL_) (REG32(ADR_WSID0_TID6_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID0_TID6_RX_SEQ)) & 0xffff0000))
++#define SET_W0_T7_SEQ(_VAL_) (REG32(ADR_WSID0_TID7_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID0_TID7_RX_SEQ)) & 0xffff0000))
++#define SET_W1_T0_SEQ(_VAL_) (REG32(ADR_WSID1_TID0_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID1_TID0_RX_SEQ)) & 0xffff0000))
++#define SET_W1_T1_SEQ(_VAL_) (REG32(ADR_WSID1_TID1_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID1_TID1_RX_SEQ)) & 0xffff0000))
++#define SET_W1_T2_SEQ(_VAL_) (REG32(ADR_WSID1_TID2_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID1_TID2_RX_SEQ)) & 0xffff0000))
++#define SET_W1_T3_SEQ(_VAL_) (REG32(ADR_WSID1_TID3_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID1_TID3_RX_SEQ)) & 0xffff0000))
++#define SET_W1_T4_SEQ(_VAL_) (REG32(ADR_WSID1_TID4_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID1_TID4_RX_SEQ)) & 0xffff0000))
++#define SET_W1_T5_SEQ(_VAL_) (REG32(ADR_WSID1_TID5_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID1_TID5_RX_SEQ)) & 0xffff0000))
++#define SET_W1_T6_SEQ(_VAL_) (REG32(ADR_WSID1_TID6_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID1_TID6_RX_SEQ)) & 0xffff0000))
++#define SET_W1_T7_SEQ(_VAL_) (REG32(ADR_WSID1_TID7_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID1_TID7_RX_SEQ)) & 0xffff0000))
++#define SET_ADDR1A_SEL(_VAL_) (REG32(ADR_HDR_ADDR_SEL)) = (((_VAL_) << 0) | ((REG32(ADR_HDR_ADDR_SEL)) & 0xfffffffc))
++#define SET_ADDR2A_SEL(_VAL_) (REG32(ADR_HDR_ADDR_SEL)) = (((_VAL_) << 2) | ((REG32(ADR_HDR_ADDR_SEL)) & 0xfffffff3))
++#define SET_ADDR3A_SEL(_VAL_) (REG32(ADR_HDR_ADDR_SEL)) = (((_VAL_) << 4) | ((REG32(ADR_HDR_ADDR_SEL)) & 0xffffffcf))
++#define SET_ADDR1B_SEL(_VAL_) (REG32(ADR_HDR_ADDR_SEL)) = (((_VAL_) << 6) | ((REG32(ADR_HDR_ADDR_SEL)) & 0xffffff3f))
++#define SET_ADDR2B_SEL(_VAL_) (REG32(ADR_HDR_ADDR_SEL)) = (((_VAL_) << 8) | ((REG32(ADR_HDR_ADDR_SEL)) & 0xfffffcff))
++#define SET_ADDR3B_SEL(_VAL_) (REG32(ADR_HDR_ADDR_SEL)) = (((_VAL_) << 10) | ((REG32(ADR_HDR_ADDR_SEL)) & 0xfffff3ff))
++#define SET_ADDR3C_SEL(_VAL_) (REG32(ADR_HDR_ADDR_SEL)) = (((_VAL_) << 12) | ((REG32(ADR_HDR_ADDR_SEL)) & 0xffffcfff))
++#define SET_FRM_CTRL(_VAL_) (REG32(ADR_FRAME_TYPE_CNTR_SET)) = (((_VAL_) << 0) | ((REG32(ADR_FRAME_TYPE_CNTR_SET)) & 0xffffffc0))
++#define SET_CSR_PHY_INFO(_VAL_) (REG32(ADR_PHY_INFO)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_INFO)) & 0xffff8000))
++#define SET_AMPDU_SIG(_VAL_) (REG32(ADR_AMPDU_SIG)) = (((_VAL_) << 0) | ((REG32(ADR_AMPDU_SIG)) & 0xffffff00))
++#define SET_MIB_AMPDU(_VAL_) (REG32(ADR_MIB_AMPDU)) = (((_VAL_) << 0) | ((REG32(ADR_MIB_AMPDU)) & 0x00000000))
++#define SET_LEN_FLT(_VAL_) (REG32(ADR_LEN_FLT)) = (((_VAL_) << 0) | ((REG32(ADR_LEN_FLT)) & 0xffff0000))
++#define SET_MIB_DELIMITER(_VAL_) (REG32(ADR_MIB_DELIMITER)) = (((_VAL_) << 0) | ((REG32(ADR_MIB_DELIMITER)) & 0xffff0000))
++#define SET_MTX_INT_Q0_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_INT_STS)) & 0xfffeffff))
++#define SET_MTX_INT_Q0_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 17) | ((REG32(ADR_MTX_INT_STS)) & 0xfffdffff))
++#define SET_MTX_INT_Q1_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 18) | ((REG32(ADR_MTX_INT_STS)) & 0xfffbffff))
++#define SET_MTX_INT_Q1_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 19) | ((REG32(ADR_MTX_INT_STS)) & 0xfff7ffff))
++#define SET_MTX_INT_Q2_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 20) | ((REG32(ADR_MTX_INT_STS)) & 0xffefffff))
++#define SET_MTX_INT_Q2_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 21) | ((REG32(ADR_MTX_INT_STS)) & 0xffdfffff))
++#define SET_MTX_INT_Q3_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 22) | ((REG32(ADR_MTX_INT_STS)) & 0xffbfffff))
++#define SET_MTX_INT_Q3_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 23) | ((REG32(ADR_MTX_INT_STS)) & 0xff7fffff))
++#define SET_MTX_INT_Q4_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 24) | ((REG32(ADR_MTX_INT_STS)) & 0xfeffffff))
++#define SET_MTX_INT_Q4_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 25) | ((REG32(ADR_MTX_INT_STS)) & 0xfdffffff))
++#define SET_MTX_EN_INT_Q0_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_INT_EN)) & 0xfffeffff))
++#define SET_MTX_EN_INT_Q0_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 17) | ((REG32(ADR_MTX_INT_EN)) & 0xfffdffff))
++#define SET_MTX_EN_INT_Q1_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 18) | ((REG32(ADR_MTX_INT_EN)) & 0xfffbffff))
++#define SET_MTX_EN_INT_Q1_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 19) | ((REG32(ADR_MTX_INT_EN)) & 0xfff7ffff))
++#define SET_MTX_EN_INT_Q2_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 20) | ((REG32(ADR_MTX_INT_EN)) & 0xffefffff))
++#define SET_MTX_EN_INT_Q2_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 21) | ((REG32(ADR_MTX_INT_EN)) & 0xffdfffff))
++#define SET_MTX_EN_INT_Q3_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 22) | ((REG32(ADR_MTX_INT_EN)) & 0xffbfffff))
++#define SET_MTX_EN_INT_Q3_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 23) | ((REG32(ADR_MTX_INT_EN)) & 0xff7fffff))
++#define SET_MTX_EN_INT_Q4_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 24) | ((REG32(ADR_MTX_INT_EN)) & 0xfeffffff))
++#define SET_MTX_EN_INT_Q4_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 25) | ((REG32(ADR_MTX_INT_EN)) & 0xfdffffff))
++#define SET_MTX_MTX2PHY_SLOW(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_MISC_EN)) & 0xfffffffe))
++#define SET_MTX_M2M_SLOW_PRD(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 1) | ((REG32(ADR_MTX_MISC_EN)) & 0xfffffff1))
++#define SET_MTX_AMPDU_CRC_AUTO(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 5) | ((REG32(ADR_MTX_MISC_EN)) & 0xffffffdf))
++#define SET_MTX_FAST_RSP_MODE(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 6) | ((REG32(ADR_MTX_MISC_EN)) & 0xffffffbf))
++#define SET_MTX_RAW_DATA_MODE(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 7) | ((REG32(ADR_MTX_MISC_EN)) & 0xffffff7f))
++#define SET_MTX_ACK_DUR0(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 8) | ((REG32(ADR_MTX_MISC_EN)) & 0xfffffeff))
++#define SET_MTX_TSF_AUTO_BCN(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 10) | ((REG32(ADR_MTX_MISC_EN)) & 0xfffffbff))
++#define SET_MTX_TSF_AUTO_MISC(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 11) | ((REG32(ADR_MTX_MISC_EN)) & 0xfffff7ff))
++#define SET_MTX_FORCE_CS_IDLE(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 12) | ((REG32(ADR_MTX_MISC_EN)) & 0xffffefff))
++#define SET_MTX_FORCE_BKF_RXEN0(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 13) | ((REG32(ADR_MTX_MISC_EN)) & 0xffffdfff))
++#define SET_MTX_FORCE_DMA_RXEN0(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 14) | ((REG32(ADR_MTX_MISC_EN)) & 0xffffbfff))
++#define SET_MTX_FORCE_RXEN0(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 15) | ((REG32(ADR_MTX_MISC_EN)) & 0xffff7fff))
++#define SET_MTX_HALT_Q_MB(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_MISC_EN)) & 0xffc0ffff))
++#define SET_MTX_CTS_SET_DIF(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 22) | ((REG32(ADR_MTX_MISC_EN)) & 0xffbfffff))
++#define SET_MTX_AMPDU_SET_DIF(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 23) | ((REG32(ADR_MTX_MISC_EN)) & 0xff7fffff))
++#define SET_MTX_EDCCA_TOUT(_VAL_) (REG32(ADR_MTX_EDCCA_TOUT)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_EDCCA_TOUT)) & 0xfffffc00))
++#define SET_MTX_INT_BCN(_VAL_) (REG32(ADR_MTX_BCN_INT_STS)) = (((_VAL_) << 1) | ((REG32(ADR_MTX_BCN_INT_STS)) & 0xfffffffd))
++#define SET_MTX_INT_DTIM(_VAL_) (REG32(ADR_MTX_BCN_INT_STS)) = (((_VAL_) << 3) | ((REG32(ADR_MTX_BCN_INT_STS)) & 0xfffffff7))
++#define SET_MTX_EN_INT_BCN(_VAL_) (REG32(ADR_MTX_BCN_EN_INT)) = (((_VAL_) << 1) | ((REG32(ADR_MTX_BCN_EN_INT)) & 0xfffffffd))
++#define SET_MTX_EN_INT_DTIM(_VAL_) (REG32(ADR_MTX_BCN_EN_INT)) = (((_VAL_) << 3) | ((REG32(ADR_MTX_BCN_EN_INT)) & 0xfffffff7))
++#define SET_MTX_BCN_TIMER_EN(_VAL_) (REG32(ADR_MTX_BCN_EN_MISC)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_BCN_EN_MISC)) & 0xfffffffe))
++#define SET_MTX_TIME_STAMP_AUTO_FILL(_VAL_) (REG32(ADR_MTX_BCN_EN_MISC)) = (((_VAL_) << 1) | ((REG32(ADR_MTX_BCN_EN_MISC)) & 0xfffffffd))
++#define SET_MTX_TSF_TIMER_EN(_VAL_) (REG32(ADR_MTX_BCN_EN_MISC)) = (((_VAL_) << 5) | ((REG32(ADR_MTX_BCN_EN_MISC)) & 0xffffffdf))
++#define SET_MTX_HALT_MNG_UNTIL_DTIM(_VAL_) (REG32(ADR_MTX_BCN_EN_MISC)) = (((_VAL_) << 6) | ((REG32(ADR_MTX_BCN_EN_MISC)) & 0xffffffbf))
++#define SET_MTX_INT_DTIM_NUM(_VAL_) (REG32(ADR_MTX_BCN_EN_MISC)) = (((_VAL_) << 8) | ((REG32(ADR_MTX_BCN_EN_MISC)) & 0xffff00ff))
++#define SET_MTX_AUTO_FLUSH_Q4(_VAL_) (REG32(ADR_MTX_BCN_EN_MISC)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_BCN_EN_MISC)) & 0xfffeffff))
++#define SET_MTX_BCN_PKTID_CH_LOCK(_VAL_) (REG32(ADR_MTX_BCN_MISC)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_BCN_MISC)) & 0xfffffffe))
++#define SET_MTX_BCN_CFG_VLD(_VAL_) (REG32(ADR_MTX_BCN_MISC)) = (((_VAL_) << 1) | ((REG32(ADR_MTX_BCN_MISC)) & 0xfffffff9))
++#define SET_MTX_AUTO_BCN_ONGOING(_VAL_) (REG32(ADR_MTX_BCN_MISC)) = (((_VAL_) << 3) | ((REG32(ADR_MTX_BCN_MISC)) & 0xfffffff7))
++#define SET_MTX_BCN_TIMER(_VAL_) (REG32(ADR_MTX_BCN_MISC)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_BCN_MISC)) & 0x0000ffff))
++#define SET_MTX_BCN_PERIOD(_VAL_) (REG32(ADR_MTX_BCN_PRD)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_BCN_PRD)) & 0xffff0000))
++#define SET_MTX_DTIM_NUM(_VAL_) (REG32(ADR_MTX_BCN_PRD)) = (((_VAL_) << 24) | ((REG32(ADR_MTX_BCN_PRD)) & 0x00ffffff))
++#define SET_MTX_BCN_TSF_L(_VAL_) (REG32(ADR_MTX_BCN_TSF_L)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_BCN_TSF_L)) & 0x00000000))
++#define SET_MTX_BCN_TSF_U(_VAL_) (REG32(ADR_MTX_BCN_TSF_U)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_BCN_TSF_U)) & 0x00000000))
++#define SET_MTX_BCN_PKT_ID0(_VAL_) (REG32(ADR_MTX_BCN_CFG0)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_BCN_CFG0)) & 0xffffff80))
++#define SET_MTX_DTIM_OFST0(_VAL_) (REG32(ADR_MTX_BCN_CFG0)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_BCN_CFG0)) & 0xfc00ffff))
++#define SET_MTX_BCN_PKT_ID1(_VAL_) (REG32(ADR_MTX_BCN_CFG1)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_BCN_CFG1)) & 0xffffff80))
++#define SET_MTX_DTIM_OFST1(_VAL_) (REG32(ADR_MTX_BCN_CFG1)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_BCN_CFG1)) & 0xfc00ffff))
++#define SET_MTX_CCA(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_STATUS)) & 0xfffffffe))
++#define SET_MRX_CCA(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 1) | ((REG32(ADR_MTX_STATUS)) & 0xfffffffd))
++#define SET_MTX_DMA_FSM(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 2) | ((REG32(ADR_MTX_STATUS)) & 0xffffffe3))
++#define SET_CH_ST_FSM(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 5) | ((REG32(ADR_MTX_STATUS)) & 0xffffff1f))
++#define SET_MTX_GNT_LOCK(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 8) | ((REG32(ADR_MTX_STATUS)) & 0xfffffeff))
++#define SET_MTX_DMA_REQ(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 9) | ((REG32(ADR_MTX_STATUS)) & 0xfffffdff))
++#define SET_MTX_Q_REQ(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 10) | ((REG32(ADR_MTX_STATUS)) & 0xfffffbff))
++#define SET_MTX_TX_EN(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 11) | ((REG32(ADR_MTX_STATUS)) & 0xfffff7ff))
++#define SET_MRX_RX_EN(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 12) | ((REG32(ADR_MTX_STATUS)) & 0xffffefff))
++#define SET_DBG_PRTC_PRD(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 13) | ((REG32(ADR_MTX_STATUS)) & 0xffffdfff))
++#define SET_DBG_DMA_RDY(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 14) | ((REG32(ADR_MTX_STATUS)) & 0xffffbfff))
++#define SET_DBG_WAIT_RSP(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 15) | ((REG32(ADR_MTX_STATUS)) & 0xffff7fff))
++#define SET_DBG_CFRM_BUSY(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_STATUS)) & 0xfffeffff))
++#define SET_DBG_RST(_VAL_) (REG32(ADR_MTX_DBG_CTRL)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_DBG_CTRL)) & 0xfffffffe))
++#define SET_DBG_MODE(_VAL_) (REG32(ADR_MTX_DBG_CTRL)) = (((_VAL_) << 1) | ((REG32(ADR_MTX_DBG_CTRL)) & 0xfffffffd))
++#define SET_MB_REQ_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT0)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_DBG_DAT0)) & 0xffff0000))
++#define SET_RX_EN_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT0)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_DBG_DAT0)) & 0x0000ffff))
++#define SET_RX_CS_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT1)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_DBG_DAT1)) & 0xffff0000))
++#define SET_TX_CCA_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT1)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_DBG_DAT1)) & 0x0000ffff))
++#define SET_Q_REQ_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT2)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_DBG_DAT2)) & 0xffff0000))
++#define SET_CH_STA0_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT2)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_DBG_DAT2)) & 0x0000ffff))
++#define SET_MTX_DUR_RSP_TOUT_B(_VAL_) (REG32(ADR_MTX_DUR_TOUT)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_DUR_TOUT)) & 0xffffff00))
++#define SET_MTX_DUR_RSP_TOUT_G(_VAL_) (REG32(ADR_MTX_DUR_TOUT)) = (((_VAL_) << 8) | ((REG32(ADR_MTX_DUR_TOUT)) & 0xffff00ff))
++#define SET_MTX_DUR_RSP_SIFS(_VAL_) (REG32(ADR_MTX_DUR_IFS)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_DUR_IFS)) & 0xffffff00))
++#define SET_MTX_DUR_BURST_SIFS(_VAL_) (REG32(ADR_MTX_DUR_IFS)) = (((_VAL_) << 8) | ((REG32(ADR_MTX_DUR_IFS)) & 0xffff00ff))
++#define SET_MTX_DUR_SLOT(_VAL_) (REG32(ADR_MTX_DUR_IFS)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_DUR_IFS)) & 0xffc0ffff))
++#define SET_MTX_DUR_RSP_EIFS(_VAL_) (REG32(ADR_MTX_DUR_IFS)) = (((_VAL_) << 22) | ((REG32(ADR_MTX_DUR_IFS)) & 0x003fffff))
++#define SET_MTX_DUR_RSP_SIFS_G(_VAL_) (REG32(ADR_MTX_DUR_SIFS_G)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_DUR_SIFS_G)) & 0xffffff00))
++#define SET_MTX_DUR_BURST_SIFS_G(_VAL_) (REG32(ADR_MTX_DUR_SIFS_G)) = (((_VAL_) << 8) | ((REG32(ADR_MTX_DUR_SIFS_G)) & 0xffff00ff))
++#define SET_MTX_DUR_SLOT_G(_VAL_) (REG32(ADR_MTX_DUR_SIFS_G)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_DUR_SIFS_G)) & 0xffc0ffff))
++#define SET_MTX_DUR_RSP_EIFS_G(_VAL_) (REG32(ADR_MTX_DUR_SIFS_G)) = (((_VAL_) << 22) | ((REG32(ADR_MTX_DUR_SIFS_G)) & 0x003fffff))
++#define SET_CH_STA1_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT3)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_DBG_DAT3)) & 0xffff0000))
++#define SET_CH_STA2_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT3)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_DBG_DAT3)) & 0x0000ffff))
++#define SET_MTX_NAV(_VAL_) (REG32(ADR_MTX_NAV)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_NAV)) & 0xffff0000))
++#define SET_MTX_MIB_CNT0(_VAL_) (REG32(ADR_MTX_MIB_WSID0)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_MIB_WSID0)) & 0xc0000000))
++#define SET_MTX_MIB_EN0(_VAL_) (REG32(ADR_MTX_MIB_WSID0)) = (((_VAL_) << 30) | ((REG32(ADR_MTX_MIB_WSID0)) & 0xbfffffff))
++#define SET_MTX_MIB_CNT1(_VAL_) (REG32(ADR_MTX_MIB_WSID1)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_MIB_WSID1)) & 0xc0000000))
++#define SET_MTX_MIB_EN1(_VAL_) (REG32(ADR_MTX_MIB_WSID1)) = (((_VAL_) << 30) | ((REG32(ADR_MTX_MIB_WSID1)) & 0xbfffffff))
++#define SET_CH_STA3_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT4)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_DBG_DAT4)) & 0xffff0000))
++#define SET_CH_STA4_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT4)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_DBG_DAT4)) & 0x0000ffff))
++#define SET_TXQ0_MTX_Q_PRE_LD(_VAL_) (REG32(ADR_TXQ0_MTX_Q_MISC_EN)) = (((_VAL_) << 1) | ((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0xfffffffd))
++#define SET_TXQ0_MTX_Q_BKF_CNT_FIXED(_VAL_) (REG32(ADR_TXQ0_MTX_Q_MISC_EN)) = (((_VAL_) << 2) | ((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0xfffffffb))
++#define SET_TXQ0_MTX_Q_TXOP_SUB_FRM_TIME(_VAL_) (REG32(ADR_TXQ0_MTX_Q_MISC_EN)) = (((_VAL_) << 3) | ((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0xfffffff7))
++#define SET_TXQ0_MTX_Q_MB_NO_RLS(_VAL_) (REG32(ADR_TXQ0_MTX_Q_MISC_EN)) = (((_VAL_) << 4) | ((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0xffffffef))
++#define SET_TXQ0_MTX_Q_TXOP_FRC_BUR(_VAL_) (REG32(ADR_TXQ0_MTX_Q_MISC_EN)) = (((_VAL_) << 5) | ((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0xffffffdf))
++#define SET_TXQ0_MTX_Q_RND_MODE(_VAL_) (REG32(ADR_TXQ0_MTX_Q_MISC_EN)) = (((_VAL_) << 6) | ((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0xffffff3f))
++#define SET_TXQ0_MTX_Q_AIFSN(_VAL_) (REG32(ADR_TXQ0_MTX_Q_AIFSN)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ0_MTX_Q_AIFSN)) & 0xfffffff0))
++#define SET_TXQ0_MTX_Q_ECWMIN(_VAL_) (REG32(ADR_TXQ0_MTX_Q_AIFSN)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ0_MTX_Q_AIFSN)) & 0xfffff0ff))
++#define SET_TXQ0_MTX_Q_ECWMAX(_VAL_) (REG32(ADR_TXQ0_MTX_Q_AIFSN)) = (((_VAL_) << 12) | ((REG32(ADR_TXQ0_MTX_Q_AIFSN)) & 0xffff0fff))
++#define SET_TXQ0_MTX_Q_TXOP_LIMIT(_VAL_) (REG32(ADR_TXQ0_MTX_Q_AIFSN)) = (((_VAL_) << 16) | ((REG32(ADR_TXQ0_MTX_Q_AIFSN)) & 0x0000ffff))
++#define SET_TXQ0_MTX_Q_BKF_CNT(_VAL_) (REG32(ADR_TXQ0_MTX_Q_BKF_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ0_MTX_Q_BKF_CNT)) & 0xffff0000))
++#define SET_TXQ0_MTX_Q_SRC_LIMIT(_VAL_) (REG32(ADR_TXQ0_MTX_Q_RC_LIMIT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ0_MTX_Q_RC_LIMIT)) & 0xffffff00))
++#define SET_TXQ0_MTX_Q_LRC_LIMIT(_VAL_) (REG32(ADR_TXQ0_MTX_Q_RC_LIMIT)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ0_MTX_Q_RC_LIMIT)) & 0xffff00ff))
++#define SET_TXQ0_MTX_Q_ID_MAP_L(_VAL_) (REG32(ADR_TXQ0_MTX_Q_ID_MAP_L)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ0_MTX_Q_ID_MAP_L)) & 0x00000000))
++#define SET_TXQ0_MTX_Q_TXOP_CH_THD(_VAL_) (REG32(ADR_TXQ0_MTX_Q_TXOP_CH_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ0_MTX_Q_TXOP_CH_THD)) & 0xffff0000))
++#define SET_TXQ0_MTX_Q_TXOP_OV_THD(_VAL_) (REG32(ADR_TXQ0_MTX_Q_TXOP_OV_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ0_MTX_Q_TXOP_OV_THD)) & 0xffff0000))
++#define SET_TXQ1_MTX_Q_PRE_LD(_VAL_) (REG32(ADR_TXQ1_MTX_Q_MISC_EN)) = (((_VAL_) << 1) | ((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0xfffffffd))
++#define SET_TXQ1_MTX_Q_BKF_CNT_FIXED(_VAL_) (REG32(ADR_TXQ1_MTX_Q_MISC_EN)) = (((_VAL_) << 2) | ((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0xfffffffb))
++#define SET_TXQ1_MTX_Q_TXOP_SUB_FRM_TIME(_VAL_) (REG32(ADR_TXQ1_MTX_Q_MISC_EN)) = (((_VAL_) << 3) | ((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0xfffffff7))
++#define SET_TXQ1_MTX_Q_MB_NO_RLS(_VAL_) (REG32(ADR_TXQ1_MTX_Q_MISC_EN)) = (((_VAL_) << 4) | ((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0xffffffef))
++#define SET_TXQ1_MTX_Q_TXOP_FRC_BUR(_VAL_) (REG32(ADR_TXQ1_MTX_Q_MISC_EN)) = (((_VAL_) << 5) | ((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0xffffffdf))
++#define SET_TXQ1_MTX_Q_RND_MODE(_VAL_) (REG32(ADR_TXQ1_MTX_Q_MISC_EN)) = (((_VAL_) << 6) | ((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0xffffff3f))
++#define SET_TXQ1_MTX_Q_AIFSN(_VAL_) (REG32(ADR_TXQ1_MTX_Q_AIFSN)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ1_MTX_Q_AIFSN)) & 0xfffffff0))
++#define SET_TXQ1_MTX_Q_ECWMIN(_VAL_) (REG32(ADR_TXQ1_MTX_Q_AIFSN)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ1_MTX_Q_AIFSN)) & 0xfffff0ff))
++#define SET_TXQ1_MTX_Q_ECWMAX(_VAL_) (REG32(ADR_TXQ1_MTX_Q_AIFSN)) = (((_VAL_) << 12) | ((REG32(ADR_TXQ1_MTX_Q_AIFSN)) & 0xffff0fff))
++#define SET_TXQ1_MTX_Q_TXOP_LIMIT(_VAL_) (REG32(ADR_TXQ1_MTX_Q_AIFSN)) = (((_VAL_) << 16) | ((REG32(ADR_TXQ1_MTX_Q_AIFSN)) & 0x0000ffff))
++#define SET_TXQ1_MTX_Q_BKF_CNT(_VAL_) (REG32(ADR_TXQ1_MTX_Q_BKF_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ1_MTX_Q_BKF_CNT)) & 0xffff0000))
++#define SET_TXQ1_MTX_Q_SRC_LIMIT(_VAL_) (REG32(ADR_TXQ1_MTX_Q_RC_LIMIT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ1_MTX_Q_RC_LIMIT)) & 0xffffff00))
++#define SET_TXQ1_MTX_Q_LRC_LIMIT(_VAL_) (REG32(ADR_TXQ1_MTX_Q_RC_LIMIT)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ1_MTX_Q_RC_LIMIT)) & 0xffff00ff))
++#define SET_TXQ1_MTX_Q_ID_MAP_L(_VAL_) (REG32(ADR_TXQ1_MTX_Q_ID_MAP_L)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ1_MTX_Q_ID_MAP_L)) & 0x00000000))
++#define SET_TXQ1_MTX_Q_TXOP_CH_THD(_VAL_) (REG32(ADR_TXQ1_MTX_Q_TXOP_CH_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ1_MTX_Q_TXOP_CH_THD)) & 0xffff0000))
++#define SET_TXQ1_MTX_Q_TXOP_OV_THD(_VAL_) (REG32(ADR_TXQ1_MTX_Q_TXOP_OV_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ1_MTX_Q_TXOP_OV_THD)) & 0xffff0000))
++#define SET_TXQ2_MTX_Q_PRE_LD(_VAL_) (REG32(ADR_TXQ2_MTX_Q_MISC_EN)) = (((_VAL_) << 1) | ((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0xfffffffd))
++#define SET_TXQ2_MTX_Q_BKF_CNT_FIXED(_VAL_) (REG32(ADR_TXQ2_MTX_Q_MISC_EN)) = (((_VAL_) << 2) | ((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0xfffffffb))
++#define SET_TXQ2_MTX_Q_TXOP_SUB_FRM_TIME(_VAL_) (REG32(ADR_TXQ2_MTX_Q_MISC_EN)) = (((_VAL_) << 3) | ((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0xfffffff7))
++#define SET_TXQ2_MTX_Q_MB_NO_RLS(_VAL_) (REG32(ADR_TXQ2_MTX_Q_MISC_EN)) = (((_VAL_) << 4) | ((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0xffffffef))
++#define SET_TXQ2_MTX_Q_TXOP_FRC_BUR(_VAL_) (REG32(ADR_TXQ2_MTX_Q_MISC_EN)) = (((_VAL_) << 5) | ((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0xffffffdf))
++#define SET_TXQ2_MTX_Q_RND_MODE(_VAL_) (REG32(ADR_TXQ2_MTX_Q_MISC_EN)) = (((_VAL_) << 6) | ((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0xffffff3f))
++#define SET_TXQ2_MTX_Q_AIFSN(_VAL_) (REG32(ADR_TXQ2_MTX_Q_AIFSN)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ2_MTX_Q_AIFSN)) & 0xfffffff0))
++#define SET_TXQ2_MTX_Q_ECWMIN(_VAL_) (REG32(ADR_TXQ2_MTX_Q_AIFSN)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ2_MTX_Q_AIFSN)) & 0xfffff0ff))
++#define SET_TXQ2_MTX_Q_ECWMAX(_VAL_) (REG32(ADR_TXQ2_MTX_Q_AIFSN)) = (((_VAL_) << 12) | ((REG32(ADR_TXQ2_MTX_Q_AIFSN)) & 0xffff0fff))
++#define SET_TXQ2_MTX_Q_TXOP_LIMIT(_VAL_) (REG32(ADR_TXQ2_MTX_Q_AIFSN)) = (((_VAL_) << 16) | ((REG32(ADR_TXQ2_MTX_Q_AIFSN)) & 0x0000ffff))
++#define SET_TXQ2_MTX_Q_BKF_CNT(_VAL_) (REG32(ADR_TXQ2_MTX_Q_BKF_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ2_MTX_Q_BKF_CNT)) & 0xffff0000))
++#define SET_TXQ2_MTX_Q_SRC_LIMIT(_VAL_) (REG32(ADR_TXQ2_MTX_Q_RC_LIMIT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ2_MTX_Q_RC_LIMIT)) & 0xffffff00))
++#define SET_TXQ2_MTX_Q_LRC_LIMIT(_VAL_) (REG32(ADR_TXQ2_MTX_Q_RC_LIMIT)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ2_MTX_Q_RC_LIMIT)) & 0xffff00ff))
++#define SET_TXQ2_MTX_Q_ID_MAP_L(_VAL_) (REG32(ADR_TXQ2_MTX_Q_ID_MAP_L)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ2_MTX_Q_ID_MAP_L)) & 0x00000000))
++#define SET_TXQ2_MTX_Q_TXOP_CH_THD(_VAL_) (REG32(ADR_TXQ2_MTX_Q_TXOP_CH_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ2_MTX_Q_TXOP_CH_THD)) & 0xffff0000))
++#define SET_TXQ2_MTX_Q_TXOP_OV_THD(_VAL_) (REG32(ADR_TXQ2_MTX_Q_TXOP_OV_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ2_MTX_Q_TXOP_OV_THD)) & 0xffff0000))
++#define SET_TXQ3_MTX_Q_PRE_LD(_VAL_) (REG32(ADR_TXQ3_MTX_Q_MISC_EN)) = (((_VAL_) << 1) | ((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0xfffffffd))
++#define SET_TXQ3_MTX_Q_BKF_CNT_FIXED(_VAL_) (REG32(ADR_TXQ3_MTX_Q_MISC_EN)) = (((_VAL_) << 2) | ((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0xfffffffb))
++#define SET_TXQ3_MTX_Q_TXOP_SUB_FRM_TIME(_VAL_) (REG32(ADR_TXQ3_MTX_Q_MISC_EN)) = (((_VAL_) << 3) | ((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0xfffffff7))
++#define SET_TXQ3_MTX_Q_MB_NO_RLS(_VAL_) (REG32(ADR_TXQ3_MTX_Q_MISC_EN)) = (((_VAL_) << 4) | ((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0xffffffef))
++#define SET_TXQ3_MTX_Q_TXOP_FRC_BUR(_VAL_) (REG32(ADR_TXQ3_MTX_Q_MISC_EN)) = (((_VAL_) << 5) | ((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0xffffffdf))
++#define SET_TXQ3_MTX_Q_RND_MODE(_VAL_) (REG32(ADR_TXQ3_MTX_Q_MISC_EN)) = (((_VAL_) << 6) | ((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0xffffff3f))
++#define SET_TXQ3_MTX_Q_AIFSN(_VAL_) (REG32(ADR_TXQ3_MTX_Q_AIFSN)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ3_MTX_Q_AIFSN)) & 0xfffffff0))
++#define SET_TXQ3_MTX_Q_ECWMIN(_VAL_) (REG32(ADR_TXQ3_MTX_Q_AIFSN)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ3_MTX_Q_AIFSN)) & 0xfffff0ff))
++#define SET_TXQ3_MTX_Q_ECWMAX(_VAL_) (REG32(ADR_TXQ3_MTX_Q_AIFSN)) = (((_VAL_) << 12) | ((REG32(ADR_TXQ3_MTX_Q_AIFSN)) & 0xffff0fff))
++#define SET_TXQ3_MTX_Q_TXOP_LIMIT(_VAL_) (REG32(ADR_TXQ3_MTX_Q_AIFSN)) = (((_VAL_) << 16) | ((REG32(ADR_TXQ3_MTX_Q_AIFSN)) & 0x0000ffff))
++#define SET_TXQ3_MTX_Q_BKF_CNT(_VAL_) (REG32(ADR_TXQ3_MTX_Q_BKF_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ3_MTX_Q_BKF_CNT)) & 0xffff0000))
++#define SET_TXQ3_MTX_Q_SRC_LIMIT(_VAL_) (REG32(ADR_TXQ3_MTX_Q_RC_LIMIT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ3_MTX_Q_RC_LIMIT)) & 0xffffff00))
++#define SET_TXQ3_MTX_Q_LRC_LIMIT(_VAL_) (REG32(ADR_TXQ3_MTX_Q_RC_LIMIT)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ3_MTX_Q_RC_LIMIT)) & 0xffff00ff))
++#define SET_TXQ3_MTX_Q_ID_MAP_L(_VAL_) (REG32(ADR_TXQ3_MTX_Q_ID_MAP_L)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ3_MTX_Q_ID_MAP_L)) & 0x00000000))
++#define SET_TXQ3_MTX_Q_TXOP_CH_THD(_VAL_) (REG32(ADR_TXQ3_MTX_Q_TXOP_CH_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ3_MTX_Q_TXOP_CH_THD)) & 0xffff0000))
++#define SET_TXQ3_MTX_Q_TXOP_OV_THD(_VAL_) (REG32(ADR_TXQ3_MTX_Q_TXOP_OV_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ3_MTX_Q_TXOP_OV_THD)) & 0xffff0000))
++#define SET_TXQ4_MTX_Q_PRE_LD(_VAL_) (REG32(ADR_TXQ4_MTX_Q_MISC_EN)) = (((_VAL_) << 1) | ((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0xfffffffd))
++#define SET_TXQ4_MTX_Q_BKF_CNT_FIXED(_VAL_) (REG32(ADR_TXQ4_MTX_Q_MISC_EN)) = (((_VAL_) << 2) | ((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0xfffffffb))
++#define SET_TXQ4_MTX_Q_TXOP_SUB_FRM_TIME(_VAL_) (REG32(ADR_TXQ4_MTX_Q_MISC_EN)) = (((_VAL_) << 3) | ((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0xfffffff7))
++#define SET_TXQ4_MTX_Q_MB_NO_RLS(_VAL_) (REG32(ADR_TXQ4_MTX_Q_MISC_EN)) = (((_VAL_) << 4) | ((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0xffffffef))
++#define SET_TXQ4_MTX_Q_TXOP_FRC_BUR(_VAL_) (REG32(ADR_TXQ4_MTX_Q_MISC_EN)) = (((_VAL_) << 5) | ((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0xffffffdf))
++#define SET_TXQ4_MTX_Q_RND_MODE(_VAL_) (REG32(ADR_TXQ4_MTX_Q_MISC_EN)) = (((_VAL_) << 6) | ((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0xffffff3f))
++#define SET_TXQ4_MTX_Q_AIFSN(_VAL_) (REG32(ADR_TXQ4_MTX_Q_AIFSN)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ4_MTX_Q_AIFSN)) & 0xfffffff0))
++#define SET_TXQ4_MTX_Q_ECWMIN(_VAL_) (REG32(ADR_TXQ4_MTX_Q_AIFSN)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ4_MTX_Q_AIFSN)) & 0xfffff0ff))
++#define SET_TXQ4_MTX_Q_ECWMAX(_VAL_) (REG32(ADR_TXQ4_MTX_Q_AIFSN)) = (((_VAL_) << 12) | ((REG32(ADR_TXQ4_MTX_Q_AIFSN)) & 0xffff0fff))
++#define SET_TXQ4_MTX_Q_TXOP_LIMIT(_VAL_) (REG32(ADR_TXQ4_MTX_Q_AIFSN)) = (((_VAL_) << 16) | ((REG32(ADR_TXQ4_MTX_Q_AIFSN)) & 0x0000ffff))
++#define SET_TXQ4_MTX_Q_BKF_CNT(_VAL_) (REG32(ADR_TXQ4_MTX_Q_BKF_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ4_MTX_Q_BKF_CNT)) & 0xffff0000))
++#define SET_TXQ4_MTX_Q_SRC_LIMIT(_VAL_) (REG32(ADR_TXQ4_MTX_Q_RC_LIMIT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ4_MTX_Q_RC_LIMIT)) & 0xffffff00))
++#define SET_TXQ4_MTX_Q_LRC_LIMIT(_VAL_) (REG32(ADR_TXQ4_MTX_Q_RC_LIMIT)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ4_MTX_Q_RC_LIMIT)) & 0xffff00ff))
++#define SET_TXQ4_MTX_Q_ID_MAP_L(_VAL_) (REG32(ADR_TXQ4_MTX_Q_ID_MAP_L)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ4_MTX_Q_ID_MAP_L)) & 0x00000000))
++#define SET_TXQ4_MTX_Q_TXOP_CH_THD(_VAL_) (REG32(ADR_TXQ4_MTX_Q_TXOP_CH_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ4_MTX_Q_TXOP_CH_THD)) & 0xffff0000))
++#define SET_TXQ4_MTX_Q_TXOP_OV_THD(_VAL_) (REG32(ADR_TXQ4_MTX_Q_TXOP_OV_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ4_MTX_Q_TXOP_OV_THD)) & 0xffff0000))
++#define SET_VALID0(_VAL_) (REG32(ADR_WSID0)) = (((_VAL_) << 0) | ((REG32(ADR_WSID0)) & 0xfffffffe))
++#define SET_PEER_QOS_EN0(_VAL_) (REG32(ADR_WSID0)) = (((_VAL_) << 1) | ((REG32(ADR_WSID0)) & 0xfffffffd))
++#define SET_PEER_OP_MODE0(_VAL_) (REG32(ADR_WSID0)) = (((_VAL_) << 2) | ((REG32(ADR_WSID0)) & 0xfffffff3))
++#define SET_PEER_HT_MODE0(_VAL_) (REG32(ADR_WSID0)) = (((_VAL_) << 4) | ((REG32(ADR_WSID0)) & 0xffffffcf))
++#define SET_PEER_MAC0_31_0(_VAL_) (REG32(ADR_PEER_MAC0_0)) = (((_VAL_) << 0) | ((REG32(ADR_PEER_MAC0_0)) & 0x00000000))
++#define SET_PEER_MAC0_47_32(_VAL_) (REG32(ADR_PEER_MAC0_1)) = (((_VAL_) << 0) | ((REG32(ADR_PEER_MAC0_1)) & 0xffff0000))
++#define SET_TX_ACK_POLICY_0_0(_VAL_) (REG32(ADR_TX_ACK_POLICY_0_0)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_0_0)) & 0xfffffffc))
++#define SET_TX_SEQ_CTRL_0_0(_VAL_) (REG32(ADR_TX_SEQ_CTRL_0_0)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_0_0)) & 0xfffff000))
++#define SET_TX_ACK_POLICY_0_1(_VAL_) (REG32(ADR_TX_ACK_POLICY_0_1)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_0_1)) & 0xfffffffc))
++#define SET_TX_SEQ_CTRL_0_1(_VAL_) (REG32(ADR_TX_SEQ_CTRL_0_1)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_0_1)) & 0xfffff000))
++#define SET_TX_ACK_POLICY_0_2(_VAL_) (REG32(ADR_TX_ACK_POLICY_0_2)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_0_2)) & 0xfffffffc))
++#define SET_TX_SEQ_CTRL_0_2(_VAL_) (REG32(ADR_TX_SEQ_CTRL_0_2)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_0_2)) & 0xfffff000))
++#define SET_TX_ACK_POLICY_0_3(_VAL_) (REG32(ADR_TX_ACK_POLICY_0_3)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_0_3)) & 0xfffffffc))
++#define SET_TX_SEQ_CTRL_0_3(_VAL_) (REG32(ADR_TX_SEQ_CTRL_0_3)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_0_3)) & 0xfffff000))
++#define SET_TX_ACK_POLICY_0_4(_VAL_) (REG32(ADR_TX_ACK_POLICY_0_4)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_0_4)) & 0xfffffffc))
++#define SET_TX_SEQ_CTRL_0_4(_VAL_) (REG32(ADR_TX_SEQ_CTRL_0_4)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_0_4)) & 0xfffff000))
++#define SET_TX_ACK_POLICY_0_5(_VAL_) (REG32(ADR_TX_ACK_POLICY_0_5)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_0_5)) & 0xfffffffc))
++#define SET_TX_SEQ_CTRL_0_5(_VAL_) (REG32(ADR_TX_SEQ_CTRL_0_5)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_0_5)) & 0xfffff000))
++#define SET_TX_ACK_POLICY_0_6(_VAL_) (REG32(ADR_TX_ACK_POLICY_0_6)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_0_6)) & 0xfffffffc))
++#define SET_TX_SEQ_CTRL_0_6(_VAL_) (REG32(ADR_TX_SEQ_CTRL_0_6)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_0_6)) & 0xfffff000))
++#define SET_TX_ACK_POLICY_0_7(_VAL_) (REG32(ADR_TX_ACK_POLICY_0_7)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_0_7)) & 0xfffffffc))
++#define SET_TX_SEQ_CTRL_0_7(_VAL_) (REG32(ADR_TX_SEQ_CTRL_0_7)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_0_7)) & 0xfffff000))
++#define SET_VALID1(_VAL_) (REG32(ADR_WSID1)) = (((_VAL_) << 0) | ((REG32(ADR_WSID1)) & 0xfffffffe))
++#define SET_PEER_QOS_EN1(_VAL_) (REG32(ADR_WSID1)) = (((_VAL_) << 1) | ((REG32(ADR_WSID1)) & 0xfffffffd))
++#define SET_PEER_OP_MODE1(_VAL_) (REG32(ADR_WSID1)) = (((_VAL_) << 2) | ((REG32(ADR_WSID1)) & 0xfffffff3))
++#define SET_PEER_HT_MODE1(_VAL_) (REG32(ADR_WSID1)) = (((_VAL_) << 4) | ((REG32(ADR_WSID1)) & 0xffffffcf))
++#define SET_PEER_MAC1_31_0(_VAL_) (REG32(ADR_PEER_MAC1_0)) = (((_VAL_) << 0) | ((REG32(ADR_PEER_MAC1_0)) & 0x00000000))
++#define SET_PEER_MAC1_47_32(_VAL_) (REG32(ADR_PEER_MAC1_1)) = (((_VAL_) << 0) | ((REG32(ADR_PEER_MAC1_1)) & 0xffff0000))
++#define SET_TX_ACK_POLICY_1_0(_VAL_) (REG32(ADR_TX_ACK_POLICY_1_0)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_1_0)) & 0xfffffffc))
++#define SET_TX_SEQ_CTRL_1_0(_VAL_) (REG32(ADR_TX_SEQ_CTRL_1_0)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_1_0)) & 0xfffff000))
++#define SET_TX_ACK_POLICY_1_1(_VAL_) (REG32(ADR_TX_ACK_POLICY_1_1)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_1_1)) & 0xfffffffc))
++#define SET_TX_SEQ_CTRL_1_1(_VAL_) (REG32(ADR_TX_SEQ_CTRL_1_1)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_1_1)) & 0xfffff000))
++#define SET_TX_ACK_POLICY_1_2(_VAL_) (REG32(ADR_TX_ACK_POLICY_1_2)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_1_2)) & 0xfffffffc))
++#define SET_TX_SEQ_CTRL_1_2(_VAL_) (REG32(ADR_TX_SEQ_CTRL_1_2)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_1_2)) & 0xfffff000))
++#define SET_TX_ACK_POLICY_1_3(_VAL_) (REG32(ADR_TX_ACK_POLICY_1_3)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_1_3)) & 0xfffffffc))
++#define SET_TX_SEQ_CTRL_1_3(_VAL_) (REG32(ADR_TX_SEQ_CTRL_1_3)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_1_3)) & 0xfffff000))
++#define SET_TX_ACK_POLICY_1_4(_VAL_) (REG32(ADR_TX_ACK_POLICY_1_4)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_1_4)) & 0xfffffffc))
++#define SET_TX_SEQ_CTRL_1_4(_VAL_) (REG32(ADR_TX_SEQ_CTRL_1_4)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_1_4)) & 0xfffff000))
++#define SET_TX_ACK_POLICY_1_5(_VAL_) (REG32(ADR_TX_ACK_POLICY_1_5)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_1_5)) & 0xfffffffc))
++#define SET_TX_SEQ_CTRL_1_5(_VAL_) (REG32(ADR_TX_SEQ_CTRL_1_5)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_1_5)) & 0xfffff000))
++#define SET_TX_ACK_POLICY_1_6(_VAL_) (REG32(ADR_TX_ACK_POLICY_1_6)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_1_6)) & 0xfffffffc))
++#define SET_TX_SEQ_CTRL_1_6(_VAL_) (REG32(ADR_TX_SEQ_CTRL_1_6)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_1_6)) & 0xfffff000))
++#define SET_TX_ACK_POLICY_1_7(_VAL_) (REG32(ADR_TX_ACK_POLICY_1_7)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_1_7)) & 0xfffffffc))
++#define SET_TX_SEQ_CTRL_1_7(_VAL_) (REG32(ADR_TX_SEQ_CTRL_1_7)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_1_7)) & 0xfffff000))
++#define SET_INFO0(_VAL_) (REG32(ADR_INFO0)) = (((_VAL_) << 0) | ((REG32(ADR_INFO0)) & 0x00000000))
++#define SET_INFO1(_VAL_) (REG32(ADR_INFO1)) = (((_VAL_) << 0) | ((REG32(ADR_INFO1)) & 0x00000000))
++#define SET_INFO2(_VAL_) (REG32(ADR_INFO2)) = (((_VAL_) << 0) | ((REG32(ADR_INFO2)) & 0x00000000))
++#define SET_INFO3(_VAL_) (REG32(ADR_INFO3)) = (((_VAL_) << 0) | ((REG32(ADR_INFO3)) & 0x00000000))
++#define SET_INFO4(_VAL_) (REG32(ADR_INFO4)) = (((_VAL_) << 0) | ((REG32(ADR_INFO4)) & 0x00000000))
++#define SET_INFO5(_VAL_) (REG32(ADR_INFO5)) = (((_VAL_) << 0) | ((REG32(ADR_INFO5)) & 0x00000000))
++#define SET_INFO6(_VAL_) (REG32(ADR_INFO6)) = (((_VAL_) << 0) | ((REG32(ADR_INFO6)) & 0x00000000))
++#define SET_INFO7(_VAL_) (REG32(ADR_INFO7)) = (((_VAL_) << 0) | ((REG32(ADR_INFO7)) & 0x00000000))
++#define SET_INFO8(_VAL_) (REG32(ADR_INFO8)) = (((_VAL_) << 0) | ((REG32(ADR_INFO8)) & 0x00000000))
++#define SET_INFO9(_VAL_) (REG32(ADR_INFO9)) = (((_VAL_) << 0) | ((REG32(ADR_INFO9)) & 0x00000000))
++#define SET_INFO10(_VAL_) (REG32(ADR_INFO10)) = (((_VAL_) << 0) | ((REG32(ADR_INFO10)) & 0x00000000))
++#define SET_INFO11(_VAL_) (REG32(ADR_INFO11)) = (((_VAL_) << 0) | ((REG32(ADR_INFO11)) & 0x00000000))
++#define SET_INFO12(_VAL_) (REG32(ADR_INFO12)) = (((_VAL_) << 0) | ((REG32(ADR_INFO12)) & 0x00000000))
++#define SET_INFO13(_VAL_) (REG32(ADR_INFO13)) = (((_VAL_) << 0) | ((REG32(ADR_INFO13)) & 0x00000000))
++#define SET_INFO14(_VAL_) (REG32(ADR_INFO14)) = (((_VAL_) << 0) | ((REG32(ADR_INFO14)) & 0x00000000))
++#define SET_INFO15(_VAL_) (REG32(ADR_INFO15)) = (((_VAL_) << 0) | ((REG32(ADR_INFO15)) & 0x00000000))
++#define SET_INFO16(_VAL_) (REG32(ADR_INFO16)) = (((_VAL_) << 0) | ((REG32(ADR_INFO16)) & 0x00000000))
++#define SET_INFO17(_VAL_) (REG32(ADR_INFO17)) = (((_VAL_) << 0) | ((REG32(ADR_INFO17)) & 0x00000000))
++#define SET_INFO18(_VAL_) (REG32(ADR_INFO18)) = (((_VAL_) << 0) | ((REG32(ADR_INFO18)) & 0x00000000))
++#define SET_INFO19(_VAL_) (REG32(ADR_INFO19)) = (((_VAL_) << 0) | ((REG32(ADR_INFO19)) & 0x00000000))
++#define SET_INFO20(_VAL_) (REG32(ADR_INFO20)) = (((_VAL_) << 0) | ((REG32(ADR_INFO20)) & 0x00000000))
++#define SET_INFO21(_VAL_) (REG32(ADR_INFO21)) = (((_VAL_) << 0) | ((REG32(ADR_INFO21)) & 0x00000000))
++#define SET_INFO22(_VAL_) (REG32(ADR_INFO22)) = (((_VAL_) << 0) | ((REG32(ADR_INFO22)) & 0x00000000))
++#define SET_INFO23(_VAL_) (REG32(ADR_INFO23)) = (((_VAL_) << 0) | ((REG32(ADR_INFO23)) & 0x00000000))
++#define SET_INFO24(_VAL_) (REG32(ADR_INFO24)) = (((_VAL_) << 0) | ((REG32(ADR_INFO24)) & 0x00000000))
++#define SET_INFO25(_VAL_) (REG32(ADR_INFO25)) = (((_VAL_) << 0) | ((REG32(ADR_INFO25)) & 0x00000000))
++#define SET_INFO26(_VAL_) (REG32(ADR_INFO26)) = (((_VAL_) << 0) | ((REG32(ADR_INFO26)) & 0x00000000))
++#define SET_INFO27(_VAL_) (REG32(ADR_INFO27)) = (((_VAL_) << 0) | ((REG32(ADR_INFO27)) & 0x00000000))
++#define SET_INFO28(_VAL_) (REG32(ADR_INFO28)) = (((_VAL_) << 0) | ((REG32(ADR_INFO28)) & 0x00000000))
++#define SET_INFO29(_VAL_) (REG32(ADR_INFO29)) = (((_VAL_) << 0) | ((REG32(ADR_INFO29)) & 0x00000000))
++#define SET_INFO30(_VAL_) (REG32(ADR_INFO30)) = (((_VAL_) << 0) | ((REG32(ADR_INFO30)) & 0x00000000))
++#define SET_INFO31(_VAL_) (REG32(ADR_INFO31)) = (((_VAL_) << 0) | ((REG32(ADR_INFO31)) & 0x00000000))
++#define SET_INFO32(_VAL_) (REG32(ADR_INFO32)) = (((_VAL_) << 0) | ((REG32(ADR_INFO32)) & 0x00000000))
++#define SET_INFO33(_VAL_) (REG32(ADR_INFO33)) = (((_VAL_) << 0) | ((REG32(ADR_INFO33)) & 0x00000000))
++#define SET_INFO34(_VAL_) (REG32(ADR_INFO34)) = (((_VAL_) << 0) | ((REG32(ADR_INFO34)) & 0x00000000))
++#define SET_INFO35(_VAL_) (REG32(ADR_INFO35)) = (((_VAL_) << 0) | ((REG32(ADR_INFO35)) & 0x00000000))
++#define SET_INFO36(_VAL_) (REG32(ADR_INFO36)) = (((_VAL_) << 0) | ((REG32(ADR_INFO36)) & 0x00000000))
++#define SET_INFO37(_VAL_) (REG32(ADR_INFO37)) = (((_VAL_) << 0) | ((REG32(ADR_INFO37)) & 0x00000000))
++#define SET_INFO38(_VAL_) (REG32(ADR_INFO38)) = (((_VAL_) << 0) | ((REG32(ADR_INFO38)) & 0x00000000))
++#define SET_INFO_MASK(_VAL_) (REG32(ADR_INFO_MASK)) = (((_VAL_) << 0) | ((REG32(ADR_INFO_MASK)) & 0x00000000))
++#define SET_INFO_DEF_RATE(_VAL_) (REG32(ADR_INFO_RATE_OFFSET)) = (((_VAL_) << 0) | ((REG32(ADR_INFO_RATE_OFFSET)) & 0xffffffc0))
++#define SET_INFO_MRX_OFFSET(_VAL_) (REG32(ADR_INFO_RATE_OFFSET)) = (((_VAL_) << 16) | ((REG32(ADR_INFO_RATE_OFFSET)) & 0xfff0ffff))
++#define SET_BCAST_RATEUNKNOW(_VAL_) (REG32(ADR_INFO_RATE_OFFSET)) = (((_VAL_) << 24) | ((REG32(ADR_INFO_RATE_OFFSET)) & 0xc0ffffff))
++#define SET_INFO_IDX_TBL_ADDR(_VAL_) (REG32(ADR_INFO_IDX_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_INFO_IDX_ADDR)) & 0x00000000))
++#define SET_INFO_LEN_TBL_ADDR(_VAL_) (REG32(ADR_INFO_LEN_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_INFO_LEN_ADDR)) & 0x00000000))
++#define SET_IC_TAG_31_0(_VAL_) (REG32(ADR_IC_TIME_TAG_0)) = (((_VAL_) << 0) | ((REG32(ADR_IC_TIME_TAG_0)) & 0x00000000))
++#define SET_IC_TAG_63_32(_VAL_) (REG32(ADR_IC_TIME_TAG_1)) = (((_VAL_) << 0) | ((REG32(ADR_IC_TIME_TAG_1)) & 0x00000000))
++#define SET_CH1_PRI(_VAL_) (REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) = (((_VAL_) << 0) | ((REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) & 0xfffffffc))
++#define SET_CH2_PRI(_VAL_) (REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) = (((_VAL_) << 8) | ((REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) & 0xfffffcff))
++#define SET_CH3_PRI(_VAL_) (REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) = (((_VAL_) << 16) | ((REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) & 0xfffcffff))
++#define SET_RG_MAC_LPBK(_VAL_) (REG32(ADR_MAC_MODE)) = (((_VAL_) << 0) | ((REG32(ADR_MAC_MODE)) & 0xfffffffe))
++#define SET_RG_MAC_M2M(_VAL_) (REG32(ADR_MAC_MODE)) = (((_VAL_) << 1) | ((REG32(ADR_MAC_MODE)) & 0xfffffffd))
++#define SET_RG_PHY_LPBK(_VAL_) (REG32(ADR_MAC_MODE)) = (((_VAL_) << 2) | ((REG32(ADR_MAC_MODE)) & 0xfffffffb))
++#define SET_RG_LPBK_RX_EN(_VAL_) (REG32(ADR_MAC_MODE)) = (((_VAL_) << 3) | ((REG32(ADR_MAC_MODE)) & 0xfffffff7))
++#define SET_EXT_MAC_MODE(_VAL_) (REG32(ADR_MAC_MODE)) = (((_VAL_) << 4) | ((REG32(ADR_MAC_MODE)) & 0xffffffef))
++#define SET_EXT_PHY_MODE(_VAL_) (REG32(ADR_MAC_MODE)) = (((_VAL_) << 5) | ((REG32(ADR_MAC_MODE)) & 0xffffffdf))
++#define SET_ASIC_TAG(_VAL_) (REG32(ADR_MAC_MODE)) = (((_VAL_) << 24) | ((REG32(ADR_MAC_MODE)) & 0x00ffffff))
++#define SET_HCI_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 0) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xfffffffe))
++#define SET_CO_PROC_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 1) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xfffffffd))
++#define SET_MTX_MISC_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 3) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xfffffff7))
++#define SET_MTX_QUE_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 4) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xffffffef))
++#define SET_MTX_CHST_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 5) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xffffffdf))
++#define SET_MTX_BCN_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 6) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xffffffbf))
++#define SET_MRX_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 7) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xffffff7f))
++#define SET_AMPDU_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 8) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xfffffeff))
++#define SET_MMU_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 9) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xfffffdff))
++#define SET_ID_MNG_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 11) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xfffff7ff))
++#define SET_MBOX_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 12) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xffffefff))
++#define SET_SCRT_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 13) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xffffdfff))
++#define SET_MIC_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 14) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xffffbfff))
++#define SET_CO_PROC_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 1) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xfffffffd))
++#define SET_MTX_MISC_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 3) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xfffffff7))
++#define SET_MTX_QUE_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 4) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xffffffef))
++#define SET_MTX_CHST_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 5) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xffffffdf))
++#define SET_MTX_BCN_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 6) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xffffffbf))
++#define SET_MRX_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 7) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xffffff7f))
++#define SET_AMPDU_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 8) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xfffffeff))
++#define SET_ID_MNG_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 14) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xffffbfff))
++#define SET_MBOX_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 15) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xffff7fff))
++#define SET_SCRT_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 16) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xfffeffff))
++#define SET_MIC_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 17) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xfffdffff))
++#define SET_CO_PROC_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 1) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xfffffffd))
++#define SET_MTX_MISC_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 3) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xfffffff7))
++#define SET_MTX_QUE0_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 4) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xffffffef))
++#define SET_MTX_QUE1_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 5) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xffffffdf))
++#define SET_MTX_QUE2_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 6) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xffffffbf))
++#define SET_MTX_QUE3_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 7) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xffffff7f))
++#define SET_MTX_QUE4_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 8) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xfffffeff))
++#define SET_MTX_QUE5_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 9) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xfffffdff))
++#define SET_MRX_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 10) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xfffffbff))
++#define SET_AMPDU_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 11) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xfffff7ff))
++#define SET_SCRT_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 13) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xffffdfff))
++#define SET_ID_MNG_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 14) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xffffbfff))
++#define SET_MBOX_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 15) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xffff7fff))
++#define SET_HCI_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 0) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xfffffffe))
++#define SET_CO_PROC_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 1) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xfffffffd))
++#define SET_MTX_MISC_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 3) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xfffffff7))
++#define SET_MTX_QUE_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 4) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xffffffef))
++#define SET_MRX_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 5) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xffffffdf))
++#define SET_AMPDU_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 6) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xffffffbf))
++#define SET_MMU_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 7) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xffffff7f))
++#define SET_ID_MNG_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 9) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xfffffdff))
++#define SET_MBOX_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 10) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xfffffbff))
++#define SET_SCRT_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 11) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xfffff7ff))
++#define SET_MIC_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 12) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xffffefff))
++#define SET_MIB_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 13) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xffffdfff))
++#define SET_HCI_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 0) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xfffffffe))
++#define SET_CO_PROC_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 1) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xfffffffd))
++#define SET_MTX_MISC_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 3) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xfffffff7))
++#define SET_MTX_QUE_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 4) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xffffffef))
++#define SET_MRX_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 5) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xffffffdf))
++#define SET_AMPDU_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 6) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xffffffbf))
++#define SET_ID_MNG_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 12) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xffffefff))
++#define SET_MBOX_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 13) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xffffdfff))
++#define SET_SCRT_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 14) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xffffbfff))
++#define SET_MIC_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 15) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xffff7fff))
++#define SET_CO_PROC_CSR_CLK_EN(_VAL_) (REG32(ADR_MAC_CSR_CLOCK_ENABLE)) = (((_VAL_) << 1) | ((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0xfffffffd))
++#define SET_MRX_CSR_CLK_EN(_VAL_) (REG32(ADR_MAC_CSR_CLOCK_ENABLE)) = (((_VAL_) << 10) | ((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0xfffffbff))
++#define SET_AMPDU_CSR_CLK_EN(_VAL_) (REG32(ADR_MAC_CSR_CLOCK_ENABLE)) = (((_VAL_) << 11) | ((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0xfffff7ff))
++#define SET_SCRT_CSR_CLK_EN(_VAL_) (REG32(ADR_MAC_CSR_CLOCK_ENABLE)) = (((_VAL_) << 13) | ((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0xffffdfff))
++#define SET_ID_MNG_CSR_CLK_EN(_VAL_) (REG32(ADR_MAC_CSR_CLOCK_ENABLE)) = (((_VAL_) << 14) | ((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0xffffbfff))
++#define SET_MBOX_CSR_CLK_EN(_VAL_) (REG32(ADR_MAC_CSR_CLOCK_ENABLE)) = (((_VAL_) << 15) | ((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0xffff7fff))
++#define SET_OP_MODE(_VAL_) (REG32(ADR_GLBLE_SET)) = (((_VAL_) << 0) | ((REG32(ADR_GLBLE_SET)) & 0xfffffffc))
++#define SET_HT_MODE(_VAL_) (REG32(ADR_GLBLE_SET)) = (((_VAL_) << 2) | ((REG32(ADR_GLBLE_SET)) & 0xfffffff3))
++#define SET_QOS_EN(_VAL_) (REG32(ADR_GLBLE_SET)) = (((_VAL_) << 4) | ((REG32(ADR_GLBLE_SET)) & 0xffffffef))
++#define SET_PB_OFFSET(_VAL_) (REG32(ADR_GLBLE_SET)) = (((_VAL_) << 8) | ((REG32(ADR_GLBLE_SET)) & 0xffff00ff))
++#define SET_SNIFFER_MODE(_VAL_) (REG32(ADR_GLBLE_SET)) = (((_VAL_) << 16) | ((REG32(ADR_GLBLE_SET)) & 0xfffeffff))
++#define SET_DUP_FLT(_VAL_) (REG32(ADR_GLBLE_SET)) = (((_VAL_) << 17) | ((REG32(ADR_GLBLE_SET)) & 0xfffdffff))
++#define SET_TX_PKT_RSVD(_VAL_) (REG32(ADR_GLBLE_SET)) = (((_VAL_) << 18) | ((REG32(ADR_GLBLE_SET)) & 0xffe3ffff))
++#define SET_AMPDU_SNIFFER(_VAL_) (REG32(ADR_GLBLE_SET)) = (((_VAL_) << 21) | ((REG32(ADR_GLBLE_SET)) & 0xffdfffff))
++#define SET_REASON_TRAP0(_VAL_) (REG32(ADR_REASON_TRAP0)) = (((_VAL_) << 0) | ((REG32(ADR_REASON_TRAP0)) & 0x00000000))
++#define SET_REASON_TRAP1(_VAL_) (REG32(ADR_REASON_TRAP1)) = (((_VAL_) << 0) | ((REG32(ADR_REASON_TRAP1)) & 0x00000000))
++#define SET_BSSID_31_0(_VAL_) (REG32(ADR_BSSID_0)) = (((_VAL_) << 0) | ((REG32(ADR_BSSID_0)) & 0x00000000))
++#define SET_BSSID_47_32(_VAL_) (REG32(ADR_BSSID_1)) = (((_VAL_) << 0) | ((REG32(ADR_BSSID_1)) & 0xffff0000))
++#define SET_SCRT_STATE(_VAL_) (REG32(ADR_SCRT_STATE)) = (((_VAL_) << 0) | ((REG32(ADR_SCRT_STATE)) & 0xfffffff0))
++#define SET_STA_MAC_31_0(_VAL_) (REG32(ADR_STA_MAC_0)) = (((_VAL_) << 0) | ((REG32(ADR_STA_MAC_0)) & 0x00000000))
++#define SET_STA_MAC_47_32(_VAL_) (REG32(ADR_STA_MAC_1)) = (((_VAL_) << 0) | ((REG32(ADR_STA_MAC_1)) & 0xffff0000))
++#define SET_PAIR_SCRT(_VAL_) (REG32(ADR_SCRT_SET)) = (((_VAL_) << 0) | ((REG32(ADR_SCRT_SET)) & 0xfffffff8))
++#define SET_GRP_SCRT(_VAL_) (REG32(ADR_SCRT_SET)) = (((_VAL_) << 3) | ((REG32(ADR_SCRT_SET)) & 0xffffffc7))
++#define SET_SCRT_PKT_ID(_VAL_) (REG32(ADR_SCRT_SET)) = (((_VAL_) << 6) | ((REG32(ADR_SCRT_SET)) & 0xffffe03f))
++#define SET_SCRT_RPLY_IGNORE(_VAL_) (REG32(ADR_SCRT_SET)) = (((_VAL_) << 16) | ((REG32(ADR_SCRT_SET)) & 0xfffeffff))
++#define SET_COEXIST_EN(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 0) | ((REG32(ADR_BTCX0)) & 0xfffffffe))
++#define SET_WIRE_MODE(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 1) | ((REG32(ADR_BTCX0)) & 0xfffffff1))
++#define SET_WL_RX_PRI(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 4) | ((REG32(ADR_BTCX0)) & 0xffffffef))
++#define SET_WL_TX_PRI(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 5) | ((REG32(ADR_BTCX0)) & 0xffffffdf))
++#define SET_GURAN_USE_EN(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 8) | ((REG32(ADR_BTCX0)) & 0xfffffeff))
++#define SET_GURAN_USE_CTRL(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 9) | ((REG32(ADR_BTCX0)) & 0xfffffdff))
++#define SET_BEACON_TIMEOUT_EN(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 10) | ((REG32(ADR_BTCX0)) & 0xfffffbff))
++#define SET_WLAN_ACT_POL(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 11) | ((REG32(ADR_BTCX0)) & 0xfffff7ff))
++#define SET_DUAL_ANT_EN(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 12) | ((REG32(ADR_BTCX0)) & 0xffffefff))
++#define SET_TRSW_PHY_POL(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 16) | ((REG32(ADR_BTCX0)) & 0xfffeffff))
++#define SET_WIFI_TX_SW_POL(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 17) | ((REG32(ADR_BTCX0)) & 0xfffdffff))
++#define SET_WIFI_RX_SW_POL(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 18) | ((REG32(ADR_BTCX0)) & 0xfffbffff))
++#define SET_BT_SW_POL(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 19) | ((REG32(ADR_BTCX0)) & 0xfff7ffff))
++#define SET_BT_PRI_SMP_TIME(_VAL_) (REG32(ADR_BTCX1)) = (((_VAL_) << 0) | ((REG32(ADR_BTCX1)) & 0xffffff00))
++#define SET_BT_STA_SMP_TIME(_VAL_) (REG32(ADR_BTCX1)) = (((_VAL_) << 8) | ((REG32(ADR_BTCX1)) & 0xffff00ff))
++#define SET_BEACON_TIMEOUT(_VAL_) (REG32(ADR_BTCX1)) = (((_VAL_) << 16) | ((REG32(ADR_BTCX1)) & 0xff00ffff))
++#define SET_WLAN_REMAIN_TIME(_VAL_) (REG32(ADR_BTCX1)) = (((_VAL_) << 24) | ((REG32(ADR_BTCX1)) & 0x00ffffff))
++#define SET_SW_MANUAL_EN(_VAL_) (REG32(ADR_SWITCH_CTL)) = (((_VAL_) << 0) | ((REG32(ADR_SWITCH_CTL)) & 0xfffffffe))
++#define SET_SW_WL_TX(_VAL_) (REG32(ADR_SWITCH_CTL)) = (((_VAL_) << 1) | ((REG32(ADR_SWITCH_CTL)) & 0xfffffffd))
++#define SET_SW_WL_RX(_VAL_) (REG32(ADR_SWITCH_CTL)) = (((_VAL_) << 2) | ((REG32(ADR_SWITCH_CTL)) & 0xfffffffb))
++#define SET_SW_BT_TRX(_VAL_) (REG32(ADR_SWITCH_CTL)) = (((_VAL_) << 3) | ((REG32(ADR_SWITCH_CTL)) & 0xfffffff7))
++#define SET_BT_TXBAR_MANUAL_EN(_VAL_) (REG32(ADR_SWITCH_CTL)) = (((_VAL_) << 4) | ((REG32(ADR_SWITCH_CTL)) & 0xffffffef))
++#define SET_BT_TXBAR_SET(_VAL_) (REG32(ADR_SWITCH_CTL)) = (((_VAL_) << 5) | ((REG32(ADR_SWITCH_CTL)) & 0xffffffdf))
++#define SET_BT_BUSY_MANUAL_EN(_VAL_) (REG32(ADR_SWITCH_CTL)) = (((_VAL_) << 8) | ((REG32(ADR_SWITCH_CTL)) & 0xfffffeff))
++#define SET_BT_BUSY_SET(_VAL_) (REG32(ADR_SWITCH_CTL)) = (((_VAL_) << 9) | ((REG32(ADR_SWITCH_CTL)) & 0xfffffdff))
++#define SET_G0_PKT_CLS_MIB_EN(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 2) | ((REG32(ADR_MIB_EN)) & 0xfffffffb))
++#define SET_G0_PKT_CLS_ONGOING(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 3) | ((REG32(ADR_MIB_EN)) & 0xfffffff7))
++#define SET_G1_PKT_CLS_MIB_EN(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 4) | ((REG32(ADR_MIB_EN)) & 0xffffffef))
++#define SET_G1_PKT_CLS_ONGOING(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 5) | ((REG32(ADR_MIB_EN)) & 0xffffffdf))
++#define SET_Q0_PKT_CLS_MIB_EN(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 6) | ((REG32(ADR_MIB_EN)) & 0xffffffbf))
++#define SET_Q0_PKT_CLS_ONGOING(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 7) | ((REG32(ADR_MIB_EN)) & 0xffffff7f))
++#define SET_Q1_PKT_CLS_MIB_EN(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 8) | ((REG32(ADR_MIB_EN)) & 0xfffffeff))
++#define SET_Q1_PKT_CLS_ONGOING(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 9) | ((REG32(ADR_MIB_EN)) & 0xfffffdff))
++#define SET_Q2_PKT_CLS_MIB_EN(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 10) | ((REG32(ADR_MIB_EN)) & 0xfffffbff))
++#define SET_Q2_PKT_CLS_ONGOING(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 11) | ((REG32(ADR_MIB_EN)) & 0xfffff7ff))
++#define SET_Q3_PKT_CLS_MIB_EN(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 12) | ((REG32(ADR_MIB_EN)) & 0xffffefff))
++#define SET_Q3_PKT_CLS_ONGOING(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 13) | ((REG32(ADR_MIB_EN)) & 0xffffdfff))
++#define SET_SCRT_PKT_CLS_MIB_EN(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 14) | ((REG32(ADR_MIB_EN)) & 0xffffbfff))
++#define SET_SCRT_PKT_CLS_ONGOING(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 15) | ((REG32(ADR_MIB_EN)) & 0xffff7fff))
++#define SET_MISC_PKT_CLS_MIB_EN(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 16) | ((REG32(ADR_MIB_EN)) & 0xfffeffff))
++#define SET_MISC_PKT_CLS_ONGOING(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 17) | ((REG32(ADR_MIB_EN)) & 0xfffdffff))
++#define SET_MTX_WSID0_SUCC(_VAL_) (REG32(ADR_MTX_WSID0_SUCC)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_WSID0_SUCC)) & 0xffff0000))
++#define SET_MTX_WSID0_FRM(_VAL_) (REG32(ADR_MTX_WSID0_FRM)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_WSID0_FRM)) & 0xffff0000))
++#define SET_MTX_WSID0_RETRY(_VAL_) (REG32(ADR_MTX_WSID0_RETRY)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_WSID0_RETRY)) & 0xffff0000))
++#define SET_MTX_WSID0_TOTAL(_VAL_) (REG32(ADR_MTX_WSID0_TOTAL)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_WSID0_TOTAL)) & 0xffff0000))
++#define SET_MTX_GRP(_VAL_) (REG32(ADR_MTX_GROUP)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_GROUP)) & 0xfff00000))
++#define SET_MTX_FAIL(_VAL_) (REG32(ADR_MTX_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_FAIL)) & 0xffff0000))
++#define SET_MTX_RETRY(_VAL_) (REG32(ADR_MTX_RETRY)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_RETRY)) & 0xfff00000))
++#define SET_MTX_MULTI_RETRY(_VAL_) (REG32(ADR_MTX_MULTI_RETRY)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_MULTI_RETRY)) & 0xfff00000))
++#define SET_MTX_RTS_SUCC(_VAL_) (REG32(ADR_MTX_RTS_SUCCESS)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_RTS_SUCCESS)) & 0xffff0000))
++#define SET_MTX_RTS_FAIL(_VAL_) (REG32(ADR_MTX_RTS_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_RTS_FAIL)) & 0xffff0000))
++#define SET_MTX_ACK_FAIL(_VAL_) (REG32(ADR_MTX_ACK_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_ACK_FAIL)) & 0xffff0000))
++#define SET_MTX_FRM(_VAL_) (REG32(ADR_MTX_FRM)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_FRM)) & 0xfff00000))
++#define SET_MTX_ACK_TX(_VAL_) (REG32(ADR_MTX_ACK_TX)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_ACK_TX)) & 0xffff0000))
++#define SET_MTX_CTS_TX(_VAL_) (REG32(ADR_MTX_CTS_TX)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_CTS_TX)) & 0xffff0000))
++#define SET_MRX_DUP(_VAL_) (REG32(ADR_MRX_DUP_FRM)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_DUP_FRM)) & 0xffff0000))
++#define SET_MRX_FRG(_VAL_) (REG32(ADR_MRX_FRG_FRM)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FRG_FRM)) & 0xfff00000))
++#define SET_MRX_GRP(_VAL_) (REG32(ADR_MRX_GROUP_FRM)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_GROUP_FRM)) & 0xfff00000))
++#define SET_MRX_FCS_ERR(_VAL_) (REG32(ADR_MRX_FCS_ERR)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FCS_ERR)) & 0xffff0000))
++#define SET_MRX_FCS_SUC(_VAL_) (REG32(ADR_MRX_FCS_SUCC)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FCS_SUCC)) & 0xffff0000))
++#define SET_MRX_MISS(_VAL_) (REG32(ADR_MRX_MISS)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MISS)) & 0xffff0000))
++#define SET_MRX_ALC_FAIL(_VAL_) (REG32(ADR_MRX_ALC_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_ALC_FAIL)) & 0xffff0000))
++#define SET_MRX_DAT_NTF(_VAL_) (REG32(ADR_MRX_DAT_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_DAT_NTF)) & 0xffff0000))
++#define SET_MRX_RTS_NTF(_VAL_) (REG32(ADR_MRX_RTS_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_RTS_NTF)) & 0xffff0000))
++#define SET_MRX_CTS_NTF(_VAL_) (REG32(ADR_MRX_CTS_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_CTS_NTF)) & 0xffff0000))
++#define SET_MRX_ACK_NTF(_VAL_) (REG32(ADR_MRX_ACK_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_ACK_NTF)) & 0xffff0000))
++#define SET_MRX_BA_NTF(_VAL_) (REG32(ADR_MRX_BA_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_BA_NTF)) & 0xffff0000))
++#define SET_MRX_DATA_NTF(_VAL_) (REG32(ADR_MRX_DATA_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_DATA_NTF)) & 0xffff0000))
++#define SET_MRX_MNG_NTF(_VAL_) (REG32(ADR_MRX_MNG_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MNG_NTF)) & 0xffff0000))
++#define SET_MRX_DAT_CRC_NTF(_VAL_) (REG32(ADR_MRX_DAT_CRC_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_DAT_CRC_NTF)) & 0xffff0000))
++#define SET_MRX_BAR_NTF(_VAL_) (REG32(ADR_MRX_BAR_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_BAR_NTF)) & 0xffff0000))
++#define SET_MRX_MB_MISS(_VAL_) (REG32(ADR_MRX_MB_MISS)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MB_MISS)) & 0xffff0000))
++#define SET_MRX_NIDLE_MISS(_VAL_) (REG32(ADR_MRX_NIDLE_MISS)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_NIDLE_MISS)) & 0xffff0000))
++#define SET_MRX_CSR_NTF(_VAL_) (REG32(ADR_MRX_CSR_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_CSR_NTF)) & 0xffff0000))
++#define SET_DBG_Q0_SUCC(_VAL_) (REG32(ADR_DBG_Q0_FRM_SUCCESS)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q0_FRM_SUCCESS)) & 0xffff0000))
++#define SET_DBG_Q0_FAIL(_VAL_) (REG32(ADR_DBG_Q0_FRM_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q0_FRM_FAIL)) & 0xffff0000))
++#define SET_DBG_Q0_ACK_SUCC(_VAL_) (REG32(ADR_DBG_Q0_ACK_SUCCESS)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q0_ACK_SUCCESS)) & 0xffff0000))
++#define SET_DBG_Q0_ACK_FAIL(_VAL_) (REG32(ADR_DBG_Q0_ACK_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q0_ACK_FAIL)) & 0xffff0000))
++#define SET_DBG_Q1_SUCC(_VAL_) (REG32(ADR_DBG_Q1_FRM_SUCCESS)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q1_FRM_SUCCESS)) & 0xffff0000))
++#define SET_DBG_Q1_FAIL(_VAL_) (REG32(ADR_DBG_Q1_FRM_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q1_FRM_FAIL)) & 0xffff0000))
++#define SET_DBG_Q1_ACK_SUCC(_VAL_) (REG32(ADR_DBG_Q1_ACK_SUCCESS)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q1_ACK_SUCCESS)) & 0xffff0000))
++#define SET_DBG_Q1_ACK_FAIL(_VAL_) (REG32(ADR_DBG_Q1_ACK_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q1_ACK_FAIL)) & 0xffff0000))
++#define SET_DBG_Q2_SUCC(_VAL_) (REG32(ADR_DBG_Q2_FRM_SUCCESS)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q2_FRM_SUCCESS)) & 0xffff0000))
++#define SET_DBG_Q2_FAIL(_VAL_) (REG32(ADR_DBG_Q2_FRM_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q2_FRM_FAIL)) & 0xffff0000))
++#define SET_DBG_Q2_ACK_SUCC(_VAL_) (REG32(ADR_DBG_Q2_ACK_SUCCESS)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q2_ACK_SUCCESS)) & 0xffff0000))
++#define SET_DBG_Q2_ACK_FAIL(_VAL_) (REG32(ADR_DBG_Q2_ACK_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q2_ACK_FAIL)) & 0xffff0000))
++#define SET_DBG_Q3_SUCC(_VAL_) (REG32(ADR_DBG_Q3_FRM_SUCCESS)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q3_FRM_SUCCESS)) & 0xffff0000))
++#define SET_DBG_Q3_FAIL(_VAL_) (REG32(ADR_DBG_Q3_FRM_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q3_FRM_FAIL)) & 0xffff0000))
++#define SET_DBG_Q3_ACK_SUCC(_VAL_) (REG32(ADR_DBG_Q3_ACK_SUCCESS)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q3_ACK_SUCCESS)) & 0xffff0000))
++#define SET_DBG_Q3_ACK_FAIL(_VAL_) (REG32(ADR_DBG_Q3_ACK_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q3_ACK_FAIL)) & 0xffff0000))
++#define SET_SCRT_TKIP_CERR(_VAL_) (REG32(ADR_MIB_SCRT_TKIP0)) = (((_VAL_) << 0) | ((REG32(ADR_MIB_SCRT_TKIP0)) & 0xfff00000))
++#define SET_SCRT_TKIP_MIC_ERR(_VAL_) (REG32(ADR_MIB_SCRT_TKIP1)) = (((_VAL_) << 0) | ((REG32(ADR_MIB_SCRT_TKIP1)) & 0xfff00000))
++#define SET_SCRT_TKIP_RPLY(_VAL_) (REG32(ADR_MIB_SCRT_TKIP2)) = (((_VAL_) << 0) | ((REG32(ADR_MIB_SCRT_TKIP2)) & 0xfff00000))
++#define SET_SCRT_CCMP_RPLY(_VAL_) (REG32(ADR_MIB_SCRT_CCMP0)) = (((_VAL_) << 0) | ((REG32(ADR_MIB_SCRT_CCMP0)) & 0xfff00000))
++#define SET_SCRT_CCMP_CERR(_VAL_) (REG32(ADR_MIB_SCRT_CCMP1)) = (((_VAL_) << 0) | ((REG32(ADR_MIB_SCRT_CCMP1)) & 0xfff00000))
++#define SET_DBG_LEN_CRC_FAIL(_VAL_) (REG32(ADR_DBG_LEN_CRC_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_LEN_CRC_FAIL)) & 0xffff0000))
++#define SET_DBG_LEN_ALC_FAIL(_VAL_) (REG32(ADR_DBG_LEN_ALC_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_LEN_ALC_FAIL)) & 0xffff0000))
++#define SET_DBG_AMPDU_PASS(_VAL_) (REG32(ADR_DBG_AMPDU_PASS)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_AMPDU_PASS)) & 0xffff0000))
++#define SET_DBG_AMPDU_FAIL(_VAL_) (REG32(ADR_DBG_AMPDU_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_AMPDU_FAIL)) & 0xffff0000))
++#define SET_RXID_ALC_CNT_FAIL(_VAL_) (REG32(ADR_ID_ALC_FAIL1)) = (((_VAL_) << 0) | ((REG32(ADR_ID_ALC_FAIL1)) & 0xffff0000))
++#define SET_RXID_ALC_LEN_FAIL(_VAL_) (REG32(ADR_ID_ALC_FAIL2)) = (((_VAL_) << 0) | ((REG32(ADR_ID_ALC_FAIL2)) & 0xffff0000))
++#define SET_CBR_RG_EN_MANUAL(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfffffffe))
++#define SET_CBR_RG_TX_EN(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfffffffd))
++#define SET_CBR_RG_TX_PA_EN(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfffffffb))
++#define SET_CBR_RG_TX_DAC_EN(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfffffff7))
++#define SET_CBR_RG_RX_AGC(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xffffffef))
++#define SET_CBR_RG_RX_GAIN_MANUAL(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xffffffdf))
++#define SET_CBR_RG_RFG(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xffffff3f))
++#define SET_CBR_RG_PGAG(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfffff0ff))
++#define SET_CBR_RG_MODE(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xffffcfff))
++#define SET_CBR_RG_EN_TX_TRSW(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xffffbfff))
++#define SET_CBR_RG_EN_SX(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 15) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xffff7fff))
++#define SET_CBR_RG_EN_RX_LNA(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfffeffff))
++#define SET_CBR_RG_EN_RX_MIXER(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 17) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfffdffff))
++#define SET_CBR_RG_EN_RX_DIV2(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfffbffff))
++#define SET_CBR_RG_EN_RX_LOBUF(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 19) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfff7ffff))
++#define SET_CBR_RG_EN_RX_TZ(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xffefffff))
++#define SET_CBR_RG_EN_RX_FILTER(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xffdfffff))
++#define SET_CBR_RG_EN_RX_HPF(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 22) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xffbfffff))
++#define SET_CBR_RG_EN_RX_RSSI(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 23) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xff7fffff))
++#define SET_CBR_RG_EN_ADC(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 24) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfeffffff))
++#define SET_CBR_RG_EN_TX_MOD(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 25) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfdffffff))
++#define SET_CBR_RG_EN_TX_DIV2(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 26) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfbffffff))
++#define SET_CBR_RG_EN_TX_DIV2_BUF(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 27) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xf7ffffff))
++#define SET_CBR_RG_EN_TX_LOBF(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 28) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xefffffff))
++#define SET_CBR_RG_EN_RX_LOBF(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 29) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xdfffffff))
++#define SET_CBR_RG_SEL_DPLL_CLK(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 30) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xbfffffff))
++#define SET_CBR_RG_EN_TX_DPD(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xfffffffe))
++#define SET_CBR_RG_EN_TX_TSSI(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xfffffffd))
++#define SET_CBR_RG_EN_RX_IQCAL(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xfffffffb))
++#define SET_CBR_RG_EN_TX_DAC_CAL(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xfffffff7))
++#define SET_CBR_RG_EN_TX_SELF_MIXER(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xffffffef))
++#define SET_CBR_RG_EN_TX_DAC_OUT(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xffffffdf))
++#define SET_CBR_RG_EN_LDO_RX_FE(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xffffffbf))
++#define SET_CBR_RG_EN_LDO_ABB(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 7) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xffffff7f))
++#define SET_CBR_RG_EN_LDO_AFE(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xfffffeff))
++#define SET_CBR_RG_EN_SX_CHPLDO(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xfffffdff))
++#define SET_CBR_RG_EN_SX_LOBFLDO(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xfffffbff))
++#define SET_CBR_RG_EN_IREF_RX(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xfffff7ff))
++#define SET_CBR_RG_DCDC_MODE(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xffffefff))
++#define SET_CBR_RG_LDO_LEVEL_RX_FE(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xfffffff8))
++#define SET_CBR_RG_LDO_LEVEL_ABB(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xffffffc7))
++#define SET_CBR_RG_LDO_LEVEL_AFE(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xfffffe3f))
++#define SET_CBR_RG_SX_LDO_CHP_LEVEL(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xfffff1ff))
++#define SET_CBR_RG_SX_LDO_LOBF_LEVEL(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xffff8fff))
++#define SET_CBR_RG_SX_LDO_XOSC_LEVEL(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 15) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xfffc7fff))
++#define SET_CBR_RG_DP_LDO_LEVEL(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xffe3ffff))
++#define SET_CBR_RG_SX_LDO_VCO_LEVEL(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xff1fffff))
++#define SET_CBR_RG_TX_LDO_TX_LEVEL(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 24) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xf8ffffff))
++#define SET_CBR_RG_BUCK_LEVEL(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 27) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xc7ffffff))
++#define SET_CBR_RG_EN_RX_PADSW(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfffffffe))
++#define SET_CBR_RG_EN_RX_TESTNODE(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfffffffd))
++#define SET_CBR_RG_RX_ABBCFIX(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfffffffb))
++#define SET_CBR_RG_RX_ABBCTUNE(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfffffe07))
++#define SET_CBR_RG_RX_ABBOUT_TRI_STATE(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfffffdff))
++#define SET_CBR_RG_RX_ABB_N_MODE(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfffffbff))
++#define SET_CBR_RG_RX_EN_LOOPA(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfffff7ff))
++#define SET_CBR_RG_RX_FILTERI1ST(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xffffcfff))
++#define SET_CBR_RG_RX_FILTERI2ND(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xffff3fff))
++#define SET_CBR_RG_RX_FILTERI3RD(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfffcffff))
++#define SET_CBR_RG_RX_FILTERI_COURSE(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfff3ffff))
++#define SET_CBR_RG_RX_FILTERVCM(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xffcfffff))
++#define SET_CBR_RG_RX_HPF3M(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 22) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xffbfffff))
++#define SET_CBR_RG_RX_HPF300K(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 23) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xff7fffff))
++#define SET_CBR_RG_RX_HPFI(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 24) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfcffffff))
++#define SET_CBR_RG_RX_HPF_FINALCORNER(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 26) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xf3ffffff))
++#define SET_CBR_RG_RX_HPF_SETTLE1_C(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 28) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xcfffffff))
++#define SET_CBR_RG_RX_HPF_SETTLE1_R(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xfffffffc))
++#define SET_CBR_RG_RX_HPF_SETTLE2_C(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xfffffff3))
++#define SET_CBR_RG_RX_HPF_SETTLE2_R(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 4) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xffffffcf))
++#define SET_CBR_RG_RX_HPF_VCMCON2(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xffffff3f))
++#define SET_CBR_RG_RX_HPF_VCMCON(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xfffffcff))
++#define SET_CBR_RG_RX_OUTVCM(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xfffff3ff))
++#define SET_CBR_RG_RX_TZI(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xffffcfff))
++#define SET_CBR_RG_RX_TZ_OUT_TRISTATE(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xffffbfff))
++#define SET_CBR_RG_RX_TZ_VCM(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 15) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xfffe7fff))
++#define SET_CBR_RG_EN_RX_RSSI_TESTNODE(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 17) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xfff1ffff))
++#define SET_CBR_RG_RX_ADCRSSI_CLKSEL(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xffefffff))
++#define SET_CBR_RG_RX_ADCRSSI_VCM(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 21) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xff9fffff))
++#define SET_CBR_RG_RX_REC_LPFCORNER(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 23) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xfe7fffff))
++#define SET_CBR_RG_RSSI_CLOCK_GATING(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 25) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xfdffffff))
++#define SET_CBR_RG_TXPGA_CAPSW(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xfffffffc))
++#define SET_CBR_RG_TXPGA_MAIN(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xffffff03))
++#define SET_CBR_RG_TXPGA_STEER(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xffffc0ff))
++#define SET_CBR_RG_TXMOD_GMCELL(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xffff3fff))
++#define SET_CBR_RG_TXLPF_GMCELL(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xfffcffff))
++#define SET_CBR_RG_PACELL_EN(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xffe3ffff))
++#define SET_CBR_RG_PABIAS_CTRL(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xfe1fffff))
++#define SET_CBR_RG_PABIAS_AB(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 25) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xfdffffff))
++#define SET_CBR_RG_TX_DIV_VSET(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 26) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xf3ffffff))
++#define SET_CBR_RG_TX_LOBUF_VSET(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 28) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xcfffffff))
++#define SET_CBR_RG_RX_SQDC(_VAL_) (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0xfffffff8))
++#define SET_CBR_RG_RX_DIV2_CORE(_VAL_) (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0xffffffe7))
++#define SET_CBR_RG_RX_LOBUF(_VAL_) (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0xffffff9f))
++#define SET_CBR_RG_TX_DPDGM_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (((_VAL_) << 7) | ((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0xfffff87f))
++#define SET_CBR_RG_TX_DPD_DIV(_VAL_) (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0xffff87ff))
++#define SET_CBR_RG_TX_TSSI_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (((_VAL_) << 15) | ((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0xfffc7fff))
++#define SET_CBR_RG_TX_TSSI_DIV(_VAL_) (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0xffe3ffff))
++#define SET_CBR_RG_TX_TSSI_TESTMODE(_VAL_) (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (((_VAL_) << 21) | ((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0xffdfffff))
++#define SET_CBR_RG_TX_TSSI_TEST(_VAL_) (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (((_VAL_) << 22) | ((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0xff3fffff))
++#define SET_CBR_RG_RX_HG_LNA_GC(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xfffffffc))
++#define SET_CBR_RG_RX_HG_LNAHGN_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xffffffc3))
++#define SET_CBR_RG_RX_HG_LNAHGP_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xfffffc3f))
++#define SET_CBR_RG_RX_HG_LNALG_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xffffc3ff))
++#define SET_CBR_RG_RX_HG_TZ_GC(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xffff3fff))
++#define SET_CBR_RG_RX_HG_TZ_CAP(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xfff8ffff))
++#define SET_CBR_RG_RX_MG_LNA_GC(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xfffffffc))
++#define SET_CBR_RG_RX_MG_LNAHGN_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xffffffc3))
++#define SET_CBR_RG_RX_MG_LNAHGP_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xfffffc3f))
++#define SET_CBR_RG_RX_MG_LNALG_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xffffc3ff))
++#define SET_CBR_RG_RX_MG_TZ_GC(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xffff3fff))
++#define SET_CBR_RG_RX_MG_TZ_CAP(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xfff8ffff))
++#define SET_CBR_RG_RX_LG_LNA_GC(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xfffffffc))
++#define SET_CBR_RG_RX_LG_LNAHGN_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xffffffc3))
++#define SET_CBR_RG_RX_LG_LNAHGP_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xfffffc3f))
++#define SET_CBR_RG_RX_LG_LNALG_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xffffc3ff))
++#define SET_CBR_RG_RX_LG_TZ_GC(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xffff3fff))
++#define SET_CBR_RG_RX_LG_TZ_CAP(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xfff8ffff))
++#define SET_CBR_RG_RX_ULG_LNA_GC(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xfffffffc))
++#define SET_CBR_RG_RX_ULG_LNAHGN_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xffffffc3))
++#define SET_CBR_RG_RX_ULG_LNAHGP_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xfffffc3f))
++#define SET_CBR_RG_RX_ULG_LNALG_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xffffc3ff))
++#define SET_CBR_RG_RX_ULG_TZ_GC(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xffff3fff))
++#define SET_CBR_RG_RX_ULG_TZ_CAP(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xfff8ffff))
++#define SET_CBR_RG_HPF1_FAST_SET_X(_VAL_) (REG32(ADR_CBR_RX_FSM_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0xfffffffe))
++#define SET_CBR_RG_HPF1_FAST_SET_Y(_VAL_) (REG32(ADR_CBR_RX_FSM_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0xfffffffd))
++#define SET_CBR_RG_HPF1_FAST_SET_Z(_VAL_) (REG32(ADR_CBR_RX_FSM_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0xfffffffb))
++#define SET_CBR_RG_HPF_T1A(_VAL_) (REG32(ADR_CBR_RX_FSM_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0xffffffe7))
++#define SET_CBR_RG_HPF_T1B(_VAL_) (REG32(ADR_CBR_RX_FSM_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0xffffff9f))
++#define SET_CBR_RG_HPF_T1C(_VAL_) (REG32(ADR_CBR_RX_FSM_REGISTER)) = (((_VAL_) << 7) | ((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0xfffffe7f))
++#define SET_CBR_RG_RX_LNA_TRI_SEL(_VAL_) (REG32(ADR_CBR_RX_FSM_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0xfffff9ff))
++#define SET_CBR_RG_RX_LNA_SETTLE(_VAL_) (REG32(ADR_CBR_RX_FSM_REGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0xffffe7ff))
++#define SET_CBR_RG_ADC_CLKSEL(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xfffffffe))
++#define SET_CBR_RG_ADC_DIBIAS(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xfffffff9))
++#define SET_CBR_RG_ADC_DIVR(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xfffffff7))
++#define SET_CBR_RG_ADC_DVCMI(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xffffffcf))
++#define SET_CBR_RG_ADC_SAMSEL(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xfffffc3f))
++#define SET_CBR_RG_ADC_STNBY(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xfffffbff))
++#define SET_CBR_RG_ADC_TESTMODE(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xfffff7ff))
++#define SET_CBR_RG_ADC_TSEL(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xffff0fff))
++#define SET_CBR_RG_ADC_VRSEL(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xfffcffff))
++#define SET_CBR_RG_DICMP(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xfff3ffff))
++#define SET_CBR_RG_DIOP(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xffcfffff))
++#define SET_CBR_RG_DACI1ST(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xfffffffc))
++#define SET_CBR_RG_TX_DACLPF_ICOURSE(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xfffffff3))
++#define SET_CBR_RG_TX_DACLPF_IFINE(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xffffffcf))
++#define SET_CBR_RG_TX_DACLPF_VCM(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xffffff3f))
++#define SET_CBR_RG_TX_DAC_CKEDGE_SEL(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xfffffeff))
++#define SET_CBR_RG_TX_DAC_IBIAS(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xfffff9ff))
++#define SET_CBR_RG_TX_DAC_OS(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xffffc7ff))
++#define SET_CBR_RG_TX_DAC_RCAL(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xffff3fff))
++#define SET_CBR_RG_TX_DAC_TSEL(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xfff0ffff))
++#define SET_CBR_RG_TX_EN_VOLTAGE_IN(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xffefffff))
++#define SET_CBR_RG_TXLPF_BYPASS(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xffdfffff))
++#define SET_CBR_RG_TXLPF_BOOSTI(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 22) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xffbfffff))
++#define SET_CBR_RG_EN_SX_R3(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xfffffffe))
++#define SET_CBR_RG_EN_SX_CH(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xfffffffd))
++#define SET_CBR_RG_EN_SX_CHP(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xfffffffb))
++#define SET_CBR_RG_EN_SX_DIVCK(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xfffffff7))
++#define SET_CBR_RG_EN_SX_VCOBF(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xffffffef))
++#define SET_CBR_RG_EN_SX_VCO(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xffffffdf))
++#define SET_CBR_RG_EN_SX_MOD(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xffffffbf))
++#define SET_CBR_RG_EN_SX_LCK(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 7) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xffffff7f))
++#define SET_CBR_RG_EN_SX_DITHER(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xfffffeff))
++#define SET_CBR_RG_EN_SX_DELCAL(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xfffffdff))
++#define SET_CBR_RG_EN_SX_PC_BYPASS(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xfffffbff))
++#define SET_CBR_RG_EN_SX_VT_MON(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xfffff7ff))
++#define SET_CBR_RG_EN_SX_VT_MON_DG(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xffffefff))
++#define SET_CBR_RG_EN_SX_DIV(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 13) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xffffdfff))
++#define SET_CBR_RG_EN_SX_LPF(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xffffbfff))
++#define SET_CBR_RG_SX_RFCTRL_F(_VAL_) (REG32(ADR_CBR_SYN_RGISTER_1)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_SYN_RGISTER_1)) & 0xff000000))
++#define SET_CBR_RG_SX_SEL_CP(_VAL_) (REG32(ADR_CBR_SYN_RGISTER_1)) = (((_VAL_) << 24) | ((REG32(ADR_CBR_SYN_RGISTER_1)) & 0xf0ffffff))
++#define SET_CBR_RG_SX_SEL_CS(_VAL_) (REG32(ADR_CBR_SYN_RGISTER_1)) = (((_VAL_) << 28) | ((REG32(ADR_CBR_SYN_RGISTER_1)) & 0x0fffffff))
++#define SET_CBR_RG_SX_RFCTRL_CH(_VAL_) (REG32(ADR_CBR_SYN_RGISTER_2)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_SYN_RGISTER_2)) & 0xfffff800))
++#define SET_CBR_RG_SX_SEL_C3(_VAL_) (REG32(ADR_CBR_SYN_RGISTER_2)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_SYN_RGISTER_2)) & 0xffff87ff))
++#define SET_CBR_RG_SX_SEL_RS(_VAL_) (REG32(ADR_CBR_SYN_RGISTER_2)) = (((_VAL_) << 15) | ((REG32(ADR_CBR_SYN_RGISTER_2)) & 0xfff07fff))
++#define SET_CBR_RG_SX_SEL_R3(_VAL_) (REG32(ADR_CBR_SYN_RGISTER_2)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_SYN_RGISTER_2)) & 0xfe0fffff))
++#define SET_CBR_RG_SX_SEL_ICHP(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xffffffe0))
++#define SET_CBR_RG_SX_SEL_PCHP(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xfffffc1f))
++#define SET_CBR_RG_SX_SEL_CHP_REGOP(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xffffc3ff))
++#define SET_CBR_RG_SX_SEL_CHP_UNIOP(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xfffc3fff))
++#define SET_CBR_RG_SX_CHP_IOST_POL(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xfffbffff))
++#define SET_CBR_RG_SX_CHP_IOST(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 19) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xffc7ffff))
++#define SET_CBR_RG_SX_PFDSEL(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 22) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xffbfffff))
++#define SET_CBR_RG_SX_PFD_SET(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 23) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xff7fffff))
++#define SET_CBR_RG_SX_PFD_SET1(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 24) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xfeffffff))
++#define SET_CBR_RG_SX_PFD_SET2(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 25) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xfdffffff))
++#define SET_CBR_RG_SX_VBNCAS_SEL(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 26) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xfbffffff))
++#define SET_CBR_RG_SX_PFD_RST_H(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 27) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xf7ffffff))
++#define SET_CBR_RG_SX_PFD_TRUP(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 28) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xefffffff))
++#define SET_CBR_RG_SX_PFD_TRDN(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 29) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xdfffffff))
++#define SET_CBR_RG_SX_PFD_TRSEL(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 30) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xbfffffff))
++#define SET_CBR_RG_SX_VCOBA_R(_VAL_) (REG32(ADR_CBR_SYN_VCO_LOBF)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0xfffffff8))
++#define SET_CBR_RG_SX_VCORSEL(_VAL_) (REG32(ADR_CBR_SYN_VCO_LOBF)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0xffffff07))
++#define SET_CBR_RG_SX_VCOCUSEL(_VAL_) (REG32(ADR_CBR_SYN_VCO_LOBF)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0xfffff0ff))
++#define SET_CBR_RG_SX_RXBFSEL(_VAL_) (REG32(ADR_CBR_SYN_VCO_LOBF)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0xffff0fff))
++#define SET_CBR_RG_SX_TXBFSEL(_VAL_) (REG32(ADR_CBR_SYN_VCO_LOBF)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0xfff0ffff))
++#define SET_CBR_RG_SX_VCOBFSEL(_VAL_) (REG32(ADR_CBR_SYN_VCO_LOBF)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0xff0fffff))
++#define SET_CBR_RG_SX_DIVBFSEL(_VAL_) (REG32(ADR_CBR_SYN_VCO_LOBF)) = (((_VAL_) << 24) | ((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0xf0ffffff))
++#define SET_CBR_RG_SX_GNDR_SEL(_VAL_) (REG32(ADR_CBR_SYN_VCO_LOBF)) = (((_VAL_) << 28) | ((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0x0fffffff))
++#define SET_CBR_RG_SX_DITHER_WEIGHT(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xfffffffc))
++#define SET_CBR_RG_SX_MOD_ERRCMP(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xfffffff3))
++#define SET_CBR_RG_SX_MOD_ORDER(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 4) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xffffffcf))
++#define SET_CBR_RG_SX_SDM_D1(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xffffffbf))
++#define SET_CBR_RG_SX_SDM_D2(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 7) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xffffff7f))
++#define SET_CBR_RG_SDM_PASS(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xfffffeff))
++#define SET_CBR_RG_SX_RST_H_DIV(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xfffffdff))
++#define SET_CBR_RG_SX_SDM_EDGE(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xfffffbff))
++#define SET_CBR_RG_SX_XO_GM(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xffffe7ff))
++#define SET_CBR_RG_SX_REFBYTWO(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 13) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xffffdfff))
++#define SET_CBR_RG_SX_XO_SWCAP(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xfffc3fff))
++#define SET_CBR_RG_SX_SDMLUT_INV(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xfffbffff))
++#define SET_CBR_RG_SX_LCKEN(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 19) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xfff7ffff))
++#define SET_CBR_RG_SX_PREVDD(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xff0fffff))
++#define SET_CBR_RG_SX_PSCONTERVDD(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 24) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xf0ffffff))
++#define SET_CBR_RG_SX_MOD_ERR_DELAY(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 28) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xcfffffff))
++#define SET_CBR_RG_SX_MODDB(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 30) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xbfffffff))
++#define SET_CBR_RG_SX_CV_CURVE_SEL(_VAL_) (REG32(ADR_CBR_SYN_LCK1)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_SYN_LCK1)) & 0xfffffffc))
++#define SET_CBR_RG_SX_SEL_DELAY(_VAL_) (REG32(ADR_CBR_SYN_LCK1)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_SYN_LCK1)) & 0xffffff83))
++#define SET_CBR_RG_SX_REF_CYCLE(_VAL_) (REG32(ADR_CBR_SYN_LCK1)) = (((_VAL_) << 7) | ((REG32(ADR_CBR_SYN_LCK1)) & 0xfffff87f))
++#define SET_CBR_RG_SX_VCOBY16(_VAL_) (REG32(ADR_CBR_SYN_LCK1)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_SYN_LCK1)) & 0xfffff7ff))
++#define SET_CBR_RG_SX_VCOBY32(_VAL_) (REG32(ADR_CBR_SYN_LCK1)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_SYN_LCK1)) & 0xffffefff))
++#define SET_CBR_RG_SX_PH(_VAL_) (REG32(ADR_CBR_SYN_LCK1)) = (((_VAL_) << 13) | ((REG32(ADR_CBR_SYN_LCK1)) & 0xffffdfff))
++#define SET_CBR_RG_SX_PL(_VAL_) (REG32(ADR_CBR_SYN_LCK1)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_SYN_LCK1)) & 0xffffbfff))
++#define SET_CBR_RG_SX_VT_MON_MODE(_VAL_) (REG32(ADR_CBR_SYN_LCK2)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_SYN_LCK2)) & 0xfffffffe))
++#define SET_CBR_RG_SX_VT_TH_HI(_VAL_) (REG32(ADR_CBR_SYN_LCK2)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_SYN_LCK2)) & 0xfffffff9))
++#define SET_CBR_RG_SX_VT_TH_LO(_VAL_) (REG32(ADR_CBR_SYN_LCK2)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_SYN_LCK2)) & 0xffffffe7))
++#define SET_CBR_RG_SX_VT_SET(_VAL_) (REG32(ADR_CBR_SYN_LCK2)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_SYN_LCK2)) & 0xffffffdf))
++#define SET_CBR_RG_SX_VT_MON_TMR(_VAL_) (REG32(ADR_CBR_SYN_LCK2)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_SYN_LCK2)) & 0xffff803f))
++#define SET_CBR_RG_IDEAL_CYCLE(_VAL_) (REG32(ADR_CBR_SYN_LCK2)) = (((_VAL_) << 15) | ((REG32(ADR_CBR_SYN_LCK2)) & 0xf0007fff))
++#define SET_CBR_RG_EN_DP_VT_MON(_VAL_) (REG32(ADR_CBR_DPLL_VCO_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0xfffffffe))
++#define SET_CBR_RG_DP_VT_TH_HI(_VAL_) (REG32(ADR_CBR_DPLL_VCO_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0xfffffff9))
++#define SET_CBR_RG_DP_VT_TH_LO(_VAL_) (REG32(ADR_CBR_DPLL_VCO_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0xffffffe7))
++#define SET_CBR_RG_DP_VT_MON_TMR(_VAL_) (REG32(ADR_CBR_DPLL_VCO_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0xffffc01f))
++#define SET_CBR_RG_DP_CK320BY2(_VAL_) (REG32(ADR_CBR_DPLL_VCO_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0xffffbfff))
++#define SET_CBR_RG_SX_DELCTRL(_VAL_) (REG32(ADR_CBR_DPLL_VCO_REGISTER)) = (((_VAL_) << 15) | ((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0xffe07fff))
++#define SET_CBR_RG_DP_OD_TEST(_VAL_) (REG32(ADR_CBR_DPLL_VCO_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0xffdfffff))
++#define SET_CBR_RG_DP_BBPLL_BP(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xfffffffe))
++#define SET_CBR_RG_DP_BBPLL_ICP(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xfffffff9))
++#define SET_CBR_RG_DP_BBPLL_IDUAL(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xffffffe7))
++#define SET_CBR_RG_DP_BBPLL_OD_TEST(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xfffffe1f))
++#define SET_CBR_RG_DP_BBPLL_PD(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xfffffdff))
++#define SET_CBR_RG_DP_BBPLL_TESTSEL(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xffffe3ff))
++#define SET_CBR_RG_DP_BBPLL_PFD_DLY(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 13) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xffff9fff))
++#define SET_CBR_RG_DP_RP(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 15) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xfffc7fff))
++#define SET_CBR_RG_DP_RHP(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xfff3ffff))
++#define SET_CBR_RG_DP_DR3(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xff8fffff))
++#define SET_CBR_RG_DP_DCP(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 23) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xf87fffff))
++#define SET_CBR_RG_DP_DCS(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 27) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x87ffffff))
++#define SET_CBR_RG_DP_FBDIV(_VAL_) (REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) & 0xfffff000))
++#define SET_CBR_RG_DP_FODIV(_VAL_) (REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) & 0xffc00fff))
++#define SET_CBR_RG_DP_REFDIV(_VAL_) (REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) = (((_VAL_) << 22) | ((REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) & 0x003fffff))
++#define SET_CBR_RG_IDACAI_PGAG15(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) & 0xffffffc0))
++#define SET_CBR_RG_IDACAQ_PGAG15(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) & 0xfffff03f))
++#define SET_CBR_RG_IDACAI_PGAG14(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) & 0xfffc0fff))
++#define SET_CBR_RG_IDACAQ_PGAG14(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) & 0xff03ffff))
++#define SET_CBR_RG_IDACAI_PGAG13(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) & 0xffffffc0))
++#define SET_CBR_RG_IDACAQ_PGAG13(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) & 0xfffff03f))
++#define SET_CBR_RG_IDACAI_PGAG12(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) & 0xfffc0fff))
++#define SET_CBR_RG_IDACAQ_PGAG12(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) & 0xff03ffff))
++#define SET_CBR_RG_IDACAI_PGAG11(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) & 0xffffffc0))
++#define SET_CBR_RG_IDACAQ_PGAG11(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) & 0xfffff03f))
++#define SET_CBR_RG_IDACAI_PGAG10(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) & 0xfffc0fff))
++#define SET_CBR_RG_IDACAQ_PGAG10(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) & 0xff03ffff))
++#define SET_CBR_RG_IDACAI_PGAG9(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) & 0xffffffc0))
++#define SET_CBR_RG_IDACAQ_PGAG9(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) & 0xfffff03f))
++#define SET_CBR_RG_IDACAI_PGAG8(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) & 0xfffc0fff))
++#define SET_CBR_RG_IDACAQ_PGAG8(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) & 0xff03ffff))
++#define SET_CBR_RG_IDACAI_PGAG7(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) & 0xffffffc0))
++#define SET_CBR_RG_IDACAQ_PGAG7(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) & 0xfffff03f))
++#define SET_CBR_RG_IDACAI_PGAG6(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) & 0xfffc0fff))
++#define SET_CBR_RG_IDACAQ_PGAG6(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) & 0xff03ffff))
++#define SET_CBR_RG_IDACAI_PGAG5(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) & 0xffffffc0))
++#define SET_CBR_RG_IDACAQ_PGAG5(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) & 0xfffff03f))
++#define SET_CBR_RG_IDACAI_PGAG4(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) & 0xfffc0fff))
++#define SET_CBR_RG_IDACAQ_PGAG4(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) & 0xff03ffff))
++#define SET_CBR_RG_IDACAI_PGAG3(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) & 0xffffffc0))
++#define SET_CBR_RG_IDACAQ_PGAG3(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) & 0xfffff03f))
++#define SET_CBR_RG_IDACAI_PGAG2(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) & 0xfffc0fff))
++#define SET_CBR_RG_IDACAQ_PGAG2(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) & 0xff03ffff))
++#define SET_CBR_RG_IDACAI_PGAG1(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) & 0xffffffc0))
++#define SET_CBR_RG_IDACAQ_PGAG1(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) & 0xfffff03f))
++#define SET_CBR_RG_IDACAI_PGAG0(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) & 0xfffc0fff))
++#define SET_CBR_RG_IDACAQ_PGAG0(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) & 0xff03ffff))
++#define SET_CBR_RG_EN_RCAL(_VAL_) (REG32(ADR_CBR_RCAL_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RCAL_REGISTER)) & 0xfffffffe))
++#define SET_CBR_RG_RCAL_SPD(_VAL_) (REG32(ADR_CBR_RCAL_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_RCAL_REGISTER)) & 0xfffffffd))
++#define SET_CBR_RG_RCAL_TMR(_VAL_) (REG32(ADR_CBR_RCAL_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_RCAL_REGISTER)) & 0xfffffe03))
++#define SET_CBR_RG_RCAL_CODE_CWR(_VAL_) (REG32(ADR_CBR_RCAL_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_RCAL_REGISTER)) & 0xfffffdff))
++#define SET_CBR_RG_RCAL_CODE_CWD(_VAL_) (REG32(ADR_CBR_RCAL_REGISTER)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_RCAL_REGISTER)) & 0xffff83ff))
++#define SET_CBR_RG_SX_SUB_SEL_CWR(_VAL_) (REG32(ADR_CBR_MANUAL_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_MANUAL_REGISTER)) & 0xfffffffe))
++#define SET_CBR_RG_SX_SUB_SEL_CWD(_VAL_) (REG32(ADR_CBR_MANUAL_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_MANUAL_REGISTER)) & 0xffffff01))
++#define SET_CBR_RG_DP_BBPLL_BS_CWR(_VAL_) (REG32(ADR_CBR_MANUAL_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_MANUAL_REGISTER)) & 0xfffffeff))
++#define SET_CBR_RG_DP_BBPLL_BS_CWD(_VAL_) (REG32(ADR_CBR_MANUAL_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_MANUAL_REGISTER)) & 0xffff81ff))
++#define SET_CBR_RCAL_RDY(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0xfffffffe))
++#define SET_CBR_DA_LCK_RDY(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0xfffffffd))
++#define SET_CBR_VT_MON_RDY(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0xfffffffb))
++#define SET_CBR_DP_VT_MON_RDY(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0xfffffff7))
++#define SET_CBR_CH_RDY(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 4) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0xffffffef))
++#define SET_CBR_DA_R_CODE_LUT(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0xfffff83f))
++#define SET_CBR_AD_SX_VT_MON_Q(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0xffffe7ff))
++#define SET_CBR_AD_DP_VT_MON_Q(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 13) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0xffff9fff))
++#define SET_CBR_DA_R_CAL_CODE(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_2)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_2)) & 0xffffffe0))
++#define SET_CBR_DA_SX_SUB_SEL(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_2)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_2)) & 0xfffff01f))
++#define SET_CBR_DA_DP_BBPLL_BS(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_2)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_2)) & 0xfffc0fff))
++#define SET_CBR_TX_EN(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_0)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0xfffffffe))
++#define SET_CBR_TX_CNT_RST(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_0)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0xfffffffd))
++#define SET_CBR_IFS_TIME(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_0)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0xffffff03))
++#define SET_CBR_LENGTH_TARGET(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_0)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0xfff000ff))
++#define SET_CBR_TX_CNT_TARGET(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_0)) = (((_VAL_) << 24) | ((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0x00ffffff))
++#define SET_CBR_TC_CNT_TARGET(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_1)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RG_PKT_GEN_1)) & 0xff000000))
++#define SET_CBR_PLCP_PSDU_DATA_MEM(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_2)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0xffffff00))
++#define SET_CBR_PLCP_PSDU_PREAMBLE_SHORT(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_2)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0xfffffeff))
++#define SET_CBR_PLCP_BYTE_LENGTH(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_2)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0xffe001ff))
++#define SET_CBR_PLCP_PSDU_RATE(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_2)) = (((_VAL_) << 21) | ((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0xff9fffff))
++#define SET_CBR_TAIL_TIME(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_2)) = (((_VAL_) << 23) | ((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0xe07fffff))
++#define SET_CBR_RG_O_PAD_PD(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xfffffffe))
++#define SET_CBR_RG_I_PAD_PD(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xfffffffd))
++#define SET_CBR_SEL_ADCKP_INV(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xfffffffb))
++#define SET_CBR_RG_PAD_DS(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xfffffff7))
++#define SET_CBR_SEL_ADCKP_MUX(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 4) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xffffffef))
++#define SET_CBR_RG_PAD_DS_CLK(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xffffffdf))
++#define SET_CBR_INTP_SEL(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xfffffdff))
++#define SET_CBR_IQ_SWP(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xfffffbff))
++#define SET_CBR_RG_EN_EXT_DA(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xfffff7ff))
++#define SET_CBR_RG_DIS_DA_OFFSET(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xffffefff))
++#define SET_CBR_DBG_SEL(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xfff0ffff))
++#define SET_CBR_DBG_EN(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xffefffff))
++#define SET_CBR_RG_PKT_GEN_TX_CNT(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_TXCNT)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RG_PKT_GEN_TXCNT)) & 0x00000000))
++#define SET_CBR_TP_SEL(_VAL_) (REG32(ADR_CBR_PATTERN_GEN)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_PATTERN_GEN)) & 0xffffffe0))
++#define SET_CBR_IDEAL_IQ_EN(_VAL_) (REG32(ADR_CBR_PATTERN_GEN)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_PATTERN_GEN)) & 0xffffffdf))
++#define SET_CBR_DATA_OUT_SEL(_VAL_) (REG32(ADR_CBR_PATTERN_GEN)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_PATTERN_GEN)) & 0xfffffe3f))
++#define SET_CBR_TWO_TONE_EN(_VAL_) (REG32(ADR_CBR_PATTERN_GEN)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_PATTERN_GEN)) & 0xfffffdff))
++#define SET_CBR_FREQ_SEL(_VAL_) (REG32(ADR_CBR_PATTERN_GEN)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_PATTERN_GEN)) & 0xff00ffff))
++#define SET_CBR_IQ_SCALE(_VAL_) (REG32(ADR_CBR_PATTERN_GEN)) = (((_VAL_) << 24) | ((REG32(ADR_CBR_PATTERN_GEN)) & 0x00ffffff))
++#define SET_CPU_QUE_POP(_VAL_) (REG32(ADR_MB_CPU_INT)) = (((_VAL_) << 0) | ((REG32(ADR_MB_CPU_INT)) & 0xfffffffe))
++#define SET_CPU_INT(_VAL_) (REG32(ADR_MB_CPU_INT)) = (((_VAL_) << 2) | ((REG32(ADR_MB_CPU_INT)) & 0xfffffffb))
++#define SET_CPU_ID_TB0(_VAL_) (REG32(ADR_CPU_ID_TB0)) = (((_VAL_) << 0) | ((REG32(ADR_CPU_ID_TB0)) & 0x00000000))
++#define SET_CPU_ID_TB1(_VAL_) (REG32(ADR_CPU_ID_TB1)) = (((_VAL_) << 0) | ((REG32(ADR_CPU_ID_TB1)) & 0x00000000))
++#define SET_HW_PKTID(_VAL_) (REG32(ADR_CH0_TRIG_1)) = (((_VAL_) << 0) | ((REG32(ADR_CH0_TRIG_1)) & 0xfffff800))
++#define SET_CH0_INT_ADDR(_VAL_) (REG32(ADR_CH0_TRIG_0)) = (((_VAL_) << 0) | ((REG32(ADR_CH0_TRIG_0)) & 0x00000000))
++#define SET_PRI_HW_PKTID(_VAL_) (REG32(ADR_CH0_PRI_TRIG)) = (((_VAL_) << 0) | ((REG32(ADR_CH0_PRI_TRIG)) & 0xfffff800))
++#define SET_CH0_FULL(_VAL_) (REG32(ADR_MCU_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MCU_STATUS)) & 0xfffffffe))
++#define SET_FF0_EMPTY(_VAL_) (REG32(ADR_MCU_STATUS)) = (((_VAL_) << 1) | ((REG32(ADR_MCU_STATUS)) & 0xfffffffd))
++#define SET_RLS_BUSY(_VAL_) (REG32(ADR_MCU_STATUS)) = (((_VAL_) << 9) | ((REG32(ADR_MCU_STATUS)) & 0xfffffdff))
++#define SET_RLS_COUNT_CLR(_VAL_) (REG32(ADR_MCU_STATUS)) = (((_VAL_) << 10) | ((REG32(ADR_MCU_STATUS)) & 0xfffffbff))
++#define SET_RTN_COUNT_CLR(_VAL_) (REG32(ADR_MCU_STATUS)) = (((_VAL_) << 11) | ((REG32(ADR_MCU_STATUS)) & 0xfffff7ff))
++#define SET_RLS_COUNT(_VAL_) (REG32(ADR_MCU_STATUS)) = (((_VAL_) << 16) | ((REG32(ADR_MCU_STATUS)) & 0xff00ffff))
++#define SET_RTN_COUNT(_VAL_) (REG32(ADR_MCU_STATUS)) = (((_VAL_) << 24) | ((REG32(ADR_MCU_STATUS)) & 0x00ffffff))
++#define SET_FF0_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT1)) = (((_VAL_) << 0) | ((REG32(ADR_RD_IN_FFCNT1)) & 0xffffffe0))
++#define SET_FF1_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT1)) = (((_VAL_) << 5) | ((REG32(ADR_RD_IN_FFCNT1)) & 0xfffffe1f))
++#define SET_FF3_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT1)) = (((_VAL_) << 11) | ((REG32(ADR_RD_IN_FFCNT1)) & 0xffffc7ff))
++#define SET_FF5_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT1)) = (((_VAL_) << 17) | ((REG32(ADR_RD_IN_FFCNT1)) & 0xfff1ffff))
++#define SET_FF6_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT1)) = (((_VAL_) << 20) | ((REG32(ADR_RD_IN_FFCNT1)) & 0xff8fffff))
++#define SET_FF7_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT1)) = (((_VAL_) << 23) | ((REG32(ADR_RD_IN_FFCNT1)) & 0xfc7fffff))
++#define SET_FF8_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT1)) = (((_VAL_) << 26) | ((REG32(ADR_RD_IN_FFCNT1)) & 0xe3ffffff))
++#define SET_FF9_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT1)) = (((_VAL_) << 29) | ((REG32(ADR_RD_IN_FFCNT1)) & 0x1fffffff))
++#define SET_FF10_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT2)) = (((_VAL_) << 0) | ((REG32(ADR_RD_IN_FFCNT2)) & 0xfffffff8))
++#define SET_FF11_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT2)) = (((_VAL_) << 3) | ((REG32(ADR_RD_IN_FFCNT2)) & 0xffffffc7))
++#define SET_FF12_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT2)) = (((_VAL_) << 6) | ((REG32(ADR_RD_IN_FFCNT2)) & 0xfffffe3f))
++#define SET_FF13_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT2)) = (((_VAL_) << 9) | ((REG32(ADR_RD_IN_FFCNT2)) & 0xfffff9ff))
++#define SET_FF14_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT2)) = (((_VAL_) << 11) | ((REG32(ADR_RD_IN_FFCNT2)) & 0xffffe7ff))
++#define SET_FF15_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT2)) = (((_VAL_) << 13) | ((REG32(ADR_RD_IN_FFCNT2)) & 0xffff9fff))
++#define SET_FF4_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT2)) = (((_VAL_) << 15) | ((REG32(ADR_RD_IN_FFCNT2)) & 0xfff07fff))
++#define SET_FF2_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT2)) = (((_VAL_) << 20) | ((REG32(ADR_RD_IN_FFCNT2)) & 0xff8fffff))
++#define SET_CH1_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 1) | ((REG32(ADR_RD_FFIN_FULL)) & 0xfffffffd))
++#define SET_CH2_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 2) | ((REG32(ADR_RD_FFIN_FULL)) & 0xfffffffb))
++#define SET_CH3_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 3) | ((REG32(ADR_RD_FFIN_FULL)) & 0xfffffff7))
++#define SET_CH4_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 4) | ((REG32(ADR_RD_FFIN_FULL)) & 0xffffffef))
++#define SET_CH5_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 5) | ((REG32(ADR_RD_FFIN_FULL)) & 0xffffffdf))
++#define SET_CH6_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 6) | ((REG32(ADR_RD_FFIN_FULL)) & 0xffffffbf))
++#define SET_CH7_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 7) | ((REG32(ADR_RD_FFIN_FULL)) & 0xffffff7f))
++#define SET_CH8_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 8) | ((REG32(ADR_RD_FFIN_FULL)) & 0xfffffeff))
++#define SET_CH9_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 9) | ((REG32(ADR_RD_FFIN_FULL)) & 0xfffffdff))
++#define SET_CH10_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 10) | ((REG32(ADR_RD_FFIN_FULL)) & 0xfffffbff))
++#define SET_CH11_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 11) | ((REG32(ADR_RD_FFIN_FULL)) & 0xfffff7ff))
++#define SET_CH12_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 12) | ((REG32(ADR_RD_FFIN_FULL)) & 0xffffefff))
++#define SET_CH13_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 13) | ((REG32(ADR_RD_FFIN_FULL)) & 0xffffdfff))
++#define SET_CH14_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 14) | ((REG32(ADR_RD_FFIN_FULL)) & 0xffffbfff))
++#define SET_CH15_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 15) | ((REG32(ADR_RD_FFIN_FULL)) & 0xffff7fff))
++#define SET_HALT_CH0(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 0) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xfffffffe))
++#define SET_HALT_CH1(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 1) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xfffffffd))
++#define SET_HALT_CH2(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 2) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xfffffffb))
++#define SET_HALT_CH3(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 3) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xfffffff7))
++#define SET_HALT_CH4(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 4) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffffffef))
++#define SET_HALT_CH5(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 5) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffffffdf))
++#define SET_HALT_CH6(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 6) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffffffbf))
++#define SET_HALT_CH7(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 7) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffffff7f))
++#define SET_HALT_CH8(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 8) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xfffffeff))
++#define SET_HALT_CH9(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 9) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xfffffdff))
++#define SET_HALT_CH10(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 10) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xfffffbff))
++#define SET_HALT_CH11(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 11) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xfffff7ff))
++#define SET_HALT_CH12(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 12) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffffefff))
++#define SET_HALT_CH13(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 13) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffffdfff))
++#define SET_HALT_CH14(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 14) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffffbfff))
++#define SET_HALT_CH15(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 15) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffff7fff))
++#define SET_STOP_MBOX(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 16) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xfffeffff))
++#define SET_MB_ERR_AUTO_HALT_EN(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 20) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffefffff))
++#define SET_MB_EXCEPT_CLR(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 21) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffdfffff))
++#define SET_MB_EXCEPT_CASE(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 24) | ((REG32(ADR_MBOX_HALT_CFG)) & 0x00ffffff))
++#define SET_MB_DBG_TIME_STEP(_VAL_) (REG32(ADR_MB_DBG_CFG1)) = (((_VAL_) << 0) | ((REG32(ADR_MB_DBG_CFG1)) & 0xffff0000))
++#define SET_DBG_TYPE(_VAL_) (REG32(ADR_MB_DBG_CFG1)) = (((_VAL_) << 16) | ((REG32(ADR_MB_DBG_CFG1)) & 0xfffcffff))
++#define SET_MB_DBG_CLR(_VAL_) (REG32(ADR_MB_DBG_CFG1)) = (((_VAL_) << 18) | ((REG32(ADR_MB_DBG_CFG1)) & 0xfffbffff))
++#define SET_DBG_ALC_LOG_EN(_VAL_) (REG32(ADR_MB_DBG_CFG1)) = (((_VAL_) << 19) | ((REG32(ADR_MB_DBG_CFG1)) & 0xfff7ffff))
++#define SET_MB_DBG_COUNTER_EN(_VAL_) (REG32(ADR_MB_DBG_CFG1)) = (((_VAL_) << 24) | ((REG32(ADR_MB_DBG_CFG1)) & 0xfeffffff))
++#define SET_MB_DBG_EN(_VAL_) (REG32(ADR_MB_DBG_CFG1)) = (((_VAL_) << 31) | ((REG32(ADR_MB_DBG_CFG1)) & 0x7fffffff))
++#define SET_MB_DBG_RECORD_CNT(_VAL_) (REG32(ADR_MB_DBG_CFG2)) = (((_VAL_) << 0) | ((REG32(ADR_MB_DBG_CFG2)) & 0xffff0000))
++#define SET_MB_DBG_LENGTH(_VAL_) (REG32(ADR_MB_DBG_CFG2)) = (((_VAL_) << 16) | ((REG32(ADR_MB_DBG_CFG2)) & 0x0000ffff))
++#define SET_MB_DBG_CFG_ADDR(_VAL_) (REG32(ADR_MB_DBG_CFG3)) = (((_VAL_) << 0) | ((REG32(ADR_MB_DBG_CFG3)) & 0x00000000))
++#define SET_DBG_HWID0_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 0) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffffffe))
++#define SET_DBG_HWID1_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 1) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffffffd))
++#define SET_DBG_HWID2_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 2) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffffffb))
++#define SET_DBG_HWID3_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 3) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffffff7))
++#define SET_DBG_HWID4_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 4) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffffffef))
++#define SET_DBG_HWID5_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 5) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffffffdf))
++#define SET_DBG_HWID6_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 6) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffffffbf))
++#define SET_DBG_HWID7_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 7) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffffff7f))
++#define SET_DBG_HWID8_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 8) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffffeff))
++#define SET_DBG_HWID9_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 9) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffffdff))
++#define SET_DBG_HWID10_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 10) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffffbff))
++#define SET_DBG_HWID11_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 11) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffff7ff))
++#define SET_DBG_HWID12_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 12) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffffefff))
++#define SET_DBG_HWID13_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 13) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffffdfff))
++#define SET_DBG_HWID14_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 14) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffffbfff))
++#define SET_DBG_HWID15_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 15) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffff7fff))
++#define SET_DBG_HWID0_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 16) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffeffff))
++#define SET_DBG_HWID1_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 17) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffdffff))
++#define SET_DBG_HWID2_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 18) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffbffff))
++#define SET_DBG_HWID3_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 19) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfff7ffff))
++#define SET_DBG_HWID4_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 20) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffefffff))
++#define SET_DBG_HWID5_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 21) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffdfffff))
++#define SET_DBG_HWID6_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 22) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffbfffff))
++#define SET_DBG_HWID7_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 23) | ((REG32(ADR_MB_DBG_CFG4)) & 0xff7fffff))
++#define SET_DBG_HWID8_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 24) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfeffffff))
++#define SET_DBG_HWID9_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 25) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfdffffff))
++#define SET_DBG_HWID10_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 26) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfbffffff))
++#define SET_DBG_HWID11_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 27) | ((REG32(ADR_MB_DBG_CFG4)) & 0xf7ffffff))
++#define SET_DBG_HWID12_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 28) | ((REG32(ADR_MB_DBG_CFG4)) & 0xefffffff))
++#define SET_DBG_HWID13_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 29) | ((REG32(ADR_MB_DBG_CFG4)) & 0xdfffffff))
++#define SET_DBG_HWID14_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 30) | ((REG32(ADR_MB_DBG_CFG4)) & 0xbfffffff))
++#define SET_DBG_HWID15_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 31) | ((REG32(ADR_MB_DBG_CFG4)) & 0x7fffffff))
++#define SET_MB_OUT_QUEUE_EN(_VAL_) (REG32(ADR_MB_OUT_QUEUE_CFG)) = (((_VAL_) << 1) | ((REG32(ADR_MB_OUT_QUEUE_CFG)) & 0xfffffffd))
++#define SET_CH0_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 0) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xfffffffe))
++#define SET_CH1_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 1) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xfffffffd))
++#define SET_CH2_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 2) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xfffffffb))
++#define SET_CH3_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 3) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xfffffff7))
++#define SET_CH4_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 4) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xffffffef))
++#define SET_CH5_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 5) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xffffffdf))
++#define SET_CH6_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 6) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xffffffbf))
++#define SET_CH7_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 7) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xffffff7f))
++#define SET_CH8_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 8) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xfffffeff))
++#define SET_CH9_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 9) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xfffffdff))
++#define SET_CH10_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 10) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xfffffbff))
++#define SET_CH11_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 11) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xfffff7ff))
++#define SET_CH12_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 12) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xffffefff))
++#define SET_CH13_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 13) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xffffdfff))
++#define SET_CH14_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 14) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xffffbfff))
++#define SET_CH15_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 15) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xffff7fff))
++#define SET_FFO0_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT1)) = (((_VAL_) << 0) | ((REG32(ADR_RD_FFOUT_CNT1)) & 0xffffffe0))
++#define SET_FFO1_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT1)) = (((_VAL_) << 5) | ((REG32(ADR_RD_FFOUT_CNT1)) & 0xfffffc1f))
++#define SET_FFO2_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT1)) = (((_VAL_) << 10) | ((REG32(ADR_RD_FFOUT_CNT1)) & 0xfffff3ff))
++#define SET_FFO3_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT1)) = (((_VAL_) << 15) | ((REG32(ADR_RD_FFOUT_CNT1)) & 0xfff07fff))
++#define SET_FFO4_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT1)) = (((_VAL_) << 20) | ((REG32(ADR_RD_FFOUT_CNT1)) & 0xffcfffff))
++#define SET_FFO5_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT1)) = (((_VAL_) << 25) | ((REG32(ADR_RD_FFOUT_CNT1)) & 0xf1ffffff))
++#define SET_FFO6_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT2)) = (((_VAL_) << 0) | ((REG32(ADR_RD_FFOUT_CNT2)) & 0xfffffff0))
++#define SET_FFO7_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT2)) = (((_VAL_) << 5) | ((REG32(ADR_RD_FFOUT_CNT2)) & 0xfffffc1f))
++#define SET_FFO8_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT2)) = (((_VAL_) << 10) | ((REG32(ADR_RD_FFOUT_CNT2)) & 0xffff83ff))
++#define SET_FFO9_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT2)) = (((_VAL_) << 15) | ((REG32(ADR_RD_FFOUT_CNT2)) & 0xfff07fff))
++#define SET_FFO10_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT2)) = (((_VAL_) << 20) | ((REG32(ADR_RD_FFOUT_CNT2)) & 0xff0fffff))
++#define SET_FFO11_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT2)) = (((_VAL_) << 25) | ((REG32(ADR_RD_FFOUT_CNT2)) & 0xc1ffffff))
++#define SET_FFO12_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT3)) = (((_VAL_) << 0) | ((REG32(ADR_RD_FFOUT_CNT3)) & 0xfffffff8))
++#define SET_FFO13_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT3)) = (((_VAL_) << 5) | ((REG32(ADR_RD_FFOUT_CNT3)) & 0xffffff9f))
++#define SET_FFO14_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT3)) = (((_VAL_) << 10) | ((REG32(ADR_RD_FFOUT_CNT3)) & 0xfffff3ff))
++#define SET_FFO15_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT3)) = (((_VAL_) << 15) | ((REG32(ADR_RD_FFOUT_CNT3)) & 0xffe07fff))
++#define SET_CH0_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 0) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xfffffffe))
++#define SET_CH1_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 1) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xfffffffd))
++#define SET_CH2_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 2) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xfffffffb))
++#define SET_CH3_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 3) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xfffffff7))
++#define SET_CH4_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 4) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xffffffef))
++#define SET_CH5_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 5) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xffffffdf))
++#define SET_CH6_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 6) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xffffffbf))
++#define SET_CH7_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 7) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xffffff7f))
++#define SET_CH8_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 8) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xfffffeff))
++#define SET_CH9_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 9) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xfffffdff))
++#define SET_CH10_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 10) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xfffffbff))
++#define SET_CH11_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 11) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xfffff7ff))
++#define SET_CH12_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 12) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xffffefff))
++#define SET_CH13_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 13) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xffffdfff))
++#define SET_CH14_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 14) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xffffbfff))
++#define SET_CH15_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 15) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xffff7fff))
++#define SET_CH0_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 0) | ((REG32(ADR_MB_THRESHOLD6)) & 0xfffffffe))
++#define SET_CH1_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 1) | ((REG32(ADR_MB_THRESHOLD6)) & 0xfffffffd))
++#define SET_CH2_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 2) | ((REG32(ADR_MB_THRESHOLD6)) & 0xfffffffb))
++#define SET_CH3_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 3) | ((REG32(ADR_MB_THRESHOLD6)) & 0xfffffff7))
++#define SET_CH4_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 4) | ((REG32(ADR_MB_THRESHOLD6)) & 0xffffffef))
++#define SET_CH5_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 5) | ((REG32(ADR_MB_THRESHOLD6)) & 0xffffffdf))
++#define SET_CH6_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 6) | ((REG32(ADR_MB_THRESHOLD6)) & 0xffffffbf))
++#define SET_CH7_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 7) | ((REG32(ADR_MB_THRESHOLD6)) & 0xffffff7f))
++#define SET_CH8_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 8) | ((REG32(ADR_MB_THRESHOLD6)) & 0xfffffeff))
++#define SET_CH9_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 9) | ((REG32(ADR_MB_THRESHOLD6)) & 0xfffffdff))
++#define SET_CH10_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 10) | ((REG32(ADR_MB_THRESHOLD6)) & 0xfffffbff))
++#define SET_CH11_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 11) | ((REG32(ADR_MB_THRESHOLD6)) & 0xfffff7ff))
++#define SET_CH12_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 12) | ((REG32(ADR_MB_THRESHOLD6)) & 0xffffefff))
++#define SET_CH13_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 13) | ((REG32(ADR_MB_THRESHOLD6)) & 0xffffdfff))
++#define SET_CH14_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 14) | ((REG32(ADR_MB_THRESHOLD6)) & 0xffffbfff))
++#define SET_CH15_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 15) | ((REG32(ADR_MB_THRESHOLD6)) & 0xffff7fff))
++#define SET_MB_LOW_THOLD_EN(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 31) | ((REG32(ADR_MB_THRESHOLD6)) & 0x7fffffff))
++#define SET_CH0_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD7)) = (((_VAL_) << 0) | ((REG32(ADR_MB_THRESHOLD7)) & 0xffffffe0))
++#define SET_CH1_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD7)) = (((_VAL_) << 8) | ((REG32(ADR_MB_THRESHOLD7)) & 0xffffe0ff))
++#define SET_CH2_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD7)) = (((_VAL_) << 16) | ((REG32(ADR_MB_THRESHOLD7)) & 0xffe0ffff))
++#define SET_CH3_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD7)) = (((_VAL_) << 24) | ((REG32(ADR_MB_THRESHOLD7)) & 0xe0ffffff))
++#define SET_CH4_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD8)) = (((_VAL_) << 0) | ((REG32(ADR_MB_THRESHOLD8)) & 0xffffffe0))
++#define SET_CH5_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD8)) = (((_VAL_) << 8) | ((REG32(ADR_MB_THRESHOLD8)) & 0xffffe0ff))
++#define SET_CH6_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD8)) = (((_VAL_) << 16) | ((REG32(ADR_MB_THRESHOLD8)) & 0xffe0ffff))
++#define SET_CH7_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD8)) = (((_VAL_) << 24) | ((REG32(ADR_MB_THRESHOLD8)) & 0xe0ffffff))
++#define SET_CH8_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD9)) = (((_VAL_) << 0) | ((REG32(ADR_MB_THRESHOLD9)) & 0xffffffe0))
++#define SET_CH9_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD9)) = (((_VAL_) << 8) | ((REG32(ADR_MB_THRESHOLD9)) & 0xffffe0ff))
++#define SET_CH10_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD9)) = (((_VAL_) << 16) | ((REG32(ADR_MB_THRESHOLD9)) & 0xffe0ffff))
++#define SET_CH11_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD9)) = (((_VAL_) << 24) | ((REG32(ADR_MB_THRESHOLD9)) & 0xe0ffffff))
++#define SET_CH12_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD10)) = (((_VAL_) << 0) | ((REG32(ADR_MB_THRESHOLD10)) & 0xffffffe0))
++#define SET_CH13_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD10)) = (((_VAL_) << 8) | ((REG32(ADR_MB_THRESHOLD10)) & 0xffffe0ff))
++#define SET_CH14_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD10)) = (((_VAL_) << 16) | ((REG32(ADR_MB_THRESHOLD10)) & 0xffe0ffff))
++#define SET_CH15_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD10)) = (((_VAL_) << 24) | ((REG32(ADR_MB_THRESHOLD10)) & 0xe0ffffff))
++#define SET_TRASH_TIMEOUT_EN(_VAL_) (REG32(ADR_MB_TRASH_CFG)) = (((_VAL_) << 0) | ((REG32(ADR_MB_TRASH_CFG)) & 0xfffffffe))
++#define SET_TRASH_CAN_INT(_VAL_) (REG32(ADR_MB_TRASH_CFG)) = (((_VAL_) << 1) | ((REG32(ADR_MB_TRASH_CFG)) & 0xfffffffd))
++#define SET_TRASH_INT_ID(_VAL_) (REG32(ADR_MB_TRASH_CFG)) = (((_VAL_) << 4) | ((REG32(ADR_MB_TRASH_CFG)) & 0xfffff80f))
++#define SET_TRASH_TIMEOUT(_VAL_) (REG32(ADR_MB_TRASH_CFG)) = (((_VAL_) << 16) | ((REG32(ADR_MB_TRASH_CFG)) & 0xfc00ffff))
++#define SET_CH0_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 0) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xfffffffe))
++#define SET_CH1_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 1) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xfffffffd))
++#define SET_CH2_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 2) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xfffffffb))
++#define SET_CH3_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 3) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xfffffff7))
++#define SET_CH4_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 4) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xffffffef))
++#define SET_CH5_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 5) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xffffffdf))
++#define SET_CH6_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 6) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xffffffbf))
++#define SET_CH7_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 7) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xffffff7f))
++#define SET_CH8_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 8) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xfffffeff))
++#define SET_CH9_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 9) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xfffffdff))
++#define SET_CH10_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 10) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xfffffbff))
++#define SET_CH11_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 11) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xfffff7ff))
++#define SET_CH12_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 12) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xffffefff))
++#define SET_CH13_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 13) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xffffdfff))
++#define SET_CH14_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 14) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xffffbfff))
++#define SET_CPU_ID_TB2(_VAL_) (REG32(ADR_CPU_ID_TB2)) = (((_VAL_) << 0) | ((REG32(ADR_CPU_ID_TB2)) & 0x00000000))
++#define SET_CPU_ID_TB3(_VAL_) (REG32(ADR_CPU_ID_TB3)) = (((_VAL_) << 0) | ((REG32(ADR_CPU_ID_TB3)) & 0x00000000))
++#define SET_IQ_LOG_EN(_VAL_) (REG32(ADR_PHY_IQ_LOG_CFG0)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_IQ_LOG_CFG0)) & 0xfffffffe))
++#define SET_IQ_LOG_STOP_MODE(_VAL_) (REG32(ADR_PHY_IQ_LOG_CFG1)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_IQ_LOG_CFG1)) & 0xfffffffe))
++#define SET_GPIO_STOP_EN(_VAL_) (REG32(ADR_PHY_IQ_LOG_CFG1)) = (((_VAL_) << 4) | ((REG32(ADR_PHY_IQ_LOG_CFG1)) & 0xffffffef))
++#define SET_GPIO_STOP_POL(_VAL_) (REG32(ADR_PHY_IQ_LOG_CFG1)) = (((_VAL_) << 5) | ((REG32(ADR_PHY_IQ_LOG_CFG1)) & 0xffffffdf))
++#define SET_IQ_LOG_TIMER(_VAL_) (REG32(ADR_PHY_IQ_LOG_CFG1)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_IQ_LOG_CFG1)) & 0x0000ffff))
++#define SET_IQ_LOG_LEN(_VAL_) (REG32(ADR_PHY_IQ_LOG_LEN)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_IQ_LOG_LEN)) & 0xffff0000))
++#define SET_IQ_LOG_TAIL_ADR(_VAL_) (REG32(ADR_PHY_IQ_LOG_PTR)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_IQ_LOG_PTR)) & 0xffff0000))
++#define SET_ALC_LENG(_VAL_) (REG32(ADR_WR_ALC)) = (((_VAL_) << 0) | ((REG32(ADR_WR_ALC)) & 0xfffc0000))
++#define SET_CH0_DYN_PRI(_VAL_) (REG32(ADR_WR_ALC)) = (((_VAL_) << 20) | ((REG32(ADR_WR_ALC)) & 0xffcfffff))
++#define SET_MCU_PKTID(_VAL_) (REG32(ADR_GETID)) = (((_VAL_) << 0) | ((REG32(ADR_GETID)) & 0x00000000))
++#define SET_CH0_STA_PRI(_VAL_) (REG32(ADR_CH_STA_PRI)) = (((_VAL_) << 0) | ((REG32(ADR_CH_STA_PRI)) & 0xfffffffc))
++#define SET_CH1_STA_PRI(_VAL_) (REG32(ADR_CH_STA_PRI)) = (((_VAL_) << 4) | ((REG32(ADR_CH_STA_PRI)) & 0xffffffcf))
++#define SET_CH2_STA_PRI(_VAL_) (REG32(ADR_CH_STA_PRI)) = (((_VAL_) << 8) | ((REG32(ADR_CH_STA_PRI)) & 0xfffffcff))
++#define SET_CH3_STA_PRI(_VAL_) (REG32(ADR_CH_STA_PRI)) = (((_VAL_) << 12) | ((REG32(ADR_CH_STA_PRI)) & 0xffffcfff))
++#define SET_ID_TB0(_VAL_) (REG32(ADR_RD_ID0)) = (((_VAL_) << 0) | ((REG32(ADR_RD_ID0)) & 0x00000000))
++#define SET_ID_TB1(_VAL_) (REG32(ADR_RD_ID1)) = (((_VAL_) << 0) | ((REG32(ADR_RD_ID1)) & 0x00000000))
++#define SET_ID_MNG_HALT(_VAL_) (REG32(ADR_IMD_CFG)) = (((_VAL_) << 4) | ((REG32(ADR_IMD_CFG)) & 0xffffffef))
++#define SET_ID_MNG_ERR_HALT_EN(_VAL_) (REG32(ADR_IMD_CFG)) = (((_VAL_) << 5) | ((REG32(ADR_IMD_CFG)) & 0xffffffdf))
++#define SET_ID_EXCEPT_FLG_CLR(_VAL_) (REG32(ADR_IMD_CFG)) = (((_VAL_) << 6) | ((REG32(ADR_IMD_CFG)) & 0xffffffbf))
++#define SET_ID_EXCEPT_FLG(_VAL_) (REG32(ADR_IMD_CFG)) = (((_VAL_) << 7) | ((REG32(ADR_IMD_CFG)) & 0xffffff7f))
++#define SET_ID_FULL(_VAL_) (REG32(ADR_IMD_STA)) = (((_VAL_) << 0) | ((REG32(ADR_IMD_STA)) & 0xfffffffe))
++#define SET_ID_MNG_BUSY(_VAL_) (REG32(ADR_IMD_STA)) = (((_VAL_) << 1) | ((REG32(ADR_IMD_STA)) & 0xfffffffd))
++#define SET_REQ_LOCK(_VAL_) (REG32(ADR_IMD_STA)) = (((_VAL_) << 2) | ((REG32(ADR_IMD_STA)) & 0xfffffffb))
++#define SET_CH0_REQ_LOCK(_VAL_) (REG32(ADR_IMD_STA)) = (((_VAL_) << 4) | ((REG32(ADR_IMD_STA)) & 0xffffffef))
++#define SET_CH1_REQ_LOCK(_VAL_) (REG32(ADR_IMD_STA)) = (((_VAL_) << 5) | ((REG32(ADR_IMD_STA)) & 0xffffffdf))
++#define SET_CH2_REQ_LOCK(_VAL_) (REG32(ADR_IMD_STA)) = (((_VAL_) << 6) | ((REG32(ADR_IMD_STA)) & 0xffffffbf))
++#define SET_CH3_REQ_LOCK(_VAL_) (REG32(ADR_IMD_STA)) = (((_VAL_) << 7) | ((REG32(ADR_IMD_STA)) & 0xffffff7f))
++#define SET_REQ_LOCK_INT_EN(_VAL_) (REG32(ADR_IMD_STA)) = (((_VAL_) << 8) | ((REG32(ADR_IMD_STA)) & 0xfffffeff))
++#define SET_REQ_LOCK_INT(_VAL_) (REG32(ADR_IMD_STA)) = (((_VAL_) << 9) | ((REG32(ADR_IMD_STA)) & 0xfffffdff))
++#define SET_MCU_ALC_READY(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 0) | ((REG32(ADR_ALC_STA)) & 0xfffffffe))
++#define SET_ALC_FAIL(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 1) | ((REG32(ADR_ALC_STA)) & 0xfffffffd))
++#define SET_ALC_BUSY(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 2) | ((REG32(ADR_ALC_STA)) & 0xfffffffb))
++#define SET_CH0_NVLD(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 4) | ((REG32(ADR_ALC_STA)) & 0xffffffef))
++#define SET_CH1_NVLD(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 5) | ((REG32(ADR_ALC_STA)) & 0xffffffdf))
++#define SET_CH2_NVLD(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 6) | ((REG32(ADR_ALC_STA)) & 0xffffffbf))
++#define SET_CH3_NVLD(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 7) | ((REG32(ADR_ALC_STA)) & 0xffffff7f))
++#define SET_ALC_INT_ID(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 8) | ((REG32(ADR_ALC_STA)) & 0xffff80ff))
++#define SET_ALC_TIMEOUT(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 16) | ((REG32(ADR_ALC_STA)) & 0xfc00ffff))
++#define SET_ALC_TIMEOUT_INT_EN(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 30) | ((REG32(ADR_ALC_STA)) & 0xbfffffff))
++#define SET_ALC_TIMEOUT_INT(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 31) | ((REG32(ADR_ALC_STA)) & 0x7fffffff))
++#define SET_TX_ID_COUNT(_VAL_) (REG32(ADR_TRX_ID_COUNT)) = (((_VAL_) << 0) | ((REG32(ADR_TRX_ID_COUNT)) & 0xffffff00))
++#define SET_RX_ID_COUNT(_VAL_) (REG32(ADR_TRX_ID_COUNT)) = (((_VAL_) << 8) | ((REG32(ADR_TRX_ID_COUNT)) & 0xffff00ff))
++#define SET_TX_ID_THOLD(_VAL_) (REG32(ADR_TRX_ID_THRESHOLD)) = (((_VAL_) << 0) | ((REG32(ADR_TRX_ID_THRESHOLD)) & 0xffffff00))
++#define SET_RX_ID_THOLD(_VAL_) (REG32(ADR_TRX_ID_THRESHOLD)) = (((_VAL_) << 8) | ((REG32(ADR_TRX_ID_THRESHOLD)) & 0xffff00ff))
++#define SET_ID_THOLD_RX_INT(_VAL_) (REG32(ADR_TRX_ID_THRESHOLD)) = (((_VAL_) << 16) | ((REG32(ADR_TRX_ID_THRESHOLD)) & 0xfffeffff))
++#define SET_RX_INT_CH(_VAL_) (REG32(ADR_TRX_ID_THRESHOLD)) = (((_VAL_) << 17) | ((REG32(ADR_TRX_ID_THRESHOLD)) & 0xfff1ffff))
++#define SET_ID_THOLD_TX_INT(_VAL_) (REG32(ADR_TRX_ID_THRESHOLD)) = (((_VAL_) << 20) | ((REG32(ADR_TRX_ID_THRESHOLD)) & 0xffefffff))
++#define SET_TX_INT_CH(_VAL_) (REG32(ADR_TRX_ID_THRESHOLD)) = (((_VAL_) << 21) | ((REG32(ADR_TRX_ID_THRESHOLD)) & 0xff1fffff))
++#define SET_ID_THOLD_INT_EN(_VAL_) (REG32(ADR_TRX_ID_THRESHOLD)) = (((_VAL_) << 24) | ((REG32(ADR_TRX_ID_THRESHOLD)) & 0xfeffffff))
++#define SET_TX_ID_TB0(_VAL_) (REG32(ADR_TX_ID0)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID0)) & 0x00000000))
++#define SET_TX_ID_TB1(_VAL_) (REG32(ADR_TX_ID1)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID1)) & 0x00000000))
++#define SET_RX_ID_TB0(_VAL_) (REG32(ADR_RX_ID0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_ID0)) & 0x00000000))
++#define SET_RX_ID_TB1(_VAL_) (REG32(ADR_RX_ID1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_ID1)) & 0x00000000))
++#define SET_DOUBLE_RLS_INT_EN(_VAL_) (REG32(ADR_RTN_STA)) = (((_VAL_) << 0) | ((REG32(ADR_RTN_STA)) & 0xfffffffe))
++#define SET_ID_DOUBLE_RLS_INT(_VAL_) (REG32(ADR_RTN_STA)) = (((_VAL_) << 1) | ((REG32(ADR_RTN_STA)) & 0xfffffffd))
++#define SET_DOUBLE_RLS_ID(_VAL_) (REG32(ADR_RTN_STA)) = (((_VAL_) << 8) | ((REG32(ADR_RTN_STA)) & 0xffff80ff))
++#define SET_ID_LEN_THOLD_INT_EN(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD1)) = (((_VAL_) << 0) | ((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0xfffffffe))
++#define SET_ALL_ID_LEN_THOLD_INT(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD1)) = (((_VAL_) << 1) | ((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0xfffffffd))
++#define SET_TX_ID_LEN_THOLD_INT(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD1)) = (((_VAL_) << 2) | ((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0xfffffffb))
++#define SET_RX_ID_LEN_THOLD_INT(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD1)) = (((_VAL_) << 3) | ((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0xfffffff7))
++#define SET_ID_TX_LEN_THOLD(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD1)) = (((_VAL_) << 4) | ((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0xffffe00f))
++#define SET_ID_RX_LEN_THOLD(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD1)) = (((_VAL_) << 13) | ((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0xffc01fff))
++#define SET_ID_LEN_THOLD(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD1)) = (((_VAL_) << 22) | ((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x803fffff))
++#define SET_ALL_ID_ALC_LEN(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD2)) = (((_VAL_) << 0) | ((REG32(ADR_ID_LEN_THREADSHOLD2)) & 0xfffffe00))
++#define SET_TX_ID_ALC_LEN(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD2)) = (((_VAL_) << 9) | ((REG32(ADR_ID_LEN_THREADSHOLD2)) & 0xfffc01ff))
++#define SET_RX_ID_ALC_LEN(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD2)) = (((_VAL_) << 18) | ((REG32(ADR_ID_LEN_THREADSHOLD2)) & 0xf803ffff))
++#define SET_CH_ARB_EN(_VAL_) (REG32(ADR_CH_ARB_PRI)) = (((_VAL_) << 0) | ((REG32(ADR_CH_ARB_PRI)) & 0xfffffffe))
++#define SET_CH_PRI1(_VAL_) (REG32(ADR_CH_ARB_PRI)) = (((_VAL_) << 4) | ((REG32(ADR_CH_ARB_PRI)) & 0xffffffcf))
++#define SET_CH_PRI2(_VAL_) (REG32(ADR_CH_ARB_PRI)) = (((_VAL_) << 8) | ((REG32(ADR_CH_ARB_PRI)) & 0xfffffcff))
++#define SET_CH_PRI3(_VAL_) (REG32(ADR_CH_ARB_PRI)) = (((_VAL_) << 12) | ((REG32(ADR_CH_ARB_PRI)) & 0xffffcfff))
++#define SET_CH_PRI4(_VAL_) (REG32(ADR_CH_ARB_PRI)) = (((_VAL_) << 16) | ((REG32(ADR_CH_ARB_PRI)) & 0xfffcffff))
++#define SET_TX_ID_REMAIN(_VAL_) (REG32(ADR_TX_ID_REMAIN_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID_REMAIN_STATUS)) & 0xffffff80))
++#define SET_TX_PAGE_REMAIN(_VAL_) (REG32(ADR_TX_ID_REMAIN_STATUS)) = (((_VAL_) << 8) | ((REG32(ADR_TX_ID_REMAIN_STATUS)) & 0xfffe00ff))
++#define SET_ID_PAGE_MAX_SIZE(_VAL_) (REG32(ADR_ID_INFO_STA)) = (((_VAL_) << 0) | ((REG32(ADR_ID_INFO_STA)) & 0xfffffe00))
++#define SET_TX_PAGE_LIMIT(_VAL_) (REG32(ADR_TX_LIMIT_INTR)) = (((_VAL_) << 0) | ((REG32(ADR_TX_LIMIT_INTR)) & 0xfffffe00))
++#define SET_TX_COUNT_LIMIT(_VAL_) (REG32(ADR_TX_LIMIT_INTR)) = (((_VAL_) << 16) | ((REG32(ADR_TX_LIMIT_INTR)) & 0xff00ffff))
++#define SET_TX_LIMIT_INT(_VAL_) (REG32(ADR_TX_LIMIT_INTR)) = (((_VAL_) << 30) | ((REG32(ADR_TX_LIMIT_INTR)) & 0xbfffffff))
++#define SET_TX_LIMIT_INT_EN(_VAL_) (REG32(ADR_TX_LIMIT_INTR)) = (((_VAL_) << 31) | ((REG32(ADR_TX_LIMIT_INTR)) & 0x7fffffff))
++#define SET_TX_PAGE_USE_7_0(_VAL_) (REG32(ADR_TX_ID_ALL_INFO)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID_ALL_INFO)) & 0xffffff00))
++#define SET_TX_ID_USE_5_0(_VAL_) (REG32(ADR_TX_ID_ALL_INFO)) = (((_VAL_) << 8) | ((REG32(ADR_TX_ID_ALL_INFO)) & 0xffffc0ff))
++#define SET_EDCA0_FFO_CNT(_VAL_) (REG32(ADR_TX_ID_ALL_INFO)) = (((_VAL_) << 14) | ((REG32(ADR_TX_ID_ALL_INFO)) & 0xfffc3fff))
++#define SET_EDCA1_FFO_CNT_3_0(_VAL_) (REG32(ADR_TX_ID_ALL_INFO)) = (((_VAL_) << 18) | ((REG32(ADR_TX_ID_ALL_INFO)) & 0xffc3ffff))
++#define SET_EDCA2_FFO_CNT(_VAL_) (REG32(ADR_TX_ID_ALL_INFO)) = (((_VAL_) << 22) | ((REG32(ADR_TX_ID_ALL_INFO)) & 0xf83fffff))
++#define SET_EDCA3_FFO_CNT(_VAL_) (REG32(ADR_TX_ID_ALL_INFO)) = (((_VAL_) << 27) | ((REG32(ADR_TX_ID_ALL_INFO)) & 0x07ffffff))
++#define SET_ID_TB2(_VAL_) (REG32(ADR_RD_ID2)) = (((_VAL_) << 0) | ((REG32(ADR_RD_ID2)) & 0x00000000))
++#define SET_ID_TB3(_VAL_) (REG32(ADR_RD_ID3)) = (((_VAL_) << 0) | ((REG32(ADR_RD_ID3)) & 0x00000000))
++#define SET_TX_ID_TB2(_VAL_) (REG32(ADR_TX_ID2)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID2)) & 0x00000000))
++#define SET_TX_ID_TB3(_VAL_) (REG32(ADR_TX_ID3)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID3)) & 0x00000000))
++#define SET_RX_ID_TB2(_VAL_) (REG32(ADR_RX_ID2)) = (((_VAL_) << 0) | ((REG32(ADR_RX_ID2)) & 0x00000000))
++#define SET_RX_ID_TB3(_VAL_) (REG32(ADR_RX_ID3)) = (((_VAL_) << 0) | ((REG32(ADR_RX_ID3)) & 0x00000000))
++#define SET_TX_PAGE_USE2(_VAL_) (REG32(ADR_TX_ID_ALL_INFO2)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID_ALL_INFO2)) & 0xfffffe00))
++#define SET_TX_ID_USE2(_VAL_) (REG32(ADR_TX_ID_ALL_INFO2)) = (((_VAL_) << 9) | ((REG32(ADR_TX_ID_ALL_INFO2)) & 0xfffe01ff))
++#define SET_EDCA4_FFO_CNT(_VAL_) (REG32(ADR_TX_ID_ALL_INFO2)) = (((_VAL_) << 17) | ((REG32(ADR_TX_ID_ALL_INFO2)) & 0xffe1ffff))
++#define SET_TX_PAGE_USE3(_VAL_) (REG32(ADR_TX_ID_ALL_INFO_A)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID_ALL_INFO_A)) & 0xfffffe00))
++#define SET_TX_ID_USE3(_VAL_) (REG32(ADR_TX_ID_ALL_INFO_A)) = (((_VAL_) << 9) | ((REG32(ADR_TX_ID_ALL_INFO_A)) & 0xfffe01ff))
++#define SET_EDCA1_FFO_CNT2(_VAL_) (REG32(ADR_TX_ID_ALL_INFO_A)) = (((_VAL_) << 21) | ((REG32(ADR_TX_ID_ALL_INFO_A)) & 0xfc1fffff))
++#define SET_EDCA4_FFO_CNT2(_VAL_) (REG32(ADR_TX_ID_ALL_INFO_A)) = (((_VAL_) << 26) | ((REG32(ADR_TX_ID_ALL_INFO_A)) & 0xc3ffffff))
++#define SET_TX_PAGE_USE4(_VAL_) (REG32(ADR_TX_ID_ALL_INFO_B)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID_ALL_INFO_B)) & 0xfffffe00))
++#define SET_TX_ID_USE4(_VAL_) (REG32(ADR_TX_ID_ALL_INFO_B)) = (((_VAL_) << 9) | ((REG32(ADR_TX_ID_ALL_INFO_B)) & 0xfffe01ff))
++#define SET_EDCA2_FFO_CNT2(_VAL_) (REG32(ADR_TX_ID_ALL_INFO_B)) = (((_VAL_) << 17) | ((REG32(ADR_TX_ID_ALL_INFO_B)) & 0xffc1ffff))
++#define SET_EDCA3_FFO_CNT2(_VAL_) (REG32(ADR_TX_ID_ALL_INFO_B)) = (((_VAL_) << 22) | ((REG32(ADR_TX_ID_ALL_INFO_B)) & 0xf83fffff))
++#define SET_TX_ID_IFO_LEN(_VAL_) (REG32(ADR_TX_ID_REMAIN_STATUS2)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID_REMAIN_STATUS2)) & 0xfffffe00))
++#define SET_RX_ID_IFO_LEN(_VAL_) (REG32(ADR_TX_ID_REMAIN_STATUS2)) = (((_VAL_) << 16) | ((REG32(ADR_TX_ID_REMAIN_STATUS2)) & 0xfe00ffff))
++#define SET_MAX_ALL_ALC_ID_CNT(_VAL_) (REG32(ADR_ALC_ID_INFO)) = (((_VAL_) << 0) | ((REG32(ADR_ALC_ID_INFO)) & 0xffffff00))
++#define SET_MAX_TX_ALC_ID_CNT(_VAL_) (REG32(ADR_ALC_ID_INFO)) = (((_VAL_) << 8) | ((REG32(ADR_ALC_ID_INFO)) & 0xffff00ff))
++#define SET_MAX_RX_ALC_ID_CNT(_VAL_) (REG32(ADR_ALC_ID_INFO)) = (((_VAL_) << 16) | ((REG32(ADR_ALC_ID_INFO)) & 0xff00ffff))
++#define SET_MAX_ALL_ID_ALC_LEN(_VAL_) (REG32(ADR_ALC_ID_INF1)) = (((_VAL_) << 0) | ((REG32(ADR_ALC_ID_INF1)) & 0xfffffe00))
++#define SET_MAX_TX_ID_ALC_LEN(_VAL_) (REG32(ADR_ALC_ID_INF1)) = (((_VAL_) << 9) | ((REG32(ADR_ALC_ID_INF1)) & 0xfffc01ff))
++#define SET_MAX_RX_ID_ALC_LEN(_VAL_) (REG32(ADR_ALC_ID_INF1)) = (((_VAL_) << 18) | ((REG32(ADR_ALC_ID_INF1)) & 0xf803ffff))
++#define SET_RG_PMDLBK(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_EN_0)) & 0xfffffffe))
++#define SET_RG_RDYACK_SEL(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 1) | ((REG32(ADR_PHY_EN_0)) & 0xfffffff9))
++#define SET_RG_ADEDGE_SEL(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 3) | ((REG32(ADR_PHY_EN_0)) & 0xfffffff7))
++#define SET_RG_SIGN_SWAP(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 4) | ((REG32(ADR_PHY_EN_0)) & 0xffffffef))
++#define SET_RG_IQ_SWAP(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 5) | ((REG32(ADR_PHY_EN_0)) & 0xffffffdf))
++#define SET_RG_Q_INV(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 6) | ((REG32(ADR_PHY_EN_0)) & 0xffffffbf))
++#define SET_RG_I_INV(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 7) | ((REG32(ADR_PHY_EN_0)) & 0xffffff7f))
++#define SET_RG_BYPASS_ACI(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_EN_0)) & 0xfffffeff))
++#define SET_RG_LBK_ANA_PATH(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 9) | ((REG32(ADR_PHY_EN_0)) & 0xfffffdff))
++#define SET_RG_SPECTRUM_LEAKY_FACTOR(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 10) | ((REG32(ADR_PHY_EN_0)) & 0xfffff3ff))
++#define SET_RG_SPECTRUM_BW(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 12) | ((REG32(ADR_PHY_EN_0)) & 0xffffcfff))
++#define SET_RG_SPECTRUM_FREQ_MANUAL(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 14) | ((REG32(ADR_PHY_EN_0)) & 0xffffbfff))
++#define SET_RG_SPECTRUM_EN(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 15) | ((REG32(ADR_PHY_EN_0)) & 0xffff7fff))
++#define SET_RG_TXPWRLVL_SET(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_EN_0)) & 0xff00ffff))
++#define SET_RG_TXPWRLVL_SEL(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_EN_0)) & 0xfeffffff))
++#define SET_RG_RF_BB_CLK_SEL(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_EN_0)) & 0x7fffffff))
++#define SET_RG_PHY_MD_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_EN_1)) & 0xfffffffe))
++#define SET_RG_PHYRX_MD_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 1) | ((REG32(ADR_PHY_EN_1)) & 0xfffffffd))
++#define SET_RG_PHYTX_MD_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 2) | ((REG32(ADR_PHY_EN_1)) & 0xfffffffb))
++#define SET_RG_PHY11GN_MD_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 3) | ((REG32(ADR_PHY_EN_1)) & 0xfffffff7))
++#define SET_RG_PHY11B_MD_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 4) | ((REG32(ADR_PHY_EN_1)) & 0xffffffef))
++#define SET_RG_PHYRXFIFO_MD_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 5) | ((REG32(ADR_PHY_EN_1)) & 0xffffffdf))
++#define SET_RG_PHYTXFIFO_MD_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 6) | ((REG32(ADR_PHY_EN_1)) & 0xffffffbf))
++#define SET_RG_PHY11BGN_MD_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_EN_1)) & 0xfffffeff))
++#define SET_RG_FORCE_11GN_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 12) | ((REG32(ADR_PHY_EN_1)) & 0xffffefff))
++#define SET_RG_FORCE_11B_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 13) | ((REG32(ADR_PHY_EN_1)) & 0xffffdfff))
++#define SET_RG_FFT_MEM_CLK_EN_RX(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 14) | ((REG32(ADR_PHY_EN_1)) & 0xffffbfff))
++#define SET_RG_FFT_MEM_CLK_EN_TX(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 15) | ((REG32(ADR_PHY_EN_1)) & 0xffff7fff))
++#define SET_RG_PHY_IQ_TRIG_SEL(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_EN_1)) & 0xfff0ffff))
++#define SET_RG_SPECTRUM_FREQ(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 20) | ((REG32(ADR_PHY_EN_1)) & 0xc00fffff))
++#define SET_SVN_VERSION(_VAL_) (REG32(ADR_SVN_VERSION_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SVN_VERSION_REG)) & 0x00000000))
++#define SET_RG_LENGTH(_VAL_) (REG32(ADR_PHY_PKT_GEN_0)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_PKT_GEN_0)) & 0xffff0000))
++#define SET_RG_PKT_MODE(_VAL_) (REG32(ADR_PHY_PKT_GEN_0)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_PKT_GEN_0)) & 0xfff8ffff))
++#define SET_RG_CH_BW(_VAL_) (REG32(ADR_PHY_PKT_GEN_0)) = (((_VAL_) << 19) | ((REG32(ADR_PHY_PKT_GEN_0)) & 0xffc7ffff))
++#define SET_RG_PRM(_VAL_) (REG32(ADR_PHY_PKT_GEN_0)) = (((_VAL_) << 22) | ((REG32(ADR_PHY_PKT_GEN_0)) & 0xffbfffff))
++#define SET_RG_SHORTGI(_VAL_) (REG32(ADR_PHY_PKT_GEN_0)) = (((_VAL_) << 23) | ((REG32(ADR_PHY_PKT_GEN_0)) & 0xff7fffff))
++#define SET_RG_RATE(_VAL_) (REG32(ADR_PHY_PKT_GEN_0)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_PKT_GEN_0)) & 0x80ffffff))
++#define SET_RG_L_LENGTH(_VAL_) (REG32(ADR_PHY_PKT_GEN_1)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_PKT_GEN_1)) & 0xfffff000))
++#define SET_RG_L_RATE(_VAL_) (REG32(ADR_PHY_PKT_GEN_1)) = (((_VAL_) << 12) | ((REG32(ADR_PHY_PKT_GEN_1)) & 0xffff8fff))
++#define SET_RG_SERVICE(_VAL_) (REG32(ADR_PHY_PKT_GEN_1)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_PKT_GEN_1)) & 0x0000ffff))
++#define SET_RG_SMOOTHING(_VAL_) (REG32(ADR_PHY_PKT_GEN_2)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_PKT_GEN_2)) & 0xfffffffe))
++#define SET_RG_NO_SOUND(_VAL_) (REG32(ADR_PHY_PKT_GEN_2)) = (((_VAL_) << 1) | ((REG32(ADR_PHY_PKT_GEN_2)) & 0xfffffffd))
++#define SET_RG_AGGREGATE(_VAL_) (REG32(ADR_PHY_PKT_GEN_2)) = (((_VAL_) << 2) | ((REG32(ADR_PHY_PKT_GEN_2)) & 0xfffffffb))
++#define SET_RG_STBC(_VAL_) (REG32(ADR_PHY_PKT_GEN_2)) = (((_VAL_) << 3) | ((REG32(ADR_PHY_PKT_GEN_2)) & 0xffffffe7))
++#define SET_RG_FEC(_VAL_) (REG32(ADR_PHY_PKT_GEN_2)) = (((_VAL_) << 5) | ((REG32(ADR_PHY_PKT_GEN_2)) & 0xffffffdf))
++#define SET_RG_N_ESS(_VAL_) (REG32(ADR_PHY_PKT_GEN_2)) = (((_VAL_) << 6) | ((REG32(ADR_PHY_PKT_GEN_2)) & 0xffffff3f))
++#define SET_RG_TXPWRLVL(_VAL_) (REG32(ADR_PHY_PKT_GEN_2)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_PKT_GEN_2)) & 0xffff00ff))
++#define SET_RG_TX_START(_VAL_) (REG32(ADR_PHY_PKT_GEN_3)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_PKT_GEN_3)) & 0xfffffffe))
++#define SET_RG_IFS_TIME(_VAL_) (REG32(ADR_PHY_PKT_GEN_3)) = (((_VAL_) << 2) | ((REG32(ADR_PHY_PKT_GEN_3)) & 0xffffff03))
++#define SET_RG_CONTINUOUS_DATA(_VAL_) (REG32(ADR_PHY_PKT_GEN_3)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_PKT_GEN_3)) & 0xfffffeff))
++#define SET_RG_DATA_SEL(_VAL_) (REG32(ADR_PHY_PKT_GEN_3)) = (((_VAL_) << 9) | ((REG32(ADR_PHY_PKT_GEN_3)) & 0xfffff9ff))
++#define SET_RG_TX_D(_VAL_) (REG32(ADR_PHY_PKT_GEN_3)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_PKT_GEN_3)) & 0xff00ffff))
++#define SET_RG_TX_CNT_TARGET(_VAL_) (REG32(ADR_PHY_PKT_GEN_4)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_PKT_GEN_4)) & 0x00000000))
++#define SET_RG_FFT_IFFT_MODE(_VAL_) (REG32(ADR_PHY_REG_00)) = (((_VAL_) << 6) | ((REG32(ADR_PHY_REG_00)) & 0xffffff3f))
++#define SET_RG_DAC_DBG_MODE(_VAL_) (REG32(ADR_PHY_REG_00)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_00)) & 0xfffffeff))
++#define SET_RG_DAC_SGN_SWAP(_VAL_) (REG32(ADR_PHY_REG_00)) = (((_VAL_) << 9) | ((REG32(ADR_PHY_REG_00)) & 0xfffffdff))
++#define SET_RG_TXD_SEL(_VAL_) (REG32(ADR_PHY_REG_00)) = (((_VAL_) << 10) | ((REG32(ADR_PHY_REG_00)) & 0xfffff3ff))
++#define SET_RG_UP8X(_VAL_) (REG32(ADR_PHY_REG_00)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_00)) & 0xff00ffff))
++#define SET_RG_IQ_DC_BYP(_VAL_) (REG32(ADR_PHY_REG_00)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_00)) & 0xfeffffff))
++#define SET_RG_IQ_DC_LEAKY_FACTOR(_VAL_) (REG32(ADR_PHY_REG_00)) = (((_VAL_) << 28) | ((REG32(ADR_PHY_REG_00)) & 0xcfffffff))
++#define SET_RG_DAC_DCEN(_VAL_) (REG32(ADR_PHY_REG_01)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_01)) & 0xfffffffe))
++#define SET_RG_DAC_DCQ(_VAL_) (REG32(ADR_PHY_REG_01)) = (((_VAL_) << 4) | ((REG32(ADR_PHY_REG_01)) & 0xffffc00f))
++#define SET_RG_DAC_DCI(_VAL_) (REG32(ADR_PHY_REG_01)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_01)) & 0xfc00ffff))
++#define SET_RG_PGA_REFDB_SAT(_VAL_) (REG32(ADR_PHY_REG_02_AGC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_02_AGC)) & 0xffffff80))
++#define SET_RG_PGA_REFDB_TOP(_VAL_) (REG32(ADR_PHY_REG_02_AGC)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_02_AGC)) & 0xffff80ff))
++#define SET_RG_PGA_REF_UND(_VAL_) (REG32(ADR_PHY_REG_02_AGC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_02_AGC)) & 0xfc00ffff))
++#define SET_RG_RF_REF_SAT(_VAL_) (REG32(ADR_PHY_REG_02_AGC)) = (((_VAL_) << 28) | ((REG32(ADR_PHY_REG_02_AGC)) & 0x0fffffff))
++#define SET_RG_PGAGC_SET(_VAL_) (REG32(ADR_PHY_REG_03_AGC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_03_AGC)) & 0xfffffff0))
++#define SET_RG_PGAGC_OW(_VAL_) (REG32(ADR_PHY_REG_03_AGC)) = (((_VAL_) << 4) | ((REG32(ADR_PHY_REG_03_AGC)) & 0xffffffef))
++#define SET_RG_RFGC_SET(_VAL_) (REG32(ADR_PHY_REG_03_AGC)) = (((_VAL_) << 5) | ((REG32(ADR_PHY_REG_03_AGC)) & 0xffffff9f))
++#define SET_RG_RFGC_OW(_VAL_) (REG32(ADR_PHY_REG_03_AGC)) = (((_VAL_) << 7) | ((REG32(ADR_PHY_REG_03_AGC)) & 0xffffff7f))
++#define SET_RG_WAIT_T_RXAGC(_VAL_) (REG32(ADR_PHY_REG_03_AGC)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_03_AGC)) & 0xffffc0ff))
++#define SET_RG_RXAGC_SET(_VAL_) (REG32(ADR_PHY_REG_03_AGC)) = (((_VAL_) << 14) | ((REG32(ADR_PHY_REG_03_AGC)) & 0xffffbfff))
++#define SET_RG_RXAGC_OW(_VAL_) (REG32(ADR_PHY_REG_03_AGC)) = (((_VAL_) << 15) | ((REG32(ADR_PHY_REG_03_AGC)) & 0xffff7fff))
++#define SET_RG_WAIT_T_FINAL(_VAL_) (REG32(ADR_PHY_REG_03_AGC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_03_AGC)) & 0xffc0ffff))
++#define SET_RG_WAIT_T(_VAL_) (REG32(ADR_PHY_REG_03_AGC)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_03_AGC)) & 0xc0ffffff))
++#define SET_RG_ULG_PGA_SAT_PGA_GAIN(_VAL_) (REG32(ADR_PHY_REG_04_AGC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_04_AGC)) & 0xfffffff0))
++#define SET_RG_LG_PGA_UND_PGA_GAIN(_VAL_) (REG32(ADR_PHY_REG_04_AGC)) = (((_VAL_) << 4) | ((REG32(ADR_PHY_REG_04_AGC)) & 0xffffff0f))
++#define SET_RG_LG_PGA_SAT_PGA_GAIN(_VAL_) (REG32(ADR_PHY_REG_04_AGC)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_04_AGC)) & 0xfffff0ff))
++#define SET_RG_LG_RF_SAT_PGA_GAIN(_VAL_) (REG32(ADR_PHY_REG_04_AGC)) = (((_VAL_) << 12) | ((REG32(ADR_PHY_REG_04_AGC)) & 0xffff0fff))
++#define SET_RG_MG_RF_SAT_PGANOREF_PGA_GAIN(_VAL_) (REG32(ADR_PHY_REG_04_AGC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_04_AGC)) & 0xfff0ffff))
++#define SET_RG_HG_PGA_SAT2_PGA_GAIN(_VAL_) (REG32(ADR_PHY_REG_04_AGC)) = (((_VAL_) << 20) | ((REG32(ADR_PHY_REG_04_AGC)) & 0xff0fffff))
++#define SET_RG_HG_PGA_SAT1_PGA_GAIN(_VAL_) (REG32(ADR_PHY_REG_04_AGC)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_04_AGC)) & 0xf0ffffff))
++#define SET_RG_HG_RF_SAT_PGA_GAIN(_VAL_) (REG32(ADR_PHY_REG_04_AGC)) = (((_VAL_) << 28) | ((REG32(ADR_PHY_REG_04_AGC)) & 0x0fffffff))
++#define SET_RG_MG_PGA_JB_TH(_VAL_) (REG32(ADR_PHY_REG_05_AGC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_05_AGC)) & 0xfffffff0))
++#define SET_RG_MA_PGA_LOW_TH_CNT_LMT(_VAL_) (REG32(ADR_PHY_REG_05_AGC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_05_AGC)) & 0xffe0ffff))
++#define SET_RG_WR_RFGC_INIT_SET(_VAL_) (REG32(ADR_PHY_REG_05_AGC)) = (((_VAL_) << 21) | ((REG32(ADR_PHY_REG_05_AGC)) & 0xff9fffff))
++#define SET_RG_WR_RFGC_INIT_EN(_VAL_) (REG32(ADR_PHY_REG_05_AGC)) = (((_VAL_) << 23) | ((REG32(ADR_PHY_REG_05_AGC)) & 0xff7fffff))
++#define SET_RG_MA_PGA_HIGH_TH_CNT_LMT(_VAL_) (REG32(ADR_PHY_REG_05_AGC)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_05_AGC)) & 0xe0ffffff))
++#define SET_RG_AGC_THRESHOLD(_VAL_) (REG32(ADR_PHY_REG_06_11B_DAGC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_06_11B_DAGC)) & 0xffffc000))
++#define SET_RG_ACI_POINT_CNT_LMT_11B(_VAL_) (REG32(ADR_PHY_REG_06_11B_DAGC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_06_11B_DAGC)) & 0xff80ffff))
++#define SET_RG_ACI_DAGC_LEAKY_FACTOR_11B(_VAL_) (REG32(ADR_PHY_REG_06_11B_DAGC)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_06_11B_DAGC)) & 0xfcffffff))
++#define SET_RG_WR_ACI_GAIN_INI_SEL_11B(_VAL_) (REG32(ADR_PHY_REG_07_11B_DAGC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_07_11B_DAGC)) & 0xffffff00))
++#define SET_RG_WR_ACI_GAIN_SEL_11B(_VAL_) (REG32(ADR_PHY_REG_07_11B_DAGC)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_07_11B_DAGC)) & 0xffff00ff))
++#define SET_RG_ACI_DAGC_SET_VALUE_11B(_VAL_) (REG32(ADR_PHY_REG_07_11B_DAGC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_07_11B_DAGC)) & 0xff80ffff))
++#define SET_RG_WR_ACI_GAIN_OW_11B(_VAL_) (REG32(ADR_PHY_REG_07_11B_DAGC)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_07_11B_DAGC)) & 0x7fffffff))
++#define SET_RG_ACI_POINT_CNT_LMT_11GN(_VAL_) (REG32(ADR_PHY_REG_08_11GN_DAGC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_08_11GN_DAGC)) & 0xffffff00))
++#define SET_RG_ACI_DAGC_LEAKY_FACTOR_11GN(_VAL_) (REG32(ADR_PHY_REG_08_11GN_DAGC)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_08_11GN_DAGC)) & 0xfffffcff))
++#define SET_RG_ACI_DAGC_DONE_CNT_LMT_11GN(_VAL_) (REG32(ADR_PHY_REG_08_11GN_DAGC)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_08_11GN_DAGC)) & 0x00ffffff))
++#define SET_RG_ACI_DAGC_SET_VALUE_11GN(_VAL_) (REG32(ADR_PHY_REG_09_11GN_DAGC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_09_11GN_DAGC)) & 0xffffff80))
++#define SET_RG_ACI_GAIN_INI_VAL_11GN(_VAL_) (REG32(ADR_PHY_REG_09_11GN_DAGC)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_09_11GN_DAGC)) & 0xffff00ff))
++#define SET_RG_ACI_GAIN_OW_VAL_11GN(_VAL_) (REG32(ADR_PHY_REG_09_11GN_DAGC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_09_11GN_DAGC)) & 0xff00ffff))
++#define SET_RG_ACI_GAIN_OW_11GN(_VAL_) (REG32(ADR_PHY_REG_09_11GN_DAGC)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_09_11GN_DAGC)) & 0x7fffffff))
++#define SET_RO_CCA_PWR_MA_11GN(_VAL_) (REG32(ADR_PHY_READ_REG_00_DIG_PWR)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_00_DIG_PWR)) & 0xffffff80))
++#define SET_RO_ED_STATE(_VAL_) (REG32(ADR_PHY_READ_REG_00_DIG_PWR)) = (((_VAL_) << 15) | ((REG32(ADR_PHY_READ_REG_00_DIG_PWR)) & 0xffff7fff))
++#define SET_RO_CCA_PWR_MA_11B(_VAL_) (REG32(ADR_PHY_READ_REG_00_DIG_PWR)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_READ_REG_00_DIG_PWR)) & 0xff80ffff))
++#define SET_RO_PGA_PWR_FF1(_VAL_) (REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) & 0xffffc000))
++#define SET_RO_RF_PWR_FF1(_VAL_) (REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) & 0xfff0ffff))
++#define SET_RO_PGAGC_FF1(_VAL_) (REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) & 0xf0ffffff))
++#define SET_RO_RFGC_FF1(_VAL_) (REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) = (((_VAL_) << 28) | ((REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) & 0xcfffffff))
++#define SET_RO_PGA_PWR_FF2(_VAL_) (REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) & 0xffffc000))
++#define SET_RO_RF_PWR_FF2(_VAL_) (REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) & 0xfff0ffff))
++#define SET_RO_PGAGC_FF2(_VAL_) (REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) & 0xf0ffffff))
++#define SET_RO_RFGC_FF2(_VAL_) (REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) = (((_VAL_) << 28) | ((REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) & 0xcfffffff))
++#define SET_RO_PGA_PWR_FF3(_VAL_) (REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) & 0xffffc000))
++#define SET_RO_RF_PWR_FF3(_VAL_) (REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) & 0xfff0ffff))
++#define SET_RO_PGAGC_FF3(_VAL_) (REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) & 0xf0ffffff))
++#define SET_RO_RFGC_FF3(_VAL_) (REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) = (((_VAL_) << 28) | ((REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) & 0xcfffffff))
++#define SET_RG_TX_DES_RATE(_VAL_) (REG32(ADR_PHY_REG_10_TX_DES)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_10_TX_DES)) & 0xffffffe0))
++#define SET_RG_TX_DES_MODE(_VAL_) (REG32(ADR_PHY_REG_10_TX_DES)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_10_TX_DES)) & 0xffffe0ff))
++#define SET_RG_TX_DES_LEN_LO(_VAL_) (REG32(ADR_PHY_REG_10_TX_DES)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_10_TX_DES)) & 0xffe0ffff))
++#define SET_RG_TX_DES_LEN_UP(_VAL_) (REG32(ADR_PHY_REG_10_TX_DES)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_10_TX_DES)) & 0xe0ffffff))
++#define SET_RG_TX_DES_SRVC_UP(_VAL_) (REG32(ADR_PHY_REG_11_TX_DES)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_11_TX_DES)) & 0xffffffe0))
++#define SET_RG_TX_DES_L_LEN_LO(_VAL_) (REG32(ADR_PHY_REG_11_TX_DES)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_11_TX_DES)) & 0xffffe0ff))
++#define SET_RG_TX_DES_L_LEN_UP(_VAL_) (REG32(ADR_PHY_REG_11_TX_DES)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_11_TX_DES)) & 0xffe0ffff))
++#define SET_RG_TX_DES_TYPE(_VAL_) (REG32(ADR_PHY_REG_11_TX_DES)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_11_TX_DES)) & 0xe0ffffff))
++#define SET_RG_TX_DES_L_LEN_UP_COMB(_VAL_) (REG32(ADR_PHY_REG_12_TX_DES)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_12_TX_DES)) & 0xfffffffe))
++#define SET_RG_TX_DES_TYPE_COMB(_VAL_) (REG32(ADR_PHY_REG_12_TX_DES)) = (((_VAL_) << 4) | ((REG32(ADR_PHY_REG_12_TX_DES)) & 0xffffffef))
++#define SET_RG_TX_DES_RATE_COMB(_VAL_) (REG32(ADR_PHY_REG_12_TX_DES)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_12_TX_DES)) & 0xfffffeff))
++#define SET_RG_TX_DES_MODE_COMB(_VAL_) (REG32(ADR_PHY_REG_12_TX_DES)) = (((_VAL_) << 12) | ((REG32(ADR_PHY_REG_12_TX_DES)) & 0xffffefff))
++#define SET_RG_TX_DES_PWRLVL(_VAL_) (REG32(ADR_PHY_REG_12_TX_DES)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_12_TX_DES)) & 0xffe0ffff))
++#define SET_RG_TX_DES_SRVC_LO(_VAL_) (REG32(ADR_PHY_REG_12_TX_DES)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_12_TX_DES)) & 0xe0ffffff))
++#define SET_RG_RX_DES_RATE(_VAL_) (REG32(ADR_PHY_REG_13_RX_DES)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_13_RX_DES)) & 0xffffffc0))
++#define SET_RG_RX_DES_MODE(_VAL_) (REG32(ADR_PHY_REG_13_RX_DES)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_13_RX_DES)) & 0xffffc0ff))
++#define SET_RG_RX_DES_LEN_LO(_VAL_) (REG32(ADR_PHY_REG_13_RX_DES)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_13_RX_DES)) & 0xffc0ffff))
++#define SET_RG_RX_DES_LEN_UP(_VAL_) (REG32(ADR_PHY_REG_13_RX_DES)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_13_RX_DES)) & 0xc0ffffff))
++#define SET_RG_RX_DES_SRVC_UP(_VAL_) (REG32(ADR_PHY_REG_14_RX_DES)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_14_RX_DES)) & 0xffffffc0))
++#define SET_RG_RX_DES_L_LEN_LO(_VAL_) (REG32(ADR_PHY_REG_14_RX_DES)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_14_RX_DES)) & 0xffffc0ff))
++#define SET_RG_RX_DES_L_LEN_UP(_VAL_) (REG32(ADR_PHY_REG_14_RX_DES)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_14_RX_DES)) & 0xffc0ffff))
++#define SET_RG_RX_DES_TYPE(_VAL_) (REG32(ADR_PHY_REG_14_RX_DES)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_14_RX_DES)) & 0xc0ffffff))
++#define SET_RG_RX_DES_L_LEN_UP_COMB(_VAL_) (REG32(ADR_PHY_REG_15_RX_DES)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_15_RX_DES)) & 0xfffffffe))
++#define SET_RG_RX_DES_TYPE_COMB(_VAL_) (REG32(ADR_PHY_REG_15_RX_DES)) = (((_VAL_) << 4) | ((REG32(ADR_PHY_REG_15_RX_DES)) & 0xffffffef))
++#define SET_RG_RX_DES_RATE_COMB(_VAL_) (REG32(ADR_PHY_REG_15_RX_DES)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_15_RX_DES)) & 0xfffffeff))
++#define SET_RG_RX_DES_MODE_COMB(_VAL_) (REG32(ADR_PHY_REG_15_RX_DES)) = (((_VAL_) << 12) | ((REG32(ADR_PHY_REG_15_RX_DES)) & 0xffffefff))
++#define SET_RG_RX_DES_SNR(_VAL_) (REG32(ADR_PHY_REG_15_RX_DES)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_15_RX_DES)) & 0xfff0ffff))
++#define SET_RG_RX_DES_RCPI(_VAL_) (REG32(ADR_PHY_REG_15_RX_DES)) = (((_VAL_) << 20) | ((REG32(ADR_PHY_REG_15_RX_DES)) & 0xff0fffff))
++#define SET_RG_RX_DES_SRVC_LO(_VAL_) (REG32(ADR_PHY_REG_15_RX_DES)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_15_RX_DES)) & 0xc0ffffff))
++#define SET_RO_TX_DES_EXCP_RATE_CNT(_VAL_) (REG32(ADR_PHY_REG_16_TX_DES_EXCP)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0xffffff00))
++#define SET_RO_TX_DES_EXCP_CH_BW_CNT(_VAL_) (REG32(ADR_PHY_REG_16_TX_DES_EXCP)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0xffff00ff))
++#define SET_RO_TX_DES_EXCP_MODE_CNT(_VAL_) (REG32(ADR_PHY_REG_16_TX_DES_EXCP)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0xff00ffff))
++#define SET_RG_TX_DES_EXCP_RATE_DEFAULT(_VAL_) (REG32(ADR_PHY_REG_16_TX_DES_EXCP)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0xf8ffffff))
++#define SET_RG_TX_DES_EXCP_MODE_DEFAULT(_VAL_) (REG32(ADR_PHY_REG_16_TX_DES_EXCP)) = (((_VAL_) << 28) | ((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0x8fffffff))
++#define SET_RG_TX_DES_EXCP_CLR(_VAL_) (REG32(ADR_PHY_REG_16_TX_DES_EXCP)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0x7fffffff))
++#define SET_RG_TX_DES_ACK_WIDTH(_VAL_) (REG32(ADR_PHY_REG_17_TX_DES_EXCP)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_17_TX_DES_EXCP)) & 0xfffffffe))
++#define SET_RG_TX_DES_ACK_PRD(_VAL_) (REG32(ADR_PHY_REG_17_TX_DES_EXCP)) = (((_VAL_) << 1) | ((REG32(ADR_PHY_REG_17_TX_DES_EXCP)) & 0xfffffff1))
++#define SET_RG_RX_DES_SNR_GN(_VAL_) (REG32(ADR_PHY_REG_17_TX_DES_EXCP)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_17_TX_DES_EXCP)) & 0xffc0ffff))
++#define SET_RG_RX_DES_RCPI_GN(_VAL_) (REG32(ADR_PHY_REG_17_TX_DES_EXCP)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_17_TX_DES_EXCP)) & 0xc0ffffff))
++#define SET_RG_TST_TBUS_SEL(_VAL_) (REG32(ADR_PHY_REG_18_RSSI_SNR)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0xfffffff0))
++#define SET_RG_RSSI_OFFSET(_VAL_) (REG32(ADR_PHY_REG_18_RSSI_SNR)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0xff00ffff))
++#define SET_RG_RSSI_INV(_VAL_) (REG32(ADR_PHY_REG_18_RSSI_SNR)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0xfeffffff))
++#define SET_RG_TST_ADC_ON(_VAL_) (REG32(ADR_PHY_REG_18_RSSI_SNR)) = (((_VAL_) << 30) | ((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0xbfffffff))
++#define SET_RG_TST_EXT_GAIN(_VAL_) (REG32(ADR_PHY_REG_18_RSSI_SNR)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0x7fffffff))
++#define SET_RG_DAC_Q_SET(_VAL_) (REG32(ADR_PHY_REG_19_DAC_MANUAL)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0xfffffc00))
++#define SET_RG_DAC_I_SET(_VAL_) (REG32(ADR_PHY_REG_19_DAC_MANUAL)) = (((_VAL_) << 12) | ((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0xffc00fff))
++#define SET_RG_DAC_EN_MAN(_VAL_) (REG32(ADR_PHY_REG_19_DAC_MANUAL)) = (((_VAL_) << 28) | ((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0xefffffff))
++#define SET_RG_IQC_FFT_EN(_VAL_) (REG32(ADR_PHY_REG_19_DAC_MANUAL)) = (((_VAL_) << 29) | ((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0xdfffffff))
++#define SET_RG_DAC_MAN_Q_EN(_VAL_) (REG32(ADR_PHY_REG_19_DAC_MANUAL)) = (((_VAL_) << 30) | ((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0xbfffffff))
++#define SET_RG_DAC_MAN_I_EN(_VAL_) (REG32(ADR_PHY_REG_19_DAC_MANUAL)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0x7fffffff))
++#define SET_RO_MRX_EN_CNT(_VAL_) (REG32(ADR_PHY_REG_20_MRX_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_20_MRX_CNT)) & 0xffff0000))
++#define SET_RG_MRX_EN_CNT_RST_N(_VAL_) (REG32(ADR_PHY_REG_20_MRX_CNT)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_20_MRX_CNT)) & 0x7fffffff))
++#define SET_RG_PA_RISE_TIME(_VAL_) (REG32(ADR_PHY_REG_21_TRX_RAMP)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_21_TRX_RAMP)) & 0xffffff00))
++#define SET_RG_RFTX_RISE_TIME(_VAL_) (REG32(ADR_PHY_REG_21_TRX_RAMP)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_21_TRX_RAMP)) & 0xffff00ff))
++#define SET_RG_DAC_RISE_TIME(_VAL_) (REG32(ADR_PHY_REG_21_TRX_RAMP)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_21_TRX_RAMP)) & 0xff00ffff))
++#define SET_RG_SW_RISE_TIME(_VAL_) (REG32(ADR_PHY_REG_21_TRX_RAMP)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_21_TRX_RAMP)) & 0x00ffffff))
++#define SET_RG_PA_FALL_TIME(_VAL_) (REG32(ADR_PHY_REG_22_TRX_RAMP)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_22_TRX_RAMP)) & 0xffffff00))
++#define SET_RG_RFTX_FALL_TIME(_VAL_) (REG32(ADR_PHY_REG_22_TRX_RAMP)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_22_TRX_RAMP)) & 0xffff00ff))
++#define SET_RG_DAC_FALL_TIME(_VAL_) (REG32(ADR_PHY_REG_22_TRX_RAMP)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_22_TRX_RAMP)) & 0xff00ffff))
++#define SET_RG_SW_FALL_TIME(_VAL_) (REG32(ADR_PHY_REG_22_TRX_RAMP)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_22_TRX_RAMP)) & 0x00ffffff))
++#define SET_RG_ANT_SW_0(_VAL_) (REG32(ADR_PHY_REG_23_ANT)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_23_ANT)) & 0xfffffff8))
++#define SET_RG_ANT_SW_1(_VAL_) (REG32(ADR_PHY_REG_23_ANT)) = (((_VAL_) << 3) | ((REG32(ADR_PHY_REG_23_ANT)) & 0xffffffc7))
++#define SET_RG_MTX_LEN_LOWER_TH_0(_VAL_) (REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) & 0xffffe000))
++#define SET_RG_MTX_LEN_UPPER_TH_0(_VAL_) (REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) & 0xe000ffff))
++#define SET_RG_MTX_LEN_CNT_EN_0(_VAL_) (REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) & 0x7fffffff))
++#define SET_RG_MTX_LEN_LOWER_TH_1(_VAL_) (REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) & 0xffffe000))
++#define SET_RG_MTX_LEN_UPPER_TH_1(_VAL_) (REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) & 0xe000ffff))
++#define SET_RG_MTX_LEN_CNT_EN_1(_VAL_) (REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) & 0x7fffffff))
++#define SET_RG_MRX_LEN_LOWER_TH_0(_VAL_) (REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) & 0xffffe000))
++#define SET_RG_MRX_LEN_UPPER_TH_0(_VAL_) (REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) & 0xe000ffff))
++#define SET_RG_MRX_LEN_CNT_EN_0(_VAL_) (REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) & 0x7fffffff))
++#define SET_RG_MRX_LEN_LOWER_TH_1(_VAL_) (REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) & 0xffffe000))
++#define SET_RG_MRX_LEN_UPPER_TH_1(_VAL_) (REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) & 0xe000ffff))
++#define SET_RG_MRX_LEN_CNT_EN_1(_VAL_) (REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) & 0x7fffffff))
++#define SET_RO_MTX_LEN_CNT_1(_VAL_) (REG32(ADR_PHY_READ_REG_04)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_04)) & 0xffff0000))
++#define SET_RO_MTX_LEN_CNT_0(_VAL_) (REG32(ADR_PHY_READ_REG_04)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_READ_REG_04)) & 0x0000ffff))
++#define SET_RO_MRX_LEN_CNT_1(_VAL_) (REG32(ADR_PHY_READ_REG_05)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_05)) & 0xffff0000))
++#define SET_RO_MRX_LEN_CNT_0(_VAL_) (REG32(ADR_PHY_READ_REG_05)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_READ_REG_05)) & 0x0000ffff))
++#define SET_RG_MODE_REG_IN_16(_VAL_) (REG32(ADR_PHY_REG_28_BIST)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_28_BIST)) & 0xffff0000))
++#define SET_RG_PARALLEL_DR_16(_VAL_) (REG32(ADR_PHY_REG_28_BIST)) = (((_VAL_) << 20) | ((REG32(ADR_PHY_REG_28_BIST)) & 0xffefffff))
++#define SET_RG_MBRUN_16(_VAL_) (REG32(ADR_PHY_REG_28_BIST)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_28_BIST)) & 0xfeffffff))
++#define SET_RG_SHIFT_DR_16(_VAL_) (REG32(ADR_PHY_REG_28_BIST)) = (((_VAL_) << 28) | ((REG32(ADR_PHY_REG_28_BIST)) & 0xefffffff))
++#define SET_RG_MODE_REG_SI_16(_VAL_) (REG32(ADR_PHY_REG_28_BIST)) = (((_VAL_) << 29) | ((REG32(ADR_PHY_REG_28_BIST)) & 0xdfffffff))
++#define SET_RG_SIMULATION_MODE_16(_VAL_) (REG32(ADR_PHY_REG_28_BIST)) = (((_VAL_) << 30) | ((REG32(ADR_PHY_REG_28_BIST)) & 0xbfffffff))
++#define SET_RG_DBIST_MODE_16(_VAL_) (REG32(ADR_PHY_REG_28_BIST)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_28_BIST)) & 0x7fffffff))
++#define SET_RO_MODE_REG_OUT_16(_VAL_) (REG32(ADR_PHY_READ_REG_06_BIST)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_06_BIST)) & 0xffff0000))
++#define SET_RO_MODE_REG_SO_16(_VAL_) (REG32(ADR_PHY_READ_REG_06_BIST)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_READ_REG_06_BIST)) & 0xfeffffff))
++#define SET_RO_MONITOR_BUS_16(_VAL_) (REG32(ADR_PHY_READ_REG_07_BIST)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_07_BIST)) & 0xfff80000))
++#define SET_RG_MRX_TYPE_1(_VAL_) (REG32(ADR_PHY_REG_29_MTRX_MAC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_29_MTRX_MAC)) & 0xffffff00))
++#define SET_RG_MRX_TYPE_0(_VAL_) (REG32(ADR_PHY_REG_29_MTRX_MAC)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_29_MTRX_MAC)) & 0xffff00ff))
++#define SET_RG_MTX_TYPE_1(_VAL_) (REG32(ADR_PHY_REG_29_MTRX_MAC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_29_MTRX_MAC)) & 0xff00ffff))
++#define SET_RG_MTX_TYPE_0(_VAL_) (REG32(ADR_PHY_REG_29_MTRX_MAC)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_29_MTRX_MAC)) & 0x00ffffff))
++#define SET_RO_MTX_TYPE_CNT_1(_VAL_) (REG32(ADR_PHY_READ_REG_08_MTRX_MAC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_08_MTRX_MAC)) & 0xffff0000))
++#define SET_RO_MTX_TYPE_CNT_0(_VAL_) (REG32(ADR_PHY_READ_REG_08_MTRX_MAC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_READ_REG_08_MTRX_MAC)) & 0x0000ffff))
++#define SET_RO_MRX_TYPE_CNT_1(_VAL_) (REG32(ADR_PHY_READ_REG_09_MTRX_MAC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_09_MTRX_MAC)) & 0xffff0000))
++#define SET_RO_MRX_TYPE_CNT_0(_VAL_) (REG32(ADR_PHY_READ_REG_09_MTRX_MAC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_READ_REG_09_MTRX_MAC)) & 0x0000ffff))
++#define SET_RG_HB_COEF0(_VAL_) (REG32(ADR_PHY_REG_30_TX_UP_FIL)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_30_TX_UP_FIL)) & 0xfffff000))
++#define SET_RG_HB_COEF1(_VAL_) (REG32(ADR_PHY_REG_30_TX_UP_FIL)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_30_TX_UP_FIL)) & 0xf000ffff))
++#define SET_RG_HB_COEF2(_VAL_) (REG32(ADR_PHY_REG_31_TX_UP_FIL)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_31_TX_UP_FIL)) & 0xfffff000))
++#define SET_RG_HB_COEF3(_VAL_) (REG32(ADR_PHY_REG_31_TX_UP_FIL)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_31_TX_UP_FIL)) & 0xf000ffff))
++#define SET_RG_HB_COEF4(_VAL_) (REG32(ADR_PHY_REG_32_TX_UP_FIL)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_32_TX_UP_FIL)) & 0xfffff000))
++#define SET_RO_TBUS_O(_VAL_) (REG32(ADR_PHY_READ_TBUS)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_TBUS)) & 0xfff00000))
++#define SET_RG_LPF4_00(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_00)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_00)) & 0xffffe000))
++#define SET_RG_LPF4_01(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_01)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_01)) & 0xffffe000))
++#define SET_RG_LPF4_02(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_02)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_02)) & 0xffffe000))
++#define SET_RG_LPF4_03(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_03)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_03)) & 0xffffe000))
++#define SET_RG_LPF4_04(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_04)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_04)) & 0xffffe000))
++#define SET_RG_LPF4_05(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_05)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_05)) & 0xffffe000))
++#define SET_RG_LPF4_06(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_06)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_06)) & 0xffffe000))
++#define SET_RG_LPF4_07(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_07)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_07)) & 0xffffe000))
++#define SET_RG_LPF4_08(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_08)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_08)) & 0xffffe000))
++#define SET_RG_LPF4_09(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_09)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_09)) & 0xffffe000))
++#define SET_RG_LPF4_10(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_10)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_10)) & 0xffffe000))
++#define SET_RG_LPF4_11(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_11)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_11)) & 0xffffe000))
++#define SET_RG_LPF4_12(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_12)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_12)) & 0xffffe000))
++#define SET_RG_LPF4_13(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_13)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_13)) & 0xffffe000))
++#define SET_RG_LPF4_14(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_14)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_14)) & 0xffffe000))
++#define SET_RG_LPF4_15(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_15)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_15)) & 0xffffe000))
++#define SET_RG_LPF4_16(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_16)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_16)) & 0xffffe000))
++#define SET_RG_LPF4_17(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_17)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_17)) & 0xffffe000))
++#define SET_RG_LPF4_18(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_18)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_18)) & 0xffffe000))
++#define SET_RG_LPF4_19(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_19)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_19)) & 0xffffe000))
++#define SET_RG_LPF4_20(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_20)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_20)) & 0xffffe000))
++#define SET_RG_LPF4_21(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_21)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_21)) & 0xffffe000))
++#define SET_RG_LPF4_22(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_22)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_22)) & 0xffffe000))
++#define SET_RG_LPF4_23(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_23)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_23)) & 0xffffe000))
++#define SET_RG_LPF4_24(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_24)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_24)) & 0xffffe000))
++#define SET_RG_LPF4_25(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_25)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_25)) & 0xffffe000))
++#define SET_RG_LPF4_26(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_26)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_26)) & 0xffffe000))
++#define SET_RG_LPF4_27(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_27)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_27)) & 0xffffe000))
++#define SET_RG_LPF4_28(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_28)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_28)) & 0xffffe000))
++#define SET_RG_LPF4_29(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_29)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_29)) & 0xffffe000))
++#define SET_RG_LPF4_30(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_30)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_30)) & 0xffffe000))
++#define SET_RG_LPF4_31(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_31)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_31)) & 0xffffe000))
++#define SET_RG_LPF4_32(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_32)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_32)) & 0xffffe000))
++#define SET_RG_LPF4_33(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_33)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_33)) & 0xffffe000))
++#define SET_RG_LPF4_34(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_34)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_34)) & 0xffffe000))
++#define SET_RG_LPF4_35(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_35)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_35)) & 0xffffe000))
++#define SET_RG_LPF4_36(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_36)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_36)) & 0xffffe000))
++#define SET_RG_LPF4_37(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_37)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_37)) & 0xffffe000))
++#define SET_RG_LPF4_38(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_38)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_38)) & 0xffffe000))
++#define SET_RG_LPF4_39(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_39)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_39)) & 0xffffe000))
++#define SET_RG_LPF4_40(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_40)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_40)) & 0xffffe000))
++#define SET_RG_BP_SMB(_VAL_) (REG32(ADR_TX_11B_PLCP)) = (((_VAL_) << 13) | ((REG32(ADR_TX_11B_PLCP)) & 0xffffdfff))
++#define SET_RG_EN_SRVC(_VAL_) (REG32(ADR_TX_11B_PLCP)) = (((_VAL_) << 14) | ((REG32(ADR_TX_11B_PLCP)) & 0xffffbfff))
++#define SET_RG_DES_SPD(_VAL_) (REG32(ADR_TX_11B_PLCP)) = (((_VAL_) << 16) | ((REG32(ADR_TX_11B_PLCP)) & 0xfffcffff))
++#define SET_RG_BB_11B_RISE_TIME(_VAL_) (REG32(ADR_TX_11B_RAMP)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_RAMP)) & 0xffffff00))
++#define SET_RG_BB_11B_FALL_TIME(_VAL_) (REG32(ADR_TX_11B_RAMP)) = (((_VAL_) << 8) | ((REG32(ADR_TX_11B_RAMP)) & 0xffff00ff))
++#define SET_RG_WR_TX_EN_CNT_RST_N(_VAL_) (REG32(ADR_TX_11B_EN_CNT_RST_N)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_EN_CNT_RST_N)) & 0xfffffffe))
++#define SET_RO_TX_EN_CNT(_VAL_) (REG32(ADR_TX_11B_EN_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_EN_CNT)) & 0xffff0000))
++#define SET_RO_TX_CNT(_VAL_) (REG32(ADR_TX_11B_PKT_GEN_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_PKT_GEN_CNT)) & 0x00000000))
++#define SET_RG_POS_DES_11B_L_EXT(_VAL_) (REG32(ADR_RX_11B_DES_DLY)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_DES_DLY)) & 0xfffffff0))
++#define SET_RG_PRE_DES_11B_DLY(_VAL_) (REG32(ADR_RX_11B_DES_DLY)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11B_DES_DLY)) & 0xffffff0f))
++#define SET_RG_CNT_CCA_LMT(_VAL_) (REG32(ADR_RX_11B_CCA_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_CCA_0)) & 0xfff0ffff))
++#define SET_RG_BYPASS_DESCRAMBLER(_VAL_) (REG32(ADR_RX_11B_CCA_0)) = (((_VAL_) << 29) | ((REG32(ADR_RX_11B_CCA_0)) & 0xdfffffff))
++#define SET_RG_BYPASS_AGC(_VAL_) (REG32(ADR_RX_11B_CCA_0)) = (((_VAL_) << 31) | ((REG32(ADR_RX_11B_CCA_0)) & 0x7fffffff))
++#define SET_RG_CCA_BIT_CNT_LMT_RX(_VAL_) (REG32(ADR_RX_11B_CCA_1)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11B_CCA_1)) & 0xffffff0f))
++#define SET_RG_CCA_SCALE_BF(_VAL_) (REG32(ADR_RX_11B_CCA_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_CCA_1)) & 0xff80ffff))
++#define SET_RG_PEAK_IDX_CNT_SEL(_VAL_) (REG32(ADR_RX_11B_CCA_1)) = (((_VAL_) << 28) | ((REG32(ADR_RX_11B_CCA_1)) & 0xcfffffff))
++#define SET_RG_TR_KI_T2(_VAL_) (REG32(ADR_RX_11B_TR_KP_KI_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_TR_KP_KI_0)) & 0xfffffff8))
++#define SET_RG_TR_KP_T2(_VAL_) (REG32(ADR_RX_11B_TR_KP_KI_0)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11B_TR_KP_KI_0)) & 0xffffff8f))
++#define SET_RG_TR_KI_T1(_VAL_) (REG32(ADR_RX_11B_TR_KP_KI_0)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11B_TR_KP_KI_0)) & 0xfffff8ff))
++#define SET_RG_TR_KP_T1(_VAL_) (REG32(ADR_RX_11B_TR_KP_KI_0)) = (((_VAL_) << 12) | ((REG32(ADR_RX_11B_TR_KP_KI_0)) & 0xffff8fff))
++#define SET_RG_CR_KI_T1(_VAL_) (REG32(ADR_RX_11B_TR_KP_KI_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_TR_KP_KI_1)) & 0xfff8ffff))
++#define SET_RG_CR_KP_T1(_VAL_) (REG32(ADR_RX_11B_TR_KP_KI_1)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11B_TR_KP_KI_1)) & 0xff8fffff))
++#define SET_RG_CHIP_CNT_SLICER(_VAL_) (REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) & 0xffffffe0))
++#define SET_RG_CE_T4_CNT_LMT(_VAL_) (REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) & 0xffff00ff))
++#define SET_RG_CE_T3_CNT_LMT(_VAL_) (REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) & 0xff00ffff))
++#define SET_RG_CE_T2_CNT_LMT(_VAL_) (REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) & 0x00ffffff))
++#define SET_RG_CE_MU_T1(_VAL_) (REG32(ADR_RX_11B_CE_MU_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_CE_MU_0)) & 0xfffffff8))
++#define SET_RG_CE_DLY_SEL(_VAL_) (REG32(ADR_RX_11B_CE_MU_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_CE_MU_0)) & 0xffc0ffff))
++#define SET_RG_CE_MU_T8(_VAL_) (REG32(ADR_RX_11B_CE_MU_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_CE_MU_1)) & 0xfffffff8))
++#define SET_RG_CE_MU_T7(_VAL_) (REG32(ADR_RX_11B_CE_MU_1)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11B_CE_MU_1)) & 0xffffff8f))
++#define SET_RG_CE_MU_T6(_VAL_) (REG32(ADR_RX_11B_CE_MU_1)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11B_CE_MU_1)) & 0xfffff8ff))
++#define SET_RG_CE_MU_T5(_VAL_) (REG32(ADR_RX_11B_CE_MU_1)) = (((_VAL_) << 12) | ((REG32(ADR_RX_11B_CE_MU_1)) & 0xffff8fff))
++#define SET_RG_CE_MU_T4(_VAL_) (REG32(ADR_RX_11B_CE_MU_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_CE_MU_1)) & 0xfff8ffff))
++#define SET_RG_CE_MU_T3(_VAL_) (REG32(ADR_RX_11B_CE_MU_1)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11B_CE_MU_1)) & 0xff8fffff))
++#define SET_RG_CE_MU_T2(_VAL_) (REG32(ADR_RX_11B_CE_MU_1)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11B_CE_MU_1)) & 0xf8ffffff))
++#define SET_RG_EQ_MU_FB_T2(_VAL_) (REG32(ADR_RX_11B_EQ_MU_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_EQ_MU_0)) & 0xfffffff0))
++#define SET_RG_EQ_MU_FF_T2(_VAL_) (REG32(ADR_RX_11B_EQ_MU_0)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11B_EQ_MU_0)) & 0xffffff0f))
++#define SET_RG_EQ_MU_FB_T1(_VAL_) (REG32(ADR_RX_11B_EQ_MU_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_EQ_MU_0)) & 0xfff0ffff))
++#define SET_RG_EQ_MU_FF_T1(_VAL_) (REG32(ADR_RX_11B_EQ_MU_0)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11B_EQ_MU_0)) & 0xff0fffff))
++#define SET_RG_EQ_MU_FB_T4(_VAL_) (REG32(ADR_RX_11B_EQ_MU_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_EQ_MU_1)) & 0xfffffff0))
++#define SET_RG_EQ_MU_FF_T4(_VAL_) (REG32(ADR_RX_11B_EQ_MU_1)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11B_EQ_MU_1)) & 0xffffff0f))
++#define SET_RG_EQ_MU_FB_T3(_VAL_) (REG32(ADR_RX_11B_EQ_MU_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_EQ_MU_1)) & 0xfff0ffff))
++#define SET_RG_EQ_MU_FF_T3(_VAL_) (REG32(ADR_RX_11B_EQ_MU_1)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11B_EQ_MU_1)) & 0xff0fffff))
++#define SET_RG_EQ_KI_T2(_VAL_) (REG32(ADR_RX_11B_EQ_CR_KP_KI)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11B_EQ_CR_KP_KI)) & 0xfffff8ff))
++#define SET_RG_EQ_KP_T2(_VAL_) (REG32(ADR_RX_11B_EQ_CR_KP_KI)) = (((_VAL_) << 12) | ((REG32(ADR_RX_11B_EQ_CR_KP_KI)) & 0xffff8fff))
++#define SET_RG_EQ_KI_T1(_VAL_) (REG32(ADR_RX_11B_EQ_CR_KP_KI)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_EQ_CR_KP_KI)) & 0xfff8ffff))
++#define SET_RG_EQ_KP_T1(_VAL_) (REG32(ADR_RX_11B_EQ_CR_KP_KI)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11B_EQ_CR_KP_KI)) & 0xff8fffff))
++#define SET_RG_TR_LPF_RATE(_VAL_) (REG32(ADR_RX_11B_LPF_RATE)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_LPF_RATE)) & 0xffc00000))
++#define SET_RG_CE_BIT_CNT_LMT(_VAL_) (REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0xffffff80))
++#define SET_RG_CE_CH_MAIN_SET(_VAL_) (REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) = (((_VAL_) << 7) | ((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0xffffff7f))
++#define SET_RG_TC_BIT_CNT_LMT(_VAL_) (REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0xffff80ff))
++#define SET_RG_CR_BIT_CNT_LMT(_VAL_) (REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0xff80ffff))
++#define SET_RG_TR_BIT_CNT_LMT(_VAL_) (REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0x80ffffff))
++#define SET_RG_EQ_MAIN_TAP_MAN(_VAL_) (REG32(ADR_RX_11B_EQ_CH_MAIN_TAP)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_EQ_CH_MAIN_TAP)) & 0xfffffffe))
++#define SET_RG_EQ_MAIN_TAP_COEF(_VAL_) (REG32(ADR_RX_11B_EQ_CH_MAIN_TAP)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_EQ_CH_MAIN_TAP)) & 0xf800ffff))
++#define SET_RG_PWRON_DLY_TH_11B(_VAL_) (REG32(ADR_RX_11B_SEARCH_CNT_TH)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_SEARCH_CNT_TH)) & 0xffffff00))
++#define SET_RG_SFD_BIT_CNT_LMT(_VAL_) (REG32(ADR_RX_11B_SEARCH_CNT_TH)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_SEARCH_CNT_TH)) & 0xff00ffff))
++#define SET_RG_CCA_PWR_TH_RX(_VAL_) (REG32(ADR_RX_11B_CCA_CONTROL)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_CCA_CONTROL)) & 0xffff8000))
++#define SET_RG_CCA_PWR_CNT_TH(_VAL_) (REG32(ADR_RX_11B_CCA_CONTROL)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_CCA_CONTROL)) & 0xffe0ffff))
++#define SET_B_FREQ_OS(_VAL_) (REG32(ADR_RX_11B_FREQUENCY_OFFSET)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_FREQUENCY_OFFSET)) & 0xfffff800))
++#define SET_B_SNR(_VAL_) (REG32(ADR_RX_11B_SNR_RSSI)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_SNR_RSSI)) & 0xffffff80))
++#define SET_B_RCPI(_VAL_) (REG32(ADR_RX_11B_SNR_RSSI)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_SNR_RSSI)) & 0xff80ffff))
++#define SET_CRC_CNT(_VAL_) (REG32(ADR_RX_11B_SFD_CRC_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_SFD_CRC_CNT)) & 0xffff0000))
++#define SET_SFD_CNT(_VAL_) (REG32(ADR_RX_11B_SFD_CRC_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_SFD_CRC_CNT)) & 0x0000ffff))
++#define SET_B_PACKET_ERR_CNT(_VAL_) (REG32(ADR_RX_11B_PKT_ERR_AND_PKT_ERR_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_PKT_ERR_AND_PKT_ERR_CNT)) & 0xffff0000))
++#define SET_PACKET_ERR(_VAL_) (REG32(ADR_RX_11B_PKT_ERR_AND_PKT_ERR_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_PKT_ERR_AND_PKT_ERR_CNT)) & 0xfffeffff))
++#define SET_B_PACKET_CNT(_VAL_) (REG32(ADR_RX_11B_PKT_CCA_AND_PKT_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_PKT_CCA_AND_PKT_CNT)) & 0xffff0000))
++#define SET_B_CCA_CNT(_VAL_) (REG32(ADR_RX_11B_PKT_CCA_AND_PKT_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_PKT_CCA_AND_PKT_CNT)) & 0x0000ffff))
++#define SET_B_LENGTH_FIELD(_VAL_) (REG32(ADR_RX_11B_SFD_FILED_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_SFD_FILED_0)) & 0xffff0000))
++#define SET_SFD_FIELD(_VAL_) (REG32(ADR_RX_11B_SFD_FILED_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_SFD_FILED_0)) & 0x0000ffff))
++#define SET_SIGNAL_FIELD(_VAL_) (REG32(ADR_RX_11B_SFD_FIELD_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_SFD_FIELD_1)) & 0xffffff00))
++#define SET_B_SERVICE_FIELD(_VAL_) (REG32(ADR_RX_11B_SFD_FIELD_1)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11B_SFD_FIELD_1)) & 0xffff00ff))
++#define SET_CRC_CORRECT(_VAL_) (REG32(ADR_RX_11B_SFD_FIELD_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_SFD_FIELD_1)) & 0xfffeffff))
++#define SET_DEBUG_SEL(_VAL_) (REG32(ADR_RX_11B_PKT_STAT_EN)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_PKT_STAT_EN)) & 0xfffffff0))
++#define SET_RG_PACKET_STAT_EN_11B(_VAL_) (REG32(ADR_RX_11B_PKT_STAT_EN)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11B_PKT_STAT_EN)) & 0xffefffff))
++#define SET_RG_BIT_REVERSE(_VAL_) (REG32(ADR_RX_11B_PKT_STAT_EN)) = (((_VAL_) << 21) | ((REG32(ADR_RX_11B_PKT_STAT_EN)) & 0xffdfffff))
++#define SET_RX_PHY_11B_SOFT_RST_N(_VAL_) (REG32(ADR_RX_11B_SOFT_RST)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_SOFT_RST)) & 0xfffffffe))
++#define SET_RG_CE_BYPASS_TAP(_VAL_) (REG32(ADR_RX_11B_SOFT_RST)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11B_SOFT_RST)) & 0xffffff0f))
++#define SET_RG_EQ_BYPASS_FBW_TAP(_VAL_) (REG32(ADR_RX_11B_SOFT_RST)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11B_SOFT_RST)) & 0xfffff0ff))
++#define SET_RG_BB_11GN_RISE_TIME(_VAL_) (REG32(ADR_TX_11GN_RAMP)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11GN_RAMP)) & 0xffffff00))
++#define SET_RG_BB_11GN_FALL_TIME(_VAL_) (REG32(ADR_TX_11GN_RAMP)) = (((_VAL_) << 8) | ((REG32(ADR_TX_11GN_RAMP)) & 0xffff00ff))
++#define SET_RG_HTCARR52_FFT_SCALE(_VAL_) (REG32(ADR_TX_11GN_PLCP)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11GN_PLCP)) & 0xfffffc00))
++#define SET_RG_HTCARR56_FFT_SCALE(_VAL_) (REG32(ADR_TX_11GN_PLCP)) = (((_VAL_) << 12) | ((REG32(ADR_TX_11GN_PLCP)) & 0xffc00fff))
++#define SET_RG_PACKET_STAT_EN(_VAL_) (REG32(ADR_TX_11GN_PLCP)) = (((_VAL_) << 23) | ((REG32(ADR_TX_11GN_PLCP)) & 0xff7fffff))
++#define SET_RG_SMB_DEF(_VAL_) (REG32(ADR_TX_11GN_PLCP)) = (((_VAL_) << 24) | ((REG32(ADR_TX_11GN_PLCP)) & 0x80ffffff))
++#define SET_RG_CONTINUOUS_DATA_11GN(_VAL_) (REG32(ADR_TX_11GN_PLCP)) = (((_VAL_) << 31) | ((REG32(ADR_TX_11GN_PLCP)) & 0x7fffffff))
++#define SET_RO_TX_CNT_R(_VAL_) (REG32(ADR_TX_11GN_PKT_GEN_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11GN_PKT_GEN_CNT)) & 0x00000000))
++#define SET_RO_PACKET_ERR_CNT(_VAL_) (REG32(ADR_TX_11GN_PLCP_CRC_ERR_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11GN_PLCP_CRC_ERR_CNT)) & 0xffff0000))
++#define SET_RG_POS_DES_11GN_L_EXT(_VAL_) (REG32(ADR_RX_11GN_DES_DLY)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_DES_DLY)) & 0xfffffff0))
++#define SET_RG_PRE_DES_11GN_DLY(_VAL_) (REG32(ADR_RX_11GN_DES_DLY)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11GN_DES_DLY)) & 0xffffff0f))
++#define SET_RG_TR_LPF_KI_G_T1(_VAL_) (REG32(ADR_RX_11GN_TR_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_TR_0)) & 0xfffffff0))
++#define SET_RG_TR_LPF_KP_G_T1(_VAL_) (REG32(ADR_RX_11GN_TR_0)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11GN_TR_0)) & 0xffffff0f))
++#define SET_RG_TR_CNT_T1(_VAL_) (REG32(ADR_RX_11GN_TR_0)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_TR_0)) & 0xffff00ff))
++#define SET_RG_TR_LPF_KI_G_T0(_VAL_) (REG32(ADR_RX_11GN_TR_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_TR_0)) & 0xfff0ffff))
++#define SET_RG_TR_LPF_KP_G_T0(_VAL_) (REG32(ADR_RX_11GN_TR_0)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11GN_TR_0)) & 0xff0fffff))
++#define SET_RG_TR_CNT_T0(_VAL_) (REG32(ADR_RX_11GN_TR_0)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_TR_0)) & 0x00ffffff))
++#define SET_RG_TR_LPF_KI_G_T2(_VAL_) (REG32(ADR_RX_11GN_TR_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_TR_1)) & 0xfffffff0))
++#define SET_RG_TR_LPF_KP_G_T2(_VAL_) (REG32(ADR_RX_11GN_TR_1)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11GN_TR_1)) & 0xffffff0f))
++#define SET_RG_TR_CNT_T2(_VAL_) (REG32(ADR_RX_11GN_TR_1)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_TR_1)) & 0xffff00ff))
++#define SET_RG_TR_LPF_KI_G(_VAL_) (REG32(ADR_RX_11GN_TR_2)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_TR_2)) & 0xfffffff0))
++#define SET_RG_TR_LPF_KP_G(_VAL_) (REG32(ADR_RX_11GN_TR_2)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11GN_TR_2)) & 0xffffff0f))
++#define SET_RG_TR_LPF_RATE_G(_VAL_) (REG32(ADR_RX_11GN_TR_2)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_TR_2)) & 0xc00000ff))
++#define SET_RG_CR_LPF_KI_G(_VAL_) (REG32(ADR_RX_11GN_CCA_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_CCA_0)) & 0xfffffff8))
++#define SET_RG_SYM_BOUND_CNT(_VAL_) (REG32(ADR_RX_11GN_CCA_0)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_CCA_0)) & 0xffff80ff))
++#define SET_RG_XSCOR32_RATIO(_VAL_) (REG32(ADR_RX_11GN_CCA_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_CCA_0)) & 0xff80ffff))
++#define SET_RG_ATCOR64_CNT_LMT(_VAL_) (REG32(ADR_RX_11GN_CCA_0)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_CCA_0)) & 0x80ffffff))
++#define SET_RG_ATCOR16_CNT_LMT2(_VAL_) (REG32(ADR_RX_11GN_CCA_1)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_CCA_1)) & 0xffff80ff))
++#define SET_RG_ATCOR16_CNT_LMT1(_VAL_) (REG32(ADR_RX_11GN_CCA_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_CCA_1)) & 0xff80ffff))
++#define SET_RG_ATCOR16_RATIO_SB(_VAL_) (REG32(ADR_RX_11GN_CCA_1)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_CCA_1)) & 0x80ffffff))
++#define SET_RG_XSCOR64_CNT_LMT2(_VAL_) (REG32(ADR_RX_11GN_CCA_2)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_CCA_2)) & 0xff80ffff))
++#define SET_RG_XSCOR64_CNT_LMT1(_VAL_) (REG32(ADR_RX_11GN_CCA_2)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_CCA_2)) & 0x80ffffff))
++#define SET_RG_RX_FFT_SCALE(_VAL_) (REG32(ADR_RX_11GN_CCA_FFT_SCALE)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_CCA_FFT_SCALE)) & 0xfffffc00))
++#define SET_RG_VITERBI_AB_SWAP(_VAL_) (REG32(ADR_RX_11GN_CCA_FFT_SCALE)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_CCA_FFT_SCALE)) & 0xfffeffff))
++#define SET_RG_ATCOR16_CNT_TH(_VAL_) (REG32(ADR_RX_11GN_CCA_FFT_SCALE)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_CCA_FFT_SCALE)) & 0xf0ffffff))
++#define SET_RG_NORMSQUARE_LOW_SNR_7(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_0)) & 0xffffff00))
++#define SET_RG_NORMSQUARE_LOW_SNR_6(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_0)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_0)) & 0xffff00ff))
++#define SET_RG_NORMSQUARE_LOW_SNR_5(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_0)) & 0xff00ffff))
++#define SET_RG_NORMSQUARE_LOW_SNR_4(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_0)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_0)) & 0x00ffffff))
++#define SET_RG_NORMSQUARE_LOW_SNR_8(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_1)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_1)) & 0x00ffffff))
++#define SET_RG_NORMSQUARE_SNR_3(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_2)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_2)) & 0xffffff00))
++#define SET_RG_NORMSQUARE_SNR_2(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_2)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_2)) & 0xffff00ff))
++#define SET_RG_NORMSQUARE_SNR_1(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_2)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_2)) & 0xff00ffff))
++#define SET_RG_NORMSQUARE_SNR_0(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_2)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_2)) & 0x00ffffff))
++#define SET_RG_NORMSQUARE_SNR_7(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_3)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_3)) & 0xffffff00))
++#define SET_RG_NORMSQUARE_SNR_6(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_3)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_3)) & 0xffff00ff))
++#define SET_RG_NORMSQUARE_SNR_5(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_3)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_3)) & 0xff00ffff))
++#define SET_RG_NORMSQUARE_SNR_4(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_3)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_3)) & 0x00ffffff))
++#define SET_RG_NORMSQUARE_SNR_8(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_4)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_4)) & 0x00ffffff))
++#define SET_RG_SNR_TH_64QAM(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_5)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_5)) & 0xffffff80))
++#define SET_RG_SNR_TH_16QAM(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_5)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_5)) & 0xffff80ff))
++#define SET_RG_ATCOR16_CNT_PLUS_LMT2(_VAL_) (REG32(ADR_RX_11GN_SYM_BOUND_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SYM_BOUND_0)) & 0xffffff80))
++#define SET_RG_ATCOR16_CNT_PLUS_LMT1(_VAL_) (REG32(ADR_RX_11GN_SYM_BOUND_0)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_SYM_BOUND_0)) & 0xffff80ff))
++#define SET_RG_SYM_BOUND_METHOD(_VAL_) (REG32(ADR_RX_11GN_SYM_BOUND_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_SYM_BOUND_0)) & 0xfffcffff))
++#define SET_RG_PWRON_DLY_TH_11GN(_VAL_) (REG32(ADR_RX_11GN_SYM_BOUND_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SYM_BOUND_1)) & 0xffffff00))
++#define SET_RG_SB_START_CNT(_VAL_) (REG32(ADR_RX_11GN_SYM_BOUND_1)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_SYM_BOUND_1)) & 0xffff80ff))
++#define SET_RG_POW16_CNT_TH(_VAL_) (REG32(ADR_RX_11GN_CCA_PWR)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11GN_CCA_PWR)) & 0xffffff0f))
++#define SET_RG_POW16_SHORT_CNT_LMT(_VAL_) (REG32(ADR_RX_11GN_CCA_PWR)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_CCA_PWR)) & 0xfffff8ff))
++#define SET_RG_POW16_TH_L(_VAL_) (REG32(ADR_RX_11GN_CCA_PWR)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_CCA_PWR)) & 0x80ffffff))
++#define SET_RG_XSCOR16_SHORT_CNT_LMT(_VAL_) (REG32(ADR_RX_11GN_CCA_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_CCA_CNT)) & 0xfffffff8))
++#define SET_RG_XSCOR16_RATIO(_VAL_) (REG32(ADR_RX_11GN_CCA_CNT)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_CCA_CNT)) & 0xffff80ff))
++#define SET_RG_ATCOR16_SHORT_CNT_LMT(_VAL_) (REG32(ADR_RX_11GN_CCA_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_CCA_CNT)) & 0xfff8ffff))
++#define SET_RG_ATCOR16_RATIO_CCD(_VAL_) (REG32(ADR_RX_11GN_CCA_CNT)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_CCA_CNT)) & 0x80ffffff))
++#define SET_RG_ATCOR64_ACC_LMT(_VAL_) (REG32(ADR_RX_11GN_CCA_ATCOR_RE_CHECK)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_CCA_ATCOR_RE_CHECK)) & 0xffffff80))
++#define SET_RG_ATCOR16_SHORT_CNT_LMT2(_VAL_) (REG32(ADR_RX_11GN_CCA_ATCOR_RE_CHECK)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_CCA_ATCOR_RE_CHECK)) & 0xfff8ffff))
++#define SET_RG_VITERBI_TB_BITS(_VAL_) (REG32(ADR_RX_11GN_VTB_TB)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_VTB_TB)) & 0x00ffffff))
++#define SET_RG_CR_CNT_UPDATE(_VAL_) (REG32(ADR_RX_11GN_ERR_UPDATE)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_ERR_UPDATE)) & 0xffffff00))
++#define SET_RG_TR_CNT_UPDATE(_VAL_) (REG32(ADR_RX_11GN_ERR_UPDATE)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_ERR_UPDATE)) & 0xff00ffff))
++#define SET_RG_BYPASS_CPE_MA(_VAL_) (REG32(ADR_RX_11GN_SHORT_GI)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11GN_SHORT_GI)) & 0xffffffef))
++#define SET_RG_PILOT_BNDRY_SHIFT(_VAL_) (REG32(ADR_RX_11GN_SHORT_GI)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_SHORT_GI)) & 0xfffff8ff))
++#define SET_RG_EQ_SHORT_GI_SHIFT(_VAL_) (REG32(ADR_RX_11GN_SHORT_GI)) = (((_VAL_) << 12) | ((REG32(ADR_RX_11GN_SHORT_GI)) & 0xffff8fff))
++#define SET_RG_FFT_WDW_SHORT_SHIFT(_VAL_) (REG32(ADR_RX_11GN_SHORT_GI)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_SHORT_GI)) & 0xfff8ffff))
++#define SET_RG_CHSMTH_COEF(_VAL_) (REG32(ADR_RX_11GN_CHANNEL_UPDATE)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_CHANNEL_UPDATE)) & 0xfffcffff))
++#define SET_RG_CHSMTH_EN(_VAL_) (REG32(ADR_RX_11GN_CHANNEL_UPDATE)) = (((_VAL_) << 18) | ((REG32(ADR_RX_11GN_CHANNEL_UPDATE)) & 0xfffbffff))
++#define SET_RG_CHEST_DD_FACTOR(_VAL_) (REG32(ADR_RX_11GN_CHANNEL_UPDATE)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_CHANNEL_UPDATE)) & 0xf8ffffff))
++#define SET_RG_CH_UPDATE(_VAL_) (REG32(ADR_RX_11GN_CHANNEL_UPDATE)) = (((_VAL_) << 31) | ((REG32(ADR_RX_11GN_CHANNEL_UPDATE)) & 0x7fffffff))
++#define SET_RG_FMT_DET_MM_TH(_VAL_) (REG32(ADR_RX_11GN_PKT_FORMAT_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_PKT_FORMAT_0)) & 0xffffff00))
++#define SET_RG_FMT_DET_GF_TH(_VAL_) (REG32(ADR_RX_11GN_PKT_FORMAT_0)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_PKT_FORMAT_0)) & 0xffff00ff))
++#define SET_RG_DO_NOT_CHECK_L_RATE(_VAL_) (REG32(ADR_RX_11GN_PKT_FORMAT_0)) = (((_VAL_) << 25) | ((REG32(ADR_RX_11GN_PKT_FORMAT_0)) & 0xfdffffff))
++#define SET_RG_FMT_DET_LENGTH_TH(_VAL_) (REG32(ADR_RX_11GN_PKT_FORMAT_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_PKT_FORMAT_1)) & 0xffff0000))
++#define SET_RG_L_LENGTH_MAX(_VAL_) (REG32(ADR_RX_11GN_PKT_FORMAT_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_PKT_FORMAT_1)) & 0x0000ffff))
++#define SET_RG_TX_TIME_EXT(_VAL_) (REG32(ADR_RX_11GN_TX_TIME)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_TX_TIME)) & 0xffffff00))
++#define SET_RG_MAC_DES_SPACE(_VAL_) (REG32(ADR_RX_11GN_TX_TIME)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11GN_TX_TIME)) & 0xff0fffff))
++#define SET_RG_TR_LPF_STBC_GF_KI_G(_VAL_) (REG32(ADR_RX_11GN_STBC_TR_KP_KI)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_STBC_TR_KP_KI)) & 0xfffffff0))
++#define SET_RG_TR_LPF_STBC_GF_KP_G(_VAL_) (REG32(ADR_RX_11GN_STBC_TR_KP_KI)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11GN_STBC_TR_KP_KI)) & 0xffffff0f))
++#define SET_RG_TR_LPF_STBC_MF_KI_G(_VAL_) (REG32(ADR_RX_11GN_STBC_TR_KP_KI)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_STBC_TR_KP_KI)) & 0xfffff0ff))
++#define SET_RG_TR_LPF_STBC_MF_KP_G(_VAL_) (REG32(ADR_RX_11GN_STBC_TR_KP_KI)) = (((_VAL_) << 12) | ((REG32(ADR_RX_11GN_STBC_TR_KP_KI)) & 0xffff0fff))
++#define SET_RG_MODE_REG_IN_80(_VAL_) (REG32(ADR_RX_11GN_BIST_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_BIST_0)) & 0xfffe0000))
++#define SET_RG_PARALLEL_DR_80(_VAL_) (REG32(ADR_RX_11GN_BIST_0)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11GN_BIST_0)) & 0xffefffff))
++#define SET_RG_MBRUN_80(_VAL_) (REG32(ADR_RX_11GN_BIST_0)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_BIST_0)) & 0xfeffffff))
++#define SET_RG_SHIFT_DR_80(_VAL_) (REG32(ADR_RX_11GN_BIST_0)) = (((_VAL_) << 28) | ((REG32(ADR_RX_11GN_BIST_0)) & 0xefffffff))
++#define SET_RG_MODE_REG_SI_80(_VAL_) (REG32(ADR_RX_11GN_BIST_0)) = (((_VAL_) << 29) | ((REG32(ADR_RX_11GN_BIST_0)) & 0xdfffffff))
++#define SET_RG_SIMULATION_MODE_80(_VAL_) (REG32(ADR_RX_11GN_BIST_0)) = (((_VAL_) << 30) | ((REG32(ADR_RX_11GN_BIST_0)) & 0xbfffffff))
++#define SET_RG_DBIST_MODE_80(_VAL_) (REG32(ADR_RX_11GN_BIST_0)) = (((_VAL_) << 31) | ((REG32(ADR_RX_11GN_BIST_0)) & 0x7fffffff))
++#define SET_RG_MODE_REG_IN_64(_VAL_) (REG32(ADR_RX_11GN_BIST_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_BIST_1)) & 0xffff0000))
++#define SET_RG_PARALLEL_DR_64(_VAL_) (REG32(ADR_RX_11GN_BIST_1)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11GN_BIST_1)) & 0xffefffff))
++#define SET_RG_MBRUN_64(_VAL_) (REG32(ADR_RX_11GN_BIST_1)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_BIST_1)) & 0xfeffffff))
++#define SET_RG_SHIFT_DR_64(_VAL_) (REG32(ADR_RX_11GN_BIST_1)) = (((_VAL_) << 28) | ((REG32(ADR_RX_11GN_BIST_1)) & 0xefffffff))
++#define SET_RG_MODE_REG_SI_64(_VAL_) (REG32(ADR_RX_11GN_BIST_1)) = (((_VAL_) << 29) | ((REG32(ADR_RX_11GN_BIST_1)) & 0xdfffffff))
++#define SET_RG_SIMULATION_MODE_64(_VAL_) (REG32(ADR_RX_11GN_BIST_1)) = (((_VAL_) << 30) | ((REG32(ADR_RX_11GN_BIST_1)) & 0xbfffffff))
++#define SET_RG_DBIST_MODE_64(_VAL_) (REG32(ADR_RX_11GN_BIST_1)) = (((_VAL_) << 31) | ((REG32(ADR_RX_11GN_BIST_1)) & 0x7fffffff))
++#define SET_RO_MODE_REG_OUT_80(_VAL_) (REG32(ADR_RX_11GN_BIST_2)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_BIST_2)) & 0xfffe0000))
++#define SET_RO_MODE_REG_SO_80(_VAL_) (REG32(ADR_RX_11GN_BIST_2)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_BIST_2)) & 0xfeffffff))
++#define SET_RO_MONITOR_BUS_80(_VAL_) (REG32(ADR_RX_11GN_BIST_3)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_BIST_3)) & 0xffc00000))
++#define SET_RO_MODE_REG_OUT_64(_VAL_) (REG32(ADR_RX_11GN_BIST_4)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_BIST_4)) & 0xffff0000))
++#define SET_RO_MODE_REG_SO_64(_VAL_) (REG32(ADR_RX_11GN_BIST_4)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_BIST_4)) & 0xfeffffff))
++#define SET_RO_MONITOR_BUS_64(_VAL_) (REG32(ADR_RX_11GN_BIST_5)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_BIST_5)) & 0xfff80000))
++#define SET_RO_SPECTRUM_DATA(_VAL_) (REG32(ADR_RX_11GN_SPECTRUM_ANALYZER)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SPECTRUM_ANALYZER)) & 0x00000000))
++#define SET_GN_SNR(_VAL_) (REG32(ADR_RX_11GN_READ_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_READ_0)) & 0xffffff80))
++#define SET_GN_NOISE_PWR(_VAL_) (REG32(ADR_RX_11GN_READ_0)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_READ_0)) & 0xffff80ff))
++#define SET_GN_RCPI(_VAL_) (REG32(ADR_RX_11GN_READ_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_READ_0)) & 0xff80ffff))
++#define SET_GN_SIGNAL_PWR(_VAL_) (REG32(ADR_RX_11GN_READ_0)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_READ_0)) & 0x80ffffff))
++#define SET_RO_FREQ_OS_LTS(_VAL_) (REG32(ADR_RX_11GN_FREQ_OFFSET)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_FREQ_OFFSET)) & 0xffff8000))
++#define SET_CSTATE(_VAL_) (REG32(ADR_RX_11GN_FREQ_OFFSET)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_FREQ_OFFSET)) & 0xfff0ffff))
++#define SET_SIGNAL_FIELD0(_VAL_) (REG32(ADR_RX_11GN_SIGNAL_FIELD_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SIGNAL_FIELD_0)) & 0xff000000))
++#define SET_SIGNAL_FIELD1(_VAL_) (REG32(ADR_RX_11GN_SIGNAL_FIELD_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SIGNAL_FIELD_1)) & 0xff000000))
++#define SET_GN_PACKET_ERR_CNT(_VAL_) (REG32(ADR_RX_11GN_PKT_ERR_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_PKT_ERR_CNT)) & 0xffff0000))
++#define SET_GN_PACKET_CNT(_VAL_) (REG32(ADR_RX_11GN_PKT_CCA_AND_PKT_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_PKT_CCA_AND_PKT_CNT)) & 0xffff0000))
++#define SET_GN_CCA_CNT(_VAL_) (REG32(ADR_RX_11GN_PKT_CCA_AND_PKT_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_PKT_CCA_AND_PKT_CNT)) & 0x0000ffff))
++#define SET_GN_LENGTH_FIELD(_VAL_) (REG32(ADR_RX_11GN_SERVICE_LENGTH_FIELD)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SERVICE_LENGTH_FIELD)) & 0xffff0000))
++#define SET_GN_SERVICE_FIELD(_VAL_) (REG32(ADR_RX_11GN_SERVICE_LENGTH_FIELD)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_SERVICE_LENGTH_FIELD)) & 0x0000ffff))
++#define SET_RO_HT_MCS_40M(_VAL_) (REG32(ADR_RX_11GN_RATE)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_RATE)) & 0xffffff80))
++#define SET_RO_L_RATE_40M(_VAL_) (REG32(ADR_RX_11GN_RATE)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_RATE)) & 0xffffc0ff))
++#define SET_RG_DAGC_CNT_TH(_VAL_) (REG32(ADR_RX_11GN_STAT_EN)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_STAT_EN)) & 0xfffffffc))
++#define SET_RG_PACKET_STAT_EN_11GN(_VAL_) (REG32(ADR_RX_11GN_STAT_EN)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11GN_STAT_EN)) & 0xffefffff))
++#define SET_RX_PHY_11GN_SOFT_RST_N(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xfffffffe))
++#define SET_RG_RIFS_EN(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 1) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xfffffffd))
++#define SET_RG_STBC_EN(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 2) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xfffffffb))
++#define SET_RG_COR_SEL(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 3) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xfffffff7))
++#define SET_RG_INI_PHASE(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xffffffcf))
++#define SET_RG_HT_LTF_SEL_EQ(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 6) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xffffffbf))
++#define SET_RG_HT_LTF_SEL_PILOT(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 7) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xffffff7f))
++#define SET_RG_CCA_PWR_SEL(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 9) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xfffffdff))
++#define SET_RG_CCA_XSCOR_PWR_SEL(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 10) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xfffffbff))
++#define SET_RG_CCA_XSCOR_AVGPWR_SEL(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 11) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xfffff7ff))
++#define SET_RG_DEBUG_SEL(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 12) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xffff0fff))
++#define SET_RG_POST_CLK_EN(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xfffeffff))
++#define SET_IQCAL_RF_TX_EN(_VAL_) (REG32(ADR_RF_CONTROL_0)) = (((_VAL_) << 0) | ((REG32(ADR_RF_CONTROL_0)) & 0xfffffffe))
++#define SET_IQCAL_RF_TX_PA_EN(_VAL_) (REG32(ADR_RF_CONTROL_0)) = (((_VAL_) << 1) | ((REG32(ADR_RF_CONTROL_0)) & 0xfffffffd))
++#define SET_IQCAL_RF_TX_DAC_EN(_VAL_) (REG32(ADR_RF_CONTROL_0)) = (((_VAL_) << 2) | ((REG32(ADR_RF_CONTROL_0)) & 0xfffffffb))
++#define SET_IQCAL_RF_RX_AGC(_VAL_) (REG32(ADR_RF_CONTROL_0)) = (((_VAL_) << 3) | ((REG32(ADR_RF_CONTROL_0)) & 0xfffffff7))
++#define SET_IQCAL_RF_PGAG(_VAL_) (REG32(ADR_RF_CONTROL_0)) = (((_VAL_) << 8) | ((REG32(ADR_RF_CONTROL_0)) & 0xfffff0ff))
++#define SET_IQCAL_RF_RFG(_VAL_) (REG32(ADR_RF_CONTROL_0)) = (((_VAL_) << 12) | ((REG32(ADR_RF_CONTROL_0)) & 0xffffcfff))
++#define SET_RG_TONEGEN_FREQ(_VAL_) (REG32(ADR_RF_CONTROL_0)) = (((_VAL_) << 16) | ((REG32(ADR_RF_CONTROL_0)) & 0xff80ffff))
++#define SET_RG_TONEGEN_EN(_VAL_) (REG32(ADR_RF_CONTROL_0)) = (((_VAL_) << 23) | ((REG32(ADR_RF_CONTROL_0)) & 0xff7fffff))
++#define SET_RG_TONEGEN_INIT_PH(_VAL_) (REG32(ADR_RF_CONTROL_0)) = (((_VAL_) << 24) | ((REG32(ADR_RF_CONTROL_0)) & 0x80ffffff))
++#define SET_RG_TONEGEN2_FREQ(_VAL_) (REG32(ADR_RF_CONTROL_1)) = (((_VAL_) << 0) | ((REG32(ADR_RF_CONTROL_1)) & 0xffffff80))
++#define SET_RG_TONEGEN2_EN(_VAL_) (REG32(ADR_RF_CONTROL_1)) = (((_VAL_) << 7) | ((REG32(ADR_RF_CONTROL_1)) & 0xffffff7f))
++#define SET_RG_TONEGEN2_SCALE(_VAL_) (REG32(ADR_RF_CONTROL_1)) = (((_VAL_) << 8) | ((REG32(ADR_RF_CONTROL_1)) & 0xffff00ff))
++#define SET_RG_TXIQ_CLP_THD_I(_VAL_) (REG32(ADR_TX_IQ_CONTROL_0)) = (((_VAL_) << 0) | ((REG32(ADR_TX_IQ_CONTROL_0)) & 0xfffffc00))
++#define SET_RG_TXIQ_CLP_THD_Q(_VAL_) (REG32(ADR_TX_IQ_CONTROL_0)) = (((_VAL_) << 16) | ((REG32(ADR_TX_IQ_CONTROL_0)) & 0xfc00ffff))
++#define SET_RG_TX_I_SCALE(_VAL_) (REG32(ADR_TX_IQ_CONTROL_1)) = (((_VAL_) << 0) | ((REG32(ADR_TX_IQ_CONTROL_1)) & 0xffffff00))
++#define SET_RG_TX_Q_SCALE(_VAL_) (REG32(ADR_TX_IQ_CONTROL_1)) = (((_VAL_) << 8) | ((REG32(ADR_TX_IQ_CONTROL_1)) & 0xffff00ff))
++#define SET_RG_TX_IQ_SWP(_VAL_) (REG32(ADR_TX_IQ_CONTROL_1)) = (((_VAL_) << 16) | ((REG32(ADR_TX_IQ_CONTROL_1)) & 0xfffeffff))
++#define SET_RG_TX_SGN_OUT(_VAL_) (REG32(ADR_TX_IQ_CONTROL_1)) = (((_VAL_) << 17) | ((REG32(ADR_TX_IQ_CONTROL_1)) & 0xfffdffff))
++#define SET_RG_TXIQ_EMU_IDX(_VAL_) (REG32(ADR_TX_IQ_CONTROL_1)) = (((_VAL_) << 18) | ((REG32(ADR_TX_IQ_CONTROL_1)) & 0xffc3ffff))
++#define SET_RG_TX_IQ_SRC(_VAL_) (REG32(ADR_TX_IQ_CONTROL_1)) = (((_VAL_) << 24) | ((REG32(ADR_TX_IQ_CONTROL_1)) & 0xfcffffff))
++#define SET_RG_TX_I_DC(_VAL_) (REG32(ADR_TX_IQ_CONTROL_2)) = (((_VAL_) << 0) | ((REG32(ADR_TX_IQ_CONTROL_2)) & 0xfffffc00))
++#define SET_RG_TX_Q_DC(_VAL_) (REG32(ADR_TX_IQ_CONTROL_2)) = (((_VAL_) << 16) | ((REG32(ADR_TX_IQ_CONTROL_2)) & 0xfc00ffff))
++#define SET_RG_TX_IQ_THETA(_VAL_) (REG32(ADR_TX_COMPENSATION_CONTROL)) = (((_VAL_) << 0) | ((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0xffffffe0))
++#define SET_RG_TX_IQ_ALPHA(_VAL_) (REG32(ADR_TX_COMPENSATION_CONTROL)) = (((_VAL_) << 8) | ((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0xffffe0ff))
++#define SET_RG_TXIQ_NOSHRINK(_VAL_) (REG32(ADR_TX_COMPENSATION_CONTROL)) = (((_VAL_) << 13) | ((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0xffffdfff))
++#define SET_RG_TX_I_OFFSET(_VAL_) (REG32(ADR_TX_COMPENSATION_CONTROL)) = (((_VAL_) << 16) | ((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0xff00ffff))
++#define SET_RG_TX_Q_OFFSET(_VAL_) (REG32(ADR_TX_COMPENSATION_CONTROL)) = (((_VAL_) << 24) | ((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0x00ffffff))
++#define SET_RG_RX_IQ_THETA(_VAL_) (REG32(ADR_RX_COMPENSATION_CONTROL)) = (((_VAL_) << 0) | ((REG32(ADR_RX_COMPENSATION_CONTROL)) & 0xffffffe0))
++#define SET_RG_RX_IQ_ALPHA(_VAL_) (REG32(ADR_RX_COMPENSATION_CONTROL)) = (((_VAL_) << 8) | ((REG32(ADR_RX_COMPENSATION_CONTROL)) & 0xffffe0ff))
++#define SET_RG_RXIQ_NOSHRINK(_VAL_) (REG32(ADR_RX_COMPENSATION_CONTROL)) = (((_VAL_) << 13) | ((REG32(ADR_RX_COMPENSATION_CONTROL)) & 0xffffdfff))
++#define SET_RG_MA_DPTH(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xfffffff0))
++#define SET_RG_INTG_PH(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 4) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xfffffc0f))
++#define SET_RG_INTG_PRD(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 10) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xffffe3ff))
++#define SET_RG_INTG_MU(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 13) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xffff9fff))
++#define SET_RG_IQCAL_SPRM_SELQ(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xfffeffff))
++#define SET_RG_IQCAL_SPRM_EN(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 17) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xfffdffff))
++#define SET_RG_IQCAL_SPRM_FREQ(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 18) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xff03ffff))
++#define SET_RG_IQCAL_IQCOL_EN(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 24) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xfeffffff))
++#define SET_RG_IQCAL_ALPHA_ESTM_EN(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 25) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xfdffffff))
++#define SET_RG_IQCAL_DC_EN(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 26) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xfbffffff))
++#define SET_RG_PHEST_STBY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 27) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xf7ffffff))
++#define SET_RG_PHEST_EN(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 28) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xefffffff))
++#define SET_RG_GP_DIV_EN(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 29) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xdfffffff))
++#define SET_RG_DPD_GAIN_EST_EN(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 30) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xbfffffff))
++#define SET_RG_IQCAL_MULT_OP0(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_1)) & 0xfffffc00))
++#define SET_RG_IQCAL_MULT_OP1(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_1)) & 0xfc00ffff))
++#define SET_RO_IQCAL_O(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 0) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xfff00000))
++#define SET_RO_IQCAL_SPRM_RDY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 20) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xffefffff))
++#define SET_RO_IQCAL_IQCOL_RDY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 21) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xffdfffff))
++#define SET_RO_IQCAL_ALPHA_ESTM_RDY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 22) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xffbfffff))
++#define SET_RO_IQCAL_DC_RDY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 23) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xff7fffff))
++#define SET_RO_IQCAL_MULT_RDY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 24) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xfeffffff))
++#define SET_RO_FFT_ENRG_RDY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 25) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xfdffffff))
++#define SET_RO_PHEST_RDY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 26) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xfbffffff))
++#define SET_RO_GP_DIV_RDY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 27) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xf7ffffff))
++#define SET_RO_GAIN_EST_RDY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 28) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xefffffff))
++#define SET_RO_AMP_O(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_3)) = (((_VAL_) << 0) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_3)) & 0xfffffe00))
++#define SET_RG_RX_I_SCALE(_VAL_) (REG32(ADR_RF_IQ_CONTROL_0)) = (((_VAL_) << 0) | ((REG32(ADR_RF_IQ_CONTROL_0)) & 0xffffff00))
++#define SET_RG_RX_Q_SCALE(_VAL_) (REG32(ADR_RF_IQ_CONTROL_0)) = (((_VAL_) << 8) | ((REG32(ADR_RF_IQ_CONTROL_0)) & 0xffff00ff))
++#define SET_RG_RX_I_OFFSET(_VAL_) (REG32(ADR_RF_IQ_CONTROL_0)) = (((_VAL_) << 16) | ((REG32(ADR_RF_IQ_CONTROL_0)) & 0xff00ffff))
++#define SET_RG_RX_Q_OFFSET(_VAL_) (REG32(ADR_RF_IQ_CONTROL_0)) = (((_VAL_) << 24) | ((REG32(ADR_RF_IQ_CONTROL_0)) & 0x00ffffff))
++#define SET_RG_RX_IQ_SWP(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 0) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0xfffffffe))
++#define SET_RG_RX_SGN_IN(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 1) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0xfffffffd))
++#define SET_RG_RX_IQ_SRC(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 2) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0xfffffff3))
++#define SET_RG_ACI_GAIN(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 4) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0xfffff00f))
++#define SET_RG_FFT_EN(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 12) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0xffffefff))
++#define SET_RG_FFT_MOD(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 13) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0xffffdfff))
++#define SET_RG_FFT_SCALE(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 14) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0xff003fff))
++#define SET_RG_FFT_ENRG_FREQ(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 24) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0xc0ffffff))
++#define SET_RG_FPGA_80M_PH_UP(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 30) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0xbfffffff))
++#define SET_RG_FPGA_80M_PH_STP(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 31) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0x7fffffff))
++#define SET_RG_ADC2LA_SEL(_VAL_) (REG32(ADR_RF_IQ_CONTROL_2)) = (((_VAL_) << 0) | ((REG32(ADR_RF_IQ_CONTROL_2)) & 0xfffffffe))
++#define SET_RG_ADC2LA_CLKPH(_VAL_) (REG32(ADR_RF_IQ_CONTROL_2)) = (((_VAL_) << 1) | ((REG32(ADR_RF_IQ_CONTROL_2)) & 0xfffffffd))
++#define SET_RG_RXIQ_EMU_IDX(_VAL_) (REG32(ADR_RF_IQ_CONTROL_3)) = (((_VAL_) << 0) | ((REG32(ADR_RF_IQ_CONTROL_3)) & 0xfffffff0))
++#define SET_RG_IQCAL_BP_ACI(_VAL_) (REG32(ADR_RF_IQ_CONTROL_3)) = (((_VAL_) << 4) | ((REG32(ADR_RF_IQ_CONTROL_3)) & 0xffffffef))
++#define SET_RG_DPD_AM_EN(_VAL_) (REG32(ADR_DPD_CONTROL)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_CONTROL)) & 0xfffffffe))
++#define SET_RG_DPD_PM_EN(_VAL_) (REG32(ADR_DPD_CONTROL)) = (((_VAL_) << 1) | ((REG32(ADR_DPD_CONTROL)) & 0xfffffffd))
++#define SET_RG_DPD_PM_AMSEL(_VAL_) (REG32(ADR_DPD_CONTROL)) = (((_VAL_) << 2) | ((REG32(ADR_DPD_CONTROL)) & 0xfffffffb))
++#define SET_RG_DPD_020_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_0)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_0)) & 0xfffffc00))
++#define SET_RG_DPD_040_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_0)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_0)) & 0xfc00ffff))
++#define SET_RG_DPD_060_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_1)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_1)) & 0xfffffc00))
++#define SET_RG_DPD_080_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_1)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_1)) & 0xfc00ffff))
++#define SET_RG_DPD_0A0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_2)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_2)) & 0xfffffc00))
++#define SET_RG_DPD_0C0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_2)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_2)) & 0xfc00ffff))
++#define SET_RG_DPD_0D0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_3)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_3)) & 0xfffffc00))
++#define SET_RG_DPD_0E0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_3)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_3)) & 0xfc00ffff))
++#define SET_RG_DPD_0F0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_4)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_4)) & 0xfffffc00))
++#define SET_RG_DPD_100_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_4)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_4)) & 0xfc00ffff))
++#define SET_RG_DPD_110_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_5)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_5)) & 0xfffffc00))
++#define SET_RG_DPD_120_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_5)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_5)) & 0xfc00ffff))
++#define SET_RG_DPD_130_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_6)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_6)) & 0xfffffc00))
++#define SET_RG_DPD_140_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_6)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_6)) & 0xfc00ffff))
++#define SET_RG_DPD_150_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_7)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_7)) & 0xfffffc00))
++#define SET_RG_DPD_160_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_7)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_7)) & 0xfc00ffff))
++#define SET_RG_DPD_170_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_8)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_8)) & 0xfffffc00))
++#define SET_RG_DPD_180_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_8)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_8)) & 0xfc00ffff))
++#define SET_RG_DPD_190_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_9)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_9)) & 0xfffffc00))
++#define SET_RG_DPD_1A0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_9)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_9)) & 0xfc00ffff))
++#define SET_RG_DPD_1B0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_A)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_A)) & 0xfffffc00))
++#define SET_RG_DPD_1C0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_A)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_A)) & 0xfc00ffff))
++#define SET_RG_DPD_1D0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_B)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_B)) & 0xfffffc00))
++#define SET_RG_DPD_1E0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_B)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_B)) & 0xfc00ffff))
++#define SET_RG_DPD_1F0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_C)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_C)) & 0xfffffc00))
++#define SET_RG_DPD_200_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_C)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_C)) & 0xfc00ffff))
++#define SET_RG_DPD_020_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_0)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_0)) & 0xffffe000))
++#define SET_RG_DPD_040_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_0)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_0)) & 0xe000ffff))
++#define SET_RG_DPD_060_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_1)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_1)) & 0xffffe000))
++#define SET_RG_DPD_080_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_1)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_1)) & 0xe000ffff))
++#define SET_RG_DPD_0A0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_2)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_2)) & 0xffffe000))
++#define SET_RG_DPD_0C0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_2)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_2)) & 0xe000ffff))
++#define SET_RG_DPD_0D0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_3)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_3)) & 0xffffe000))
++#define SET_RG_DPD_0E0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_3)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_3)) & 0xe000ffff))
++#define SET_RG_DPD_0F0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_4)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_4)) & 0xffffe000))
++#define SET_RG_DPD_100_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_4)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_4)) & 0xe000ffff))
++#define SET_RG_DPD_110_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_5)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_5)) & 0xffffe000))
++#define SET_RG_DPD_120_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_5)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_5)) & 0xe000ffff))
++#define SET_RG_DPD_130_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_6)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_6)) & 0xffffe000))
++#define SET_RG_DPD_140_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_6)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_6)) & 0xe000ffff))
++#define SET_RG_DPD_150_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_7)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_7)) & 0xffffe000))
++#define SET_RG_DPD_160_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_7)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_7)) & 0xe000ffff))
++#define SET_RG_DPD_170_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_8)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_8)) & 0xffffe000))
++#define SET_RG_DPD_180_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_8)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_8)) & 0xe000ffff))
++#define SET_RG_DPD_190_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_9)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_9)) & 0xffffe000))
++#define SET_RG_DPD_1A0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_9)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_9)) & 0xe000ffff))
++#define SET_RG_DPD_1B0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_A)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_A)) & 0xffffe000))
++#define SET_RG_DPD_1C0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_A)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_A)) & 0xe000ffff))
++#define SET_RG_DPD_1D0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_B)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_B)) & 0xffffe000))
++#define SET_RG_DPD_1E0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_B)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_B)) & 0xe000ffff))
++#define SET_RG_DPD_1F0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_C)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_C)) & 0xffffe000))
++#define SET_RG_DPD_200_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_C)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_C)) & 0xe000ffff))
++#define SET_RG_DPD_GAIN_EST_Y0(_VAL_) (REG32(ADR_DPD_GAIN_ESTIMATION_0)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_ESTIMATION_0)) & 0xfffffe00))
++#define SET_RG_DPD_GAIN_EST_Y1(_VAL_) (REG32(ADR_DPD_GAIN_ESTIMATION_0)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_ESTIMATION_0)) & 0xfe00ffff))
++#define SET_RG_DPD_LOOP_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_ESTIMATION_1)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_ESTIMATION_1)) & 0xfffffc00))
++#define SET_RG_DPD_GAIN_EST_X0(_VAL_) (REG32(ADR_DPD_GAIN_ESTIMATION_2)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_ESTIMATION_2)) & 0xfffffe00))
++#define SET_RO_DPD_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_ESTIMATION_2)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_ESTIMATION_2)) & 0xfc00ffff))
++#define SET_TX_SCALE_11B(_VAL_) (REG32(ADR_TX_GAIN_FACTOR)) = (((_VAL_) << 0) | ((REG32(ADR_TX_GAIN_FACTOR)) & 0xffffff00))
++#define SET_TX_SCALE_11B_P0D5(_VAL_) (REG32(ADR_TX_GAIN_FACTOR)) = (((_VAL_) << 8) | ((REG32(ADR_TX_GAIN_FACTOR)) & 0xffff00ff))
++#define SET_TX_SCALE_11G(_VAL_) (REG32(ADR_TX_GAIN_FACTOR)) = (((_VAL_) << 16) | ((REG32(ADR_TX_GAIN_FACTOR)) & 0xff00ffff))
++#define SET_TX_SCALE_11G_P0D5(_VAL_) (REG32(ADR_TX_GAIN_FACTOR)) = (((_VAL_) << 24) | ((REG32(ADR_TX_GAIN_FACTOR)) & 0x00ffffff))
++#define SET_RG_EN_MANUAL(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfffffffe))
++#define SET_RG_TX_EN(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfffffffd))
++#define SET_RG_TX_PA_EN(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfffffffb))
++#define SET_RG_TX_DAC_EN(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfffffff7))
++#define SET_RG_RX_AGC(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xffffffef))
++#define SET_RG_RX_GAIN_MANUAL(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xffffffdf))
++#define SET_RG_RFG(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xffffff3f))
++#define SET_RG_PGAG(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfffff0ff))
++#define SET_RG_MODE(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xffffcfff))
++#define SET_RG_EN_TX_TRSW(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xffffbfff))
++#define SET_RG_EN_SX(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 15) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xffff7fff))
++#define SET_RG_EN_RX_LNA(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfffeffff))
++#define SET_RG_EN_RX_MIXER(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 17) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfffdffff))
++#define SET_RG_EN_RX_DIV2(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfffbffff))
++#define SET_RG_EN_RX_LOBUF(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 19) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfff7ffff))
++#define SET_RG_EN_RX_TZ(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 20) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xffefffff))
++#define SET_RG_EN_RX_FILTER(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xffdfffff))
++#define SET_RG_EN_RX_HPF(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 22) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xffbfffff))
++#define SET_RG_EN_RX_RSSI(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 23) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xff7fffff))
++#define SET_RG_EN_ADC(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 24) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfeffffff))
++#define SET_RG_EN_TX_MOD(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 25) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfdffffff))
++#define SET_RG_EN_TX_DIV2(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 26) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfbffffff))
++#define SET_RG_EN_TX_DIV2_BUF(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 27) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xf7ffffff))
++#define SET_RG_EN_TX_LOBF(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 28) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xefffffff))
++#define SET_RG_EN_RX_LOBF(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 29) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xdfffffff))
++#define SET_RG_SEL_DPLL_CLK(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 30) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xbfffffff))
++#define SET_RG_EN_CLK_960MBY13_UART(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 31) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x7fffffff))
++#define SET_RG_EN_TX_DPD(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffffffe))
++#define SET_RG_EN_TX_TSSI(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffffffd))
++#define SET_RG_EN_RX_IQCAL(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffffffb))
++#define SET_RG_EN_TX_DAC_CAL(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffffff7))
++#define SET_RG_EN_TX_SELF_MIXER(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xffffffef))
++#define SET_RG_EN_TX_DAC_OUT(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xffffffdf))
++#define SET_RG_EN_LDO_RX_FE(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xffffffbf))
++#define SET_RG_EN_LDO_ABB(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 7) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xffffff7f))
++#define SET_RG_EN_LDO_AFE(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffffeff))
++#define SET_RG_EN_SX_CHPLDO(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffffdff))
++#define SET_RG_EN_SX_LOBFLDO(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 10) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffffbff))
++#define SET_RG_EN_IREF_RX(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffff7ff))
++#define SET_RG_EN_TX_DAC_VOUT(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 13) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xffffdfff))
++#define SET_RG_EN_SX_LCK_BIN(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xffffbfff))
++#define SET_RG_RTC_CAL_MODE(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffeffff))
++#define SET_RG_EN_IQPAD_IOSW(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 17) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffdffff))
++#define SET_RG_EN_TESTPAD_IOSW(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffbffff))
++#define SET_RG_EN_TRXBF_BYPASS(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 19) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfff7ffff))
++#define SET_RG_LDO_LEVEL_RX_FE(_VAL_) (REG32(ADR_LDO_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_LDO_REGISTER)) & 0xfffffff8))
++#define SET_RG_LDO_LEVEL_ABB(_VAL_) (REG32(ADR_LDO_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_LDO_REGISTER)) & 0xffffffc7))
++#define SET_RG_LDO_LEVEL_AFE(_VAL_) (REG32(ADR_LDO_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_LDO_REGISTER)) & 0xfffffe3f))
++#define SET_RG_SX_LDO_CHP_LEVEL(_VAL_) (REG32(ADR_LDO_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_LDO_REGISTER)) & 0xfffff1ff))
++#define SET_RG_SX_LDO_LOBF_LEVEL(_VAL_) (REG32(ADR_LDO_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_LDO_REGISTER)) & 0xffff8fff))
++#define SET_RG_SX_LDO_XOSC_LEVEL(_VAL_) (REG32(ADR_LDO_REGISTER)) = (((_VAL_) << 15) | ((REG32(ADR_LDO_REGISTER)) & 0xfffc7fff))
++#define SET_RG_DP_LDO_LEVEL(_VAL_) (REG32(ADR_LDO_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_LDO_REGISTER)) & 0xffe3ffff))
++#define SET_RG_SX_LDO_VCO_LEVEL(_VAL_) (REG32(ADR_LDO_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_LDO_REGISTER)) & 0xff1fffff))
++#define SET_RG_TX_LDO_TX_LEVEL(_VAL_) (REG32(ADR_LDO_REGISTER)) = (((_VAL_) << 24) | ((REG32(ADR_LDO_REGISTER)) & 0xf8ffffff))
++#define SET_RG_EN_RX_PADSW(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 0) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfffffffe))
++#define SET_RG_EN_RX_TESTNODE(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 1) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfffffffd))
++#define SET_RG_RX_ABBCFIX(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 2) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfffffffb))
++#define SET_RG_RX_ABBCTUNE(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 3) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfffffe07))
++#define SET_RG_RX_ABBOUT_TRI_STATE(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 9) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfffffdff))
++#define SET_RG_RX_ABB_N_MODE(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 10) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfffffbff))
++#define SET_RG_RX_EN_LOOPA(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 11) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfffff7ff))
++#define SET_RG_RX_FILTERI1ST(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 12) | ((REG32(ADR_ABB_REGISTER_1)) & 0xffffcfff))
++#define SET_RG_RX_FILTERI2ND(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 14) | ((REG32(ADR_ABB_REGISTER_1)) & 0xffff3fff))
++#define SET_RG_RX_FILTERI3RD(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 16) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfffcffff))
++#define SET_RG_RX_FILTERI_COURSE(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 18) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfff3ffff))
++#define SET_RG_RX_FILTERVCM(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 20) | ((REG32(ADR_ABB_REGISTER_1)) & 0xffcfffff))
++#define SET_RG_RX_HPF3M(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 22) | ((REG32(ADR_ABB_REGISTER_1)) & 0xffbfffff))
++#define SET_RG_RX_HPF300K(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 23) | ((REG32(ADR_ABB_REGISTER_1)) & 0xff7fffff))
++#define SET_RG_RX_HPFI(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 24) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfcffffff))
++#define SET_RG_RX_HPF_FINALCORNER(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 26) | ((REG32(ADR_ABB_REGISTER_1)) & 0xf3ffffff))
++#define SET_RG_RX_HPF_SETTLE1_C(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 28) | ((REG32(ADR_ABB_REGISTER_1)) & 0xcfffffff))
++#define SET_RG_RX_HPF_SETTLE1_R(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 0) | ((REG32(ADR_ABB_REGISTER_2)) & 0xfffffffc))
++#define SET_RG_RX_HPF_SETTLE2_C(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 2) | ((REG32(ADR_ABB_REGISTER_2)) & 0xfffffff3))
++#define SET_RG_RX_HPF_SETTLE2_R(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 4) | ((REG32(ADR_ABB_REGISTER_2)) & 0xffffffcf))
++#define SET_RG_RX_HPF_VCMCON2(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 6) | ((REG32(ADR_ABB_REGISTER_2)) & 0xffffff3f))
++#define SET_RG_RX_HPF_VCMCON(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 8) | ((REG32(ADR_ABB_REGISTER_2)) & 0xfffffcff))
++#define SET_RG_RX_OUTVCM(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 10) | ((REG32(ADR_ABB_REGISTER_2)) & 0xfffff3ff))
++#define SET_RG_RX_TZI(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 12) | ((REG32(ADR_ABB_REGISTER_2)) & 0xffffcfff))
++#define SET_RG_RX_TZ_OUT_TRISTATE(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 14) | ((REG32(ADR_ABB_REGISTER_2)) & 0xffffbfff))
++#define SET_RG_RX_TZ_VCM(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 15) | ((REG32(ADR_ABB_REGISTER_2)) & 0xfffe7fff))
++#define SET_RG_EN_RX_RSSI_TESTNODE(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 17) | ((REG32(ADR_ABB_REGISTER_2)) & 0xfff1ffff))
++#define SET_RG_RX_ADCRSSI_CLKSEL(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 20) | ((REG32(ADR_ABB_REGISTER_2)) & 0xffefffff))
++#define SET_RG_RX_ADCRSSI_VCM(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 21) | ((REG32(ADR_ABB_REGISTER_2)) & 0xff9fffff))
++#define SET_RG_RX_REC_LPFCORNER(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 23) | ((REG32(ADR_ABB_REGISTER_2)) & 0xfe7fffff))
++#define SET_RG_RSSI_CLOCK_GATING(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 25) | ((REG32(ADR_ABB_REGISTER_2)) & 0xfdffffff))
++#define SET_RG_TXPGA_CAPSW(_VAL_) (REG32(ADR_TX_FE_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_TX_FE_REGISTER)) & 0xfffffffc))
++#define SET_RG_TXPGA_MAIN(_VAL_) (REG32(ADR_TX_FE_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_TX_FE_REGISTER)) & 0xffffff03))
++#define SET_RG_TXPGA_STEER(_VAL_) (REG32(ADR_TX_FE_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_TX_FE_REGISTER)) & 0xffffc0ff))
++#define SET_RG_TXMOD_GMCELL(_VAL_) (REG32(ADR_TX_FE_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_TX_FE_REGISTER)) & 0xffff3fff))
++#define SET_RG_TXLPF_GMCELL(_VAL_) (REG32(ADR_TX_FE_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_TX_FE_REGISTER)) & 0xfffcffff))
++#define SET_RG_PACELL_EN(_VAL_) (REG32(ADR_TX_FE_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_TX_FE_REGISTER)) & 0xffe3ffff))
++#define SET_RG_PABIAS_CTRL(_VAL_) (REG32(ADR_TX_FE_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_TX_FE_REGISTER)) & 0xfe1fffff))
++#define SET_RG_TX_DIV_VSET(_VAL_) (REG32(ADR_TX_FE_REGISTER)) = (((_VAL_) << 26) | ((REG32(ADR_TX_FE_REGISTER)) & 0xf3ffffff))
++#define SET_RG_TX_LOBUF_VSET(_VAL_) (REG32(ADR_TX_FE_REGISTER)) = (((_VAL_) << 28) | ((REG32(ADR_TX_FE_REGISTER)) & 0xcfffffff))
++#define SET_RG_RX_SQDC(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xfffffff8))
++#define SET_RG_RX_DIV2_CORE(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 3) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xffffffe7))
++#define SET_RG_RX_LOBUF(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 5) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xffffff9f))
++#define SET_RG_TX_DPDGM_BIAS(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 7) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xfffff87f))
++#define SET_RG_TX_DPD_DIV(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 11) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xffff87ff))
++#define SET_RG_TX_TSSI_BIAS(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 15) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xfffc7fff))
++#define SET_RG_TX_TSSI_DIV(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 18) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xffe3ffff))
++#define SET_RG_TX_TSSI_TESTMODE(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 21) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xffdfffff))
++#define SET_RG_TX_TSSI_TEST(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 22) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xff3fffff))
++#define SET_RG_PACASCODE_CTRL(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 24) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xf8ffffff))
++#define SET_RG_RX_HG_LNA_GC(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xfffffffc))
++#define SET_RG_RX_HG_LNAHGN_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 2) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xffffffc3))
++#define SET_RG_RX_HG_LNAHGP_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 6) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xfffffc3f))
++#define SET_RG_RX_HG_LNALG_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 10) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xffffc3ff))
++#define SET_RG_RX_HG_TZ_GC(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 14) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xffff3fff))
++#define SET_RG_RX_HG_TZ_CAP(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xfff8ffff))
++#define SET_RG_RX_MG_LNA_GC(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 0) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xfffffffc))
++#define SET_RG_RX_MG_LNAHGN_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 2) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xffffffc3))
++#define SET_RG_RX_MG_LNAHGP_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 6) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xfffffc3f))
++#define SET_RG_RX_MG_LNALG_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 10) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xffffc3ff))
++#define SET_RG_RX_MG_TZ_GC(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 14) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xffff3fff))
++#define SET_RG_RX_MG_TZ_CAP(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 16) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xfff8ffff))
++#define SET_RG_RX_LG_LNA_GC(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 0) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xfffffffc))
++#define SET_RG_RX_LG_LNAHGN_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 2) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xffffffc3))
++#define SET_RG_RX_LG_LNAHGP_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 6) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xfffffc3f))
++#define SET_RG_RX_LG_LNALG_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 10) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xffffc3ff))
++#define SET_RG_RX_LG_TZ_GC(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 14) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xffff3fff))
++#define SET_RG_RX_LG_TZ_CAP(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 16) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xfff8ffff))
++#define SET_RG_RX_ULG_LNA_GC(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 0) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xfffffffc))
++#define SET_RG_RX_ULG_LNAHGN_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 2) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xffffffc3))
++#define SET_RG_RX_ULG_LNAHGP_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 6) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xfffffc3f))
++#define SET_RG_RX_ULG_LNALG_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 10) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xffffc3ff))
++#define SET_RG_RX_ULG_TZ_GC(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 14) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xffff3fff))
++#define SET_RG_RX_ULG_TZ_CAP(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 16) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xfff8ffff))
++#define SET_RG_HPF1_FAST_SET_X(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xfffffffe))
++#define SET_RG_HPF1_FAST_SET_Y(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xfffffffd))
++#define SET_RG_HPF1_FAST_SET_Z(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xfffffffb))
++#define SET_RG_HPF_T1A(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xffffffe7))
++#define SET_RG_HPF_T1B(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xffffff9f))
++#define SET_RG_HPF_T1C(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 7) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xfffffe7f))
++#define SET_RG_RX_LNA_TRI_SEL(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xfffff9ff))
++#define SET_RG_RX_LNA_SETTLE(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xffffe7ff))
++#define SET_RG_TXGAIN_PHYCTRL(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 13) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xffffdfff))
++#define SET_RG_TX_GAIN(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xffc03fff))
++#define SET_RG_TXGAIN_MANUAL(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 22) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xffbfffff))
++#define SET_RG_TX_GAIN_OFFSET(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 23) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xf87fffff))
++#define SET_RG_ADC_CLKSEL(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfffffffe))
++#define SET_RG_ADC_DIBIAS(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfffffff9))
++#define SET_RG_ADC_DIVR(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfffffff7))
++#define SET_RG_ADC_DVCMI(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xffffffcf))
++#define SET_RG_ADC_SAMSEL(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfffffc3f))
++#define SET_RG_ADC_STNBY(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 10) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfffffbff))
++#define SET_RG_ADC_TESTMODE(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfffff7ff))
++#define SET_RG_ADC_TSEL(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xffff0fff))
++#define SET_RG_ADC_VRSEL(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfffcffff))
++#define SET_RG_DICMP(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfff3ffff))
++#define SET_RG_DIOP(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 20) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xffcfffff))
++#define SET_RG_SARADC_VRSEL(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 22) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xff3fffff))
++#define SET_RG_EN_SAR_TEST(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 24) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfcffffff))
++#define SET_RG_SARADC_THERMAL(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 26) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfbffffff))
++#define SET_RG_SARADC_TSSI(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 27) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xf7ffffff))
++#define SET_RG_CLK_SAR_SEL(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 28) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xcfffffff))
++#define SET_RG_EN_SARADC(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 30) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xbfffffff))
++#define SET_RG_DACI1ST(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xfffffffc))
++#define SET_RG_TX_DACLPF_ICOURSE(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xfffffff3))
++#define SET_RG_TX_DACLPF_IFINE(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xffffffcf))
++#define SET_RG_TX_DACLPF_VCM(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xffffff3f))
++#define SET_RG_TX_DAC_CKEDGE_SEL(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xfffffeff))
++#define SET_RG_TX_DAC_IBIAS(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xfffff9ff))
++#define SET_RG_TX_DAC_OS(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xffffc7ff))
++#define SET_RG_TX_DAC_RCAL(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xffff3fff))
++#define SET_RG_TX_DAC_TSEL(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xfff0ffff))
++#define SET_RG_TX_EN_VOLTAGE_IN(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 20) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xffefffff))
++#define SET_RG_TXLPF_BYPASS(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xffdfffff))
++#define SET_RG_TXLPF_BOOSTI(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 22) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xffbfffff))
++#define SET_RG_TX_DAC_IOFFSET(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 23) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xf87fffff))
++#define SET_RG_TX_DAC_QOFFSET(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 27) | ((REG32(ADR_TX_DAC_REGISTER)) & 0x87ffffff))
++#define SET_RG_EN_SX_R3(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xfffffffe))
++#define SET_RG_EN_SX_CH(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xfffffffd))
++#define SET_RG_EN_SX_CHP(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xfffffffb))
++#define SET_RG_EN_SX_DIVCK(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xfffffff7))
++#define SET_RG_EN_SX_VCOBF(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xffffffef))
++#define SET_RG_EN_SX_VCO(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xffffffdf))
++#define SET_RG_EN_SX_MOD(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xffffffbf))
++#define SET_RG_EN_SX_DITHER(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xfffffeff))
++#define SET_RG_EN_SX_VT_MON(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xfffff7ff))
++#define SET_RG_EN_SX_VT_MON_DG(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xffffefff))
++#define SET_RG_EN_SX_DIV(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 13) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xffffdfff))
++#define SET_RG_EN_SX_LPF(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xffffbfff))
++#define SET_RG_EN_DPL_MOD(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 15) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xffff7fff))
++#define SET_RG_DPL_MOD_ORDER(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xfffcffff))
++#define SET_RG_SX_RFCTRL_F(_VAL_) (REG32(ADR_SYN_REGISTER_1)) = (((_VAL_) << 0) | ((REG32(ADR_SYN_REGISTER_1)) & 0xff000000))
++#define SET_RG_SX_SEL_CP(_VAL_) (REG32(ADR_SYN_REGISTER_1)) = (((_VAL_) << 24) | ((REG32(ADR_SYN_REGISTER_1)) & 0xf0ffffff))
++#define SET_RG_SX_SEL_CS(_VAL_) (REG32(ADR_SYN_REGISTER_1)) = (((_VAL_) << 28) | ((REG32(ADR_SYN_REGISTER_1)) & 0x0fffffff))
++#define SET_RG_SX_RFCTRL_CH(_VAL_) (REG32(ADR_SYN_REGISTER_2)) = (((_VAL_) << 0) | ((REG32(ADR_SYN_REGISTER_2)) & 0xfffff800))
++#define SET_RG_SX_SEL_C3(_VAL_) (REG32(ADR_SYN_REGISTER_2)) = (((_VAL_) << 11) | ((REG32(ADR_SYN_REGISTER_2)) & 0xffff87ff))
++#define SET_RG_SX_SEL_RS(_VAL_) (REG32(ADR_SYN_REGISTER_2)) = (((_VAL_) << 15) | ((REG32(ADR_SYN_REGISTER_2)) & 0xfff07fff))
++#define SET_RG_SX_SEL_R3(_VAL_) (REG32(ADR_SYN_REGISTER_2)) = (((_VAL_) << 20) | ((REG32(ADR_SYN_REGISTER_2)) & 0xfe0fffff))
++#define SET_RG_SX_SEL_ICHP(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 0) | ((REG32(ADR_SYN_PFD_CHP)) & 0xffffffe0))
++#define SET_RG_SX_SEL_PCHP(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 5) | ((REG32(ADR_SYN_PFD_CHP)) & 0xfffffc1f))
++#define SET_RG_SX_SEL_CHP_REGOP(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 10) | ((REG32(ADR_SYN_PFD_CHP)) & 0xffffc3ff))
++#define SET_RG_SX_SEL_CHP_UNIOP(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 14) | ((REG32(ADR_SYN_PFD_CHP)) & 0xfffc3fff))
++#define SET_RG_SX_CHP_IOST_POL(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 18) | ((REG32(ADR_SYN_PFD_CHP)) & 0xfffbffff))
++#define SET_RG_SX_CHP_IOST(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 19) | ((REG32(ADR_SYN_PFD_CHP)) & 0xffc7ffff))
++#define SET_RG_SX_PFDSEL(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 22) | ((REG32(ADR_SYN_PFD_CHP)) & 0xffbfffff))
++#define SET_RG_SX_PFD_SET(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 23) | ((REG32(ADR_SYN_PFD_CHP)) & 0xff7fffff))
++#define SET_RG_SX_PFD_SET1(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 24) | ((REG32(ADR_SYN_PFD_CHP)) & 0xfeffffff))
++#define SET_RG_SX_PFD_SET2(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 25) | ((REG32(ADR_SYN_PFD_CHP)) & 0xfdffffff))
++#define SET_RG_SX_VBNCAS_SEL(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 26) | ((REG32(ADR_SYN_PFD_CHP)) & 0xfbffffff))
++#define SET_RG_SX_PFD_RST_H(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 27) | ((REG32(ADR_SYN_PFD_CHP)) & 0xf7ffffff))
++#define SET_RG_SX_PFD_TRUP(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 28) | ((REG32(ADR_SYN_PFD_CHP)) & 0xefffffff))
++#define SET_RG_SX_PFD_TRDN(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 29) | ((REG32(ADR_SYN_PFD_CHP)) & 0xdfffffff))
++#define SET_RG_SX_PFD_TRSEL(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 30) | ((REG32(ADR_SYN_PFD_CHP)) & 0xbfffffff))
++#define SET_RG_SX_VCOBA_R(_VAL_) (REG32(ADR_SYN_VCO_LOBF)) = (((_VAL_) << 0) | ((REG32(ADR_SYN_VCO_LOBF)) & 0xfffffff8))
++#define SET_RG_SX_VCORSEL(_VAL_) (REG32(ADR_SYN_VCO_LOBF)) = (((_VAL_) << 3) | ((REG32(ADR_SYN_VCO_LOBF)) & 0xffffff07))
++#define SET_RG_SX_VCOCUSEL(_VAL_) (REG32(ADR_SYN_VCO_LOBF)) = (((_VAL_) << 8) | ((REG32(ADR_SYN_VCO_LOBF)) & 0xfffff0ff))
++#define SET_RG_SX_RXBFSEL(_VAL_) (REG32(ADR_SYN_VCO_LOBF)) = (((_VAL_) << 12) | ((REG32(ADR_SYN_VCO_LOBF)) & 0xffff0fff))
++#define SET_RG_SX_TXBFSEL(_VAL_) (REG32(ADR_SYN_VCO_LOBF)) = (((_VAL_) << 16) | ((REG32(ADR_SYN_VCO_LOBF)) & 0xfff0ffff))
++#define SET_RG_SX_VCOBFSEL(_VAL_) (REG32(ADR_SYN_VCO_LOBF)) = (((_VAL_) << 20) | ((REG32(ADR_SYN_VCO_LOBF)) & 0xff0fffff))
++#define SET_RG_SX_DIVBFSEL(_VAL_) (REG32(ADR_SYN_VCO_LOBF)) = (((_VAL_) << 24) | ((REG32(ADR_SYN_VCO_LOBF)) & 0xf0ffffff))
++#define SET_RG_SX_GNDR_SEL(_VAL_) (REG32(ADR_SYN_VCO_LOBF)) = (((_VAL_) << 28) | ((REG32(ADR_SYN_VCO_LOBF)) & 0x0fffffff))
++#define SET_RG_SX_DITHER_WEIGHT(_VAL_) (REG32(ADR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 0) | ((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0xfffffffc))
++#define SET_RG_SX_MOD_ORDER(_VAL_) (REG32(ADR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 4) | ((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0xffffffcf))
++#define SET_RG_SX_RST_H_DIV(_VAL_) (REG32(ADR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 9) | ((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0xfffffdff))
++#define SET_RG_SX_SDM_EDGE(_VAL_) (REG32(ADR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 10) | ((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0xfffffbff))
++#define SET_RG_SX_XO_GM(_VAL_) (REG32(ADR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 11) | ((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0xffffe7ff))
++#define SET_RG_SX_REFBYTWO(_VAL_) (REG32(ADR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 13) | ((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0xffffdfff))
++#define SET_RG_SX_LCKEN(_VAL_) (REG32(ADR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 19) | ((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0xfff7ffff))
++#define SET_RG_SX_PREVDD(_VAL_) (REG32(ADR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 20) | ((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0xff0fffff))
++#define SET_RG_SX_PSCONTERVDD(_VAL_) (REG32(ADR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 24) | ((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0xf0ffffff))
++#define SET_RG_SX_PH(_VAL_) (REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) = (((_VAL_) << 13) | ((REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) & 0xffffdfff))
++#define SET_RG_SX_PL(_VAL_) (REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) = (((_VAL_) << 14) | ((REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) & 0xffffbfff))
++#define SET_RG_XOSC_CBANK_XO(_VAL_) (REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) = (((_VAL_) << 15) | ((REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) & 0xfff87fff))
++#define SET_RG_XOSC_CBANK_XI(_VAL_) (REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) = (((_VAL_) << 19) | ((REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) & 0xff87ffff))
++#define SET_RG_SX_VT_MON_MODE(_VAL_) (REG32(ADR_SYN_LCK_VT)) = (((_VAL_) << 0) | ((REG32(ADR_SYN_LCK_VT)) & 0xfffffffe))
++#define SET_RG_SX_VT_TH_HI(_VAL_) (REG32(ADR_SYN_LCK_VT)) = (((_VAL_) << 1) | ((REG32(ADR_SYN_LCK_VT)) & 0xfffffff9))
++#define SET_RG_SX_VT_TH_LO(_VAL_) (REG32(ADR_SYN_LCK_VT)) = (((_VAL_) << 3) | ((REG32(ADR_SYN_LCK_VT)) & 0xffffffe7))
++#define SET_RG_SX_VT_SET(_VAL_) (REG32(ADR_SYN_LCK_VT)) = (((_VAL_) << 5) | ((REG32(ADR_SYN_LCK_VT)) & 0xffffffdf))
++#define SET_RG_SX_VT_MON_TMR(_VAL_) (REG32(ADR_SYN_LCK_VT)) = (((_VAL_) << 6) | ((REG32(ADR_SYN_LCK_VT)) & 0xffff803f))
++#define SET_RG_EN_DP_VT_MON(_VAL_) (REG32(ADR_DPLL_VCO_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_DPLL_VCO_REGISTER)) & 0xfffffffe))
++#define SET_RG_DP_VT_TH_HI(_VAL_) (REG32(ADR_DPLL_VCO_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_DPLL_VCO_REGISTER)) & 0xfffffff9))
++#define SET_RG_DP_VT_TH_LO(_VAL_) (REG32(ADR_DPLL_VCO_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_DPLL_VCO_REGISTER)) & 0xffffffe7))
++#define SET_RG_DP_CK320BY2(_VAL_) (REG32(ADR_DPLL_VCO_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_DPLL_VCO_REGISTER)) & 0xffffbfff))
++#define SET_RG_DP_OD_TEST(_VAL_) (REG32(ADR_DPLL_VCO_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_DPLL_VCO_REGISTER)) & 0xffdfffff))
++#define SET_RG_DP_BBPLL_BP(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0xfffffffe))
++#define SET_RG_DP_BBPLL_ICP(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0xfffffff9))
++#define SET_RG_DP_BBPLL_IDUAL(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0xffffffe7))
++#define SET_RG_DP_BBPLL_OD_TEST(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0xfffffe1f))
++#define SET_RG_DP_BBPLL_PD(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0xfffffdff))
++#define SET_RG_DP_BBPLL_TESTSEL(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 10) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0xffffe3ff))
++#define SET_RG_DP_BBPLL_PFD_DLY(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 13) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0xffff9fff))
++#define SET_RG_DP_RP(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 15) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0xfffc7fff))
++#define SET_RG_DP_RHP(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0xfff3ffff))
++#define SET_RG_DP_BBPLL_SDM_EDGE(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 31) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x7fffffff))
++#define SET_RG_DP_FODIV(_VAL_) (REG32(ADR_DPLL_DIVIDER_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_DPLL_DIVIDER_REGISTER)) & 0xfff80fff))
++#define SET_RG_DP_REFDIV(_VAL_) (REG32(ADR_DPLL_DIVIDER_REGISTER)) = (((_VAL_) << 22) | ((REG32(ADR_DPLL_DIVIDER_REGISTER)) & 0xe03fffff))
++#define SET_RG_IDACAI_PGAG15(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER1)) = (((_VAL_) << 0) | ((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0xffffffc0))
++#define SET_RG_IDACAQ_PGAG15(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER1)) = (((_VAL_) << 6) | ((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0xfffff03f))
++#define SET_RG_IDACAI_PGAG14(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER1)) = (((_VAL_) << 12) | ((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0xfffc0fff))
++#define SET_RG_IDACAQ_PGAG14(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER1)) = (((_VAL_) << 18) | ((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0xff03ffff))
++#define SET_RG_DP_BBPLL_BS(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER1)) = (((_VAL_) << 24) | ((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0xc0ffffff))
++#define SET_RG_IDACAI_PGAG13(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER2)) = (((_VAL_) << 0) | ((REG32(ADR_DCOC_IDAC_REGISTER2)) & 0xffffffc0))
++#define SET_RG_IDACAQ_PGAG13(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER2)) = (((_VAL_) << 6) | ((REG32(ADR_DCOC_IDAC_REGISTER2)) & 0xfffff03f))
++#define SET_RG_IDACAI_PGAG12(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER2)) = (((_VAL_) << 12) | ((REG32(ADR_DCOC_IDAC_REGISTER2)) & 0xfffc0fff))
++#define SET_RG_IDACAQ_PGAG12(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER2)) = (((_VAL_) << 18) | ((REG32(ADR_DCOC_IDAC_REGISTER2)) & 0xff03ffff))
++#define SET_RG_IDACAI_PGAG11(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER3)) = (((_VAL_) << 0) | ((REG32(ADR_DCOC_IDAC_REGISTER3)) & 0xffffffc0))
++#define SET_RG_IDACAQ_PGAG11(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER3)) = (((_VAL_) << 6) | ((REG32(ADR_DCOC_IDAC_REGISTER3)) & 0xfffff03f))
++#define SET_RG_IDACAI_PGAG10(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER3)) = (((_VAL_) << 12) | ((REG32(ADR_DCOC_IDAC_REGISTER3)) & 0xfffc0fff))
++#define SET_RG_IDACAQ_PGAG10(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER3)) = (((_VAL_) << 18) | ((REG32(ADR_DCOC_IDAC_REGISTER3)) & 0xff03ffff))
++#define SET_RG_IDACAI_PGAG9(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER4)) = (((_VAL_) << 0) | ((REG32(ADR_DCOC_IDAC_REGISTER4)) & 0xffffffc0))
++#define SET_RG_IDACAQ_PGAG9(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER4)) = (((_VAL_) << 6) | ((REG32(ADR_DCOC_IDAC_REGISTER4)) & 0xfffff03f))
++#define SET_RG_IDACAI_PGAG8(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER4)) = (((_VAL_) << 12) | ((REG32(ADR_DCOC_IDAC_REGISTER4)) & 0xfffc0fff))
++#define SET_RG_IDACAQ_PGAG8(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER4)) = (((_VAL_) << 18) | ((REG32(ADR_DCOC_IDAC_REGISTER4)) & 0xff03ffff))
++#define SET_RG_IDACAI_PGAG7(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER5)) = (((_VAL_) << 0) | ((REG32(ADR_DCOC_IDAC_REGISTER5)) & 0xffffffc0))
++#define SET_RG_IDACAQ_PGAG7(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER5)) = (((_VAL_) << 6) | ((REG32(ADR_DCOC_IDAC_REGISTER5)) & 0xfffff03f))
++#define SET_RG_IDACAI_PGAG6(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER5)) = (((_VAL_) << 12) | ((REG32(ADR_DCOC_IDAC_REGISTER5)) & 0xfffc0fff))
++#define SET_RG_IDACAQ_PGAG6(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER5)) = (((_VAL_) << 18) | ((REG32(ADR_DCOC_IDAC_REGISTER5)) & 0xff03ffff))
++#define SET_RG_IDACAI_PGAG5(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER6)) = (((_VAL_) << 0) | ((REG32(ADR_DCOC_IDAC_REGISTER6)) & 0xffffffc0))
++#define SET_RG_IDACAQ_PGAG5(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER6)) = (((_VAL_) << 6) | ((REG32(ADR_DCOC_IDAC_REGISTER6)) & 0xfffff03f))
++#define SET_RG_IDACAI_PGAG4(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER6)) = (((_VAL_) << 12) | ((REG32(ADR_DCOC_IDAC_REGISTER6)) & 0xfffc0fff))
++#define SET_RG_IDACAQ_PGAG4(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER6)) = (((_VAL_) << 18) | ((REG32(ADR_DCOC_IDAC_REGISTER6)) & 0xff03ffff))
++#define SET_RG_IDACAI_PGAG3(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER7)) = (((_VAL_) << 0) | ((REG32(ADR_DCOC_IDAC_REGISTER7)) & 0xffffffc0))
++#define SET_RG_IDACAQ_PGAG3(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER7)) = (((_VAL_) << 6) | ((REG32(ADR_DCOC_IDAC_REGISTER7)) & 0xfffff03f))
++#define SET_RG_IDACAI_PGAG2(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER7)) = (((_VAL_) << 12) | ((REG32(ADR_DCOC_IDAC_REGISTER7)) & 0xfffc0fff))
++#define SET_RG_IDACAQ_PGAG2(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER7)) = (((_VAL_) << 18) | ((REG32(ADR_DCOC_IDAC_REGISTER7)) & 0xff03ffff))
++#define SET_RG_IDACAI_PGAG1(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER8)) = (((_VAL_) << 0) | ((REG32(ADR_DCOC_IDAC_REGISTER8)) & 0xffffffc0))
++#define SET_RG_IDACAQ_PGAG1(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER8)) = (((_VAL_) << 6) | ((REG32(ADR_DCOC_IDAC_REGISTER8)) & 0xfffff03f))
++#define SET_RG_IDACAI_PGAG0(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER8)) = (((_VAL_) << 12) | ((REG32(ADR_DCOC_IDAC_REGISTER8)) & 0xfffc0fff))
++#define SET_RG_IDACAQ_PGAG0(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER8)) = (((_VAL_) << 18) | ((REG32(ADR_DCOC_IDAC_REGISTER8)) & 0xff03ffff))
++#define SET_RG_EN_RCAL(_VAL_) (REG32(ADR_RCAL_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_RCAL_REGISTER)) & 0xfffffffe))
++#define SET_RG_RCAL_SPD(_VAL_) (REG32(ADR_RCAL_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_RCAL_REGISTER)) & 0xfffffffd))
++#define SET_RG_RCAL_TMR(_VAL_) (REG32(ADR_RCAL_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_RCAL_REGISTER)) & 0xfffffe03))
++#define SET_RG_RCAL_CODE_CWR(_VAL_) (REG32(ADR_RCAL_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_RCAL_REGISTER)) & 0xfffffdff))
++#define SET_RG_RCAL_CODE_CWD(_VAL_) (REG32(ADR_RCAL_REGISTER)) = (((_VAL_) << 10) | ((REG32(ADR_RCAL_REGISTER)) & 0xffff83ff))
++#define SET_RG_SX_SUB_SEL_CWR(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (((_VAL_) << 0) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0xfffffffe))
++#define SET_RG_SX_SUB_SEL_CWD(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (((_VAL_) << 1) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0xffffff01))
++#define SET_RG_SX_LCK_BIN_OFFSET(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (((_VAL_) << 15) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0xfff87fff))
++#define SET_RG_SX_LCK_BIN_PRECISION(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (((_VAL_) << 19) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0xfff7ffff))
++#define SET_RG_SX_LOCK_EN_N(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (((_VAL_) << 20) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0xffefffff))
++#define SET_RG_SX_LOCK_MANUAL(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (((_VAL_) << 21) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0xffdfffff))
++#define SET_RG_SX_SUB_MANUAL(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (((_VAL_) << 22) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0xffbfffff))
++#define SET_RG_SX_SUB_SEL(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (((_VAL_) << 23) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0xc07fffff))
++#define SET_RG_SX_MUX_SEL_VTH_BINL(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (((_VAL_) << 30) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0xbfffffff))
++#define SET_RG_TRX_DUMMMY(_VAL_) (REG32(ADR_TRX_DUMMY_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_TRX_DUMMY_REGISTER)) & 0x00000000))
++#define SET_RG_SX_DUMMMY(_VAL_) (REG32(ADR_SX_DUMMY_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_SX_DUMMY_REGISTER)) & 0x00000000))
++#define SET_RCAL_RDY(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 0) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xfffffffe))
++#define SET_LCK_BIN_RDY(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 1) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xfffffffd))
++#define SET_VT_MON_RDY(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 2) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xfffffffb))
++#define SET_DA_R_CODE_LUT(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 6) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xfffff83f))
++#define SET_AD_SX_VT_MON_Q(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 11) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xffffe7ff))
++#define SET_AD_DP_VT_MON_Q(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 13) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xffff9fff))
++#define SET_RTC_CAL_RDY(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 15) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xffff7fff))
++#define SET_RG_SARADC_BIT(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 16) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xffc0ffff))
++#define SET_SAR_ADC_FSM_RDY(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 22) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xffbfffff))
++#define SET_AD_CIRCUIT_VERSION(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 23) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xf87fffff))
++#define SET_DA_R_CAL_CODE(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_2)) = (((_VAL_) << 0) | ((REG32(ADR_READ_ONLY_FLAGS_2)) & 0xffffffe0))
++#define SET_DA_SX_SUB_SEL(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_2)) = (((_VAL_) << 5) | ((REG32(ADR_READ_ONLY_FLAGS_2)) & 0xfffff01f))
++#define SET_RG_DPL_RFCTRL_CH(_VAL_) (REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) = (((_VAL_) << 0) | ((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) & 0xfffff800))
++#define SET_RG_RSSIADC_RO_BIT(_VAL_) (REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) = (((_VAL_) << 11) | ((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) & 0xffff87ff))
++#define SET_RG_RX_ADC_I_RO_BIT(_VAL_) (REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) = (((_VAL_) << 15) | ((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) & 0xff807fff))
++#define SET_RG_RX_ADC_Q_RO_BIT(_VAL_) (REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) = (((_VAL_) << 23) | ((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) & 0x807fffff))
++#define SET_RG_DPL_RFCTRL_F(_VAL_) (REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_II)) = (((_VAL_) << 0) | ((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_II)) & 0xff000000))
++#define SET_RG_SX_TARGET_CNT(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_II)) = (((_VAL_) << 0) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_II)) & 0xffffe000))
++#define SET_RG_RTC_OFFSET(_VAL_) (REG32(ADR_RC_OSC_32K_CAL_REGISTERS)) = (((_VAL_) << 0) | ((REG32(ADR_RC_OSC_32K_CAL_REGISTERS)) & 0xffffff00))
++#define SET_RG_RTC_CAL_TARGET_COUNT(_VAL_) (REG32(ADR_RC_OSC_32K_CAL_REGISTERS)) = (((_VAL_) << 8) | ((REG32(ADR_RC_OSC_32K_CAL_REGISTERS)) & 0xfff000ff))
++#define SET_RG_RF_D_REG(_VAL_) (REG32(ADR_RF_D_DIGITAL_DEBUG_PORT_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_RF_D_DIGITAL_DEBUG_PORT_REGISTER)) & 0xffff0000))
++#define SET_DIRECT_MODE(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 0) | ((REG32(ADR_MMU_CTRL)) & 0xfffffffe))
++#define SET_TAG_INTERLEAVE_MD(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 1) | ((REG32(ADR_MMU_CTRL)) & 0xfffffffd))
++#define SET_DIS_DEMAND(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 2) | ((REG32(ADR_MMU_CTRL)) & 0xfffffffb))
++#define SET_SAME_ID_ALLOC_MD(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 3) | ((REG32(ADR_MMU_CTRL)) & 0xfffffff7))
++#define SET_HS_ACCESS_MD(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 4) | ((REG32(ADR_MMU_CTRL)) & 0xffffffef))
++#define SET_SRAM_ACCESS_MD(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 5) | ((REG32(ADR_MMU_CTRL)) & 0xffffffdf))
++#define SET_NOHIT_RPASS_MD(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 6) | ((REG32(ADR_MMU_CTRL)) & 0xffffffbf))
++#define SET_DMN_FLAG_CLR(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 7) | ((REG32(ADR_MMU_CTRL)) & 0xffffff7f))
++#define SET_ERR_SW_RST_N(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 8) | ((REG32(ADR_MMU_CTRL)) & 0xfffffeff))
++#define SET_ALR_SW_RST_N(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 9) | ((REG32(ADR_MMU_CTRL)) & 0xfffffdff))
++#define SET_MCH_SW_RST_N(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 10) | ((REG32(ADR_MMU_CTRL)) & 0xfffffbff))
++#define SET_TAG_SW_RST_N(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 11) | ((REG32(ADR_MMU_CTRL)) & 0xfffff7ff))
++#define SET_ABT_SW_RST_N(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 12) | ((REG32(ADR_MMU_CTRL)) & 0xffffefff))
++#define SET_MMU_VER(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 13) | ((REG32(ADR_MMU_CTRL)) & 0xffff1fff))
++#define SET_MMU_SHARE_MCU(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 16) | ((REG32(ADR_MMU_CTRL)) & 0xff00ffff))
++#define SET_HS_WR(_VAL_) (REG32(ADR_HS_CTRL)) = (((_VAL_) << 0) | ((REG32(ADR_HS_CTRL)) & 0xfffffffe))
++#define SET_HS_FLAG(_VAL_) (REG32(ADR_HS_CTRL)) = (((_VAL_) << 4) | ((REG32(ADR_HS_CTRL)) & 0xffffffef))
++#define SET_HS_ID(_VAL_) (REG32(ADR_HS_CTRL)) = (((_VAL_) << 8) | ((REG32(ADR_HS_CTRL)) & 0xffff80ff))
++#define SET_HS_CHANNEL(_VAL_) (REG32(ADR_HS_CTRL)) = (((_VAL_) << 16) | ((REG32(ADR_HS_CTRL)) & 0xfff0ffff))
++#define SET_HS_PAGE(_VAL_) (REG32(ADR_HS_CTRL)) = (((_VAL_) << 20) | ((REG32(ADR_HS_CTRL)) & 0xff0fffff))
++#define SET_HS_DATA(_VAL_) (REG32(ADR_HS_CTRL)) = (((_VAL_) << 24) | ((REG32(ADR_HS_CTRL)) & 0x00ffffff))
++#define SET_CPU_POR0(_VAL_) (REG32(ADR_CPU_POR0_7)) = (((_VAL_) << 0) | ((REG32(ADR_CPU_POR0_7)) & 0xfffffff0))
++#define SET_CPU_POR1(_VAL_) (REG32(ADR_CPU_POR0_7)) = (((_VAL_) << 4) | ((REG32(ADR_CPU_POR0_7)) & 0xffffff0f))
++#define SET_CPU_POR2(_VAL_) (REG32(ADR_CPU_POR0_7)) = (((_VAL_) << 8) | ((REG32(ADR_CPU_POR0_7)) & 0xfffff0ff))
++#define SET_CPU_POR3(_VAL_) (REG32(ADR_CPU_POR0_7)) = (((_VAL_) << 12) | ((REG32(ADR_CPU_POR0_7)) & 0xffff0fff))
++#define SET_CPU_POR4(_VAL_) (REG32(ADR_CPU_POR0_7)) = (((_VAL_) << 16) | ((REG32(ADR_CPU_POR0_7)) & 0xfff0ffff))
++#define SET_CPU_POR5(_VAL_) (REG32(ADR_CPU_POR0_7)) = (((_VAL_) << 20) | ((REG32(ADR_CPU_POR0_7)) & 0xff0fffff))
++#define SET_CPU_POR6(_VAL_) (REG32(ADR_CPU_POR0_7)) = (((_VAL_) << 24) | ((REG32(ADR_CPU_POR0_7)) & 0xf0ffffff))
++#define SET_CPU_POR7(_VAL_) (REG32(ADR_CPU_POR0_7)) = (((_VAL_) << 28) | ((REG32(ADR_CPU_POR0_7)) & 0x0fffffff))
++#define SET_CPU_POR8(_VAL_) (REG32(ADR_CPU_POR8_F)) = (((_VAL_) << 0) | ((REG32(ADR_CPU_POR8_F)) & 0xfffffff0))
++#define SET_CPU_POR9(_VAL_) (REG32(ADR_CPU_POR8_F)) = (((_VAL_) << 4) | ((REG32(ADR_CPU_POR8_F)) & 0xffffff0f))
++#define SET_CPU_PORA(_VAL_) (REG32(ADR_CPU_POR8_F)) = (((_VAL_) << 8) | ((REG32(ADR_CPU_POR8_F)) & 0xfffff0ff))
++#define SET_CPU_PORB(_VAL_) (REG32(ADR_CPU_POR8_F)) = (((_VAL_) << 12) | ((REG32(ADR_CPU_POR8_F)) & 0xffff0fff))
++#define SET_CPU_PORC(_VAL_) (REG32(ADR_CPU_POR8_F)) = (((_VAL_) << 16) | ((REG32(ADR_CPU_POR8_F)) & 0xfff0ffff))
++#define SET_CPU_PORD(_VAL_) (REG32(ADR_CPU_POR8_F)) = (((_VAL_) << 20) | ((REG32(ADR_CPU_POR8_F)) & 0xff0fffff))
++#define SET_CPU_PORE(_VAL_) (REG32(ADR_CPU_POR8_F)) = (((_VAL_) << 24) | ((REG32(ADR_CPU_POR8_F)) & 0xf0ffffff))
++#define SET_CPU_PORF(_VAL_) (REG32(ADR_CPU_POR8_F)) = (((_VAL_) << 28) | ((REG32(ADR_CPU_POR8_F)) & 0x0fffffff))
++#define SET_ACC_WR_LEN(_VAL_) (REG32(ADR_REG_LEN_CTRL)) = (((_VAL_) << 0) | ((REG32(ADR_REG_LEN_CTRL)) & 0xffffffc0))
++#define SET_ACC_RD_LEN(_VAL_) (REG32(ADR_REG_LEN_CTRL)) = (((_VAL_) << 8) | ((REG32(ADR_REG_LEN_CTRL)) & 0xffffc0ff))
++#define SET_REQ_NACK_CLR(_VAL_) (REG32(ADR_REG_LEN_CTRL)) = (((_VAL_) << 15) | ((REG32(ADR_REG_LEN_CTRL)) & 0xffff7fff))
++#define SET_NACK_FLAG_BUS(_VAL_) (REG32(ADR_REG_LEN_CTRL)) = (((_VAL_) << 16) | ((REG32(ADR_REG_LEN_CTRL)) & 0x0000ffff))
++#define SET_DMN_R_PASS(_VAL_) (REG32(ADR_DMN_READ_BYPASS)) = (((_VAL_) << 0) | ((REG32(ADR_DMN_READ_BYPASS)) & 0xffff0000))
++#define SET_PARA_ALC_RLS(_VAL_) (REG32(ADR_DMN_READ_BYPASS)) = (((_VAL_) << 16) | ((REG32(ADR_DMN_READ_BYPASS)) & 0xfffeffff))
++#define SET_REQ_PORNS_CHGEN(_VAL_) (REG32(ADR_DMN_READ_BYPASS)) = (((_VAL_) << 24) | ((REG32(ADR_DMN_READ_BYPASS)) & 0xfeffffff))
++#define SET_ALC_ABT_ID(_VAL_) (REG32(ADR_ALC_RLS_ABORT)) = (((_VAL_) << 0) | ((REG32(ADR_ALC_RLS_ABORT)) & 0xffffff80))
++#define SET_ALC_ABT_INT(_VAL_) (REG32(ADR_ALC_RLS_ABORT)) = (((_VAL_) << 15) | ((REG32(ADR_ALC_RLS_ABORT)) & 0xffff7fff))
++#define SET_RLS_ABT_ID(_VAL_) (REG32(ADR_ALC_RLS_ABORT)) = (((_VAL_) << 16) | ((REG32(ADR_ALC_RLS_ABORT)) & 0xff80ffff))
++#define SET_RLS_ABT_INT(_VAL_) (REG32(ADR_ALC_RLS_ABORT)) = (((_VAL_) << 31) | ((REG32(ADR_ALC_RLS_ABORT)) & 0x7fffffff))
++#define SET_DEBUG_CTL(_VAL_) (REG32(ADR_DEBUG_CTL)) = (((_VAL_) << 0) | ((REG32(ADR_DEBUG_CTL)) & 0xffffff00))
++#define SET_DEBUG_H16(_VAL_) (REG32(ADR_DEBUG_CTL)) = (((_VAL_) << 8) | ((REG32(ADR_DEBUG_CTL)) & 0xfffffeff))
++#define SET_DEBUG_OUT(_VAL_) (REG32(ADR_DEBUG_OUT)) = (((_VAL_) << 0) | ((REG32(ADR_DEBUG_OUT)) & 0x00000000))
++#define SET_ALC_ERR(_VAL_) (REG32(ADR_MMU_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MMU_STATUS)) & 0xfffffffe))
++#define SET_RLS_ERR(_VAL_) (REG32(ADR_MMU_STATUS)) = (((_VAL_) << 1) | ((REG32(ADR_MMU_STATUS)) & 0xfffffffd))
++#define SET_AL_STATE(_VAL_) (REG32(ADR_MMU_STATUS)) = (((_VAL_) << 8) | ((REG32(ADR_MMU_STATUS)) & 0xfffff8ff))
++#define SET_RL_STATE(_VAL_) (REG32(ADR_MMU_STATUS)) = (((_VAL_) << 12) | ((REG32(ADR_MMU_STATUS)) & 0xffff8fff))
++#define SET_ALC_ERR_ID(_VAL_) (REG32(ADR_MMU_STATUS)) = (((_VAL_) << 16) | ((REG32(ADR_MMU_STATUS)) & 0xff80ffff))
++#define SET_RLS_ERR_ID(_VAL_) (REG32(ADR_MMU_STATUS)) = (((_VAL_) << 24) | ((REG32(ADR_MMU_STATUS)) & 0x80ffffff))
++#define SET_DMN_NOHIT_FLAG(_VAL_) (REG32(ADR_DMN_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_DMN_STATUS)) & 0xfffffffe))
++#define SET_DMN_FLAG(_VAL_) (REG32(ADR_DMN_STATUS)) = (((_VAL_) << 1) | ((REG32(ADR_DMN_STATUS)) & 0xfffffffd))
++#define SET_DMN_WR(_VAL_) (REG32(ADR_DMN_STATUS)) = (((_VAL_) << 3) | ((REG32(ADR_DMN_STATUS)) & 0xfffffff7))
++#define SET_DMN_PORT(_VAL_) (REG32(ADR_DMN_STATUS)) = (((_VAL_) << 4) | ((REG32(ADR_DMN_STATUS)) & 0xffffff0f))
++#define SET_DMN_NHIT_ID(_VAL_) (REG32(ADR_DMN_STATUS)) = (((_VAL_) << 8) | ((REG32(ADR_DMN_STATUS)) & 0xffff80ff))
++#define SET_DMN_NHIT_ADDR(_VAL_) (REG32(ADR_DMN_STATUS)) = (((_VAL_) << 16) | ((REG32(ADR_DMN_STATUS)) & 0x0000ffff))
++#define SET_TX_MOUNT(_VAL_) (REG32(ADR_TAG_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_TAG_STATUS)) & 0xffffff00))
++#define SET_RX_MOUNT(_VAL_) (REG32(ADR_TAG_STATUS)) = (((_VAL_) << 8) | ((REG32(ADR_TAG_STATUS)) & 0xffff00ff))
++#define SET_AVA_TAG(_VAL_) (REG32(ADR_TAG_STATUS)) = (((_VAL_) << 16) | ((REG32(ADR_TAG_STATUS)) & 0xfe00ffff))
++#define SET_PKTBUF_FULL(_VAL_) (REG32(ADR_TAG_STATUS)) = (((_VAL_) << 31) | ((REG32(ADR_TAG_STATUS)) & 0x7fffffff))
++#define SET_DMN_NOHIT_MCU(_VAL_) (REG32(ADR_DMN_MCU_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_DMN_MCU_STATUS)) & 0xfffffffe))
++#define SET_DMN_MCU_FLAG(_VAL_) (REG32(ADR_DMN_MCU_STATUS)) = (((_VAL_) << 1) | ((REG32(ADR_DMN_MCU_STATUS)) & 0xfffffffd))
++#define SET_DMN_MCU_WR(_VAL_) (REG32(ADR_DMN_MCU_STATUS)) = (((_VAL_) << 3) | ((REG32(ADR_DMN_MCU_STATUS)) & 0xfffffff7))
++#define SET_DMN_MCU_PORT(_VAL_) (REG32(ADR_DMN_MCU_STATUS)) = (((_VAL_) << 4) | ((REG32(ADR_DMN_MCU_STATUS)) & 0xffffff0f))
++#define SET_DMN_MCU_ID(_VAL_) (REG32(ADR_DMN_MCU_STATUS)) = (((_VAL_) << 8) | ((REG32(ADR_DMN_MCU_STATUS)) & 0xffff80ff))
++#define SET_DMN_MCU_ADDR(_VAL_) (REG32(ADR_DMN_MCU_STATUS)) = (((_VAL_) << 16) | ((REG32(ADR_DMN_MCU_STATUS)) & 0x0000ffff))
++#define SET_MB_IDTBL_31_0(_VAL_) (REG32(ADR_MB_IDTBL_0_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MB_IDTBL_0_STATUS)) & 0x00000000))
++#define SET_MB_IDTBL_63_32(_VAL_) (REG32(ADR_MB_IDTBL_1_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MB_IDTBL_1_STATUS)) & 0x00000000))
++#define SET_MB_IDTBL_95_64(_VAL_) (REG32(ADR_MB_IDTBL_2_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MB_IDTBL_2_STATUS)) & 0x00000000))
++#define SET_MB_IDTBL_127_96(_VAL_) (REG32(ADR_MB_IDTBL_3_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MB_IDTBL_3_STATUS)) & 0x00000000))
++#define SET_PKT_IDTBL_31_0(_VAL_) (REG32(ADR_PKT_IDTBL_0_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_PKT_IDTBL_0_STATUS)) & 0x00000000))
++#define SET_PKT_IDTBL_63_32(_VAL_) (REG32(ADR_PKT_IDTBL_1_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_PKT_IDTBL_1_STATUS)) & 0x00000000))
++#define SET_PKT_IDTBL_95_64(_VAL_) (REG32(ADR_PKT_IDTBL_2_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_PKT_IDTBL_2_STATUS)) & 0x00000000))
++#define SET_PKT_IDTBL_127_96(_VAL_) (REG32(ADR_PKT_IDTBL_3_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_PKT_IDTBL_3_STATUS)) & 0x00000000))
++#define SET_DMN_IDTBL_31_0(_VAL_) (REG32(ADR_DMN_IDTBL_0_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_DMN_IDTBL_0_STATUS)) & 0x00000000))
++#define SET_DMN_IDTBL_63_32(_VAL_) (REG32(ADR_DMN_IDTBL_1_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_DMN_IDTBL_1_STATUS)) & 0x00000000))
++#define SET_DMN_IDTBL_95_64(_VAL_) (REG32(ADR_DMN_IDTBL_2_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_DMN_IDTBL_2_STATUS)) & 0x00000000))
++#define SET_DMN_IDTBL_127_96(_VAL_) (REG32(ADR_DMN_IDTBL_3_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_DMN_IDTBL_3_STATUS)) & 0x00000000))
++#define SET_NEQ_MB_ID_31_0(_VAL_) (REG32(ADR_MB_NEQID_0_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MB_NEQID_0_STATUS)) & 0x00000000))
++#define SET_NEQ_MB_ID_63_32(_VAL_) (REG32(ADR_MB_NEQID_1_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MB_NEQID_1_STATUS)) & 0x00000000))
++#define SET_NEQ_MB_ID_95_64(_VAL_) (REG32(ADR_MB_NEQID_2_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MB_NEQID_2_STATUS)) & 0x00000000))
++#define SET_NEQ_MB_ID_127_96(_VAL_) (REG32(ADR_MB_NEQID_3_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MB_NEQID_3_STATUS)) & 0x00000000))
++#define SET_NEQ_PKT_ID_31_0(_VAL_) (REG32(ADR_PKT_NEQID_0_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_PKT_NEQID_0_STATUS)) & 0x00000000))
++#define SET_NEQ_PKT_ID_63_32(_VAL_) (REG32(ADR_PKT_NEQID_1_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_PKT_NEQID_1_STATUS)) & 0x00000000))
++#define SET_NEQ_PKT_ID_95_64(_VAL_) (REG32(ADR_PKT_NEQID_2_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_PKT_NEQID_2_STATUS)) & 0x00000000))
++#define SET_NEQ_PKT_ID_127_96(_VAL_) (REG32(ADR_PKT_NEQID_3_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_PKT_NEQID_3_STATUS)) & 0x00000000))
++#define SET_ALC_NOCHG_ID(_VAL_) (REG32(ADR_ALC_NOCHG_ID_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_ALC_NOCHG_ID_STATUS)) & 0xffffff80))
++#define SET_ALC_NOCHG_INT(_VAL_) (REG32(ADR_ALC_NOCHG_ID_STATUS)) = (((_VAL_) << 15) | ((REG32(ADR_ALC_NOCHG_ID_STATUS)) & 0xffff7fff))
++#define SET_NEQ_PKT_FLAG(_VAL_) (REG32(ADR_ALC_NOCHG_ID_STATUS)) = (((_VAL_) << 16) | ((REG32(ADR_ALC_NOCHG_ID_STATUS)) & 0xfffeffff))
++#define SET_NEQ_MB_FLAG(_VAL_) (REG32(ADR_ALC_NOCHG_ID_STATUS)) = (((_VAL_) << 24) | ((REG32(ADR_ALC_NOCHG_ID_STATUS)) & 0xfeffffff))
++#define SET_SRAM_TAG_0(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_0)) = (((_VAL_) << 0) | ((REG32(ADR_TAG_SRAM0_F_STATUS_0)) & 0xffff0000))
++#define SET_SRAM_TAG_1(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_0)) = (((_VAL_) << 16) | ((REG32(ADR_TAG_SRAM0_F_STATUS_0)) & 0x0000ffff))
++#define SET_SRAM_TAG_2(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_1)) = (((_VAL_) << 0) | ((REG32(ADR_TAG_SRAM0_F_STATUS_1)) & 0xffff0000))
++#define SET_SRAM_TAG_3(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_1)) = (((_VAL_) << 16) | ((REG32(ADR_TAG_SRAM0_F_STATUS_1)) & 0x0000ffff))
++#define SET_SRAM_TAG_4(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_2)) = (((_VAL_) << 0) | ((REG32(ADR_TAG_SRAM0_F_STATUS_2)) & 0xffff0000))
++#define SET_SRAM_TAG_5(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_2)) = (((_VAL_) << 16) | ((REG32(ADR_TAG_SRAM0_F_STATUS_2)) & 0x0000ffff))
++#define SET_SRAM_TAG_6(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_3)) = (((_VAL_) << 0) | ((REG32(ADR_TAG_SRAM0_F_STATUS_3)) & 0xffff0000))
++#define SET_SRAM_TAG_7(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_3)) = (((_VAL_) << 16) | ((REG32(ADR_TAG_SRAM0_F_STATUS_3)) & 0x0000ffff))
++#define SET_SRAM_TAG_8(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_4)) = (((_VAL_) << 0) | ((REG32(ADR_TAG_SRAM0_F_STATUS_4)) & 0xffff0000))
++#define SET_SRAM_TAG_9(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_4)) = (((_VAL_) << 16) | ((REG32(ADR_TAG_SRAM0_F_STATUS_4)) & 0x0000ffff))
++#define SET_SRAM_TAG_10(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_5)) = (((_VAL_) << 0) | ((REG32(ADR_TAG_SRAM0_F_STATUS_5)) & 0xffff0000))
++#define SET_SRAM_TAG_11(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_5)) = (((_VAL_) << 16) | ((REG32(ADR_TAG_SRAM0_F_STATUS_5)) & 0x0000ffff))
++#define SET_SRAM_TAG_12(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_6)) = (((_VAL_) << 0) | ((REG32(ADR_TAG_SRAM0_F_STATUS_6)) & 0xffff0000))
++#define SET_SRAM_TAG_13(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_6)) = (((_VAL_) << 16) | ((REG32(ADR_TAG_SRAM0_F_STATUS_6)) & 0x0000ffff))
++#define SET_SRAM_TAG_14(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_7)) = (((_VAL_) << 0) | ((REG32(ADR_TAG_SRAM0_F_STATUS_7)) & 0xffff0000))
++#define SET_SRAM_TAG_15(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_7)) = (((_VAL_) << 16) | ((REG32(ADR_TAG_SRAM0_F_STATUS_7)) & 0x0000ffff))
++#define DEF_BRG_SW_RST() (REG32(ADR_BRG_SW_RST)) = (0x00000000)
++#define DEF_BOOT() (REG32(ADR_BOOT)) = (0x00040000)
++#define DEF_CHIP_ID_0() (REG32(ADR_CHIP_ID_0)) = (0x31333131)
++#define DEF_CHIP_ID_1() (REG32(ADR_CHIP_ID_1)) = (0x322d3230)
++#define DEF_CHIP_ID_2() (REG32(ADR_CHIP_ID_2)) = (0x32303041)
++#define DEF_CHIP_ID_3() (REG32(ADR_CHIP_ID_3)) = (0x53535636)
++#define DEF_CLOCK_SELECTION() (REG32(ADR_CLOCK_SELECTION)) = (0x00000000)
++#define DEF_PLATFORM_CLOCK_ENABLE() (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (0x008fffff)
++#define DEF_SYS_CSR_CLOCK_ENABLE() (REG32(ADR_SYS_CSR_CLOCK_ENABLE)) = (0x00000400)
++#define DEF_MCU_DBG_SEL() (REG32(ADR_MCU_DBG_SEL)) = (0x00000000)
++#define DEF_MCU_DBG_DATA() (REG32(ADR_MCU_DBG_DATA)) = (0x00000000)
++#define DEF_AHB_BRG_STATUS() (REG32(ADR_AHB_BRG_STATUS)) = (0x00000000)
++#define DEF_BIST_BIST_CTRL() (REG32(ADR_BIST_BIST_CTRL)) = (0x00000000)
++#define DEF_BIST_MODE_REG_IN() (REG32(ADR_BIST_MODE_REG_IN)) = (0x001ffe3e)
++#define DEF_BIST_MODE_REG_OUT() (REG32(ADR_BIST_MODE_REG_OUT)) = (0x00000000)
++#define DEF_BIST_MONITOR_BUS_LSB() (REG32(ADR_BIST_MONITOR_BUS_LSB)) = (0x00000000)
++#define DEF_BIST_MONITOR_BUS_MSB() (REG32(ADR_BIST_MONITOR_BUS_MSB)) = (0x00000000)
++#define DEF_TB_ADR_SEL() (REG32(ADR_TB_ADR_SEL)) = (0x00000000)
++#define DEF_TB_RDATA() (REG32(ADR_TB_RDATA)) = (0x00000000)
++#define DEF_UART_W2B() (REG32(ADR_UART_W2B)) = (0x00000000)
++#define DEF_AHB_ILL_ADDR() (REG32(ADR_AHB_ILL_ADDR)) = (0x00000000)
++#define DEF_AHB_FEN_ADDR() (REG32(ADR_AHB_FEN_ADDR)) = (0x00000000)
++#define DEF_AHB_ILLFEN_STATUS() (REG32(ADR_AHB_ILLFEN_STATUS)) = (0x00000000)
++#define DEF_PWM_A() (REG32(ADR_PWM_A)) = (0x400a1010)
++#define DEF_PWM_B() (REG32(ADR_PWM_B)) = (0x400a1010)
++#define DEF_HBUSREQ_LOCK() (REG32(ADR_HBUSREQ_LOCK)) = (0x00001ffd)
++#define DEF_HBURST_LOCK() (REG32(ADR_HBURST_LOCK)) = (0x00000000)
++#define DEF_PRESCALER_USTIMER() (REG32(ADR_PRESCALER_USTIMER)) = (0x00000028)
++#define DEF_BIST_MODE_REG_IN_MMU() (REG32(ADR_BIST_MODE_REG_IN_MMU)) = (0x0000fe3e)
++#define DEF_BIST_MODE_REG_OUT_MMU() (REG32(ADR_BIST_MODE_REG_OUT_MMU)) = (0x00000000)
++#define DEF_BIST_MONITOR_BUS_MMU() (REG32(ADR_BIST_MONITOR_BUS_MMU)) = (0x00000000)
++#define DEF_TEST_MODE() (REG32(ADR_TEST_MODE)) = (0x00000000)
++#define DEF_BOOT_INFO() (REG32(ADR_BOOT_INFO)) = (0x00000000)
++#define DEF_SD_INIT_CFG() (REG32(ADR_SD_INIT_CFG)) = (0x00000000)
++#define DEF_SPARE_UART_INFO() (REG32(ADR_SPARE_UART_INFO)) = (0x00000000)
++#define DEF_TU0_MICROSECOND_TIMER() (REG32(ADR_TU0_MICROSECOND_TIMER)) = (0x00000000)
++#define DEF_TU0_CURRENT_MICROSECOND_TIME_VALUE() (REG32(ADR_TU0_CURRENT_MICROSECOND_TIME_VALUE)) = (0x00000000)
++#define DEF_TU0_DUMMY_BIT_0() (REG32(ADR_TU0_DUMMY_BIT_0)) = (0x00000000)
++#define DEF_TU0_DUMMY_BIT_1() (REG32(ADR_TU0_DUMMY_BIT_1)) = (0x00000000)
++#define DEF_TU1_MICROSECOND_TIMER() (REG32(ADR_TU1_MICROSECOND_TIMER)) = (0x00000000)
++#define DEF_TU1_CURRENT_MICROSECOND_TIME_VALUE() (REG32(ADR_TU1_CURRENT_MICROSECOND_TIME_VALUE)) = (0x00000000)
++#define DEF_TU1_DUMMY_BIT_0() (REG32(ADR_TU1_DUMMY_BIT_0)) = (0x00000000)
++#define DEF_TU1_DUMMY_BIT_1() (REG32(ADR_TU1_DUMMY_BIT_1)) = (0x00000000)
++#define DEF_TU2_MICROSECOND_TIMER() (REG32(ADR_TU2_MICROSECOND_TIMER)) = (0x00000000)
++#define DEF_TU2_CURRENT_MICROSECOND_TIME_VALUE() (REG32(ADR_TU2_CURRENT_MICROSECOND_TIME_VALUE)) = (0x00000000)
++#define DEF_TU2_DUMMY_BIT_0() (REG32(ADR_TU2_DUMMY_BIT_0)) = (0x00000000)
++#define DEF_TU2_DUMMY_BIT_1() (REG32(ADR_TU2_DUMMY_BIT_1)) = (0x00000000)
++#define DEF_TU3_MICROSECOND_TIMER() (REG32(ADR_TU3_MICROSECOND_TIMER)) = (0x00000000)
++#define DEF_TU3_CURRENT_MICROSECOND_TIME_VALUE() (REG32(ADR_TU3_CURRENT_MICROSECOND_TIME_VALUE)) = (0x00000000)
++#define DEF_TU3_DUMMY_BIT_0() (REG32(ADR_TU3_DUMMY_BIT_0)) = (0x00000000)
++#define DEF_TU3_DUMMY_BIT_1() (REG32(ADR_TU3_DUMMY_BIT_1)) = (0x00000000)
++#define DEF_TM0_MILISECOND_TIMER() (REG32(ADR_TM0_MILISECOND_TIMER)) = (0x00000000)
++#define DEF_TM0_CURRENT_MILISECOND_TIME_VALUE() (REG32(ADR_TM0_CURRENT_MILISECOND_TIME_VALUE)) = (0x00000000)
++#define DEF_TM0_DUMMY_BIT_0() (REG32(ADR_TM0_DUMMY_BIT_0)) = (0x00000000)
++#define DEF_TM0_DUMMY_BIT_1() (REG32(ADR_TM0_DUMMY_BIT_1)) = (0x00000000)
++#define DEF_TM1_MILISECOND_TIMER() (REG32(ADR_TM1_MILISECOND_TIMER)) = (0x00000000)
++#define DEF_TM1_CURRENT_MILISECOND_TIME_VALUE() (REG32(ADR_TM1_CURRENT_MILISECOND_TIME_VALUE)) = (0x00000000)
++#define DEF_TM1_DUMMY_BIT_0() (REG32(ADR_TM1_DUMMY_BIT_0)) = (0x00000000)
++#define DEF_TM1_DUMMY_BIT_1() (REG32(ADR_TM1_DUMMY_BIT_1)) = (0x00000000)
++#define DEF_TM2_MILISECOND_TIMER() (REG32(ADR_TM2_MILISECOND_TIMER)) = (0x00000000)
++#define DEF_TM2_CURRENT_MILISECOND_TIME_VALUE() (REG32(ADR_TM2_CURRENT_MILISECOND_TIME_VALUE)) = (0x00000000)
++#define DEF_TM2_DUMMY_BIT_0() (REG32(ADR_TM2_DUMMY_BIT_0)) = (0x00000000)
++#define DEF_TM2_DUMMY_BIT_1() (REG32(ADR_TM2_DUMMY_BIT_1)) = (0x00000000)
++#define DEF_TM3_MILISECOND_TIMER() (REG32(ADR_TM3_MILISECOND_TIMER)) = (0x00000000)
++#define DEF_TM3_CURRENT_MILISECOND_TIME_VALUE() (REG32(ADR_TM3_CURRENT_MILISECOND_TIME_VALUE)) = (0x00000000)
++#define DEF_TM3_DUMMY_BIT_0() (REG32(ADR_TM3_DUMMY_BIT_0)) = (0x00000000)
++#define DEF_TM3_DUMMY_BIT_1() (REG32(ADR_TM3_DUMMY_BIT_1)) = (0x00000000)
++#define DEF_MCU_WDOG_REG() (REG32(ADR_MCU_WDOG_REG)) = (0x00000000)
++#define DEF_SYS_WDOG_REG() (REG32(ADR_SYS_WDOG_REG)) = (0x00000000)
++#define DEF_PAD6() (REG32(ADR_PAD6)) = (0x00000008)
++#define DEF_PAD7() (REG32(ADR_PAD7)) = (0x00000008)
++#define DEF_PAD8() (REG32(ADR_PAD8)) = (0x00000008)
++#define DEF_PAD9() (REG32(ADR_PAD9)) = (0x00000008)
++#define DEF_PAD11() (REG32(ADR_PAD11)) = (0x00000008)
++#define DEF_PAD15() (REG32(ADR_PAD15)) = (0x0000000a)
++#define DEF_PAD16() (REG32(ADR_PAD16)) = (0x0000000a)
++#define DEF_PAD17() (REG32(ADR_PAD17)) = (0x0000000a)
++#define DEF_PAD18() (REG32(ADR_PAD18)) = (0x0000000a)
++#define DEF_PAD19() (REG32(ADR_PAD19)) = (0x00007000)
++#define DEF_PAD20() (REG32(ADR_PAD20)) = (0x0000000a)
++#define DEF_PAD21() (REG32(ADR_PAD21)) = (0x0000000a)
++#define DEF_PAD22() (REG32(ADR_PAD22)) = (0x00000009)
++#define DEF_PAD24() (REG32(ADR_PAD24)) = (0x00000008)
++#define DEF_PAD25() (REG32(ADR_PAD25)) = (0x0000000b)
++#define DEF_PAD27() (REG32(ADR_PAD27)) = (0x00000008)
++#define DEF_PAD28() (REG32(ADR_PAD28)) = (0x00000008)
++#define DEF_PAD29() (REG32(ADR_PAD29)) = (0x00000009)
++#define DEF_PAD30() (REG32(ADR_PAD30)) = (0x0000000a)
++#define DEF_PAD31() (REG32(ADR_PAD31)) = (0x0000000a)
++#define DEF_PAD32() (REG32(ADR_PAD32)) = (0x0000000a)
++#define DEF_PAD33() (REG32(ADR_PAD33)) = (0x0000000a)
++#define DEF_PAD34() (REG32(ADR_PAD34)) = (0x0000000a)
++#define DEF_PAD42() (REG32(ADR_PAD42)) = (0x0000000a)
++#define DEF_PAD43() (REG32(ADR_PAD43)) = (0x0000000a)
++#define DEF_PAD44() (REG32(ADR_PAD44)) = (0x0000000a)
++#define DEF_PAD45() (REG32(ADR_PAD45)) = (0x0000000a)
++#define DEF_PAD46() (REG32(ADR_PAD46)) = (0x0000000a)
++#define DEF_PAD47() (REG32(ADR_PAD47)) = (0x00100000)
++#define DEF_PAD48() (REG32(ADR_PAD48)) = (0x00100808)
++#define DEF_PAD49() (REG32(ADR_PAD49)) = (0x00100008)
++#define DEF_PAD50() (REG32(ADR_PAD50)) = (0x00100008)
++#define DEF_PAD51() (REG32(ADR_PAD51)) = (0x00100008)
++#define DEF_PAD52() (REG32(ADR_PAD52)) = (0x00100000)
++#define DEF_PAD53() (REG32(ADR_PAD53)) = (0x0000000a)
++#define DEF_PAD54() (REG32(ADR_PAD54)) = (0x00000000)
++#define DEF_PAD56() (REG32(ADR_PAD56)) = (0x00000000)
++#define DEF_PAD57() (REG32(ADR_PAD57)) = (0x00000008)
++#define DEF_PAD58() (REG32(ADR_PAD58)) = (0x0000000a)
++#define DEF_PAD59() (REG32(ADR_PAD59)) = (0x0000000a)
++#define DEF_PAD60() (REG32(ADR_PAD60)) = (0x0000000a)
++#define DEF_PAD61() (REG32(ADR_PAD61)) = (0x0000000a)
++#define DEF_PAD62() (REG32(ADR_PAD62)) = (0x0000000a)
++#define DEF_PAD64() (REG32(ADR_PAD64)) = (0x00000009)
++#define DEF_PAD65() (REG32(ADR_PAD65)) = (0x00000009)
++#define DEF_PAD66() (REG32(ADR_PAD66)) = (0x00000008)
++#define DEF_PAD68() (REG32(ADR_PAD68)) = (0x00000008)
++#define DEF_PAD67() (REG32(ADR_PAD67)) = (0x00000159)
++#define DEF_PAD69() (REG32(ADR_PAD69)) = (0x0000000b)
++#define DEF_PAD70() (REG32(ADR_PAD70)) = (0x00000008)
++#define DEF_PAD231() (REG32(ADR_PAD231)) = (0x00000008)
++#define DEF_PIN_SEL_0() (REG32(ADR_PIN_SEL_0)) = (0x00000000)
++#define DEF_PIN_SEL_1() (REG32(ADR_PIN_SEL_1)) = (0x00000000)
++#define DEF_IO_PORT_REG() (REG32(ADR_IO_PORT_REG)) = (0x00010000)
++#define DEF_INT_MASK_REG() (REG32(ADR_INT_MASK_REG)) = (0x000000ff)
++#define DEF_INT_STATUS_REG() (REG32(ADR_INT_STATUS_REG)) = (0x00000000)
++#define DEF_FN1_STATUS_REG() (REG32(ADR_FN1_STATUS_REG)) = (0x00000000)
++#define DEF_CARD_PKT_STATUS_TEST() (REG32(ADR_CARD_PKT_STATUS_TEST)) = (0x00000000)
++#define DEF_SYSTEM_INFORMATION_REG() (REG32(ADR_SYSTEM_INFORMATION_REG)) = (0x00000000)
++#define DEF_CARD_RCA_REG() (REG32(ADR_CARD_RCA_REG)) = (0x00000000)
++#define DEF_SDIO_FIFO_WR_THLD_REG() (REG32(ADR_SDIO_FIFO_WR_THLD_REG)) = (0x00000000)
++#define DEF_SDIO_FIFO_WR_LIMIT_REG() (REG32(ADR_SDIO_FIFO_WR_LIMIT_REG)) = (0x00000000)
++#define DEF_SDIO_TX_DATA_BATCH_SIZE_REG() (REG32(ADR_SDIO_TX_DATA_BATCH_SIZE_REG)) = (0x00000000)
++#define DEF_SDIO_THLD_FOR_CMD53RD_REG() (REG32(ADR_SDIO_THLD_FOR_CMD53RD_REG)) = (0x00000000)
++#define DEF_SDIO_RX_DATA_BATCH_SIZE_REG() (REG32(ADR_SDIO_RX_DATA_BATCH_SIZE_REG)) = (0x00000000)
++#define DEF_SDIO_LOG_START_END_DATA_REG() (REG32(ADR_SDIO_LOG_START_END_DATA_REG)) = (0x00000000)
++#define DEF_SDIO_BYTE_MODE_BATCH_SIZE_REG() (REG32(ADR_SDIO_BYTE_MODE_BATCH_SIZE_REG)) = (0x00000000)
++#define DEF_SDIO_LAST_CMD_INDEX_CRC_REG() (REG32(ADR_SDIO_LAST_CMD_INDEX_CRC_REG)) = (0x00000000)
++#define DEF_SDIO_LAST_CMD_ARG_REG() (REG32(ADR_SDIO_LAST_CMD_ARG_REG)) = (0x00000000)
++#define DEF_SDIO_BUS_STATE_DEBUG_MONITOR() (REG32(ADR_SDIO_BUS_STATE_DEBUG_MONITOR)) = (0x00000000)
++#define DEF_SDIO_CARD_STATUS_REG() (REG32(ADR_SDIO_CARD_STATUS_REG)) = (0x00000000)
++#define DEF_R5_RESP_FLAG_OUT_TIMING() (REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) = (0x00000000)
++#define DEF_CMD52_DATA_FOR_LAST_TIME() (REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) = (0x00000000)
++#define DEF_FN1_DMA_START_ADDR_REG() (REG32(ADR_FN1_DMA_START_ADDR_REG)) = (0x00000000)
++#define DEF_FN1_INT_CTRL_RESET() (REG32(ADR_FN1_INT_CTRL_RESET)) = (0x00000000)
++#define DEF_IO_REG_PORT_REG() (REG32(ADR_IO_REG_PORT_REG)) = (0x00010020)
++#define DEF_SDIO_FIFO_ERROR_CNT() (REG32(ADR_SDIO_FIFO_ERROR_CNT)) = (0x00000000)
++#define DEF_SDIO_CRC7_CRC16_ERROR_REG() (REG32(ADR_SDIO_CRC7_CRC16_ERROR_REG)) = (0x00000000)
++#define DEF_SDIO_BLOCK_CNT_INFO() (REG32(ADR_SDIO_BLOCK_CNT_INFO)) = (0x00000000)
++#define DEF_RX_DATA_CMD52_ABORT_COUNT() (REG32(ADR_RX_DATA_CMD52_ABORT_COUNT)) = (0x00000000)
++#define DEF_FIFO_PTR_READ_BLOCK_CNT() (REG32(ADR_FIFO_PTR_READ_BLOCK_CNT)) = (0x00000000)
++#define DEF_TX_TIME_OUT_READ_CTRL() (REG32(ADR_TX_TIME_OUT_READ_CTRL)) = (0x00000000)
++#define DEF_SDIO_TX_ALLOC_REG() (REG32(ADR_SDIO_TX_ALLOC_REG)) = (0x00000000)
++#define DEF_SDIO_TX_INFORM() (REG32(ADR_SDIO_TX_INFORM)) = (0x00000000)
++#define DEF_F1_BLOCK_SIZE_0_REG() (REG32(ADR_F1_BLOCK_SIZE_0_REG)) = (0x00000000)
++#define DEF_SDIO_COMMAND_LOG_DATA_31_0() (REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) = (0x000000ec)
++#define DEF_SDIO_COMMAND_LOG_DATA_63_32() (REG32(ADR_SDIO_COMMAND_LOG_DATA_63_32)) = (0xce000000)
++#define DEF_SYSTEM_INFORMATION_REGISTER() (REG32(ADR_SYSTEM_INFORMATION_REGISTER)) = (0x00000000)
++#define DEF_CCCR_00H_REG() (REG32(ADR_CCCR_00H_REG)) = (0x00000000)
++#define DEF_CCCR_04H_REG() (REG32(ADR_CCCR_04H_REG)) = (0x00000000)
++#define DEF_CCCR_08H_REG() (REG32(ADR_CCCR_08H_REG)) = (0x00000000)
++#define DEF_CCCR_13H_REG() (REG32(ADR_CCCR_13H_REG)) = (0x00000000)
++#define DEF_FBR_100H_REG() (REG32(ADR_FBR_100H_REG)) = (0x00000000)
++#define DEF_FBR_109H_REG() (REG32(ADR_FBR_109H_REG)) = (0x00000000)
++#define DEF_F0_CIS_CONTENT_REG_0() (REG32(ADR_F0_CIS_CONTENT_REG_0)) = (0x00000000)
++#define DEF_F0_CIS_CONTENT_REG_1() (REG32(ADR_F0_CIS_CONTENT_REG_1)) = (0x00000000)
++#define DEF_F0_CIS_CONTENT_REG_2() (REG32(ADR_F0_CIS_CONTENT_REG_2)) = (0x00000000)
++#define DEF_F0_CIS_CONTENT_REG_3() (REG32(ADR_F0_CIS_CONTENT_REG_3)) = (0x00000000)
++#define DEF_F0_CIS_CONTENT_REG_4() (REG32(ADR_F0_CIS_CONTENT_REG_4)) = (0x00000000)
++#define DEF_F0_CIS_CONTENT_REG_5() (REG32(ADR_F0_CIS_CONTENT_REG_5)) = (0x00000000)
++#define DEF_F0_CIS_CONTENT_REG_6() (REG32(ADR_F0_CIS_CONTENT_REG_6)) = (0x00000000)
++#define DEF_F0_CIS_CONTENT_REG_7() (REG32(ADR_F0_CIS_CONTENT_REG_7)) = (0x00000000)
++#define DEF_F0_CIS_CONTENT_REG_8() (REG32(ADR_F0_CIS_CONTENT_REG_8)) = (0x00000000)
++#define DEF_F0_CIS_CONTENT_REG_9() (REG32(ADR_F0_CIS_CONTENT_REG_9)) = (0x00000000)
++#define DEF_F0_CIS_CONTENT_REG_10() (REG32(ADR_F0_CIS_CONTENT_REG_10)) = (0x00000000)
++#define DEF_F0_CIS_CONTENT_REG_11() (REG32(ADR_F0_CIS_CONTENT_REG_11)) = (0x00000000)
++#define DEF_F0_CIS_CONTENT_REG_12() (REG32(ADR_F0_CIS_CONTENT_REG_12)) = (0x00000000)
++#define DEF_F0_CIS_CONTENT_REG_13() (REG32(ADR_F0_CIS_CONTENT_REG_13)) = (0x00000000)
++#define DEF_F0_CIS_CONTENT_REG_14() (REG32(ADR_F0_CIS_CONTENT_REG_14)) = (0x00000000)
++#define DEF_F0_CIS_CONTENT_REG_15() (REG32(ADR_F0_CIS_CONTENT_REG_15)) = (0x00000000)
++#define DEF_F1_CIS_CONTENT_REG_0() (REG32(ADR_F1_CIS_CONTENT_REG_0)) = (0x00000000)
++#define DEF_F1_CIS_CONTENT_REG_1() (REG32(ADR_F1_CIS_CONTENT_REG_1)) = (0x00000000)
++#define DEF_F1_CIS_CONTENT_REG_2() (REG32(ADR_F1_CIS_CONTENT_REG_2)) = (0x00000000)
++#define DEF_F1_CIS_CONTENT_REG_3() (REG32(ADR_F1_CIS_CONTENT_REG_3)) = (0x00000000)
++#define DEF_F1_CIS_CONTENT_REG_4() (REG32(ADR_F1_CIS_CONTENT_REG_4)) = (0x00000000)
++#define DEF_F1_CIS_CONTENT_REG_5() (REG32(ADR_F1_CIS_CONTENT_REG_5)) = (0x00000000)
++#define DEF_F1_CIS_CONTENT_REG_6() (REG32(ADR_F1_CIS_CONTENT_REG_6)) = (0x00000000)
++#define DEF_F1_CIS_CONTENT_REG_7() (REG32(ADR_F1_CIS_CONTENT_REG_7)) = (0x00000000)
++#define DEF_F1_CIS_CONTENT_REG_8() (REG32(ADR_F1_CIS_CONTENT_REG_8)) = (0x00000000)
++#define DEF_F1_CIS_CONTENT_REG_9() (REG32(ADR_F1_CIS_CONTENT_REG_9)) = (0x00000000)
++#define DEF_F1_CIS_CONTENT_REG_10() (REG32(ADR_F1_CIS_CONTENT_REG_10)) = (0x00000000)
++#define DEF_F1_CIS_CONTENT_REG_11() (REG32(ADR_F1_CIS_CONTENT_REG_11)) = (0x00000000)
++#define DEF_F1_CIS_CONTENT_REG_12() (REG32(ADR_F1_CIS_CONTENT_REG_12)) = (0x00000000)
++#define DEF_F1_CIS_CONTENT_REG_13() (REG32(ADR_F1_CIS_CONTENT_REG_13)) = (0x00000000)
++#define DEF_F1_CIS_CONTENT_REG_14() (REG32(ADR_F1_CIS_CONTENT_REG_14)) = (0x00000000)
++#define DEF_F1_CIS_CONTENT_REG_15() (REG32(ADR_F1_CIS_CONTENT_REG_15)) = (0x00000000)
++#define DEF_SPI_MODE() (REG32(ADR_SPI_MODE)) = (0x00000000)
++#define DEF_RX_QUOTA() (REG32(ADR_RX_QUOTA)) = (0x00000000)
++#define DEF_CONDITION_NUMBER() (REG32(ADR_CONDITION_NUMBER)) = (0x00000004)
++#define DEF_HOST_PATH() (REG32(ADR_HOST_PATH)) = (0x00000001)
++#define DEF_TX_SEG() (REG32(ADR_TX_SEG)) = (0x00000000)
++#define DEF_DEBUG_BURST_MODE() (REG32(ADR_DEBUG_BURST_MODE)) = (0x00000000)
++#define DEF_SPI_TO_PHY_PARAM1() (REG32(ADR_SPI_TO_PHY_PARAM1)) = (0x000e0006)
++#define DEF_SPI_TO_PHY_PARAM2() (REG32(ADR_SPI_TO_PHY_PARAM2)) = (0x000e000e)
++#define DEF_SPI_STS() (REG32(ADR_SPI_STS)) = (0x00000000)
++#define DEF_TX_ALLOC_SET() (REG32(ADR_TX_ALLOC_SET)) = (0x00000000)
++#define DEF_TX_ALLOC() (REG32(ADR_TX_ALLOC)) = (0x00000000)
++#define DEF_DBG_CNT() (REG32(ADR_DBG_CNT)) = (0x00000000)
++#define DEF_DBG_CNT2() (REG32(ADR_DBG_CNT2)) = (0x00000000)
++#define DEF_DBG_CNT3() (REG32(ADR_DBG_CNT3)) = (0x00000000)
++#define DEF_DBG_CNT4() (REG32(ADR_DBG_CNT4)) = (0x00000000)
++#define DEF_INT_TAG() (REG32(ADR_INT_TAG)) = (0x00000000)
++#define DEF_I2CM_EN() (REG32(ADR_I2CM_EN)) = (0x00000074)
++#define DEF_I2CM_DEV_A() (REG32(ADR_I2CM_DEV_A)) = (0x00008000)
++#define DEF_I2CM_LEN() (REG32(ADR_I2CM_LEN)) = (0x00000000)
++#define DEF_I2CM_WDAT() (REG32(ADR_I2CM_WDAT)) = (0x00000000)
++#define DEF_I2CM_RDAT() (REG32(ADR_I2CM_RDAT)) = (0x00000000)
++#define DEF_I2CM_EN_2() (REG32(ADR_I2CM_EN_2)) = (0x00010000)
++#define DEF_UART_DATA() (REG32(ADR_UART_DATA)) = (0x00000000)
++#define DEF_UART_IER() (REG32(ADR_UART_IER)) = (0x00000000)
++#define DEF_UART_FCR() (REG32(ADR_UART_FCR)) = (0x00000001)
++#define DEF_UART_LCR() (REG32(ADR_UART_LCR)) = (0x00000003)
++#define DEF_UART_MCR() (REG32(ADR_UART_MCR)) = (0x00000000)
++#define DEF_UART_LSR() (REG32(ADR_UART_LSR)) = (0x00000000)
++#define DEF_UART_MSR() (REG32(ADR_UART_MSR)) = (0x00000000)
++#define DEF_UART_SPR() (REG32(ADR_UART_SPR)) = (0x00000000)
++#define DEF_UART_RTHR() (REG32(ADR_UART_RTHR)) = (0x000000c8)
++#define DEF_UART_ISR() (REG32(ADR_UART_ISR)) = (0x000000c1)
++#define DEF_DAT_UART_DATA() (REG32(ADR_DAT_UART_DATA)) = (0x00000000)
++#define DEF_DAT_UART_IER() (REG32(ADR_DAT_UART_IER)) = (0x00000000)
++#define DEF_DAT_UART_FCR() (REG32(ADR_DAT_UART_FCR)) = (0x00000001)
++#define DEF_DAT_UART_LCR() (REG32(ADR_DAT_UART_LCR)) = (0x00000003)
++#define DEF_DAT_UART_MCR() (REG32(ADR_DAT_UART_MCR)) = (0x00000000)
++#define DEF_DAT_UART_LSR() (REG32(ADR_DAT_UART_LSR)) = (0x00000000)
++#define DEF_DAT_UART_MSR() (REG32(ADR_DAT_UART_MSR)) = (0x00000000)
++#define DEF_DAT_UART_SPR() (REG32(ADR_DAT_UART_SPR)) = (0x00000000)
++#define DEF_DAT_UART_RTHR() (REG32(ADR_DAT_UART_RTHR)) = (0x000000c8)
++#define DEF_DAT_UART_ISR() (REG32(ADR_DAT_UART_ISR)) = (0x000000c1)
++#define DEF_INT_MASK() (REG32(ADR_INT_MASK)) = (0xffffffff)
++#define DEF_INT_MODE() (REG32(ADR_INT_MODE)) = (0x00000000)
++#define DEF_INT_IRQ_STS() (REG32(ADR_INT_IRQ_STS)) = (0x00000000)
++#define DEF_INT_FIQ_STS() (REG32(ADR_INT_FIQ_STS)) = (0x00000000)
++#define DEF_INT_IRQ_RAW() (REG32(ADR_INT_IRQ_RAW)) = (0x00000000)
++#define DEF_INT_FIQ_RAW() (REG32(ADR_INT_FIQ_RAW)) = (0x00000000)
++#define DEF_INT_PERI_MASK() (REG32(ADR_INT_PERI_MASK)) = (0xffffffff)
++#define DEF_INT_PERI_STS() (REG32(ADR_INT_PERI_STS)) = (0x00000000)
++#define DEF_INT_PERI_RAW() (REG32(ADR_INT_PERI_RAW)) = (0x00000000)
++#define DEF_INT_GPI_CFG() (REG32(ADR_INT_GPI_CFG)) = (0x00000000)
++#define DEF_SYS_INT_FOR_HOST() (REG32(ADR_SYS_INT_FOR_HOST)) = (0x00000001)
++#define DEF_SPI_IPC() (REG32(ADR_SPI_IPC)) = (0x00000000)
++#define DEF_SDIO_IPC() (REG32(ADR_SDIO_IPC)) = (0x00000000)
++#define DEF_SDIO_MASK() (REG32(ADR_SDIO_MASK)) = (0xffffffff)
++#define DEF_SDIO_IRQ_STS() (REG32(ADR_SDIO_IRQ_STS)) = (0x00000000)
++#define DEF_SD_PERI_MASK() (REG32(ADR_SD_PERI_MASK)) = (0xffffffff)
++#define DEF_SD_PERI_STS() (REG32(ADR_SD_PERI_STS)) = (0x00000000)
++#define DEF_DBG_SPI_MODE() (REG32(ADR_DBG_SPI_MODE)) = (0x00000000)
++#define DEF_DBG_RX_QUOTA() (REG32(ADR_DBG_RX_QUOTA)) = (0x00000000)
++#define DEF_DBG_CONDITION_NUMBER() (REG32(ADR_DBG_CONDITION_NUMBER)) = (0x00000004)
++#define DEF_DBG_HOST_PATH() (REG32(ADR_DBG_HOST_PATH)) = (0x00000001)
++#define DEF_DBG_TX_SEG() (REG32(ADR_DBG_TX_SEG)) = (0x00000000)
++#define DEF_DBG_DEBUG_BURST_MODE() (REG32(ADR_DBG_DEBUG_BURST_MODE)) = (0x00000000)
++#define DEF_DBG_SPI_TO_PHY_PARAM1() (REG32(ADR_DBG_SPI_TO_PHY_PARAM1)) = (0x000e0006)
++#define DEF_DBG_SPI_TO_PHY_PARAM2() (REG32(ADR_DBG_SPI_TO_PHY_PARAM2)) = (0x000e000e)
++#define DEF_DBG_SPI_STS() (REG32(ADR_DBG_SPI_STS)) = (0x00000000)
++#define DEF_DBG_TX_ALLOC_SET() (REG32(ADR_DBG_TX_ALLOC_SET)) = (0x00000000)
++#define DEF_DBG_TX_ALLOC() (REG32(ADR_DBG_TX_ALLOC)) = (0x00000000)
++#define DEF_DBG_DBG_CNT() (REG32(ADR_DBG_DBG_CNT)) = (0x00000000)
++#define DEF_DBG_DBG_CNT2() (REG32(ADR_DBG_DBG_CNT2)) = (0x00000000)
++#define DEF_DBG_DBG_CNT3() (REG32(ADR_DBG_DBG_CNT3)) = (0x00000000)
++#define DEF_DBG_DBG_CNT4() (REG32(ADR_DBG_DBG_CNT4)) = (0x00000000)
++#define DEF_DBG_INT_TAG() (REG32(ADR_DBG_INT_TAG)) = (0x00000000)
++#define DEF_BOOT_ADDR() (REG32(ADR_BOOT_ADDR)) = (0x00000000)
++#define DEF_VERIFY_DATA() (REG32(ADR_VERIFY_DATA)) = (0x5e11aa11)
++#define DEF_FLASH_ADDR() (REG32(ADR_FLASH_ADDR)) = (0x00000000)
++#define DEF_SRAM_ADDR() (REG32(ADR_SRAM_ADDR)) = (0x00000000)
++#define DEF_LEN() (REG32(ADR_LEN)) = (0x00000000)
++#define DEF_SPI_PARAM() (REG32(ADR_SPI_PARAM)) = (0x000f000f)
++#define DEF_SPI_PARAM2() (REG32(ADR_SPI_PARAM2)) = (0x00040001)
++#define DEF_CHECK_SUM_RESULT() (REG32(ADR_CHECK_SUM_RESULT)) = (0x00000000)
++#define DEF_CHECK_SUM_IN_FILE() (REG32(ADR_CHECK_SUM_IN_FILE)) = (0x00000000)
++#define DEF_COMMAND_LEN() (REG32(ADR_COMMAND_LEN)) = (0x00000000)
++#define DEF_COMMAND_ADDR() (REG32(ADR_COMMAND_ADDR)) = (0x00000000)
++#define DEF_DMA_ADR_SRC() (REG32(ADR_DMA_ADR_SRC)) = (0x00000000)
++#define DEF_DMA_ADR_DST() (REG32(ADR_DMA_ADR_DST)) = (0x00000000)
++#define DEF_DMA_CTRL() (REG32(ADR_DMA_CTRL)) = (0x000000aa)
++#define DEF_DMA_INT() (REG32(ADR_DMA_INT)) = (0x00000001)
++#define DEF_DMA_FILL_CONST() (REG32(ADR_DMA_FILL_CONST)) = (0x00000000)
++#define DEF_PMU_0() (REG32(ADR_PMU_0)) = (0x0f000040)
++#define DEF_PMU_1() (REG32(ADR_PMU_1)) = (0x015d015d)
++#define DEF_PMU_2() (REG32(ADR_PMU_2)) = (0x00000000)
++#define DEF_PMU_3() (REG32(ADR_PMU_3)) = (0x55550000)
++#define DEF_RTC_1() (REG32(ADR_RTC_1)) = (0x7fff0000)
++#define DEF_RTC_2() (REG32(ADR_RTC_2)) = (0x00000003)
++#define DEF_RTC_3W() (REG32(ADR_RTC_3W)) = (0x00000000)
++#define DEF_RTC_3R() (REG32(ADR_RTC_3R)) = (0x00000000)
++#define DEF_RTC_4() (REG32(ADR_RTC_4)) = (0x00000000)
++#define DEF_D2_DMA_ADR_SRC() (REG32(ADR_D2_DMA_ADR_SRC)) = (0x00000000)
++#define DEF_D2_DMA_ADR_DST() (REG32(ADR_D2_DMA_ADR_DST)) = (0x00000000)
++#define DEF_D2_DMA_CTRL() (REG32(ADR_D2_DMA_CTRL)) = (0x000000aa)
++#define DEF_D2_DMA_INT() (REG32(ADR_D2_DMA_INT)) = (0x00000001)
++#define DEF_D2_DMA_FILL_CONST() (REG32(ADR_D2_DMA_FILL_CONST)) = (0x00000000)
++#define DEF_CONTROL() (REG32(ADR_CONTROL)) = (0x02700008)
++#define DEF_SDIO_WAKE_MODE() (REG32(ADR_SDIO_WAKE_MODE)) = (0x00000000)
++#define DEF_TX_FLOW_0() (REG32(ADR_TX_FLOW_0)) = (0x00000000)
++#define DEF_TX_FLOW_1() (REG32(ADR_TX_FLOW_1)) = (0x00000000)
++#define DEF_THREASHOLD() (REG32(ADR_THREASHOLD)) = (0x09000000)
++#define DEF_TXFID_INCREASE() (REG32(ADR_TXFID_INCREASE)) = (0x00000000)
++#define DEF_GLOBAL_SEQUENCE() (REG32(ADR_GLOBAL_SEQUENCE)) = (0x00000000)
++#define DEF_HCI_TX_RX_INFO_SIZE() (REG32(ADR_HCI_TX_RX_INFO_SIZE)) = (0x00040450)
++#define DEF_HCI_TX_INFO_CLEAR() (REG32(ADR_HCI_TX_INFO_CLEAR)) = (0x00000008)
++#define DEF_TX_ETHER_TYPE_0() (REG32(ADR_TX_ETHER_TYPE_0)) = (0x00000000)
++#define DEF_TX_ETHER_TYPE_1() (REG32(ADR_TX_ETHER_TYPE_1)) = (0x00000000)
++#define DEF_RX_ETHER_TYPE_0() (REG32(ADR_RX_ETHER_TYPE_0)) = (0x00000000)
++#define DEF_RX_ETHER_TYPE_1() (REG32(ADR_RX_ETHER_TYPE_1)) = (0x00000000)
++#define DEF_PACKET_COUNTER_INFO_0() (REG32(ADR_PACKET_COUNTER_INFO_0)) = (0x00000000)
++#define DEF_PACKET_COUNTER_INFO_1() (REG32(ADR_PACKET_COUNTER_INFO_1)) = (0x00000000)
++#define DEF_PACKET_COUNTER_INFO_2() (REG32(ADR_PACKET_COUNTER_INFO_2)) = (0x00000000)
++#define DEF_PACKET_COUNTER_INFO_3() (REG32(ADR_PACKET_COUNTER_INFO_3)) = (0x00000000)
++#define DEF_PACKET_COUNTER_INFO_4() (REG32(ADR_PACKET_COUNTER_INFO_4)) = (0x00000000)
++#define DEF_PACKET_COUNTER_INFO_5() (REG32(ADR_PACKET_COUNTER_INFO_5)) = (0x00000000)
++#define DEF_PACKET_COUNTER_INFO_6() (REG32(ADR_PACKET_COUNTER_INFO_6)) = (0x00000000)
++#define DEF_PACKET_COUNTER_INFO_7() (REG32(ADR_PACKET_COUNTER_INFO_7)) = (0x00000000)
++#define DEF_SDIO_TX_RX_FAIL_COUNTER_0() (REG32(ADR_SDIO_TX_RX_FAIL_COUNTER_0)) = (0x00000000)
++#define DEF_SDIO_TX_RX_FAIL_COUNTER_1() (REG32(ADR_SDIO_TX_RX_FAIL_COUNTER_1)) = (0x00000000)
++#define DEF_HCI_STATE_DEBUG_MODE_0() (REG32(ADR_HCI_STATE_DEBUG_MODE_0)) = (0x00000000)
++#define DEF_HCI_STATE_DEBUG_MODE_1() (REG32(ADR_HCI_STATE_DEBUG_MODE_1)) = (0x00000000)
++#define DEF_HCI_STATE_DEBUG_MODE_2() (REG32(ADR_HCI_STATE_DEBUG_MODE_2)) = (0x00000000)
++#define DEF_HCI_STATE_DEBUG_MODE_3() (REG32(ADR_HCI_STATE_DEBUG_MODE_3)) = (0x00000000)
++#define DEF_HCI_STATE_DEBUG_MODE_4() (REG32(ADR_HCI_STATE_DEBUG_MODE_4)) = (0x00000000)
++#define DEF_HCI_STATE_DEBUG_MODE_5() (REG32(ADR_HCI_STATE_DEBUG_MODE_5)) = (0x00000000)
++#define DEF_HCI_STATE_DEBUG_MODE_6() (REG32(ADR_HCI_STATE_DEBUG_MODE_6)) = (0x00000000)
++#define DEF_HCI_STATE_DEBUG_MODE_7() (REG32(ADR_HCI_STATE_DEBUG_MODE_7)) = (0x00000000)
++#define DEF_HCI_STATE_DEBUG_MODE_8() (REG32(ADR_HCI_STATE_DEBUG_MODE_8)) = (0x00000000)
++#define DEF_HCI_STATE_DEBUG_MODE_9() (REG32(ADR_HCI_STATE_DEBUG_MODE_9)) = (0x00000000)
++#define DEF_HCI_STATE_DEBUG_MODE_10() (REG32(ADR_HCI_STATE_DEBUG_MODE_10)) = (0x00000000)
++#define DEF_CS_START_ADDR() (REG32(ADR_CS_START_ADDR)) = (0x00000000)
++#define DEF_CS_ADD_LEN() (REG32(ADR_CS_ADD_LEN)) = (0x00000000)
++#define DEF_CS_CMD() (REG32(ADR_CS_CMD)) = (0x00000000)
++#define DEF_CS_INI_BUF() (REG32(ADR_CS_INI_BUF)) = (0x00000000)
++#define DEF_CS_PSEUDO_BUF() (REG32(ADR_CS_PSEUDO_BUF)) = (0x00000000)
++#define DEF_CS_CHECK_SUM() (REG32(ADR_CS_CHECK_SUM)) = (0x00000000)
++#define DEF_RAND_EN() (REG32(ADR_RAND_EN)) = (0x00000000)
++#define DEF_RAND_NUM() (REG32(ADR_RAND_NUM)) = (0x00000000)
++#define DEF_MUL_OP1() (REG32(ADR_MUL_OP1)) = (0x00000000)
++#define DEF_MUL_OP2() (REG32(ADR_MUL_OP2)) = (0x00000000)
++#define DEF_MUL_ANS0() (REG32(ADR_MUL_ANS0)) = (0x00000000)
++#define DEF_MUL_ANS1() (REG32(ADR_MUL_ANS1)) = (0x00000000)
++#define DEF_DMA_RDATA() (REG32(ADR_DMA_RDATA)) = (0x00000000)
++#define DEF_DMA_WDATA() (REG32(ADR_DMA_WDATA)) = (0x00000000)
++#define DEF_DMA_LEN() (REG32(ADR_DMA_LEN)) = (0x00000000)
++#define DEF_DMA_CLR() (REG32(ADR_DMA_CLR)) = (0x00000000)
++#define DEF_NAV_DATA() (REG32(ADR_NAV_DATA)) = (0x00000000)
++#define DEF_CO_NAV() (REG32(ADR_CO_NAV)) = (0x00000000)
++#define DEF_SHA_DST_ADDR() (REG32(ADR_SHA_DST_ADDR)) = (0x00000000)
++#define DEF_SHA_SRC_ADDR() (REG32(ADR_SHA_SRC_ADDR)) = (0x00000000)
++#define DEF_SHA_SETTING() (REG32(ADR_SHA_SETTING)) = (0x00000002)
++#define DEF_EFUSE_CLK_FREQ() (REG32(ADR_EFUSE_CLK_FREQ)) = (0x610100d0)
++#define DEF_EFUSE_LDO_TIME() (REG32(ADR_EFUSE_LDO_TIME)) = (0x00020002)
++#define DEF_EFUSE_AHB_RDATA_0() (REG32(ADR_EFUSE_AHB_RDATA_0)) = (0x00000000)
++#define DEF_EFUSE_WDATA_0() (REG32(ADR_EFUSE_WDATA_0)) = (0x00000000)
++#define DEF_EFUSE_AHB_RDATA_1() (REG32(ADR_EFUSE_AHB_RDATA_1)) = (0x00000000)
++#define DEF_EFUSE_WDATA_1() (REG32(ADR_EFUSE_WDATA_1)) = (0x00000000)
++#define DEF_EFUSE_AHB_RDATA_2() (REG32(ADR_EFUSE_AHB_RDATA_2)) = (0x00000000)
++#define DEF_EFUSE_WDATA_2() (REG32(ADR_EFUSE_WDATA_2)) = (0x00000000)
++#define DEF_EFUSE_AHB_RDATA_3() (REG32(ADR_EFUSE_AHB_RDATA_3)) = (0x00000000)
++#define DEF_EFUSE_WDATA_3() (REG32(ADR_EFUSE_WDATA_3)) = (0x00000000)
++#define DEF_EFUSE_AHB_RDATA_4() (REG32(ADR_EFUSE_AHB_RDATA_4)) = (0x00000000)
++#define DEF_EFUSE_WDATA_4() (REG32(ADR_EFUSE_WDATA_4)) = (0x00000000)
++#define DEF_EFUSE_AHB_RDATA_5() (REG32(ADR_EFUSE_AHB_RDATA_5)) = (0x00000000)
++#define DEF_EFUSE_WDATA_5() (REG32(ADR_EFUSE_WDATA_5)) = (0x00000000)
++#define DEF_EFUSE_AHB_RDATA_6() (REG32(ADR_EFUSE_AHB_RDATA_6)) = (0x00000000)
++#define DEF_EFUSE_WDATA_6() (REG32(ADR_EFUSE_WDATA_6)) = (0x00000000)
++#define DEF_EFUSE_AHB_RDATA_7() (REG32(ADR_EFUSE_AHB_RDATA_7)) = (0x00000000)
++#define DEF_EFUSE_WDATA_7() (REG32(ADR_EFUSE_WDATA_7)) = (0x00000000)
++#define DEF_EFUSE_SPI_RD0_EN() (REG32(ADR_EFUSE_SPI_RD0_EN)) = (0x00000000)
++#define DEF_EFUSE_SPI_RD1_EN() (REG32(ADR_EFUSE_SPI_RD1_EN)) = (0x00000000)
++#define DEF_EFUSE_SPI_RD2_EN() (REG32(ADR_EFUSE_SPI_RD2_EN)) = (0x00000000)
++#define DEF_EFUSE_SPI_RD3_EN() (REG32(ADR_EFUSE_SPI_RD3_EN)) = (0x00000000)
++#define DEF_EFUSE_SPI_RD4_EN() (REG32(ADR_EFUSE_SPI_RD4_EN)) = (0x00000000)
++#define DEF_EFUSE_SPI_RD5_EN() (REG32(ADR_EFUSE_SPI_RD5_EN)) = (0x00000000)
++#define DEF_EFUSE_SPI_RD6_EN() (REG32(ADR_EFUSE_SPI_RD6_EN)) = (0x00000000)
++#define DEF_EFUSE_SPI_RD7_EN() (REG32(ADR_EFUSE_SPI_RD7_EN)) = (0x00000000)
++#define DEF_EFUSE_SPI_BUSY() (REG32(ADR_EFUSE_SPI_BUSY)) = (0x00000000)
++#define DEF_EFUSE_SPI_RDATA_0() (REG32(ADR_EFUSE_SPI_RDATA_0)) = (0x00000000)
++#define DEF_EFUSE_SPI_RDATA_1() (REG32(ADR_EFUSE_SPI_RDATA_1)) = (0x00000000)
++#define DEF_EFUSE_SPI_RDATA_2() (REG32(ADR_EFUSE_SPI_RDATA_2)) = (0x00000000)
++#define DEF_EFUSE_SPI_RDATA_3() (REG32(ADR_EFUSE_SPI_RDATA_3)) = (0x00000000)
++#define DEF_EFUSE_SPI_RDATA_4() (REG32(ADR_EFUSE_SPI_RDATA_4)) = (0x00000000)
++#define DEF_EFUSE_SPI_RDATA_5() (REG32(ADR_EFUSE_SPI_RDATA_5)) = (0x00000000)
++#define DEF_EFUSE_SPI_RDATA_6() (REG32(ADR_EFUSE_SPI_RDATA_6)) = (0x00000000)
++#define DEF_EFUSE_SPI_RDATA_7() (REG32(ADR_EFUSE_SPI_RDATA_7)) = (0x00000000)
++#define DEF_SMS4_CFG1() (REG32(ADR_SMS4_CFG1)) = (0x00000002)
++#define DEF_SMS4_CFG2() (REG32(ADR_SMS4_CFG2)) = (0x00000000)
++#define DEF_SMS4_MODE1() (REG32(ADR_SMS4_MODE1)) = (0x00000000)
++#define DEF_SMS4_TRIG() (REG32(ADR_SMS4_TRIG)) = (0x00000000)
++#define DEF_SMS4_STATUS1() (REG32(ADR_SMS4_STATUS1)) = (0x00000000)
++#define DEF_SMS4_STATUS2() (REG32(ADR_SMS4_STATUS2)) = (0x00000000)
++#define DEF_SMS4_DATA_IN0() (REG32(ADR_SMS4_DATA_IN0)) = (0x00000000)
++#define DEF_SMS4_DATA_IN1() (REG32(ADR_SMS4_DATA_IN1)) = (0x00000000)
++#define DEF_SMS4_DATA_IN2() (REG32(ADR_SMS4_DATA_IN2)) = (0x00000000)
++#define DEF_SMS4_DATA_IN3() (REG32(ADR_SMS4_DATA_IN3)) = (0x00000000)
++#define DEF_SMS4_DATA_OUT0() (REG32(ADR_SMS4_DATA_OUT0)) = (0x00000000)
++#define DEF_SMS4_DATA_OUT1() (REG32(ADR_SMS4_DATA_OUT1)) = (0x00000000)
++#define DEF_SMS4_DATA_OUT2() (REG32(ADR_SMS4_DATA_OUT2)) = (0x00000000)
++#define DEF_SMS4_DATA_OUT3() (REG32(ADR_SMS4_DATA_OUT3)) = (0x00000000)
++#define DEF_SMS4_KEY_0() (REG32(ADR_SMS4_KEY_0)) = (0x00000000)
++#define DEF_SMS4_KEY_1() (REG32(ADR_SMS4_KEY_1)) = (0x00000000)
++#define DEF_SMS4_KEY_2() (REG32(ADR_SMS4_KEY_2)) = (0x00000000)
++#define DEF_SMS4_KEY_3() (REG32(ADR_SMS4_KEY_3)) = (0x00000000)
++#define DEF_SMS4_MODE_IV0() (REG32(ADR_SMS4_MODE_IV0)) = (0x00000000)
++#define DEF_SMS4_MODE_IV1() (REG32(ADR_SMS4_MODE_IV1)) = (0x00000000)
++#define DEF_SMS4_MODE_IV2() (REG32(ADR_SMS4_MODE_IV2)) = (0x00000000)
++#define DEF_SMS4_MODE_IV3() (REG32(ADR_SMS4_MODE_IV3)) = (0x00000000)
++#define DEF_SMS4_OFB_ENC0() (REG32(ADR_SMS4_OFB_ENC0)) = (0x00000000)
++#define DEF_SMS4_OFB_ENC1() (REG32(ADR_SMS4_OFB_ENC1)) = (0x00000000)
++#define DEF_SMS4_OFB_ENC2() (REG32(ADR_SMS4_OFB_ENC2)) = (0x00000000)
++#define DEF_SMS4_OFB_ENC3() (REG32(ADR_SMS4_OFB_ENC3)) = (0x00000000)
++#define DEF_MRX_MCAST_TB0_0() (REG32(ADR_MRX_MCAST_TB0_0)) = (0x00000000)
++#define DEF_MRX_MCAST_TB0_1() (REG32(ADR_MRX_MCAST_TB0_1)) = (0x00000000)
++#define DEF_MRX_MCAST_MK0_0() (REG32(ADR_MRX_MCAST_MK0_0)) = (0x00000000)
++#define DEF_MRX_MCAST_MK0_1() (REG32(ADR_MRX_MCAST_MK0_1)) = (0x00000000)
++#define DEF_MRX_MCAST_CTRL0() (REG32(ADR_MRX_MCAST_CTRL0)) = (0x00000000)
++#define DEF_MRX_MCAST_TB1_0() (REG32(ADR_MRX_MCAST_TB1_0)) = (0x00000000)
++#define DEF_MRX_MCAST_TB1_1() (REG32(ADR_MRX_MCAST_TB1_1)) = (0x00000000)
++#define DEF_MRX_MCAST_MK1_0() (REG32(ADR_MRX_MCAST_MK1_0)) = (0x00000000)
++#define DEF_MRX_MCAST_MK1_1() (REG32(ADR_MRX_MCAST_MK1_1)) = (0x00000000)
++#define DEF_MRX_MCAST_CTRL1() (REG32(ADR_MRX_MCAST_CTRL1)) = (0x00000000)
++#define DEF_MRX_MCAST_TB2_0() (REG32(ADR_MRX_MCAST_TB2_0)) = (0x00000000)
++#define DEF_MRX_MCAST_TB2_1() (REG32(ADR_MRX_MCAST_TB2_1)) = (0x00000000)
++#define DEF_MRX_MCAST_MK2_0() (REG32(ADR_MRX_MCAST_MK2_0)) = (0x00000000)
++#define DEF_MRX_MCAST_MK2_1() (REG32(ADR_MRX_MCAST_MK2_1)) = (0x00000000)
++#define DEF_MRX_MCAST_CTRL2() (REG32(ADR_MRX_MCAST_CTRL2)) = (0x00000000)
++#define DEF_MRX_MCAST_TB3_0() (REG32(ADR_MRX_MCAST_TB3_0)) = (0x00000000)
++#define DEF_MRX_MCAST_TB3_1() (REG32(ADR_MRX_MCAST_TB3_1)) = (0x00000000)
++#define DEF_MRX_MCAST_MK3_0() (REG32(ADR_MRX_MCAST_MK3_0)) = (0x00000000)
++#define DEF_MRX_MCAST_MK3_1() (REG32(ADR_MRX_MCAST_MK3_1)) = (0x00000000)
++#define DEF_MRX_MCAST_CTRL3() (REG32(ADR_MRX_MCAST_CTRL3)) = (0x00000000)
++#define DEF_MRX_PHY_INFO() (REG32(ADR_MRX_PHY_INFO)) = (0x00000000)
++#define DEF_MRX_BA_DBG() (REG32(ADR_MRX_BA_DBG)) = (0x00000000)
++#define DEF_MRX_FLT_TB0() (REG32(ADR_MRX_FLT_TB0)) = (0x00003df5)
++#define DEF_MRX_FLT_TB1() (REG32(ADR_MRX_FLT_TB1)) = (0x000031f6)
++#define DEF_MRX_FLT_TB2() (REG32(ADR_MRX_FLT_TB2)) = (0x000035f9)
++#define DEF_MRX_FLT_TB3() (REG32(ADR_MRX_FLT_TB3)) = (0x000021c1)
++#define DEF_MRX_FLT_TB4() (REG32(ADR_MRX_FLT_TB4)) = (0x00004bf9)
++#define DEF_MRX_FLT_TB5() (REG32(ADR_MRX_FLT_TB5)) = (0x00004db1)
++#define DEF_MRX_FLT_TB6() (REG32(ADR_MRX_FLT_TB6)) = (0x000011fe)
++#define DEF_MRX_FLT_TB7() (REG32(ADR_MRX_FLT_TB7)) = (0x00000bfe)
++#define DEF_MRX_FLT_TB8() (REG32(ADR_MRX_FLT_TB8)) = (0x00000000)
++#define DEF_MRX_FLT_TB9() (REG32(ADR_MRX_FLT_TB9)) = (0x00000000)
++#define DEF_MRX_FLT_TB10() (REG32(ADR_MRX_FLT_TB10)) = (0x00000000)
++#define DEF_MRX_FLT_TB11() (REG32(ADR_MRX_FLT_TB11)) = (0x00000006)
++#define DEF_MRX_FLT_TB12() (REG32(ADR_MRX_FLT_TB12)) = (0x00000001)
++#define DEF_MRX_FLT_TB13() (REG32(ADR_MRX_FLT_TB13)) = (0x00000003)
++#define DEF_MRX_FLT_TB14() (REG32(ADR_MRX_FLT_TB14)) = (0x00000005)
++#define DEF_MRX_FLT_TB15() (REG32(ADR_MRX_FLT_TB15)) = (0x00000007)
++#define DEF_MRX_FLT_EN0() (REG32(ADR_MRX_FLT_EN0)) = (0x00002008)
++#define DEF_MRX_FLT_EN1() (REG32(ADR_MRX_FLT_EN1)) = (0x00001001)
++#define DEF_MRX_FLT_EN2() (REG32(ADR_MRX_FLT_EN2)) = (0x00000808)
++#define DEF_MRX_FLT_EN3() (REG32(ADR_MRX_FLT_EN3)) = (0x00001000)
++#define DEF_MRX_FLT_EN4() (REG32(ADR_MRX_FLT_EN4)) = (0x00002008)
++#define DEF_MRX_FLT_EN5() (REG32(ADR_MRX_FLT_EN5)) = (0x0000800e)
++#define DEF_MRX_FLT_EN6() (REG32(ADR_MRX_FLT_EN6)) = (0x00000838)
++#define DEF_MRX_FLT_EN7() (REG32(ADR_MRX_FLT_EN7)) = (0x00002008)
++#define DEF_MRX_FLT_EN8() (REG32(ADR_MRX_FLT_EN8)) = (0x00002008)
++#define DEF_MRX_LEN_FLT() (REG32(ADR_MRX_LEN_FLT)) = (0x00000000)
++#define DEF_RX_FLOW_DATA() (REG32(ADR_RX_FLOW_DATA)) = (0x00105034)
++#define DEF_RX_FLOW_MNG() (REG32(ADR_RX_FLOW_MNG)) = (0x00000004)
++#define DEF_RX_FLOW_CTRL() (REG32(ADR_RX_FLOW_CTRL)) = (0x00000004)
++#define DEF_RX_TIME_STAMP_CFG() (REG32(ADR_RX_TIME_STAMP_CFG)) = (0x00001c00)
++#define DEF_DBG_FF_FULL() (REG32(ADR_DBG_FF_FULL)) = (0x00000000)
++#define DEF_DBG_WFF_FULL() (REG32(ADR_DBG_WFF_FULL)) = (0x00000000)
++#define DEF_DBG_MB_FULL() (REG32(ADR_DBG_MB_FULL)) = (0x00000000)
++#define DEF_BA_CTRL() (REG32(ADR_BA_CTRL)) = (0x00000008)
++#define DEF_BA_TA_0() (REG32(ADR_BA_TA_0)) = (0x00000000)
++#define DEF_BA_TA_1() (REG32(ADR_BA_TA_1)) = (0x00000000)
++#define DEF_BA_TID() (REG32(ADR_BA_TID)) = (0x00000000)
++#define DEF_BA_ST_SEQ() (REG32(ADR_BA_ST_SEQ)) = (0x00000000)
++#define DEF_BA_SB0() (REG32(ADR_BA_SB0)) = (0x00000000)
++#define DEF_BA_SB1() (REG32(ADR_BA_SB1)) = (0x00000000)
++#define DEF_MRX_WATCH_DOG() (REG32(ADR_MRX_WATCH_DOG)) = (0x0000ffff)
++#define DEF_ACK_GEN_EN() (REG32(ADR_ACK_GEN_EN)) = (0x00000000)
++#define DEF_ACK_GEN_PARA() (REG32(ADR_ACK_GEN_PARA)) = (0x00000000)
++#define DEF_ACK_GEN_RA_0() (REG32(ADR_ACK_GEN_RA_0)) = (0x00000000)
++#define DEF_ACK_GEN_RA_1() (REG32(ADR_ACK_GEN_RA_1)) = (0x00000000)
++#define DEF_MIB_LEN_FAIL() (REG32(ADR_MIB_LEN_FAIL)) = (0x00000000)
++#define DEF_TRAP_HW_ID() (REG32(ADR_TRAP_HW_ID)) = (0x00000000)
++#define DEF_ID_IN_USE() (REG32(ADR_ID_IN_USE)) = (0x00000000)
++#define DEF_MRX_ERR() (REG32(ADR_MRX_ERR)) = (0x00000000)
++#define DEF_WSID0_TID0_RX_SEQ() (REG32(ADR_WSID0_TID0_RX_SEQ)) = (0x00000000)
++#define DEF_WSID0_TID1_RX_SEQ() (REG32(ADR_WSID0_TID1_RX_SEQ)) = (0x00000000)
++#define DEF_WSID0_TID2_RX_SEQ() (REG32(ADR_WSID0_TID2_RX_SEQ)) = (0x00000000)
++#define DEF_WSID0_TID3_RX_SEQ() (REG32(ADR_WSID0_TID3_RX_SEQ)) = (0x00000000)
++#define DEF_WSID0_TID4_RX_SEQ() (REG32(ADR_WSID0_TID4_RX_SEQ)) = (0x00000000)
++#define DEF_WSID0_TID5_RX_SEQ() (REG32(ADR_WSID0_TID5_RX_SEQ)) = (0x00000000)
++#define DEF_WSID0_TID6_RX_SEQ() (REG32(ADR_WSID0_TID6_RX_SEQ)) = (0x00000000)
++#define DEF_WSID0_TID7_RX_SEQ() (REG32(ADR_WSID0_TID7_RX_SEQ)) = (0x00000000)
++#define DEF_WSID1_TID0_RX_SEQ() (REG32(ADR_WSID1_TID0_RX_SEQ)) = (0x00000000)
++#define DEF_WSID1_TID1_RX_SEQ() (REG32(ADR_WSID1_TID1_RX_SEQ)) = (0x00000000)
++#define DEF_WSID1_TID2_RX_SEQ() (REG32(ADR_WSID1_TID2_RX_SEQ)) = (0x00000000)
++#define DEF_WSID1_TID3_RX_SEQ() (REG32(ADR_WSID1_TID3_RX_SEQ)) = (0x00000000)
++#define DEF_WSID1_TID4_RX_SEQ() (REG32(ADR_WSID1_TID4_RX_SEQ)) = (0x00000000)
++#define DEF_WSID1_TID5_RX_SEQ() (REG32(ADR_WSID1_TID5_RX_SEQ)) = (0x00000000)
++#define DEF_WSID1_TID6_RX_SEQ() (REG32(ADR_WSID1_TID6_RX_SEQ)) = (0x00000000)
++#define DEF_WSID1_TID7_RX_SEQ() (REG32(ADR_WSID1_TID7_RX_SEQ)) = (0x00000000)
++#define DEF_HDR_ADDR_SEL() (REG32(ADR_HDR_ADDR_SEL)) = (0x00003e79)
++#define DEF_FRAME_TYPE_CNTR_SET() (REG32(ADR_FRAME_TYPE_CNTR_SET)) = (0x00000000)
++#define DEF_PHY_INFO() (REG32(ADR_PHY_INFO)) = (0x00000000)
++#define DEF_AMPDU_SIG() (REG32(ADR_AMPDU_SIG)) = (0x0000004e)
++#define DEF_MIB_AMPDU() (REG32(ADR_MIB_AMPDU)) = (0x00000000)
++#define DEF_LEN_FLT() (REG32(ADR_LEN_FLT)) = (0x00000000)
++#define DEF_MIB_DELIMITER() (REG32(ADR_MIB_DELIMITER)) = (0x00000000)
++#define DEF_MTX_INT_STS() (REG32(ADR_MTX_INT_STS)) = (0x00000000)
++#define DEF_MTX_INT_EN() (REG32(ADR_MTX_INT_EN)) = (0x00000000)
++#define DEF_MTX_MISC_EN() (REG32(ADR_MTX_MISC_EN)) = (0x00c00c00)
++#define DEF_MTX_EDCCA_TOUT() (REG32(ADR_MTX_EDCCA_TOUT)) = (0x00000200)
++#define DEF_MTX_BCN_INT_STS() (REG32(ADR_MTX_BCN_INT_STS)) = (0x00000000)
++#define DEF_MTX_BCN_EN_INT() (REG32(ADR_MTX_BCN_EN_INT)) = (0x00000000)
++#define DEF_MTX_BCN_EN_MISC() (REG32(ADR_MTX_BCN_EN_MISC)) = (0x00000042)
++#define DEF_MTX_BCN_MISC() (REG32(ADR_MTX_BCN_MISC)) = (0x00000000)
++#define DEF_MTX_BCN_PRD() (REG32(ADR_MTX_BCN_PRD)) = (0x00000064)
++#define DEF_MTX_BCN_TSF_L() (REG32(ADR_MTX_BCN_TSF_L)) = (0x00000000)
++#define DEF_MTX_BCN_TSF_U() (REG32(ADR_MTX_BCN_TSF_U)) = (0x00000000)
++#define DEF_MTX_BCN_CFG0() (REG32(ADR_MTX_BCN_CFG0)) = (0x00000000)
++#define DEF_MTX_BCN_CFG1() (REG32(ADR_MTX_BCN_CFG1)) = (0x00000000)
++#define DEF_MTX_STATUS() (REG32(ADR_MTX_STATUS)) = (0x00000000)
++#define DEF_MTX_DBG_CTRL() (REG32(ADR_MTX_DBG_CTRL)) = (0x00000000)
++#define DEF_MTX_DBG_DAT0() (REG32(ADR_MTX_DBG_DAT0)) = (0x00000000)
++#define DEF_MTX_DBG_DAT1() (REG32(ADR_MTX_DBG_DAT1)) = (0x00000000)
++#define DEF_MTX_DBG_DAT2() (REG32(ADR_MTX_DBG_DAT2)) = (0x00000000)
++#define DEF_MTX_DUR_TOUT() (REG32(ADR_MTX_DUR_TOUT)) = (0x00002c2c)
++#define DEF_MTX_DUR_IFS() (REG32(ADR_MTX_DUR_IFS)) = (0x12d40a05)
++#define DEF_MTX_DUR_SIFS_G() (REG32(ADR_MTX_DUR_SIFS_G)) = (0x12c90100)
++#define DEF_MTX_DBG_DAT3() (REG32(ADR_MTX_DBG_DAT3)) = (0x00000000)
++#define DEF_MTX_NAV() (REG32(ADR_MTX_NAV)) = (0x00000000)
++#define DEF_MTX_MIB_WSID0() (REG32(ADR_MTX_MIB_WSID0)) = (0x00000000)
++#define DEF_MTX_MIB_WSID1() (REG32(ADR_MTX_MIB_WSID1)) = (0x00000000)
++#define DEF_MTX_DBG_DAT4() (REG32(ADR_MTX_DBG_DAT4)) = (0x00000000)
++#define DEF_TXQ0_MTX_Q_MISC_EN() (REG32(ADR_TXQ0_MTX_Q_MISC_EN)) = (0x00000000)
++#define DEF_TXQ0_MTX_Q_AIFSN() (REG32(ADR_TXQ0_MTX_Q_AIFSN)) = (0x0000a502)
++#define DEF_TXQ0_MTX_Q_BKF_CNT() (REG32(ADR_TXQ0_MTX_Q_BKF_CNT)) = (0x00000000)
++#define DEF_TXQ0_MTX_Q_RC_LIMIT() (REG32(ADR_TXQ0_MTX_Q_RC_LIMIT)) = (0x00000407)
++#define DEF_TXQ0_MTX_Q_ID_MAP_L() (REG32(ADR_TXQ0_MTX_Q_ID_MAP_L)) = (0x00000000)
++#define DEF_TXQ0_MTX_Q_TXOP_CH_THD() (REG32(ADR_TXQ0_MTX_Q_TXOP_CH_THD)) = (0x00000000)
++#define DEF_TXQ0_MTX_Q_TXOP_OV_THD() (REG32(ADR_TXQ0_MTX_Q_TXOP_OV_THD)) = (0x00000000)
++#define DEF_TXQ1_MTX_Q_MISC_EN() (REG32(ADR_TXQ1_MTX_Q_MISC_EN)) = (0x00000000)
++#define DEF_TXQ1_MTX_Q_AIFSN() (REG32(ADR_TXQ1_MTX_Q_AIFSN)) = (0x0000a502)
++#define DEF_TXQ1_MTX_Q_BKF_CNT() (REG32(ADR_TXQ1_MTX_Q_BKF_CNT)) = (0x00000000)
++#define DEF_TXQ1_MTX_Q_RC_LIMIT() (REG32(ADR_TXQ1_MTX_Q_RC_LIMIT)) = (0x00000407)
++#define DEF_TXQ1_MTX_Q_ID_MAP_L() (REG32(ADR_TXQ1_MTX_Q_ID_MAP_L)) = (0x00000000)
++#define DEF_TXQ1_MTX_Q_TXOP_CH_THD() (REG32(ADR_TXQ1_MTX_Q_TXOP_CH_THD)) = (0x00000000)
++#define DEF_TXQ1_MTX_Q_TXOP_OV_THD() (REG32(ADR_TXQ1_MTX_Q_TXOP_OV_THD)) = (0x00000000)
++#define DEF_TXQ2_MTX_Q_MISC_EN() (REG32(ADR_TXQ2_MTX_Q_MISC_EN)) = (0x00000000)
++#define DEF_TXQ2_MTX_Q_AIFSN() (REG32(ADR_TXQ2_MTX_Q_AIFSN)) = (0x0000a502)
++#define DEF_TXQ2_MTX_Q_BKF_CNT() (REG32(ADR_TXQ2_MTX_Q_BKF_CNT)) = (0x00000000)
++#define DEF_TXQ2_MTX_Q_RC_LIMIT() (REG32(ADR_TXQ2_MTX_Q_RC_LIMIT)) = (0x00000407)
++#define DEF_TXQ2_MTX_Q_ID_MAP_L() (REG32(ADR_TXQ2_MTX_Q_ID_MAP_L)) = (0x00000000)
++#define DEF_TXQ2_MTX_Q_TXOP_CH_THD() (REG32(ADR_TXQ2_MTX_Q_TXOP_CH_THD)) = (0x00000000)
++#define DEF_TXQ2_MTX_Q_TXOP_OV_THD() (REG32(ADR_TXQ2_MTX_Q_TXOP_OV_THD)) = (0x00000000)
++#define DEF_TXQ3_MTX_Q_MISC_EN() (REG32(ADR_TXQ3_MTX_Q_MISC_EN)) = (0x00000000)
++#define DEF_TXQ3_MTX_Q_AIFSN() (REG32(ADR_TXQ3_MTX_Q_AIFSN)) = (0x0000a502)
++#define DEF_TXQ3_MTX_Q_BKF_CNT() (REG32(ADR_TXQ3_MTX_Q_BKF_CNT)) = (0x00000000)
++#define DEF_TXQ3_MTX_Q_RC_LIMIT() (REG32(ADR_TXQ3_MTX_Q_RC_LIMIT)) = (0x00000407)
++#define DEF_TXQ3_MTX_Q_ID_MAP_L() (REG32(ADR_TXQ3_MTX_Q_ID_MAP_L)) = (0x00000000)
++#define DEF_TXQ3_MTX_Q_TXOP_CH_THD() (REG32(ADR_TXQ3_MTX_Q_TXOP_CH_THD)) = (0x00000000)
++#define DEF_TXQ3_MTX_Q_TXOP_OV_THD() (REG32(ADR_TXQ3_MTX_Q_TXOP_OV_THD)) = (0x00000000)
++#define DEF_TXQ4_MTX_Q_MISC_EN() (REG32(ADR_TXQ4_MTX_Q_MISC_EN)) = (0x00000000)
++#define DEF_TXQ4_MTX_Q_AIFSN() (REG32(ADR_TXQ4_MTX_Q_AIFSN)) = (0x0000a502)
++#define DEF_TXQ4_MTX_Q_BKF_CNT() (REG32(ADR_TXQ4_MTX_Q_BKF_CNT)) = (0x00000000)
++#define DEF_TXQ4_MTX_Q_RC_LIMIT() (REG32(ADR_TXQ4_MTX_Q_RC_LIMIT)) = (0x00000407)
++#define DEF_TXQ4_MTX_Q_ID_MAP_L() (REG32(ADR_TXQ4_MTX_Q_ID_MAP_L)) = (0x00000000)
++#define DEF_TXQ4_MTX_Q_TXOP_CH_THD() (REG32(ADR_TXQ4_MTX_Q_TXOP_CH_THD)) = (0x00000000)
++#define DEF_TXQ4_MTX_Q_TXOP_OV_THD() (REG32(ADR_TXQ4_MTX_Q_TXOP_OV_THD)) = (0x00000000)
++#define DEF_WSID0() (REG32(ADR_WSID0)) = (0x00000000)
++#define DEF_PEER_MAC0_0() (REG32(ADR_PEER_MAC0_0)) = (0x00000000)
++#define DEF_PEER_MAC0_1() (REG32(ADR_PEER_MAC0_1)) = (0x00000000)
++#define DEF_TX_ACK_POLICY_0_0() (REG32(ADR_TX_ACK_POLICY_0_0)) = (0x00000000)
++#define DEF_TX_SEQ_CTRL_0_0() (REG32(ADR_TX_SEQ_CTRL_0_0)) = (0x00000000)
++#define DEF_TX_ACK_POLICY_0_1() (REG32(ADR_TX_ACK_POLICY_0_1)) = (0x00000000)
++#define DEF_TX_SEQ_CTRL_0_1() (REG32(ADR_TX_SEQ_CTRL_0_1)) = (0x00000000)
++#define DEF_TX_ACK_POLICY_0_2() (REG32(ADR_TX_ACK_POLICY_0_2)) = (0x00000000)
++#define DEF_TX_SEQ_CTRL_0_2() (REG32(ADR_TX_SEQ_CTRL_0_2)) = (0x00000000)
++#define DEF_TX_ACK_POLICY_0_3() (REG32(ADR_TX_ACK_POLICY_0_3)) = (0x00000000)
++#define DEF_TX_SEQ_CTRL_0_3() (REG32(ADR_TX_SEQ_CTRL_0_3)) = (0x00000000)
++#define DEF_TX_ACK_POLICY_0_4() (REG32(ADR_TX_ACK_POLICY_0_4)) = (0x00000000)
++#define DEF_TX_SEQ_CTRL_0_4() (REG32(ADR_TX_SEQ_CTRL_0_4)) = (0x00000000)
++#define DEF_TX_ACK_POLICY_0_5() (REG32(ADR_TX_ACK_POLICY_0_5)) = (0x00000000)
++#define DEF_TX_SEQ_CTRL_0_5() (REG32(ADR_TX_SEQ_CTRL_0_5)) = (0x00000000)
++#define DEF_TX_ACK_POLICY_0_6() (REG32(ADR_TX_ACK_POLICY_0_6)) = (0x00000000)
++#define DEF_TX_SEQ_CTRL_0_6() (REG32(ADR_TX_SEQ_CTRL_0_6)) = (0x00000000)
++#define DEF_TX_ACK_POLICY_0_7() (REG32(ADR_TX_ACK_POLICY_0_7)) = (0x00000000)
++#define DEF_TX_SEQ_CTRL_0_7() (REG32(ADR_TX_SEQ_CTRL_0_7)) = (0x00000000)
++#define DEF_WSID1() (REG32(ADR_WSID1)) = (0x00000000)
++#define DEF_PEER_MAC1_0() (REG32(ADR_PEER_MAC1_0)) = (0x00000000)
++#define DEF_PEER_MAC1_1() (REG32(ADR_PEER_MAC1_1)) = (0x00000000)
++#define DEF_TX_ACK_POLICY_1_0() (REG32(ADR_TX_ACK_POLICY_1_0)) = (0x00000000)
++#define DEF_TX_SEQ_CTRL_1_0() (REG32(ADR_TX_SEQ_CTRL_1_0)) = (0x00000000)
++#define DEF_TX_ACK_POLICY_1_1() (REG32(ADR_TX_ACK_POLICY_1_1)) = (0x00000000)
++#define DEF_TX_SEQ_CTRL_1_1() (REG32(ADR_TX_SEQ_CTRL_1_1)) = (0x00000000)
++#define DEF_TX_ACK_POLICY_1_2() (REG32(ADR_TX_ACK_POLICY_1_2)) = (0x00000000)
++#define DEF_TX_SEQ_CTRL_1_2() (REG32(ADR_TX_SEQ_CTRL_1_2)) = (0x00000000)
++#define DEF_TX_ACK_POLICY_1_3() (REG32(ADR_TX_ACK_POLICY_1_3)) = (0x00000000)
++#define DEF_TX_SEQ_CTRL_1_3() (REG32(ADR_TX_SEQ_CTRL_1_3)) = (0x00000000)
++#define DEF_TX_ACK_POLICY_1_4() (REG32(ADR_TX_ACK_POLICY_1_4)) = (0x00000000)
++#define DEF_TX_SEQ_CTRL_1_4() (REG32(ADR_TX_SEQ_CTRL_1_4)) = (0x00000000)
++#define DEF_TX_ACK_POLICY_1_5() (REG32(ADR_TX_ACK_POLICY_1_5)) = (0x00000000)
++#define DEF_TX_SEQ_CTRL_1_5() (REG32(ADR_TX_SEQ_CTRL_1_5)) = (0x00000000)
++#define DEF_TX_ACK_POLICY_1_6() (REG32(ADR_TX_ACK_POLICY_1_6)) = (0x00000000)
++#define DEF_TX_SEQ_CTRL_1_6() (REG32(ADR_TX_SEQ_CTRL_1_6)) = (0x00000000)
++#define DEF_TX_ACK_POLICY_1_7() (REG32(ADR_TX_ACK_POLICY_1_7)) = (0x00000000)
++#define DEF_TX_SEQ_CTRL_1_7() (REG32(ADR_TX_SEQ_CTRL_1_7)) = (0x00000000)
++#define DEF_INFO0() (REG32(ADR_INFO0)) = (0x00000000)
++#define DEF_INFO1() (REG32(ADR_INFO1)) = (0x00000100)
++#define DEF_INFO2() (REG32(ADR_INFO2)) = (0x00000200)
++#define DEF_INFO3() (REG32(ADR_INFO3)) = (0x00000300)
++#define DEF_INFO4() (REG32(ADR_INFO4)) = (0x00000140)
++#define DEF_INFO5() (REG32(ADR_INFO5)) = (0x00000240)
++#define DEF_INFO6() (REG32(ADR_INFO6)) = (0x00000340)
++#define DEF_INFO7() (REG32(ADR_INFO7)) = (0x00000001)
++#define DEF_INFO8() (REG32(ADR_INFO8)) = (0x00000101)
++#define DEF_INFO9() (REG32(ADR_INFO9)) = (0x00000201)
++#define DEF_INFO10() (REG32(ADR_INFO10)) = (0x00000301)
++#define DEF_INFO11() (REG32(ADR_INFO11)) = (0x00000401)
++#define DEF_INFO12() (REG32(ADR_INFO12)) = (0x00000501)
++#define DEF_INFO13() (REG32(ADR_INFO13)) = (0x00000601)
++#define DEF_INFO14() (REG32(ADR_INFO14)) = (0x00000701)
++#define DEF_INFO15() (REG32(ADR_INFO15)) = (0x00030002)
++#define DEF_INFO16() (REG32(ADR_INFO16)) = (0x00030102)
++#define DEF_INFO17() (REG32(ADR_INFO17)) = (0x00030202)
++#define DEF_INFO18() (REG32(ADR_INFO18)) = (0x00030302)
++#define DEF_INFO19() (REG32(ADR_INFO19)) = (0x00030402)
++#define DEF_INFO20() (REG32(ADR_INFO20)) = (0x00030502)
++#define DEF_INFO21() (REG32(ADR_INFO21)) = (0x00030602)
++#define DEF_INFO22() (REG32(ADR_INFO22)) = (0x00030702)
++#define DEF_INFO23() (REG32(ADR_INFO23)) = (0x00030082)
++#define DEF_INFO24() (REG32(ADR_INFO24)) = (0x00030182)
++#define DEF_INFO25() (REG32(ADR_INFO25)) = (0x00030282)
++#define DEF_INFO26() (REG32(ADR_INFO26)) = (0x00030382)
++#define DEF_INFO27() (REG32(ADR_INFO27)) = (0x00030482)
++#define DEF_INFO28() (REG32(ADR_INFO28)) = (0x00030582)
++#define DEF_INFO29() (REG32(ADR_INFO29)) = (0x00030682)
++#define DEF_INFO30() (REG32(ADR_INFO30)) = (0x00030782)
++#define DEF_INFO31() (REG32(ADR_INFO31)) = (0x00030042)
++#define DEF_INFO32() (REG32(ADR_INFO32)) = (0x00030142)
++#define DEF_INFO33() (REG32(ADR_INFO33)) = (0x00030242)
++#define DEF_INFO34() (REG32(ADR_INFO34)) = (0x00030342)
++#define DEF_INFO35() (REG32(ADR_INFO35)) = (0x00030442)
++#define DEF_INFO36() (REG32(ADR_INFO36)) = (0x00030542)
++#define DEF_INFO37() (REG32(ADR_INFO37)) = (0x00030642)
++#define DEF_INFO38() (REG32(ADR_INFO38)) = (0x00030742)
++#define DEF_INFO_MASK() (REG32(ADR_INFO_MASK)) = (0x00007fc7)
++#define DEF_INFO_RATE_OFFSET() (REG32(ADR_INFO_RATE_OFFSET)) = (0x00040000)
++#define DEF_INFO_IDX_ADDR() (REG32(ADR_INFO_IDX_ADDR)) = (0x00000000)
++#define DEF_INFO_LEN_ADDR() (REG32(ADR_INFO_LEN_ADDR)) = (0x00000000)
++#define DEF_IC_TIME_TAG_0() (REG32(ADR_IC_TIME_TAG_0)) = (0x00000000)
++#define DEF_IC_TIME_TAG_1() (REG32(ADR_IC_TIME_TAG_1)) = (0x00000000)
++#define DEF_PACKET_ID_ALLOCATION_PRIORITY() (REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) = (0x00000000)
++#define DEF_MAC_MODE() (REG32(ADR_MAC_MODE)) = (0x00000000)
++#define DEF_ALL_SOFTWARE_RESET() (REG32(ADR_ALL_SOFTWARE_RESET)) = (0x00000000)
++#define DEF_ENG_SOFTWARE_RESET() (REG32(ADR_ENG_SOFTWARE_RESET)) = (0x00000000)
++#define DEF_CSR_SOFTWARE_RESET() (REG32(ADR_CSR_SOFTWARE_RESET)) = (0x00000000)
++#define DEF_MAC_CLOCK_ENABLE() (REG32(ADR_MAC_CLOCK_ENABLE)) = (0x00003efb)
++#define DEF_MAC_ENGINE_CLOCK_ENABLE() (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (0x0000f07b)
++#define DEF_MAC_CSR_CLOCK_ENABLE() (REG32(ADR_MAC_CSR_CLOCK_ENABLE)) = (0x0000ec02)
++#define DEF_GLBLE_SET() (REG32(ADR_GLBLE_SET)) = (0x000e5000)
++#define DEF_REASON_TRAP0() (REG32(ADR_REASON_TRAP0)) = (0x00000000)
++#define DEF_REASON_TRAP1() (REG32(ADR_REASON_TRAP1)) = (0x00000000)
++#define DEF_BSSID_0() (REG32(ADR_BSSID_0)) = (0x00000000)
++#define DEF_BSSID_1() (REG32(ADR_BSSID_1)) = (0x00000000)
++#define DEF_SCRT_STATE() (REG32(ADR_SCRT_STATE)) = (0x00000000)
++#define DEF_STA_MAC_0() (REG32(ADR_STA_MAC_0)) = (0x00000000)
++#define DEF_STA_MAC_1() (REG32(ADR_STA_MAC_1)) = (0x00000000)
++#define DEF_SCRT_SET() (REG32(ADR_SCRT_SET)) = (0x00000000)
++#define DEF_BTCX0() (REG32(ADR_BTCX0)) = (0x00000006)
++#define DEF_BTCX1() (REG32(ADR_BTCX1)) = (0x00000000)
++#define DEF_SWITCH_CTL() (REG32(ADR_SWITCH_CTL)) = (0x00000000)
++#define DEF_MIB_EN() (REG32(ADR_MIB_EN)) = (0x00000000)
++#define DEF_MTX_WSID0_SUCC() (REG32(ADR_MTX_WSID0_SUCC)) = (0x00000000)
++#define DEF_MTX_WSID0_FRM() (REG32(ADR_MTX_WSID0_FRM)) = (0x00000000)
++#define DEF_MTX_WSID0_RETRY() (REG32(ADR_MTX_WSID0_RETRY)) = (0x00000000)
++#define DEF_MTX_WSID0_TOTAL() (REG32(ADR_MTX_WSID0_TOTAL)) = (0x00000000)
++#define DEF_MTX_GROUP() (REG32(ADR_MTX_GROUP)) = (0x00000000)
++#define DEF_MTX_FAIL() (REG32(ADR_MTX_FAIL)) = (0x00000000)
++#define DEF_MTX_RETRY() (REG32(ADR_MTX_RETRY)) = (0x00000000)
++#define DEF_MTX_MULTI_RETRY() (REG32(ADR_MTX_MULTI_RETRY)) = (0x00000000)
++#define DEF_MTX_RTS_SUCCESS() (REG32(ADR_MTX_RTS_SUCCESS)) = (0x00000000)
++#define DEF_MTX_RTS_FAIL() (REG32(ADR_MTX_RTS_FAIL)) = (0x00000000)
++#define DEF_MTX_ACK_FAIL() (REG32(ADR_MTX_ACK_FAIL)) = (0x00000000)
++#define DEF_MTX_FRM() (REG32(ADR_MTX_FRM)) = (0x00000000)
++#define DEF_MTX_ACK_TX() (REG32(ADR_MTX_ACK_TX)) = (0x00000000)
++#define DEF_MTX_CTS_TX() (REG32(ADR_MTX_CTS_TX)) = (0x00000000)
++#define DEF_MRX_DUP_FRM() (REG32(ADR_MRX_DUP_FRM)) = (0x00000000)
++#define DEF_MRX_FRG_FRM() (REG32(ADR_MRX_FRG_FRM)) = (0x00000000)
++#define DEF_MRX_GROUP_FRM() (REG32(ADR_MRX_GROUP_FRM)) = (0x00000000)
++#define DEF_MRX_FCS_ERR() (REG32(ADR_MRX_FCS_ERR)) = (0x00000000)
++#define DEF_MRX_FCS_SUCC() (REG32(ADR_MRX_FCS_SUCC)) = (0x00000000)
++#define DEF_MRX_MISS() (REG32(ADR_MRX_MISS)) = (0x00000000)
++#define DEF_MRX_ALC_FAIL() (REG32(ADR_MRX_ALC_FAIL)) = (0x00000000)
++#define DEF_MRX_DAT_NTF() (REG32(ADR_MRX_DAT_NTF)) = (0x00000000)
++#define DEF_MRX_RTS_NTF() (REG32(ADR_MRX_RTS_NTF)) = (0x00000000)
++#define DEF_MRX_CTS_NTF() (REG32(ADR_MRX_CTS_NTF)) = (0x00000000)
++#define DEF_MRX_ACK_NTF() (REG32(ADR_MRX_ACK_NTF)) = (0x00000000)
++#define DEF_MRX_BA_NTF() (REG32(ADR_MRX_BA_NTF)) = (0x00000000)
++#define DEF_MRX_DATA_NTF() (REG32(ADR_MRX_DATA_NTF)) = (0x00000000)
++#define DEF_MRX_MNG_NTF() (REG32(ADR_MRX_MNG_NTF)) = (0x00000000)
++#define DEF_MRX_DAT_CRC_NTF() (REG32(ADR_MRX_DAT_CRC_NTF)) = (0x00000000)
++#define DEF_MRX_BAR_NTF() (REG32(ADR_MRX_BAR_NTF)) = (0x00000000)
++#define DEF_MRX_MB_MISS() (REG32(ADR_MRX_MB_MISS)) = (0x00000000)
++#define DEF_MRX_NIDLE_MISS() (REG32(ADR_MRX_NIDLE_MISS)) = (0x00000000)
++#define DEF_MRX_CSR_NTF() (REG32(ADR_MRX_CSR_NTF)) = (0x00000000)
++#define DEF_DBG_Q0_FRM_SUCCESS() (REG32(ADR_DBG_Q0_FRM_SUCCESS)) = (0x00000000)
++#define DEF_DBG_Q0_FRM_FAIL() (REG32(ADR_DBG_Q0_FRM_FAIL)) = (0x00000000)
++#define DEF_DBG_Q0_ACK_SUCCESS() (REG32(ADR_DBG_Q0_ACK_SUCCESS)) = (0x00000000)
++#define DEF_DBG_Q0_ACK_FAIL() (REG32(ADR_DBG_Q0_ACK_FAIL)) = (0x00000000)
++#define DEF_DBG_Q1_FRM_SUCCESS() (REG32(ADR_DBG_Q1_FRM_SUCCESS)) = (0x00000000)
++#define DEF_DBG_Q1_FRM_FAIL() (REG32(ADR_DBG_Q1_FRM_FAIL)) = (0x00000000)
++#define DEF_DBG_Q1_ACK_SUCCESS() (REG32(ADR_DBG_Q1_ACK_SUCCESS)) = (0x00000000)
++#define DEF_DBG_Q1_ACK_FAIL() (REG32(ADR_DBG_Q1_ACK_FAIL)) = (0x00000000)
++#define DEF_DBG_Q2_FRM_SUCCESS() (REG32(ADR_DBG_Q2_FRM_SUCCESS)) = (0x00000000)
++#define DEF_DBG_Q2_FRM_FAIL() (REG32(ADR_DBG_Q2_FRM_FAIL)) = (0x00000000)
++#define DEF_DBG_Q2_ACK_SUCCESS() (REG32(ADR_DBG_Q2_ACK_SUCCESS)) = (0x00000000)
++#define DEF_DBG_Q2_ACK_FAIL() (REG32(ADR_DBG_Q2_ACK_FAIL)) = (0x00000000)
++#define DEF_DBG_Q3_FRM_SUCCESS() (REG32(ADR_DBG_Q3_FRM_SUCCESS)) = (0x00000000)
++#define DEF_DBG_Q3_FRM_FAIL() (REG32(ADR_DBG_Q3_FRM_FAIL)) = (0x00000000)
++#define DEF_DBG_Q3_ACK_SUCCESS() (REG32(ADR_DBG_Q3_ACK_SUCCESS)) = (0x00000000)
++#define DEF_DBG_Q3_ACK_FAIL() (REG32(ADR_DBG_Q3_ACK_FAIL)) = (0x00000000)
++#define DEF_MIB_SCRT_TKIP0() (REG32(ADR_MIB_SCRT_TKIP0)) = (0x00000000)
++#define DEF_MIB_SCRT_TKIP1() (REG32(ADR_MIB_SCRT_TKIP1)) = (0x00000000)
++#define DEF_MIB_SCRT_TKIP2() (REG32(ADR_MIB_SCRT_TKIP2)) = (0x00000000)
++#define DEF_MIB_SCRT_CCMP0() (REG32(ADR_MIB_SCRT_CCMP0)) = (0x00000000)
++#define DEF_MIB_SCRT_CCMP1() (REG32(ADR_MIB_SCRT_CCMP1)) = (0x00000000)
++#define DEF_DBG_LEN_CRC_FAIL() (REG32(ADR_DBG_LEN_CRC_FAIL)) = (0x00000000)
++#define DEF_DBG_LEN_ALC_FAIL() (REG32(ADR_DBG_LEN_ALC_FAIL)) = (0x00000000)
++#define DEF_DBG_AMPDU_PASS() (REG32(ADR_DBG_AMPDU_PASS)) = (0x00000000)
++#define DEF_DBG_AMPDU_FAIL() (REG32(ADR_DBG_AMPDU_FAIL)) = (0x00000000)
++#define DEF_ID_ALC_FAIL1() (REG32(ADR_ID_ALC_FAIL1)) = (0x00000000)
++#define DEF_ID_ALC_FAIL2() (REG32(ADR_ID_ALC_FAIL2)) = (0x00000000)
++#define DEF_CBR_HARD_WIRE_PIN_REGISTER() (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (0x00004000)
++#define DEF_CBR_MANUAL_ENABLE_REGISTER() (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (0x00001fc0)
++#define DEF_CBR_LDO_REGISTER() (REG32(ADR_CBR_LDO_REGISTER)) = (0x2496db1b)
++#define DEF_CBR_ABB_REGISTER_1() (REG32(ADR_CBR_ABB_REGISTER_1)) = (0x151558dd)
++#define DEF_CBR_ABB_REGISTER_2() (REG32(ADR_CBR_ABB_REGISTER_2)) = (0x01011a88)
++#define DEF_CBR_TX_FE_REGISTER() (REG32(ADR_CBR_TX_FE_REGISTER)) = (0x3cbe84fe)
++#define DEF_CBR_RX_FE_REGISTER_1() (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (0x00657579)
++#define DEF_CBR_RX_FE_GAIN_DECODER_REGISTER_1() (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) = (0x000103a7)
++#define DEF_CBR_RX_FE_GAIN_DECODER_REGISTER_2() (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) = (0x000103a6)
++#define DEF_CBR_RX_FE_GAIN_DECODER_REGISTER_3() (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) = (0x00012001)
++#define DEF_CBR_RX_FE_GAIN_DECODER_REGISTER_4() (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) = (0x00036000)
++#define DEF_CBR_RX_FSM_REGISTER() (REG32(ADR_CBR_RX_FSM_REGISTER)) = (0x00000ca8)
++#define DEF_CBR_RX_ADC_REGISTER() (REG32(ADR_CBR_RX_ADC_REGISTER)) = (0x002a0224)
++#define DEF_CBR_TX_DAC_REGISTER() (REG32(ADR_CBR_TX_DAC_REGISTER)) = (0x00002655)
++#define DEF_CBR_SX_ENABLE_RGISTER() (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (0x0000647c)
++#define DEF_CBR_SYN_RGISTER_1() (REG32(ADR_CBR_SYN_RGISTER_1)) = (0xaa800000)
++#define DEF_CBR_SYN_RGISTER_2() (REG32(ADR_CBR_SYN_RGISTER_2)) = (0x00550800)
++#define DEF_CBR_SYN_PFD_CHP() (REG32(ADR_CBR_SYN_PFD_CHP)) = (0x07c0894a)
++#define DEF_CBR_SYN_VCO_LOBF() (REG32(ADR_CBR_SYN_VCO_LOBF)) = (0xfcccca27)
++#define DEF_CBR_SYN_DIV_SDM_XOSC() (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (0x2773c93c)
++#define DEF_CBR_SYN_LCK1() (REG32(ADR_CBR_SYN_LCK1)) = (0x00000a7c)
++#define DEF_CBR_SYN_LCK2() (REG32(ADR_CBR_SYN_LCK2)) = (0x01c67ff4)
++#define DEF_CBR_DPLL_VCO_REGISTER() (REG32(ADR_CBR_DPLL_VCO_REGISTER)) = (0x00103014)
++#define DEF_CBR_DPLL_CP_PFD_REGISTER() (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (0x0001848c)
++#define DEF_CBR_DPLL_DIVIDER_REGISTER() (REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) = (0x034061e0)
++#define DEF_CBR_DCOC_IDAC_REGISTER1() (REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) = (0x00820820)
++#define DEF_CBR_DCOC_IDAC_REGISTER2() (REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) = (0x00820820)
++#define DEF_CBR_DCOC_IDAC_REGISTER3() (REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) = (0x00820820)
++#define DEF_CBR_DCOC_IDAC_REGISTER4() (REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) = (0x00820820)
++#define DEF_CBR_DCOC_IDAC_REGISTER5() (REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) = (0x00820820)
++#define DEF_CBR_DCOC_IDAC_REGISTER6() (REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) = (0x00820820)
++#define DEF_CBR_DCOC_IDAC_REGISTER7() (REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) = (0x00820820)
++#define DEF_CBR_DCOC_IDAC_REGISTER8() (REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) = (0x00820820)
++#define DEF_CBR_RCAL_REGISTER() (REG32(ADR_CBR_RCAL_REGISTER)) = (0x00004080)
++#define DEF_CBR_MANUAL_REGISTER() (REG32(ADR_CBR_MANUAL_REGISTER)) = (0x00003e7e)
++#define DEF_CBR_TRX_DUMMY_REGISTER() (REG32(ADR_CBR_TRX_DUMMY_REGISTER)) = (0xaaaaaaaa)
++#define DEF_CBR_SX_DUMMY_REGISTER() (REG32(ADR_CBR_SX_DUMMY_REGISTER)) = (0xaaaaaaaa)
++#define DEF_CBR_RG_PKT_GEN_0() (REG32(ADR_CBR_RG_PKT_GEN_0)) = (0x00000000)
++#define DEF_CBR_RG_PKT_GEN_1() (REG32(ADR_CBR_RG_PKT_GEN_1)) = (0x00000000)
++#define DEF_CBR_RG_PKT_GEN_2() (REG32(ADR_CBR_RG_PKT_GEN_2)) = (0x00000000)
++#define DEF_CBR_RG_INTEGRATION() (REG32(ADR_CBR_RG_INTEGRATION)) = (0x00000000)
++#define DEF_CBR_RG_PKT_GEN_TXCNT() (REG32(ADR_CBR_RG_PKT_GEN_TXCNT)) = (0x00000000)
++#define DEF_CBR_PATTERN_GEN() (REG32(ADR_CBR_PATTERN_GEN)) = (0xff000000)
++#define DEF_MB_CPU_INT() (REG32(ADR_MB_CPU_INT)) = (0x00000000)
++#define DEF_CPU_ID_TB0() (REG32(ADR_CPU_ID_TB0)) = (0x00000000)
++#define DEF_CPU_ID_TB1() (REG32(ADR_CPU_ID_TB1)) = (0x00000000)
++#define DEF_CH0_TRIG_1() (REG32(ADR_CH0_TRIG_1)) = (0x00000000)
++#define DEF_CH0_TRIG_0() (REG32(ADR_CH0_TRIG_0)) = (0x00000000)
++#define DEF_CH0_PRI_TRIG() (REG32(ADR_CH0_PRI_TRIG)) = (0x00000000)
++#define DEF_MCU_STATUS() (REG32(ADR_MCU_STATUS)) = (0x00000000)
++#define DEF_RD_IN_FFCNT1() (REG32(ADR_RD_IN_FFCNT1)) = (0x00000000)
++#define DEF_RD_IN_FFCNT2() (REG32(ADR_RD_IN_FFCNT2)) = (0x00000000)
++#define DEF_RD_FFIN_FULL() (REG32(ADR_RD_FFIN_FULL)) = (0x00000000)
++#define DEF_MBOX_HALT_CFG() (REG32(ADR_MBOX_HALT_CFG)) = (0x00000000)
++#define DEF_MB_DBG_CFG1() (REG32(ADR_MB_DBG_CFG1)) = (0x00080000)
++#define DEF_MB_DBG_CFG2() (REG32(ADR_MB_DBG_CFG2)) = (0x00000000)
++#define DEF_MB_DBG_CFG3() (REG32(ADR_MB_DBG_CFG3)) = (0x00000000)
++#define DEF_MB_DBG_CFG4() (REG32(ADR_MB_DBG_CFG4)) = (0xffffffff)
++#define DEF_MB_OUT_QUEUE_CFG() (REG32(ADR_MB_OUT_QUEUE_CFG)) = (0x00000002)
++#define DEF_MB_OUT_QUEUE_FLUSH() (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (0x00000000)
++#define DEF_RD_FFOUT_CNT1() (REG32(ADR_RD_FFOUT_CNT1)) = (0x00000000)
++#define DEF_RD_FFOUT_CNT2() (REG32(ADR_RD_FFOUT_CNT2)) = (0x00000000)
++#define DEF_RD_FFOUT_CNT3() (REG32(ADR_RD_FFOUT_CNT3)) = (0x00000000)
++#define DEF_RD_FFOUT_FULL() (REG32(ADR_RD_FFOUT_FULL)) = (0x00000000)
++#define DEF_MB_THRESHOLD6() (REG32(ADR_MB_THRESHOLD6)) = (0x00000000)
++#define DEF_MB_THRESHOLD7() (REG32(ADR_MB_THRESHOLD7)) = (0x00000000)
++#define DEF_MB_THRESHOLD8() (REG32(ADR_MB_THRESHOLD8)) = (0x00000000)
++#define DEF_MB_THRESHOLD9() (REG32(ADR_MB_THRESHOLD9)) = (0x00000000)
++#define DEF_MB_THRESHOLD10() (REG32(ADR_MB_THRESHOLD10)) = (0x00000000)
++#define DEF_MB_TRASH_CFG() (REG32(ADR_MB_TRASH_CFG)) = (0x01000001)
++#define DEF_MB_IN_FF_FLUSH() (REG32(ADR_MB_IN_FF_FLUSH)) = (0x00000000)
++#define DEF_CPU_ID_TB2() (REG32(ADR_CPU_ID_TB2)) = (0x00000000)
++#define DEF_CPU_ID_TB3() (REG32(ADR_CPU_ID_TB3)) = (0x00000000)
++#define DEF_PHY_IQ_LOG_CFG0() (REG32(ADR_PHY_IQ_LOG_CFG0)) = (0x00000000)
++#define DEF_PHY_IQ_LOG_CFG1() (REG32(ADR_PHY_IQ_LOG_CFG1)) = (0x00000000)
++#define DEF_PHY_IQ_LOG_LEN() (REG32(ADR_PHY_IQ_LOG_LEN)) = (0x00001000)
++#define DEF_PHY_IQ_LOG_PTR() (REG32(ADR_PHY_IQ_LOG_PTR)) = (0x00000000)
++#define DEF_WR_ALC() (REG32(ADR_WR_ALC)) = (0x00000000)
++#define DEF_GETID() (REG32(ADR_GETID)) = (0x00000000)
++#define DEF_CH_STA_PRI() (REG32(ADR_CH_STA_PRI)) = (0x00000213)
++#define DEF_RD_ID0() (REG32(ADR_RD_ID0)) = (0x00000000)
++#define DEF_RD_ID1() (REG32(ADR_RD_ID1)) = (0x00000000)
++#define DEF_IMD_CFG() (REG32(ADR_IMD_CFG)) = (0x00000000)
++#define DEF_IMD_STA() (REG32(ADR_IMD_STA)) = (0x00000000)
++#define DEF_ALC_STA() (REG32(ADR_ALC_STA)) = (0x01000000)
++#define DEF_TRX_ID_COUNT() (REG32(ADR_TRX_ID_COUNT)) = (0x00000000)
++#define DEF_TRX_ID_THRESHOLD() (REG32(ADR_TRX_ID_THRESHOLD)) = (0x01ee3c3c)
++#define DEF_TX_ID0() (REG32(ADR_TX_ID0)) = (0x00000000)
++#define DEF_TX_ID1() (REG32(ADR_TX_ID1)) = (0x00000000)
++#define DEF_RX_ID0() (REG32(ADR_RX_ID0)) = (0x00000000)
++#define DEF_RX_ID1() (REG32(ADR_RX_ID1)) = (0x00000000)
++#define DEF_RTN_STA() (REG32(ADR_RTN_STA)) = (0x00000001)
++#define DEF_ID_LEN_THREADSHOLD1() (REG32(ADR_ID_LEN_THREADSHOLD1)) = (0x000f0641)
++#define DEF_ID_LEN_THREADSHOLD2() (REG32(ADR_ID_LEN_THREADSHOLD2)) = (0x00000000)
++#define DEF_CH_ARB_PRI() (REG32(ADR_CH_ARB_PRI)) = (0x00031201)
++#define DEF_TX_ID_REMAIN_STATUS() (REG32(ADR_TX_ID_REMAIN_STATUS)) = (0x00000000)
++#define DEF_ID_INFO_STA() (REG32(ADR_ID_INFO_STA)) = (0x00000100)
++#define DEF_TX_LIMIT_INTR() (REG32(ADR_TX_LIMIT_INTR)) = (0x00000000)
++#define DEF_TX_ID_ALL_INFO() (REG32(ADR_TX_ID_ALL_INFO)) = (0x00000000)
++#define DEF_RD_ID2() (REG32(ADR_RD_ID2)) = (0x00000000)
++#define DEF_RD_ID3() (REG32(ADR_RD_ID3)) = (0x00000000)
++#define DEF_TX_ID2() (REG32(ADR_TX_ID2)) = (0x00000000)
++#define DEF_TX_ID3() (REG32(ADR_TX_ID3)) = (0x00000000)
++#define DEF_RX_ID2() (REG32(ADR_RX_ID2)) = (0x00000000)
++#define DEF_RX_ID3() (REG32(ADR_RX_ID3)) = (0x00000000)
++#define DEF_TX_ID_ALL_INFO2() (REG32(ADR_TX_ID_ALL_INFO2)) = (0x00000000)
++#define DEF_TX_ID_ALL_INFO_A() (REG32(ADR_TX_ID_ALL_INFO_A)) = (0x00000000)
++#define DEF_TX_ID_ALL_INFO_B() (REG32(ADR_TX_ID_ALL_INFO_B)) = (0x00000000)
++#define DEF_TX_ID_REMAIN_STATUS2() (REG32(ADR_TX_ID_REMAIN_STATUS2)) = (0x01000100)
++#define DEF_ALC_ID_INFO() (REG32(ADR_ALC_ID_INFO)) = (0x00000000)
++#define DEF_ALC_ID_INF1() (REG32(ADR_ALC_ID_INF1)) = (0x00000000)
++#define DEF_PHY_EN_0() (REG32(ADR_PHY_EN_0)) = (0x00000014)
++#define DEF_PHY_EN_1() (REG32(ADR_PHY_EN_1)) = (0x00000000)
++#define DEF_SVN_VERSION_REG() (REG32(ADR_SVN_VERSION_REG)) = (0x00000000)
++#define DEF_PHY_PKT_GEN_0() (REG32(ADR_PHY_PKT_GEN_0)) = (0x00000064)
++#define DEF_PHY_PKT_GEN_1() (REG32(ADR_PHY_PKT_GEN_1)) = (0x00000fff)
++#define DEF_PHY_PKT_GEN_2() (REG32(ADR_PHY_PKT_GEN_2)) = (0x00000003)
++#define DEF_PHY_PKT_GEN_3() (REG32(ADR_PHY_PKT_GEN_3)) = (0x005a0220)
++#define DEF_PHY_PKT_GEN_4() (REG32(ADR_PHY_PKT_GEN_4)) = (0x00000001)
++#define DEF_PHY_REG_00() (REG32(ADR_PHY_REG_00)) = (0x10000000)
++#define DEF_PHY_REG_01() (REG32(ADR_PHY_REG_01)) = (0x00000000)
++#define DEF_PHY_REG_02_AGC() (REG32(ADR_PHY_REG_02_AGC)) = (0x80046771)
++#define DEF_PHY_REG_03_AGC() (REG32(ADR_PHY_REG_03_AGC)) = (0x1f300f6f)
++#define DEF_PHY_REG_04_AGC() (REG32(ADR_PHY_REG_04_AGC)) = (0x663f36d0)
++#define DEF_PHY_REG_05_AGC() (REG32(ADR_PHY_REG_05_AGC)) = (0x106c0000)
++#define DEF_PHY_REG_06_11B_DAGC() (REG32(ADR_PHY_REG_06_11B_DAGC)) = (0x01603fff)
++#define DEF_PHY_REG_07_11B_DAGC() (REG32(ADR_PHY_REG_07_11B_DAGC)) = (0x00600808)
++#define DEF_PHY_REG_08_11GN_DAGC() (REG32(ADR_PHY_REG_08_11GN_DAGC)) = (0xff000160)
++#define DEF_PHY_REG_09_11GN_DAGC() (REG32(ADR_PHY_REG_09_11GN_DAGC)) = (0x00080840)
++#define DEF_PHY_READ_REG_00_DIG_PWR() (REG32(ADR_PHY_READ_REG_00_DIG_PWR)) = (0x00000000)
++#define DEF_PHY_READ_REG_01_RF_GAIN_PWR() (REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) = (0x00000000)
++#define DEF_PHY_READ_REG_02_RF_GAIN_PWR() (REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) = (0x00000000)
++#define DEF_PHY_READ_REG_03_RF_GAIN_PWR() (REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) = (0x00000000)
++#define DEF_PHY_REG_10_TX_DES() (REG32(ADR_PHY_REG_10_TX_DES)) = (0x00010405)
++#define DEF_PHY_REG_11_TX_DES() (REG32(ADR_PHY_REG_11_TX_DES)) = (0x06090813)
++#define DEF_PHY_REG_12_TX_DES() (REG32(ADR_PHY_REG_12_TX_DES)) = (0x12070000)
++#define DEF_PHY_REG_13_RX_DES() (REG32(ADR_PHY_REG_13_RX_DES)) = (0x01000405)
++#define DEF_PHY_REG_14_RX_DES() (REG32(ADR_PHY_REG_14_RX_DES)) = (0x06090813)
++#define DEF_PHY_REG_15_RX_DES() (REG32(ADR_PHY_REG_15_RX_DES)) = (0x12010000)
++#define DEF_PHY_REG_16_TX_DES_EXCP() (REG32(ADR_PHY_REG_16_TX_DES_EXCP)) = (0x00000000)
++#define DEF_PHY_REG_17_TX_DES_EXCP() (REG32(ADR_PHY_REG_17_TX_DES_EXCP)) = (0x10110000)
++#define DEF_PHY_REG_18_RSSI_SNR() (REG32(ADR_PHY_REG_18_RSSI_SNR)) = (0x00fc000f)
++#define DEF_PHY_REG_19_DAC_MANUAL() (REG32(ADR_PHY_REG_19_DAC_MANUAL)) = (0x00000000)
++#define DEF_PHY_REG_20_MRX_CNT() (REG32(ADR_PHY_REG_20_MRX_CNT)) = (0x00000000)
++#define DEF_PHY_REG_21_TRX_RAMP() (REG32(ADR_PHY_REG_21_TRX_RAMP)) = (0x3c012801)
++#define DEF_PHY_REG_22_TRX_RAMP() (REG32(ADR_PHY_REG_22_TRX_RAMP)) = (0x24243724)
++#define DEF_PHY_REG_23_ANT() (REG32(ADR_PHY_REG_23_ANT)) = (0x00000011)
++#define DEF_PHY_REG_24_MTX_LEN_CNT() (REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) = (0x1fff0000)
++#define DEF_PHY_REG_25_MTX_LEN_CNT() (REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) = (0x1fff0000)
++#define DEF_PHY_REG_26_MRX_LEN_CNT() (REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) = (0x1fff0000)
++#define DEF_PHY_REG_27_MRX_LEN_CNT() (REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) = (0x1fff0000)
++#define DEF_PHY_READ_REG_04() (REG32(ADR_PHY_READ_REG_04)) = (0x00000000)
++#define DEF_PHY_READ_REG_05() (REG32(ADR_PHY_READ_REG_05)) = (0x00000000)
++#define DEF_PHY_REG_28_BIST() (REG32(ADR_PHY_REG_28_BIST)) = (0x0000fe3e)
++#define DEF_PHY_READ_REG_06_BIST() (REG32(ADR_PHY_READ_REG_06_BIST)) = (0x00000000)
++#define DEF_PHY_READ_REG_07_BIST() (REG32(ADR_PHY_READ_REG_07_BIST)) = (0x00000000)
++#define DEF_PHY_REG_29_MTRX_MAC() (REG32(ADR_PHY_REG_29_MTRX_MAC)) = (0xffffffff)
++#define DEF_PHY_READ_REG_08_MTRX_MAC() (REG32(ADR_PHY_READ_REG_08_MTRX_MAC)) = (0x00000000)
++#define DEF_PHY_READ_REG_09_MTRX_MAC() (REG32(ADR_PHY_READ_REG_09_MTRX_MAC)) = (0x00000000)
++#define DEF_PHY_REG_30_TX_UP_FIL() (REG32(ADR_PHY_REG_30_TX_UP_FIL)) = (0x0ead04f5)
++#define DEF_PHY_REG_31_TX_UP_FIL() (REG32(ADR_PHY_REG_31_TX_UP_FIL)) = (0x0fd60080)
++#define DEF_PHY_REG_32_TX_UP_FIL() (REG32(ADR_PHY_REG_32_TX_UP_FIL)) = (0x00000009)
++#define DEF_PHY_READ_TBUS() (REG32(ADR_PHY_READ_TBUS)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_00() (REG32(ADR_TX_11B_FIL_COEF_00)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_01() (REG32(ADR_TX_11B_FIL_COEF_01)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_02() (REG32(ADR_TX_11B_FIL_COEF_02)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_03() (REG32(ADR_TX_11B_FIL_COEF_03)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_04() (REG32(ADR_TX_11B_FIL_COEF_04)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_05() (REG32(ADR_TX_11B_FIL_COEF_05)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_06() (REG32(ADR_TX_11B_FIL_COEF_06)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_07() (REG32(ADR_TX_11B_FIL_COEF_07)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_08() (REG32(ADR_TX_11B_FIL_COEF_08)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_09() (REG32(ADR_TX_11B_FIL_COEF_09)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_10() (REG32(ADR_TX_11B_FIL_COEF_10)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_11() (REG32(ADR_TX_11B_FIL_COEF_11)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_12() (REG32(ADR_TX_11B_FIL_COEF_12)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_13() (REG32(ADR_TX_11B_FIL_COEF_13)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_14() (REG32(ADR_TX_11B_FIL_COEF_14)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_15() (REG32(ADR_TX_11B_FIL_COEF_15)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_16() (REG32(ADR_TX_11B_FIL_COEF_16)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_17() (REG32(ADR_TX_11B_FIL_COEF_17)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_18() (REG32(ADR_TX_11B_FIL_COEF_18)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_19() (REG32(ADR_TX_11B_FIL_COEF_19)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_20() (REG32(ADR_TX_11B_FIL_COEF_20)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_21() (REG32(ADR_TX_11B_FIL_COEF_21)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_22() (REG32(ADR_TX_11B_FIL_COEF_22)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_23() (REG32(ADR_TX_11B_FIL_COEF_23)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_24() (REG32(ADR_TX_11B_FIL_COEF_24)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_25() (REG32(ADR_TX_11B_FIL_COEF_25)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_26() (REG32(ADR_TX_11B_FIL_COEF_26)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_27() (REG32(ADR_TX_11B_FIL_COEF_27)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_28() (REG32(ADR_TX_11B_FIL_COEF_28)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_29() (REG32(ADR_TX_11B_FIL_COEF_29)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_30() (REG32(ADR_TX_11B_FIL_COEF_30)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_31() (REG32(ADR_TX_11B_FIL_COEF_31)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_32() (REG32(ADR_TX_11B_FIL_COEF_32)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_33() (REG32(ADR_TX_11B_FIL_COEF_33)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_34() (REG32(ADR_TX_11B_FIL_COEF_34)) = (0x00000000)
++#define DEF_TX_11B_FIL_COEF_35() (REG32(ADR_TX_11B_FIL_COEF_35)) = (0x00000005)
++#define DEF_TX_11B_FIL_COEF_36() (REG32(ADR_TX_11B_FIL_COEF_36)) = (0x0000003d)
++#define DEF_TX_11B_FIL_COEF_37() (REG32(ADR_TX_11B_FIL_COEF_37)) = (0x00000162)
++#define DEF_TX_11B_FIL_COEF_38() (REG32(ADR_TX_11B_FIL_COEF_38)) = (0x00000400)
++#define DEF_TX_11B_FIL_COEF_39() (REG32(ADR_TX_11B_FIL_COEF_39)) = (0x00000699)
++#define DEF_TX_11B_FIL_COEF_40() (REG32(ADR_TX_11B_FIL_COEF_40)) = (0x00000787)
++#define DEF_TX_11B_PLCP() (REG32(ADR_TX_11B_PLCP)) = (0x00000000)
++#define DEF_TX_11B_RAMP() (REG32(ADR_TX_11B_RAMP)) = (0x0000403c)
++#define DEF_TX_11B_EN_CNT_RST_N() (REG32(ADR_TX_11B_EN_CNT_RST_N)) = (0x00000001)
++#define DEF_TX_11B_EN_CNT() (REG32(ADR_TX_11B_EN_CNT)) = (0x00000000)
++#define DEF_TX_11B_PKT_GEN_CNT() (REG32(ADR_TX_11B_PKT_GEN_CNT)) = (0x00000000)
++#define DEF_RX_11B_DES_DLY() (REG32(ADR_RX_11B_DES_DLY)) = (0x00000044)
++#define DEF_RX_11B_CCA_0() (REG32(ADR_RX_11B_CCA_0)) = (0x00040000)
++#define DEF_RX_11B_CCA_1() (REG32(ADR_RX_11B_CCA_1)) = (0x00400040)
++#define DEF_RX_11B_TR_KP_KI_0() (REG32(ADR_RX_11B_TR_KP_KI_0)) = (0x00003467)
++#define DEF_RX_11B_TR_KP_KI_1() (REG32(ADR_RX_11B_TR_KP_KI_1)) = (0x00540000)
++#define DEF_RX_11B_CE_CNT_THRESHOLD() (REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) = (0x12243615)
++#define DEF_RX_11B_CE_MU_0() (REG32(ADR_RX_11B_CE_MU_0)) = (0x00390002)
++#define DEF_RX_11B_CE_MU_1() (REG32(ADR_RX_11B_CE_MU_1)) = (0x03456777)
++#define DEF_RX_11B_EQ_MU_0() (REG32(ADR_RX_11B_EQ_MU_0)) = (0x00350046)
++#define DEF_RX_11B_EQ_MU_1() (REG32(ADR_RX_11B_EQ_MU_1)) = (0x00570057)
++#define DEF_RX_11B_EQ_CR_KP_KI() (REG32(ADR_RX_11B_EQ_CR_KP_KI)) = (0x00236700)
++#define DEF_RX_11B_LPF_RATE() (REG32(ADR_RX_11B_LPF_RATE)) = (0x000d1746)
++#define DEF_RX_11B_CIT_CNT_THRESHOLD() (REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) = (0x04061787)
++#define DEF_RX_11B_EQ_CH_MAIN_TAP() (REG32(ADR_RX_11B_EQ_CH_MAIN_TAP)) = (0x07800000)
++#define DEF_RX_11B_SEARCH_CNT_TH() (REG32(ADR_RX_11B_SEARCH_CNT_TH)) = (0x00c0000a)
++#define DEF_RX_11B_CCA_CONTROL() (REG32(ADR_RX_11B_CCA_CONTROL)) = (0x00000000)
++#define DEF_RX_11B_FREQUENCY_OFFSET() (REG32(ADR_RX_11B_FREQUENCY_OFFSET)) = (0x00000000)
++#define DEF_RX_11B_SNR_RSSI() (REG32(ADR_RX_11B_SNR_RSSI)) = (0x00000000)
++#define DEF_RX_11B_SFD_CRC_CNT() (REG32(ADR_RX_11B_SFD_CRC_CNT)) = (0x00000000)
++#define DEF_RX_11B_PKT_ERR_AND_PKT_ERR_CNT() (REG32(ADR_RX_11B_PKT_ERR_AND_PKT_ERR_CNT)) = (0x00000000)
++#define DEF_RX_11B_PKT_CCA_AND_PKT_CNT() (REG32(ADR_RX_11B_PKT_CCA_AND_PKT_CNT)) = (0x00000000)
++#define DEF_RX_11B_SFD_FILED_0() (REG32(ADR_RX_11B_SFD_FILED_0)) = (0x00000000)
++#define DEF_RX_11B_SFD_FIELD_1() (REG32(ADR_RX_11B_SFD_FIELD_1)) = (0x00000000)
++#define DEF_RX_11B_PKT_STAT_EN() (REG32(ADR_RX_11B_PKT_STAT_EN)) = (0x00100000)
++#define DEF_RX_11B_SOFT_RST() (REG32(ADR_RX_11B_SOFT_RST)) = (0x00000001)
++#define DEF_TX_11GN_RAMP() (REG32(ADR_TX_11GN_RAMP)) = (0x0000233c)
++#define DEF_TX_11GN_PLCP() (REG32(ADR_TX_11GN_PLCP)) = (0x5d08908e)
++#define DEF_TX_11GN_PKT_GEN_CNT() (REG32(ADR_TX_11GN_PKT_GEN_CNT)) = (0x00000000)
++#define DEF_TX_11GN_PLCP_CRC_ERR_CNT() (REG32(ADR_TX_11GN_PLCP_CRC_ERR_CNT)) = (0x00000000)
++#define DEF_RX_11GN_DES_DLY() (REG32(ADR_RX_11GN_DES_DLY)) = (0x00000044)
++#define DEF_RX_11GN_TR_0() (REG32(ADR_RX_11GN_TR_0)) = (0x00750075)
++#define DEF_RX_11GN_TR_1() (REG32(ADR_RX_11GN_TR_1)) = (0x00000075)
++#define DEF_RX_11GN_TR_2() (REG32(ADR_RX_11GN_TR_2)) = (0x10000075)
++#define DEF_RX_11GN_CCA_0() (REG32(ADR_RX_11GN_CCA_0)) = (0x38324705)
++#define DEF_RX_11GN_CCA_1() (REG32(ADR_RX_11GN_CCA_1)) = (0x30182000)
++#define DEF_RX_11GN_CCA_2() (REG32(ADR_RX_11GN_CCA_2)) = (0x20600000)
++#define DEF_RX_11GN_CCA_FFT_SCALE() (REG32(ADR_RX_11GN_CCA_FFT_SCALE)) = (0x0a010100)
++#define DEF_RX_11GN_SOFT_DEMAP_0() (REG32(ADR_RX_11GN_SOFT_DEMAP_0)) = (0x50505050)
++#define DEF_RX_11GN_SOFT_DEMAP_1() (REG32(ADR_RX_11GN_SOFT_DEMAP_1)) = (0x50000000)
++#define DEF_RX_11GN_SOFT_DEMAP_2() (REG32(ADR_RX_11GN_SOFT_DEMAP_2)) = (0x50505050)
++#define DEF_RX_11GN_SOFT_DEMAP_3() (REG32(ADR_RX_11GN_SOFT_DEMAP_3)) = (0x50505050)
++#define DEF_RX_11GN_SOFT_DEMAP_4() (REG32(ADR_RX_11GN_SOFT_DEMAP_4)) = (0x50000000)
++#define DEF_RX_11GN_SOFT_DEMAP_5() (REG32(ADR_RX_11GN_SOFT_DEMAP_5)) = (0x00000000)
++#define DEF_RX_11GN_SYM_BOUND_0() (REG32(ADR_RX_11GN_SYM_BOUND_0)) = (0x00001420)
++#define DEF_RX_11GN_SYM_BOUND_1() (REG32(ADR_RX_11GN_SYM_BOUND_1)) = (0x0000200a)
++#define DEF_RX_11GN_CCA_PWR() (REG32(ADR_RX_11GN_CCA_PWR)) = (0x30000280)
++#define DEF_RX_11GN_CCA_CNT() (REG32(ADR_RX_11GN_CCA_CNT)) = (0x30023002)
++#define DEF_RX_11GN_CCA_ATCOR_RE_CHECK() (REG32(ADR_RX_11GN_CCA_ATCOR_RE_CHECK)) = (0x0000003a)
++#define DEF_RX_11GN_VTB_TB() (REG32(ADR_RX_11GN_VTB_TB)) = (0x40000000)
++#define DEF_RX_11GN_ERR_UPDATE() (REG32(ADR_RX_11GN_ERR_UPDATE)) = (0x009e007e)
++#define DEF_RX_11GN_SHORT_GI() (REG32(ADR_RX_11GN_SHORT_GI)) = (0x00044400)
++#define DEF_RX_11GN_CHANNEL_UPDATE() (REG32(ADR_RX_11GN_CHANNEL_UPDATE)) = (0x82000000)
++#define DEF_RX_11GN_PKT_FORMAT_0() (REG32(ADR_RX_11GN_PKT_FORMAT_0)) = (0x02003030)
++#define DEF_RX_11GN_PKT_FORMAT_1() (REG32(ADR_RX_11GN_PKT_FORMAT_1)) = (0x092a092a)
++#define DEF_RX_11GN_TX_TIME() (REG32(ADR_RX_11GN_TX_TIME)) = (0x00700010)
++#define DEF_RX_11GN_STBC_TR_KP_KI() (REG32(ADR_RX_11GN_STBC_TR_KP_KI)) = (0x00007575)
++#define DEF_RX_11GN_BIST_0() (REG32(ADR_RX_11GN_BIST_0)) = (0x0001fe3e)
++#define DEF_RX_11GN_BIST_1() (REG32(ADR_RX_11GN_BIST_1)) = (0x0000fe3e)
++#define DEF_RX_11GN_BIST_2() (REG32(ADR_RX_11GN_BIST_2)) = (0x00000000)
++#define DEF_RX_11GN_BIST_3() (REG32(ADR_RX_11GN_BIST_3)) = (0x00000000)
++#define DEF_RX_11GN_BIST_4() (REG32(ADR_RX_11GN_BIST_4)) = (0x00000000)
++#define DEF_RX_11GN_BIST_5() (REG32(ADR_RX_11GN_BIST_5)) = (0x00000000)
++#define DEF_RX_11GN_SPECTRUM_ANALYZER() (REG32(ADR_RX_11GN_SPECTRUM_ANALYZER)) = (0x00000000)
++#define DEF_RX_11GN_READ_0() (REG32(ADR_RX_11GN_READ_0)) = (0x00000000)
++#define DEF_RX_11GN_FREQ_OFFSET() (REG32(ADR_RX_11GN_FREQ_OFFSET)) = (0x00000000)
++#define DEF_RX_11GN_SIGNAL_FIELD_0() (REG32(ADR_RX_11GN_SIGNAL_FIELD_0)) = (0x00000000)
++#define DEF_RX_11GN_SIGNAL_FIELD_1() (REG32(ADR_RX_11GN_SIGNAL_FIELD_1)) = (0x00000000)
++#define DEF_RX_11GN_PKT_ERR_CNT() (REG32(ADR_RX_11GN_PKT_ERR_CNT)) = (0x00000000)
++#define DEF_RX_11GN_PKT_CCA_AND_PKT_CNT() (REG32(ADR_RX_11GN_PKT_CCA_AND_PKT_CNT)) = (0x00000000)
++#define DEF_RX_11GN_SERVICE_LENGTH_FIELD() (REG32(ADR_RX_11GN_SERVICE_LENGTH_FIELD)) = (0x00000000)
++#define DEF_RX_11GN_RATE() (REG32(ADR_RX_11GN_RATE)) = (0x00000000)
++#define DEF_RX_11GN_STAT_EN() (REG32(ADR_RX_11GN_STAT_EN)) = (0x00100001)
++#define DEF_RX_11GN_SOFT_RST() (REG32(ADR_RX_11GN_SOFT_RST)) = (0x00000001)
++#define DEF_RF_CONTROL_0() (REG32(ADR_RF_CONTROL_0)) = (0x00000000)
++#define DEF_RF_CONTROL_1() (REG32(ADR_RF_CONTROL_1)) = (0x00008000)
++#define DEF_TX_IQ_CONTROL_0() (REG32(ADR_TX_IQ_CONTROL_0)) = (0x00200020)
++#define DEF_TX_IQ_CONTROL_1() (REG32(ADR_TX_IQ_CONTROL_1)) = (0x00028080)
++#define DEF_TX_IQ_CONTROL_2() (REG32(ADR_TX_IQ_CONTROL_2)) = (0x00000000)
++#define DEF_TX_COMPENSATION_CONTROL() (REG32(ADR_TX_COMPENSATION_CONTROL)) = (0x00000000)
++#define DEF_RX_COMPENSATION_CONTROL() (REG32(ADR_RX_COMPENSATION_CONTROL)) = (0x00000000)
++#define DEF_RX_OBSERVATION_CIRCUIT_0() (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (0x000028ff)
++#define DEF_RX_OBSERVATION_CIRCUIT_1() (REG32(ADR_RX_OBSERVATION_CIRCUIT_1)) = (0x00000000)
++#define DEF_RX_OBSERVATION_CIRCUIT_2() (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (0x00000000)
++#define DEF_RX_OBSERVATION_CIRCUIT_3() (REG32(ADR_RX_OBSERVATION_CIRCUIT_3)) = (0x00000000)
++#define DEF_RF_IQ_CONTROL_0() (REG32(ADR_RF_IQ_CONTROL_0)) = (0x00000202)
++#define DEF_RF_IQ_CONTROL_1() (REG32(ADR_RF_IQ_CONTROL_1)) = (0x00ffc200)
++#define DEF_RF_IQ_CONTROL_2() (REG32(ADR_RF_IQ_CONTROL_2)) = (0x00000000)
++#define DEF_RF_IQ_CONTROL_3() (REG32(ADR_RF_IQ_CONTROL_3)) = (0x00000000)
++#define DEF_DPD_CONTROL() (REG32(ADR_DPD_CONTROL)) = (0x00000000)
++#define DEF_DPD_GAIN_TABLE_0() (REG32(ADR_DPD_GAIN_TABLE_0)) = (0x02000200)
++#define DEF_DPD_GAIN_TABLE_1() (REG32(ADR_DPD_GAIN_TABLE_1)) = (0x02000200)
++#define DEF_DPD_GAIN_TABLE_2() (REG32(ADR_DPD_GAIN_TABLE_2)) = (0x02000200)
++#define DEF_DPD_GAIN_TABLE_3() (REG32(ADR_DPD_GAIN_TABLE_3)) = (0x02000200)
++#define DEF_DPD_GAIN_TABLE_4() (REG32(ADR_DPD_GAIN_TABLE_4)) = (0x02000200)
++#define DEF_DPD_GAIN_TABLE_5() (REG32(ADR_DPD_GAIN_TABLE_5)) = (0x02000200)
++#define DEF_DPD_GAIN_TABLE_6() (REG32(ADR_DPD_GAIN_TABLE_6)) = (0x02000200)
++#define DEF_DPD_GAIN_TABLE_7() (REG32(ADR_DPD_GAIN_TABLE_7)) = (0x02000200)
++#define DEF_DPD_GAIN_TABLE_8() (REG32(ADR_DPD_GAIN_TABLE_8)) = (0x02000200)
++#define DEF_DPD_GAIN_TABLE_9() (REG32(ADR_DPD_GAIN_TABLE_9)) = (0x02000200)
++#define DEF_DPD_GAIN_TABLE_A() (REG32(ADR_DPD_GAIN_TABLE_A)) = (0x02000200)
++#define DEF_DPD_GAIN_TABLE_B() (REG32(ADR_DPD_GAIN_TABLE_B)) = (0x02000200)
++#define DEF_DPD_GAIN_TABLE_C() (REG32(ADR_DPD_GAIN_TABLE_C)) = (0x02000200)
++#define DEF_DPD_PH_TABLE_0() (REG32(ADR_DPD_PH_TABLE_0)) = (0x00000000)
++#define DEF_DPD_PH_TABLE_1() (REG32(ADR_DPD_PH_TABLE_1)) = (0x00000000)
++#define DEF_DPD_PH_TABLE_2() (REG32(ADR_DPD_PH_TABLE_2)) = (0x00000000)
++#define DEF_DPD_PH_TABLE_3() (REG32(ADR_DPD_PH_TABLE_3)) = (0x00000000)
++#define DEF_DPD_PH_TABLE_4() (REG32(ADR_DPD_PH_TABLE_4)) = (0x00000000)
++#define DEF_DPD_PH_TABLE_5() (REG32(ADR_DPD_PH_TABLE_5)) = (0x00000000)
++#define DEF_DPD_PH_TABLE_6() (REG32(ADR_DPD_PH_TABLE_6)) = (0x00000000)
++#define DEF_DPD_PH_TABLE_7() (REG32(ADR_DPD_PH_TABLE_7)) = (0x00000000)
++#define DEF_DPD_PH_TABLE_8() (REG32(ADR_DPD_PH_TABLE_8)) = (0x00000000)
++#define DEF_DPD_PH_TABLE_9() (REG32(ADR_DPD_PH_TABLE_9)) = (0x00000000)
++#define DEF_DPD_PH_TABLE_A() (REG32(ADR_DPD_PH_TABLE_A)) = (0x00000000)
++#define DEF_DPD_PH_TABLE_B() (REG32(ADR_DPD_PH_TABLE_B)) = (0x00000000)
++#define DEF_DPD_PH_TABLE_C() (REG32(ADR_DPD_PH_TABLE_C)) = (0x00000000)
++#define DEF_DPD_GAIN_ESTIMATION_0() (REG32(ADR_DPD_GAIN_ESTIMATION_0)) = (0x00000000)
++#define DEF_DPD_GAIN_ESTIMATION_1() (REG32(ADR_DPD_GAIN_ESTIMATION_1)) = (0x00000100)
++#define DEF_DPD_GAIN_ESTIMATION_2() (REG32(ADR_DPD_GAIN_ESTIMATION_2)) = (0x00000000)
++#define DEF_TX_GAIN_FACTOR() (REG32(ADR_TX_GAIN_FACTOR)) = (0x80808080)
++#define DEF_HARD_WIRE_PIN_REGISTER() (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (0x00004000)
++#define DEF_MANUAL_ENABLE_REGISTER() (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (0x00000fc0)
++#define DEF_LDO_REGISTER() (REG32(ADR_LDO_REGISTER)) = (0x000db71b)
++#define DEF_ABB_REGISTER_1() (REG32(ADR_ABB_REGISTER_1)) = (0x151558dd)
++#define DEF_ABB_REGISTER_2() (REG32(ADR_ABB_REGISTER_2)) = (0x01011a88)
++#define DEF_TX_FE_REGISTER() (REG32(ADR_TX_FE_REGISTER)) = (0x3d3e84fe)
++#define DEF_RX_FE_REGISTER_1() (REG32(ADR_RX_FE_REGISTER_1)) = (0x03457579)
++#define DEF_RX_FE_GAIN_DECODER_REGISTER_1() (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) = (0x000103a7)
++#define DEF_RX_FE_GAIN_DECODER_REGISTER_2() (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) = (0x000103a6)
++#define DEF_RX_FE_GAIN_DECODER_REGISTER_3() (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) = (0x00012001)
++#define DEF_RX_FE_GAIN_DECODER_REGISTER_4() (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) = (0x00036000)
++#define DEF_RX_TX_FSM_REGISTER() (REG32(ADR_RX_TX_FSM_REGISTER)) = (0x00030ca8)
++#define DEF_RX_ADC_REGISTER() (REG32(ADR_RX_ADC_REGISTER)) = (0x20ea0224)
++#define DEF_TX_DAC_REGISTER() (REG32(ADR_TX_DAC_REGISTER)) = (0x44000655)
++#define DEF_SX_ENABLE_REGISTER() (REG32(ADR_SX_ENABLE_REGISTER)) = (0x0003e07c)
++#define DEF_SYN_REGISTER_1() (REG32(ADR_SYN_REGISTER_1)) = (0xaa800000)
++#define DEF_SYN_REGISTER_2() (REG32(ADR_SYN_REGISTER_2)) = (0x00550800)
++#define DEF_SYN_PFD_CHP() (REG32(ADR_SYN_PFD_CHP)) = (0x07c0894a)
++#define DEF_SYN_VCO_LOBF() (REG32(ADR_SYN_VCO_LOBF)) = (0xfcccca27)
++#define DEF_SYN_DIV_SDM_XOSC() (REG32(ADR_SYN_DIV_SDM_XOSC)) = (0x07700830)
++#define DEF_SYN_KVCO_XO_FINE_TUNE_CBANK() (REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) = (0x00440000)
++#define DEF_SYN_LCK_VT() (REG32(ADR_SYN_LCK_VT)) = (0x00007ff4)
++#define DEF_DPLL_VCO_REGISTER() (REG32(ADR_DPLL_VCO_REGISTER)) = (0x0000000e)
++#define DEF_DPLL_CP_PFD_REGISTER() (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (0x00088008)
++#define DEF_DPLL_DIVIDER_REGISTER() (REG32(ADR_DPLL_DIVIDER_REGISTER)) = (0x00406000)
++#define DEF_DCOC_IDAC_REGISTER1() (REG32(ADR_DCOC_IDAC_REGISTER1)) = (0x08820820)
++#define DEF_DCOC_IDAC_REGISTER2() (REG32(ADR_DCOC_IDAC_REGISTER2)) = (0x00820820)
++#define DEF_DCOC_IDAC_REGISTER3() (REG32(ADR_DCOC_IDAC_REGISTER3)) = (0x00820820)
++#define DEF_DCOC_IDAC_REGISTER4() (REG32(ADR_DCOC_IDAC_REGISTER4)) = (0x00820820)
++#define DEF_DCOC_IDAC_REGISTER5() (REG32(ADR_DCOC_IDAC_REGISTER5)) = (0x00820820)
++#define DEF_DCOC_IDAC_REGISTER6() (REG32(ADR_DCOC_IDAC_REGISTER6)) = (0x00820820)
++#define DEF_DCOC_IDAC_REGISTER7() (REG32(ADR_DCOC_IDAC_REGISTER7)) = (0x00820820)
++#define DEF_DCOC_IDAC_REGISTER8() (REG32(ADR_DCOC_IDAC_REGISTER8)) = (0x00820820)
++#define DEF_RCAL_REGISTER() (REG32(ADR_RCAL_REGISTER)) = (0x00004080)
++#define DEF_SX_LCK_BIN_REGISTERS_I() (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (0x20080080)
++#define DEF_TRX_DUMMY_REGISTER() (REG32(ADR_TRX_DUMMY_REGISTER)) = (0xaaaaaaaa)
++#define DEF_SX_DUMMY_REGISTER() (REG32(ADR_SX_DUMMY_REGISTER)) = (0xaaaaaaaa)
++#define DEF_DPLL_FB_DIVIDER_REGISTERS_II() (REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_II)) = (0x00ec2ec5)
++#define DEF_SX_LCK_BIN_REGISTERS_II() (REG32(ADR_SX_LCK_BIN_REGISTERS_II)) = (0x00000f13)
++#define DEF_RC_OSC_32K_CAL_REGISTERS() (REG32(ADR_RC_OSC_32K_CAL_REGISTERS)) = (0x00098900)
++#define DEF_RF_D_DIGITAL_DEBUG_PORT_REGISTER() (REG32(ADR_RF_D_DIGITAL_DEBUG_PORT_REGISTER)) = (0x00000000)
++#define DEF_MMU_CTRL() (REG32(ADR_MMU_CTRL)) = (0x00002042)
++#define DEF_HS_CTRL() (REG32(ADR_HS_CTRL)) = (0x00000000)
++#define DEF_CPU_POR0_7() (REG32(ADR_CPU_POR0_7)) = (0x00000000)
++#define DEF_CPU_POR8_F() (REG32(ADR_CPU_POR8_F)) = (0x00000000)
++#define DEF_REG_LEN_CTRL() (REG32(ADR_REG_LEN_CTRL)) = (0x00000f0f)
++#define DEF_DMN_READ_BYPASS() (REG32(ADR_DMN_READ_BYPASS)) = (0x0000ffff)
++#define DEF_ALC_RLS_ABORT() (REG32(ADR_ALC_RLS_ABORT)) = (0x00000000)
++#define DEF_DEBUG_CTL() (REG32(ADR_DEBUG_CTL)) = (0x00000000)
++#define DEF_DEBUG_OUT() (REG32(ADR_DEBUG_OUT)) = (0x00000000)
++#define DEF_MMU_STATUS() (REG32(ADR_MMU_STATUS)) = (0x00000000)
++#define DEF_DMN_STATUS() (REG32(ADR_DMN_STATUS)) = (0x00000000)
++#define DEF_TAG_STATUS() (REG32(ADR_TAG_STATUS)) = (0x00000000)
++#define DEF_DMN_MCU_STATUS() (REG32(ADR_DMN_MCU_STATUS)) = (0x00000000)
++#define DEF_MB_IDTBL_0_STATUS() (REG32(ADR_MB_IDTBL_0_STATUS)) = (0x00000000)
++#define DEF_MB_IDTBL_1_STATUS() (REG32(ADR_MB_IDTBL_1_STATUS)) = (0x00000000)
++#define DEF_MB_IDTBL_2_STATUS() (REG32(ADR_MB_IDTBL_2_STATUS)) = (0x00000000)
++#define DEF_MB_IDTBL_3_STATUS() (REG32(ADR_MB_IDTBL_3_STATUS)) = (0x00000000)
++#define DEF_PKT_IDTBL_0_STATUS() (REG32(ADR_PKT_IDTBL_0_STATUS)) = (0x00000000)
++#define DEF_PKT_IDTBL_1_STATUS() (REG32(ADR_PKT_IDTBL_1_STATUS)) = (0x00000000)
++#define DEF_PKT_IDTBL_2_STATUS() (REG32(ADR_PKT_IDTBL_2_STATUS)) = (0x00000000)
++#define DEF_PKT_IDTBL_3_STATUS() (REG32(ADR_PKT_IDTBL_3_STATUS)) = (0x00000000)
++#define DEF_DMN_IDTBL_0_STATUS() (REG32(ADR_DMN_IDTBL_0_STATUS)) = (0x00000000)
++#define DEF_DMN_IDTBL_1_STATUS() (REG32(ADR_DMN_IDTBL_1_STATUS)) = (0x00000000)
++#define DEF_DMN_IDTBL_2_STATUS() (REG32(ADR_DMN_IDTBL_2_STATUS)) = (0x00000000)
++#define DEF_DMN_IDTBL_3_STATUS() (REG32(ADR_DMN_IDTBL_3_STATUS)) = (0x00000000)
++#define DEF_MB_NEQID_0_STATUS() (REG32(ADR_MB_NEQID_0_STATUS)) = (0x00000000)
++#define DEF_MB_NEQID_1_STATUS() (REG32(ADR_MB_NEQID_1_STATUS)) = (0x00000000)
++#define DEF_MB_NEQID_2_STATUS() (REG32(ADR_MB_NEQID_2_STATUS)) = (0x00000000)
++#define DEF_MB_NEQID_3_STATUS() (REG32(ADR_MB_NEQID_3_STATUS)) = (0x00000000)
++#define DEF_PKT_NEQID_0_STATUS() (REG32(ADR_PKT_NEQID_0_STATUS)) = (0x00000000)
++#define DEF_PKT_NEQID_1_STATUS() (REG32(ADR_PKT_NEQID_1_STATUS)) = (0x00000000)
++#define DEF_PKT_NEQID_2_STATUS() (REG32(ADR_PKT_NEQID_2_STATUS)) = (0x00000000)
++#define DEF_PKT_NEQID_3_STATUS() (REG32(ADR_PKT_NEQID_3_STATUS)) = (0x00000000)
++#define DEF_ALC_NOCHG_ID_STATUS() (REG32(ADR_ALC_NOCHG_ID_STATUS)) = (0x00000000)
++#define DEF_TAG_SRAM0_F_STATUS_0() (REG32(ADR_TAG_SRAM0_F_STATUS_0)) = (0x00000000)
++#define DEF_TAG_SRAM0_F_STATUS_1() (REG32(ADR_TAG_SRAM0_F_STATUS_1)) = (0x00000000)
++#define DEF_TAG_SRAM0_F_STATUS_2() (REG32(ADR_TAG_SRAM0_F_STATUS_2)) = (0x00000000)
++#define DEF_TAG_SRAM0_F_STATUS_3() (REG32(ADR_TAG_SRAM0_F_STATUS_3)) = (0x00000000)
++#define DEF_TAG_SRAM0_F_STATUS_4() (REG32(ADR_TAG_SRAM0_F_STATUS_4)) = (0x00000000)
++#define DEF_TAG_SRAM0_F_STATUS_5() (REG32(ADR_TAG_SRAM0_F_STATUS_5)) = (0x00000000)
++#define DEF_TAG_SRAM0_F_STATUS_6() (REG32(ADR_TAG_SRAM0_F_STATUS_6)) = (0x00000000)
++#define DEF_TAG_SRAM0_F_STATUS_7() (REG32(ADR_TAG_SRAM0_F_STATUS_7)) = (0x00000000)
+diff --git a/drivers/net/wireless/ssv6051/include/ssv6200_reg_sim.h b/drivers/net/wireless/ssv6051/include/ssv6200_reg_sim.h
+new file mode 100644
+index 000000000000..e15a481ba300
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/include/ssv6200_reg_sim.h
+@@ -0,0 +1,176 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation, either version 3 of the License, or
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include "ssv6200_reg.h"
++#define BANK_COUNT 49
++static const u32 BASE_BANK_SSV6200[] = {
++	SYS_REG_BASE,
++	WBOOT_REG_BASE,
++	TU0_US_REG_BASE,
++	TU1_US_REG_BASE,
++	TU2_US_REG_BASE,
++	TU3_US_REG_BASE,
++	TM0_MS_REG_BASE,
++	TM1_MS_REG_BASE,
++	TM2_MS_REG_BASE,
++	TM3_MS_REG_BASE,
++	MCU_WDT_REG_BASE,
++	SYS_WDT_REG_BASE,
++	GPIO_REG_BASE,
++	SD_REG_BASE,
++	SPI_REG_BASE,
++	CSR_I2C_MST_BASE,
++	UART_REG_BASE,
++	DAT_UART_REG_BASE,
++	INT_REG_BASE,
++	DBG_SPI_REG_BASE,
++	FLASH_SPI_REG_BASE,
++	DMA_REG_BASE,
++	CSR_PMU_BASE,
++	CSR_RTC_BASE,
++	RTC_RAM_BASE,
++	D2_DMA_REG_BASE,
++	HCI_REG_BASE,
++	CO_REG_BASE,
++	EFS_REG_BASE,
++	SMS4_REG_BASE,
++	MRX_REG_BASE,
++	AMPDU_REG_BASE,
++	MT_REG_CSR_BASE,
++	TXQ0_MT_Q_REG_CSR_BASE,
++	TXQ1_MT_Q_REG_CSR_BASE,
++	TXQ2_MT_Q_REG_CSR_BASE,
++	TXQ3_MT_Q_REG_CSR_BASE,
++	TXQ4_MT_Q_REG_CSR_BASE,
++	HIF_INFO_BASE,
++	PHY_RATE_INFO_BASE,
++	MAC_GLB_SET_BASE,
++	BTCX_REG_BASE,
++	MIB_REG_BASE,
++	CBR_A_REG_BASE,
++	MB_REG_BASE,
++	ID_MNG_REG_BASE,
++	CSR_PHY_BASE,
++	CSR_RF_BASE,
++	MMU_REG_BASE,
++	0x00000000
++};
++
++static const char *STR_BANK_SSV6200[] = {
++	"SYS_REG",
++	"WBOOT_REG",
++	"TU0_US_REG",
++	"TU1_US_REG",
++	"TU2_US_REG",
++	"TU3_US_REG",
++	"TM0_MS_REG",
++	"TM1_MS_REG",
++	"TM2_MS_REG",
++	"TM3_MS_REG",
++	"MCU_WDT_REG",
++	"SYS_WDT_REG",
++	"GPIO_REG",
++	"SD_REG",
++	"SPI_REG",
++	"CSR_I2C_MST",
++	"UART_REG",
++	"DAT_UART_REG",
++	"INT_REG",
++	"DBG_SPI_REG",
++	"FLASH_SPI_REG",
++	"DMA_REG",
++	"CSR_PMU",
++	"CSR_RTC",
++	"RTC_RAM",
++	"D2_DMA_REG",
++	"HCI_REG",
++	"CO_REG",
++	"EFS_REG",
++	"SMS4_REG",
++	"MRX_REG",
++	"AMPDU_REG",
++	"MT_REG_CSR",
++	"TXQ0_MT_Q_REG_CSR",
++	"TXQ1_MT_Q_REG_CSR",
++	"TXQ2_MT_Q_REG_CSR",
++	"TXQ3_MT_Q_REG_CSR",
++	"TXQ4_MT_Q_REG_CSR",
++	"HIF_INFO",
++	"PHY_RATE_INFO",
++	"MAC_GLB_SET",
++	"BTCX_REG",
++	"MIB_REG",
++	"CBR_A_REG",
++	"MB_REG",
++	"ID_MNG_REG",
++	"CSR_PHY",
++	"CSR_RF",
++	"MMU_REG",
++	""
++};
++
++static const u32 SIZE_BANK_SSV6200[] = {
++	SYS_REG_BANK_SIZE,
++	WBOOT_REG_BANK_SIZE,
++	TU0_US_REG_BANK_SIZE,
++	TU1_US_REG_BANK_SIZE,
++	TU2_US_REG_BANK_SIZE,
++	TU3_US_REG_BANK_SIZE,
++	TM0_MS_REG_BANK_SIZE,
++	TM1_MS_REG_BANK_SIZE,
++	TM2_MS_REG_BANK_SIZE,
++	TM3_MS_REG_BANK_SIZE,
++	MCU_WDT_REG_BANK_SIZE,
++	SYS_WDT_REG_BANK_SIZE,
++	GPIO_REG_BANK_SIZE,
++	SD_REG_BANK_SIZE,
++	SPI_REG_BANK_SIZE,
++	CSR_I2C_MST_BANK_SIZE,
++	UART_REG_BANK_SIZE,
++	DAT_UART_REG_BANK_SIZE,
++	INT_REG_BANK_SIZE,
++	DBG_SPI_REG_BANK_SIZE,
++	FLASH_SPI_REG_BANK_SIZE,
++	DMA_REG_BANK_SIZE,
++	CSR_PMU_BANK_SIZE,
++	CSR_RTC_BANK_SIZE,
++	RTC_RAM_BANK_SIZE,
++	D2_DMA_REG_BANK_SIZE,
++	HCI_REG_BANK_SIZE,
++	CO_REG_BANK_SIZE,
++	EFS_REG_BANK_SIZE,
++	SMS4_REG_BANK_SIZE,
++	MRX_REG_BANK_SIZE,
++	AMPDU_REG_BANK_SIZE,
++	MT_REG_CSR_BANK_SIZE,
++	TXQ0_MT_Q_REG_CSR_BANK_SIZE,
++	TXQ1_MT_Q_REG_CSR_BANK_SIZE,
++	TXQ2_MT_Q_REG_CSR_BANK_SIZE,
++	TXQ3_MT_Q_REG_CSR_BANK_SIZE,
++	TXQ4_MT_Q_REG_CSR_BANK_SIZE,
++	HIF_INFO_BANK_SIZE,
++	PHY_RATE_INFO_BANK_SIZE,
++	MAC_GLB_SET_BANK_SIZE,
++	BTCX_REG_BANK_SIZE,
++	MIB_REG_BANK_SIZE,
++	CBR_A_REG_BANK_SIZE,
++	MB_REG_BANK_SIZE,
++	ID_MNG_REG_BANK_SIZE,
++	CSR_PHY_BANK_SIZE,
++	CSR_RF_BANK_SIZE,
++	MMU_REG_BANK_SIZE,
++	0x00000000
++};
+diff --git a/drivers/net/wireless/ssv6051/include/ssv_cfg.h b/drivers/net/wireless/ssv6051/include/ssv_cfg.h
+new file mode 100644
+index 000000000000..79b75619936e
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/include/ssv_cfg.h
+@@ -0,0 +1,60 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation, either version 3 of the License, or
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _SSV_CFG_H_
++#define _SSV_CFG_H_
++#define SSV6200_HW_CAP_HT 0x00000001
++#define SSV6200_HW_CAP_GF 0x00000002
++#define SSV6200_HW_CAP_2GHZ 0x00000004
++#define SSV6200_HW_CAP_5GHZ 0x00000008
++#define SSV6200_HW_CAP_SECURITY 0x00000010
++#define SSV6200_HT_CAP_SGI_20 0x00000020
++#define SSV6200_HT_CAP_SGI_40 0x00000040
++#define SSV6200_HW_CAP_AP 0x00000080
++#define SSV6200_HW_CAP_P2P 0x00000100
++#define SSV6200_HW_CAP_AMPDU_RX 0x00000200
++#define SSV6200_HW_CAP_AMPDU_TX 0x00000400
++#define SSV6200_HW_CAP_TDLS 0x00000800
++#define EXTERNEL_CONFIG_SUPPORT 64
++struct ssv6xxx_cfg {
++	u32 hw_caps;
++	u32 def_chan;
++	u32 crystal_type;
++	u32 volt_regulator;
++	u32 force_chip_identity;
++	u8 maddr[2][6];
++	u32 n_maddr;
++	u32 use_wpa2_only;
++	u32 ignore_reset_in_ap;
++	u32 r_calbration_result;
++	u32 sar_result;
++	u32 crystal_frequency_offset;
++	u32 tx_power_index_1;
++	u32 tx_power_index_2;
++	u32 chip_identity;
++	u32 wifi_tx_gain_level_gn;
++	u32 wifi_tx_gain_level_b;
++	u32 rssi_ctl;
++	u32 sr_bhvr;
++	u32 configuration[EXTERNEL_CONFIG_SUPPORT + 1][2];
++	u8 firmware_path[128];
++	u8 flash_bin_path[128];
++	u8 mac_address_path[128];
++	u8 mac_output_path[128];
++	u32 ignore_efuse_mac;
++	u32 mac_address_mode;
++};
++#endif
+diff --git a/drivers/net/wireless/ssv6051/include/ssv_firmware_version.h b/drivers/net/wireless/ssv6051/include/ssv_firmware_version.h
+new file mode 100644
+index 000000000000..7fabbe308f9d
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/include/ssv_firmware_version.h
+@@ -0,0 +1,25 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation, either version 3 of the License, or
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _SSV_FIRMWARE_VERSION_H_
++#define _SSV_FIRMWARE_VERSION_H_
++static u32 ssv_firmware_version = 16380;
++#define SSV_FIRMWARE_URl "http://192.168.15.30/svn/software/wifi/tag/smac-release-tag/6051.Q0.1009.21.000000/ssv6xxx/smac/firmware"
++#define FIRMWARE_COMPILERHOST "ssv-ThinkPad-X230"
++#define FIRMWARE_COMPILERDATE "11-06-2017-09:17:18"
++#define FIRMWARE_COMPILEROS "linux"
++#define FIRMWARE_COMPILEROSARCH "x86_64-linux-gnu-thread-multi"
++#endif
+diff --git a/drivers/net/wireless/ssv6051/include/ssv_version.h b/drivers/net/wireless/ssv6051/include/ssv_version.h
+new file mode 100644
+index 000000000000..99be5354f783
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/include/ssv_version.h
+@@ -0,0 +1,12 @@
++#ifndef _SSV_VERSION_H_
++#define _SSV_VERSION_H_
++
++static u32 ssv_root_version = 16529;
++
++#define SSV_ROOT_URl "http://192.168.15.30/svn/software/project/release/android/box/rk3x28/6051.Q0.1009.21.400401/ssv6xxx"
++#define COMPILERHOST "icomm-buildserver-T320"
++#define COMPILERDATE "12-08-2017-10:34:54"
++#define COMPILEROS "linux"
++#define COMPILEROSARCH "x86_64-linux-gnu-thread-multi"
++
++#endif
+diff --git a/drivers/net/wireless/ssv6051/platform-config.mak b/drivers/net/wireless/ssv6051/platform-config.mak
+new file mode 100644
+index 000000000000..b1b6f0510d28
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/platform-config.mak
+@@ -0,0 +1,97 @@
++
++ccflags-y += -DCONFIG_SSV6200_CORE
++
++###########################################################################
++# Compiler options                                                        #
++###########################################################################
++
++# Enable -g to help debug. Deassembly from .o to .S would help to track to
++# the problomatic line from call stack dump.
++#ccflags-y += -g
++ccflags += -Os
++
++############################################################
++# If you change the settings, please change the file synchronization
++# smac\firmware\include\config.h & compiler firmware
++############################################################
++#ccflags-y += -DCONFIG_SSV_CABRIO_A
++ccflags-y += -DCONFIG_SSV_CABRIO_E
++
++#CONFIG_SSV_SUPPORT_BTCX=y
++
++#ccflags-y += -DDEBUG
++ccflags-y += -DCONFIG_SSV6200_CLI_ENABLE
++
++#PADPD
++#ccflags-y += -DCONFIG_SSV_DPD
++
++#ccflags-y += -DCONFIG_SSV_CABRIO_MB_DEBUG
++#ccflags-y += -DCONFIG_SSV6XXX_DEBUGFS
++
++#SDIO
++ccflags-y += -DCONFIG_SSV_TX_LOWTHRESHOLD
++
++ccflags-y += -DCONFIG_FW_ALIGNMENT_CHECK
++ccflags-y += -DCONFIG_PLATFORM_SDIO_OUTPUT_TIMING=3
++ccflags-y += -DCONFIG_PLATFORM_SDIO_BLOCK_SIZE=128
++#ccflags-y += -DMULTI_THREAD_ENCRYPT
++#ccflags-y += -DKTHREAD_BIND
++#ccflags-y += -DROCKCHIP_WIFI_AUTO_SUPPORT
++ccflags-y += -DCONFIG_SSV_RSSI
++ccflags-y += -DCONFIG_SSV_VENDOR_EXT_SUPPORT
++
++############################################################
++# Rate control update for MPDU.
++############################################################
++ccflags-y += -DRATE_CONTROL_REALTIME_UPDATA
++
++#workaround
++#ccflags-y += -DCONFIG_SSV_CABRIO_EXT_PA
++
++############################################################
++# NOTE:
++#    Only one of the following flags could be turned on.
++# It also turned off the following flags. In this case,
++# pure software security or pure hardware security is used.
++#
++############################################################
++#ccflags-y += -DCONFIG_SSV_SW_ENCRYPT_HW_DECRYPT
++#ccflags-y += -DCONFIG_SSV_HW_ENCRYPT_SW_DECRYPT
++
++# FOR WFA
++#ccflags-y += -DWIFI_CERTIFIED
++
++#ccflags-y += -DCONFIG_SSV_SDIO_EXT_INT
++
++#######################################################
++ccflags-y += -DCONFIG_SSV6200_HAS_RX_WORKQUEUE
++ccflags-y += -DUSE_THREAD_RX
++ccflags-y += -DUSE_THREAD_TX
++ccflags-y += -DENABLE_AGGREGATE_IN_TIME
++ccflags-y += -DENABLE_INCREMENTAL_AGGREGATION
++
++# Generic decision table applicable to both AP and STA modes.
++ccflags-y += -DUSE_GENERIC_DECI_TBL
++
++#ccflags-y += -DCONFIG_SSV_WAPI
++
++ccflags-y += -DFW_WSID_WATCH_LIST
++#ccflags-y += -DUSE_BATCH_RX
++#ccflags-y += -DCONFIG_IRQ_DEBUG_COUNT
++
++ccflags-y += -DSSV6200_ECO
++#ccflags-y += -DENABLE_WAKE_IO_ISR_WHEN_HCI_ENQUEUE
++ccflags-y += -DHAS_CRYPTO_LOCK
++ccflags-y += -DENABLE_TX_Q_FLOW_CONTROL
++
++#ccflags-y += -DCONFIG_DEBUG_SKB_TIMESTAMP
++
++
++#enable p2p client to parse GO broadcast noa
++#ccflags-y += -DCONFIG_P2P_NOA
++
++#enable rx management frame check
++#ccflags-y += -DCONFIG_RX_MGMT_CHECK
++
++#force SW Broadcast/Multicast decryption
++ccflags-y += -DUSE_MAC80211_DECRYPT_BROADCAST
+\ No newline at end of file
+diff --git a/drivers/net/wireless/ssv6051/rules.mak b/drivers/net/wireless/ssv6051/rules.mak
+new file mode 100644
+index 000000000000..b3262852249c
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/rules.mak
+@@ -0,0 +1,19 @@
++
++
++$(KMODULE_NAME)-y += $(KERN_SRCS:.c=.o)
++obj-$(CONFIG_SSV6200_CORE) += $(KMODULE_NAME).o
++
++
++.PHONY: all clean install
++
++all:
++	@$(MAKE) -C /lib/modules/$(KVERSION)/build \
++		SUBDIRS=$(KBUILD_DIR) CONFIG_DEBUG_SECTION_MISMATCH=y \
++		modules
++
++clean:
++	@$(MAKE) -C /lib/modules/$(KVERSION)/build SUBDIRS=$(KBUILD_DIR) clean
++
++install:
++	@$(MAKE) INSTALL_MOD_DIR=$(DRVPATH) -C /lib/modules/$(KVERSION)/build \
++	        M=$(KBUILD_DIR) modules_install
+diff --git a/drivers/net/wireless/ssv6051/smac/ampdu.c b/drivers/net/wireless/ssv6051/smac/ampdu.c
+new file mode 100644
+index 000000000000..846830f3d209
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/ampdu.c
+@@ -0,0 +1,2111 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation, either version 3 of the License, or
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <linux/version.h>
++#include <ssv6200.h>
++#include "dev.h"
++#include "ap.h"
++#include "sec.h"
++#include "ssv_rc_common.h"
++#include "ssv_ht_rc.h"
++extern struct ieee80211_ops ssv6200_ops;
++
++// Hack: redefine MAX_AMPDU_BUF because buf_size here is a 8-bit char
++// and mainline kernel value is 0x100, which overflows
++#ifdef IEEE80211_MAX_AMPDU_BUF
++#undef IEEE80211_MAX_AMPDU_BUF
++#endif
++#define IEEE80211_MAX_AMPDU_BUF 0x40
++
++#define BA_WAIT_TIMEOUT (800)
++#define AMPDU_BA_FRAME_LEN (68)
++#define ampdu_skb_hdr(skb) ((struct ieee80211_hdr*)((u8*)((skb)->data)+AMPDU_DELIMITER_LEN))
++#define ampdu_skb_ssn(skb) ((ampdu_skb_hdr(skb)->seq_ctrl)>>SSV_SEQ_NUM_SHIFT)
++#define ampdu_hdr_ssn(hdr) ((hdr)->seq_ctrl>>SSV_SEQ_NUM_SHIFT)
++#undef prn_aggr_dbg
++#define prn_aggr_dbg(fmt,...)
++static void void_func(const char *fmt, ...)
++{
++}
++
++#define prn_aggr_err(fmt,...) \
++    do { \
++        void_func(KERN_ERR fmt, ##__VA_ARGS__);\
++    } while (0)
++#define get_tid_aggr_len(agg_len,tid_data) \
++    ({ \
++        u32 agg_max_num = (tid_data)->agg_num_max; \
++        u32 to_agg_len = (agg_len); \
++        (agg_len >= agg_max_num) ? agg_max_num : to_agg_len; \
++    })
++#define INDEX_PKT_BY_SSN(tid,ssn) \
++    ((tid)->aggr_pkts[(ssn) % SSV_AMPDU_BA_WINDOW_SIZE])
++#define NEXT_PKT_SN(sn) \
++    ({ (sn + 1) % SSV_AMPDU_MAX_SSN; })
++#define INC_PKT_SN(sn) \
++    ({ \
++        sn = NEXT_PKT_SN(sn); \
++        sn; \
++    })
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++static ssize_t ampdu_tx_mib_dump(struct ssv_sta_priv_data *ssv_sta_priv,
++				 char *mib_str, ssize_t length);
++static int _dump_ba_skb(char *buf, int buf_size, struct sk_buff *ba_skb);
++#endif
++static struct sk_buff *_aggr_retry_mpdu(struct ssv_softc *sc,
++					struct AMPDU_TID_st *cur_AMPDU_TID,
++					struct sk_buff_head *retry_queue,
++					u32 max_aggr_len);
++static int _dump_BA_notification(char *buf,
++				 struct ampdu_ba_notify_data *ba_notification);
++static struct sk_buff *_alloc_ampdu_skb(struct ssv_softc *sc,
++					struct AMPDU_TID_st *ampdu_tid,
++					u32 len);
++static bool _sync_ampdu_pkt_arr(struct AMPDU_TID_st *ampdu_tid,
++				struct sk_buff *ampdu_skb, bool retry);
++static void _put_mpdu_to_ampdu(struct sk_buff *ampdu, struct sk_buff *mpdu);
++static void _add_ampdu_txinfo(struct ssv_softc *sc, struct sk_buff *ampdu_skb);
++static u32 _flush_early_ampdu_q(struct ssv_softc *sc,
++				struct AMPDU_TID_st *ampdu_tid);
++static bool _is_skb_q_empty(struct ssv_softc *sc, struct sk_buff *skb);
++static void _aggr_ampdu_tx_q(struct ieee80211_hw *hw,
++			     struct AMPDU_TID_st *ampdu_tid);
++static void _queue_early_ampdu(struct ssv_softc *sc,
++			       struct AMPDU_TID_st *ampdu_tid,
++			       struct sk_buff *ampdu_skb);
++static int _mark_skb_retry(struct SKB_info_st *skb_info, struct sk_buff *skb);
++#ifdef CONFIG_DEBUG_SKB_TIMESTAMP
++unsigned int cal_duration_of_ampdu(struct sk_buff *ampdu_skb, int stage)
++{
++	unsigned int timeout;
++	SKB_info *mpdu_skb_info;
++	u16 ssn = 0;
++	struct sk_buff *mpdu = NULL;
++	struct ampdu_hdr_st *ampdu_hdr = NULL;
++	ktime_t current_ktime;
++	ampdu_hdr = (struct ampdu_hdr_st *)ampdu_skb->head;
++	ssn = ampdu_hdr->ssn[0];
++	mpdu = INDEX_PKT_BY_SSN(ampdu_hdr->ampdu_tid, ssn);
++	if (mpdu == NULL)
++		return 0;
++	mpdu_skb_info = (SKB_info *) (mpdu->head);
++	current_ktime = ktime_get();
++	timeout =
++	    (unsigned int)
++	    ktime_to_ms(ktime_sub(current_ktime, mpdu_skb_info->timestamp));
++	if (timeout > SKB_DURATION_TIMEOUT_MS) {
++		if (stage == SKB_DURATION_STAGE_TO_SDIO)
++			pr_debug("*a_to_sdio: %ums\n", timeout);
++		else if (stage == SKB_DURATION_STAGE_TX_ENQ)
++			pr_debug("*a_to_txenqueue: %ums\n", timeout);
++		else
++			pr_debug("*a_in_hwq: %ums\n", timeout);
++	}
++	return timeout;
++}
++#endif
++static u8 _cal_ampdu_delm_half_crc(u8 value)
++{
++	u32 c32 = value, v32 = value;
++	c32 ^= (v32 >> 1) | (v32 << 7);
++	c32 ^= (v32 >> 2);
++	if (v32 & 2)
++		c32 ^= (0xC0);
++	c32 ^= ((v32 << 4) & 0x30);
++	return (u8) c32;
++}
++
++static u8 _cal_ampdu_delm_crc(u8 * pointer)
++{
++	u8 crc = 0xCF;
++	crc ^= _cal_ampdu_delm_half_crc(*pointer++);
++	crc =
++	    _cal_ampdu_delm_half_crc(crc) ^ _cal_ampdu_delm_half_crc(*pointer);
++	return ~crc;
++}
++
++static bool ssv6200_ampdu_add_delimiter_and_crc32(struct sk_buff *mpdu)
++{
++	p_AMPDU_DELIMITER delimiter_p;
++	struct ieee80211_hdr *mpdu_hdr;
++	int ret;
++	u32 orig_mpdu_len = mpdu->len;
++	u32 pad = (4 - (orig_mpdu_len % 4)) % 4;
++	mpdu_hdr = (struct ieee80211_hdr *)(mpdu->data);
++	mpdu_hdr->duration_id = AMPDU_TX_NAV_MCS_567;
++	ret = skb_padto(mpdu, mpdu->len + (AMPDU_FCS_LEN + pad));
++	if (ret) {
++		pr_err("Failed to extand skb for aggregation\n");
++		return false;
++	}
++	skb_put(mpdu, AMPDU_FCS_LEN + pad);
++	skb_push(mpdu, AMPDU_DELIMITER_LEN);
++	delimiter_p = (p_AMPDU_DELIMITER) mpdu->data;
++	delimiter_p->reserved = 0;
++	delimiter_p->length = orig_mpdu_len + AMPDU_FCS_LEN;
++	delimiter_p->signature = AMPDU_SIGNATURE;
++	delimiter_p->crc = _cal_ampdu_delm_crc((u8 *) (delimiter_p));
++	return true;
++}
++
++static void ssv6200_ampdu_hw_init(struct ieee80211_hw *hw)
++{
++	struct ssv_softc *sc = hw->priv;
++	u32 temp32;
++	SMAC_REG_READ(sc->sh, ADR_MTX_MISC_EN, &temp32);
++	temp32 |= (0x1 << MTX_AMPDU_CRC_AUTO_SFT);
++	SMAC_REG_WRITE(sc->sh, ADR_MTX_MISC_EN, temp32);
++	SMAC_REG_READ(sc->sh, ADR_MTX_MISC_EN, &temp32);
++}
++
++bool _sync_ampdu_pkt_arr(struct AMPDU_TID_st *ampdu_tid, struct sk_buff *ampdu,
++			 bool retry)
++{
++	struct sk_buff **pp_aggr_pkt;
++	struct sk_buff *p_aggr_pkt;
++	unsigned long flags;
++	struct ampdu_hdr_st *ampdu_hdr = (struct ampdu_hdr_st *)ampdu->head;
++	struct sk_buff *mpdu;
++	u32 first_ssn = SSV_ILLEGAL_SN;
++	u32 old_aggr_pkt_num;
++	u32 old_baw_head;
++	u32 sync_num = skb_queue_len(&ampdu_hdr->mpdu_q);
++	bool ret = true;
++	spin_lock_irqsave(&ampdu_tid->pkt_array_lock, flags);
++	old_baw_head = ampdu_tid->ssv_baw_head;
++	old_aggr_pkt_num = ampdu_tid->aggr_pkt_num;
++	ampdu_tid->mib.ampdu_mib_ampdu_counter += 1;
++	ampdu_tid->mib.ampdu_mib_dist[sync_num] += 1;
++	do {
++		if (!retry) {
++			ampdu_tid->mib.ampdu_mib_mpdu_counter += sync_num;
++			mpdu = skb_peek_tail(&ampdu_hdr->mpdu_q);
++			if (mpdu == NULL) {
++				ret = false;
++				break;
++			} else {
++				u32 ssn = ampdu_skb_ssn(mpdu);
++				p_aggr_pkt = INDEX_PKT_BY_SSN(ampdu_tid, ssn);
++				if (p_aggr_pkt != NULL) {
++					char msg[256];
++					u32 sn = ampdu_skb_ssn(mpdu);
++					skb_queue_walk(&ampdu_hdr->mpdu_q, mpdu) {
++						sn = ampdu_skb_ssn(mpdu);
++						sprintf(msg, " %d", sn);
++					}
++					prn_aggr_err("ES %d -> %d (%s)\n",
++						     ssn,
++						     ampdu_skb_ssn(p_aggr_pkt),
++						     msg);
++					ret = false;
++					break;
++				}
++			}
++		} else
++			ampdu_tid->mib.ampdu_mib_aggr_retry_counter += 1;
++		skb_queue_walk(&ampdu_hdr->mpdu_q, mpdu) {
++			u32 ssn = ampdu_skb_ssn(mpdu);
++			SKB_info *mpdu_skb_info = (SKB_info *) (mpdu->head);
++			if (first_ssn == SSV_ILLEGAL_SN)
++				first_ssn = ssn;
++			pp_aggr_pkt = &INDEX_PKT_BY_SSN(ampdu_tid, ssn);
++			p_aggr_pkt = *pp_aggr_pkt;
++			*pp_aggr_pkt = mpdu;
++			if (!retry)
++				ampdu_tid->aggr_pkt_num++;
++			mpdu_skb_info->ampdu_tx_status = AMPDU_ST_AGGREGATED;
++			if (ampdu_tid->ssv_baw_head == SSV_ILLEGAL_SN) {
++				ampdu_tid->ssv_baw_head = ssn;
++			}
++			if ((p_aggr_pkt != NULL) && (mpdu != p_aggr_pkt))
++				prn_aggr_err("%d -> %d (H%d, N%d, Q%d)\n",
++					     ssn, ampdu_skb_ssn(p_aggr_pkt),
++					     old_baw_head, old_aggr_pkt_num,
++					     sync_num);
++		}
++	} while (0);
++	spin_unlock_irqrestore(&ampdu_tid->pkt_array_lock, flags);
++	{
++		u32 page_count = (ampdu->len + SSV6200_ALLOC_RSVD);
++		if (page_count & HW_MMU_PAGE_MASK)
++			page_count = (page_count >> HW_MMU_PAGE_SHIFT) + 1;
++		else
++			page_count = page_count >> HW_MMU_PAGE_SHIFT;
++		if (page_count > (SSV6200_PAGE_TX_THRESHOLD / 2))
++			pr_err("AMPDU requires pages %d(%d-%d-%d) exceeds resource limit %d.\n",
++			       page_count, ampdu->len, ampdu_hdr->max_size,
++			       ampdu_hdr->size,
++			       (SSV6200_PAGE_TX_THRESHOLD / 2));
++	}
++	return ret;
++}
++
++struct sk_buff *_aggr_retry_mpdu(struct ssv_softc *sc,
++				 struct AMPDU_TID_st *ampdu_tid,
++				 struct sk_buff_head *retry_queue,
++				 u32 max_aggr_len)
++{
++	struct sk_buff *retry_mpdu;
++	struct sk_buff *new_ampdu_skb;
++	u32 num_retry_mpdu;
++	u32 temp_i;
++	u32 total_skb_size;
++	unsigned long flags;
++	u16 head_ssn = ampdu_tid->ssv_baw_head;
++	struct ampdu_hdr_st *ampdu_hdr;
++	BUG_ON(head_ssn == SSV_ILLEGAL_SN);
++	num_retry_mpdu = skb_queue_len(retry_queue);
++	if (num_retry_mpdu == 0)
++		return NULL;
++	new_ampdu_skb = _alloc_ampdu_skb(sc, ampdu_tid, max_aggr_len);
++	if (new_ampdu_skb == 0)
++		return NULL;
++	ampdu_hdr = (struct ampdu_hdr_st *)new_ampdu_skb->head;
++	total_skb_size = 0;
++	spin_lock_irqsave(&retry_queue->lock, flags);
++	for (temp_i = 0; temp_i < ampdu_tid->agg_num_max; temp_i++) {
++		struct ieee80211_hdr *mpdu_hdr;
++		u16 mpdu_sn;
++		u16 diff;
++		u32 new_total_skb_size;
++		retry_mpdu = skb_peek(retry_queue);
++		if (retry_mpdu == NULL) {
++			break;
++		}
++		mpdu_hdr = ampdu_skb_hdr(retry_mpdu);
++		mpdu_sn = ampdu_hdr_ssn(mpdu_hdr);
++		diff = SSV_AMPDU_SN_a_minus_b(head_ssn, mpdu_sn);
++		if ((head_ssn != SSV_ILLEGAL_SN)
++		    && (diff > 0)
++		    && (diff <= ampdu_tid->ssv_baw_size)) {
++			struct SKB_info_st *skb_info;
++			prn_aggr_err("Z. release skb (s %d, h %d, d %d)\n",
++				     mpdu_sn, head_ssn, diff);
++			skb_info = (struct SKB_info_st *)(retry_mpdu->head);
++			skb_info->ampdu_tx_status = AMPDU_ST_DROPPED;
++			ampdu_tid->mib.ampdu_mib_discard_counter++;
++			continue;
++		}
++		new_total_skb_size = total_skb_size + retry_mpdu->len;
++		if (new_total_skb_size > ampdu_hdr->max_size)
++			break;
++		total_skb_size = new_total_skb_size;
++		retry_mpdu = __skb_dequeue(retry_queue);
++		_put_mpdu_to_ampdu(new_ampdu_skb, retry_mpdu);
++		ampdu_tid->mib.ampdu_mib_retry_counter++;
++	}
++	ampdu_tid->mib.ampdu_mib_aggr_retry_counter += 1;
++	ampdu_tid->mib.ampdu_mib_dist[temp_i] += 1;
++	spin_unlock_irqrestore(&retry_queue->lock, flags);
++	if (ampdu_hdr->mpdu_num == 0) {
++		dev_kfree_skb_any(new_ampdu_skb);
++		return NULL;
++	}
++	return new_ampdu_skb;
++}
++
++static void _add_ampdu_txinfo(struct ssv_softc *sc, struct sk_buff *ampdu_skb)
++{
++	struct ssv6200_tx_desc *tx_desc;
++	ssv6xxx_add_txinfo(sc, ampdu_skb);
++	tx_desc = (struct ssv6200_tx_desc *)ampdu_skb->data;
++	tx_desc->tx_report = 1;
++}
++
++void _send_hci_skb(struct ssv_softc *sc, struct sk_buff *skb, u32 tx_flag)
++{
++	struct ssv6200_tx_desc *tx_desc = (struct ssv6200_tx_desc *)skb->data;
++	int ret = AMPDU_HCI_SEND(sc->sh, skb, tx_desc->txq_idx, tx_flag);
++	if ((tx_desc->txq_idx > 3) && (ret <= 0)) {
++		prn_aggr_err("BUG!! %d %d\n", tx_desc->txq_idx, ret);
++	}
++}
++
++static void ssv6200_ampdu_add_txinfo_and_send_HCI(struct ssv_softc *sc,
++						  struct sk_buff *ampdu_skb,
++						  u32 tx_flag)
++{
++	_add_ampdu_txinfo(sc, ampdu_skb);
++	_send_hci_skb(sc, ampdu_skb, tx_flag);
++}
++
++static void ssv6200_ampdu_send_retry(struct ieee80211_hw *hw,
++				     AMPDU_TID * cur_ampdu_tid,
++				     struct sk_buff_head
++				     *ampdu_skb_retry_queue_p,
++				     bool send_aggr_tx)
++{
++	struct ssv_softc *sc = hw->priv;
++	struct sk_buff *ampdu_retry_skb;
++	u32 ampdu_skb_retry_queue_len;
++	u32 max_agg_len;
++	u16 lowest_rate;
++	struct fw_rc_retry_params rates[SSV62XX_TX_MAX_RATES];
++	ampdu_skb_retry_queue_len = skb_queue_len(ampdu_skb_retry_queue_p);
++	if (ampdu_skb_retry_queue_len == 0)
++		return;
++	ampdu_retry_skb = skb_peek(ampdu_skb_retry_queue_p);
++	lowest_rate = ssv62xx_ht_rate_update(ampdu_retry_skb, sc, rates);
++	max_agg_len = ampdu_max_transmit_length[lowest_rate];
++	if (max_agg_len > 0) {
++		u32 cur_ampdu_max_size = SSV_GET_MAX_AMPDU_SIZE(sc->sh);
++		if (max_agg_len >= cur_ampdu_max_size)
++			max_agg_len = cur_ampdu_max_size;
++		while (ampdu_skb_retry_queue_len > 0) {
++			struct sk_buff *retry_mpdu =
++			    skb_peek(ampdu_skb_retry_queue_p);
++			SKB_info *mpdu_skb_info =
++			    (SKB_info *) (retry_mpdu->head);
++			mpdu_skb_info->lowest_rate = lowest_rate;
++			memcpy(mpdu_skb_info->rates, rates, sizeof(rates));
++			ampdu_retry_skb =
++			    _aggr_retry_mpdu(sc, cur_ampdu_tid,
++					     ampdu_skb_retry_queue_p,
++					     max_agg_len);
++			if (ampdu_retry_skb != NULL) {
++				_sync_ampdu_pkt_arr(cur_ampdu_tid,
++						    ampdu_retry_skb, true);
++				ssv6200_ampdu_add_txinfo_and_send_HCI(sc,
++								      ampdu_retry_skb,
++								      AMPDU_HCI_SEND_HEAD_WITHOUT_FLOWCTRL);
++			} else {
++				prn_aggr_err("AMPDU retry failed.\n");
++				return;
++			}
++			ampdu_skb_retry_queue_len =
++			    skb_queue_len(ampdu_skb_retry_queue_p);
++		}
++	} else {
++		struct ieee80211_tx_rate rates[IEEE80211_TX_MAX_RATES];
++		struct ieee80211_tx_info *info =
++		    IEEE80211_SKB_CB(ampdu_retry_skb);
++		memcpy(rates, info->control.rates, sizeof(info->control.rates));
++		while ((ampdu_retry_skb =
++			__skb_dequeue_tail(ampdu_skb_retry_queue_p)) != NULL) {
++			struct ieee80211_tx_info *info =
++			    IEEE80211_SKB_CB(ampdu_retry_skb);
++			info->flags &= ~IEEE80211_TX_CTL_AMPDU;
++			memcpy(info->control.rates, rates,
++			       sizeof(info->control.rates));
++			ssv6xxx_update_txinfo(sc, ampdu_retry_skb);
++			_send_hci_skb(sc, ampdu_retry_skb,
++				      AMPDU_HCI_SEND_HEAD_WITHOUT_FLOWCTRL);
++		}
++	}
++}
++
++void ssv6200_ampdu_init(struct ieee80211_hw *hw)
++{
++	struct ssv_softc *sc = hw->priv;
++	ssv6200_ampdu_hw_init(hw);
++	sc->tx.ampdu_tx_group_id = 0;
++#ifdef USE_ENCRYPT_WORK
++	INIT_WORK(&sc->ampdu_tx_encry_work, encry_work);
++	INIT_WORK(&sc->sync_hwkey_work, sync_hw_key_work);
++#endif
++}
++
++void ssv6200_ampdu_deinit(struct ieee80211_hw *hw)
++{
++}
++
++void ssv6200_ampdu_release_skb(struct sk_buff *skb, struct ieee80211_hw *hw)
++{
++	ieee80211_free_txskb(hw, skb);
++}
++
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++struct mib_dump_data {
++	char *prt_buff;
++	size_t buff_size;
++	size_t prt_len;
++};
++#define AMPDU_TX_MIB_SUMMARY_BUF_SIZE (4096)
++static ssize_t ampdu_tx_mib_summary_read(struct file *file,
++					 char __user * user_buf, size_t count,
++					 loff_t * ppos)
++{
++	struct ssv_sta_priv_data *ssv_sta_priv =
++	    (struct ssv_sta_priv_data *)file->private_data;
++	char *summary_buf = kzalloc(AMPDU_TX_MIB_SUMMARY_BUF_SIZE, GFP_KERNEL);
++	ssize_t summary_size;
++	ssize_t ret;
++	if (!summary_buf)
++		return -ENOMEM;
++	summary_size = ampdu_tx_mib_dump(ssv_sta_priv, summary_buf,
++					 AMPDU_TX_MIB_SUMMARY_BUF_SIZE);
++	ret = simple_read_from_buffer(user_buf, count, ppos, summary_buf,
++				      summary_size);
++	kfree(summary_buf);
++	return ret;
++}
++
++static int ampdu_tx_mib_summary_open(struct inode *inode, struct file *file)
++{
++	file->private_data = inode->i_private;
++	return 0;
++}
++
++static const struct file_operations mib_summary_fops = {.read =
++	    ampdu_tx_mib_summary_read,.open = ampdu_tx_mib_summary_open,
++};
++
++static ssize_t ampdu_tx_tid_window_read(struct file *file,
++					char __user * user_buf, size_t count,
++					loff_t * ppos)
++{
++	struct AMPDU_TID_st *ampdu_tid =
++	    (struct AMPDU_TID_st *)file->private_data;
++	char *summary_buf = kzalloc(AMPDU_TX_MIB_SUMMARY_BUF_SIZE, GFP_KERNEL);
++	ssize_t ret;
++	char *prn_ptr = summary_buf;
++	int prt_size;
++	int buf_size = AMPDU_TX_MIB_SUMMARY_BUF_SIZE;
++	int i;
++	struct sk_buff *ba_skb, *tmp_ba_skb;
++	if (!summary_buf)
++		return -ENOMEM;
++	prt_size = snprintf(prn_ptr, buf_size, "\nWMM_TID %d:\n"
++			    "\tWindow:", ampdu_tid->tidno);
++	prn_ptr += prt_size;
++	buf_size -= prt_size;
++	for (i = 0; i < SSV_AMPDU_BA_WINDOW_SIZE; i++) {
++		struct sk_buff *skb = ampdu_tid->aggr_pkts[i];
++		if ((i % 8) == 0) {
++			prt_size = snprintf(prn_ptr, buf_size, "\n\t\t");
++			prn_ptr += prt_size;
++			buf_size -= prt_size;
++		}
++		if (skb == NULL)
++			prt_size = snprintf(prn_ptr, buf_size, " %s", "NULL ");
++		else {
++			struct SKB_info_st *skb_info =
++			    (struct SKB_info_st *)(skb->head);
++			const char status_symbol[] = { 'N',
++				'A',
++				'S',
++				'R',
++				'P',
++				'D'
++			};
++			prt_size =
++			    snprintf(prn_ptr, buf_size, " %4d%c",
++				     ampdu_skb_ssn(skb),
++				     ((skb_info->ampdu_tx_status <=
++				       AMPDU_ST_DONE)
++				      ? status_symbol[skb_info->ampdu_tx_status]
++				      : 'X'));
++		}
++		prn_ptr += prt_size;
++		buf_size -= prt_size;
++	}
++	prt_size =
++	    snprintf(prn_ptr, buf_size, "\n\tEarly aggregated #: %d\n",
++		     ampdu_tid->early_aggr_skb_num);
++	prn_ptr += prt_size;
++	buf_size -= prt_size;
++	prt_size =
++	    snprintf(prn_ptr, buf_size, "\tBAW skb #: %d\n",
++		     ampdu_tid->aggr_pkt_num);
++	prn_ptr += prt_size;
++	buf_size -= prt_size;
++	prt_size =
++	    snprintf(prn_ptr, buf_size, "\tBAW head: %d\n",
++		     ampdu_tid->ssv_baw_head);
++	prn_ptr += prt_size;
++	buf_size -= prt_size;
++	prt_size =
++	    snprintf(prn_ptr, buf_size, "\tState: %d\n", ampdu_tid->state);
++	prn_ptr += prt_size;
++	buf_size -= prt_size;
++	prt_size = snprintf(prn_ptr, buf_size, "\tBA:\n");
++	prn_ptr += prt_size;
++	buf_size -= prt_size;
++	skb_queue_walk_safe(&ampdu_tid->ba_q, ba_skb, tmp_ba_skb) {
++		prt_size = _dump_ba_skb(prn_ptr, buf_size, ba_skb);
++		prn_ptr += prt_size;
++		buf_size -= prt_size;
++	}
++	buf_size = AMPDU_TX_MIB_SUMMARY_BUF_SIZE - buf_size;
++	ret = simple_read_from_buffer(user_buf, count, ppos, summary_buf,
++				      buf_size);
++	kfree(summary_buf);
++	return ret;
++}
++
++static int ampdu_tx_tid_window_open(struct inode *inode, struct file *file)
++{
++	file->private_data = inode->i_private;
++	return 0;
++}
++
++static const struct file_operations tid_window_fops = {.read =
++	    ampdu_tx_tid_window_read,.open = ampdu_tx_tid_window_open,
++};
++
++static int ampdu_tx_mib_reset_open(struct inode *inode, struct file *file)
++{
++	file->private_data = inode->i_private;
++	return 0;
++}
++
++static ssize_t ampdu_tx_mib_reset_read(struct file *file,
++				       char __user * user_buf, size_t count,
++				       loff_t * ppos)
++{
++	char *reset_buf = kzalloc(64, GFP_KERNEL);
++	ssize_t ret;
++	u32 reset_size;
++	if (!reset_buf)
++		return -ENOMEM;
++	reset_size = snprintf(reset_buf, 63, "%d", 0);
++	ret = simple_read_from_buffer(user_buf, count, ppos, reset_buf,
++				      reset_size);
++	kfree(reset_buf);
++	return ret;
++}
++
++static ssize_t ampdu_tx_mib_reset_write(struct file *file,
++					const char __user * buffer,
++					size_t count, loff_t * pos)
++{
++	struct AMPDU_TID_st *ampdu_tid =
++	    (struct AMPDU_TID_st *)file->private_data;
++	memset(&ampdu_tid->mib, 0, sizeof(struct AMPDU_MIB_st));
++	return count;
++}
++
++static const struct file_operations mib_reset_fops
++    = {.read = ampdu_tx_mib_reset_read,
++	.open = ampdu_tx_mib_reset_open,
++	.write = ampdu_tx_mib_reset_write
++};
++
++static void ssv6200_ampdu_tx_init_debugfs(struct ssv_softc *sc,
++					  struct ssv_sta_priv_data
++					  *ssv_sta_priv)
++{
++	struct ssv_sta_info *sta_info = ssv_sta_priv->sta_info;
++	int i;
++	struct dentry *sta_debugfs_dir = sta_info->debugfs_dir;
++	dev_info(sc->dev, "Creating AMPDU TX debugfs.\n");
++	if (sta_debugfs_dir == NULL) {
++		dev_err(sc->dev, "No STA debugfs.\n");
++		return;
++	}
++	debugfs_create_file("ampdu_tx_summary", 00444, sta_debugfs_dir,
++			    ssv_sta_priv, &mib_summary_fops);
++	debugfs_create_u32("total_BA", 00644, sta_debugfs_dir,
++			   &ssv_sta_priv->ampdu_mib_total_BA_counter);
++	for (i = 0; i < WMM_TID_NUM; i++) {
++		char debugfs_name[20];
++		struct dentry *ampdu_tx_debugfs_dir;
++		int j;
++		struct AMPDU_TID_st *ampdu_tid = &ssv_sta_priv->ampdu_tid[i];
++		struct AMPDU_MIB_st *ampdu_mib = &ampdu_tid->mib;
++		snprintf(debugfs_name, sizeof(debugfs_name), "ampdu_tx_%d", i);
++		ampdu_tx_debugfs_dir = debugfs_create_dir(debugfs_name,
++							  sta_debugfs_dir);
++		if (ampdu_tx_debugfs_dir == NULL) {
++			dev_err(sc->dev,
++				"Failed to create debugfs for AMPDU TX TID %d: %s\n",
++				i, debugfs_name);
++			continue;
++		}
++		ssv_sta_priv->ampdu_tid[i].debugfs_dir = ampdu_tx_debugfs_dir;
++		debugfs_create_file("baw_status", 00444, ampdu_tx_debugfs_dir,
++				    ampdu_tid, &tid_window_fops);
++		debugfs_create_file("reset", 00644, ampdu_tx_debugfs_dir,
++				    ampdu_tid, &mib_reset_fops);
++		debugfs_create_u32("total", 00444, ampdu_tx_debugfs_dir,
++				   &ampdu_mib->ampdu_mib_ampdu_counter);
++		debugfs_create_u32("retry", 00444, ampdu_tx_debugfs_dir,
++				   &ampdu_mib->ampdu_mib_retry_counter);
++		debugfs_create_u32("aggr_retry", 00444, ampdu_tx_debugfs_dir,
++				   &ampdu_mib->ampdu_mib_aggr_retry_counter);
++		debugfs_create_u32("BAR", 00444, ampdu_tx_debugfs_dir,
++				   &ampdu_mib->ampdu_mib_bar_counter);
++		debugfs_create_u32("Discarded", 00444, ampdu_tx_debugfs_dir,
++				   &ampdu_mib->ampdu_mib_discard_counter);
++		debugfs_create_u32("BA", 00444, ampdu_tx_debugfs_dir,
++				   &ampdu_mib->ampdu_mib_BA_counter);
++		debugfs_create_u32("Pass", 00444, ampdu_tx_debugfs_dir,
++				   &ampdu_mib->ampdu_mib_pass_counter);
++		for (j = 0; j <= SSV_AMPDU_aggr_num_max; j++) {
++			char dist_dbg_name[10];
++			snprintf(dist_dbg_name, sizeof(dist_dbg_name),
++				 "aggr_%d", j);
++			debugfs_create_u32(dist_dbg_name, 00444,
++					   ampdu_tx_debugfs_dir,
++					   &ampdu_mib->ampdu_mib_dist[j]);
++		}
++		skb_queue_head_init(&ssv_sta_priv->ampdu_tid[i].ba_q);
++	}
++}
++#endif
++void ssv6200_ampdu_tx_add_sta(struct ieee80211_hw *hw,
++			      struct ieee80211_sta *sta)
++{
++	struct ssv_sta_priv_data *ssv_sta_priv;
++	struct ssv_softc *sc;
++	u32 temp_i;
++	ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
++	sc = (struct ssv_softc *)hw->priv;
++	for (temp_i = 0; temp_i < WMM_TID_NUM; temp_i++) {
++		ssv_sta_priv->ampdu_tid[temp_i].sta = sta;
++		ssv_sta_priv->ampdu_tid[temp_i].state = AMPDU_STATE_STOP;
++		spin_lock_init(&ssv_sta_priv->ampdu_tid[temp_i].
++			       ampdu_skb_tx_queue_lock);
++		spin_lock_init(&ssv_sta_priv->ampdu_tid[temp_i].pkt_array_lock);
++	}
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	ssv6200_ampdu_tx_init_debugfs(sc, ssv_sta_priv);
++#endif
++}
++
++void ssv6200_ampdu_tx_start(u16 tid, struct ieee80211_sta *sta,
++			    struct ieee80211_hw *hw, u16 * ssn)
++{
++	struct ssv_softc *sc = hw->priv;
++	struct ssv_sta_priv_data *ssv_sta_priv;
++	struct AMPDU_TID_st *ampdu_tid;
++	int i;
++	ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
++	ampdu_tid = &ssv_sta_priv->ampdu_tid[tid];
++	ampdu_tid->ssv_baw_head = SSV_ILLEGAL_SN;
++#ifdef DEBUG_AMPDU_FLUSH
++	pr_debug("Adding %02X-%02X-%02X-%02X-%02X-%02X TID %d (%p).\n",
++	       sta->addr[0], sta->addr[1], sta->addr[2],
++	       sta->addr[3], sta->addr[4], sta->addr[5],
++	       ampdu_tid->tidno, ampdu_tid);
++	{
++		int j;
++		for (j = 0; j <= MAX_TID; j++) {
++			if (sc->tid[j] == 0)
++				break;
++		}
++		if (j == MAX_TID) {
++			dev_err(sc->dev, "No room for new TID.\n");
++		} else
++			sc->tid[j] = ampdu_tid;
++	}
++#endif
++	list_add_tail_rcu(&ampdu_tid->list, &sc->tx.ampdu_tx_que);
++	skb_queue_head_init(&ampdu_tid->ampdu_skb_tx_queue);
++	skb_queue_head_init(&ampdu_tid->early_aggr_ampdu_q);
++	ampdu_tid->early_aggr_skb_num = 0;
++	skb_queue_head_init(&ampdu_tid->ampdu_skb_wait_encry_queue);
++	skb_queue_head_init(&ampdu_tid->retry_queue);
++	skb_queue_head_init(&ampdu_tid->release_queue);
++	for (i = 0;
++	     i <
++	     (sizeof(ampdu_tid->aggr_pkts) / sizeof(ampdu_tid->aggr_pkts[0]));
++	     i++)
++		ampdu_tid->aggr_pkts[i] = 0;
++	ampdu_tid->aggr_pkt_num = 0;
++	ampdu_tid->cur_ampdu_pkt = _alloc_ampdu_skb(sc, ampdu_tid, 0);
++#ifdef AMPDU_CHECK_SKB_SEQNO
++	ssv_sta_priv->ampdu_tid[tid].last_seqno = (-1);
++#endif
++	ssv_sta_priv->ampdu_mib_total_BA_counter = 0;
++	memset(&ssv_sta_priv->ampdu_tid[tid].mib, 0,
++	       sizeof(struct AMPDU_MIB_st));
++	ssv_sta_priv->ampdu_tid[tid].state = AMPDU_STATE_START;
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	skb_queue_head_init(&ssv_sta_priv->ampdu_tid[tid].ba_q);
++#endif
++}
++
++void ssv6200_ampdu_tx_operation(u16 tid, struct ieee80211_sta *sta,
++				struct ieee80211_hw *hw, u8 buffer_size)
++{
++    struct ssv_softc *sc = hw->priv;
++	struct ssv_sta_priv_data *ssv_sta_priv;
++	ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
++	ssv_sta_priv->ampdu_tid[tid].tidno = tid;
++	ssv_sta_priv->ampdu_tid[tid].sta = sta;
++	ssv_sta_priv->ampdu_tid[tid].agg_num_max = MAX_AGGR_NUM;
++	if (buffer_size > IEEE80211_MAX_AMPDU_BUF) {
++		buffer_size = IEEE80211_MAX_AMPDU_BUF;
++	}
++	dev_info(sc->dev, "AMPDU buffer_size=%d\n", buffer_size);
++	ssv_sta_priv->ampdu_tid[tid].ssv_baw_size = SSV_AMPDU_WINDOW_SIZE;
++	ssv_sta_priv->ampdu_tid[tid].state = AMPDU_STATE_OPERATION;
++}
++
++static void _clear_mpdu_q(struct ieee80211_hw *hw, struct sk_buff_head *q,
++			  bool aggregated_mpdu)
++{
++	struct sk_buff *skb;
++	while (1) {
++		skb = skb_dequeue(q);
++		if (!skb)
++			break;
++		if (aggregated_mpdu)
++			skb_pull(skb, AMPDU_DELIMITER_LEN);
++		ieee80211_tx_status_skb(hw, skb);
++	}
++}
++
++void ssv6200_ampdu_tx_stop(u16 tid, struct ieee80211_sta *sta,
++			   struct ieee80211_hw *hw)
++{
++	struct ssv_softc *sc = hw->priv;
++	struct ssv_sta_priv_data *ssv_sta_priv;
++	ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
++	if (ssv_sta_priv->ampdu_tid[tid].state == AMPDU_STATE_STOP)
++		return;
++	ssv_sta_priv->ampdu_tid[tid].state = AMPDU_STATE_STOP;
++	dev_dbg(sc->dev, "ssv6200_ampdu_tx_stop\n");
++	if (!list_empty(&sc->tx.ampdu_tx_que)) {
++#ifdef DEBUG_AMPDU_FLUSH
++		{
++			int j;
++			struct AMPDU_TID_st *ampdu_tid =
++			    &ssv_sta_priv->ampdu_tid[tid];
++			for (j = 0; j <= MAX_TID; j++) {
++				if (sc->tid[j] == ampdu_tid)
++					break;
++			}
++			if (j == MAX_TID) {
++				dev_dbg(sc->dev, "No TID found when deleting it.\n");
++			} else
++				sc->tid[j] = NULL;
++			dev_dbg(sc->dev, "Deleting %02X-%02X-%02X-%02X-%02X-%02X TID %d (%p).\n",
++			       sta->addr[0], sta->addr[1], sta->addr[2],
++			       sta->addr[3], sta->addr[4], sta->addr[5],
++			       ampdu_tid->tidno, ampdu_tid);
++		}
++#endif
++		list_del_rcu(&ssv_sta_priv->ampdu_tid[tid].list);
++	}
++	dev_dbg(sc->dev, "clear tx q len=%d\n",
++	       skb_queue_len(&ssv_sta_priv->ampdu_tid[tid].ampdu_skb_tx_queue));
++	_clear_mpdu_q(sc->hw, &ssv_sta_priv->ampdu_tid[tid].ampdu_skb_tx_queue,
++		      true);
++	dev_dbg(sc->dev, "clear retry q len=%d\n",
++	       skb_queue_len(&ssv_sta_priv->ampdu_tid[tid].retry_queue));
++	_clear_mpdu_q(sc->hw, &ssv_sta_priv->ampdu_tid[tid].retry_queue, true);
++#ifdef USE_ENCRYPT_WORK
++	dev_dbg(sc->dev, "clear encrypt q len=%d\n",
++	       skb_queue_len(&ssv_sta_priv->ampdu_tid[tid].
++			     ampdu_skb_wait_encry_queue));
++	_clear_mpdu_q(sc->hw,
++		      &ssv_sta_priv->ampdu_tid[tid].ampdu_skb_wait_encry_queue,
++		      false);
++#endif
++	if (ssv_sta_priv->ampdu_tid[tid].cur_ampdu_pkt != NULL) {
++		dev_kfree_skb_any(ssv_sta_priv->ampdu_tid[tid].cur_ampdu_pkt);
++		ssv_sta_priv->ampdu_tid[tid].cur_ampdu_pkt = NULL;
++	}
++	ssv6200_tx_flow_control((void *)sc,
++				sc->tx.hw_txqid[ssv_sta_priv->ampdu_tid[tid].
++						ac], false, 1000);
++}
++
++static void ssv6200_ampdu_tx_state_stop_func(struct ssv_softc *sc,
++					     struct ieee80211_sta *sta,
++					     struct sk_buff *skb,
++					     struct AMPDU_TID_st *cur_AMPDU_TID)
++{
++	struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
++	u8 *skb_qos_ctl = ieee80211_get_qos_ctl(hdr);
++	u8 tid_no = skb_qos_ctl[0] & 0xf;
++	if ((sta->deflink.ht_cap.ht_supported == true)
++	    && (!!(sc->sh->cfg.hw_caps & SSV6200_HW_CAP_AMPDU_TX))) {
++		ieee80211_start_tx_ba_session(sta, tid_no, 0);
++		ampdu_db_log("start ampdu_tx(rc) : tid_no = %d\n", tid_no);
++	}
++}
++
++static void ssv6200_ampdu_tx_state_operation_func(struct ssv_softc *sc,
++						  struct ieee80211_sta *sta,
++						  struct sk_buff *skb,
++						  struct AMPDU_TID_st
++						  *cur_AMPDU_TID)
++{
++}
++
++void ssv6200_ampdu_tx_update_state(void *priv, struct ieee80211_sta *sta,
++				   struct sk_buff *skb)
++{
++	struct ssv_softc *sc = (struct ssv_softc *)priv;
++	struct ssv_sta_priv_data *ssv_sta_priv =
++	    (struct ssv_sta_priv_data *)sta->drv_priv;
++	struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
++	u8 *skb_qos_ctl;
++	u8 tid_no;
++	{
++		skb_qos_ctl = ieee80211_get_qos_ctl(hdr);
++		tid_no = skb_qos_ctl[0] & 0xf;
++		switch (ssv_sta_priv->ampdu_tid[tid_no].state) {
++		case AMPDU_STATE_STOP:
++			ssv6200_ampdu_tx_state_stop_func(sc, sta, skb,
++							 &(ssv_sta_priv->
++							   ampdu_tid[tid_no]));
++			break;
++		case AMPDU_STATE_START:
++			break;
++		case AMPDU_STATE_OPERATION:
++			ssv6200_ampdu_tx_state_operation_func(sc, sta, skb,
++							      &(ssv_sta_priv->
++								ampdu_tid
++								[tid_no]));
++			break;
++		default:
++			break;
++		}
++	}
++}
++
++void _put_mpdu_to_ampdu(struct sk_buff *ampdu, struct sk_buff *mpdu)
++{
++	bool is_empty_ampdu = (ampdu->len == 0);
++	unsigned char *data_dest;
++	struct ampdu_hdr_st *ampdu_hdr = (struct ampdu_hdr_st *)ampdu->head;
++	BUG_ON(skb_tailroom(ampdu) < mpdu->len);
++	data_dest = skb_tail_pointer(ampdu);
++	skb_put(ampdu, mpdu->len);
++	if (is_empty_ampdu) {
++		struct ieee80211_tx_info *ampdu_info = IEEE80211_SKB_CB(ampdu);
++		struct ieee80211_tx_info *mpdu_info = IEEE80211_SKB_CB(mpdu);
++		SKB_info *mpdu_skb_info = (SKB_info *) (mpdu->head);
++		u32 max_size_for_rate =
++		    ampdu_max_transmit_length[mpdu_skb_info->lowest_rate];
++		BUG_ON(max_size_for_rate == 0);
++		memcpy(ampdu_info, mpdu_info, sizeof(struct ieee80211_tx_info));
++		skb_set_queue_mapping(ampdu, skb_get_queue_mapping(mpdu));
++		ampdu_hdr->first_sn = ampdu_skb_ssn(mpdu);
++		ampdu_hdr->sta = ((struct SKB_info_st *)mpdu->head)->sta;
++		if (ampdu_hdr->max_size > max_size_for_rate)
++			ampdu_hdr->max_size = max_size_for_rate;
++		memcpy(ampdu_hdr->rates, mpdu_skb_info->rates,
++		       sizeof(ampdu_hdr->rates));
++	}
++	memcpy(data_dest, mpdu->data, mpdu->len);
++	__skb_queue_tail(&ampdu_hdr->mpdu_q, mpdu);
++	ampdu_hdr->ssn[ampdu_hdr->mpdu_num++] = ampdu_skb_ssn(mpdu);
++	ampdu_hdr->size += mpdu->len;
++	BUG_ON(ampdu_hdr->size > ampdu_hdr->max_size);
++}
++
++u32 _flush_early_ampdu_q(struct ssv_softc *sc, struct AMPDU_TID_st *ampdu_tid)
++{
++	u32 flushed_ampdu = 0;
++	unsigned long flags;
++	struct sk_buff_head *early_aggr_ampdu_q =
++	    &ampdu_tid->early_aggr_ampdu_q;
++	spin_lock_irqsave(&early_aggr_ampdu_q->lock, flags);
++	while (skb_queue_len(early_aggr_ampdu_q)) {
++		struct sk_buff *head_ampdu;
++		struct ampdu_hdr_st *head_ampdu_hdr;
++		u32 ampdu_aggr_num;
++		head_ampdu = skb_peek(early_aggr_ampdu_q);
++		head_ampdu_hdr = (struct ampdu_hdr_st *)head_ampdu->head;
++		ampdu_aggr_num = skb_queue_len(&head_ampdu_hdr->mpdu_q);
++		if ((SSV_AMPDU_BA_WINDOW_SIZE - ampdu_tid->aggr_pkt_num)
++		    < ampdu_aggr_num)
++			break;
++		if (_sync_ampdu_pkt_arr(ampdu_tid, head_ampdu, false)) {
++			head_ampdu = __skb_dequeue(early_aggr_ampdu_q);
++			ampdu_tid->early_aggr_skb_num -= ampdu_aggr_num;
++#ifdef SSV_AMPDU_FLOW_CONTROL
++			if (ampdu_tid->early_aggr_skb_num
++			    <= SSV_AMPDU_FLOW_CONTROL_LOWER_BOUND) {
++				ssv6200_tx_flow_control((void *)sc,
++							sc->tx.
++							hw_txqid[ampdu_tid->ac],
++							false, 1000);
++			}
++#endif
++			if ((skb_queue_len(early_aggr_ampdu_q) == 0)
++			    && (ampdu_tid->early_aggr_skb_num > 0)) {
++				dev_warn(sc->dev, "Empty early Q w. %d.\n",
++				       ampdu_tid->early_aggr_skb_num);
++			}
++			spin_unlock_irqrestore(&early_aggr_ampdu_q->lock,
++					       flags);
++			_send_hci_skb(sc, head_ampdu,
++				      AMPDU_HCI_SEND_TAIL_WITHOUT_FLOWCTRL);
++			spin_lock_irqsave(&early_aggr_ampdu_q->lock, flags);
++			flushed_ampdu++;
++		} else
++			break;
++	}
++	spin_unlock_irqrestore(&early_aggr_ampdu_q->lock, flags);
++	return flushed_ampdu;
++}
++
++volatile int max_aggr_num = 24;
++void _aggr_ampdu_tx_q(struct ieee80211_hw *hw, struct AMPDU_TID_st *ampdu_tid)
++{
++	struct ssv_softc *sc = hw->priv;
++	struct sk_buff *ampdu_skb = ampdu_tid->cur_ampdu_pkt;
++	while (skb_queue_len(&ampdu_tid->ampdu_skb_tx_queue)) {
++		u32 aggr_len;
++		struct sk_buff *mpdu_skb;
++		struct ampdu_hdr_st *ampdu_hdr;
++		bool is_aggr_full = false;
++		if (ampdu_skb == NULL) {
++			ampdu_skb = _alloc_ampdu_skb(sc, ampdu_tid, 0);
++			if (ampdu_skb == NULL)
++				break;
++			ampdu_tid->cur_ampdu_pkt = ampdu_skb;
++		}
++		ampdu_hdr = (struct ampdu_hdr_st *)ampdu_skb->head;
++		aggr_len = skb_queue_len(&ampdu_hdr->mpdu_q);
++		do {
++			struct sk_buff_head *tx_q =
++			    &ampdu_tid->ampdu_skb_tx_queue;
++			unsigned long flags;
++			spin_lock_irqsave(&tx_q->lock, flags);
++			mpdu_skb = skb_peek(&ampdu_tid->ampdu_skb_tx_queue);
++			if (mpdu_skb == NULL) {
++				spin_unlock_irqrestore(&tx_q->lock, flags);
++				break;
++			}
++			if ((mpdu_skb->len + ampdu_hdr->size) >
++			    ampdu_hdr->max_size) {
++				is_aggr_full = true;
++				spin_unlock_irqrestore(&tx_q->lock, flags);
++				break;
++			}
++			mpdu_skb =
++			    __skb_dequeue(&ampdu_tid->ampdu_skb_tx_queue);
++			spin_unlock_irqrestore(&tx_q->lock, flags);
++			_put_mpdu_to_ampdu(ampdu_skb, mpdu_skb);
++		} while (++aggr_len < max_aggr_num);
++		if ((is_aggr_full || (aggr_len >= max_aggr_num))
++		    || ((aggr_len > 0)
++			&& (skb_queue_len(&ampdu_tid->early_aggr_ampdu_q) == 0)
++			&& (ampdu_tid->ssv_baw_head == SSV_ILLEGAL_SN)
++			&& _is_skb_q_empty(sc, ampdu_skb))) {
++			_add_ampdu_txinfo(sc, ampdu_skb);
++			_queue_early_ampdu(sc, ampdu_tid, ampdu_skb);
++			ampdu_tid->cur_ampdu_pkt = ampdu_skb = NULL;
++		}
++		_flush_early_ampdu_q(sc, ampdu_tid);
++	}
++}
++
++void _queue_early_ampdu(struct ssv_softc *sc, struct AMPDU_TID_st *ampdu_tid,
++			struct sk_buff *ampdu_skb)
++{
++	unsigned long flags;
++	struct ampdu_hdr_st *ampdu_hdr = (struct ampdu_hdr_st *)ampdu_skb->head;
++	spin_lock_irqsave(&ampdu_tid->early_aggr_ampdu_q.lock, flags);
++	__skb_queue_tail(&ampdu_tid->early_aggr_ampdu_q, ampdu_skb);
++	ampdu_tid->early_aggr_skb_num += skb_queue_len(&ampdu_hdr->mpdu_q);
++#ifdef SSV_AMPDU_FLOW_CONTROL
++	if (ampdu_tid->early_aggr_skb_num >= SSV_AMPDU_FLOW_CONTROL_UPPER_BOUND) {
++		ssv6200_tx_flow_control((void *)sc,
++					sc->tx.hw_txqid[ampdu_tid->ac], true,
++					1000);
++	}
++#endif
++	spin_unlock_irqrestore(&ampdu_tid->early_aggr_ampdu_q.lock, flags);
++}
++
++void _flush_mpdu(struct ssv_softc *sc, struct ieee80211_sta *sta)
++{
++	unsigned long flags;
++	struct ssv_sta_priv_data *ssv_sta_priv =
++	    (struct ssv_sta_priv_data *)sta->drv_priv;
++	int i;
++	for (i = 0;
++	     i <
++	     (sizeof(ssv_sta_priv->ampdu_tid) /
++	      sizeof(ssv_sta_priv->ampdu_tid[0])); i++) {
++		struct AMPDU_TID_st *ampdu_tid = &ssv_sta_priv->ampdu_tid[i];
++		struct sk_buff_head *early_aggr_ampdu_q;
++		struct sk_buff *ampdu;
++		struct ampdu_hdr_st *ampdu_hdr;
++		struct sk_buff_head *mpdu_q;
++		struct sk_buff *mpdu;
++		if (ampdu_tid->state != AMPDU_STATE_OPERATION)
++			continue;
++		early_aggr_ampdu_q = &ampdu_tid->early_aggr_ampdu_q;
++		spin_lock_irqsave(&early_aggr_ampdu_q->lock, flags);
++		while ((ampdu = __skb_dequeue(early_aggr_ampdu_q)) != NULL) {
++			ampdu_hdr = (struct ampdu_hdr_st *)ampdu->head;
++			mpdu_q = &ampdu_hdr->mpdu_q;
++			spin_unlock_irqrestore(&early_aggr_ampdu_q->lock,
++					       flags);
++			while ((mpdu = __skb_dequeue(mpdu_q)) != NULL) {
++				_send_hci_skb(sc, mpdu,
++					      AMPDU_HCI_SEND_TAIL_WITHOUT_FLOWCTRL);
++			}
++			ssv6200_ampdu_release_skb(ampdu, sc->hw);
++			spin_lock_irqsave(&early_aggr_ampdu_q->lock, flags);
++		}
++		if (ampdu_tid->cur_ampdu_pkt != NULL) {
++			ampdu_hdr =
++			    (struct ampdu_hdr_st *)ampdu_tid->cur_ampdu_pkt->
++			    head;
++			mpdu_q = &ampdu_hdr->mpdu_q;
++			spin_unlock_irqrestore(&early_aggr_ampdu_q->lock,
++					       flags);
++			while ((mpdu = __skb_dequeue(mpdu_q)) != NULL) {
++				_send_hci_skb(sc, mpdu,
++					      AMPDU_HCI_SEND_TAIL_WITHOUT_FLOWCTRL);
++			}
++			ssv6200_ampdu_release_skb(ampdu_tid->cur_ampdu_pkt,
++						  sc->hw);
++			spin_lock_irqsave(&early_aggr_ampdu_q->lock, flags);
++			ampdu_tid->cur_ampdu_pkt = NULL;
++		}
++		spin_unlock_irqrestore(&early_aggr_ampdu_q->lock, flags);
++	}
++}
++
++bool ssv6200_ampdu_tx_handler(struct ieee80211_hw *hw, struct sk_buff *skb)
++{
++	struct ssv_softc *sc = hw->priv;
++	struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
++#ifdef REPORT_TX_STATUS_DIRECTLY
++	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
++	struct sk_buff *tx_skb = skb;
++	struct sk_buff *copy_skb = NULL;
++#endif
++	struct SKB_info_st *mpdu_skb_info_p = (SKB_info *) (skb->head);
++	struct ieee80211_sta *sta = mpdu_skb_info_p->sta;
++	struct ssv_sta_priv_data *ssv_sta_priv =
++	    (struct ssv_sta_priv_data *)sta->drv_priv;
++	u8 tidno;
++	struct AMPDU_TID_st *ampdu_tid;
++	if (sta == NULL) {
++		WARN_ON(1);
++		return false;
++	}
++	tidno = ieee80211_get_qos_ctl(hdr)[0] & IEEE80211_QOS_CTL_TID_MASK;
++	ampdu_db_log("tidno = %d\n", tidno);
++	ampdu_tid = &ssv_sta_priv->ampdu_tid[tidno];
++	if (ampdu_tid->state != AMPDU_STATE_OPERATION)
++		return false;
++#ifdef AMPDU_CHECK_SKB_SEQNO
++	{
++		u32 skb_seqno = ((struct ieee80211_hdr *)(skb->data))->seq_ctrl
++		    >> SSV_SEQ_NUM_SHIFT;
++		u32 tid_seqno = ampdu_tid->last_seqno;
++		if ((tid_seqno != (-1))
++		    && (skb_seqno != NEXT_PKT_SN(tid_seqno))) {
++			prn_aggr_err("Non continueous seq no: %d - %d\n",
++				     tid_seqno, skb_seqno);
++			return false;
++		}
++		ampdu_tid->last_seqno = skb_seqno;
++	}
++#endif
++	mpdu_skb_info_p->lowest_rate =
++	    ssv62xx_ht_rate_update(skb, sc, mpdu_skb_info_p->rates);
++	if (ampdu_max_transmit_length[mpdu_skb_info_p->lowest_rate] == 0) {
++		_flush_mpdu(sc, sta);
++		return false;
++	}
++	mpdu_skb_info_p = (SKB_info *) (skb->head);
++	mpdu_skb_info_p->mpdu_retry_counter = 0;
++	mpdu_skb_info_p->ampdu_tx_status = AMPDU_ST_NON_AMPDU;
++	mpdu_skb_info_p->ampdu_tx_final_retry_count = 0;
++	ssv_sta_priv->ampdu_tid[tidno].ac = skb_get_queue_mapping(skb);
++#ifdef REPORT_TX_STATUS_DIRECTLY
++	info->flags |= IEEE80211_TX_STAT_ACK;
++	copy_skb = skb_copy(tx_skb, GFP_ATOMIC);
++	if (!copy_skb) {
++		dev_err(sc->dev, "create TX skb copy failed!\n");
++		return false;
++	}
++	ieee80211_tx_status_skb(sc->hw, tx_skb);
++	skb = copy_skb;
++#endif
++	{
++		bool ret;
++		ret = ssv6200_ampdu_add_delimiter_and_crc32(skb);
++		if (ret == false) {
++			ssv6200_ampdu_release_skb(skb, hw);
++			return false;
++		}
++		skb_queue_tail(&ssv_sta_priv->ampdu_tid[tidno].
++			       ampdu_skb_tx_queue, skb);
++		ssv_sta_priv->ampdu_tid[tidno].timestamp = jiffies;
++	}
++	_aggr_ampdu_tx_q(hw, &ssv_sta_priv->ampdu_tid[tidno]);
++	return true;
++}
++
++u32 ssv6xxx_ampdu_flush(struct ieee80211_hw *hw)
++{
++	struct ssv_softc *sc = hw->priv;
++	struct AMPDU_TID_st *cur_AMPDU_TID;
++	u32 flushed_ampdu = 0;
++	u32 tid_idx = 0;
++	if (!list_empty(&sc->tx.ampdu_tx_que)) {
++		list_for_each_entry_rcu(cur_AMPDU_TID, &sc->tx.ampdu_tx_que,
++					list) {
++			tid_idx++;
++#ifdef DEBUG_AMPDU_FLUSH
++			{
++				int i = 0;
++				for (i = 0; i < MAX_TID; i++)
++					if (sc->tid[i] == cur_AMPDU_TID)
++						break;
++				if (i == MAX_TID) {
++					dev_err(sc->dev, "No matching TID (%d) found! %p\n",
++					       tid_idx, cur_AMPDU_TID);
++					continue;
++				}
++			}
++#endif
++			if (cur_AMPDU_TID->state != AMPDU_STATE_OPERATION) {
++				struct ieee80211_sta *sta = cur_AMPDU_TID->sta;
++				struct ssv_sta_priv_data *sta_priv =
++				    (struct ssv_sta_priv_data *)sta->drv_priv;
++				dev_dbg(sc->dev, "STA %d TID %d is @%d\n",
++					sta_priv->sta_idx, cur_AMPDU_TID->tidno,
++					cur_AMPDU_TID->state);
++				continue;
++			}
++			if ((cur_AMPDU_TID->state == AMPDU_STATE_OPERATION)
++			    &&
++			    (skb_queue_len(&cur_AMPDU_TID->early_aggr_ampdu_q)
++			     == 0)
++			    && (cur_AMPDU_TID->cur_ampdu_pkt != NULL)) {
++				struct ampdu_hdr_st *ampdu_hdr =
++				    (struct ampdu_hdr_st *)(cur_AMPDU_TID->
++							    cur_ampdu_pkt->
++							    head);
++				u32 aggr_len =
++				    skb_queue_len(&ampdu_hdr->mpdu_q);
++				if (aggr_len) {
++					struct sk_buff *ampdu_skb =
++					    cur_AMPDU_TID->cur_ampdu_pkt;
++					cur_AMPDU_TID->cur_ampdu_pkt = NULL;
++					_add_ampdu_txinfo(sc, ampdu_skb);
++					_queue_early_ampdu(sc, cur_AMPDU_TID,
++							   ampdu_skb);
++				}
++			}
++			if (skb_queue_len(&cur_AMPDU_TID->early_aggr_ampdu_q) >
++			    0)
++				flushed_ampdu +=
++				    _flush_early_ampdu_q(sc, cur_AMPDU_TID);
++		}
++	}
++	return flushed_ampdu;
++}
++
++int _dump_BA_notification(char *buf,
++			  struct ampdu_ba_notify_data *ba_notification)
++{
++	int i;
++	char *orig_buf = buf;
++	for (i = 0; i < MAX_AGGR_NUM; i++) {
++		if (ba_notification->seq_no[i] == (u16) (-1))
++			break;
++		buf += sprintf(buf, " %d", ba_notification->seq_no[i]);
++	}
++	return ((size_t)buf - (size_t)orig_buf);
++}
++
++int _dump_ba_skb(char *buf, int buf_size, struct sk_buff *ba_skb)
++{
++	struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)(ba_skb->data
++							     +
++							     SSV6XXX_RX_DESC_LEN);
++	AMPDU_BLOCKACK *BA_frame = (AMPDU_BLOCKACK *) hdr;
++	u32 ssn = BA_frame->BA_ssn;
++	struct ampdu_ba_notify_data *ba_notification =
++	    (struct ampdu_ba_notify_data *)(ba_skb->data + ba_skb->len
++					    -
++					    sizeof(struct
++						   ampdu_ba_notify_data));
++	int prt_size;
++	prt_size = snprintf(buf, buf_size, "\n\t\t%04d %08X %08X -",
++			    ssn, BA_frame->BA_sn_bit_map[0],
++			    BA_frame->BA_sn_bit_map[1]);
++	buf_size -= prt_size;
++	buf += prt_size;
++	prt_size = prt_size + _dump_BA_notification(buf, ba_notification);
++	return prt_size;
++}
++
++static bool _ssn_to_bit_idx(u32 start_ssn, u32 mpdu_ssn, u32 * word_idx,
++			    u32 * bit_idx)
++{
++	u32 ret_bit_idx, ret_word_idx = 0;
++	s32 diff = mpdu_ssn - start_ssn;
++	if (diff >= 0) {
++		if (diff >= SSV_AMPDU_BA_WINDOW_SIZE) {
++			return false;
++		}
++		ret_bit_idx = diff;
++	} else {
++		diff = -diff;
++		if (diff <= (SSV_AMPDU_MAX_SSN - SSV_AMPDU_BA_WINDOW_SIZE)) {
++			*word_idx = 0;
++			*bit_idx = 0;
++			return false;
++		}
++		ret_bit_idx = SSV_AMPDU_MAX_SSN - diff;
++	}
++	if (ret_bit_idx >= 32) {
++		ret_bit_idx -= 32;
++		ret_word_idx = 1;
++	}
++	*bit_idx = ret_bit_idx;
++	*word_idx = ret_word_idx;
++	return true;
++}
++
++static bool _inc_bit_idx(u32 ssn_1st, u32 ssn_next, u32 * word_idx,
++			 u32 * bit_idx)
++{
++	u32 ret_word_idx = *word_idx, ret_bit_idx = *bit_idx;
++	s32 diff = (s32) ssn_1st - (s32) ssn_next;
++	if (diff > 0) {
++		if (diff < (SSV_AMPDU_MAX_SSN - SSV_AMPDU_BA_WINDOW_SIZE)) {
++			prn_aggr_err
++			    ("Irrational SN distance in AMPDU: %d %d.\n",
++			     ssn_1st, ssn_next);
++			return false;
++		}
++		diff = SSV_AMPDU_MAX_SSN - diff;
++	} else {
++		diff = -diff;
++	}
++	if (diff > SSV_AMPDU_MAX_SSN)
++		prn_aggr_err("DF %d - %d = %d\n", ssn_1st, ssn_next, diff);
++	ret_bit_idx += diff;
++	if (ret_bit_idx >= 32) {
++		ret_bit_idx -= 32;
++		ret_word_idx++;
++	}
++	*word_idx = ret_word_idx;
++	*bit_idx = ret_bit_idx;
++	return true;
++}
++
++static void _release_frames(struct AMPDU_TID_st *ampdu_tid)
++{
++	u32 head_ssn, head_ssn_before, last_ssn;
++	struct sk_buff **skb;
++	struct SKB_info_st *skb_info;
++	spin_lock_bh(&ampdu_tid->pkt_array_lock);
++	head_ssn_before = ampdu_tid->ssv_baw_head;
++	if (head_ssn_before >= SSV_AMPDU_MAX_SSN) {
++		spin_unlock_bh(&ampdu_tid->pkt_array_lock);
++		prn_aggr_err("l x.x %d\n", head_ssn_before);
++		return;
++	}
++	head_ssn = ampdu_tid->ssv_baw_head;
++	last_ssn = head_ssn;
++	do {
++		skb = &INDEX_PKT_BY_SSN(ampdu_tid, head_ssn);
++		if (*skb == NULL) {
++			head_ssn = SSV_ILLEGAL_SN;
++			{
++				int i;
++				char sn_str[66 * 5] = "";
++				char *str = sn_str;
++				for (i = 0; i < 64; i++)
++					if (ampdu_tid->aggr_pkts[i] != NULL) {
++						str += sprintf(str, "%d ",
++							       ampdu_skb_ssn
++							       (ampdu_tid->
++								aggr_pkts[i]));
++					}
++				*str = 0;
++				if (str == sn_str) {
++				} else
++					prn_aggr_err("ILL %d %d - %d (%s)\n",
++						     head_ssn_before, last_ssn,
++						     ampdu_tid->aggr_pkt_num,
++						     sn_str);
++			}
++			break;
++		}
++		skb_info = (struct SKB_info_st *)((*skb)->head);
++		if ((skb_info->ampdu_tx_status == AMPDU_ST_DONE)
++		    || (skb_info->ampdu_tx_status == AMPDU_ST_DROPPED)) {
++			__skb_queue_tail(&ampdu_tid->release_queue, *skb);
++			*skb = NULL;
++			last_ssn = head_ssn;
++			INC_PKT_SN(head_ssn);
++			ampdu_tid->aggr_pkt_num--;
++			if (skb_info->ampdu_tx_status == AMPDU_ST_DROPPED)
++				ampdu_tid->mib.ampdu_mib_discard_counter++;
++		} else {
++			break;
++		}
++	} while (1);
++	ampdu_tid->ssv_baw_head = head_ssn;
++	spin_unlock_bh(&ampdu_tid->pkt_array_lock);
++}
++
++static int _collect_retry_frames(struct AMPDU_TID_st *ampdu_tid)
++{
++	u16 ssn, head_ssn, end_ssn;
++	int num_retry = 0;
++	int timeout_check = 1;
++	unsigned long check_jiffies = jiffies;
++	head_ssn = ampdu_tid->ssv_baw_head;
++	ssn = head_ssn;
++	if (ssn == SSV_ILLEGAL_SN)
++		return 0;
++	end_ssn = (head_ssn + SSV_AMPDU_BA_WINDOW_SIZE) % SSV_AMPDU_MAX_SSN;
++	do {
++		struct sk_buff *skb = INDEX_PKT_BY_SSN(ampdu_tid, ssn);
++		struct SKB_info_st *skb_info;
++		int timeout_retry = 0;
++		if (skb == NULL)
++			break;
++		skb_info = (SKB_info *) (skb->head);
++		if (timeout_check
++		    && (skb_info->ampdu_tx_status == AMPDU_ST_SENT)) {
++			unsigned long cur_jiffies = jiffies;
++			unsigned long timeout_jiffies = skb_info->aggr_timestamp
++			    + msecs_to_jiffies(BA_WAIT_TIMEOUT);
++			u32 delta_ms;
++			if (time_before(cur_jiffies, timeout_jiffies)) {
++				timeout_check = 0;
++				continue;
++			}
++			_mark_skb_retry(skb_info, skb);
++			delta_ms =
++			    jiffies_to_msecs(cur_jiffies -
++					     skb_info->aggr_timestamp);
++			prn_aggr_err("t S%d-T%d-%d (%u)\n",
++				     ((struct ssv_sta_priv_data *)skb_info->
++				      sta->drv_priv)->sta_idx, ampdu_tid->tidno,
++				     ssn, delta_ms);
++			if (delta_ms > 1000) {
++				prn_aggr_err("Last checktime %lu - %lu = %u\n",
++					     check_jiffies,
++					     ampdu_tid->timestamp,
++					     jiffies_to_msecs(check_jiffies -
++							      ampdu_tid->
++							      timestamp));
++			}
++			timeout_retry = 1;
++		}
++		if (skb_info->ampdu_tx_status == AMPDU_ST_RETRY) {
++			skb_queue_tail(&ampdu_tid->retry_queue, skb);
++			ampdu_tid->mib.ampdu_mib_retry_counter++;
++			num_retry++;
++		}
++		INC_PKT_SN(ssn);
++	} while (ssn != end_ssn);
++	ampdu_tid->timestamp = check_jiffies;
++	return num_retry;
++}
++
++int _mark_skb_retry(struct SKB_info_st *skb_info, struct sk_buff *skb)
++{
++	if (skb_info->mpdu_retry_counter < SSV_AMPDU_retry_counter_max) {
++		if (skb_info->mpdu_retry_counter == 0) {
++			struct ieee80211_hdr *skb_hdr = ampdu_skb_hdr(skb);
++			skb_hdr->frame_control |=
++			    cpu_to_le16(IEEE80211_FCTL_RETRY);
++		}
++		skb_info->ampdu_tx_status = AMPDU_ST_RETRY;
++		skb_info->mpdu_retry_counter++;
++		return 1;
++	} else {
++		skb_info->ampdu_tx_status = AMPDU_ST_DROPPED;
++		prn_aggr_err("p %d\n", ampdu_skb_ssn(skb));
++		return 0;
++	}
++}
++
++static u32 _ba_map_walker(struct AMPDU_TID_st *ampdu_tid, u32 start_ssn,
++			  u32 sn_bit_map[2],
++			  struct ampdu_ba_notify_data *ba_notify_data,
++			  u32 * p_acked_num)
++{
++	int i = 0;
++	u32 ssn = ba_notify_data->seq_no[0];
++	u32 word_idx = (-1), bit_idx = (-1);
++	bool found = _ssn_to_bit_idx(start_ssn, ssn, &word_idx, &bit_idx);
++	bool first_found = found;
++	u32 aggr_num = 0;
++	u32 acked_num = 0;
++	if (found && (word_idx >= 2 || bit_idx >= 32))
++		prn_aggr_err("idx error 1: %d %d %d %d\n",
++			     start_ssn, ssn, word_idx, bit_idx);
++	while ((i < MAX_AGGR_NUM) && (ssn < SSV_AMPDU_MAX_SSN)) {
++		u32 cur_ssn;
++		struct sk_buff *skb = INDEX_PKT_BY_SSN(ampdu_tid, ssn);
++		u32 skb_ssn = (skb == NULL) ? (-1) : ampdu_skb_ssn(skb);
++		struct SKB_info_st *skb_info;
++		aggr_num++;
++		if (skb_ssn != ssn) {
++			prn_aggr_err("Unmatched SSN packet: %d - %d - %d\n",
++				     ssn, skb_ssn, start_ssn);
++		} else {
++			skb_info = (struct SKB_info_st *)(skb->head);
++			if (found && (sn_bit_map[word_idx] & (1 << bit_idx))) {
++				if (skb_info->ampdu_tx_status != AMPDU_ST_SENT) {
++					pr_err("BA marks a MPDU of status %d!\n",
++					       skb_info->ampdu_tx_status);
++				}
++				skb_info->ampdu_tx_status = AMPDU_ST_DONE;
++				acked_num++;
++			} else {
++				_mark_skb_retry(skb_info, skb);
++			}
++		}
++		cur_ssn = ssn;
++		if (++i >= MAX_AGGR_NUM)
++			break;
++		ssn = ba_notify_data->seq_no[i];
++		if (ssn >= SSV_AMPDU_MAX_SSN)
++			break;
++		if (first_found) {
++			u32 old_word_idx = word_idx, old_bit_idx = bit_idx;
++			found = _inc_bit_idx(cur_ssn, ssn, &word_idx, &bit_idx);
++			if (found && (word_idx >= 2 || bit_idx >= 32)) {
++				prn_aggr_err
++				    ("idx error 2: %d 0x%08X 0X%08X %d %d (%d %d) (%d %d)\n",
++				     start_ssn, sn_bit_map[1], sn_bit_map[0],
++				     cur_ssn, ssn, word_idx, bit_idx,
++				     old_word_idx, old_bit_idx);
++				found = false;
++			} else if (!found) {
++				char strbuf[256];
++				_dump_BA_notification(strbuf, ba_notify_data);
++				prn_aggr_err("SN out-of-order: %d\n%s\n",
++					     start_ssn, strbuf);
++			}
++		} else {
++			found =
++			    _ssn_to_bit_idx(start_ssn, ssn, &word_idx,
++					    &bit_idx);
++			first_found = found;
++			if (found && (word_idx >= 2 || bit_idx >= 32))
++				prn_aggr_err("idx error 3: %d %d %d %d\n",
++					     cur_ssn, ssn, word_idx, bit_idx);
++		}
++	}
++	_release_frames(ampdu_tid);
++	if (p_acked_num != NULL)
++		*p_acked_num = acked_num;
++	return aggr_num;
++}
++
++static void _flush_release_queue(struct ieee80211_hw *hw,
++				 struct sk_buff_head *release_queue)
++{
++	do {
++		struct sk_buff *ampdu_skb = __skb_dequeue(release_queue);
++		struct ieee80211_tx_info *tx_info;
++		struct SKB_info_st *skb_info;
++		if (ampdu_skb == NULL)
++			break;
++		skb_info = (struct SKB_info_st *)(ampdu_skb->head);
++		skb_pull(ampdu_skb, AMPDU_DELIMITER_LEN);
++		tx_info = IEEE80211_SKB_CB(ampdu_skb);
++		ieee80211_tx_info_clear_status(tx_info);
++		tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
++		if (skb_info->ampdu_tx_status == AMPDU_ST_DONE)
++			tx_info->flags |= IEEE80211_TX_STAT_ACK;
++		tx_info->status.ampdu_len = 1;
++		tx_info->status.ampdu_ack_len = 1;
++#ifdef REPORT_TX_STATUS_DIRECTLY
++		dev_kfree_skb_any(ampdu_skb);
++#else
++#if defined(USE_THREAD_RX) && !defined(IRQ_PROC_TX_DATA)
++		ieee80211_tx_status_skb(hw, ampdu_skb);
++#else
++		ieee80211_tx_status_irqsafe(hw, ampdu_skb);
++#endif
++#endif
++	} while (1);
++}
++
++void ssv6200_ampdu_no_BA_handler(struct ieee80211_hw *hw, struct sk_buff *skb)
++{
++	struct cfg_host_event *host_event = (struct cfg_host_event *)skb->data;
++	struct ampdu_ba_notify_data *ba_notification =
++	    (struct ampdu_ba_notify_data *)&host_event->dat[0];
++	struct ieee80211_hdr *hdr =
++	    (struct ieee80211_hdr *)(ba_notification + 1);
++	struct ssv_softc *sc = hw->priv;
++	struct ieee80211_sta *sta = ssv6xxx_find_sta_by_addr(sc, hdr->addr1);
++	u8 tidno = ieee80211_get_qos_ctl(hdr)[0] & IEEE80211_QOS_CTL_TID_MASK;
++	struct ssv_sta_priv_data *ssv_sta_priv;
++	char seq_str[256];
++	struct AMPDU_TID_st *ampdu_tid;
++	int i;
++	u16 aggr_num = 0;
++	struct firmware_rate_control_report_data *report_data;
++	if (sta == NULL) {
++		prn_aggr_err
++		    ("NO BA for %d to unmatched STA %02X-%02X-%02X-%02X-%02X-%02X: %s\n",
++		     tidno, hdr->addr1[0], hdr->addr1[1], hdr->addr1[2],
++		     hdr->addr1[3], hdr->addr1[4], hdr->addr1[5], seq_str);
++		dev_kfree_skb_any(skb);
++		return;
++	}
++	ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
++	_dump_BA_notification(seq_str, ba_notification);
++	prn_aggr_err("NO BA for %d to %02X-%02X-%02X-%02X-%02X-%02X: %s\n",
++		     tidno, sta->addr[0], sta->addr[1], sta->addr[2],
++		     sta->addr[3], sta->addr[4], sta->addr[5], seq_str);
++	ampdu_tid = &ssv_sta_priv->ampdu_tid[tidno];
++	if (ampdu_tid->state != AMPDU_STATE_OPERATION) {
++		dev_kfree_skb_any(skb);
++		return;
++	}
++	for (i = 0; i < MAX_AGGR_NUM; i++) {
++		u32 ssn = ba_notification->seq_no[i];
++		struct sk_buff *skb;
++		u32 skb_ssn;
++		struct SKB_info_st *skb_info;
++		if (ssn >= (4096))
++			break;
++		aggr_num++;
++		skb = INDEX_PKT_BY_SSN(ampdu_tid, ssn);
++		skb_ssn = (skb == NULL) ? (-1) : ampdu_skb_ssn(skb);
++		if (skb_ssn != ssn) {
++			prn_aggr_err("Unmatched SSN packet: %d - %d\n", ssn,
++				     skb_ssn);
++			continue;
++		}
++		skb_info = (struct SKB_info_st *)(skb->head);
++		if (skb_info->ampdu_tx_status == AMPDU_ST_SENT) {
++			if (skb_info->mpdu_retry_counter <
++			    SSV_AMPDU_retry_counter_max) {
++				if (skb_info->mpdu_retry_counter == 0) {
++					struct ieee80211_hdr *skb_hdr =
++					    ampdu_skb_hdr(skb);
++					skb_hdr->frame_control |=
++					    cpu_to_le16(IEEE80211_FCTL_RETRY);
++				}
++				skb_info->ampdu_tx_status = AMPDU_ST_RETRY;
++				skb_info->mpdu_retry_counter++;
++			} else {
++				skb_info->ampdu_tx_status = AMPDU_ST_DROPPED;
++				prn_aggr_err("p %d\n", skb_ssn);
++			}
++		} else {
++			prn_aggr_err("S %d %d\n", skb_ssn,
++				     skb_info->ampdu_tx_status);
++		}
++	}
++	_release_frames(ampdu_tid);
++	host_event->h_event = SOC_EVT_RC_AMPDU_REPORT;
++	report_data =
++	    (struct firmware_rate_control_report_data *)&host_event->dat[0];
++	report_data->ampdu_len = aggr_num;
++	report_data->ampdu_ack_len = 0;
++	report_data->wsid = ssv_sta_priv->sta_info->hw_wsid;
++	skb_queue_tail(&sc->rc_report_queue, skb);
++	if (sc->rc_sample_sechedule == 0)
++		queue_work(sc->rc_sample_workqueue, &sc->rc_sample_work);
++}
++
++void ssv6200_ampdu_BA_handler(struct ieee80211_hw *hw, struct sk_buff *skb)
++{
++	struct ssv_softc *sc = hw->priv;
++	struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)(skb->data
++							     +
++							     SSV6XXX_RX_DESC_LEN);
++	AMPDU_BLOCKACK *BA_frame = (AMPDU_BLOCKACK *) hdr;
++	struct ieee80211_sta *sta;
++	struct ssv_sta_priv_data *ssv_sta_priv;
++	struct ampdu_ba_notify_data *ba_notification;
++	u32 ssn, aggr_num = 0, acked_num = 0;
++	u8 tid_no;
++	u32 sn_bit_map[2];
++	struct firmware_rate_control_report_data *report_data;
++	HDR_HostEvent *host_evt;
++	sta = ssv6xxx_find_sta_by_rx_skb(sc, skb);
++	if (sta == NULL) {
++		if (skb->len > AMPDU_BA_FRAME_LEN) {
++			char strbuf[256];
++			struct ampdu_ba_notify_data *ba_notification =
++			    (struct ampdu_ba_notify_data *)(skb->data + skb->len
++							    -
++							    sizeof(struct
++								   ampdu_ba_notify_data));
++			_dump_BA_notification(strbuf, ba_notification);
++			prn_aggr_err
++			    ("BA from not connected STA (%02X-%02X-%02X-%02X-%02X-%02X) (%s)\n",
++			     BA_frame->ta_addr[0], BA_frame->ta_addr[1],
++			     BA_frame->ta_addr[2], BA_frame->ta_addr[3],
++			     BA_frame->ta_addr[4], BA_frame->ta_addr[5],
++			     strbuf);
++		}
++		dev_kfree_skb_any(skb);
++		return;
++	}
++	ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
++	ssn = BA_frame->BA_ssn;
++	sn_bit_map[0] = BA_frame->BA_sn_bit_map[0];
++	sn_bit_map[1] = BA_frame->BA_sn_bit_map[1];
++	tid_no = BA_frame->tid_info;
++	ssv_sta_priv->ampdu_mib_total_BA_counter++;
++	if (ssv_sta_priv->ampdu_tid[tid_no].state == AMPDU_STATE_STOP) {
++		prn_aggr_err
++		    ("ssv6200_ampdu_BA_handler state == AMPDU_STATE_STOP.\n");
++		dev_kfree_skb_any(skb);
++		return;
++	}
++	ssv_sta_priv->ampdu_tid[tid_no].mib.ampdu_mib_BA_counter++;
++	if (skb->len <= AMPDU_BA_FRAME_LEN) {
++		prn_aggr_err("b %d\n", ssn);
++		dev_kfree_skb_any(skb);
++		return;
++	}
++	ba_notification =
++	    (struct ampdu_ba_notify_data *)(skb->data + skb->len
++					    -
++					    sizeof(struct
++						   ampdu_ba_notify_data));
++	aggr_num =
++	    _ba_map_walker(&(ssv_sta_priv->ampdu_tid[tid_no]), ssn, sn_bit_map,
++			   ba_notification, &acked_num);
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	if (ssv_sta_priv->ampdu_tid[tid_no].debugfs_dir) {
++		struct sk_buff *dup_skb;
++		if (skb_queue_len(&ssv_sta_priv->ampdu_tid[tid_no].ba_q) > 24) {
++			struct sk_buff *ba_skb =
++			    skb_dequeue(&ssv_sta_priv->ampdu_tid[tid_no].ba_q);
++			if (ba_skb)
++				dev_kfree_skb_any(ba_skb);
++		}
++		dup_skb = skb_clone(skb, GFP_ATOMIC);
++		if (dup_skb)
++			skb_queue_tail(&ssv_sta_priv->ampdu_tid[tid_no].ba_q,
++				       dup_skb);
++	}
++#endif
++	skb_trim(skb, skb->len - sizeof(struct ampdu_ba_notify_data));
++	host_evt = (HDR_HostEvent *) skb->data;
++	host_evt->h_event = SOC_EVT_RC_AMPDU_REPORT;
++	report_data =
++	    (struct firmware_rate_control_report_data *)&host_evt->dat[0];
++	memcpy(report_data, ba_notification,
++	       sizeof(struct firmware_rate_control_report_data));
++	report_data->ampdu_len = aggr_num;
++	report_data->ampdu_ack_len = acked_num;
++#ifdef RATE_CONTROL_HT_PERCENTAGE_TRACE
++	if ((acked_num) && (acked_num != aggr_num)) {
++		int i;
++		for (i = 0; i < SSV62XX_TX_MAX_RATES; i++) {
++			if (report_data->rates[i].data_rate == -1)
++				break;
++			if (report_data->rates[i].count == 0)
++                dev_err(sc->dev, "illegal HT report\n");
++
++			dev_dbg(sc->dev, "i=[%d] rate[%d] count[%d]\n", i,
++			       report_data->rates[i].data_rate,
++			       report_data->rates[i].count);
++		}
++		dev_dbg(sc->dev, "AMPDU percentage = %d%% \n",
++		       acked_num * 100 / aggr_num);
++	} else if (acked_num == 0) {
++		dev_dbg(sc->dev, "AMPDU percentage = 0%% aggr_num=%d acked_num=%d\n",
++		       aggr_num, acked_num);
++	}
++#endif
++	skb_queue_tail(&sc->rc_report_queue, skb);
++	if (sc->rc_sample_sechedule == 0)
++		queue_work(sc->rc_sample_workqueue, &sc->rc_sample_work);
++}
++
++static void _postprocess_BA(struct ssv_softc *sc, struct ssv_sta_info *sta_info,
++			    void *param)
++{
++	int j;
++	struct ssv_sta_priv_data *ssv_sta_priv;
++	if ((sta_info->sta == NULL)
++	    || ((sta_info->s_flags & STA_FLAG_VALID) == 0))
++		return;
++	ssv_sta_priv = (struct ssv_sta_priv_data *)sta_info->sta->drv_priv;
++	for (j = 0; j < WMM_TID_NUM; j++) {
++		AMPDU_TID *ampdu_tid = &ssv_sta_priv->ampdu_tid[j];
++		if (ampdu_tid->state != AMPDU_STATE_OPERATION)
++			continue;
++		_collect_retry_frames(ampdu_tid);
++		ssv6200_ampdu_send_retry(sc->hw, ampdu_tid,
++					 &ampdu_tid->retry_queue, true);
++		_flush_early_ampdu_q(sc, ampdu_tid);
++		_flush_release_queue(sc->hw, &ampdu_tid->release_queue);
++	}
++}
++
++void ssv6xxx_ampdu_postprocess_BA(struct ieee80211_hw *hw)
++{
++	struct ssv_softc *sc = hw->priv;
++	ssv6xxx_foreach_sta(sc, _postprocess_BA, NULL);
++}
++
++static void ssv6200_hw_set_rx_ba_session(struct ssv_hw *sh, bool on, u8 * ta,
++					 u16 tid, u16 ssn, u8 buf_size)
++{
++	if (on) {
++		u32 u32ta;
++		u32ta = 0;
++		u32ta |= (ta[0] & 0xff) << (8 * 0);
++		u32ta |= (ta[1] & 0xff) << (8 * 1);
++		u32ta |= (ta[2] & 0xff) << (8 * 2);
++		u32ta |= (ta[3] & 0xff) << (8 * 3);
++		SMAC_REG_WRITE(sh, ADR_BA_TA_0, u32ta);
++		u32ta = 0;
++		u32ta |= (ta[4] & 0xff) << (8 * 0);
++		u32ta |= (ta[5] & 0xff) << (8 * 1);
++		SMAC_REG_WRITE(sh, ADR_BA_TA_1, u32ta);
++		SMAC_REG_WRITE(sh, ADR_BA_TID, tid);
++		SMAC_REG_WRITE(sh, ADR_BA_ST_SEQ, ssn);
++		SMAC_REG_WRITE(sh, ADR_BA_SB0, 0);
++		SMAC_REG_WRITE(sh, ADR_BA_SB1, 0);
++		SMAC_REG_WRITE(sh, ADR_BA_CTRL, 0xb);
++	} else {
++		SMAC_REG_WRITE(sh, ADR_BA_CTRL, 0x0);
++	}
++}
++
++void ssv6xxx_set_ampdu_rx_add_work(struct work_struct *work)
++{
++	struct ssv_softc
++	*sc = container_of(work, struct ssv_softc, set_ampdu_rx_add_work);
++	ssv6200_hw_set_rx_ba_session(sc->sh, true, sc->ba_ra_addr, sc->ba_tid,
++				     sc->ba_ssn, 64);
++}
++
++void ssv6xxx_set_ampdu_rx_del_work(struct work_struct *work)
++{
++	struct ssv_softc *sc = container_of(work, struct ssv_softc,
++					    set_ampdu_rx_del_work);
++	u8 addr[6] = { 0 };
++	ssv6200_hw_set_rx_ba_session(sc->sh, false, addr, 0, 0, 0);
++}
++
++static void _reset_ampdu_mib(struct ssv_softc *sc,
++			     struct ssv_sta_info *sta_info, void *param)
++{
++	struct ieee80211_sta *sta = sta_info->sta;
++	struct ssv_sta_priv_data *ssv_sta_priv;
++	int i;
++	ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
++	for (i = 0; i < WMM_TID_NUM; i++) {
++		ssv_sta_priv->ampdu_tid[i].ampdu_mib_reset = 1;
++	}
++}
++
++void ssv6xxx_ampdu_mib_reset(struct ieee80211_hw *hw)
++{
++	struct ssv_softc *sc = hw->priv;
++	if (sc == NULL)
++		return;
++	ssv6xxx_foreach_sta(sc, _reset_ampdu_mib, NULL);
++}
++
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++ssize_t ampdu_tx_mib_dump(struct ssv_sta_priv_data *ssv_sta_priv,
++			  char *mib_str, ssize_t length)
++{
++	ssize_t buf_size = length;
++	ssize_t prt_size;
++	int j;
++	struct ssv_sta_info *ssv_sta = ssv_sta_priv->sta_info;
++	if (ssv_sta->sta == NULL) {
++		prt_size = snprintf(mib_str, buf_size, "\n    NULL STA.\n");
++		mib_str += prt_size;
++		buf_size -= prt_size;
++		goto mib_dump_exit;
++	}
++	for (j = 0; j < WMM_TID_NUM; j++) {
++		int k;
++		struct AMPDU_TID_st *ampdu_tid = &ssv_sta_priv->ampdu_tid[j];
++		struct AMPDU_MIB_st *ampdu_mib = &ampdu_tid->mib;
++		prt_size =
++		    snprintf(mib_str, buf_size, "\n    WMM_TID %d@%d\n", j,
++			     ampdu_tid->state);
++		mib_str += prt_size;
++		buf_size -= prt_size;
++		if (ampdu_tid->state != AMPDU_STATE_OPERATION)
++			continue;
++		prt_size =
++		    snprintf(mib_str, buf_size, "        BA window size: %d\n",
++			     ampdu_tid->ssv_baw_size);
++		mib_str += prt_size;
++		buf_size -= prt_size;
++		prt_size =
++		    snprintf(mib_str, buf_size, "        BA window head: %d\n",
++			     ampdu_tid->ssv_baw_head);
++		mib_str += prt_size;
++		buf_size -= prt_size;
++		prt_size = snprintf(mib_str, buf_size,
++				    "        Sending aggregated #: %d\n",
++				    ampdu_tid->aggr_pkt_num);
++		mib_str += prt_size;
++		buf_size -= prt_size;
++		prt_size =
++		    snprintf(mib_str, buf_size, "        Waiting #: %d\n",
++			     skb_queue_len(&ampdu_tid->ampdu_skb_tx_queue));
++		mib_str += prt_size;
++		buf_size -= prt_size;
++		prt_size =
++		    snprintf(mib_str, buf_size, "        Early aggregated %d\n",
++			     ampdu_tid->early_aggr_skb_num);
++		mib_str += prt_size;
++		buf_size -= prt_size;
++		prt_size = snprintf(mib_str, buf_size,
++				    "        MPDU: %d\n",
++				    ampdu_mib->ampdu_mib_mpdu_counter);
++		mib_str += prt_size;
++		buf_size -= prt_size;
++		prt_size = snprintf(mib_str, buf_size,
++				    "        Passed: %d\n",
++				    ampdu_mib->ampdu_mib_pass_counter);
++		mib_str += prt_size;
++		buf_size -= prt_size;
++		prt_size = snprintf(mib_str, buf_size,
++				    "        Retry: %d\n",
++				    ampdu_mib->ampdu_mib_retry_counter);
++		mib_str += prt_size;
++		buf_size -= prt_size;
++		prt_size = snprintf(mib_str, buf_size,
++				    "        AMPDU: %d\n",
++				    ampdu_mib->ampdu_mib_ampdu_counter);
++		mib_str += prt_size;
++		buf_size -= prt_size;
++		prt_size = snprintf(mib_str, buf_size,
++				    "        Retry AMPDU: %d\n",
++				    ampdu_mib->ampdu_mib_aggr_retry_counter);
++		mib_str += prt_size;
++		buf_size -= prt_size;
++		prt_size = snprintf(mib_str, buf_size,
++				    "        BAR count: %d\n",
++				    ampdu_mib->ampdu_mib_bar_counter);
++		mib_str += prt_size;
++		buf_size -= prt_size;
++		prt_size = snprintf(mib_str, buf_size,
++				    "        Discard count: %d\n",
++				    ampdu_mib->ampdu_mib_discard_counter);
++		mib_str += prt_size;
++		buf_size -= prt_size;
++		prt_size = snprintf(mib_str, buf_size,
++				    "        BA count: %d\n",
++				    ampdu_mib->ampdu_mib_BA_counter);
++		mib_str += prt_size;
++		buf_size -= prt_size;
++		prt_size =
++		    snprintf(mib_str, buf_size, "        Total BA count: %d\n",
++			     ssv_sta_priv->ampdu_mib_total_BA_counter);
++		mib_str += prt_size;
++		buf_size -= prt_size;
++		prt_size =
++		    snprintf(mib_str, buf_size, "        Aggr # count:\n");
++		mib_str += prt_size;
++		buf_size -= prt_size;
++		for (k = 0; k <= SSV_AMPDU_aggr_num_max; k++) {
++			prt_size =
++			    snprintf(mib_str, buf_size, "            %d: %d\n",
++				     k, ampdu_mib->ampdu_mib_dist[k]);
++			mib_str += prt_size;
++			buf_size -= prt_size;
++		}
++	}
++ mib_dump_exit:
++	return (length - buf_size);
++}
++
++static void _dump_ampdu_mib(struct ssv_softc *sc, struct ssv_sta_info *sta_info,
++			    void *param)
++{
++	struct mib_dump_data *dump_data = (struct mib_dump_data *)param;
++	struct ieee80211_sta *sta;
++	struct ssv_sta_priv_data *ssv_sta_priv;
++	ssize_t buf_size;
++	ssize_t prt_size;
++	char *mib_str = dump_data->prt_buff;
++	if (param == NULL)
++		return;
++	buf_size = dump_data->buff_size - 1;
++	sta = sta_info->sta;
++	if ((sta == NULL) || ((sta_info->s_flags & STA_FLAG_VALID) == 0))
++		return;
++	prt_size = snprintf(mib_str, buf_size,
++			    "STA: %02X-%02X-%02X-%02X-%02X-%02X:\n",
++			    sta->addr[0], sta->addr[1], sta->addr[2],
++			    sta->addr[3], sta->addr[4], sta->addr[5]);
++	mib_str += prt_size;
++	buf_size -= prt_size;
++	ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
++	prt_size = ampdu_tx_mib_dump(ssv_sta_priv, mib_str, buf_size);
++	mib_str += prt_size;
++	buf_size -= prt_size;
++	dump_data->prt_len = (dump_data->buff_size - 1 - buf_size);
++	dump_data->prt_buff = mib_str;
++	dump_data->buff_size = buf_size;
++}
++
++ssize_t ssv6xxx_ampdu_mib_dump(struct ieee80211_hw *hw, char *mib_str,
++			       ssize_t length)
++{
++	struct ssv_softc *sc = hw->priv;
++	ssize_t buf_size = length - 1;
++	struct mib_dump_data dump_data = { mib_str, buf_size, 0 };
++	if (sc == NULL)
++		return 0;
++	ssv6xxx_foreach_sta(sc, _dump_ampdu_mib, &dump_data);
++	return dump_data.prt_len;
++}
++#endif
++struct sk_buff *_alloc_ampdu_skb(struct ssv_softc *sc,
++				 struct AMPDU_TID_st *ampdu_tid, u32 len)
++{
++	unsigned char *payload_addr;
++	u32 headroom = sc->hw->extra_tx_headroom;
++	u32 offset;
++	u32 cur_max_ampdu_size = SSV_GET_MAX_AMPDU_SIZE(sc->sh);
++	u32 extra_room = sc->sh->tx_desc_len * 2 + 48;
++	u32 max_physical_len = (len
++				&& ((len + extra_room) < cur_max_ampdu_size))
++	    ? (len + extra_room)
++	    : cur_max_ampdu_size;
++	u32 skb_len = max_physical_len + headroom + 3;
++	struct sk_buff *ampdu_skb = __dev_alloc_skb(skb_len, GFP_KERNEL);
++	struct ampdu_hdr_st *ampdu_hdr;
++	if (ampdu_skb == NULL) {
++		dev_err(sc->dev, "AMPDU allocation of size %d(%d) failed\n",
++			len, skb_len);
++		return NULL;
++	}
++	payload_addr = ampdu_skb->data + headroom - sc->sh->tx_desc_len;
++	offset = ((size_t)payload_addr) % 4U;
++	if (offset) {
++		dev_dbg(sc->dev, "Align AMPDU data %d\n", offset);
++		skb_reserve(ampdu_skb, headroom + 4 - offset);
++	} else
++		skb_reserve(ampdu_skb, headroom);
++	ampdu_hdr = (struct ampdu_hdr_st *)ampdu_skb->head;
++	skb_queue_head_init(&ampdu_hdr->mpdu_q);
++	ampdu_hdr->max_size = max_physical_len - extra_room;
++	ampdu_hdr->size = 0;
++	ampdu_hdr->ampdu_tid = ampdu_tid;
++	memset(ampdu_hdr->ssn, 0xFF, sizeof(ampdu_hdr->ssn));
++	ampdu_hdr->mpdu_num = 0;
++	return ampdu_skb;
++}
++
++bool _is_skb_q_empty(struct ssv_softc *sc, struct sk_buff *skb)
++{
++	u32 ac = skb_get_queue_mapping(skb);
++	u32 hw_txqid = sc->tx.hw_txqid[ac];
++	return AMPDU_HCI_Q_EMPTY(sc->sh, hw_txqid);
++}
++
++static u32 _check_timeout(struct AMPDU_TID_st *ampdu_tid)
++{
++	u16 ssn, head_ssn, end_ssn;
++	unsigned long check_jiffies = jiffies;
++	u32 has_retry = 0;
++	head_ssn = ampdu_tid->ssv_baw_head;
++	ssn = head_ssn;
++	if (ssn == SSV_ILLEGAL_SN)
++		return 0;
++	end_ssn = (head_ssn + SSV_AMPDU_BA_WINDOW_SIZE) % SSV_AMPDU_MAX_SSN;
++	do {
++		struct sk_buff *skb = INDEX_PKT_BY_SSN(ampdu_tid, ssn);
++		struct SKB_info_st *skb_info;
++		unsigned long cur_jiffies;
++		unsigned long timeout_jiffies;
++		u32 delta_ms;
++		if (skb == NULL)
++			break;
++		skb_info = (SKB_info *) (skb->head);
++		cur_jiffies = jiffies;
++		timeout_jiffies =
++		    skb_info->aggr_timestamp +
++		    msecs_to_jiffies(BA_WAIT_TIMEOUT);
++		if ((skb_info->ampdu_tx_status != AMPDU_ST_SENT)
++		    || time_before(cur_jiffies, timeout_jiffies))
++			break;
++		delta_ms =
++		    jiffies_to_msecs(cur_jiffies - skb_info->aggr_timestamp);
++		prn_aggr_err("rt S%d-T%d-%d (%u)\n",
++			     ((struct ssv_sta_priv_data *)skb_info->sta->
++			      drv_priv)->sta_idx, ampdu_tid->tidno, ssn,
++			     delta_ms);
++		if (delta_ms > 1000) {
++			prn_aggr_err("Last checktime %lu - %lu = %u\n",
++				     check_jiffies, ampdu_tid->timestamp,
++				     jiffies_to_msecs(check_jiffies -
++						      ampdu_tid->timestamp));
++		}
++		has_retry += _mark_skb_retry(skb_info, skb);
++		INC_PKT_SN(ssn);
++	} while (ssn != end_ssn);
++	ampdu_tid->timestamp = check_jiffies;
++	return has_retry;
++}
++
++void ssv6xxx_ampdu_check_timeout(struct ieee80211_hw *hw)
++{
++	struct ssv_softc *sc = hw->priv;
++	struct AMPDU_TID_st *cur_AMPDU_TID;
++	if (!list_empty(&sc->tx.ampdu_tx_que)) {
++		list_for_each_entry_rcu(cur_AMPDU_TID, &sc->tx.ampdu_tx_que,
++					list) {
++			u32 has_retry;
++			if (cur_AMPDU_TID->state != AMPDU_STATE_OPERATION)
++				continue;
++			has_retry = _check_timeout(cur_AMPDU_TID);
++			if (has_retry) {
++				_collect_retry_frames(cur_AMPDU_TID);
++				ssv6200_ampdu_send_retry(sc->hw, cur_AMPDU_TID,
++							 &cur_AMPDU_TID->
++							 retry_queue, true);
++			}
++		}
++	}
++}
++
++void ssv6xxx_ampdu_sent(struct ieee80211_hw *hw, struct sk_buff *ampdu)
++{
++	struct ssv_softc *sc = hw->priv;
++	struct ampdu_hdr_st *ampdu_hdr = (struct ampdu_hdr_st *)ampdu->head;
++	struct sk_buff *mpdu;
++	unsigned long cur_jiffies = jiffies;
++	int i;
++	SKB_info *mpdu_skb_info;
++	u16 ssn;
++	if (ampdu_hdr->ampdu_tid->state != AMPDU_STATE_OPERATION)
++		return;
++	spin_lock_bh(&ampdu_hdr->ampdu_tid->pkt_array_lock);
++	for (i = 0; i < ampdu_hdr->mpdu_num; i++) {
++		ssn = ampdu_hdr->ssn[i];
++		mpdu = INDEX_PKT_BY_SSN(ampdu_hdr->ampdu_tid, ssn);
++		if (mpdu == NULL) {
++			dev_err(sc->dev, "T%d-%d is a NULL MPDU.\n",
++				ampdu_hdr->ampdu_tid->tidno, ssn);
++			continue;
++		}
++		if (ampdu_skb_ssn(mpdu) != ssn) {
++			dev_err(sc->dev, "T%d-%d does not match %d MPDU.\n",
++				ampdu_hdr->ampdu_tid->tidno, ssn,
++				ampdu_skb_ssn(mpdu));
++			continue;
++		}
++		mpdu_skb_info = (SKB_info *) (mpdu->head);
++		mpdu_skb_info->aggr_timestamp = cur_jiffies;
++		mpdu_skb_info->ampdu_tx_status = AMPDU_ST_SENT;
++	}
++	spin_unlock_bh(&ampdu_hdr->ampdu_tid->pkt_array_lock);
++}
+diff --git a/drivers/net/wireless/ssv6051/smac/ampdu.h b/drivers/net/wireless/ssv6051/smac/ampdu.h
+new file mode 100644
+index 000000000000..faa61c4f9297
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/ampdu.h
+@@ -0,0 +1,215 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation, either version 3 of the License, or
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _AMPDU_H_
++#define _AMPDU_H_
++#include <linux/version.h>
++#include <ssv6200_common.h>
++#define Enable_ampdu_debug_log (0)
++#define Enable_AMPDU_Live_Time (0)
++#define Enable_HW_AUTO_CRC_32 (1)
++#define Enable_AMPDU_Rx (1)
++#define Enable_AMPDU_Tx (1)
++#define Enable_AMPDU_FW_Retry (1)
++#define Enable_AMPDU_delay_work (1)
++#define USE_FLUSH_RETRY
++#define USE_AMPDU_TX_STATUS_ARRAY
++#define SSV_AMPDU_FLOW_CONTROL
++#define AMPDU_CHECK_SKB_SEQNO
++#define REPORT_TX_STATUS_DIRECTLY
++#define SSV_AMPDU_aggr_num_max MAX_AGGR_NUM
++#define SSV_AMPDU_seq_num_max (4096)
++#define SSV_AMPDU_retry_counter_max (3)
++#define SSV_AMPDU_tx_group_id_max (64)
++#define SSV_AMPDU_MAX_SSN (4096)
++#define SSV_AMPDU_BA_WINDOW_SIZE (64)
++#define SSV_AMPDU_WINDOW_SIZE (64)
++#define SSV_GET_MAX_AMPDU_SIZE(sh) (((sh)->tx_page_available/(sh)->ampdu_divider) << HW_MMU_PAGE_SHIFT)
++#define SSV_AMPDU_FLOW_CONTROL_UPPER_BOUND (64)
++#define SSV_AMPDU_FLOW_CONTROL_LOWER_BOUND (48)
++#define SSV_AMPDU_timer_period (50)
++#define SSV_AMPDU_TX_TIME_THRESHOLD (50)
++#define SSV_AMPDU_MPDU_LIVE_TIME (SSV_AMPDU_retry_counter_max*8)
++#define SSV_AMPDU_BA_TIME (50)
++#define SSV_ILLEGAL_SN (0xffff)
++#define AMPDU_BUFFER_SIZE (32*1024)
++#define AMPDU_SIGNATURE (0x4E)
++#define AMPDU_DELIMITER_LEN (4)
++#define AMPDU_FCS_LEN (4)
++#define AMPDU_RESERVED_LEN (3)
++#define AMPDU_TX_NAV_MCS_567 (48)
++#define SSV_SEQ_NUM_SHIFT (4)
++#define SSV_RETRY_BIT_SHIFT (11)
++#define IEEE80211_SEQ_SEQ_SHIFT (4)
++#define IEEE80211_AMPDU_BA_LEN (34)
++#define SSV6200_AMPDU_TRIGGER_INDEX 0
++#define SSV_SN_STATUS_Release (0xaa)
++#define SSV_SN_STATUS_Retry (0xbb)
++#define SSV_SN_STATUS_Wait_BA (0xcc)
++#define SSV_SN_STATUS_Discard (0xdd)
++#define AMPDU_HCI_SEND_TAIL_WITH_FLOWCTRL (0)
++#define AMPDU_HCI_SEND_HEAD_WITH_FLOWCTRL (1)
++#define AMPDU_HCI_SEND_TAIL_WITHOUT_FLOWCTRL (2)
++#define AMPDU_HCI_SEND_HEAD_WITHOUT_FLOWCTRL (3)
++#define SSV_BAR_CTRL_ACK_POLICY_NORMAL (0x0000)
++#define SSV_BAR_CTRL_CBMTID_COMPRESSED_BA (0x0004)
++#define SSV_BAR_CTRL_TID_INFO_SHIFT (12)
++#define AMPDU_STATE_START BIT(0)
++#define AMPDU_STATE_OPERATION BIT(1)
++#define AMPDU_STATE_STOP BIT(2)
++typedef enum {
++	AMPDU_REKEY_PAUSE_STOP = 0,
++	AMPDU_REKEY_PAUSE_START,
++	AMPDU_REKEY_PAUSE_ONGOING,
++	AMPDU_REKEY_PAUSE_DEFER,
++	AMPDU_REKEY_PAUSE_HWKEY_SYNC,
++} AMPDU_REKEY_PAUSE_STATE;
++#define SSV_a_minus_b_in_c(a,b,c) (((a)>=(b))?((a)-(b)):((c)-(b)+(a)))
++#define SSV_AMPDU_SN_a_minus_b(a,b) (SSV_a_minus_b_in_c((a), (b), SSV_AMPDU_seq_num_max))
++#define AMPDU_HCI_SEND(_sh,_sk,_q,_flag) (_sh)->hci.hci_ops->hci_tx((_sk), (_q), (_flag))
++#define AMPDU_HCI_Q_EMPTY(_sh,_q) (_sh)->hci.hci_ops->hci_txq_empty((_q))
++struct ampdu_hdr_st {
++	u32 first_sn;
++	struct sk_buff_head mpdu_q;
++	u32 max_size;
++	u32 size;
++	struct AMPDU_TID_st *ampdu_tid;
++	u16 ssn[MAX_AGGR_NUM];
++	u16 mpdu_num;
++	struct fw_rc_retry_params rates[SSV62XX_TX_MAX_RATES];
++	struct ieee80211_sta *sta;
++};
++enum AMPDU_TX_STATUS_E {
++	AMPDU_ST_NON_AMPDU,
++	AMPDU_ST_AGGREGATED,
++	AMPDU_ST_SENT,
++	AMPDU_ST_RETRY,
++	AMPDU_ST_DROPPED,
++	AMPDU_ST_DONE,
++};
++typedef struct AMPDU_MIB_st {
++	u32 ampdu_mib_mpdu_counter;
++	u32 ampdu_mib_retry_counter;
++	u32 ampdu_mib_ampdu_counter;
++	u32 ampdu_mib_aggr_retry_counter;
++	u32 ampdu_mib_bar_counter;
++	u32 ampdu_mib_discard_counter;
++	u32 ampdu_mib_total_BA_counter;
++	u32 ampdu_mib_BA_counter;
++	u32 ampdu_mib_pass_counter;
++	u32 ampdu_mib_dist[SSV_AMPDU_aggr_num_max + 1];
++} AMPDU_MIB;
++typedef struct AMPDU_TID_st {
++	struct list_head list;
++	volatile unsigned long timestamp;
++	u32 tidno;
++	u16 ac;
++	struct ieee80211_sta *sta;
++	u16 ssv_baw_size;
++	u8 agg_num_max;
++	u8 state;
++#ifdef AMPDU_CHECK_SKB_SEQNO
++	u32 last_seqno;
++#endif
++	struct sk_buff_head ampdu_skb_tx_queue;
++	spinlock_t ampdu_skb_tx_queue_lock;
++	struct sk_buff_head retry_queue;
++	struct sk_buff_head release_queue;
++	struct sk_buff *aggr_pkts[SSV_AMPDU_BA_WINDOW_SIZE];
++	volatile u32 aggr_pkt_num;
++	volatile u16 ssv_baw_head;
++	spinlock_t pkt_array_lock;
++	struct sk_buff *cur_ampdu_pkt;
++	struct sk_buff_head early_aggr_ampdu_q;
++	u32 early_aggr_skb_num;
++	struct sk_buff_head ampdu_skb_wait_encry_queue;
++	u32 ampdu_mib_reset;
++	struct AMPDU_MIB_st mib;
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	struct dentry *debugfs_dir;
++	struct sk_buff_head ba_q;
++#endif
++} AMPDU_TID, *p_AMPDU_TID;
++typedef struct AMPDU_DELIMITER_st {
++	u16 reserved:4;
++	u16 length:12;
++	u8 crc;
++	u8 signature;
++} AMPDU_DELIMITER, *p_AMPDU_DELIMITER;
++typedef struct AMPDU_BLOCKACK_st {
++	u16 frame_control;
++	u16 duration;
++	u8 ra_addr[ETH_ALEN];
++	u8 ta_addr[ETH_ALEN];
++	u16 BA_ack_ploicy:1;
++	u16 multi_tid:1;
++	u16 compress_bitmap:1;
++	u16 reserved:9;
++	u16 tid_info:4;
++	u16 BA_fragment_sn:4;
++	u16 BA_ssn:12;
++	u32 BA_sn_bit_map[2];
++} AMPDU_BLOCKACK, *p_AMPDU_BLOCKACK;
++struct ssv_bar {
++	unsigned short frame_control;
++	unsigned short duration;
++	unsigned char ra[6];
++	unsigned char ta[6];
++	unsigned short control;
++	unsigned short start_seq_num;
++} __packed;
++#if Enable_ampdu_debug_log
++#define ampdu_db_log(format, args...) printk("~~~ampdu [%s:%d] "format, __FUNCTION__, __LINE__, ##args)
++#define ampdu_db_log_simple(format, args...) printk(format, ##args)
++#else
++#define ampdu_db_log(...) do {} while (0)
++#define ampdu_db_log_simple(...) do {} while (0)
++#endif
++#if Enable_AMPDU_delay_work
++void ssv6200_ampdu_delayed_work_callback_func(struct work_struct *work);
++#else
++void ssv6200_ampdu_timer_callback_func(unsigned long data);
++#endif
++void ssv6200_ampdu_init(struct ieee80211_hw *hw);
++void ssv6200_ampdu_deinit(struct ieee80211_hw *hw);
++void ssv6200_ampdu_release_skb(struct sk_buff *skb, struct ieee80211_hw *hw);
++void ssv6200_ampdu_tx_start(u16 tid, struct ieee80211_sta *sta,
++			    struct ieee80211_hw *hw, u16 * ssn);
++void ssv6200_ampdu_tx_operation(u16 tid, struct ieee80211_sta *sta,
++				struct ieee80211_hw *hw, u8 buffer_size);
++void ssv6200_ampdu_tx_stop(u16 tid, struct ieee80211_sta *sta,
++			   struct ieee80211_hw *hw);
++bool ssv6200_ampdu_tx_handler(struct ieee80211_hw *hw, struct sk_buff *skb);
++u32 ssv6xxx_ampdu_flush(struct ieee80211_hw *hw);
++void ssv6200_ampdu_timeout_tx(struct ieee80211_hw *hw);
++struct cfg_host_event;
++void ssv6200_ampdu_no_BA_handler(struct ieee80211_hw *hw, struct sk_buff *skb);
++void ssv6200_ampdu_BA_handler(struct ieee80211_hw *hw, struct sk_buff *skb);
++void ssv6200_ampdu_tx_update_state(void *priv, struct ieee80211_sta *sta,
++				   struct sk_buff *skb);
++void ssv6200_ampdu_tx_add_sta(struct ieee80211_hw *hw,
++			      struct ieee80211_sta *sta);
++void ssv6xxx_ampdu_postprocess_BA(struct ieee80211_hw *hw);
++void ssv6xxx_ampdu_check_timeout(struct ieee80211_hw *hw);
++void ssv6xxx_ampdu_sent(struct ieee80211_hw *hw, struct sk_buff *ampdu);
++extern void ssv6xxx_set_ampdu_rx_add_work(struct work_struct *work);
++extern void ssv6xxx_set_ampdu_rx_del_work(struct work_struct *work);
++void ssv6xxx_mib_reset(struct ieee80211_hw *hw);
++ssize_t ssv6xxx_mib_dump(struct ieee80211_hw *hw, char *mib_str,
++			 ssize_t length);
++void encry_work(struct work_struct *work);
++void sync_hw_key_work(struct work_struct *work);
++#endif
+diff --git a/drivers/net/wireless/ssv6051/smac/ap.c b/drivers/net/wireless/ssv6051/smac/ap.c
+new file mode 100644
+index 000000000000..0f2ba6a31a05
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/ap.c
+@@ -0,0 +1,598 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation, either version 3 of the License, or
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <ssv6200.h>
++#include <linux/nl80211.h>
++#include <linux/etherdevice.h>
++#include <linux/delay.h>
++#include <linux/version.h>
++#include <linux/time.h>
++#include <linux/sched.h>
++#include <net/mac80211.h>
++#include <ssv6200.h>
++#include "lib.h"
++#include "dev.h"
++#include "ap.h"
++#include "ssv_rc_common.h"
++#include "ssv_rc.h"
++int ssv6200_bcast_queue_len(struct ssv6xxx_bcast_txq *bcast_txq);
++#define IS_EQUAL(a,b) ( (a) == (b) )
++#define SET_BIT(v,b) ( (v) |= (0x01<<b) )
++#define CLEAR_BIT(v,b) ( (v) &= ~(0x01<<b) )
++#define IS_BIT_SET(v,b) ( (v) & (0x01<<(b) ) )
++#define PBUF_BASE_ADDR 0x80000000
++#define PBUF_ADDR_SHIFT 16
++#define PBUF_MapPkttoID(_PKT) (((u32)_PKT&0x0FFF0000)>>PBUF_ADDR_SHIFT)
++#define PBUF_MapIDtoPkt(_ID) (PBUF_BASE_ADDR|((_ID)<<PBUF_ADDR_SHIFT))
++#define SSV6xxx_BEACON_MAX_ALLOCATE_CNT 10
++#define MTX_BCN_PKTID_CH_LOCK_SHIFT MTX_BCN_PKTID_CH_LOCK_SFT
++#define MTX_BCN_CFG_VLD_SHIFT MTX_BCN_CFG_VLD_SFT
++#define MTX_BCN_CFG_VLD_MASK MTX_BCN_CFG_VLD_MSK
++#define AUTO_BCN_ONGOING_MASK MTX_AUTO_BCN_ONGOING_MSK
++#define AUTO_BCN_ONGOING_SHIFT MTX_AUTO_BCN_ONGOING_SFT
++#define MTX_BCN_TIMER_EN_SHIFT MTX_BCN_TIMER_EN_SFT
++#define MTX_TSF_TIMER_EN_SHIFT MTX_TSF_TIMER_EN_SFT
++#define MTX_HALT_MNG_UNTIL_DTIM_SHIFT MTX_HALT_MNG_UNTIL_DTIM_SFT
++#define MTX_BCN_ENABLE_MASK (MTX_BCN_TIMER_EN_I_MSK)
++#define MTX_BCN_PERIOD_SHIFT MTX_BCN_PERIOD_SFT
++#define MTX_DTIM_NUM_SHIFT MTX_DTIM_NUM_SFT
++#define MTX_DTIM_OFST0 MTX_DTIM_OFST0_SFT
++enum ssv6xxx_beacon_type {
++	SSV6xxx_BEACON_0,
++	SSV6xxx_BEACON_1,
++};
++static const u32 ssv6xxx_beacon_adr[] = {
++	ADR_MTX_BCN_CFG0,
++	ADR_MTX_BCN_CFG1,
++};
++
++void ssv6xxx_beacon_reg_lock(struct ssv_softc *sc, bool block)
++{
++	u32 val;
++	val = block << MTX_BCN_PKTID_CH_LOCK_SHIFT;
++#ifdef BEACON_DEBUG
++	printk("ssv6xxx_beacon_reg_lock   val[0x:%08x]\n ", val);
++#endif
++	SMAC_REG_WRITE(sc->sh, ADR_MTX_BCN_MISC, val);
++}
++
++void ssv6xxx_beacon_set_info(struct ssv_softc *sc, u8 beacon_interval,
++			     u8 dtim_cnt)
++{
++	u32 val;
++	if (beacon_interval == 0)
++		beacon_interval = 100;
++#ifdef BEACON_DEBUG
++	printk("[A] BSS_CHANGED_BEACON_INT beacon_int[%d] dtim_cnt[%d]\n",
++	       beacon_interval, (dtim_cnt));
++#endif
++	val =
++	    (beacon_interval << MTX_BCN_PERIOD_SHIFT) | (dtim_cnt <<
++							 MTX_DTIM_NUM_SHIFT);
++	SMAC_REG_WRITE(sc->sh, ADR_MTX_BCN_PRD, val);
++}
++
++bool ssv6xxx_beacon_enable(struct ssv_softc *sc, bool bEnable)
++{
++	u32 regval = 0;
++	int ret = 0;
++	if (bEnable && !sc->beacon_usage) {
++		printk
++		    ("[A] Reject to set beacon!!!.        ssv6xxx_beacon_enable bEnable[%d] sc->beacon_usage[%d]\n",
++		     bEnable, sc->beacon_usage);
++		sc->enable_beacon = BEACON_WAITING_ENABLED;
++		return 0;
++	}
++	if ((bEnable && (BEACON_ENABLED & sc->enable_beacon)) ||
++	    (!bEnable && !sc->enable_beacon)) {
++		printk
++		    ("[A] ssv6xxx_beacon_enable bEnable[%d] and sc->enable_beacon[%d] are the same. no need to execute.\n",
++		     bEnable, sc->enable_beacon);
++		if (bEnable) {
++			printk("        Ignore enable beacon cmd!!!!\n");
++			return 0;
++		}
++	}
++	SMAC_REG_READ(sc->sh, ADR_MTX_BCN_EN_MISC, &regval);
++#ifdef BEACON_DEBUG
++	printk("[A] ssv6xxx_beacon_enable read misc reg val [%08x]\n", regval);
++#endif
++	regval &= MTX_BCN_ENABLE_MASK;
++#ifdef BEACON_DEBUG
++	printk("[A] ssv6xxx_beacon_enable read misc reg val [%08x]\n", regval);
++#endif
++	regval |= (bEnable << MTX_BCN_TIMER_EN_SHIFT);
++	ret = SMAC_REG_WRITE(sc->sh, ADR_MTX_BCN_EN_MISC, regval);
++#ifdef BEACON_DEBUG
++	printk("[A] ssv6xxx_beacon_enable read misc reg val [%08x]\n", regval);
++#endif
++	sc->enable_beacon = (bEnable == true) ? BEACON_ENABLED : 0;
++	return ret;
++}
++
++int ssv6xxx_beacon_fill_content(struct ssv_softc *sc, u32 regaddr, u8 * beacon,
++				int size)
++{
++	u32 i, val;
++	u32 *ptr = (u32 *) beacon;
++	size = size / 4;
++	for (i = 0; i < size; i++) {
++		val = (u32) (*(ptr + i));
++#ifdef BEACON_DEBUG
++		printk("[%08x] ", val);
++#endif
++		SMAC_REG_WRITE(sc->sh, regaddr + i * 4, val);
++	}
++#ifdef BEACON_DEBUG
++	printk("\n");
++#endif
++	return 0;
++}
++
++void ssv6xxx_beacon_fill_tx_desc(struct ssv_softc *sc,
++				 struct sk_buff *beacon_skb)
++{
++	struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(beacon_skb);
++	struct ssv6200_tx_desc *tx_desc;
++	u16 pb_offset = TXPB_OFFSET;
++	struct ssv_rate_info ssv_rate;
++	skb_push(beacon_skb, pb_offset);
++	tx_desc = (struct ssv6200_tx_desc *)beacon_skb->data;
++	memset(tx_desc, 0, pb_offset);
++	ssv6xxx_rc_hw_rate_idx(sc, tx_info, &ssv_rate);
++	tx_desc->len = beacon_skb->len - pb_offset;
++	tx_desc->c_type = M2_TXREQ;
++	tx_desc->f80211 = 1;
++	tx_desc->ack_policy = 1;
++	tx_desc->hdr_offset = pb_offset;
++	tx_desc->hdr_len = 24;
++	tx_desc->payload_offset = tx_desc->hdr_offset + tx_desc->hdr_len;
++	tx_desc->crate_idx = ssv_rate.crate_hw_idx;
++	tx_desc->drate_idx = ssv_rate.drate_hw_idx;
++	skb_put(beacon_skb, 4);
++}
++
++inline enum ssv6xxx_beacon_type ssv6xxx_beacon_get_valid_reg(struct ssv_softc
++							     *sc)
++{
++	u32 regval = 0;
++	SMAC_REG_READ(sc->sh, ADR_MTX_BCN_MISC, &regval);
++	regval &= MTX_BCN_CFG_VLD_MASK;
++	regval = regval >> MTX_BCN_CFG_VLD_SHIFT;
++	if (regval == 0x2 || regval == 0x0)
++		return SSV6xxx_BEACON_0;
++	else if (regval == 0x1)
++		return SSV6xxx_BEACON_1;
++	else
++		printk("=============>ERROR!!drv_bcn_reg_available\n");
++	return SSV6xxx_BEACON_0;
++}
++
++bool ssv6xxx_beacon_set(struct ssv_softc *sc, struct sk_buff *beacon_skb,
++			int dtim_offset)
++{
++	u32 reg_tx_beacon_adr = ADR_MTX_BCN_CFG0;
++	enum ssv6xxx_beacon_type avl_bcn_type = SSV6xxx_BEACON_0;
++	bool ret = true;
++	int val;
++	ssv6xxx_beacon_reg_lock(sc, 1);
++	avl_bcn_type = ssv6xxx_beacon_get_valid_reg(sc);
++	if (avl_bcn_type == SSV6xxx_BEACON_1)
++		reg_tx_beacon_adr = ADR_MTX_BCN_CFG1;
++#ifdef BEACON_DEBUG
++	printk("[A] ssv6xxx_beacon_set avl_bcn_type[%d]\n", avl_bcn_type);
++#endif
++	do {
++		if (IS_BIT_SET(sc->beacon_usage, avl_bcn_type)) {
++#ifdef BEACON_DEBUG
++			printk
++			    ("[A] beacon has already been set old len[%d] new len[%d]\n",
++			     sc->beacon_info[avl_bcn_type].len,
++			     beacon_skb->len);
++#endif
++			if (sc->beacon_info[avl_bcn_type].len >=
++			    beacon_skb->len) {
++				break;
++			} else {
++				if (false ==
++				    ssv6xxx_pbuf_free(sc,
++						      sc->
++						      beacon_info[avl_bcn_type].
++						      pubf_addr)) {
++#ifdef BEACON_DEBUG
++					printk
++					    ("=============>ERROR!!Intend to allcoate beacon from ASIC fail.\n");
++#endif
++					ret = false;
++					goto out;
++				}
++				CLEAR_BIT(sc->beacon_usage, avl_bcn_type);
++			}
++		}
++		sc->beacon_info[avl_bcn_type].pubf_addr =
++		    ssv6xxx_pbuf_alloc(sc, beacon_skb->len, TX_BUF);
++		sc->beacon_info[avl_bcn_type].len = beacon_skb->len;
++		if (sc->beacon_info[avl_bcn_type].pubf_addr == 0) {
++			ret = false;
++			goto out;
++		}
++		SET_BIT(sc->beacon_usage, avl_bcn_type);
++#ifdef BEACON_DEBUG
++		printk
++		    ("[A] beacon type[%d] usage[%d] allocate new beacon addr[%08x] \n",
++		     avl_bcn_type, sc->beacon_usage,
++		     sc->beacon_info[avl_bcn_type].pubf_addr);
++#endif
++	} while (0);
++	ssv6xxx_beacon_fill_content(sc, sc->beacon_info[avl_bcn_type].pubf_addr,
++				    beacon_skb->data, beacon_skb->len);
++	val =
++	    (PBUF_MapPkttoID(sc->beacon_info[avl_bcn_type].pubf_addr)) |
++	    (dtim_offset << MTX_DTIM_OFST0);
++	SMAC_REG_WRITE(sc->sh, reg_tx_beacon_adr, val);
++#ifdef BEACON_DEBUG
++	printk("[A] update to register reg_tx_beacon_adr[%08x] val[%08x]\n",
++	       reg_tx_beacon_adr, val);
++#endif
++ out:
++	ssv6xxx_beacon_reg_lock(sc, 0);
++	if (sc->beacon_usage && (sc->enable_beacon & BEACON_WAITING_ENABLED)) {
++		printk("[A] enable beacon for BEACON_WAITING_ENABLED flags\n");
++		ssv6xxx_beacon_enable(sc, true);
++	}
++	return ret;
++}
++
++inline bool ssv6xxx_auto_bcn_ongoing(struct ssv_softc *sc)
++{
++	u32 regval;
++	SMAC_REG_READ(sc->sh, ADR_MTX_BCN_MISC, &regval);
++	return ((AUTO_BCN_ONGOING_MASK & regval) >> AUTO_BCN_ONGOING_SHIFT);
++}
++
++void ssv6xxx_beacon_release(struct ssv_softc *sc)
++{
++	int cnt = 10;
++	printk("[A] ssv6xxx_beacon_release Enter\n");
++	cancel_work_sync(&sc->set_tim_work);
++	do {
++		if (ssv6xxx_auto_bcn_ongoing(sc))
++			ssv6xxx_beacon_enable(sc, false);
++		else
++			break;
++		cnt--;
++		if (cnt <= 0)
++			break;
++	} while (1);
++	if (IS_BIT_SET(sc->beacon_usage, SSV6xxx_BEACON_0)) {
++		ssv6xxx_pbuf_free(sc,
++				  sc->beacon_info[SSV6xxx_BEACON_0].pubf_addr);
++		CLEAR_BIT(sc->beacon_usage, SSV6xxx_BEACON_0);
++	}
++	if (IS_BIT_SET(sc->beacon_usage, SSV6xxx_BEACON_1)) {
++		ssv6xxx_pbuf_free(sc,
++				  sc->beacon_info[SSV6xxx_BEACON_1].pubf_addr);
++		CLEAR_BIT(sc->beacon_usage, SSV6xxx_BEACON_1);
++	}
++	sc->enable_beacon = 0;
++	if (sc->beacon_buf) {
++		dev_kfree_skb_any(sc->beacon_buf);
++		sc->beacon_buf = NULL;
++	}
++#ifdef BEACON_DEBUG
++	printk("[A] ssv6xxx_beacon_release leave\n");
++#endif
++}
++
++void ssv6xxx_beacon_change(struct ssv_softc *sc, struct ieee80211_hw *hw,
++			   struct ieee80211_vif *vif, bool aid0_bit_set)
++{
++	struct sk_buff *skb;
++	struct sk_buff *old_skb = NULL;
++	u16 tim_offset, tim_length;
++	if (sc == NULL || hw == NULL || vif == NULL) {
++		printk("[Error]........ssv6xxx_beacon_change input error\n");
++		return;
++	}
++	do {
++		skb = ieee80211_beacon_get_tim(hw, vif,
++					       &tim_offset, &tim_length, 0);
++		if (skb == NULL) {
++			printk("[Error]........skb is NULL\n");
++			break;
++		}
++		if (tim_offset && tim_length >= 6) {
++			skb->data[tim_offset + 2] = 0;
++			if (aid0_bit_set)
++				skb->data[tim_offset + 4] |= 1;
++			else
++				skb->data[tim_offset + 4] &= ~1;
++		}
++#ifdef BEACON_DEBUG
++		printk("[A] beacon len [%d] tim_offset[%d]\n", skb->len,
++		       tim_offset);
++#endif
++		ssv6xxx_beacon_fill_tx_desc(sc, skb);
++#ifdef BEACON_DEBUG
++		printk("[A] beacon len [%d] tim_offset[%d]\n", skb->len,
++		       tim_offset);
++#endif
++		if (sc->beacon_buf) {
++			if (memcmp
++			    (sc->beacon_buf->data, skb->data,
++			     (skb->len - FCS_LEN)) == 0) {
++				old_skb = skb;
++				break;
++			} else {
++				old_skb = sc->beacon_buf;
++				sc->beacon_buf = skb;
++			}
++		} else {
++			sc->beacon_buf = skb;
++		}
++		tim_offset += 2;
++		if (ssv6xxx_beacon_set(sc, skb, tim_offset)) {
++			u8 dtim_cnt = vif->bss_conf.dtim_period - 1;
++			if (sc->beacon_dtim_cnt != dtim_cnt) {
++				sc->beacon_dtim_cnt = dtim_cnt;
++#ifdef BEACON_DEBUG
++				printk("[A] beacon_dtim_cnt [%d]\n",
++				       sc->beacon_dtim_cnt);
++#endif
++				ssv6xxx_beacon_set_info(sc, sc->beacon_interval,
++							sc->beacon_dtim_cnt);
++			}
++		}
++	} while (0);
++	if (old_skb)
++		dev_kfree_skb_any(old_skb);
++}
++
++void ssv6200_set_tim_work(struct work_struct *work)
++{
++	struct ssv_softc *sc =
++	    container_of(work, struct ssv_softc, set_tim_work);
++#ifdef BROADCAST_DEBUG
++	printk("%s() enter\n", __FUNCTION__);
++#endif
++	ssv6xxx_beacon_change(sc, sc->hw, sc->ap_vif, sc->aid0_bit_set);
++#ifdef BROADCAST_DEBUG
++	printk("%s() leave\n", __FUNCTION__);
++#endif
++}
++
++int ssv6200_bcast_queue_len(struct ssv6xxx_bcast_txq *bcast_txq)
++{
++	u32 len;
++	unsigned long flags;
++	spin_lock_irqsave(&bcast_txq->txq_lock, flags);
++	len = bcast_txq->cur_qsize;
++	spin_unlock_irqrestore(&bcast_txq->txq_lock, flags);
++	return len;
++}
++
++struct sk_buff *ssv6200_bcast_dequeue(struct ssv6xxx_bcast_txq *bcast_txq,
++				      u8 * remain_len)
++{
++	struct sk_buff *skb = NULL;
++	unsigned long flags;
++	spin_lock_irqsave(&bcast_txq->txq_lock, flags);
++	if (bcast_txq->cur_qsize) {
++		bcast_txq->cur_qsize--;
++		if (remain_len)
++			*remain_len = bcast_txq->cur_qsize;
++		skb = __skb_dequeue(&bcast_txq->qhead);
++	}
++	spin_unlock_irqrestore(&bcast_txq->txq_lock, flags);
++	return skb;
++}
++
++int ssv6200_bcast_enqueue(struct ssv_softc *sc,
++			  struct ssv6xxx_bcast_txq *bcast_txq,
++			  struct sk_buff *skb)
++{
++	unsigned long flags;
++	spin_lock_irqsave(&bcast_txq->txq_lock, flags);
++	if (bcast_txq->cur_qsize >= SSV6200_MAX_BCAST_QUEUE_LEN) {
++		struct sk_buff *old_skb;
++		old_skb = __skb_dequeue(&bcast_txq->qhead);
++		bcast_txq->cur_qsize--;
++		ssv6xxx_txbuf_free_skb(old_skb, (void *)sc);
++		printk("[B] ssv6200_bcast_enqueue - remove oldest queue\n");
++	}
++	__skb_queue_tail(&bcast_txq->qhead, skb);
++	bcast_txq->cur_qsize++;
++	spin_unlock_irqrestore(&bcast_txq->txq_lock, flags);
++	return bcast_txq->cur_qsize;
++}
++
++void ssv6200_bcast_flush(struct ssv_softc *sc,
++			 struct ssv6xxx_bcast_txq *bcast_txq)
++{
++	struct sk_buff *skb;
++	unsigned long flags;
++#ifdef BCAST_DEBUG
++	printk("ssv6200_bcast_flush\n");
++#endif
++	spin_lock_irqsave(&bcast_txq->txq_lock, flags);
++	while (bcast_txq->cur_qsize > 0) {
++		skb = __skb_dequeue(&bcast_txq->qhead);
++		bcast_txq->cur_qsize--;
++		ssv6xxx_txbuf_free_skb(skb, (void *)sc);
++	}
++	spin_unlock_irqrestore(&bcast_txq->txq_lock, flags);
++}
++
++static int queue_block_cnt = 0;
++void ssv6200_bcast_tx_work(struct work_struct *work)
++{
++	struct ssv_softc *sc =
++	    container_of(work, struct ssv_softc, bcast_tx_work.work);
++	struct sk_buff *skb;
++	int i;
++	u8 remain_size;
++	unsigned long flags;
++	bool needtimer = true;
++	long tmo = sc->bcast_interval;
++	spin_lock_irqsave(&sc->ps_state_lock, flags);
++	do {
++#ifdef BCAST_DEBUG
++		printk
++		    ("[B] bcast_timer: hw_mng_used[%d] HCI_TXQ_EMPTY[%d] bcast_queue_len[%d].....................\n",
++		     sc->hw_mng_used, HCI_TXQ_EMPTY(sc->sh, 4),
++		     ssv6200_bcast_queue_len(&sc->bcast_txq));
++#endif
++		if (sc->hw_mng_used != 0 || false == HCI_TXQ_EMPTY(sc->sh, 4)) {
++#ifdef BCAST_DEBUG
++			printk
++			    ("HW queue still have frames insdide. skip this one hw_mng_used[%d] bEmptyTXQ4[%d]\n",
++			     sc->hw_mng_used, HCI_TXQ_EMPTY(sc->sh, 4));
++#endif
++			queue_block_cnt++;
++			if (queue_block_cnt > 5) {
++				queue_block_cnt = 0;
++				ssv6200_bcast_flush(sc, &sc->bcast_txq);
++				needtimer = false;
++			}
++			break;
++		}
++		queue_block_cnt = 0;
++		for (i = 0; i < SSV6200_ID_MANAGER_QUEUE; i++) {
++			skb =
++			    ssv6200_bcast_dequeue(&sc->bcast_txq, &remain_size);
++			if (!skb) {
++				needtimer = false;
++				break;
++			}
++			if ((0 != remain_size) &&
++			    (SSV6200_ID_MANAGER_QUEUE - 1) != i) {
++				struct ieee80211_hdr *hdr;
++				struct ssv6200_tx_desc *tx_desc =
++				    (struct ssv6200_tx_desc *)skb->data;
++				hdr =
++				    (struct ieee80211_hdr *)((u8 *) tx_desc +
++							     tx_desc->
++							     hdr_offset);
++				hdr->frame_control |=
++				    cpu_to_le16(IEEE80211_FCTL_MOREDATA);
++			}
++#ifdef BCAST_DEBUG
++			printk("[B] bcast_timer:tx remain_size[%d] i[%d]\n",
++			       remain_size, i);
++#endif
++			spin_unlock_irqrestore(&sc->ps_state_lock, flags);
++			if (HCI_SEND(sc->sh, skb, 4) < 0) {
++				printk("bcast_timer send fail!!!!!!! \n");
++				ssv6xxx_txbuf_free_skb(skb, (void *)sc);
++				BUG_ON(1);
++			}
++			spin_lock_irqsave(&sc->ps_state_lock, flags);
++		}
++	} while (0);
++	if (needtimer) {
++#ifdef BCAST_DEBUG
++		printk
++		    ("[B] bcast_timer:need more timer to tx bcast frame time[%d]\n",
++		     sc->bcast_interval);
++#endif
++		queue_delayed_work(sc->config_wq, &sc->bcast_tx_work, tmo);
++	} else {
++#ifdef BCAST_DEBUG
++		printk("[B] bcast_timer: ssv6200_bcast_stop\n");
++#endif
++		ssv6200_bcast_stop(sc);
++	}
++	spin_unlock_irqrestore(&sc->ps_state_lock, flags);
++#ifdef BCAST_DEBUG
++	printk("[B] bcast_timer: leave.....................\n");
++#endif
++}
++
++void ssv6200_bcast_start_work(struct work_struct *work)
++{
++	struct ssv_softc *sc =
++	    container_of(work, struct ssv_softc, bcast_start_work);
++#ifdef BCAST_DEBUG
++	printk("[B] ssv6200_bcast_start_work==\n");
++#endif
++	sc->bcast_interval = (sc->beacon_dtim_cnt + 1) *
++	    (sc->beacon_interval + 20) * HZ / 1000;
++	if (!sc->aid0_bit_set) {
++		sc->aid0_bit_set = true;
++		ssv6xxx_beacon_change(sc, sc->hw, sc->ap_vif, sc->aid0_bit_set);
++		queue_delayed_work(sc->config_wq,
++				   &sc->bcast_tx_work, sc->bcast_interval);
++#ifdef BCAST_DEBUG
++		printk("[B] bcast_start_work: Modify timer to DTIM[%d]ms==\n",
++		       (sc->beacon_dtim_cnt + 1) * (sc->beacon_interval + 20));
++#endif
++	}
++}
++
++void ssv6200_bcast_stop_work(struct work_struct *work)
++{
++	struct ssv_softc *sc =
++	    container_of(work, struct ssv_softc, bcast_stop_work.work);
++	long tmo = HZ / 100;
++#ifdef BCAST_DEBUG
++	printk("[B] ssv6200_bcast_stop_work\n");
++#endif
++	if (sc->aid0_bit_set) {
++		if (0 == ssv6200_bcast_queue_len(&sc->bcast_txq)) {
++			cancel_delayed_work_sync(&sc->bcast_tx_work);
++			sc->aid0_bit_set = false;
++			ssv6xxx_beacon_change(sc, sc->hw,
++					      sc->ap_vif, sc->aid0_bit_set);
++#ifdef BCAST_DEBUG
++			printk("remove group bit in DTIM\n");
++#endif
++		} else {
++#ifdef BCAST_DEBUG
++			printk
++			    ("bcast_stop_work: bcast queue still have data. just modify timer to 10ms\n");
++#endif
++			queue_delayed_work(sc->config_wq,
++					   &sc->bcast_tx_work, tmo);
++		}
++	}
++}
++
++void ssv6200_bcast_stop(struct ssv_softc *sc)
++{
++	queue_delayed_work(sc->config_wq,
++			   &sc->bcast_stop_work,
++			   sc->beacon_interval * HZ / 1024);
++}
++
++void ssv6200_bcast_start(struct ssv_softc *sc)
++{
++	queue_work(sc->config_wq, &sc->bcast_start_work);
++}
++
++void ssv6200_release_bcast_frame_res(struct ssv_softc *sc,
++				     struct ieee80211_vif *vif)
++{
++	unsigned long flags;
++	struct ssv_vif_priv_data *priv_vif =
++	    (struct ssv_vif_priv_data *)vif->drv_priv;
++	spin_lock_irqsave(&sc->ps_state_lock, flags);
++	priv_vif->sta_asleep_mask = 0;
++	spin_unlock_irqrestore(&sc->ps_state_lock, flags);
++	cancel_work_sync(&sc->bcast_start_work);
++	cancel_delayed_work_sync(&sc->bcast_stop_work);
++	ssv6200_bcast_flush(sc, &sc->bcast_txq);
++	cancel_delayed_work_sync(&sc->bcast_tx_work);
++}
+diff --git a/drivers/net/wireless/ssv6051/smac/ap.h b/drivers/net/wireless/ssv6051/smac/ap.h
+new file mode 100644
+index 000000000000..93b5275715b5
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/ap.h
+@@ -0,0 +1,41 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation, either version 3 of the License, or
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _AP_H_
++#define _AP_H_
++#define BEACON_WAITING_ENABLED 1<<0
++#define BEACON_ENABLED 1<<1
++void ssv6xxx_beacon_change(struct ssv_softc *sc, struct ieee80211_hw *hw,
++			   struct ieee80211_vif *vif, bool aid0_bit_set);
++void ssv6xxx_beacon_set_info(struct ssv_softc *sc, u8 beacon_interval,
++			     u8 dtim_cnt);
++bool ssv6xxx_beacon_enable(struct ssv_softc *sc, bool bEnable);
++void ssv6xxx_beacon_release(struct ssv_softc *sc);
++void ssv6200_set_tim_work(struct work_struct *work);
++void ssv6200_bcast_start_work(struct work_struct *work);
++void ssv6200_bcast_stop_work(struct work_struct *work);
++void ssv6200_bcast_tx_work(struct work_struct *work);
++int ssv6200_bcast_queue_len(struct ssv6xxx_bcast_txq *bcast_txq);
++struct sk_buff *ssv6200_bcast_dequeue(struct ssv6xxx_bcast_txq *bcast_txq,
++				      u8 * remain_len);
++int ssv6200_bcast_enqueue(struct ssv_softc *sc,
++			  struct ssv6xxx_bcast_txq *bcast_txq,
++			  struct sk_buff *skb);
++void ssv6200_bcast_start(struct ssv_softc *sc);
++void ssv6200_bcast_stop(struct ssv_softc *sc);
++void ssv6200_release_bcast_frame_res(struct ssv_softc *sc,
++				     struct ieee80211_vif *vif);
++#endif
+diff --git a/drivers/net/wireless/ssv6051/smac/dev.c b/drivers/net/wireless/ssv6051/smac/dev.c
+new file mode 100644
+index 000000000000..214e93fae460
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/dev.c
+@@ -0,0 +1,3881 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation, either version 3 of the License, or
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <linux/nl80211.h>
++#include <linux/etherdevice.h>
++#include <linux/delay.h>
++#include <linux/version.h>
++#include <linux/time.h>
++#include <linux/kthread.h>
++#include <linux/ktime.h>
++
++#include <net/mac80211.h>
++#include <ssv6200.h>
++#include <hci/hctrl.h>
++#include "linux_80211.h"
++#include "lib.h"
++#include "ssv_rc.h"
++#include "ssv_ht_rc.h"
++#include "dev.h"
++#include "ap.h"
++#include "init.h"
++#include "p2p.h"
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++#include "ssv6xxx_debugfs.h"
++#endif
++struct rssi_res_st rssi_res, *p_rssi_res;
++#define NO_USE_RXQ_LOCK
++#ifndef WLAN_CIPHER_SUITE_SMS4
++#define WLAN_CIPHER_SUITE_SMS4 0x00147201
++#endif
++#define MAX_TX_Q_LEN (64)
++#define LOW_TX_Q_LEN (MAX_TX_Q_LEN/2)
++static u16 bits_per_symbol[][2] = {
++	{26, 54},
++	{52, 108},
++	{78, 162},
++	{104, 216},
++	{156, 324},
++	{208, 432},
++	{234, 486},
++	{260, 540},
++};
++
++#ifdef CONFIG_DEBUG_SKB_TIMESTAMP
++extern struct ssv6xxx_hci_ctrl *ssv_dbg_ctrl_hci;
++extern unsigned int cal_duration_of_ampdu(struct sk_buff *ampdu_skb, int stage);
++#endif
++struct ssv6xxx_calib_table {
++	u16 channel_id;
++	u32 rf_ctrl_N;
++	u32 rf_ctrl_F;
++	u16 rf_precision_default;
++};
++static void _process_rx_q(struct ssv_softc *sc, struct sk_buff_head *rx_q,
++			  spinlock_t * rx_q_lock);
++static u32 _process_tx_done(struct ssv_softc *sc);
++
++void ssv6xxx_txbuf_free_skb(struct sk_buff *skb, void *args)
++{
++	struct ssv_softc *sc = (struct ssv_softc *)args;
++	if (!skb)
++		return;
++	ieee80211_free_txskb(sc->hw, skb);
++}
++
++#define ADDRESS_OFFSET 16
++#define HW_ID_OFFSET 7
++#define CH0_FULL_MASK CH0_FULL_MSK
++#define MAX_FAIL_COUNT 100
++#define MAX_RETRY_COUNT 20
++inline bool ssv6xxx_mcu_input_full(struct ssv_softc *sc)
++{
++	u32 regval = 0;
++	SMAC_REG_READ(sc->sh, ADR_MCU_STATUS, &regval);
++	return CH0_FULL_MASK & regval;
++}
++
++u32 ssv6xxx_pbuf_alloc(struct ssv_softc *sc, int size, int type)
++{
++	u32 regval, pad;
++	int cnt = MAX_RETRY_COUNT;
++	int page_cnt =
++	    (size + ((1 << HW_MMU_PAGE_SHIFT) - 1)) >> HW_MMU_PAGE_SHIFT;
++	regval = 0;
++	mutex_lock(&sc->mem_mutex);
++	pad = size % 4;
++	size += pad;
++	do {
++		SMAC_REG_WRITE(sc->sh, ADR_WR_ALC, (size | (type << 16)));
++		SMAC_REG_READ(sc->sh, ADR_WR_ALC, &regval);
++		if (regval == 0) {
++			cnt--;
++			msleep(1);
++		} else
++			break;
++	} while (cnt);
++	if (type == TX_BUF) {
++		sc->sh->tx_page_available -= page_cnt;
++		sc->sh->page_count[PACKET_ADDR_2_ID(regval)] = page_cnt;
++	}
++	mutex_unlock(&sc->mem_mutex);
++	if (regval == 0)
++		dev_err(sc->dev,
++			"Failed to allocate packet buffer of %d bytes in %d type.",
++			size, type);
++	else {
++		dev_dbg(sc->dev,
++			"Allocated %d type packet buffer of size %d (%d) at address %x.\n",
++			type, size, page_cnt, regval);
++	}
++	return regval;
++}
++
++bool ssv6xxx_pbuf_free(struct ssv_softc *sc, u32 pbuf_addr)
++{
++	u32 regval = 0;
++	u16 failCount = 0;
++	u8 *p_tx_page_cnt = &sc->sh->page_count[PACKET_ADDR_2_ID(pbuf_addr)];
++	while (ssv6xxx_mcu_input_full(sc)) {
++		if (failCount++ < 1000)
++			continue;
++		dev_err(sc->dev, "Error in mailbox block after %d iterations\n", failCount);
++		return false;
++	}
++	mutex_lock(&sc->mem_mutex);
++	regval =
++	    ((M_ENG_TRASH_CAN << HW_ID_OFFSET) | (pbuf_addr >> ADDRESS_OFFSET));
++	SMAC_REG_WRITE(sc->sh, ADR_CH0_TRIG_1, regval);
++	if (*p_tx_page_cnt) {
++		sc->sh->tx_page_available += *p_tx_page_cnt;
++		*p_tx_page_cnt = 0;
++	}
++	mutex_unlock(&sc->mem_mutex);
++	return true;
++}
++
++static const struct ssv6xxx_calib_table vt_tbl[SSV6XXX_IQK_CFG_XTAL_MAX][14] = {
++	{
++	 {1, 0xB9, 0x89D89E, 3859},
++	 {2, 0xB9, 0xEC4EC5, 3867},
++	 {3, 0xBA, 0x4EC4EC, 3875},
++	 {4, 0xBA, 0xB13B14, 3883},
++	 {5, 0xBB, 0x13B13B, 3891},
++	 {6, 0xBB, 0x762762, 3899},
++	 {7, 0xBB, 0xD89D8A, 3907},
++	 {8, 0xBC, 0x3B13B1, 3915},
++	 {9, 0xBC, 0x9D89D9, 3923},
++	 {10, 0xBD, 0x000000, 3931},
++	 {11, 0xBD, 0x627627, 3939},
++	 {12, 0xBD, 0xC4EC4F, 3947},
++	 {13, 0xBE, 0x276276, 3955},
++	 {14, 0xBF, 0x13B13B, 3974},
++	 },
++	{
++	 {1, 0xf1, 0x333333, 3859},
++	 {2, 0xf1, 0xB33333, 3867},
++	 {3, 0xf2, 0x333333, 3875},
++	 {4, 0xf2, 0xB33333, 3883},
++	 {5, 0xf3, 0x333333, 3891},
++	 {6, 0xf3, 0xB33333, 3899},
++	 {7, 0xf4, 0x333333, 3907},
++	 {8, 0xf4, 0xB33333, 3915},
++	 {9, 0xf5, 0x333333, 3923},
++	 {10, 0xf5, 0xB33333, 3931},
++	 {11, 0xf6, 0x333333, 3939},
++	 {12, 0xf6, 0xB33333, 3947},
++	 {13, 0xf7, 0x333333, 3955},
++	 {14, 0xf8, 0x666666, 3974},
++	 },
++	{
++	 {1, 0xC9, 0x000000, 3859},
++	 {2, 0xC9, 0x6AAAAB, 3867},
++	 {3, 0xC9, 0xD55555, 3875},
++	 {4, 0xCA, 0x400000, 3883},
++	 {5, 0xCA, 0xAAAAAB, 3891},
++	 {6, 0xCB, 0x155555, 3899},
++	 {7, 0xCB, 0x800000, 3907},
++	 {8, 0xCB, 0xEAAAAB, 3915},
++	 {9, 0xCC, 0x555555, 3923},
++	 {10, 0xCC, 0xC00000, 3931},
++	 {11, 0xCD, 0x2AAAAB, 3939},
++	 {12, 0xCD, 0x955555, 3947},
++	 {13, 0xCE, 0x000000, 3955},
++	 {14, 0xCF, 0x000000, 3974},
++	 }
++};
++
++#define FAIL_MAX 100
++#define RETRY_MAX 20
++int ssv6xxx_set_channel(struct ssv_softc *sc, int ch)
++{
++	struct ssv_hw *sh = sc->sh;
++	int retry_cnt, fail_cnt = 0;
++	u32 regval;
++	int ret = -1;
++	int chidx;
++	bool chidx_vld = 0;
++	dev_dbg(sc->dev, "Setting channel to %d\n", ch);
++	if ((sh->cfg.chip_identity == SSV6051Z)
++	    || (sc->sh->cfg.chip_identity == SSV6051P)) {
++		if ((ch == 13) || (ch == 14)) {
++			if (sh->ipd_channel_touch == 0) {
++				for (chidx = 0; chidx < sh->ch_cfg_size;
++				     chidx++) {
++					SMAC_REG_WRITE(sh,
++						       sh->p_ch_cfg[chidx].
++						       reg_addr,
++						       sh->p_ch_cfg[chidx].
++						       ch13_14_value);
++				}
++				sh->ipd_channel_touch = 1;
++			}
++		} else {
++			if (sh->ipd_channel_touch) {
++				for (chidx = 0; chidx < sh->ch_cfg_size;
++				     chidx++) {
++					SMAC_REG_WRITE(sh,
++						       sh->p_ch_cfg[chidx].
++						       reg_addr,
++						       sh->p_ch_cfg[chidx].
++						       ch1_12_value);
++				}
++				sh->ipd_channel_touch = 0;
++			}
++		}
++	}
++	for (chidx = 0; chidx < 14; chidx++) {
++		if (vt_tbl[sh->cfg.crystal_type][chidx].channel_id == ch) {
++			chidx_vld = 1;
++			break;
++		}
++	}
++	if (chidx_vld == 0) {
++		dev_dbg(sc->dev, "%s(): fail! channel_id not found in vt_tbl\n",
++			__FUNCTION__);
++		goto exit;
++	}
++	if ((ret = ssv6xxx_rf_disable(sc->sh)) != 0)
++		goto exit;
++	do {
++		if ((sh->cfg.crystal_type == SSV6XXX_IQK_CFG_XTAL_26M)
++		    || (sh->cfg.crystal_type == SSV6XXX_IQK_CFG_XTAL_24M)) {
++			if ((ret =
++			     SMAC_REG_SET_BITS(sc->sh, ADR_SYN_DIV_SDM_XOSC,
++					       (0x00 << 13),
++					       (0x01 << 13))) != 0)
++				break;
++		} else if (sh->cfg.crystal_type == SSV6XXX_IQK_CFG_XTAL_40M) {
++			if ((ret =
++			     SMAC_REG_SET_BITS(sc->sh, ADR_SYN_DIV_SDM_XOSC,
++					       (0x01 << 13),
++					       (0x01 << 13))) != 0)
++				break;
++		} else {
++			dev_warn(sc->dev, "Illegal crystal setting in ssv6xxx_set_channel\n");
++			BUG_ON(1);
++		}
++		if ((ret = SMAC_REG_SET_BITS(sc->sh, ADR_SX_LCK_BIN_REGISTERS_I,
++					     (0x01 << 19), (0x01 << 19))) != 0)
++			break;
++		regval = vt_tbl[sh->cfg.crystal_type][chidx].rf_ctrl_F;
++		if ((ret = SMAC_REG_SET_BITS(sc->sh, ADR_SYN_REGISTER_1,
++					     (regval << 0),
++					     (0x00ffffff << 0))) != 0)
++			break;
++		regval = vt_tbl[sh->cfg.crystal_type][chidx].rf_ctrl_N;
++		if ((ret = SMAC_REG_SET_BITS(sc->sh, ADR_SYN_REGISTER_2,
++					     (regval << 0),
++					     (0x07ff << 0))) != 0)
++			break;
++		if ((ret =
++		     SMAC_REG_READ(sc->sh, ADR_SX_LCK_BIN_REGISTERS_I,
++				   &regval)) != 0)
++			break;
++		regval =
++		    vt_tbl[sh->cfg.crystal_type][chidx].rf_precision_default;
++		if ((ret =
++		     SMAC_REG_SET_BITS(sc->sh, ADR_SX_LCK_BIN_REGISTERS_II,
++				       (regval << 0), (0x1fff << 0))) != 0)
++			break;
++		if ((ret = SMAC_REG_SET_BITS(sc->sh, ADR_MANUAL_ENABLE_REGISTER,
++					     (0x00 << 14), (0x01 << 14))) != 0)
++			break;
++		if ((ret = SMAC_REG_SET_BITS(sc->sh, ADR_MANUAL_ENABLE_REGISTER,
++					     (0x01 << 14), (0x01 << 14))) != 0)
++			break;
++		retry_cnt = 0;
++		do {
++			mdelay(1);
++			if ((ret =
++			     SMAC_REG_READ(sc->sh, ADR_READ_ONLY_FLAGS_1,
++					   &regval)) != 0)
++				break;
++			if (regval & 0x00000002) {
++				if ((ret =
++				     SMAC_REG_READ(sc->sh,
++						   ADR_READ_ONLY_FLAGS_2,
++						   &regval)) != 0)
++					break;
++				ret = ssv6xxx_rf_enable(sc->sh);
++				//dev_info(sc->dev, "Lock to channel %d ([0xce010098]=%x)!!\n", vt_tbl[sh->cfg.crystal_type][chidx].channel_id, regval);
++				sc->hw_chan = ch;
++				goto exit;
++			}
++			retry_cnt++;
++		}
++		while (retry_cnt < RETRY_MAX);
++		fail_cnt++;
++		dev_warn(sc->dev, "calibation fail after %d iterations\n", fail_cnt);
++	}
++	while ((fail_cnt < FAIL_MAX) && (ret == 0));
++ exit:
++	if (ch == 14 && regval == 0xff0) {
++		SMAC_IFC_RESET(sc->sh);
++		ssv6xxx_restart_hw(sc);
++	}
++	if (ch <= 7) {
++		if (sh->cfg.tx_power_index_1) {
++			SMAC_REG_READ(sc->sh, ADR_RX_TX_FSM_REGISTER, &regval);
++			regval &= RG_TX_GAIN_OFFSET_I_MSK;
++			regval |=
++			    (sh->cfg.tx_power_index_1 << RG_TX_GAIN_OFFSET_SFT);
++			SMAC_REG_WRITE(sc->sh, ADR_RX_TX_FSM_REGISTER, regval);
++		} else if (sh->cfg.tx_power_index_2) {
++			SMAC_REG_READ(sc->sh, ADR_RX_TX_FSM_REGISTER, &regval);
++			regval &= RG_TX_GAIN_OFFSET_I_MSK;
++			SMAC_REG_WRITE(sc->sh, ADR_RX_TX_FSM_REGISTER, regval);
++		}
++	} else {
++		if (sh->cfg.tx_power_index_2) {
++			SMAC_REG_READ(sc->sh, ADR_RX_TX_FSM_REGISTER, &regval);
++			regval &= RG_TX_GAIN_OFFSET_I_MSK;
++			regval |=
++			    (sh->cfg.tx_power_index_2 << RG_TX_GAIN_OFFSET_SFT);
++			SMAC_REG_WRITE(sc->sh, ADR_RX_TX_FSM_REGISTER, regval);
++		} else if (sh->cfg.tx_power_index_1) {
++			SMAC_REG_READ(sc->sh, ADR_RX_TX_FSM_REGISTER, &regval);
++			regval &= RG_TX_GAIN_OFFSET_I_MSK;
++			SMAC_REG_WRITE(sc->sh, ADR_RX_TX_FSM_REGISTER, regval);
++		}
++	}
++	return ret;
++}
++
++#ifdef CONFIG_SSV_SMARTLINK
++int ssv6xxx_get_channel(struct ssv_softc *sc, int *pch)
++{
++	*pch = sc->hw_chan;
++	return 0;
++}
++
++int ssv6xxx_set_promisc(struct ssv_softc *sc, int accept)
++{
++	u32 val = 0;
++	if (accept) {
++		val = 0x2;
++	} else {
++		val = 0x3;
++	}
++	SMAC_REG_WRITE(sc->sh, ADR_MRX_FLT_TB13, val);
++	return 0;
++}
++
++int ssv6xxx_get_promisc(struct ssv_softc *sc, int *paccept)
++{
++	u32 val = 0;
++	SMAC_REG_READ(sc->sh, ADR_MRX_FLT_TB13, &val);
++	if (val == 0x2) {
++		*paccept = 1;
++	} else {
++		*paccept = 0;
++	}
++	return 0;
++}
++#endif
++int ssv6xxx_rf_enable(struct ssv_hw *sh)
++{
++	return SMAC_REG_SET_BITS(sh, 0xce010000, (0x02 << 12), (0x03 << 12)
++	    );
++}
++
++int ssv6xxx_rf_disable(struct ssv_hw *sh)
++{
++	return SMAC_REG_SET_BITS(sh, 0xce010000, (0x01 << 12), (0x03 << 12)
++	    );
++}
++
++int ssv6xxx_update_decision_table(struct ssv_softc *sc)
++{
++	int i;
++	for (i = 0; i < MAC_DECITBL1_SIZE; i++) {
++		SMAC_REG_WRITE(sc->sh, ADR_MRX_FLT_TB0 + i * 4,
++			       sc->mac_deci_tbl[i]);
++		SMAC_REG_CONFIRM(sc->sh, ADR_MRX_FLT_TB0 + i * 4,
++				 sc->mac_deci_tbl[i]);
++	}
++	for (i = 0; i < MAC_DECITBL2_SIZE; i++) {
++		SMAC_REG_WRITE(sc->sh, ADR_MRX_FLT_EN0 + i * 4,
++			       sc->mac_deci_tbl[i + MAC_DECITBL1_SIZE]);
++		SMAC_REG_CONFIRM(sc->sh, ADR_MRX_FLT_EN0 + i * 4,
++				 sc->mac_deci_tbl[i + MAC_DECITBL1_SIZE]);
++	}
++	return 0;
++}
++
++static int ssv6xxx_frame_hdrlen(struct ieee80211_hdr *hdr, bool is_ht)
++{
++#define CTRL_FRAME_INDEX(fc) ((hdr->frame_control-IEEE80211_STYPE_BACK_REQ)>>4)
++	u16 fc, CTRL_FLEN[] = { 16, 16, 16, 16, 10, 10, 16, 16 };
++	int hdr_len = 24;
++	fc = hdr->frame_control;
++	if (ieee80211_is_ctl(fc))
++		hdr_len = CTRL_FLEN[CTRL_FRAME_INDEX(fc)];
++	else if (ieee80211_is_mgmt(fc)) {
++		if (ieee80211_has_order(fc))
++			hdr_len += ((is_ht == 1) ? 4 : 0);
++	} else {
++		if (ieee80211_has_a4(fc))
++			hdr_len += 6;
++		if (ieee80211_is_data_qos(fc)) {
++			hdr_len += 2;
++			if (ieee80211_has_order(hdr->frame_control) &&
++			    is_ht == true)
++				hdr_len += 4;
++		}
++	}
++	return hdr_len;
++}
++
++static u32 ssv6xxx_ht_txtime(u8 rix, int pktlen, int width,
++			     int half_gi, bool is_gf)
++{
++	u32 nbits, nsymbits, duration, nsymbols;
++	int streams;
++	streams = 1;
++	nbits = (pktlen << 3) + OFDM_PLCP_BITS;
++	nsymbits = bits_per_symbol[rix % 8][width] * streams;
++	nsymbols = (nbits + nsymbits - 1) / nsymbits;
++	if (!half_gi)
++		duration = SYMBOL_TIME(nsymbols);
++	else {
++		if (!is_gf)
++			duration =
++			    DIV_ROUND_UP(SYMBOL_TIME_HALFGI(nsymbols), 4) << 2;
++		else
++			duration = SYMBOL_TIME_HALFGI(nsymbols);
++	}
++	duration +=
++	    L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams) +
++	    HT_SIGNAL_EXT;
++	if (is_gf)
++		duration -= 12;
++	duration += HT_SIFS_TIME;
++	return duration;
++}
++
++static u32 ssv6xxx_non_ht_txtime(u8 phy, int kbps,
++				 u32 frameLen, bool shortPreamble)
++{
++	u32 bits_per_symbol, num_bits, num_symbols;
++	u32 phy_time, tx_time;
++	if (kbps == 0)
++		return 0;
++	switch (phy) {
++	case WLAN_RC_PHY_CCK:
++		phy_time = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
++		if (shortPreamble)
++			phy_time >>= 1;
++		num_bits = frameLen << 3;
++		tx_time = CCK_SIFS_TIME + phy_time + ((num_bits * 1000) / kbps);
++		break;
++	case WLAN_RC_PHY_OFDM:
++		bits_per_symbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
++		num_bits = OFDM_PLCP_BITS + (frameLen << 3);
++		num_symbols = DIV_ROUND_UP(num_bits, bits_per_symbol);
++		tx_time = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
++		    + (num_symbols * OFDM_SYMBOL_TIME);
++		break;
++	default:
++		pr_err("ssv6051: unknown phy %u\n", phy);
++		BUG_ON(1);
++		tx_time = 0;
++		break;
++	}
++	return tx_time;
++}
++
++static u32 ssv6xxx_set_frame_duration(struct ieee80211_tx_info *info,
++				      struct ssv_rate_info *ssv_rate, u16 len,
++				      struct ssv6200_tx_desc *tx_desc,
++				      struct fw_rc_retry_params *rc_params,
++				      struct ssv_softc *sc)
++{
++	struct ieee80211_tx_rate *tx_drate;
++	u32 frame_time = 0, ack_time = 0, rts_cts_nav = 0, frame_consume_time =
++	    0;
++	u32 l_length = 0, drate_kbps = 0, crate_kbps = 0;
++	bool ctrl_short_preamble = false, is_sgi, is_ht40;
++	bool is_ht, is_gf;
++	int d_phy, c_phy, nRCParams, mcsidx;
++	struct ssv_rate_ctrl *ssv_rc = NULL;
++	tx_drate = &info->control.rates[0];
++	is_sgi = !!(tx_drate->flags & IEEE80211_TX_RC_SHORT_GI);
++	is_ht40 = !!(tx_drate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH);
++	is_ht = !!(tx_drate->flags & IEEE80211_TX_RC_MCS);
++	is_gf = !!(tx_drate->flags & IEEE80211_TX_RC_GREEN_FIELD);
++	if ((info->control.short_preamble) ||
++	    (tx_drate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE))
++		ctrl_short_preamble = true;
++	pr_debug("mcs = %d, data rate idx=%d\n", tx_drate->idx, tx_drate[3].count);
++	for (nRCParams = 0; (nRCParams < SSV62XX_TX_MAX_RATES); nRCParams++) {
++		if ((rc_params == NULL) || (sc == NULL)) {
++			mcsidx = tx_drate->idx;
++			drate_kbps = ssv_rate->drate_kbps;
++			crate_kbps = ssv_rate->crate_kbps;
++		} else {
++			if (rc_params[nRCParams].count == 0) {
++				break;
++			}
++			ssv_rc = sc->rc;
++			mcsidx =
++			    (rc_params[nRCParams].drate -
++			     SSV62XX_RATE_MCS_INDEX) % MCS_GROUP_RATES;
++			drate_kbps =
++			    ssv_rc->rc_table[rc_params[nRCParams].drate].
++			    rate_kbps;
++			crate_kbps =
++			    ssv_rc->rc_table[rc_params[nRCParams].crate].
++			    rate_kbps;
++		}
++		if (tx_drate->flags & IEEE80211_TX_RC_MCS) {
++			frame_time = ssv6xxx_ht_txtime(mcsidx,
++						       len, is_ht40, is_sgi,
++						       is_gf);
++			d_phy = 0;
++		} else {
++			if ((info->band == INDEX_80211_BAND_2GHZ) &&
++			    !(ssv_rate->d_flags & IEEE80211_RATE_ERP_G))
++				d_phy = WLAN_RC_PHY_CCK;
++			else
++				d_phy = WLAN_RC_PHY_OFDM;
++			frame_time = ssv6xxx_non_ht_txtime(d_phy, drate_kbps,
++							   len,
++							   ctrl_short_preamble);
++		}
++		if ((info->band == INDEX_80211_BAND_2GHZ) &&
++		    !(ssv_rate->c_flags & IEEE80211_RATE_ERP_G))
++			c_phy = WLAN_RC_PHY_CCK;
++		else
++			c_phy = WLAN_RC_PHY_OFDM;
++		if (tx_desc->unicast) {
++			if (info->flags & IEEE80211_TX_CTL_AMPDU) {
++				ack_time = ssv6xxx_non_ht_txtime(c_phy,
++								 crate_kbps,
++								 BA_LEN,
++								 ctrl_short_preamble);
++			} else {
++				ack_time = ssv6xxx_non_ht_txtime(c_phy,
++								 crate_kbps,
++								 ACK_LEN,
++								 ctrl_short_preamble);
++			}
++		}
++		if (tx_desc->do_rts_cts & IEEE80211_TX_RC_USE_RTS_CTS) {
++			rts_cts_nav = frame_time;
++			rts_cts_nav += ack_time;
++			rts_cts_nav += ssv6xxx_non_ht_txtime(c_phy,
++							     crate_kbps,
++							     CTS_LEN,
++							     ctrl_short_preamble);
++			frame_consume_time = rts_cts_nav;
++			frame_consume_time += ssv6xxx_non_ht_txtime(c_phy,
++								    crate_kbps,
++								    RTS_LEN,
++								    ctrl_short_preamble);
++		} else if (tx_desc->
++			   do_rts_cts & IEEE80211_TX_RC_USE_CTS_PROTECT) {
++			rts_cts_nav = frame_time;
++			rts_cts_nav += ack_time;
++			frame_consume_time = rts_cts_nav;
++			frame_consume_time += ssv6xxx_non_ht_txtime(c_phy,
++								    crate_kbps,
++								    CTS_LEN,
++								    ctrl_short_preamble);
++		} else {;
++		}
++		if (tx_drate->flags & IEEE80211_TX_RC_MCS) {
++			l_length = frame_time - HT_SIFS_TIME;
++			l_length = ((l_length - (HT_SIGNAL_EXT + 20)) + 3) >> 2;
++			l_length += ((l_length << 1) - 3);
++		}
++		if ((rc_params == NULL) || (sc == NULL)) {
++			tx_desc->rts_cts_nav = rts_cts_nav;
++			tx_desc->frame_consume_time =
++			    (frame_consume_time >> 5) + 1;;
++			tx_desc->dl_length = l_length;
++			break;
++		} else {
++			rc_params[nRCParams].rts_cts_nav = rts_cts_nav;
++			rc_params[nRCParams].frame_consume_time =
++			    (frame_consume_time >> 5) + 1;
++			rc_params[nRCParams].dl_length = l_length;
++			if (nRCParams == 0) {
++				tx_desc->drate_idx = rc_params[nRCParams].drate;
++				tx_desc->crate_idx = rc_params[nRCParams].crate;
++				tx_desc->rts_cts_nav =
++				    rc_params[nRCParams].rts_cts_nav;
++				tx_desc->frame_consume_time =
++				    rc_params[nRCParams].frame_consume_time;
++				tx_desc->dl_length =
++				    rc_params[nRCParams].dl_length;
++			}
++		}
++	}
++	return ack_time;
++}
++
++static void ssv6200_hw_set_pair_type(struct ssv_hw *sh, u8 type)
++{
++	u32 temp;
++	SMAC_REG_READ(sh, ADR_SCRT_SET, &temp);
++	temp = (temp & PAIR_SCRT_I_MSK);
++	temp |= (type << PAIR_SCRT_SFT);
++	SMAC_REG_WRITE(sh, ADR_SCRT_SET, temp);
++	dev_dbg(sh->sc->dev, "==>%s: write cipher type %d into hw\n", __func__, type);
++}
++
++static u32 ssv6200_hw_get_pair_type(struct ssv_hw *sh)
++{
++	u32 temp;
++	SMAC_REG_READ(sh, ADR_SCRT_SET, &temp);
++	temp &= PAIR_SCRT_MSK;
++	temp = (temp >> PAIR_SCRT_SFT);
++	SMAC_REG_WRITE(sh, ADR_SCRT_SET, temp);
++	dev_dbg(sh->sc->dev, "==>%s: read cipher type %d from hw\n", __func__, temp);
++	return temp;
++}
++
++static void ssv6200_hw_set_group_type(struct ssv_hw *sh, u8 type)
++{
++	u32 temp;
++	SMAC_REG_READ(sh, ADR_SCRT_SET, &temp);
++	temp = temp & GRP_SCRT_I_MSK;
++	temp |= (type << GRP_SCRT_SFT);
++	SMAC_REG_WRITE(sh, ADR_SCRT_SET, temp);
++	dev_dbg(sh->sc->dev, "Set group key type %d\n", type);
++}
++
++void ssv6xxx_reset_sec_module(struct ssv_softc *sc)
++{
++	ssv6200_hw_set_group_type(sc->sh, ME_NONE);
++	ssv6200_hw_set_pair_type(sc->sh, ME_NONE);
++}
++
++static int hw_update_watch_wsid(struct ssv_softc *sc, struct ieee80211_sta *sta,
++				struct ssv_sta_info *sta_info, int sta_idx,
++				int rx_hw_sec, int ops)
++{
++	int ret = 0;
++	int retry_cnt = 20;
++	struct sk_buff *skb = NULL;
++	struct cfg_host_cmd *host_cmd;
++	struct ssv6xxx_wsid_params *ptr;
++	dev_dbg(sc->dev, "cmd=%d for fw wsid list, wsid %d \n", ops, sta_idx);
++	skb =
++	    ssv_skb_alloc(HOST_CMD_HDR_LEN +
++			  sizeof(struct ssv6xxx_wsid_params));
++	if (skb == NULL || sta_info == NULL || sc == NULL)
++		return -1;
++	skb->data_len = HOST_CMD_HDR_LEN + sizeof(struct ssv6xxx_wsid_params);
++	skb->len = skb->data_len;
++	host_cmd = (struct cfg_host_cmd *)skb->data;
++	host_cmd->c_type = HOST_CMD;
++	host_cmd->h_cmd = (u8) SSV6XXX_HOST_CMD_WSID_OP;
++	host_cmd->len = skb->data_len;
++	ptr = (struct ssv6xxx_wsid_params *)host_cmd->dat8;
++	ptr->cmd = ops;
++	ptr->hw_security = rx_hw_sec;
++	if ((ptr->cmd != SSV6XXX_WSID_OPS_HWWSID_PAIRWISE_SET_TYPE)
++	    && (ptr->cmd != SSV6XXX_WSID_OPS_HWWSID_GROUP_SET_TYPE)) {
++		ptr->wsid_idx = (u8) (sta_idx - SSV_NUM_HW_STA);
++	} else {
++		ptr->wsid_idx = (u8) (sta_idx);
++	};
++	memcpy(&ptr->target_wsid, &sta->addr[0], 6);
++	while (((sc->sh->hci.hci_ops->hci_send_cmd(skb)) != 0) && (retry_cnt)) {
++		dev_dbg(sc->dev, "WSID cmd=%d retry=%d!!\n", ops, retry_cnt);
++		retry_cnt--;
++	}
++	dev_dbg(sc->dev, "%s: wsid_idx = %u\n", __FUNCTION__, ptr->wsid_idx);
++	ssv_skb_free(skb);
++	if (ops == SSV6XXX_WSID_OPS_ADD)
++		sta_info->hw_wsid = sta_idx;
++	return ret;
++}
++
++static void hw_crypto_key_clear(struct ieee80211_hw *hw, int index,
++				struct ieee80211_key_conf *key,
++				struct ssv_vif_priv_data *vif_priv,
++				struct ssv_sta_priv_data *sta_priv)
++{
++	struct ssv_softc *sc = hw->priv;
++	struct ssv_sta_info *sta_info = NULL;
++	if ((index == 0) && (sta_priv == NULL))
++		return;
++	if ((index < 0) || (index >= 4))
++		return;
++	if (index > 0) {
++		if (vif_priv)
++			vif_priv->group_key_idx = 0;
++		if (sta_priv)
++			sta_priv->group_key_idx = 0;
++	}
++	if (sta_priv) {
++		sta_info = &sc->sta_info[sta_priv->sta_idx];
++		if ((index == 0) && (sta_priv->has_hw_decrypt == true)
++		    && (sta_info->hw_wsid >= SSV_NUM_HW_STA)) {
++			hw_update_watch_wsid(sc, sta_info->sta, sta_info,
++					     sta_priv->sta_idx,
++					     SSV6XXX_WSID_SEC_PAIRWISE,
++					     SSV6XXX_WSID_OPS_DISABLE_CAPS);
++		}
++	}
++	if (vif_priv) {
++		if ((index != 0) && !list_empty(&vif_priv->sta_list)) {
++			struct ssv_sta_priv_data *sta_priv_iter;
++			list_for_each_entry(sta_priv_iter, &vif_priv->sta_list,
++					    list) {
++				if (((sta_priv_iter->sta_info->
++				      s_flags & STA_FLAG_VALID) == 0)
++				    || (sta_priv_iter->sta_info->hw_wsid <
++					SSV_NUM_HW_STA))
++					continue;
++				hw_update_watch_wsid(sc,
++						     sta_priv_iter->sta_info->
++						     sta,
++						     sta_priv_iter->sta_info,
++						     sta_priv_iter->sta_idx,
++						     SSV6XXX_WSID_SEC_GROUP,
++						     SSV6XXX_WSID_OPS_DISABLE_CAPS);
++			}
++		}
++	}
++}
++
++static void _set_wep_sw_crypto_key(struct ssv_softc *sc,
++				   struct ssv_vif_info *vif_info,
++				   struct ssv_sta_info *sta_info, void *param)
++{
++	struct ssv_sta_priv_data *sta_priv =
++	    (struct ssv_sta_priv_data *)sta_info->sta->drv_priv;
++	struct ssv_vif_priv_data *vif_priv =
++	    (struct ssv_vif_priv_data *)vif_info->vif->drv_priv;
++	sta_priv->has_hw_encrypt = vif_priv->has_hw_encrypt;
++	sta_priv->has_hw_decrypt = vif_priv->has_hw_decrypt;
++	sta_priv->need_sw_encrypt = vif_priv->need_sw_encrypt;
++	sta_priv->need_sw_decrypt = vif_priv->need_sw_decrypt;
++}
++
++static void _set_wep_hw_crypto_pair_key(struct ssv_softc *sc,
++					struct ssv_vif_info *vif_info,
++					struct ssv_sta_info *sta_info,
++					void *param)
++{
++	int wsid = sta_info->hw_wsid;
++	struct ssv6xxx_hw_sec *sram_key = (struct ssv6xxx_hw_sec *)param;
++	int address = 0;
++	int *pointer = NULL;
++	u32 sec_key_tbl_base = sc->sh->hw_sec_key[0];
++	u32 sec_key_tbl = sec_key_tbl_base;
++	int i;
++	u8 *key = sram_key->sta_key[0].pair.key;
++	u32 key_len = *(u16 *) & sram_key->sta_key[0].reserve[0];
++	struct ssv_sta_priv_data *sta_priv =
++	    (struct ssv_sta_priv_data *)sta_info->sta->drv_priv;
++	struct ssv_vif_priv_data *vif_priv =
++	    (struct ssv_vif_priv_data *)vif_info->vif->drv_priv;
++	if (wsid == (-1))
++		return;
++	sram_key->sta_key[wsid].pair_key_idx = 0;
++	sram_key->sta_key[wsid].group_key_idx = 0;
++	sta_priv->has_hw_encrypt = vif_priv->has_hw_encrypt;
++	sta_priv->has_hw_decrypt = vif_priv->has_hw_decrypt;
++	sta_priv->need_sw_encrypt = vif_priv->need_sw_encrypt;
++	sta_priv->need_sw_decrypt = vif_priv->need_sw_decrypt;
++	if (wsid != 0)
++		memcpy(sram_key->sta_key[wsid].pair.key, key, key_len);
++	address = sec_key_tbl + (3 * sizeof(struct ssv6xxx_hw_key))
++	    + wsid * sizeof(struct ssv6xxx_hw_sta_key);
++	address += (0x10000 * wsid);
++	pointer = (int *)&sram_key->sta_key[wsid];
++	for (i = 0; i < (sizeof(struct ssv6xxx_hw_sta_key) / 4); i++)
++		SMAC_REG_WRITE(sc->sh, address + (i * 4), *(pointer++));
++}
++
++static void _set_wep_hw_crypto_group_key(struct ssv_softc *sc,
++					 struct ssv_vif_info *vif_info,
++					 struct ssv_sta_info *sta_info,
++					 void *param)
++{
++	int wsid = sta_info->hw_wsid;
++	struct ssv6xxx_hw_sec *sram_key = (struct ssv6xxx_hw_sec *)param;
++	int address = 0;
++	int *pointer = NULL;
++	u32 key_idx = sram_key->sta_key[0].pair_key_idx;
++	u32 sec_key_tbl_base = sc->sh->hw_sec_key[0];
++	u32 key_len = *(u16 *) & sram_key->sta_key[0].reserve[0];
++	u8 *key = sram_key->group_key[key_idx - 1].key;
++	u32 sec_key_tbl = sec_key_tbl_base;
++	struct ssv_sta_priv_data *sta_priv =
++	    (struct ssv_sta_priv_data *)sta_info->sta->drv_priv;
++	struct ssv_vif_priv_data *vif_priv =
++	    (struct ssv_vif_priv_data *)vif_info->vif->drv_priv;
++	if (wsid == (-1))
++		return;
++	if (wsid != 0) {
++		sram_key->sta_key[wsid].pair_key_idx = key_idx;
++		sram_key->sta_key[wsid].group_key_idx = key_idx;
++		sta_priv->has_hw_encrypt = vif_priv->has_hw_encrypt;
++		sta_priv->has_hw_decrypt = vif_priv->has_hw_decrypt;
++		sta_priv->need_sw_encrypt = vif_priv->need_sw_encrypt;
++		sta_priv->need_sw_decrypt = vif_priv->need_sw_decrypt;
++	}
++	if (wsid != 0)
++		memcpy(sram_key->group_key[key_idx - 1].key, key, key_len);
++	sec_key_tbl += (0x10000 * wsid);
++	address = sec_key_tbl + ((key_idx - 1) * sizeof(struct ssv6xxx_hw_key));
++	pointer = (int *)&sram_key->group_key[key_idx - 1];
++	{
++		int i;
++		for (i = 0; i < (sizeof(struct ssv6xxx_hw_key) / 4); i++)
++			SMAC_REG_WRITE(sc->sh, address + (i * 4), *(pointer++));
++	}
++	address = sec_key_tbl + (3 * sizeof(struct ssv6xxx_hw_key))
++	    + (wsid * sizeof(struct ssv6xxx_hw_sta_key));
++	pointer = (int *)&sram_key->sta_key[wsid];
++	SMAC_REG_WRITE(sc->sh, address, *(pointer));
++}
++
++static int hw_crypto_key_write_wep(struct ieee80211_hw *hw,
++				   struct ieee80211_key_conf *key,
++				   u8 algorithm, struct ssv_vif_info *vif_info)
++{
++	struct ssv_softc *sc = hw->priv;
++	struct ssv6xxx_hw_sec *sramKey = &vif_info->sramKey;
++	if (key->keyidx == 0) {
++		ssv6xxx_foreach_vif_sta(sc, vif_info,
++					_set_wep_hw_crypto_pair_key, sramKey);
++	} else {
++		ssv6xxx_foreach_vif_sta(sc, vif_info,
++					_set_wep_hw_crypto_group_key, sramKey);
++	}
++	return 0;
++}
++
++static void _set_aes_tkip_hw_crypto_group_key(struct ssv_softc *sc,
++					      struct ssv_vif_info *vif_info,
++					      struct ssv_sta_info *sta_info,
++					      void *param)
++{
++	int wsid = sta_info->hw_wsid;
++	int j;
++	u32 sec_key_tbl_base = sc->sh->hw_sec_key[0];
++	u32 sec_key_tbl = sec_key_tbl_base;
++	int address = 0;
++	int *pointer = 0;
++	struct ssv6xxx_hw_sec *sramKey = &(vif_info->sramKey);
++	int index = *(u8 *) param;
++	if (wsid == (-1))
++		return;
++	BUG_ON(index == 0);
++	sramKey->sta_key[wsid].group_key_idx = index;
++	sec_key_tbl += (0x10000 * wsid);
++	address = sec_key_tbl + ((index - 1) * sizeof(struct ssv6xxx_hw_key));
++	if (vif_info->vif_priv != NULL)
++		dev_dbg(sc->dev, "Write group key %d to VIF %d to %08X\n",
++			index, vif_info->vif_priv->vif_idx, address);
++	else
++		dev_err(sc->dev, "NULL VIF.\n");
++	pointer = (int *)&sramKey->group_key[index - 1];
++	for (j = 0; j < (sizeof(struct ssv6xxx_hw_key) / 4); j++)
++		SMAC_REG_WRITE(sc->sh, address + (j * 4), *(pointer++));
++	address = sec_key_tbl + (3 * sizeof(struct ssv6xxx_hw_key))
++	    + (wsid * sizeof(struct ssv6xxx_hw_sta_key));
++	pointer = (int *)&sramKey->sta_key[wsid];
++	SMAC_REG_WRITE(sc->sh, address, *(pointer));
++	if (wsid >= SSV_NUM_HW_STA) {
++		hw_update_watch_wsid(sc, sta_info->sta, sta_info,
++				     wsid, SSV6XXX_WSID_SEC_GROUP,
++				     SSV6XXX_WSID_OPS_ENABLE_CAPS);
++	}
++}
++
++static int _write_pairwise_key_to_hw(struct ssv_softc *sc,
++				     int index, u8 algorithm,
++				     const u8 * key, int key_len,
++				     struct ieee80211_key_conf *keyconf,
++				     struct ssv_vif_priv_data *vif_priv,
++				     struct ssv_sta_priv_data *sta_priv)
++{
++	int i;
++	struct ssv6xxx_hw_sec *sramKey;
++	int address = 0;
++	int *pointer = NULL;
++	u32 sec_key_tbl_base = sc->sh->hw_sec_key[0];
++	u32 sec_key_tbl;
++	int wsid = (-1);
++	if (sta_priv == NULL) {
++		dev_err(sc->dev, "Set pair-wise key with NULL STA.\n");
++		return -EOPNOTSUPP;
++	}
++	wsid = sta_priv->sta_info->hw_wsid;
++	if ((wsid < 0) || (wsid >= SSV_NUM_STA)) {
++		dev_err(sc->dev, "Set pair-wise key to invalid WSID %d.\n",
++			wsid);
++		return -EOPNOTSUPP;
++	}
++	dev_dbg(sc->dev, "Set STA %d's pair-wise key of %d bytes.\n", wsid,
++		key_len);
++	sramKey = &(sc->vif_info[vif_priv->vif_idx].sramKey);
++	sramKey->sta_key[wsid].pair_key_idx = 0;
++	sramKey->sta_key[wsid].group_key_idx = vif_priv->group_key_idx;
++	memcpy(sramKey->sta_key[wsid].pair.key, key, key_len);
++	sec_key_tbl = sec_key_tbl_base;
++	sec_key_tbl += (0x10000 * wsid);
++	address = sec_key_tbl + (3 * sizeof(struct ssv6xxx_hw_key))
++	    + wsid * sizeof(struct ssv6xxx_hw_sta_key);
++	pointer = (int *)&sramKey->sta_key[wsid];
++	for (i = 0; i < (sizeof(struct ssv6xxx_hw_sta_key) / 4); i++)
++		SMAC_REG_WRITE(sc->sh, (address + (i * 4)), *(pointer++));
++	if (wsid >= SSV_NUM_HW_STA) {
++		hw_update_watch_wsid(sc, sta_priv->sta_info->sta,
++				     sta_priv->sta_info, sta_priv->sta_idx,
++				     SSV6XXX_WSID_SEC_PAIRWISE,
++				     SSV6XXX_WSID_OPS_ENABLE_CAPS);
++	}
++	return 0;
++}
++
++static int _write_group_key_to_hw(struct ssv_softc *sc,
++				  int index, u8 algorithm,
++				  const u8 * key, int key_len,
++				  struct ieee80211_key_conf *keyconf,
++				  struct ssv_vif_priv_data *vif_priv,
++				  struct ssv_sta_priv_data *sta_priv)
++{
++	struct ssv6xxx_hw_sec *sramKey;
++	int wsid = sta_priv ? sta_priv->sta_info->hw_wsid : (-1);
++	int ret = 0;
++	if (vif_priv == NULL) {
++		dev_err(sc->dev, "Setting group key to NULL VIF\n");
++		return -EOPNOTSUPP;
++	}
++	dev_dbg(sc->dev,
++		"Setting VIF %d group key %d of length %d to WSID %d.\n",
++		vif_priv->vif_idx, index, key_len, wsid);
++	sramKey = &(sc->vif_info[vif_priv->vif_idx].sramKey);
++	vif_priv->group_key_idx = index;
++	if (sta_priv)
++		sta_priv->group_key_idx = index;
++	memcpy(sramKey->group_key[index - 1].key, key, key_len);
++	WARN_ON(sc->vif_info[vif_priv->vif_idx].vif_priv == NULL);
++	ssv6xxx_foreach_vif_sta(sc, &sc->vif_info[vif_priv->vif_idx],
++				_set_aes_tkip_hw_crypto_group_key, &index);
++	ret = 0;
++	return ret;
++}
++
++static enum SSV_CIPHER_E _prepare_key(struct ieee80211_key_conf *key)
++{
++	enum SSV_CIPHER_E cipher;
++	switch (key->cipher) {
++	case WLAN_CIPHER_SUITE_WEP40:
++		cipher = SSV_CIPHER_WEP40;
++		break;
++	case WLAN_CIPHER_SUITE_WEP104:
++		cipher = SSV_CIPHER_WEP104;
++		break;
++	case WLAN_CIPHER_SUITE_TKIP:
++		key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
++		cipher = SSV_CIPHER_TKIP;
++		break;
++	case WLAN_CIPHER_SUITE_CCMP:
++		key->flags |=
++		    (IEEE80211_KEY_FLAG_SW_MGMT_TX |
++		     IEEE80211_KEY_FLAG_RX_MGMT);
++		cipher = SSV_CIPHER_CCMP;
++		break;
++	default:
++		cipher = SSV_CIPHER_INVALID;
++		break;
++	}
++	return cipher;
++}
++int _set_key_wep(struct ssv_softc *sc, struct ssv_vif_priv_data *vif_priv,
++		 struct ssv_sta_priv_data *sta_priv, enum SSV_CIPHER_E cipher,
++		 struct ieee80211_key_conf *key)
++{
++	int ret = 0;
++	struct ssv_vif_info *vif_info = &sc->vif_info[vif_priv->vif_idx];
++	struct ssv6xxx_hw_sec *sram_key = &vif_info->sramKey;
++	sram_key->sta_key[0].pair_key_idx = key->keyidx;
++	sram_key->sta_key[0].group_key_idx = key->keyidx;
++	*(u16 *) & sram_key->sta_key[0].reserve[0] = key->keylen;
++	dev_dbg(sc->dev, "Set WEP %02X %02X %02X %02X %02X %02X %02X %02X... (%d %d)\n",
++	       key->key[0], key->key[1], key->key[2], key->key[3], key->key[4],
++	       key->key[5], key->key[6], key->key[7], key->keyidx, key->keylen);
++	if (key->keyidx == 0) {
++		memcpy(sram_key->sta_key[0].pair.key, key->key, key->keylen);
++	} else {
++		memcpy(sram_key->group_key[key->keyidx - 1].key, key->key,
++		       key->keylen);
++	}
++	if (sc->sh->cfg.use_wpa2_only) {
++		dev_warn(sc->dev, "WEP: use WPA2 HW security mode only.\n");
++	}
++	if ((sc->sh->cfg.use_wpa2_only == 0)
++	    && vif_priv->vif_idx == 0) {
++		vif_priv->has_hw_decrypt = true;
++		vif_priv->has_hw_encrypt = true;
++		vif_priv->need_sw_decrypt = false;
++		vif_priv->need_sw_encrypt = false;
++		vif_priv->use_mac80211_decrypt = false;
++		ssv6200_hw_set_pair_type(sc->sh, cipher);
++		ssv6200_hw_set_group_type(sc->sh, cipher);
++		hw_crypto_key_write_wep(sc->hw, key, cipher,
++					&sc->vif_info[vif_priv->vif_idx]);
++	} else {
++		vif_priv->has_hw_decrypt = false;
++		vif_priv->has_hw_encrypt = false;
++		vif_priv->need_sw_decrypt = false;
++		vif_priv->need_sw_encrypt = false;
++		vif_priv->use_mac80211_decrypt = true;
++		ssv6xxx_foreach_vif_sta(sc, vif_info, _set_wep_sw_crypto_key,
++					NULL);
++		ret = -EOPNOTSUPP;
++	}
++	vif_priv->pair_cipher = vif_priv->group_cipher = cipher;
++	vif_priv->is_security_valid = true;
++	return ret;
++}
++
++static int _set_pairwise_key_tkip_ccmp(struct ssv_softc *sc,
++				       struct ssv_vif_priv_data *vif_priv,
++				       struct ssv_sta_priv_data *sta_priv,
++				       enum SSV_CIPHER_E cipher,
++				       struct ieee80211_key_conf *key)
++{
++	int ret = 0;
++	const char *cipher_name = (cipher == SSV_CIPHER_CCMP) ? "CCMP" : "TKIP";
++	struct ssv_vif_info *vif_info = &sc->vif_info[vif_priv->vif_idx];
++	bool tdls_link = false, tdls_use_sw_cipher = false, tkip_use_sw_cipher =
++	    false;
++	bool use_non_ccmp = false;
++	int another_vif_idx = ((vif_priv->vif_idx + 1) % 2);
++	struct ssv_vif_priv_data *another_vif_priv =
++	    (struct ssv_vif_priv_data *)sc->vif_info[another_vif_idx].vif_priv;
++	if (sta_priv == NULL) {
++		dev_err(sc->dev,
++			"Setting pairwise TKIP/CCMP key to NULL STA.\n");
++		return -EOPNOTSUPP;
++	}
++	if (sc->sh->cfg.use_wpa2_only) {
++		dev_warn(sc->dev, "Pairwise TKIP/CCMP: use WPA2 HW security mode only.\n");
++	}
++	if (vif_info->if_type == NL80211_IFTYPE_STATION) {
++		struct ssv_sta_priv_data *first_sta_priv =
++		    list_first_entry(&vif_priv->sta_list,
++				     struct ssv_sta_priv_data, list);
++		if (first_sta_priv->sta_idx != sta_priv->sta_idx) {
++			tdls_link = true;
++		}
++		dev_dbg(sc->dev, "first sta idx %d, current sta idx %d\n",
++		       first_sta_priv->sta_idx, sta_priv->sta_idx);
++	}
++	if ((tdls_link) && (vif_priv->pair_cipher != SSV_CIPHER_CCMP)
++	    && (sc->sh->cfg.use_wpa2_only == false)) {
++		tdls_use_sw_cipher = true;
++	}
++	if (another_vif_priv != NULL) {
++		if ((another_vif_priv->pair_cipher != SSV_CIPHER_CCMP)
++		    && (another_vif_priv->pair_cipher != SSV_CIPHER_NONE)) {
++			use_non_ccmp = true;
++			dev_dbg(sc->dev, "another vif use none ccmp\n");
++		}
++	}
++	if ((((tdls_link) && (vif_priv->pair_cipher != SSV_CIPHER_CCMP))
++	     || (use_non_ccmp))
++	    && (sc->sh->cfg.use_wpa2_only == 1) && (cipher == SSV_CIPHER_CCMP)) {
++		u32 val;
++		SMAC_REG_READ(sc->sh, ADR_RX_FLOW_DATA, &val);
++		if (((val >> 4) & 0xF) != M_ENG_CPU) {
++			SMAC_REG_WRITE(sc->sh, ADR_RX_FLOW_DATA,
++				       ((val & 0xf) | (M_ENG_CPU << 4)
++					| (val & 0xfffffff0) << 4));
++			dev_dbg(sc->dev,
++				"orginal Rx_Flow %x , modified flow %x \n", val,
++				((val & 0xf) | (M_ENG_CPU << 4) |
++				 (val & 0xfffffff0) << 4));
++		}
++	}
++	if ((cipher == SSV_CIPHER_TKIP) && (sc->sh->cfg.use_wpa2_only == 1)) {
++		tkip_use_sw_cipher = true;
++	}
++	if (tkip_use_sw_cipher == true)
++		dev_info(sc->dev, "Using software TKIP cipher\n");
++	if ((((vif_priv->vif_idx == 0) && (tdls_use_sw_cipher == false)
++	      && (tkip_use_sw_cipher == false)))
++	    || ((cipher == SSV_CIPHER_CCMP)
++		&& (sc->sh->cfg.use_wpa2_only == 1))) {
++		sta_priv->has_hw_decrypt = true;
++		sta_priv->need_sw_decrypt = false;
++		if ((cipher == SSV_CIPHER_TKIP)
++		    || ((!(sc->sh->cfg.hw_caps & SSV6200_HW_CAP_AMPDU_TX) ||
++			 (sta_priv->sta_info->sta->deflink.ht_cap.ht_supported ==
++			  false))
++			&& (vif_priv->force_sw_encrypt == false))) {
++			dev_dbg(sc->dev,
++				"STA %d uses HW encrypter for pairwise.\n",
++				sta_priv->sta_idx);
++			sta_priv->has_hw_encrypt = true;
++			sta_priv->need_sw_encrypt = false;
++			sta_priv->use_mac80211_decrypt = false;
++			ret = 0;
++		} else {
++			sta_priv->has_hw_encrypt = false;
++			sta_priv->need_sw_encrypt = false;
++			sta_priv->use_mac80211_decrypt = true;
++			ret = -EOPNOTSUPP;
++		}
++	} else {
++		sta_priv->has_hw_encrypt = false;
++		sta_priv->has_hw_decrypt = false;
++		dev_err(sc->dev, "STA %d MAC80211's %s cipher.\n",
++			sta_priv->sta_idx, cipher_name);
++		sta_priv->need_sw_encrypt = false;
++		sta_priv->need_sw_decrypt = false;
++		sta_priv->use_mac80211_decrypt = true;
++		ret = -EOPNOTSUPP;
++	}
++	if (sta_priv->has_hw_encrypt || sta_priv->has_hw_decrypt) {
++		ssv6200_hw_set_pair_type(sc->sh, cipher);
++		_write_pairwise_key_to_hw(sc, key->keyidx, cipher,
++					  key->key, key->keylen, key,
++					  vif_priv, sta_priv);
++	}
++	if ((vif_priv->has_hw_encrypt || vif_priv->has_hw_decrypt)
++	    && (vif_priv->group_key_idx > 0)) {
++		_set_aes_tkip_hw_crypto_group_key(sc,
++						  &sc->vif_info[vif_priv->
++								vif_idx],
++						  sta_priv->sta_info,
++						  &vif_priv->group_key_idx);
++	}
++	return ret;
++}
++
++static int _set_group_key_tkip_ccmp(struct ssv_softc *sc,
++				    struct ssv_vif_priv_data *vif_priv,
++				    struct ssv_sta_priv_data *sta_priv,
++				    enum SSV_CIPHER_E cipher,
++				    struct ieee80211_key_conf *key)
++{
++	int ret = 0;
++	const char *cipher_name = (cipher == SSV_CIPHER_CCMP) ? "CCMP" : "TKIP";
++	bool tkip_use_sw_cipher = false;
++	vif_priv->group_cipher = cipher;
++	if (sc->sh->cfg.use_wpa2_only) {
++		dev_warn(sc->dev, "Group TKIP/CCMP: use WPA2 HW security mode only.\n");
++	}
++	if ((cipher == SSV_CIPHER_TKIP) && (sc->sh->cfg.use_wpa2_only == 1)) {
++		tkip_use_sw_cipher = true;
++	}
++	if (((vif_priv->vif_idx == 0) && (tkip_use_sw_cipher == false))
++	    || ((cipher == SSV_CIPHER_CCMP)
++		&& (sc->sh->cfg.use_wpa2_only == 1))) {
++		dev_dbg(sc->dev, "VIF %d uses HW %s cipher for group.\n",
++			vif_priv->vif_idx, cipher_name);
++#ifdef USE_MAC80211_DECRYPT_BROADCAST
++		vif_priv->has_hw_decrypt = false;
++		ret = -EOPNOTSUPP;
++#else
++		vif_priv->has_hw_decrypt = true;
++#endif
++		vif_priv->has_hw_encrypt = true;
++		vif_priv->need_sw_decrypt = false;
++		vif_priv->need_sw_encrypt = false;
++		vif_priv->use_mac80211_decrypt = false;
++	} else {
++		vif_priv->has_hw_decrypt = false;
++		vif_priv->has_hw_encrypt = false;
++		dev_err(sc->dev, "VIF %d uses MAC80211's %s cipher.\n",
++			vif_priv->vif_idx, cipher_name);
++		vif_priv->need_sw_encrypt = false;
++		vif_priv->need_sw_encrypt = false;
++		vif_priv->use_mac80211_decrypt = true;
++		ret = -EOPNOTSUPP;
++	}
++	if (vif_priv->has_hw_encrypt || vif_priv->has_hw_decrypt) {
++#ifdef USE_MAC80211_DECRYPT_BROADCAST
++		ssv6200_hw_set_group_type(sc->sh, ME_NONE);
++#else
++		ssv6200_hw_set_group_type(sc->sh, cipher);
++#endif
++		key->hw_key_idx = key->keyidx;
++		_write_group_key_to_hw(sc, key->keyidx, cipher,
++				       key->key, key->keylen, key,
++				       vif_priv, sta_priv);
++	}
++	vif_priv->is_security_valid = true;
++	{
++		int another_vif_idx = ((vif_priv->vif_idx + 1) % 2);
++		struct ssv_vif_priv_data *another_vif_priv =
++		    (struct ssv_vif_priv_data *)sc->vif_info[another_vif_idx].
++		    vif_priv;
++		if (another_vif_priv != NULL) {
++			if (((SSV6XXX_USE_SW_DECRYPT(vif_priv)
++			      && SSV6XXX_USE_HW_DECRYPT(another_vif_priv)))
++			    || ((SSV6XXX_USE_HW_DECRYPT(vif_priv)
++				 &&
++				 (SSV6XXX_USE_SW_DECRYPT(another_vif_priv))))) {
++				u32 val;
++				SMAC_REG_READ(sc->sh, ADR_RX_FLOW_DATA, &val);
++				if (((val >> 4) & 0xF) != M_ENG_CPU) {
++					SMAC_REG_WRITE(sc->sh, ADR_RX_FLOW_DATA,
++						       ((val & 0xf) |
++							(M_ENG_CPU << 4)
++							| (val & 0xfffffff0) <<
++							4));
++					dev_dbg(sc->dev,
++						"orginal Rx_Flow %x , modified flow %x \n",
++						val,
++						((val & 0xf) | (M_ENG_CPU << 4)
++						 | (val & 0xfffffff0) << 4));
++				} else {
++					dev_dbg(sc->dev, " doesn't need to change rx flow\n");
++				}
++			}
++		}
++	}
++	return ret;
++}
++
++static int _set_key_tkip_ccmp(struct ssv_softc *sc,
++			      struct ssv_vif_priv_data *vif_priv,
++			      struct ssv_sta_priv_data *sta_priv,
++			      enum SSV_CIPHER_E cipher,
++			      struct ieee80211_key_conf *key)
++{
++	if (key->keyidx == 0)
++		return _set_pairwise_key_tkip_ccmp(sc, vif_priv, sta_priv,
++						   cipher, key);
++	else
++		return _set_group_key_tkip_ccmp(sc, vif_priv, sta_priv, cipher,
++						key);
++}
++
++static int ssv6200_set_key(struct ieee80211_hw *hw,
++			   enum set_key_cmd cmd,
++			   struct ieee80211_vif *vif,
++			   struct ieee80211_sta *sta,
++			   struct ieee80211_key_conf *key)
++{
++	struct ssv_softc *sc = hw->priv;
++	int ret = 0;
++	enum SSV_CIPHER_E cipher = SSV_CIPHER_NONE;
++	int sta_idx = (-1);
++	struct ssv_sta_info *sta_info = NULL;
++	struct ssv_sta_priv_data *sta_priv = NULL;
++	struct ssv_vif_priv_data *vif_priv =
++	    (struct ssv_vif_priv_data *)vif->drv_priv;
++	struct ssv_vif_info *vif_info = &sc->vif_info[vif_priv->vif_idx];
++	if (sta) {
++		sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
++		sta_idx = sta_priv->sta_idx;
++		sta_info = sta_priv->sta_info;
++	}
++	BUG_ON((cmd != SET_KEY) && (cmd != DISABLE_KEY));
++	if (!(sc->sh->cfg.hw_caps & SSV6200_HW_CAP_SECURITY)) {
++		dev_warn(sc->dev, "HW does not support security.\n");
++		return -EOPNOTSUPP;
++	}
++	if (sta_info && (sta_info->hw_wsid == (-1))) {
++		dev_warn(sc->dev,
++			 "Add STA without HW resource. Use MAC80211's solution.\n");
++		return -EOPNOTSUPP;
++	}
++	cipher = _prepare_key(key);
++	dev_dbg(sc->dev,
++		"Set key VIF %d VIF type %d STA %d algorithm = %d, key->keyidx = %d, cmd = %d\n",
++		vif_priv->vif_idx, vif->type, sta_idx, cipher, key->keyidx,
++		cmd);
++	if (cipher == SSV_CIPHER_INVALID) {
++		dev_warn(sc->dev, "Unsupported cipher type.\n");
++		return -EOPNOTSUPP;
++	}
++	mutex_lock(&sc->mutex);
++	switch (cmd) {
++	case SET_KEY:
++		{
++			switch (cipher) {
++			case SSV_CIPHER_WEP40:
++			case SSV_CIPHER_WEP104:
++				ret =
++				    _set_key_wep(sc, vif_priv, sta_priv, cipher,
++						 key);
++				break;
++			case SSV_CIPHER_TKIP:
++			case SSV_CIPHER_CCMP:
++				ret =
++				    _set_key_tkip_ccmp(sc, vif_priv, sta_priv,
++						       cipher, key);
++				break;
++			default:
++				break;
++			}
++			if (sta) {
++				struct ssv_sta_priv_data *first_sta_priv =
++				    list_first_entry(&vif_priv->sta_list,
++						     struct ssv_sta_priv_data,
++						     list);
++				if (first_sta_priv->sta_idx ==
++				    sta_priv->sta_idx) {
++					vif_priv->pair_cipher = cipher;
++				}
++				if (SSV6200_USE_HW_WSID(sta_idx)) {
++					if (SSV6XXX_USE_SW_DECRYPT(sta_priv)) {
++						u32 cipher_setting;
++						cipher_setting =
++						    ssv6200_hw_get_pair_type
++						    (sc->sh);
++						if (cipher_setting != ME_NONE) {
++							u32 val;
++							SMAC_REG_READ(sc->sh,
++								      ADR_RX_FLOW_DATA,
++								      &val);
++							if (((val >> 4) & 0xF)
++							    != M_ENG_CPU) {
++								SMAC_REG_WRITE
++								    (sc->sh,
++								     ADR_RX_FLOW_DATA,
++								     ((val &
++								       0xf) |
++								      (M_ENG_CPU
++								       << 4)
++								      | (val &
++									 0xfffffff0)
++								      << 4));
++								dev_dbg(sc->dev,
++									"orginal Rx_Flow %x , modified flow %x \n",
++									val,
++									((val &
++									  0xf) |
++									 (M_ENG_CPU
++									  << 4)
++									 | (val
++									    &
++									    0xfffffff0)
++									 << 4));
++							} else {
++								dev_dbg(sc->dev, " doesn't need to change rx flow\n");
++							}
++						}
++					}
++					if (sta_priv->has_hw_decrypt) {
++						hw_update_watch_wsid(sc, sta,
++								     sta_info,
++								     sta_idx,
++								     SSV6XXX_WSID_SEC_HW,
++								     SSV6XXX_WSID_OPS_HWWSID_PAIRWISE_SET_TYPE);
++						dev_info(sc->dev, "set hw wsid %d cipher mode to HW cipher for pairwise key\n", sta_idx);
++					}
++				}
++			} else {
++				if (vif_info->if_type == NL80211_IFTYPE_STATION) {
++					struct ssv_sta_priv_data *first_sta_priv
++					    =
++					    list_first_entry(&vif_priv->
++							     sta_list,
++							     struct
++							     ssv_sta_priv_data,
++							     list);
++					if (SSV6200_USE_HW_WSID
++					    (first_sta_priv->sta_idx)) {
++						if (vif_priv->has_hw_decrypt) {
++							hw_update_watch_wsid(sc,
++									     sta,
++									     sta_info,
++									     first_sta_priv->
++									     sta_idx,
++									     SSV6XXX_WSID_SEC_HW,
++									     SSV6XXX_WSID_OPS_HWWSID_GROUP_SET_TYPE);
++							dev_info(sc->dev, "set hw wsid %d cipher mode to HW cipher for group key\n", first_sta_priv->sta_idx);
++						}
++					}
++				}
++			}
++		}
++		break;
++	case DISABLE_KEY:
++		{
++			int another_vif_idx = ((vif_priv->vif_idx + 1) % 2);
++			struct ssv_vif_priv_data *another_vif_priv =
++			    (struct ssv_vif_priv_data *)sc->
++			    vif_info[another_vif_idx].vif_priv;
++			if (another_vif_priv != NULL) {
++				struct ssv_vif_info *vif_info =
++				    &sc->vif_info[vif_priv->vif_idx];
++				if (vif_info->if_type != NL80211_IFTYPE_AP) {
++					if ((SSV6XXX_USE_SW_DECRYPT(vif_priv)
++					     &&
++					     SSV6XXX_USE_HW_DECRYPT
++					     (another_vif_priv))
++					    ||
++					    (SSV6XXX_USE_SW_DECRYPT
++					     (another_vif_priv)
++					     &&
++					     SSV6XXX_USE_HW_DECRYPT(vif_priv)))
++					{
++						SMAC_REG_WRITE(sc->sh,
++							       ADR_RX_FLOW_DATA,
++							       M_ENG_MACRX |
++							       (M_ENG_ENCRYPT_SEC
++								<< 4) |
++							       (M_ENG_HWHCI <<
++								8));
++						dev_dbg(sc->dev, "redirect Rx flow for disconnect\n");
++					}
++				} else {
++					if (sta == NULL) {
++						if (SSV6XXX_USE_SW_DECRYPT
++						    (another_vif_priv)
++						    &&
++						    SSV6XXX_USE_HW_DECRYPT
++						    (vif_priv)) {
++							SMAC_REG_WRITE(sc->sh,
++								       ADR_RX_FLOW_DATA,
++								       M_ENG_MACRX
++								       |
++								       (M_ENG_ENCRYPT_SEC
++									<< 4) |
++								       (M_ENG_HWHCI
++									<< 8));
++							dev_dbg(sc->dev, "redirect Rx flow for disconnect\n");
++						}
++					}
++				}
++			}
++			if (sta == NULL) {
++				vif_priv->group_cipher = ME_NONE;
++				if ((another_vif_priv == NULL)
++				    || ((another_vif_priv != NULL)
++					&&
++					(!SSV6XXX_USE_HW_DECRYPT
++					 (another_vif_priv)))) {
++					ssv6200_hw_set_group_type(sc->sh,
++								  ME_NONE);
++				}
++			} else {
++				struct ssv_vif_info *vif_info =
++				    &sc->vif_info[vif_priv->vif_idx];
++				if ((vif_info->if_type != NL80211_IFTYPE_AP)
++				    && (another_vif_priv == NULL)) {
++					struct ssv_sta_priv_data *first_sta_priv
++					    =
++					    list_first_entry(&vif_priv->
++							     sta_list,
++							     struct
++							     ssv_sta_priv_data,
++							     list);
++					if (sta_priv == first_sta_priv) {
++						ssv6200_hw_set_pair_type(sc->sh,
++									 ME_NONE);
++					}
++				}
++				vif_priv->pair_cipher = ME_NONE;
++			}
++			if ((cipher == ME_TKIP) || (cipher == ME_CCMP)) {
++				dev_dbg(sc->dev, "Clear key %d VIF %d, STA %d\n",
++				       key->keyidx, (vif != NULL),
++				       (sta != NULL));
++				hw_crypto_key_clear(hw, key->keyidx, key,
++						    vif_priv, sta_priv);
++			}
++			{
++				if ((key->keyidx == 0) && (sta_priv != NULL)) {
++					sta_priv->has_hw_decrypt = false;
++					sta_priv->has_hw_encrypt = false;
++					sta_priv->need_sw_encrypt = false;
++					sta_priv->use_mac80211_decrypt = false;
++				}
++				if ((vif_priv->is_security_valid)
++				    && (key->keyidx != 0)) {
++					vif_priv->is_security_valid = false;
++				}
++			}
++			ret = 0;
++		}
++		break;
++	default:
++		ret = -EINVAL;
++	}
++	mutex_unlock(&sc->mutex);
++	if (sta_priv != NULL) {
++		dev_info(sc->dev, "station mode: hardware encrypt:%d/decrypt:%d, software encrypt:%d/decrypt:%d\n",
++		       (sta_priv->has_hw_encrypt == true),
++		       (sta_priv->has_hw_decrypt == true),
++		       (sta_priv->need_sw_encrypt == true),
++		       (sta_priv->need_sw_decrypt == true));
++	}
++	if (vif_priv) {
++		dev_info
++		    (sc->dev, "vif mode: hardware encrypt:%d/decrypt:%d, software encrypt:%d/decrypt:%d, mac80211 decrypt: %d, valid:%d\n",
++		     (vif_priv->has_hw_encrypt == true),
++		     (vif_priv->has_hw_decrypt == true),
++		     (vif_priv->need_sw_encrypt == true),
++		     (vif_priv->need_sw_decrypt == true),
++		     (vif_priv->use_mac80211_decrypt == true),
++		     (vif_priv->is_security_valid == true));
++	}
++	if (vif_priv->force_sw_encrypt
++	    || (sta_info && (sta_info->hw_wsid != 1)
++		&& (sta_info->hw_wsid != 0))) {
++		if (vif_priv->force_sw_encrypt == false)
++			vif_priv->force_sw_encrypt = true;
++		ret = -EOPNOTSUPP;
++	}
++	dev_dbg(sc->dev, "SET KEY %d\n", ret);
++	return ret;
++}
++
++u32 _process_tx_done(struct ssv_softc *sc)
++{
++	struct ieee80211_tx_info *tx_info;
++	struct sk_buff *skb;
++	while ((skb = skb_dequeue(&sc->tx_done_q))) {
++		struct ssv6200_tx_desc *tx_desc;
++		tx_info = IEEE80211_SKB_CB(skb);
++		tx_desc = (struct ssv6200_tx_desc *)skb->data;
++		if (tx_desc->c_type > M2_TXREQ) {
++			ssv_skb_free(skb);
++			dev_dbg(sc->dev, "free cmd skb!\n");
++			continue;
++		}
++		if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
++			ssv6200_ampdu_release_skb(skb, sc->hw);
++			continue;
++		}
++		skb_pull(skb, SSV6XXX_TX_DESC_LEN);
++		ieee80211_tx_info_clear_status(tx_info);
++		tx_info->flags |= IEEE80211_TX_STAT_ACK;
++		tx_info->status.ack_signal = 100;
++#ifdef REPORT_TX_DONE_IN_IRQ
++		ieee80211_tx_status_irqsafe(sc->hw, skb);
++#else
++		ieee80211_tx_status_skb(sc->hw, skb);
++		if (skb_queue_len(&sc->rx_skb_q))
++			break;
++#endif
++	}
++	return skb_queue_len(&sc->tx_done_q);
++}
++
++#ifdef REPORT_TX_DONE_IN_IRQ
++void ssv6xxx_tx_cb(struct sk_buff_head *skb_head, void *args)
++{
++	struct ssv_softc *sc = (struct ssv_softc *)args;
++	_process_tx_done *(sc);
++}
++#else
++void ssv6xxx_tx_cb(struct sk_buff_head *skb_head, void *args)
++{
++	struct ssv_softc *sc = (struct ssv_softc *)args;
++	struct sk_buff *skb;
++	while ((skb = skb_dequeue(skb_head))) {
++		struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
++		struct ssv6200_tx_desc *tx_desc;
++		tx_desc = (struct ssv6200_tx_desc *)skb->data;
++		if (tx_desc->c_type > M2_TXREQ) {
++			ssv_skb_free(skb);
++			dev_dbg(sc->dev, "free cmd skb!\n");
++			continue;
++		}
++		if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
++			ssv6xxx_ampdu_sent(sc->hw, skb);
++		skb_queue_tail(&sc->tx_done_q, skb);
++	}
++	wake_up_interruptible(&sc->rx_wait_q);
++}
++#endif
++void ssv6xxx_tx_rate_update(struct sk_buff *skb, void *args)
++{
++	struct ieee80211_hdr *hdr;
++	struct ssv_softc *sc = args;
++	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
++	struct ssv6200_tx_desc *tx_desc;
++	struct ssv_rate_info ssv_rate;
++	u32 nav = 0;
++	int ret = 0;
++	tx_desc = (struct ssv6200_tx_desc *)skb->data;
++	if (tx_desc->c_type > M2_TXREQ)
++		return;
++	if (!(info->flags & IEEE80211_TX_CTL_AMPDU)) {
++		hdr = (struct ieee80211_hdr *)(skb->data + SSV6XXX_TX_DESC_LEN);
++		if ((ieee80211_is_data_qos(hdr->frame_control)
++		     || ieee80211_is_data(hdr->frame_control))
++		    && (tx_desc->wsid < SSV_RC_MAX_HARDWARE_SUPPORT)) {
++			ret =
++			    ssv6xxx_rc_hw_rate_update_check(skb, sc,
++							    tx_desc->
++							    do_rts_cts);
++			if (ret & RC_FIRMWARE_REPORT_FLAG) {
++				{
++					tx_desc->RSVD_0 = SSV6XXX_RC_REPORT;
++					tx_desc->tx_report = 1;
++				}
++				ret &= 0xf;
++			}
++			if (ret) {
++				ssv6xxx_rc_hw_rate_idx(sc, info, &ssv_rate);
++				tx_desc->crate_idx = ssv_rate.crate_hw_idx;
++				tx_desc->drate_idx = ssv_rate.drate_hw_idx;
++				nav =
++				    ssv6xxx_set_frame_duration(info, &ssv_rate,
++							       skb->len +
++							       FCS_LEN, tx_desc,
++							       NULL, NULL);
++				if (tx_desc->tx_burst == 0) {
++					if (tx_desc->ack_policy != 0x01)
++						hdr->duration_id = nav;
++				}
++			}
++		}
++	} else {
++	}
++	return;
++}
++
++void ssv6xxx_update_txinfo(struct ssv_softc *sc, struct sk_buff *skb)
++{
++	struct ieee80211_hdr *hdr;
++	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
++	struct ieee80211_sta *sta;
++	struct ssv_sta_info *sta_info = NULL;
++	struct ssv_sta_priv_data *ssv_sta_priv = NULL;
++	struct ssv_vif_priv_data *vif_priv =
++	    (struct ssv_vif_priv_data *)info->control.vif->drv_priv;
++	struct ssv6200_tx_desc *tx_desc = (struct ssv6200_tx_desc *)skb->data;
++	struct ieee80211_tx_rate *tx_drate;
++	struct ssv_rate_info ssv_rate;
++	int ac, hw_txqid;
++	u32 nav = 0;
++	if (info->flags & IEEE80211_TX_CTL_AMPDU) {
++		struct ampdu_hdr_st *ampdu_hdr =
++		    (struct ampdu_hdr_st *)skb->head;
++		sta = ampdu_hdr->ampdu_tid->sta;
++		hdr =
++		    (struct ieee80211_hdr *)(skb->data + TXPB_OFFSET +
++					     AMPDU_DELIMITER_LEN);
++	} else {
++		struct SKB_info_st *skb_info = (struct SKB_info_st *)skb->head;
++		sta = skb_info->sta;
++		hdr = (struct ieee80211_hdr *)(skb->data + TXPB_OFFSET);
++	}
++	if (sta) {
++		ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
++		sta_info = ssv_sta_priv->sta_info;
++	}
++	if ((!sc->bq4_dtim) &&
++	    (ieee80211_is_mgmt(hdr->frame_control) ||
++	     ieee80211_is_nullfunc(hdr->frame_control) ||
++	     ieee80211_is_qos_nullfunc(hdr->frame_control))) {
++		ac = 4;
++		hw_txqid = 4;
++	} else if ((sc->bq4_dtim) &&
++		   info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
++		hw_txqid = 4;
++		ac = 4;
++	} else {
++		ac = skb_get_queue_mapping(skb);
++		hw_txqid = sc->tx.hw_txqid[ac];
++	}
++	tx_drate = &info->control.rates[0];
++	ssv6xxx_rc_hw_rate_idx(sc, info, &ssv_rate);
++	tx_desc->len = skb->len;
++	tx_desc->c_type = M2_TXREQ;
++	tx_desc->f80211 = 1;
++	tx_desc->qos = (ieee80211_is_data_qos(hdr->frame_control)) ? 1 : 0;
++	if (tx_drate->flags & IEEE80211_TX_RC_MCS) {
++		if (ieee80211_is_mgmt(hdr->frame_control) &&
++		    ieee80211_has_order(hdr->frame_control))
++			tx_desc->ht = 1;
++	}
++	tx_desc->use_4addr = (ieee80211_has_a4(hdr->frame_control)) ? 1 : 0;
++	tx_desc->more_data =
++	    (ieee80211_has_morefrags(hdr->frame_control)) ? 1 : 0;
++	tx_desc->stype_b5b4 = (cpu_to_le16(hdr->frame_control) >> 4) & 0x3;
++	tx_desc->frag = (tx_desc->more_data || (hdr->seq_ctrl & 0xf)) ? 1 : 0;
++	tx_desc->unicast = (is_multicast_ether_addr(hdr->addr1)) ? 0 : 1;
++	tx_desc->tx_burst = (tx_desc->frag) ? 1 : 0;
++	tx_desc->wsid = (!sta_info
++			 || (sta_info->hw_wsid < 0)) ? 0x0F : sta_info->hw_wsid;
++	tx_desc->txq_idx = hw_txqid;
++	tx_desc->hdr_offset = TXPB_OFFSET;
++	tx_desc->hdr_len = ssv6xxx_frame_hdrlen(hdr, tx_desc->ht);
++	tx_desc->payload_offset = tx_desc->hdr_offset + tx_desc->hdr_len;
++	if (info->control.use_rts)
++		tx_desc->do_rts_cts = IEEE80211_TX_RC_USE_RTS_CTS;
++	else if (info->control.use_cts_prot)
++		tx_desc->do_rts_cts = IEEE80211_TX_RC_USE_CTS_PROTECT;
++	if (tx_desc->do_rts_cts == IEEE80211_TX_RC_USE_CTS_PROTECT)
++		tx_desc->do_rts_cts = IEEE80211_TX_RC_USE_RTS_CTS;
++	if (tx_desc->do_rts_cts == IEEE80211_TX_RC_USE_CTS_PROTECT) {
++		tx_desc->crate_idx = 0;
++	} else
++		tx_desc->crate_idx = ssv_rate.crate_hw_idx;
++	tx_desc->drate_idx = ssv_rate.drate_hw_idx;
++	if (tx_desc->unicast == 0)
++		tx_desc->ack_policy = 1;
++	else if (tx_desc->qos == 1)
++		tx_desc->ack_policy = (*ieee80211_get_qos_ctl(hdr) & 0x60) >> 5;
++	else if (ieee80211_is_ctl(hdr->frame_control))
++		tx_desc->ack_policy = 1;
++	tx_desc->security = 0;
++	tx_desc->fCmdIdx = 0;
++	tx_desc->fCmd = (hw_txqid + M_ENG_TX_EDCA0);
++	if (info->flags & IEEE80211_TX_CTL_AMPDU) {
++#ifdef AMPDU_HAS_LEADING_FRAME
++		tx_desc->fCmd = (tx_desc->fCmd << 4) | M_ENG_CPU;
++#else
++		tx_desc->RSVD_1 = 1;
++#endif
++		tx_desc->aggregation = 1;
++		tx_desc->ack_policy = 0x01;
++		if ((tx_desc->do_rts_cts == 0)
++		    && ((sc->hw->wiphy->rts_threshold == (-1))
++			|| ((skb->len - sc->sh->tx_desc_len) >
++			    sc->hw->wiphy->rts_threshold))) {
++			tx_drate->flags |= IEEE80211_TX_RC_USE_RTS_CTS;
++			tx_desc->do_rts_cts = 1;
++		}
++	}
++	if (ieee80211_has_protected(hdr->frame_control)
++	    && (ieee80211_is_data_qos(hdr->frame_control)
++		|| ieee80211_is_data(hdr->frame_control))) {
++		if ((tx_desc->unicast && ssv_sta_priv
++		     && ssv_sta_priv->has_hw_encrypt)
++		    || (!tx_desc->unicast && vif_priv
++			&& vif_priv->has_hw_encrypt)) {
++			if (!tx_desc->unicast
++			    && !list_empty(&vif_priv->sta_list)) {
++				struct ssv_sta_priv_data *one_sta_priv;
++				int hw_wsid;
++				one_sta_priv =
++				    list_first_entry(&vif_priv->sta_list,
++						     struct ssv_sta_priv_data,
++						     list);
++				hw_wsid = one_sta_priv->sta_info->hw_wsid;
++				if (hw_wsid != (-1)) {
++					tx_desc->wsid = hw_wsid;
++				}
++			}
++			tx_desc->fCmd = (tx_desc->fCmd << 4) | M_ENG_ENCRYPT;
++		} else if (ssv_sta_priv->need_sw_encrypt) {
++		} else {
++		}
++	} else {
++	}
++	tx_desc->fCmd = (tx_desc->fCmd << 4) | M_ENG_HWHCI;
++	if (tx_desc->aggregation == 1) {
++		struct ampdu_hdr_st *ampdu_hdr =
++		    (struct ampdu_hdr_st *)skb->head;
++		memcpy(&tx_desc->rc_params[0], ampdu_hdr->rates,
++		       sizeof(tx_desc->rc_params));
++		nav =
++		    ssv6xxx_set_frame_duration(info, &ssv_rate,
++					       (skb->len + FCS_LEN), tx_desc,
++					       &tx_desc->rc_params[0], sc);
++#ifdef FW_RC_RETRY_DEBUG
++		{
++			dev_dbg
++			    (sc->dev, "[FW_RC]:param[0]: drate =%d, count =%d, crate=%d, dl_length =%d, frame_consume_time =%d, rts_cts_nav=%d\n",
++			     tx_desc->rc_params[0].drate,
++			     tx_desc->rc_params[0].count,
++			     tx_desc->rc_params[0].crate,
++			     tx_desc->rc_params[0].dl_length,
++			     tx_desc->rc_params[0].frame_consume_time,
++			     tx_desc->rc_params[0].rts_cts_nav);
++			dev_dbg
++			    (sc->dev, "[FW_RC]:param[1]: drate =%d, count =%d, crate=%d, dl_length =%d, frame_consume_time =%d, rts_cts_nav=%d\n",
++			     tx_desc->rc_params[1].drate,
++			     tx_desc->rc_params[1].count,
++			     tx_desc->rc_params[1].crate,
++			     tx_desc->rc_params[1].dl_length,
++			     tx_desc->rc_params[1].frame_consume_time,
++			     tx_desc->rc_params[1].rts_cts_nav);
++			dev_dbg
++			    (sc->dev, "[FW_RC]:param[2]: drate =%d, count =%d, crate=%d, dl_length =%d, frame_consume_time =%d, rts_cts_nav=%d\n",
++			     tx_desc->rc_params[2].drate,
++			     tx_desc->rc_params[2].count,
++			     tx_desc->rc_params[2].crate,
++			     tx_desc->rc_params[2].dl_length,
++			     tx_desc->rc_params[2].frame_consume_time,
++			     tx_desc->rc_params[2].rts_cts_nav);
++		}
++#endif
++	} else {
++		nav =
++		    ssv6xxx_set_frame_duration(info, &ssv_rate,
++					       (skb->len + FCS_LEN), tx_desc,
++					       NULL, NULL);
++	}
++	if ((tx_desc->aggregation == 0)) {
++		if (tx_desc->tx_burst == 0) {
++			if (tx_desc->ack_policy != 0x01)
++				hdr->duration_id = nav;
++		} else {
++		}
++	}
++}
++
++void ssv6xxx_add_txinfo(struct ssv_softc *sc, struct sk_buff *skb)
++{
++	struct ssv6200_tx_desc *tx_desc;
++	skb_push(skb, sc->sh->tx_desc_len);
++	tx_desc = (struct ssv6200_tx_desc *)skb->data;
++	memset((void *)tx_desc, 0, sc->sh->tx_desc_len);
++	ssv6xxx_update_txinfo(sc, skb);
++}
++
++int ssv6xxx_get_real_index(struct ssv_softc *sc, struct sk_buff *skb)
++{
++	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
++	struct ieee80211_tx_rate *tx_drate;
++	struct ssv_rate_info ssv_rate;
++	tx_drate = &info->control.rates[0];
++	ssv6xxx_rc_hw_rate_idx(sc, info, &ssv_rate);
++	return ssv_rate.drate_hw_idx;
++}
++
++static void _ssv6xxx_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
++{
++	struct ssv_softc *sc = hw->priv;
++	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
++	struct ieee80211_vif *vif = info->control.vif;
++	struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
++	struct ssv6200_tx_desc *tx_desc;
++	int ret;
++	unsigned long flags;
++	bool send_hci = false;
++	do {
++		if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
++			if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
++				sc->tx.seq_no += 0x10;
++			hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
++			hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
++		}
++		if (info->flags & IEEE80211_TX_CTL_AMPDU) {
++			if (ssv6xxx_get_real_index(sc, skb) <
++			    SSV62XX_RATE_MCS_INDEX) {
++				info->flags &= (~IEEE80211_TX_CTL_AMPDU);
++				goto tx_mpdu;
++			}
++			if (ssv6200_ampdu_tx_handler(hw, skb)) {
++				break;
++			} else {
++				info->flags &= (~IEEE80211_TX_CTL_AMPDU);
++			}
++		}
++ tx_mpdu:
++		ssv6xxx_add_txinfo(sc, skb);
++		if (vif &&
++		    vif->type == NL80211_IFTYPE_AP &&
++		    (sc->bq4_dtim) &&
++		    info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
++			struct ssv_vif_priv_data *priv_vif =
++			    (struct ssv_vif_priv_data *)vif->drv_priv;
++			u8 buffered = 0;
++			spin_lock_irqsave(&sc->ps_state_lock, flags);
++			if (priv_vif->sta_asleep_mask) {
++				buffered =
++				    ssv6200_bcast_enqueue(sc, &sc->bcast_txq,
++							  skb);
++				if (1 == buffered) {
++					dev_dbg(sc->dev, "ssv6200_tx:ssv6200_bcast_start\n");
++					ssv6200_bcast_start(sc);
++				}
++			}
++			spin_unlock_irqrestore(&sc->ps_state_lock, flags);
++			if (buffered)
++				break;
++		}
++		if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
++			struct ssv_vif_priv_data *vif_priv =
++			    (struct ssv_vif_priv_data *)vif->drv_priv;
++			dev_dbg(sc->dev, "vif[%d] sc->bq4_dtim[%d]\n",
++				vif_priv->vif_idx, sc->bq4_dtim);
++		}
++		tx_desc = (struct ssv6200_tx_desc *)skb->data;
++		ret = HCI_SEND(sc->sh, skb, tx_desc->txq_idx);
++		send_hci = true;
++	} while (0);
++	if ((skb_queue_len(&sc->tx_skb_q) < LOW_TX_Q_LEN)
++	    ) {
++		if (sc->tx.flow_ctrl_status != 0) {
++			int ac;
++			for (ac = 0; ac < sc->hw->queues; ac++) {
++				if ((sc->tx.flow_ctrl_status & BIT(ac)) == 0)
++					ieee80211_wake_queue(sc->hw, ac);
++			}
++		} else {
++			ieee80211_wake_queues(sc->hw);
++		}
++	}
++}
++
++static void ssv6200_tx(struct ieee80211_hw *hw,
++		       struct ieee80211_tx_control *control,
++		       struct sk_buff *skb)
++{
++	struct ssv_softc *sc = (struct ssv_softc *)hw->priv;
++	struct SKB_info_st *skb_info = (struct SKB_info_st *)skb->head;
++	skb_info->sta = control ? control->sta : NULL;
++#ifdef CONFIG_DEBUG_SKB_TIMESTAMP
++	skb_info->timestamp = ktime_get();
++#endif
++	skb_queue_tail(&sc->tx_skb_q, skb);
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	if (sc->max_tx_skb_q_len < skb_queue_len(&sc->tx_skb_q))
++		sc->max_tx_skb_q_len = skb_queue_len(&sc->tx_skb_q);
++#endif
++	wake_up_interruptible(&sc->tx_wait_q);
++	do {
++		if (skb_queue_len(&sc->tx_skb_q) >= MAX_TX_Q_LEN)
++			ieee80211_stop_queues(sc->hw);
++	} while (0);
++}
++
++int ssv6xxx_tx_task(void *data)
++{
++	struct ssv_softc *sc = (struct ssv_softc *)data;
++	u32 wait_period = SSV_AMPDU_timer_period / 2;
++	dev_info(sc->dev, "TX Task started\n");
++	while (!kthread_should_stop()) {
++		u32 before_timeout = (-1);
++		set_current_state(TASK_INTERRUPTIBLE);
++		before_timeout = wait_event_interruptible_timeout(sc->tx_wait_q,
++								  (skb_queue_len
++								   (&sc->
++								    tx_skb_q)
++								   ||
++								   kthread_should_stop
++								   ()
++								   || sc->
++								   tx_q_empty),
++								  msecs_to_jiffies
++								  (wait_period));
++		if (kthread_should_stop()) {
++			dev_dbg(sc->dev, "Quit TX task loop...\n");
++			break;
++		}
++		set_current_state(TASK_RUNNING);
++		do {
++			struct sk_buff *tx_skb = skb_dequeue(&sc->tx_skb_q);
++			if (tx_skb == NULL)
++				break;
++			_ssv6xxx_tx(sc->hw, tx_skb);
++		} while (1);
++#ifdef CONFIG_DEBUG_SKB_TIMESTAMP
++		{
++			struct ssv_hw_txq *hw_txq = NULL;
++			struct ieee80211_tx_info *tx_info = NULL;
++			struct sk_buff *skb = NULL;
++			int txqid;
++			unsigned int timeout;
++			u32 status;
++			for (txqid = 0; txqid < SSV_HW_TXQ_NUM; txqid++) {
++				hw_txq = &ssv_dbg_ctrl_hci->hw_txq[txqid];
++				skb = skb_peek(&hw_txq->qhead);
++				if (skb != NULL) {
++					tx_info = IEEE80211_SKB_CB(skb);
++					if (tx_info->
++					    flags & IEEE80211_TX_CTL_AMPDU)
++						timeout =
++						    cal_duration_of_ampdu(skb,
++									  SKB_DURATION_STAGE_IN_HWQ);
++					else
++						timeout =
++						    cal_duration_of_mpdu(skb);
++					if (timeout > SKB_DURATION_TIMEOUT_MS) {
++						HCI_IRQ_STATUS(ssv_dbg_ctrl_hci,
++							       &status);
++						dev_dbg(sc->dev, "hci int_mask: %08x\n",
++						       ssv_dbg_ctrl_hci->
++						       int_mask);
++						dev_dbg(sc->dev, "sdio status: %08x\n",
++						       status);
++						dev_dbg(sc->dev, "hwq%d len: %d\n", txqid,
++						       skb_queue_len(&hw_txq->
++								     qhead));
++					}
++				}
++			}
++		}
++#endif
++		if (sc->tx_q_empty || (before_timeout == 0)) {
++			u32 flused_ampdu = ssv6xxx_ampdu_flush(sc->hw);
++			sc->tx_q_empty = false;
++			if (flused_ampdu == 0 && before_timeout == 0) {
++				wait_period *= 2;
++				if (wait_period > 1000)
++					wait_period = 1000;
++			}
++		} else
++			wait_period = SSV_AMPDU_timer_period / 2;
++	}
++	return 0;
++}
++
++int ssv6xxx_rx_task(void *data)
++{
++	struct ssv_softc *sc = (struct ssv_softc *)data;
++	unsigned long wait_period = msecs_to_jiffies(200);
++	unsigned long last_timeout_check_jiffies = jiffies;
++	unsigned long cur_jiffies;
++	dev_info(sc->dev, "RX Task started\n");
++	while (!kthread_should_stop()) {
++		u32 before_timeout = (-1);
++		set_current_state(TASK_INTERRUPTIBLE);
++		before_timeout = wait_event_interruptible_timeout(sc->rx_wait_q,
++								  (skb_queue_len
++								   (&sc->
++								    rx_skb_q)
++								   ||
++								   skb_queue_len
++								   (&sc->
++								    tx_done_q)
++								   ||
++								   kthread_should_stop
++								   ()),
++								  wait_period);
++		if (kthread_should_stop()) {
++			dev_dbg(sc->dev, "Quit RX task loop...\n");
++			break;
++		}
++		set_current_state(TASK_RUNNING);
++		cur_jiffies = jiffies;
++		if ((before_timeout == 0)
++		    || time_before((last_timeout_check_jiffies + wait_period),
++				   cur_jiffies)) {
++			ssv6xxx_ampdu_check_timeout(sc->hw);
++			last_timeout_check_jiffies = cur_jiffies;
++		}
++		if (skb_queue_len(&sc->rx_skb_q))
++			_process_rx_q(sc, &sc->rx_skb_q, NULL);
++		if (skb_queue_len(&sc->tx_done_q))
++			_process_tx_done(sc);
++	}
++	return 0;
++}
++
++struct ssv6xxx_iqk_cfg init_iqk_cfg = {
++	SSV6XXX_IQK_CFG_XTAL_26M,
++#ifdef CONFIG_SSV_DPD
++	SSV6XXX_IQK_CFG_PA_LI_MPB,
++#else
++	SSV6XXX_IQK_CFG_PA_DEF,
++#endif
++	0,
++	0,
++	26,
++	3,
++	0x75,
++	0x75,
++	0x80,
++	0x80,
++	SSV6XXX_IQK_CMD_INIT_CALI,
++	{SSV6XXX_IQK_TEMPERATURE
++	 + SSV6XXX_IQK_RXDC
++	 + SSV6XXX_IQK_RXRC
++	 + SSV6XXX_IQK_TXDC + SSV6XXX_IQK_TXIQ + SSV6XXX_IQK_RXIQ
++#ifdef CONFIG_SSV_DPD
++	 + SSV6XXX_IQK_PAPD
++#endif
++	 },
++};
++
++static int ssv6200_start(struct ieee80211_hw *hw)
++{
++	struct ssv_softc *sc = hw->priv;
++	struct ssv_hw *sh = sc->sh;
++	struct ieee80211_channel *chan;
++    int ret;
++
++	mutex_lock(&sc->mutex);
++    ret = ssv6xxx_init_mac(sc->sh);
++	if (ret != 0) {
++		dev_err(sc->dev, "Failed to initialize mac, ret=%d\n", ret);
++		ssv6xxx_deinit_mac(sc);
++		mutex_unlock(&sc->mutex);
++		return -1;
++	}
++#ifdef CONFIG_P2P_NOA
++	ssv6xxx_noa_reset(sc);
++#endif
++	HCI_START(sh);
++	ieee80211_wake_queues(hw);
++	ssv6200_ampdu_init(hw);
++	sc->watchdog_flag = WD_KICKED;
++	mutex_unlock(&sc->mutex);
++	mod_timer(&sc->watchdog_timeout, jiffies + WATCHDOG_TIMEOUT);
++#ifdef CONFIG_SSV_SMARTLINK
++	{
++		extern int ksmartlink_init(void);
++		(void)ksmartlink_init();
++	}
++#endif
++    ret = ssv6xxx_do_iq_calib(sc->sh, &init_iqk_cfg);
++    if (ret != 0) {
++        dev_err(sc->dev, "IQ Calibration failed, ret=%d\n", ret);
++        return ret;
++    }
++
++	dev_info(sc->dev, "Calibration successful\n");
++
++	SMAC_REG_WRITE(sc->sh, ADR_PHY_EN_1, 0x217f);
++	if ((sh->cfg.chip_identity == SSV6051Z)
++	    || (sc->sh->cfg.chip_identity == SSV6051P)) {
++		int i;
++		for (i = 0; i < sh->ch_cfg_size; i++) {
++			SMAC_REG_READ(sh, sh->p_ch_cfg[i].reg_addr,
++				      &sh->p_ch_cfg[i].ch1_12_value);
++		}
++	}
++	chan = hw->conf.chandef.chan;
++	sc->cur_channel = chan;
++	dev_dbg(sc->dev, "%s(): current channel: %d,sc->ps_status=%d\n", __FUNCTION__,
++	       sc->cur_channel->hw_value, sc->ps_status);
++	ssv6xxx_set_channel(sc, chan->hw_value);
++	ssv6xxx_rf_enable(sh);
++	return 0;
++}
++
++static void ssv6200_stop(struct ieee80211_hw *hw)
++{
++	struct ssv_softc *sc = hw->priv;
++	u32 count = 0;
++	struct rssi_res_st *rssi_tmp0, *rssi_tmp1;
++	dev_dbg(sc->dev, "%s(): sc->ps_status=%d\n", __FUNCTION__,
++	       sc->ps_status);
++	mutex_lock(&sc->mutex);
++	list_for_each_entry_safe(rssi_tmp0, rssi_tmp1, &rssi_res.rssi_list,
++				 rssi_list) {
++		list_del(&rssi_tmp0->rssi_list);
++		kfree(rssi_tmp0);
++	}
++	ssv6200_ampdu_deinit(hw);
++	ssv6xxx_rf_disable(sc->sh);
++	HCI_STOP(sc->sh);
++#ifndef NO_USE_RXQ_LOCK
++	while (0) {
++#else
++	while (skb_queue_len(&sc->rx.rxq_head)) {
++#endif
++		dev_dbg(sc->dev, "sc->rx.rxq_count=%d\n", sc->rx.rxq_count);
++		count++;
++		if (count > 90000000) {
++			dev_err(sc->dev, "Could not empty RX queue during shutdown\n");
++			break;
++		}
++	}
++	HCI_TXQ_FLUSH(sc->sh, (TXQ_EDCA_0 | TXQ_EDCA_1 | TXQ_EDCA_2 |
++			       TXQ_EDCA_3 | TXQ_MGMT));
++	if ((sc->ps_status == PWRSV_PREPARE) || (sc->ps_status == PWRSV_ENABLE)) {
++		ssv6xxx_enable_ps(sc);
++		ssv6xxx_rf_enable(sc->sh);
++	}
++	sc->watchdog_flag = WD_SLEEP;
++	mutex_unlock(&sc->mutex);
++	del_timer_sync(&sc->watchdog_timeout);
++#ifdef CONFIG_SSV_SMARTLINK
++	{
++		extern void ksmartlink_exit(void);
++		ksmartlink_exit();
++	}
++#endif
++	dev_dbg(sc->dev, "%s(): leave\n", __FUNCTION__);
++}
++
++void inline ssv62xxx_set_bssid(struct ssv_softc *sc, u8 * bssid)
++{
++	memcpy(sc->bssid, bssid, 6);
++	SMAC_REG_WRITE(sc->sh, ADR_BSSID_0, *((u32 *) & sc->bssid[0]));
++	SMAC_REG_WRITE(sc->sh, ADR_BSSID_1, *((u32 *) & sc->bssid[4]));
++}
++
++struct ssv_vif_priv_data *ssv6xxx_config_vif_res(struct ssv_softc *sc,
++						 struct ieee80211_vif *vif)
++{
++	int i;
++	struct ssv_vif_priv_data *priv_vif;
++	struct ssv_vif_info *vif_info;
++	lockdep_assert_held(&sc->mutex);
++	for (i = 0; i < SSV6200_MAX_VIF; i++) {
++		if (sc->vif_info[i].vif == NULL)
++			break;
++	}
++	BUG_ON(i >= SSV6200_MAX_VIF);
++	dev_dbg(sc->dev, "ssv6xxx_config_vif_res id[%d].\n", i);
++	priv_vif = (struct ssv_vif_priv_data *)vif->drv_priv;
++	memset(priv_vif, 0, sizeof(struct ssv_vif_priv_data));
++	priv_vif->vif_idx = i;
++	memset(&sc->vif_info[i], 0, sizeof(sc->vif_info[0]));
++	sc->vif_info[i].vif = vif;
++	sc->vif_info[i].vif_priv = priv_vif;
++	INIT_LIST_HEAD(&priv_vif->sta_list);
++	priv_vif->pair_cipher = SSV_CIPHER_NONE;
++	priv_vif->group_cipher = SSV_CIPHER_NONE;
++	priv_vif->has_hw_decrypt = false;
++	priv_vif->has_hw_encrypt = false;
++	priv_vif->need_sw_encrypt = false;
++	priv_vif->need_sw_decrypt = false;
++	priv_vif->use_mac80211_decrypt = false;
++	priv_vif->is_security_valid = false;
++	priv_vif->force_sw_encrypt = (vif->type == NL80211_IFTYPE_AP);
++	vif_info = &sc->vif_info[priv_vif->vif_idx];
++	vif_info->if_type = vif->type;
++	vif_info->vif = vif;
++	return priv_vif;
++}
++
++static int ssv6200_add_interface(struct ieee80211_hw *hw,
++				 struct ieee80211_vif *vif)
++{
++	struct ssv_softc *sc = hw->priv;
++	int ret = 0;
++	struct ssv_vif_priv_data *vif_priv = NULL;
++	dev_dbg(sc->dev, "[I] %s(): vif->type = %d, NL80211_IFTYPE_AP=%d\n", __FUNCTION__,
++	       vif->type, NL80211_IFTYPE_AP);
++	if ((sc->nvif >= SSV6200_MAX_VIF)
++	    || (((vif->type == NL80211_IFTYPE_AP)
++		 || (vif->p2p))
++		&& (sc->ap_vif != NULL))) {
++		dev_err(sc->dev, "Add interface of type %d (p2p: %d) failed.\n",
++			vif->type, vif->p2p);
++		return -EOPNOTSUPP;
++	}
++	mutex_lock(&sc->mutex);
++	vif_priv = ssv6xxx_config_vif_res(sc, vif);
++	if ((vif_priv->vif_idx == 0) && (vif->p2p == 0)
++	    && (vif->type == NL80211_IFTYPE_AP)) {
++		dev_dbg(sc->dev, "VIF[0] set bssid and config opmode to ap\n");
++		ssv62xxx_set_bssid(sc, sc->sh->cfg.maddr[0]);
++		SMAC_REG_SET_BITS(sc->sh, ADR_GLBLE_SET, SSV6200_OPMODE_AP,
++				  OP_MODE_MSK);
++	}
++	if (vif->type == NL80211_IFTYPE_AP) {
++		BUG_ON(sc->ap_vif != NULL);
++		sc->ap_vif = vif;
++		if (!vif->p2p && (vif_priv->vif_idx == 0)) {
++			dev_dbg(sc->dev, "Normal AP mode. Config Q4 to DTIM Q.\n");
++			SMAC_REG_SET_BITS(sc->sh, ADR_MTX_BCN_EN_MISC,
++					  MTX_HALT_MNG_UNTIL_DTIM_MSK,
++					  MTX_HALT_MNG_UNTIL_DTIM_MSK);
++			sc->bq4_dtim = true;
++		}
++	}
++	sc->nvif++;
++	dev_dbg(sc->dev,
++		"VIF %02x:%02x:%02x:%02x:%02x:%02x of type %d is added.\n",
++		vif->addr[0], vif->addr[1], vif->addr[2], vif->addr[3],
++		vif->addr[4], vif->addr[5], vif->type);
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	ssv6xxx_debugfs_add_interface(sc, vif);
++#endif
++	mutex_unlock(&sc->mutex);
++	return ret;
++}
++
++static void ssv6200_remove_interface(struct ieee80211_hw *hw,
++				     struct ieee80211_vif *vif)
++{
++	struct ssv_softc *sc = hw->priv;
++	struct ssv_vif_priv_data *vif_priv =
++	    (struct ssv_vif_priv_data *)vif->drv_priv;
++	dev_err(sc->dev,
++		"Removing interface %02x:%02x:%02x:%02x:%02x:%02x. PS=%d\n",
++		vif->addr[0], vif->addr[1], vif->addr[2], vif->addr[3],
++		vif->addr[4], vif->addr[5], sc->ps_status);
++	mutex_lock(&sc->mutex);
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	ssv6xxx_debugfs_remove_interface(sc, vif);
++#endif
++	if (vif->type == NL80211_IFTYPE_AP) {
++		if (sc->bq4_dtim) {
++			sc->bq4_dtim = false;
++			ssv6200_release_bcast_frame_res(sc, vif);
++			SMAC_REG_SET_BITS(sc->sh, ADR_MTX_BCN_EN_MISC,
++					  0, MTX_HALT_MNG_UNTIL_DTIM_MSK);
++			dev_dbg(sc->dev, "Config Q4 to normal Q \n");
++		}
++		ssv6xxx_beacon_release(sc);
++		sc->ap_vif = NULL;
++	}
++	memset(&sc->vif_info[vif_priv->vif_idx], 0,
++	       sizeof(struct ssv_vif_info));
++	sc->nvif--;
++	mutex_unlock(&sc->mutex);
++}
++
++static int ssv6200_change_interface(struct ieee80211_hw *dev,
++				    struct ieee80211_vif *vif,
++				    enum nl80211_iftype new_type, bool p2p)
++{
++    struct ssv_softc *sc = dev->priv;
++	int ret = 0;
++
++	dev_dbg(sc->dev, "change_interface new: %d (%d), old: %d (%d)\n", new_type,
++	       p2p, vif->type, vif->p2p);
++
++	if (new_type != vif->type || vif->p2p != p2p) {
++		ssv6200_remove_interface(dev, vif);
++		vif->type = new_type;
++		vif->p2p = p2p;
++		ret = ssv6200_add_interface(dev, vif);
++	}
++
++	return ret;
++}
++
++void ssv6xxx_ps_callback_func(unsigned long data)
++{
++	struct ssv_softc *sc = (struct ssv_softc *)data;
++	struct sk_buff *skb;
++	struct cfg_host_cmd *host_cmd;
++	int retry_cnt = 20;
++#ifdef SSV_WAKEUP_HOST
++	SMAC_REG_WRITE(sc->sh, ADR_RX_FLOW_MNG,
++		       M_ENG_MACRX | (M_ENG_CPU << 4) | (M_ENG_HWHCI << 8));
++	SMAC_REG_WRITE(sc->sh, ADR_RX_FLOW_DATA,
++		       M_ENG_MACRX | (M_ENG_CPU << 4) | (M_ENG_HWHCI << 8));
++	SMAC_REG_WRITE(sc->sh, ADR_MRX_FLT_TB0 + 6 * 4,
++		       (sc->mac_deci_tbl[6] | 1));
++#else
++	SMAC_REG_WRITE(sc->sh, ADR_RX_FLOW_MNG,
++		       M_ENG_MACRX | (M_ENG_TRASH_CAN << 4));
++	SMAC_REG_WRITE(sc->sh, ADR_RX_FLOW_DATA,
++		       M_ENG_MACRX | (M_ENG_TRASH_CAN << 4));
++	SMAC_REG_WRITE(sc->sh, ADR_RX_FLOW_MNG,
++		       M_ENG_MACRX | (M_ENG_TRASH_CAN << 4));
++#endif
++	skb = ssv_skb_alloc(sizeof(struct cfg_host_cmd));
++	skb->data_len = sizeof(struct cfg_host_cmd);
++	skb->len = skb->data_len;
++	host_cmd = (struct cfg_host_cmd *)skb->data;
++	host_cmd->c_type = HOST_CMD;
++	host_cmd->RSVD0 = 0;
++	host_cmd->h_cmd = (u8) SSV6XXX_HOST_CMD_PS;
++	host_cmd->len = skb->data_len;
++#ifdef SSV_WAKEUP_HOST
++	host_cmd->dummy = sc->ps_aid;
++#else
++	host_cmd->dummy = 0;
++#endif
++	sc->ps_aid = 0;
++	while ((HCI_SEND_CMD(sc->sh, skb) != 0) && (retry_cnt)) {
++		dev_warn(sc->dev, "PS cmd retry=%d!!\n", retry_cnt);
++		retry_cnt--;
++	}
++	ssv_skb_free(skb);
++	dev_dbg(sc->dev, "SSV6XXX_HOST_CMD_PS,ps_aid = %d,len=%d,tabl=0x%x\n",
++	       host_cmd->dummy, skb->len, (sc->mac_deci_tbl[6] | 1));
++}
++
++void ssv6xxx_enable_ps(struct ssv_softc *sc)
++{
++	sc->ps_status = PWRSV_ENABLE;
++}
++
++void ssv6xxx_disable_ps(struct ssv_softc *sc)
++{
++	sc->ps_status = PWRSV_DISABLE;
++	dev_info(sc->dev, "Power saving disabled\n");
++}
++
++int ssv6xxx_watchdog_controller(struct ssv_hw *sh, u8 flag)
++{
++	struct sk_buff *skb;
++	struct cfg_host_cmd *host_cmd;
++	int ret = 0;
++	dev_dbg(sh->sc->dev, "ssv6xxx_watchdog_controller %d\n", flag);
++	skb = ssv_skb_alloc(HOST_CMD_HDR_LEN);
++	if (skb == NULL) {
++		dev_warn(sh->sc->dev, "init ssv6xxx_watchdog_controller fail!!!\n");
++		return (-1);
++	}
++	skb->data_len = HOST_CMD_HDR_LEN;
++	skb->len = skb->data_len;
++	host_cmd = (struct cfg_host_cmd *)skb->data;
++	host_cmd->c_type = HOST_CMD;
++	host_cmd->h_cmd = (u8) flag;
++	host_cmd->len = skb->data_len;
++	sh->hci.hci_ops->hci_send_cmd(skb);
++	ssv_skb_free(skb);
++	return ret;
++}
++
++static int ssv6200_config(struct ieee80211_hw *hw, u32 changed)
++{
++	struct ssv_softc *sc = hw->priv;
++	int ret = 0;
++	mutex_lock(&sc->mutex);
++	if (changed & IEEE80211_CONF_CHANGE_PS) {
++		struct ieee80211_conf *conf = &hw->conf;
++		if (conf->flags & IEEE80211_CONF_PS) {
++			dev_dbg(sc->dev, "Enable IEEE80211_CONF_PS ps_aid=%d\n",
++			       sc->ps_aid);
++		} else {
++			dev_dbg(sc->dev, "Disable IEEE80211_CONF_PS ps_aid=%d\n",
++			       sc->ps_aid);
++		}
++	}
++	if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
++		struct ieee80211_channel *chan;
++		chan = hw->conf.chandef.chan;
++#ifdef CONFIG_P2P_NOA
++		if (sc->p2p_noa.active_noa_vif) {
++			dev_dbg(sc->dev, "NOA operating-active vif[%02x] skip scan\n",
++			       sc->p2p_noa.active_noa_vif);
++			goto out;
++		}
++#endif
++		if (hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) {
++			if ((sc->ap_vif == NULL)
++			    ||
++			    list_empty(&
++				       ((struct ssv_vif_priv_data *)sc->ap_vif->
++					drv_priv)->sta_list)) {
++				HCI_PAUSE(sc->sh,
++					  (TXQ_EDCA_0 | TXQ_EDCA_1 | TXQ_EDCA_2
++					   | TXQ_EDCA_3 | TXQ_MGMT));
++				sc->sc_flags |= SC_OP_OFFCHAN;
++				ssv6xxx_set_channel(sc, chan->hw_value);
++				sc->hw_chan = chan->hw_value;
++				HCI_RESUME(sc->sh, TXQ_MGMT);
++			} else {
++				dev_dbg(sc->dev,
++					"Off-channel to %d is ignored when AP mode enabled.\n",
++					chan->hw_value);
++			}
++		} else {
++			if ((sc->cur_channel == NULL)
++			    || (sc->sc_flags & SC_OP_OFFCHAN)
++			    || (sc->hw_chan != chan->hw_value)) {
++				HCI_PAUSE(sc->sh,
++					  (TXQ_EDCA_0 | TXQ_EDCA_1 | TXQ_EDCA_2
++					   | TXQ_EDCA_3 | TXQ_MGMT));
++				ssv6xxx_set_channel(sc, chan->hw_value);
++				sc->cur_channel = chan;
++				HCI_RESUME(sc->sh,
++					   (TXQ_EDCA_0 | TXQ_EDCA_1 | TXQ_EDCA_2
++					    | TXQ_EDCA_3 | TXQ_MGMT));
++				sc->sc_flags &= ~SC_OP_OFFCHAN;
++			} else {
++				dev_dbg(sc->dev,
++					"Change to the same channel %d\n",
++					chan->hw_value);
++			}
++		}
++	}
++#ifdef CONFIG_P2P_NOA
++ out:
++#endif
++	mutex_unlock(&sc->mutex);
++	return ret;
++}
++
++#define SUPPORTED_FILTERS \
++    (FIF_ALLMULTI | \
++    FIF_CONTROL | \
++    FIF_PSPOLL | \
++    FIF_OTHER_BSS | \
++    FIF_BCN_PRBRESP_PROMISC | \
++    FIF_PROBE_REQ | \
++    FIF_FCSFAIL)
++static void ssv6200_config_filter(struct ieee80211_hw *hw,
++				  unsigned int changed_flags,
++				  unsigned int *total_flags, u64 multicast)
++{
++	changed_flags &= SUPPORTED_FILTERS;
++	*total_flags &= SUPPORTED_FILTERS;
++}
++
++static void ssv6200_bss_info_changed(struct ieee80211_hw *hw,
++				     struct ieee80211_vif *vif,
++				     struct ieee80211_bss_conf *info,
++				     u64 changed)
++{
++	struct ssv_vif_priv_data *priv_vif = (struct ssv_vif_priv_data *)vif->drv_priv;
++	struct ssv_softc *sc = hw->priv;
++#ifdef CONFIG_P2P_NOA
++	u8 null_address[6] = { 0 };
++#endif
++	mutex_lock(&sc->mutex);
++	if (changed & BSS_CHANGED_ERP_PREAMBLE) {
++		dev_dbg(sc->dev, "BSS Changed use_short_preamble[%d]\n",
++		       info->use_short_preamble);
++		if (info->use_short_preamble)
++			sc->sc_flags |= SC_OP_SHORT_PREAMBLE;
++		else
++			sc->sc_flags &= ~SC_OP_SHORT_PREAMBLE;
++	}
++	if (!priv_vif->vif_idx) {
++		if (changed & BSS_CHANGED_BSSID) {
++#ifdef CONFIG_P2P_NOA
++			struct ssv_vif_priv_data *vif_priv;
++			vif_priv = (struct ssv_vif_priv_data *)vif->drv_priv;
++#endif
++			ssv62xxx_set_bssid(sc, (u8 *) info->bssid);
++			dev_dbg(sc->dev, "BSS_CHANGED_BSSID: %02x:%02x:%02x:%02x:%02x:%02x\n",
++			     info->bssid[0], info->bssid[1], info->bssid[2],
++			     info->bssid[3], info->bssid[4], info->bssid[5]);
++#ifdef CONFIG_P2P_NOA
++			if (memcmp(info->bssid, null_address, 6))
++				ssv6xxx_noa_hdl_bss_change(sc,
++							   MONITOR_NOA_CONF_ADD,
++							   vif_priv->vif_idx);
++			else
++				ssv6xxx_noa_hdl_bss_change(sc,
++							   MONITOR_NOA_CONF_REMOVE,
++							   vif_priv->vif_idx);
++#endif
++		}
++		if (changed & BSS_CHANGED_ERP_SLOT) {
++			u32 regval = 0;
++			dev_dbg(sc->dev, "BSS_CHANGED_ERP_SLOT: use_short_slot[%d]\n",
++			       info->use_short_slot);
++			if (info->use_short_slot) {
++				SMAC_REG_READ(sc->sh, ADR_MTX_DUR_IFS, &regval);
++				regval = regval & MTX_DUR_SLOT_I_MSK;
++				regval |= 9 << MTX_DUR_SLOT_SFT;
++				SMAC_REG_WRITE(sc->sh, ADR_MTX_DUR_IFS, regval);
++				SMAC_REG_READ(sc->sh, ADR_MTX_DUR_SIFS_G,
++					      &regval);
++				regval = regval & MTX_DUR_BURST_SIFS_G_I_MSK;
++				regval |= 0xa << MTX_DUR_BURST_SIFS_G_SFT;
++				regval = regval & MTX_DUR_SLOT_G_I_MSK;
++				regval |= 9 << MTX_DUR_SLOT_G_SFT;
++				SMAC_REG_WRITE(sc->sh, ADR_MTX_DUR_SIFS_G,
++					       regval);
++			} else {
++				SMAC_REG_READ(sc->sh, ADR_MTX_DUR_IFS, &regval);
++				regval = regval & MTX_DUR_SLOT_I_MSK;
++				regval |= 20 << MTX_DUR_SLOT_SFT;
++				SMAC_REG_WRITE(sc->sh, ADR_MTX_DUR_IFS, regval);
++				SMAC_REG_READ(sc->sh, ADR_MTX_DUR_SIFS_G,
++					      &regval);
++				regval = regval & MTX_DUR_BURST_SIFS_G_I_MSK;
++				regval |= 0xa << MTX_DUR_BURST_SIFS_G_SFT;
++				regval = regval & MTX_DUR_SLOT_G_I_MSK;
++				regval |= 20 << MTX_DUR_SLOT_G_SFT;
++				SMAC_REG_WRITE(sc->sh, ADR_MTX_DUR_SIFS_G,
++					       regval);
++			}
++		}
++	}
++	if (changed & BSS_CHANGED_HT) {
++		dev_dbg(sc->dev, "BSS_CHANGED_HT: Untreated!!\n");
++	}
++	if (changed & BSS_CHANGED_BASIC_RATES) {
++		dev_dbg(sc->dev, "ssv6xxx_rc_update_basic_rate!!\n");
++		ssv6xxx_rc_update_basic_rate(sc, info->basic_rates);
++	}
++	if (vif->type == NL80211_IFTYPE_STATION) {
++		dev_dbg(sc->dev, "NL80211_IFTYPE_STATION!!\n");
++		if ((changed & BSS_CHANGED_ASSOC) && (vif->p2p == 0)) {
++			sc->isAssoc = vif->cfg.assoc;
++			if (!sc->isAssoc) {
++				sc->channel_center_freq = 0;
++				sc->ps_aid = 0;
++#ifdef CONFIG_SSV_MRX_EN3_CTRL
++				SMAC_REG_WRITE(sc->sh, ADR_MRX_FLT_EN3, 0x0400);
++#endif
++				SMAC_REG_WRITE(sc->sh, ADR_RX_11B_CCA_CONTROL,
++					       0x0);
++			} else {
++				struct ieee80211_channel *curchan;
++				curchan = hw->conf.chandef.chan;
++				sc->channel_center_freq = curchan->center_freq;
++				dev_dbg(sc->dev, "info->aid = %d\n", vif->cfg.aid);
++				sc->ps_aid = vif->cfg.aid;
++#ifdef CONFIG_SSV_MRX_EN3_CTRL
++				SMAC_REG_WRITE(sc->sh, ADR_MRX_FLT_EN3, 0x1000);
++#endif
++			}
++		}
++#ifdef CONFIG_SSV_MRX_EN3_CTRL
++		else if ((changed & BSS_CHANGED_ASSOC) && vif->p2p == 1) {
++			if (info->assoc)
++				SMAC_REG_WRITE(sc->sh, ADR_MRX_FLT_EN3, 0x0400);
++			else if (sc->ps_aid != 0)
++				SMAC_REG_WRITE(sc->sh, ADR_MRX_FLT_EN3, 0x1000);
++		}
++#endif
++	}
++	if (vif->type == NL80211_IFTYPE_AP) {
++		if (changed & (BSS_CHANGED_BEACON
++			       | BSS_CHANGED_SSID
++			       | BSS_CHANGED_BSSID | BSS_CHANGED_BASIC_RATES)) {
++#ifdef BROADCAST_DEBUG
++			dev_dbg(sc->dev, "[A] ssv6200_bss_info_changed:beacon changed\n");
++#endif
++			queue_work(sc->config_wq, &sc->set_tim_work);
++		}
++		if (changed & BSS_CHANGED_BEACON_INT) {
++			dev_dbg(sc->dev, "[A] BSS_CHANGED_BEACON_INT beacon_interval(%d)\n",
++			     info->beacon_int);
++			if (sc->beacon_interval != info->beacon_int) {
++				sc->beacon_interval = info->beacon_int;
++				ssv6xxx_beacon_set_info(sc, sc->beacon_interval,
++							sc->beacon_dtim_cnt);
++			}
++		}
++		if (changed & BSS_CHANGED_BEACON_ENABLED) {
++#ifdef BEACON_DEBUG
++			dev_dbg(sc->dev, "[A] BSS_CHANGED_BEACON_ENABLED (0x%x)\n",
++			       info->enable_beacon);
++#endif
++			if (0 != ssv6xxx_beacon_enable(sc, info->enable_beacon)) {
++				dev_err(sc->dev, "Beacon enable %d error.\n",
++					info->enable_beacon);
++			}
++		}
++	}
++	mutex_unlock(&sc->mutex);
++	dev_dbg(sc->dev, "[I] %s(): leave\n", __FUNCTION__);
++}
++
++static int ssv6200_sta_add(struct ieee80211_hw *hw,
++			   struct ieee80211_vif *vif, struct ieee80211_sta *sta)
++{
++	struct ssv_sta_priv_data *sta_priv_dat = NULL;
++	struct ssv_softc *sc = hw->priv;
++	struct ssv_sta_info *sta_info;
++	u32 reg_wsid[] = { ADR_WSID0, ADR_WSID1 };
++	int s, i;
++	u32 reg_wsid_tid0[] = { ADR_WSID0_TID0_RX_SEQ, ADR_WSID1_TID0_RX_SEQ };
++	u32 reg_wsid_tid7[] = { ADR_WSID0_TID7_RX_SEQ, ADR_WSID1_TID7_RX_SEQ };
++	unsigned long flags;
++	int ret = 0;
++	struct ssv_vif_priv_data *vif_priv =
++	    (struct ssv_vif_priv_data *)vif->drv_priv;
++	int fw_sec_caps = SSV6XXX_WSID_SEC_NONE;
++	bool tdls_use_sw_cipher = false, tdls_link = false;
++	dev_dbg(sc->dev, "[I] %s(): vif[%d] ", __FUNCTION__, vif_priv->vif_idx);
++	if (sc->force_triger_reset == true) {
++		vif_priv->sta_asleep_mask = 0;
++		do {
++			spin_lock_irqsave(&sc->ps_state_lock, flags);
++			for (s = 0; s < SSV_NUM_STA; s++, sta_info++) {
++				sta_info = &sc->sta_info[s];
++				if ((sta_info->s_flags & STA_FLAG_VALID)) {
++					if (sta_info->sta == sta) {
++						dev_dbg
++						    (sc->dev, "search stat %02x:%02x:%02x:%02x:%02x:%02x to  wsid=%d\n",
++						     sta->addr[0], sta->addr[1],
++						     sta->addr[2], sta->addr[3],
++						     sta->addr[4], sta->addr[5],
++						     sta_info->hw_wsid);
++						spin_unlock_irqrestore(&sc->
++								       ps_state_lock,
++								       flags);
++						return ret;
++					}
++				}
++			}
++			spin_unlock_irqrestore(&sc->ps_state_lock, flags);
++			if (s >= SSV_NUM_STA) {
++				break;
++			}
++		} while (0);
++	}
++	do {
++		spin_lock_irqsave(&sc->ps_state_lock, flags);
++		if (!list_empty(&vif_priv->sta_list)
++		    && vif->type == NL80211_IFTYPE_STATION) {
++			tdls_link = true;
++		}
++		if ((tdls_link) && (vif_priv->pair_cipher != SSV_CIPHER_NONE)
++		    && (vif_priv->pair_cipher != SSV_CIPHER_CCMP)
++		    && (sc->sh->cfg.use_wpa2_only == false)) {
++			tdls_use_sw_cipher = true;
++		}
++		if (((vif_priv->vif_idx == 0) && (tdls_use_sw_cipher == false))
++		    || sc->sh->cfg.use_wpa2_only)
++			s = 0;
++		else
++			s = 2;
++		for (; s < SSV_NUM_STA; s++) {
++			sta_info = &sc->sta_info[s];
++			if ((sta_info->s_flags & STA_FLAG_VALID) == 0) {
++				sta_info->aid = sta->aid;
++				sta_info->sta = sta;
++				sta_info->vif = vif;
++				sta_info->s_flags = STA_FLAG_VALID;
++				sta_priv_dat =
++				    (struct ssv_sta_priv_data *)sta->drv_priv;
++				sta_priv_dat->sta_idx = s;
++				sta_priv_dat->sta_info = sta_info;
++				sta_priv_dat->has_hw_encrypt = false;
++				sta_priv_dat->has_hw_decrypt = false;
++				sta_priv_dat->need_sw_decrypt = false;
++				sta_priv_dat->need_sw_encrypt = false;
++				sta_priv_dat->use_mac80211_decrypt = false;
++				if ((vif_priv->pair_cipher == SSV_CIPHER_WEP40)
++				    || (vif_priv->pair_cipher ==
++					SSV_CIPHER_WEP104)) {
++					sta_priv_dat->has_hw_encrypt =
++					    vif_priv->has_hw_encrypt;
++					sta_priv_dat->has_hw_decrypt =
++					    vif_priv->has_hw_decrypt;
++					sta_priv_dat->need_sw_encrypt =
++					    vif_priv->need_sw_encrypt;
++					sta_priv_dat->need_sw_decrypt =
++					    vif_priv->need_sw_decrypt;
++				}
++				list_add_tail(&sta_priv_dat->list,
++					      &vif_priv->sta_list);
++				break;
++			}
++		}
++		spin_unlock_irqrestore(&sc->ps_state_lock, flags);
++		if (s >= SSV_NUM_STA) {
++			dev_err(sc->dev,
++				"Number of STA exceeds driver limitation %d\n.",
++				SSV_NUM_STA);
++			ret = -1;
++			break;
++		}
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++		ssv6xxx_debugfs_add_sta(sc, sta_info);
++#endif
++		sta_info->hw_wsid = -1;
++		if (sta_priv_dat->sta_idx < SSV_NUM_HW_STA) {
++			SMAC_REG_WRITE(sc->sh, reg_wsid[s] + 4,
++				       *((u32 *) & sta->addr[0]));
++			SMAC_REG_WRITE(sc->sh, reg_wsid[s] + 8,
++				       *((u32 *) & sta->addr[4]));
++			SMAC_REG_WRITE(sc->sh, reg_wsid[s], 1);
++			for (i = reg_wsid_tid0[s]; i <= reg_wsid_tid7[s];
++			     i += 4)
++				SMAC_REG_WRITE(sc->sh, i, 0);
++			ssv6xxx_rc_hw_reset(sc, sta_priv_dat->rc_idx, s);
++			sta_info->hw_wsid = sta_priv_dat->sta_idx;
++		} else if ((vif_priv->vif_idx == 0)
++			   || sc->sh->cfg.use_wpa2_only) {
++			sta_info->hw_wsid = sta_priv_dat->sta_idx;
++		}
++		if ((sta_priv_dat->has_hw_encrypt
++		     || sta_priv_dat->has_hw_decrypt)
++		    && ((vif_priv->pair_cipher == SSV_CIPHER_WEP40)
++			|| (vif_priv->pair_cipher == SSV_CIPHER_WEP104))) {
++			struct ssv_vif_info *vif_info =
++			    &sc->vif_info[vif_priv->vif_idx];
++			struct ssv6xxx_hw_sec *sramKey = &vif_info->sramKey;
++			_set_wep_hw_crypto_pair_key(sc, vif_info, sta_info,
++						    (void *)sramKey);
++			if (sramKey->sta_key[0].pair_key_idx != 0) {
++				_set_wep_hw_crypto_group_key(sc, vif_info,
++							     sta_info,
++							     (void *)sramKey);
++			}
++		}
++		ssv6200_ampdu_tx_add_sta(hw, sta);
++		if (sta_info->hw_wsid >= SSV_NUM_HW_STA) {
++			if (sta_priv_dat->has_hw_decrypt)
++				fw_sec_caps = SSV6XXX_WSID_SEC_PAIRWISE;
++			if (vif_priv->has_hw_decrypt)
++				fw_sec_caps |= SSV6XXX_WSID_SEC_GROUP;
++			hw_update_watch_wsid(sc, sta, sta_info,
++					     sta_priv_dat->sta_idx, fw_sec_caps,
++					     SSV6XXX_WSID_OPS_ADD);
++		} else if (SSV6200_USE_HW_WSID(sta_priv_dat->sta_idx)) {
++			hw_update_watch_wsid(sc, sta, sta_info,
++					     sta_priv_dat->sta_idx,
++					     SSV6XXX_WSID_SEC_SW,
++					     SSV6XXX_WSID_OPS_HWWSID_PAIRWISE_SET_TYPE);
++			hw_update_watch_wsid(sc, sta, sta_info,
++					     sta_priv_dat->sta_idx,
++					     SSV6XXX_WSID_SEC_SW,
++					     SSV6XXX_WSID_OPS_HWWSID_GROUP_SET_TYPE);
++		}
++		dev_dbg
++		    (sc->dev, "Add %02x:%02x:%02x:%02x:%02x:%02x to VIF %d sw_idx=%d, wsid=%d\n",
++		     sta->addr[0], sta->addr[1], sta->addr[2], sta->addr[3],
++		     sta->addr[4], sta->addr[5], vif_priv->vif_idx,
++		     sta_priv_dat->sta_idx, sta_info->hw_wsid);
++	} while (0);
++	return ret;
++}
++
++void ssv6200_rx_flow_check(struct ssv_sta_priv_data *sta_priv_dat,
++			   struct ssv_softc *sc)
++{
++	if (SSV6200_USE_HW_WSID(sta_priv_dat->sta_idx)
++	    && (sta_priv_dat->need_sw_decrypt)) {
++		int other_hw_wsid = (sta_priv_dat->sta_idx + 1) & 1;
++		struct ssv_sta_info *sta_info = &sc->sta_info[other_hw_wsid];
++		struct ieee80211_sta *sta = sta_info->sta;
++		struct ssv_sta_priv_data *sta_priv =
++		    (struct ssv_sta_priv_data *)sta->drv_priv;
++		mutex_lock(&sc->mutex);
++		if ((sta_info->s_flags == 0)
++		    || ((sta_info->s_flags && STA_FLAG_VALID)
++			&& (sta_priv->has_hw_decrypt))) {
++			SMAC_REG_WRITE(sc->sh, ADR_RX_FLOW_DATA,
++				       M_ENG_MACRX | (M_ENG_ENCRYPT_SEC << 4) |
++				       (M_ENG_HWHCI << 8));
++			dev_dbg(sc->dev, "redirect Rx flow for sta %d disconnect\n",
++			       sta_priv_dat->sta_idx);
++		}
++		mutex_unlock(&sc->mutex);
++	}
++}
++
++static int ssv6200_sta_remove(struct ieee80211_hw *hw,
++			      struct ieee80211_vif *vif,
++			      struct ieee80211_sta *sta)
++{
++	u32 reg_wsid[] = { ADR_WSID0, ADR_WSID1 };
++	struct ssv_sta_priv_data *sta_priv_dat =
++	    (struct ssv_sta_priv_data *)sta->drv_priv;
++	struct ssv_softc *sc = hw->priv;
++	struct ssv_sta_info *sta_info = sta_priv_dat->sta_info;
++	unsigned long flags;
++	u32 bit;
++	struct ssv_vif_priv_data *priv_vif =
++	    (struct ssv_vif_priv_data *)vif->drv_priv;
++	u8 hw_wsid = -1;
++	BUG_ON(sta_priv_dat->sta_idx >= SSV_NUM_STA);
++	dev_notice(sc->dev,
++		   "Removing STA %d (%02X:%02X:%02X:%02X:%02X:%02X) from VIF %d\n.",
++		   sta_priv_dat->sta_idx, sta->addr[0], sta->addr[1],
++		   sta->addr[2], sta->addr[3], sta->addr[4], sta->addr[5],
++		   priv_vif->vif_idx);
++	ssv6200_rx_flow_check(sta_priv_dat, sc);
++	spin_lock_irqsave(&sc->ps_state_lock, flags);
++	bit = BIT(sta_priv_dat->sta_idx);
++	priv_vif->sta_asleep_mask &= ~bit;
++	if (sta_info->hw_wsid != -1) {
++		hw_wsid = sta_info->hw_wsid;
++	}
++	if (sta_info->hw_wsid >= SSV_NUM_HW_STA) {
++		spin_unlock_irqrestore(&sc->ps_state_lock, flags);
++		hw_update_watch_wsid(sc, sta, sta_info, sta_info->hw_wsid, 0,
++				     SSV6XXX_WSID_OPS_DEL);
++		spin_lock_irqsave(&sc->ps_state_lock, flags);
++	}
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	{
++		ssv6xxx_debugfs_remove_sta(sc, sta_info);
++	}
++#endif
++	memset(sta_info, 0, sizeof(*sta_info));
++	sta_priv_dat->sta_idx = -1;
++	list_del(&sta_priv_dat->list);
++	if (list_empty(&priv_vif->sta_list)
++	    && vif->type == NL80211_IFTYPE_STATION) {
++		priv_vif->pair_cipher = 0;
++		priv_vif->group_cipher = 0;
++	}
++	spin_unlock_irqrestore(&sc->ps_state_lock, flags);
++	if ((hw_wsid != -1) && (hw_wsid < SSV_NUM_HW_STA))
++		SMAC_REG_WRITE(sc->sh, reg_wsid[hw_wsid], 0x00);
++	return 0;
++}
++
++static void ssv6200_sta_notify(struct ieee80211_hw *hw,
++			       struct ieee80211_vif *vif,
++			       enum sta_notify_cmd cmd,
++			       struct ieee80211_sta *sta)
++{
++	struct ssv_softc *sc = hw->priv;
++	struct ssv_vif_priv_data *priv_vif =
++	    (struct ssv_vif_priv_data *)vif->drv_priv;
++	struct ssv_sta_priv_data *sta_priv_dat =
++	    sta != NULL ? (struct ssv_sta_priv_data *)sta->drv_priv : NULL;
++	struct ssv_sta_info *sta_info;
++	u32 bit, prev;
++	unsigned long flags;
++	spin_lock_irqsave(&sc->ps_state_lock, flags);
++	if (sta_priv_dat != NULL) {
++		bit = BIT(sta_priv_dat->sta_idx);
++		prev = priv_vif->sta_asleep_mask & bit;
++		sta_info = sta_priv_dat->sta_info;
++		switch (cmd) {
++		case STA_NOTIFY_SLEEP:
++			if (!prev) {
++				sta_info->sleeping = true;
++				if ((vif->type == NL80211_IFTYPE_AP)
++				    && sc->bq4_dtim
++				    && !priv_vif->sta_asleep_mask
++				    && ssv6200_bcast_queue_len(&sc->
++							       bcast_txq)) {
++					dev_dbg(sc->dev, "%s(): ssv6200_bcast_start\n", __FUNCTION__);
++					ssv6200_bcast_start(sc);
++				}
++				priv_vif->sta_asleep_mask |= bit;
++			}
++			break;
++		case STA_NOTIFY_AWAKE:
++			if (prev) {
++				sta_info->sleeping = false;
++				priv_vif->sta_asleep_mask &= ~bit;
++			}
++			break;
++		default:
++			break;
++		}
++	}
++	spin_unlock_irqrestore(&sc->ps_state_lock, flags);
++}
++
++static u64 ssv6200_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
++{
++	return jiffies * 1000 * 1000 / HZ;
++}
++
++static u64 ssv6200_get_systime_us(void)
++{
++#if LINUX_VERSION_CODE > KERNEL_VERSION(4,19,0)
++	struct timespec64 ts;
++	ktime_get_boottime_ts64(&ts);
++#else
++	struct timespec ts;
++	get_monotonic_boottime(&ts);
++#endif
++	return ((u64) ts.tv_sec * 1000000) + ts.tv_nsec / 1000;
++}
++
++static u32 pre_11b_cca_control;
++static u32 pre_11b_cca_1;
++static void ssv6200_sw_scan_start(struct ieee80211_hw *hw,
++				  struct ieee80211_vif *vif,
++				  const u8 * mac_addr)
++{
++	((struct ssv_softc *)(hw->priv))->bScanning = true;
++	SMAC_REG_READ(((struct ssv_softc *)(hw->priv))->sh,
++		      ADR_RX_11B_CCA_CONTROL, &pre_11b_cca_control);
++	SMAC_REG_WRITE(((struct ssv_softc *)(hw->priv))->sh,
++		       ADR_RX_11B_CCA_CONTROL, 0x0);
++	SMAC_REG_READ(((struct ssv_softc *)(hw->priv))->sh, ADR_RX_11B_CCA_1,
++		      &pre_11b_cca_1);
++	SMAC_REG_WRITE(((struct ssv_softc *)(hw->priv))->sh, ADR_RX_11B_CCA_1,
++		       RX_11B_CCA_IN_SCAN);
++#ifdef CONFIG_SSV_MRX_EN3_CTRL
++	SMAC_REG_WRITE(((struct ssv_softc *)(hw->priv))->sh, ADR_MRX_FLT_EN3,
++		       0x0400);
++#endif
++}
++
++static void ssv6200_sw_scan_complete(struct ieee80211_hw *hw,
++				     struct ieee80211_vif *vif)
++{
++
++#ifdef CONFIG_SSV_MRX_EN3_CTRL
++	bool is_p2p_assoc;
++#endif
++	((struct ssv_softc *)(hw->priv))->bScanning = false;
++	SMAC_REG_WRITE(((struct ssv_softc *)(hw->priv))->sh,
++		       ADR_RX_11B_CCA_CONTROL, pre_11b_cca_control);
++	SMAC_REG_WRITE(((struct ssv_softc *)(hw->priv))->sh, ADR_RX_11B_CCA_1,
++		       pre_11b_cca_1);
++#ifdef CONFIG_SSV_MRX_EN3_CTRL
++	is_p2p_assoc =
++	    ((struct ssv_softc *)(hw->priv))->vif_info[1].vif->bss_conf.assoc;
++	if (((struct ssv_softc *)(hw->priv))->ps_aid != 0 && (!is_p2p_assoc))
++		SMAC_REG_WRITE(((struct ssv_softc *)(hw->priv))->sh,
++			       ADR_MRX_FLT_EN3, 0x1000);
++#endif
++}
++
++static int ssv6200_set_tim(struct ieee80211_hw *hw, struct ieee80211_sta *sta,
++			   bool set)
++{
++	struct ssv_softc *sc = hw->priv;
++	struct ssv_sta_info *sta_info = sta
++	    ? ((struct ssv_sta_priv_data *)sta->drv_priv)->sta_info : NULL;
++	if (sta_info && (sta_info->tim_set ^ set)) {
++        dev_dbg(sc->dev, "[I] [A] ssvcabrio_set_tim");
++		sta_info->tim_set = set;
++		queue_work(sc->config_wq, &sc->set_tim_work);
++	}
++	return 0;
++}
++
++static int ssv6200_conf_tx(struct ieee80211_hw *hw,
++			   struct ieee80211_vif *vif, u32 link_id, u16 queue,
++			   const struct ieee80211_tx_queue_params *params)
++{
++	struct ssv_softc *sc = hw->priv;
++	u32 cw;
++	u8 hw_txqid = sc->tx.hw_txqid[queue];
++	struct ssv_vif_priv_data *priv_vif =
++	    (struct ssv_vif_priv_data *)vif->drv_priv;
++	dev_dbg
++	    (sc->dev, "[I] sv6200_conf_tx vif[%d] qos[%d] queue[%d] aifsn[%d] cwmin[%d] cwmax[%d] txop[%d] \n",
++	     priv_vif->vif_idx, vif->bss_conf.qos, queue, params->aifs,
++	     params->cw_min, params->cw_max, params->txop);
++	if (queue > NL80211_TXQ_Q_BK)
++		return 1;
++	if (priv_vif->vif_idx != 0) {
++		dev_warn(sc->dev,
++			 "WMM setting applicable to primary interface only.\n");
++		return 1;
++	}
++	mutex_lock(&sc->mutex);
++	SMAC_REG_SET_BITS(sc->sh, ADR_GLBLE_SET,
++			  (vif->bss_conf.qos << QOS_EN_SFT), QOS_EN_MSK);
++	cw = (params->aifs - 1) & 0xf;
++	cw |= ((ilog2(params->cw_min + 1)) & 0xf) << TXQ1_MTX_Q_ECWMIN_SFT;
++	cw |= ((ilog2(params->cw_max + 1)) & 0xf) << TXQ1_MTX_Q_ECWMAX_SFT;
++	cw |= ((params->txop) & 0xff) << TXQ1_MTX_Q_TXOP_LIMIT_SFT;
++	SMAC_REG_WRITE(sc->sh, ADR_TXQ0_MTX_Q_AIFSN + 0x100 * hw_txqid, cw);
++	mutex_unlock(&sc->mutex);
++	return 0;
++}
++
++static int ssv6200_ampdu_action(struct ieee80211_hw *hw,
++				struct ieee80211_vif *vif,
++				struct ieee80211_ampdu_params *params)
++{
++	struct ssv_softc *sc = hw->priv;
++	int ret = 0;
++	struct ieee80211_sta *sta = params->sta;
++	enum ieee80211_ampdu_mlme_action action = params->action;
++	u16 tid = params->tid;
++	u16 *ssn = &(params->ssn);
++	u8 buf_size = params->buf_size;
++	if (sta == NULL)
++		return ret;
++#if (!Enable_AMPDU_Rx)
++	if (action == IEEE80211_AMPDU_RX_START
++	    || action == IEEE80211_AMPDU_RX_STOP) {
++		ampdu_db_log("Disable AMPDU_RX for test(1).\n");
++		return -EOPNOTSUPP;
++	}
++#endif
++#if (!Enable_AMPDU_Tx)
++	if (action == IEEE80211_AMPDU_TX_START
++	    || action == IEEE80211_AMPDU_TX_STOP
++	    || action == IEEE80211_AMPDU_TX_OPERATIONAL) {
++		ampdu_db_log("Disable AMPDU_TX for test(1).\n");
++		return -EOPNOTSUPP;
++	}
++#endif
++	if ((action == IEEE80211_AMPDU_RX_START
++	     || action == IEEE80211_AMPDU_RX_STOP)
++	    && (!(sc->sh->cfg.hw_caps & SSV6200_HW_CAP_AMPDU_RX))) {
++		ampdu_db_log("Disable AMPDU_RX(2).\n");
++		return -EOPNOTSUPP;
++	}
++	if ((action == IEEE80211_AMPDU_TX_START
++	     || action == IEEE80211_AMPDU_TX_STOP_CONT
++	     || action == IEEE80211_AMPDU_TX_STOP_FLUSH
++	     || action == IEEE80211_AMPDU_TX_STOP_FLUSH_CONT
++	     || action == IEEE80211_AMPDU_TX_OPERATIONAL)
++	    && (!(sc->sh->cfg.hw_caps & SSV6200_HW_CAP_AMPDU_TX))) {
++		ampdu_db_log("Disable AMPDU_TX(2).\n");
++		return -EOPNOTSUPP;
++	}
++	switch (action) {
++	case IEEE80211_AMPDU_RX_START:
++#ifdef WIFI_CERTIFIED
++		if (sc->rx_ba_session_count >= SSV6200_RX_BA_MAX_SESSIONS) {
++			ieee80211_stop_rx_ba_session(vif,
++						     (1 << (sc->ba_tid)),
++						     sc->ba_ra_addr);
++			sc->rx_ba_session_count--;
++		}
++#else
++		if ((sc->rx_ba_session_count >= SSV6200_RX_BA_MAX_SESSIONS)
++		    && (sc->rx_ba_sta != sta)) {
++			ret = -EBUSY;
++			break;
++		} else
++		    if ((sc->rx_ba_session_count >= SSV6200_RX_BA_MAX_SESSIONS)
++			&& (sc->rx_ba_sta == sta)) {
++			ieee80211_stop_rx_ba_session(vif, (1 << (sc->ba_tid)),
++						     sc->ba_ra_addr);
++			sc->rx_ba_session_count--;
++		}
++#endif
++		dev_dbg(sc->dev, "IEEE80211_AMPDU_RX_START %02X:%02X:%02X:%02X:%02X:%02X %d.\n",
++		       sta->addr[0], sta->addr[1], sta->addr[2], sta->addr[3],
++		       sta->addr[4], sta->addr[5], tid);
++		sc->rx_ba_session_count++;
++		sc->rx_ba_sta = sta;
++		sc->ba_tid = tid;
++		sc->ba_ssn = *ssn;
++		memcpy(sc->ba_ra_addr, sta->addr, ETH_ALEN);
++		queue_work(sc->config_wq, &sc->set_ampdu_rx_add_work);
++		break;
++	case IEEE80211_AMPDU_RX_STOP:
++		sc->rx_ba_session_count--;
++		if (sc->rx_ba_session_count == 0)
++			sc->rx_ba_sta = NULL;
++		queue_work(sc->config_wq, &sc->set_ampdu_rx_del_work);
++		break;
++	case IEEE80211_AMPDU_TX_START:
++		dev_dbg(sc->dev, "AMPDU_TX_START %02X:%02X:%02X:%02X:%02X:%02X %d.\n",
++		       sta->addr[0], sta->addr[1], sta->addr[2], sta->addr[3],
++		       sta->addr[4], sta->addr[5], tid);
++		ssv6200_ampdu_tx_start(tid, sta, hw, ssn);
++		ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
++		break;
++	case IEEE80211_AMPDU_TX_STOP_CONT:
++	case IEEE80211_AMPDU_TX_STOP_FLUSH:
++	case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
++		dev_dbg(sc->dev, "AMPDU_TX_STOP %02X:%02X:%02X:%02X:%02X:%02X %d.\n",
++		       sta->addr[0], sta->addr[1], sta->addr[2], sta->addr[3],
++		       sta->addr[4], sta->addr[5], tid);
++		ssv6200_ampdu_tx_stop(tid, sta, hw);
++		ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
++		break;
++	case IEEE80211_AMPDU_TX_OPERATIONAL:
++		dev_dbg(sc->dev, "AMPDU_TX_OPERATIONAL %02X:%02X:%02X:%02X:%02X:%02X %d.\n",
++		       sta->addr[0], sta->addr[1], sta->addr[2], sta->addr[3],
++		       sta->addr[4], sta->addr[5], tid);
++		ssv6200_ampdu_tx_operation(tid, sta, hw, buf_size);
++		break;
++	default:
++		ret = -EOPNOTSUPP;
++		break;
++	}
++	return ret;
++}
++
++#ifdef CONFIG_PM
++int ssv6xxx_suspend(struct ieee80211_hw *hw, struct cfg80211_wowlan *wowlan)
++{
++	return 0;
++}
++
++int ssv6xxx_resume(struct ieee80211_hw *hw)
++{
++	return 0;
++}
++#endif
++struct ieee80211_ops ssv6200_ops = {
++	.tx = ssv6200_tx,
++	.start = ssv6200_start,
++	.stop = ssv6200_stop,
++	.add_interface = ssv6200_add_interface,
++	.remove_interface = ssv6200_remove_interface,
++	.change_interface = ssv6200_change_interface,
++	.config = ssv6200_config,
++	.configure_filter = ssv6200_config_filter,
++	.bss_info_changed = ssv6200_bss_info_changed,
++	.sta_add = ssv6200_sta_add,
++	.sta_remove = ssv6200_sta_remove,
++	.sta_notify = ssv6200_sta_notify,
++	.set_key = ssv6200_set_key,
++	.sw_scan_start = ssv6200_sw_scan_start,
++	.sw_scan_complete = ssv6200_sw_scan_complete,
++	.get_tsf = ssv6200_get_tsf,
++	.set_tim = ssv6200_set_tim,
++	.conf_tx = ssv6200_conf_tx,
++	.ampdu_action = ssv6200_ampdu_action,
++	.wake_tx_queue = ieee80211_handle_wake_tx_queue,
++#ifdef CONFIG_PM
++	.suspend = ssv6xxx_suspend,
++	.resume = ssv6xxx_resume,
++#endif
++};
++
++int ssv6200_tx_flow_control(void *dev, int hw_txqid, bool fc_en, int debug)
++{
++	struct ssv_softc *sc = dev;
++	int ac;
++	BUG_ON(hw_txqid > 4);
++	if (hw_txqid == 4)
++		return 0;
++	ac = sc->tx.ac_txqid[hw_txqid];
++	if (fc_en == false) {
++		if (sc->tx.flow_ctrl_status & (1 << ac)) {
++			ieee80211_wake_queue(sc->hw, ac);
++			sc->tx.flow_ctrl_status &= ~(1 << ac);
++		} else {
++		}
++	} else {
++		if ((sc->tx.flow_ctrl_status & (1 << ac)) == 0) {
++			ieee80211_stop_queue(sc->hw, ac);
++			sc->tx.flow_ctrl_status |= (1 << ac);
++		} else {
++		}
++	}
++	return 0;
++}
++
++void ssv6xxx_tx_q_empty_cb(u32 txq_no, void *cb_data)
++{
++	struct ssv_softc *sc = cb_data;
++	BUG_ON(sc == NULL);
++	sc->tx_q_empty = true;
++	smp_mb();
++	wake_up_interruptible(&sc->tx_wait_q);
++}
++
++struct ssv6xxx_b_cca_control {
++	u32 down_level;
++	u32 upper_level;
++	u32 adjust_cca_control;
++	u32 adjust_cca_1;
++};
++struct ssv6xxx_b_cca_control adjust_cci[] = {
++	{0, 43, 0x00162000, 0x20380050},
++	{40, 48, 0x00161000, 0x20380050},
++	{45, 53, 0x00160800, 0x20380050},
++	{50, 63, 0x00160400, 0x20380050},
++	{60, 68, 0x00160200, 0x20380050},
++	{65, 73, 0x00160100, 0x20380050},
++	{70, 128, 0x00000000, 0x20300050},
++};
++
++#define MAX_CCI_LEVEL 128
++static unsigned long last_jiffies = INITIAL_JIFFIES;
++static s32 size = sizeof(adjust_cci) / sizeof(adjust_cci[0]);
++static u32 current_level = MAX_CCI_LEVEL;
++static u32 current_gate = (sizeof(adjust_cci) / sizeof(adjust_cci[0])) - 1;
++void mitigate_cci(struct ssv_softc *sc, u32 input_level)
++{
++	s32 i;
++	if (input_level > MAX_CCI_LEVEL) {
++		dev_dbg(sc->dev, "mitigate_cci input error[%d]!!\n", input_level);
++		return;
++	}
++	if (time_after(jiffies, last_jiffies + msecs_to_jiffies(3000))) {
++		dev_dbg(sc->dev, "jiffies=%lu, input_level=%d\n", jiffies, input_level);
++		last_jiffies = jiffies;
++		if ((input_level >= adjust_cci[current_gate].down_level)
++		    && (input_level <= adjust_cci[current_gate].upper_level)) {
++			current_level = input_level;
++#ifdef DEBUG_MITIGATE_CCI
++			dev_dbg(sc->dev, "Keep the 0xce0020a0[%x] 0xce002008[%x]!!\n",
++			       adjust_cci[current_gate].adjust_cca_control,
++			       adjust_cci[current_gate].adjust_cca_1);
++#endif
++		} else {
++			if (current_level < input_level) {
++				for (i = 0; i < size; i++) {
++					if (input_level <=
++					    adjust_cci[i].upper_level) {
++#ifdef DEBUG_MITIGATE_CCI
++						dev_dbg(sc->dev, "gate=%d, input_level=%d, adjust_cci[%d].upper_level=%d, value=%08x\n",
++						     current_gate, input_level,
++						     i,
++						     adjust_cci[i].upper_level,
++						     adjust_cci[i].
++						     adjust_cca_control);
++#endif
++						current_level = input_level;
++						current_gate = i;
++						SMAC_REG_WRITE(sc->sh,
++							       ADR_RX_11B_CCA_CONTROL,
++							       adjust_cci[i].
++							       adjust_cca_control);
++						SMAC_REG_WRITE(sc->sh,
++							       ADR_RX_11B_CCA_1,
++							       adjust_cci[i].
++							       adjust_cca_1);
++#ifdef DEBUG_MITIGATE_CCI
++						dev_dbg(sc->dev, "##Set to the 0xce0020a0[%x] 0xce002008[%x]##!!\n",
++						     adjust_cci[current_gate].
++						     adjust_cca_control,
++						     adjust_cci[current_gate].
++						     adjust_cca_1);
++#endif
++						return;
++					}
++				}
++			} else {
++				for (i = (size - 1); i >= 0; i--) {
++					if (input_level >=
++					    adjust_cci[i].down_level) {
++#ifdef DEBUG_MITIGATE_CCI
++						dev_dbg(sc->dev, "gate=%d, input_level=%d, adjust_cci[%d].down_level=%d, value=%08x\n",
++						     current_gate, input_level,
++						     i,
++						     adjust_cci[i].down_level,
++						     adjust_cci[i].
++						     adjust_cca_control);
++#endif
++						current_level = input_level;
++						current_gate = i;
++						SMAC_REG_WRITE(sc->sh,
++							       ADR_RX_11B_CCA_CONTROL,
++							       adjust_cci[i].
++							       adjust_cca_control);
++						SMAC_REG_WRITE(sc->sh,
++							       ADR_RX_11B_CCA_1,
++							       adjust_cci[i].
++							       adjust_cca_1);
++#ifdef DEBUG_MITIGATE_CCI
++						dev_dbg(sc->dev, "##Set to the 0xce0020a0[%x] 0xce002008[%x]##!!\n",
++						     adjust_cci[current_gate].
++						     adjust_cca_control,
++						     adjust_cci[current_gate].
++						     adjust_cca_1);
++#endif
++						return;
++					}
++				}
++			}
++		}
++	}
++}
++
++#define RSSI_SMOOTHING_SHIFT 5
++#define RSSI_DECIMAL_POINT_SHIFT 6
++static void _proc_data_rx_skb(struct ssv_softc *sc, struct sk_buff *rx_skb)
++{
++	struct ieee80211_rx_status *rxs;
++	struct ieee80211_hdr *hdr;
++	__le16 fc;
++	struct ssv6200_rx_desc *rxdesc;
++	struct ssv6200_rxphy_info_padding *rxphypad;
++	struct ssv6200_rxphy_info *rxphy;
++	struct ieee80211_channel *chan;
++	struct ieee80211_vif *vif = NULL;
++	struct ieee80211_sta *sta = NULL;
++	bool rx_hw_dec = false;
++	bool do_sw_dec = false;
++	struct ssv_sta_priv_data *sta_priv = NULL;
++	struct ssv_vif_priv_data *vif_priv = NULL;
++	SKB_info *skb_info = NULL;
++	u8 is_beacon;
++	u8 is_probe_resp;
++	s32 found = 0;
++#ifdef CONFIG_SSV_SMARTLINK
++	{
++		extern int ksmartlink_smartlink_started(void);
++		void smartlink_nl_send_msg(struct sk_buff *skb);
++		if (unlikely(ksmartlink_smartlink_started())) {
++			skb_pull(rx_skb, SSV6XXX_RX_DESC_LEN);
++			skb_trim(rx_skb, rx_skb->len - sc->sh->rx_pinfo_pad);
++			smartlink_nl_send_msg(rx_skb);
++			return;
++		}
++	}
++#endif
++	rxdesc = (struct ssv6200_rx_desc *)rx_skb->data;
++	rxphy = (struct ssv6200_rxphy_info *)(rx_skb->data + sizeof(*rxdesc));
++	rxphypad =
++	    (struct ssv6200_rxphy_info_padding *)(rx_skb->data + rx_skb->len -
++						  sizeof(struct
++							 ssv6200_rxphy_info_padding));
++	hdr = (struct ieee80211_hdr *)(rx_skb->data + SSV6XXX_RX_DESC_LEN);
++	fc = hdr->frame_control;
++	skb_info = (SKB_info *) rx_skb->head;
++	if (rxdesc->wsid >= SSV_RC_MAX_HARDWARE_SUPPORT) {
++		if ((ieee80211_is_data(hdr->frame_control))
++		    && (!(ieee80211_is_nullfunc(hdr->frame_control)))) {
++			ssv6xxx_rc_rx_data_handler(sc->hw, rx_skb,
++						   rxdesc->rate_idx);
++		}
++	}
++	rxs = IEEE80211_SKB_RXCB(rx_skb);
++	memset(rxs, 0, sizeof(struct ieee80211_rx_status));
++	ssv6xxx_rc_mac8011_rate_idx(sc, rxdesc->rate_idx, rxs);
++
++	rxs->mactime = *((u32 *) & rx_skb->data[28]);
++	chan = sc->hw->conf.chandef.chan;
++	rxs->band = chan->band;
++	rxs->freq = chan->center_freq;
++	rxs->antenna = 1;
++	is_beacon = ieee80211_is_beacon(hdr->frame_control);
++	is_probe_resp = ieee80211_is_probe_resp(hdr->frame_control);
++	if (is_beacon)		//+++
++	{
++		struct ieee80211_mgmt *mgmt_tmp = NULL;
++		mgmt_tmp =
++		    (struct ieee80211_mgmt *)(rx_skb->data +
++					      SSV6XXX_RX_DESC_LEN);
++		mgmt_tmp->u.beacon.timestamp =
++		    cpu_to_le64(ssv6200_get_systime_us());
++	}
++	if (is_probe_resp) {
++		struct ieee80211_mgmt *mgmt_tmp = NULL;
++		mgmt_tmp =
++		    (struct ieee80211_mgmt *)(rx_skb->data +
++					      SSV6XXX_RX_DESC_LEN);
++		mgmt_tmp->u.probe_resp.timestamp =
++		    cpu_to_le64(ssv6200_get_systime_us());
++	}
++
++	if (rxdesc->rate_idx < SSV62XX_G_RATE_INDEX && rxphypad->RSVD == 0) {
++		if (is_beacon || is_probe_resp) {
++			sta = ssv6xxx_find_sta_by_rx_skb(sc, rx_skb);
++			if (sta) {
++				sta_priv =
++				    (struct ssv_sta_priv_data *)sta->drv_priv;
++#ifdef SSV_RSSI_DEBUG
++				dev_dbg(sc->dev, "b_beacon %02X:%02X:%02X:%02X:%02X:%02X rssi=%d, snr=%d\n",
++				       hdr->addr2[0], hdr->addr2[1],
++				       hdr->addr2[2], hdr->addr2[3],
++				       hdr->addr2[4], hdr->addr2[5],
++				       rxphypad->rpci, rxphypad->snr);
++#endif
++				if (sta_priv->beacon_rssi) {
++					sta_priv->beacon_rssi =
++					    ((rxphypad->
++					      rpci << RSSI_DECIMAL_POINT_SHIFT)
++					     +
++					     ((sta_priv->
++					       beacon_rssi <<
++					       RSSI_SMOOTHING_SHIFT) -
++					      sta_priv->
++					      beacon_rssi)) >>
++					    RSSI_SMOOTHING_SHIFT;
++					rxphypad->rpci =
++					    (sta_priv->
++					     beacon_rssi >>
++					     RSSI_DECIMAL_POINT_SHIFT);
++				} else
++					sta_priv->beacon_rssi =
++					    (rxphypad->
++					     rpci << RSSI_DECIMAL_POINT_SHIFT);
++#ifdef SSV_RSSI_DEBUG
++				dev_dbg(sc->dev, "Beacon smoothing RSSI %d\n", rxphypad->rpci);
++#endif
++				mitigate_cci(sc, rxphypad->rpci);
++			} else {
++				mutex_lock(&sc->mutex);
++				list_for_each_entry(p_rssi_res,
++						    &rssi_res.rssi_list,
++						    rssi_list) {
++					if (!memcmp
++					    (p_rssi_res->bssid, hdr->addr2,
++					     ETH_ALEN)) {
++						{
++							p_rssi_res->rssi =
++							    ((rxphypad->
++							      rpci <<
++							      RSSI_DECIMAL_POINT_SHIFT)
++							     +
++							     ((p_rssi_res->
++							       rssi <<
++							       RSSI_SMOOTHING_SHIFT)
++							      -
++							      p_rssi_res->
++							      rssi)) >>
++							    RSSI_SMOOTHING_SHIFT;
++							rxphypad->rpci =
++							    (p_rssi_res->
++							     rssi >>
++							     RSSI_DECIMAL_POINT_SHIFT);
++						}
++						p_rssi_res->cache_jiffies =
++						    jiffies;
++						found = 1;
++						break;
++					} else {
++						if (p_rssi_res->rssi) {
++							if (time_after
++							    (jiffies,
++							     p_rssi_res->
++							     cache_jiffies +
++							     msecs_to_jiffies
++							     (40000))) {
++								p_rssi_res->
++								    timeout = 1;
++							}
++						}
++					}
++				}
++				if (!found) {
++					p_rssi_res =
++					    kmalloc(sizeof(struct rssi_res_st),
++						    GFP_KERNEL);
++					memcpy(p_rssi_res->bssid, hdr->addr2,
++					       ETH_ALEN);
++					p_rssi_res->cache_jiffies = jiffies;
++					p_rssi_res->rssi =
++					    (rxphypad->
++					     rpci << RSSI_DECIMAL_POINT_SHIFT);
++					p_rssi_res->timeout = 0;
++					INIT_LIST_HEAD(&p_rssi_res->rssi_list);
++					list_add_tail_rcu(&
++							  (p_rssi_res->
++							   rssi_list),
++							  &(rssi_res.
++							    rssi_list));
++				}
++				mutex_unlock(&sc->mutex);
++			}
++			if (rxphypad->rpci > 88)
++				rxphypad->rpci = 88;
++		}
++		if (sc->sh->cfg.rssi_ctl) {
++			rxs->signal = (-rxphypad->rpci) + sc->sh->cfg.rssi_ctl;
++		} else {
++			rxs->signal = (-rxphypad->rpci);
++		}
++	} else if (rxdesc->rate_idx >= SSV62XX_G_RATE_INDEX
++		   && rxphy->service == 0) {
++		if (is_beacon || is_probe_resp) {
++			sta = ssv6xxx_find_sta_by_rx_skb(sc, rx_skb);
++			if (sta) {
++				sta_priv =
++				    (struct ssv_sta_priv_data *)sta->drv_priv;
++#ifdef SSV_RSSI_DEBUG
++				dev_dbg(sc->dev, "gn_beacon %02X:%02X:%02X:%02X:%02X:%02X rssi=%d, snr=%d\n",
++				     hdr->addr2[0], hdr->addr2[1],
++				     hdr->addr2[2], hdr->addr2[3],
++				     hdr->addr2[4], hdr->addr2[5], rxphy->rpci,
++				     rxphy->snr);
++#endif
++				if (sta_priv->beacon_rssi) {
++					sta_priv->beacon_rssi =
++					    ((rxphy->
++					      rpci << RSSI_DECIMAL_POINT_SHIFT)
++					     +
++					     ((sta_priv->
++					       beacon_rssi <<
++					       RSSI_SMOOTHING_SHIFT) -
++					      sta_priv->
++					      beacon_rssi)) >>
++					    RSSI_SMOOTHING_SHIFT;
++					rxphy->rpci =
++					    (sta_priv->
++					     beacon_rssi >>
++					     RSSI_DECIMAL_POINT_SHIFT);
++				} else
++					sta_priv->beacon_rssi =
++					    (rxphy->
++					     rpci << RSSI_DECIMAL_POINT_SHIFT);
++#ifdef SSV_RSSI_DEBUG
++				dev_dbg(sc->dev, "Beacon smoothing RSSI %d\n", rxphy->rpci);
++#endif
++			}
++			if (rxphy->rpci > 88)
++				rxphy->rpci = 88;
++		}
++		if (sc->sh->cfg.rssi_ctl) {
++			rxs->signal = (-rxphy->rpci) + sc->sh->cfg.rssi_ctl;
++		} else {
++			rxs->signal = (-rxphy->rpci);
++		}
++	} else {
++#ifdef SSV_RSSI_DEBUG
++		dev_dbg(sc->dev, "########unicast: %d, b_rssi/snr: %d/%d, gn_rssi/snr: %d/%d, rate:%d###############\n",
++		     rxdesc->unicast, (-rxphy->rpci), rxphy->snr,
++		     (-rxphypad->rpci), rxphypad->snr, rxdesc->rate_idx);
++		dev_dbg(sc->dev, "RSSI, %d, rate_idx, %d\n", rxs->signal,
++		       rxdesc->rate_idx);
++		dev_dbg(sc->dev, "rxdesc->RxResult = %x,rxdesc->wsid = %d\n",
++		       rxdesc->RxResult, rxdesc->wsid);
++#endif
++		sta = ssv6xxx_find_sta_by_rx_skb(sc, rx_skb);
++		if (sta) {
++			sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
++			rxs->signal =
++			    -(sta_priv->
++			      beacon_rssi >> RSSI_DECIMAL_POINT_SHIFT);
++		}
++#ifdef SSV_RSSI_DEBUG
++		dev_dbg(sc->dev, "Others signal %d\n", rxs->signal);
++#endif
++	}
++//    rxs->flag = RX_FLAG_MACTIME_START;          //+++
++	rxs->rx_flags = 0;
++	if (rxphy->aggregate)
++		rxs->flag |= RX_FLAG_NO_SIGNAL_VAL;
++	sc->hw_mng_used = rxdesc->mng_used;
++	if ((ieee80211_is_data(fc) || ieee80211_is_data_qos(fc))
++	    && ieee80211_has_protected(fc)) {
++		sta = ssv6xxx_find_sta_by_rx_skb(sc, rx_skb);
++		if (sta == NULL)
++			goto drop_rx;
++		sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
++		vif = sta_priv->sta_info->vif;
++		if (vif == NULL)
++			goto drop_rx;
++		if (is_broadcast_ether_addr(hdr->addr1) || is_multicast_ether_addr(hdr->addr1)) {
++			vif_priv = (struct ssv_vif_priv_data *)vif->drv_priv;
++			rx_hw_dec = vif_priv->has_hw_decrypt;
++			do_sw_dec = vif_priv->need_sw_decrypt;
++		} else {
++			rx_hw_dec = sta_priv->has_hw_decrypt;
++			do_sw_dec = sta_priv->need_sw_decrypt;
++		}
++	}
++	skb_pull(rx_skb, SSV6XXX_RX_DESC_LEN);
++	skb_trim(rx_skb, rx_skb->len - sc->sh->rx_pinfo_pad);
++#ifdef CONFIG_P2P_NOA
++	if (is_beacon)
++		ssv6xxx_noa_detect(sc, hdr, rx_skb->len);
++#endif
++	if (rx_hw_dec || do_sw_dec) {
++		hdr = (struct ieee80211_hdr *)rx_skb->data;
++		rxs = IEEE80211_SKB_RXCB(rx_skb);
++		hdr->frame_control =
++		    hdr->
++		    frame_control & ~(cpu_to_le16(IEEE80211_FCTL_PROTECTED));
++		rxs->flag |= (RX_FLAG_DECRYPTED | RX_FLAG_IV_STRIPPED);
++	}
++#if defined(USE_THREAD_RX) && !defined(IRQ_PROC_RX_DATA)
++	local_bh_disable();
++	ieee80211_rx(sc->hw, rx_skb);
++	local_bh_enable();
++#else
++	ieee80211_rx_irqsafe(sc->hw, rx_skb);
++#endif
++	return;
++ drop_rx:
++	dev_kfree_skb_any(rx_skb);
++}
++
++#ifdef IRQ_PROC_RX_DATA
++static struct sk_buff *_proc_rx_skb(struct ssv_softc *sc,
++				    struct sk_buff *rx_skb)
++{
++	struct ieee80211_hdr *hdr =
++	    (struct ieee80211_hdr *)(rx_skb->data + SSV6XXX_RX_DESC_LEN);
++	struct ssv6200_rx_desc *rxdesc = (struct ssv6200_rx_desc *)rx_skb->data;
++	if (ieee80211_is_back(hdr->frame_control)
++	    || (rxdesc->c_type == HOST_EVENT))
++		return rx_skb;
++	_proc_data_rx_skb(sc, rx_skb);
++	return NULL;
++}
++#endif
++void _process_rx_q(struct ssv_softc *sc, struct sk_buff_head *rx_q,
++		   spinlock_t * rx_q_lock)
++{
++	struct sk_buff *skb;
++	struct ieee80211_hdr *hdr;
++	struct ssv6200_rx_desc *rxdesc;
++	unsigned long flags = 0;
++#ifdef USE_FLUSH_RETRY
++	bool has_ba_processed = false;
++#endif
++	while (1) {
++		if (rx_q_lock != NULL) {
++			spin_lock_irqsave(rx_q_lock, flags);
++			skb = __skb_dequeue(rx_q);
++		} else
++			skb = skb_dequeue(rx_q);
++		if (!skb) {
++			if (rx_q_lock != NULL)
++				spin_unlock_irqrestore(rx_q_lock, flags);
++			break;
++		}
++		sc->rx.rxq_count--;
++		if (rx_q_lock != NULL)
++			spin_unlock_irqrestore(rx_q_lock, flags);
++		rxdesc = (struct ssv6200_rx_desc *)skb->data;
++		if (rxdesc->c_type == HOST_EVENT) {
++			struct cfg_host_event *h_evt =
++			    (struct cfg_host_event *)rxdesc;
++			if (h_evt->h_event == SOC_EVT_NO_BA) {
++				ssv6200_ampdu_no_BA_handler(sc->hw, skb);
++#ifdef USE_FLUSH_RETRY
++				has_ba_processed = true;
++#endif
++			} else if (h_evt->h_event == SOC_EVT_RC_MPDU_REPORT) {
++				skb_queue_tail(&sc->rc_report_queue, skb);
++				if (sc->rc_sample_sechedule == 0)
++					queue_work(sc->rc_sample_workqueue,
++						   &sc->rc_sample_work);
++			} else if (h_evt->h_event == SOC_EVT_SDIO_TEST_COMMAND) {
++				if (h_evt->evt_seq_no == 0) {
++					dev_dbg(sc->dev, "SOC_EVT_SDIO_TEST_COMMAND\n");
++					sc->sdio_rx_evt_size = h_evt->len;
++					sc->sdio_throughput_timestamp = jiffies;
++				} else {
++					sc->sdio_rx_evt_size += h_evt->len;
++					if (time_after
++					    (jiffies,
++					     sc->sdio_throughput_timestamp +
++					     msecs_to_jiffies(1000))) {
++						dev_dbg(sc->dev, "data[%ld] SDIO RX throughput %ld Kbps\n",
++						     sc->sdio_rx_evt_size,
++						     (sc->
++						      sdio_rx_evt_size << 3) /
++						     jiffies_to_msecs(jiffies -
++								      sc->
++								      sdio_throughput_timestamp));
++						sc->sdio_throughput_timestamp =
++						    jiffies;
++						sc->sdio_rx_evt_size = 0;
++					}
++				}
++				dev_kfree_skb_any(skb);
++			} else if (h_evt->h_event == SOC_EVT_WATCHDOG_TRIGGER) {
++				dev_kfree_skb_any(skb);
++//              if(sc->watchdog_flag != WD_SLEEP)     //+++
++				sc->watchdog_flag = WD_KICKED;
++			} else if (h_evt->h_event == SOC_EVT_RESET_HOST) {
++				dev_kfree_skb_any(skb);
++				if ((sc->ap_vif == NULL)
++				    || !(sc->sh->cfg.ignore_reset_in_ap)) {
++					ssv6xxx_restart_hw(sc);
++				} else {
++					dev_warn(sc->dev,
++						 "Reset event ignored.\n");
++				}
++			}
++#ifdef CONFIG_P2P_NOA
++			else if (h_evt->h_event == SOC_EVT_NOA) {
++				ssv6xxx_process_noa_event(sc, skb);
++				dev_kfree_skb_any(skb);
++			}
++#endif
++			else if (h_evt->h_event == SOC_EVT_SDIO_TXTPUT_RESULT) {
++				dev_dbg(sc->dev, "data SDIO TX throughput %d Kbps\n",
++				       h_evt->evt_seq_no);
++				dev_kfree_skb_any(skb);
++			} else if (h_evt->h_event == SOC_EVT_TXLOOPBK_RESULT) {
++				if (h_evt->evt_seq_no == SSV6XXX_STATE_OK) {
++					dev_dbg(sc->dev, "FW TX LOOPBACK OK\n");
++					sc->iq_cali_done = IQ_CALI_OK;
++				} else {
++					dev_dbg(sc->dev, "FW TX LOOPBACK FAILED\n");
++					sc->iq_cali_done = IQ_CALI_FAILED;
++				}
++				dev_kfree_skb_any(skb);
++				wake_up_interruptible(&sc->fw_wait_q);
++			} else {
++				dev_warn(sc->dev, "Unkown event %d received\n",
++					 h_evt->h_event);
++				dev_kfree_skb_any(skb);
++			}
++			continue;
++		}
++		hdr = (struct ieee80211_hdr *)(skb->data + SSV6XXX_RX_DESC_LEN);
++		if (ieee80211_is_back(hdr->frame_control)) {
++			ssv6200_ampdu_BA_handler(sc->hw, skb);
++#ifdef USE_FLUSH_RETRY
++			has_ba_processed = true;
++#endif
++			continue;
++		}
++		_proc_data_rx_skb(sc, skb);
++	}
++#ifdef USE_FLUSH_RETRY
++	if (has_ba_processed) {
++		ssv6xxx_ampdu_postprocess_BA(sc->hw);
++	}
++#endif
++}
++
++#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
++int ssv6200_rx(struct sk_buff_head *rx_skb_q, void *args)
++#else
++int ssv6200_rx(struct sk_buff *rx_skb, void *args)
++#endif
++{
++	struct ssv_softc *sc = args;
++#ifdef IRQ_PROC_RX_DATA
++	struct sk_buff *skb;
++	skb = _proc_rx_skb(sc, rx_skb);
++	if (skb == NULL)
++		return 0;
++#endif
++#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
++	{
++		unsigned long flags;
++		spin_lock_irqsave(&sc->rx_skb_q.lock, flags);
++		while (skb_queue_len(rx_skb_q))
++			__skb_queue_tail(&sc->rx_skb_q,
++					 __skb_dequeue(rx_skb_q));
++		spin_unlock_irqrestore(&sc->rx_skb_q.lock, flags);
++	}
++#else
++	skb_queue_tail(&sc->rx_skb_q, rx_skb);
++#endif
++	wake_up_interruptible(&sc->rx_wait_q);
++	return 0;
++}
++
++struct ieee80211_sta *ssv6xxx_find_sta_by_rx_skb(struct ssv_softc *sc,
++						 struct sk_buff *skb)
++{
++	struct ieee80211_hdr *hdr =
++	    (struct ieee80211_hdr *)(skb->data + SSV6XXX_RX_DESC_LEN);
++	struct ssv6200_rx_desc *rxdesc = (struct ssv6200_rx_desc *)skb->data;;
++	if ((rxdesc->wsid >= 0) && (rxdesc->wsid < SSV_NUM_STA))
++		return sc->sta_info[rxdesc->wsid].sta;
++	else
++		return ssv6xxx_find_sta_by_addr(sc, hdr->addr2);
++}
++
++struct ieee80211_sta *ssv6xxx_find_sta_by_addr(struct ssv_softc *sc, u8 addr[6])
++{
++	struct ieee80211_sta *sta;
++	int i;
++	for (i = 0; i < SSV6200_MAX_VIF; i++) {
++		if (sc->vif_info[i].vif == NULL)
++			continue;
++		sta = ieee80211_find_sta(sc->vif_info[i].vif, addr);
++		if (sta != NULL)
++			return sta;
++	}
++	return NULL;
++}
++
++void ssv6xxx_foreach_sta(struct ssv_softc *sc,
++			 void (*sta_func)(struct ssv_softc *,
++					  struct ssv_sta_info *, void *),
++			 void *param)
++{
++	int i;
++	BUG_ON(sta_func == NULL);
++	for (i = 0; i < SSV_NUM_STA; i++) {
++		if ((sc->sta_info[i].s_flags & STA_FLAG_VALID) == 0)
++			continue;
++		(*sta_func) (sc, &sc->sta_info[i], param);
++	}
++}
++
++void ssv6xxx_foreach_vif_sta(struct ssv_softc *sc,
++			     struct ssv_vif_info *vif_info,
++			     void (*sta_func)(struct ssv_softc *,
++					      struct ssv_vif_info *,
++					      struct ssv_sta_info *,
++					      void *), void *param)
++{
++	struct ssv_vif_priv_data *vif_priv;
++	struct ssv_sta_priv_data *sta_priv_iter;
++	BUG_ON(vif_info == NULL);
++	BUG_ON((size_t)vif_info < 0x30000);
++	vif_priv = (struct ssv_vif_priv_data *)vif_info->vif->drv_priv;
++	BUG_ON((size_t)vif_info->vif < 0x30000);
++	BUG_ON((size_t)vif_priv < 0x30000);
++	list_for_each_entry(sta_priv_iter, &vif_priv->sta_list, list) {
++		BUG_ON(sta_priv_iter == NULL);
++		BUG_ON((size_t)sta_priv_iter < 0x30000);
++		BUG_ON(sta_priv_iter->sta_info == NULL);
++		BUG_ON((size_t)sta_priv_iter->sta_info < 0x30000);
++		if ((sta_priv_iter->sta_info->s_flags & STA_FLAG_VALID) == 0)
++			continue;
++		(*sta_func) (sc, vif_info, sta_priv_iter->sta_info, param);
++	}
++}
++
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++ssize_t ssv6xxx_tx_queue_status_dump(struct ssv_softc *sc, char *status_buf,
++				     ssize_t length)
++{
++	ssize_t buf_size = length;
++	ssize_t prt_size;
++	prt_size =
++	    snprintf(status_buf, buf_size, "\nSMAC driver queue status:.\n");
++	status_buf += prt_size;
++	buf_size -= prt_size;
++	prt_size = snprintf(status_buf, buf_size, "\tTX queue: %d\n",
++			    skb_queue_len(&sc->tx_skb_q));
++	status_buf += prt_size;
++	buf_size -= prt_size;
++	prt_size = snprintf(status_buf, buf_size, "\tMax TX queue: %d\n",
++			    sc->max_tx_skb_q_len);
++	status_buf += prt_size;
++	buf_size -= prt_size;
++	return (length - buf_size);
++}
++#endif
+diff --git a/drivers/net/wireless/ssv6051/smac/dev.h b/drivers/net/wireless/ssv6051/smac/dev.h
+new file mode 100644
+index 000000000000..0a6357624b1c
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/dev.h
+@@ -0,0 +1,445 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation, either version 3 of the License, or
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _DEV_H_
++#define _DEV_H_
++#include <linux/version.h>
++#include <linux/device.h>
++#include <linux/interrupt.h>
++#include <net/mac80211.h>
++#include "ampdu.h"
++#include "ssv_rc_common.h"
++#include "drv_comm.h"
++#include "sec.h"
++#include "p2p.h"
++#include <linux/kthread.h>
++#define SSV6200_MAX_HW_MAC_ADDR 2
++#define SSV6200_MAX_VIF 2
++#define SSV6200_RX_BA_MAX_SESSIONS 1
++#define SSV6200_OPMODE_STA 0
++#define SSV6200_OPMODE_AP 1
++#define SSV6200_OPMODE_IBSS 2
++#define SSV6200_OPMODE_WDS 3
++#define SSV6200_USE_HW_WSID(_sta_idx) ((_sta_idx == 0) || (_sta_idx == 1))
++#define HW_MAX_RATE_TRIES 7
++#define MAC_DECITBL1_SIZE 16
++#define MAC_DECITBL2_SIZE 9
++#define RX_11B_CCA_IN_SCAN 0x20230050
++//#define WATCHDOG_TIMEOUT (10*HZ)
++#define WATCHDOG_TIMEOUT (99999*HZ)
++extern u16 generic_deci_tbl[];
++#define ap_deci_tbl generic_deci_tbl
++#define sta_deci_tbl generic_deci_tbl
++#define HT_SIGNAL_EXT 6
++#define HT_SIFS_TIME 10
++#define BITS_PER_BYTE 8
++#define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
++#define ACK_LEN (14)
++#define BA_LEN (32)
++#define RTS_LEN (20)
++#define CTS_LEN (14)
++#define L_STF 8
++#define L_LTF 8
++#define L_SIG 4
++#define HT_SIG 8
++#define HT_STF 4
++#define HT_LTF(_ns) (4 * (_ns))
++#define SYMBOL_TIME(_ns) ((_ns) << 2)
++#define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5)
++#define CCK_SIFS_TIME 10
++#define CCK_PREAMBLE_BITS 144
++#define CCK_PLCP_BITS 48
++#define OFDM_SIFS_TIME 16
++#define OFDM_PREAMBLE_TIME 20
++#define OFDM_PLCP_BITS 22
++#define OFDM_SYMBOL_TIME 4
++#define WMM_AC_VO 0
++#define WMM_AC_VI 1
++#define WMM_AC_BE 2
++#define WMM_AC_BK 3
++#define WMM_NUM_AC 4
++#define WMM_TID_NUM 8
++#define TXQ_EDCA_0 0x01
++#define TXQ_EDCA_1 0x02
++#define TXQ_EDCA_2 0x04
++#define TXQ_EDCA_3 0x08
++#define TXQ_MGMT 0x10
++#define IS_SSV_HT(dsc) ((dsc)->rate_idx >= 15)
++#define IS_SSV_SHORT_GI(dsc) ((dsc)->rate_idx>=23 && (dsc)->rate_idx<=30)
++#define IS_SSV_HT_GF(dsc) ((dsc)->rate_idx >= 31)
++#define IS_SSV_SHORT_PRE(dsc) ((dsc)->rate_idx>=4 && (dsc)->rate_idx<=14)
++#define SMAC_REG_WRITE(_s,_r,_v) \
++        (_s)->hci.hci_ops->hci_write_word(_r,_v)
++#define SMAC_REG_READ(_s,_r,_v) \
++        (_s)->hci.hci_ops->hci_read_word(_r, _v)
++#define SMAC_LOAD_FW(_s,_r,_v) \
++        (_s)->hci.hci_ops->hci_load_fw(_r, _v)
++#define SMAC_IFC_RESET(_s) (_s)->hci.hci_ops->hci_interface_reset()
++#define SMAC_REG_CONFIRM(_s,_r,_v) \
++{ \
++    u32 _regval; \
++    SMAC_REG_READ(_s, _r, &_regval); \
++    if (_regval != (_v)) { \
++        printk("ERROR!!Please check interface!\n"); \
++        printk("[0x%08x]: 0x%08x!=0x%08x\n", \
++        (_r), (_v), _regval); \
++        printk("SOS!SOS!\n"); \
++        return -1; \
++    } \
++}
++#define SMAC_REG_SET_BITS(_sh,_reg,_set,_clr) \
++({ \
++    int ret; \
++    u32 _regval; \
++    ret = SMAC_REG_READ(_sh, _reg, &_regval); \
++    _regval &= ~(_clr); \
++    _regval |= (_set); \
++    if (ret == 0) \
++        ret = SMAC_REG_WRITE(_sh, _reg, _regval); \
++    ret; \
++})
++#define HCI_START(_sh) \
++    (_sh)->hci.hci_ops->hci_start()
++#define HCI_STOP(_sh) \
++    (_sh)->hci.hci_ops->hci_stop()
++#define HCI_SEND(_sh,_sk,_q) \
++    (_sh)->hci.hci_ops->hci_tx(_sk, _q, 0)
++#define HCI_PAUSE(_sh,_mk) \
++    (_sh)->hci.hci_ops->hci_tx_pause(_mk)
++#define HCI_RESUME(_sh,_mk) \
++    (_sh)->hci.hci_ops->hci_tx_resume(_mk)
++#define HCI_TXQ_FLUSH(_sh,_mk) \
++    (_sh)->hci.hci_ops->hci_txq_flush(_mk)
++#define HCI_TXQ_FLUSH_BY_STA(_sh,_aid) \
++  (_sh)->hci.hci_ops->hci_txq_flush_by_sta(_aid)
++#define HCI_TXQ_EMPTY(_sh,_txqid) \
++  (_sh)->hci.hci_ops->hci_txq_empty(_txqid)
++#define HCI_WAKEUP_PMU(_sh) \
++    (_sh)->hci.hci_ops->hci_pmu_wakeup()
++#define HCI_SEND_CMD(_sh,_sk) \
++        (_sh)->hci.hci_ops->hci_send_cmd(_sk)
++#define SSV6XXX_SET_HW_TABLE(sh_,tbl_) \
++({ \
++    int ret = 0; \
++    u32 i=0; \
++    for(; i<sizeof(tbl_)/sizeof(struct ssv6xxx_dev_table); i++) { \
++        ret = SMAC_REG_WRITE(sh_, tbl_[i].address, tbl_[i].data); \
++        if (ret) break; \
++    } \
++    ret; \
++})
++#define SSV6XXX_USE_HW_DECRYPT(_priv) (_priv->has_hw_decrypt)
++#define SSV6XXX_USE_SW_DECRYPT(_priv) (SSV6XXX_USE_LOCAL_SW_DECRYPT(_priv) || SSV6XXX_USE_MAC80211_DECRYPT(_priv))
++#define SSV6XXX_USE_LOCAL_SW_DECRYPT(_priv) (_priv->need_sw_decrypt)
++#define SSV6XXX_USE_MAC80211_DECRYPT(_priv) (_priv->use_mac80211_decrypt)
++struct ssv_softc;
++#ifdef CONFIG_P2P_NOA
++struct ssv_p2p_noa;
++#endif
++#define SSV6200_HT_TX_STREAMS 1
++#define SSV6200_HT_RX_STREAMS 1
++#define SSV6200_RX_HIGHEST_RATE 72
++enum PWRSV_STATUS {
++	PWRSV_DISABLE,
++	PWRSV_ENABLE,
++	PWRSV_PREPARE,
++};
++struct rssi_res_st {
++	struct list_head rssi_list;
++	unsigned long cache_jiffies;
++	s32 rssi;
++	s32 timeout;
++	u8 bssid[ETH_ALEN];
++};
++struct ssv_hw {
++	struct ssv_softc *sc;
++	struct ssv6xxx_platform_data *priv;
++	struct ssv6xxx_hci_info hci;
++	char chip_id[24];
++	u64 chip_tag;
++	u32 tx_desc_len;
++	u32 rx_desc_len;
++	u32 rx_pinfo_pad;
++	u32 tx_page_available;
++	u32 ampdu_divider;
++	u8 page_count[SSV6200_ID_NUMBER];
++	u32 hw_buf_ptr[SSV_RC_MAX_STA];
++	u32 hw_sec_key[SSV_RC_MAX_STA];
++	u32 hw_pinfo;
++	struct ssv6xxx_cfg cfg;
++	u32 n_addresses;
++	struct mac_address maddr[SSV6200_MAX_HW_MAC_ADDR];
++	u8 ipd_channel_touch;
++	struct ssv6xxx_ch_cfg *p_ch_cfg;
++	u32 ch_cfg_size;
++};
++struct ssv_tx {
++	u16 seq_no;
++	int hw_txqid[WMM_NUM_AC];
++	int ac_txqid[WMM_NUM_AC];
++	u32 flow_ctrl_status;
++	u32 tx_pkt[SSV_HW_TXQ_NUM];
++	u32 tx_frag[SSV_HW_TXQ_NUM];
++	struct list_head ampdu_tx_que;
++	spinlock_t ampdu_tx_que_lock;
++	u16 ampdu_tx_group_id;
++};
++struct ssv_rx {
++	struct sk_buff *rx_buf;
++	spinlock_t rxq_lock;
++	struct sk_buff_head rxq_head;
++	u32 rxq_count;
++};
++#define SSV6XXX_GET_STA_INFO(_sc,_s) \
++    &(_sc)->sta_info[((struct ssv_sta_priv_data *)((_s)->drv_priv))->sta_idx]
++#define STA_FLAG_VALID 0x00001
++#define STA_FLAG_QOS 0x00002
++#define STA_FLAG_AMPDU 0x00004
++#define STA_FLAG_ENCRYPT 0x00008
++struct ssv_sta_info {
++	u16 aid;
++	u16 s_flags;
++	int hw_wsid;
++	struct ieee80211_sta *sta;
++	struct ieee80211_vif *vif;
++	bool sleeping;
++	bool tim_set;
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	struct dentry *debugfs_dir;
++#endif
++};
++struct ssv_vif_info {
++	struct ieee80211_vif *vif;
++	struct ssv_vif_priv_data *vif_priv;
++	enum nl80211_iftype if_type;
++	struct ssv6xxx_hw_sec sramKey;
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	struct dentry *debugfs_dir;
++#endif
++};
++struct ssv_sta_priv_data {
++	int sta_idx;
++	int rc_idx;
++	int rx_data_rate;
++	struct ssv_sta_info *sta_info;
++	struct list_head list;
++	u32 ampdu_mib_total_BA_counter;
++	AMPDU_TID ampdu_tid[WMM_TID_NUM];
++	bool has_hw_encrypt;
++	bool need_sw_encrypt;
++	bool has_hw_decrypt;
++	bool need_sw_decrypt;
++	bool use_mac80211_decrypt;
++	u8 group_key_idx;
++	u32 beacon_rssi;
++};
++struct ssv_vif_priv_data {
++	int vif_idx;
++	struct list_head sta_list;
++	u32 sta_asleep_mask;
++	u32 pair_cipher;
++	u32 group_cipher;
++	bool is_security_valid;
++	bool has_hw_encrypt;
++	bool need_sw_encrypt;
++	bool has_hw_decrypt;
++	bool need_sw_decrypt;
++	bool use_mac80211_decrypt;
++	bool force_sw_encrypt;
++	u8 group_key_idx;
++};
++#define SC_OP_INVALID 0x00000001
++#define SC_OP_HW_RESET 0x00000002
++#define SC_OP_OFFCHAN 0x00000004
++#define SC_OP_FIXED_RATE 0x00000008
++#define SC_OP_SHORT_PREAMBLE 0x00000010
++struct ssv6xxx_beacon_info {
++	u32 pubf_addr;
++	u16 len;
++	u8 tim_offset;
++	u8 tim_cnt;
++};
++#define SSV6200_MAX_BCAST_QUEUE_LEN 16
++struct ssv6xxx_bcast_txq {
++	spinlock_t txq_lock;
++	struct sk_buff_head qhead;
++	int cur_qsize;
++};
++#ifdef DEBUG_AMPDU_FLUSH
++typedef struct AMPDU_TID_st AMPDU_TID;
++#define MAX_TID (24)
++#endif
++struct ssv_softc {
++	struct ieee80211_hw *hw;
++	struct device *dev;
++	u32 restart_counter;
++	bool force_triger_reset;
++	unsigned long sdio_throughput_timestamp;
++	unsigned long sdio_rx_evt_size;
++#if LINUX_VERSION_CODE < KERNEL_VERSION(4,7,0)
++	struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
++#else
++	struct ieee80211_supported_band sbands[NUM_NL80211_BANDS];
++#endif
++	struct ieee80211_channel *cur_channel;
++	u16 hw_chan;
++	struct mutex mutex;
++	struct ssv_hw *sh;
++	struct ssv_tx tx;
++	struct ssv_rx rx;
++	struct ssv_vif_info vif_info[SSV_NUM_VIF];
++	struct ssv_sta_info sta_info[SSV_NUM_STA];
++	struct ieee80211_vif *ap_vif;
++	u8 nvif;
++	u32 sc_flags;
++	void *rc;
++	int max_rate_idx;
++	struct workqueue_struct *rc_sample_workqueue;
++	struct sk_buff_head rc_report_queue;
++	struct work_struct rc_sample_work;
++#ifdef DEBUG_AMPDU_FLUSH
++	struct AMPDU_TID_st *tid[MAX_TID];
++#endif
++	u16 rc_sample_sechedule;
++	u16 *mac_deci_tbl;
++	struct workqueue_struct *config_wq;
++	bool bq4_dtim;
++	struct work_struct set_tim_work;
++	u8 enable_beacon;
++	u8 beacon_interval;
++	u8 beacon_dtim_cnt;
++	u8 beacon_usage;
++	struct ssv6xxx_beacon_info beacon_info[2];
++	struct sk_buff *beacon_buf;
++	struct work_struct bcast_start_work;
++	struct delayed_work bcast_stop_work;
++	struct delayed_work bcast_tx_work;
++	struct delayed_work thermal_monitor_work;
++	struct workqueue_struct *thermal_wq;
++	int is_sar_enabled;
++	bool aid0_bit_set;
++	u8 hw_mng_used;
++	struct ssv6xxx_bcast_txq bcast_txq;
++	int bcast_interval;
++	u8 bssid[6];
++	struct mutex mem_mutex;
++	spinlock_t ps_state_lock;
++	u8 hw_wsid_bit;
++	int rx_ba_session_count;
++	struct ieee80211_sta *rx_ba_sta;
++	u8 rx_ba_bitmap;
++	u8 ba_ra_addr[ETH_ALEN];
++	u16 ba_tid;
++	u16 ba_ssn;
++	struct work_struct set_ampdu_rx_add_work;
++	struct work_struct set_ampdu_rx_del_work;
++	bool isAssoc;
++	u16 channel_center_freq;
++	bool bScanning;
++	int ps_status;
++	u16 ps_aid;
++	u16 tx_wait_q_woken;
++	wait_queue_head_t tx_wait_q;
++	struct sk_buff_head tx_skb_q;
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	u32 max_tx_skb_q_len;
++#endif
++	struct task_struct *tx_task;
++	bool tx_q_empty;
++	struct sk_buff_head tx_done_q;
++	u16 rx_wait_q_woken;
++	wait_queue_head_t rx_wait_q;
++	struct sk_buff_head rx_skb_q;
++	struct task_struct *rx_task;
++	bool dbg_rx_frame;
++	bool dbg_tx_frame;
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	struct dentry *debugfs_dir;
++#endif
++#ifdef CONFIG_P2P_NOA
++	struct ssv_p2p_noa p2p_noa;
++#endif
++	struct timer_list watchdog_timeout;
++	u32 watchdog_flag;
++	wait_queue_head_t fw_wait_q;
++	u32 iq_cali_done;
++	u32 sr_bhvr;
++};
++enum {
++	IQ_CALI_RUNNING,
++	IQ_CALI_OK,
++	IQ_CALI_FAILED
++};
++enum {
++	WD_SLEEP,
++	WD_BARKING,
++	WD_KICKED,
++	WD_MAX
++};
++void ssv6xxx_txbuf_free_skb(struct sk_buff *skb, void *args);
++void ssv6200_rx_process(struct work_struct *work);
++#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
++int ssv6200_rx(struct sk_buff_head *rx_skb_q, void *args);
++#else
++int ssv6200_rx(struct sk_buff *rx_skb, void *args);
++#endif
++void ssv6xxx_tx_cb(struct sk_buff_head *skb_head, void *args);
++void ssv6xxx_tx_rate_update(struct sk_buff *skb, void *args);
++int ssv6200_tx_flow_control(void *dev, int hw_txqid, bool fc_en, int debug);
++void ssv6xxx_tx_q_empty_cb(u32 txq_no, void *);
++int ssv6xxx_rf_disable(struct ssv_hw *sh);
++int ssv6xxx_rf_enable(struct ssv_hw *sh);
++int ssv6xxx_set_channel(struct ssv_softc *sc, int ch);
++#ifdef CONFIG_SSV_SMARTLINK
++int ssv6xxx_get_channel(struct ssv_softc *sc, int *pch);
++int ssv6xxx_set_promisc(struct ssv_softc *sc, int accept);
++int ssv6xxx_get_promisc(struct ssv_softc *sc, int *paccept);
++#endif
++int ssv6xxx_tx_task(void *data);
++int ssv6xxx_rx_task(void *data);
++u32 ssv6xxx_pbuf_alloc(struct ssv_softc *sc, int size, int type);
++bool ssv6xxx_pbuf_free(struct ssv_softc *sc, u32 pbuf_addr);
++void ssv6xxx_add_txinfo(struct ssv_softc *sc, struct sk_buff *skb);
++void ssv6xxx_update_txinfo(struct ssv_softc *sc, struct sk_buff *skb);
++int ssv6xxx_update_decision_table(struct ssv_softc *sc);
++void ssv6xxx_ps_callback_func(unsigned long data);
++void ssv6xxx_enable_ps(struct ssv_softc *sc);
++void ssv6xxx_disable_ps(struct ssv_softc *sc);
++int ssv6xxx_watchdog_controller(struct ssv_hw *sh, u8 flag);
++int ssv6xxx_skb_encrypt(struct sk_buff *mpdu, struct ssv_softc *sc);
++int ssv6xxx_skb_decrypt(struct sk_buff *mpdu, struct ieee80211_sta *sta,
++			struct ssv_softc *sc);
++void ssv6200_sync_hw_key_sequence(struct ssv_softc *sc,
++				  struct ssv_sta_info *sta_info, bool bWrite);
++struct ieee80211_sta *ssv6xxx_find_sta_by_rx_skb(struct ssv_softc *sc,
++						 struct sk_buff *skb);
++struct ieee80211_sta *ssv6xxx_find_sta_by_addr(struct ssv_softc *sc,
++					       u8 addr[6]);
++void ssv6xxx_foreach_sta(struct ssv_softc *sc,
++			 void (*sta_func)(struct ssv_softc *,
++					  struct ssv_sta_info *, void *),
++			 void *param);
++void ssv6xxx_foreach_vif_sta(struct ssv_softc *sc,
++			     struct ssv_vif_info *vif_info,
++			     void (*sta_func)(struct ssv_softc *,
++					      struct ssv_vif_info *,
++					      struct ssv_sta_info *, void *),
++			     void *param);
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++ssize_t ssv6xxx_tx_queue_status_dump(struct ssv_softc *sc, char *status_buf,
++				     ssize_t buf_size);
++#endif
++#endif
+diff --git a/drivers/net/wireless/ssv6051/smac/dev_tbl.h b/drivers/net/wireless/ssv6051/smac/dev_tbl.h
+new file mode 100644
+index 000000000000..5c49d0bde6a6
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/dev_tbl.h
+@@ -0,0 +1,141 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation, either version 3 of the License, or
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _DEV_TBL_H_
++#define _DEV_TBL_H_
++#include "ssv6200_configuration.h"
++#include "drv_comm.h"
++struct ssv6xxx_dev_table {
++	u32 address;
++	u32 data;
++};
++#define ssv6200_phy_tbl phy_setting
++#define ssv6200_rf_tbl asic_rf_setting
++#define ACTION_DO_NOTHING 0
++#define ACTION_UPDATE_NAV 1
++#define ACTION_RESET_NAV 2
++#define ACTION_SIGNAL_ACK 3
++#define FRAME_ACCEPT 0
++#define FRAME_DROP 1
++#define SET_DEC_TBL(_type,_mask,_action,_drop) \
++    (_type<<9| \
++    _mask <<3| \
++    _action<<1| \
++    _drop)
++u16 generic_deci_tbl[] = {
++	SET_DEC_TBL(0x1e, 0x3e, ACTION_RESET_NAV, FRAME_DROP),
++	SET_DEC_TBL(0x18, 0x3e, ACTION_SIGNAL_ACK, FRAME_ACCEPT),
++	SET_DEC_TBL(0x1a, 0x3f, ACTION_DO_NOTHING, FRAME_ACCEPT),
++	SET_DEC_TBL(0x10, 0x38, ACTION_DO_NOTHING, FRAME_DROP),
++	0,
++	0,
++	0,
++	SET_DEC_TBL(0x05, 0x3f, ACTION_SIGNAL_ACK, FRAME_ACCEPT),
++	SET_DEC_TBL(0x0b, 0x3f, ACTION_SIGNAL_ACK, FRAME_ACCEPT),
++	SET_DEC_TBL(0x01, 0x3d, ACTION_SIGNAL_ACK, FRAME_ACCEPT),
++	SET_DEC_TBL(0x00, 0x00, ACTION_DO_NOTHING, FRAME_ACCEPT),
++	SET_DEC_TBL(0x00, 0x00, ACTION_SIGNAL_ACK, FRAME_ACCEPT),
++	SET_DEC_TBL(0x00, 0x00, ACTION_DO_NOTHING, FRAME_DROP),
++	SET_DEC_TBL(0x00, 0x00, ACTION_UPDATE_NAV, FRAME_DROP),
++	SET_DEC_TBL(0x00, 0x00, ACTION_RESET_NAV, FRAME_DROP),
++	SET_DEC_TBL(0x00, 0x00, ACTION_SIGNAL_ACK, FRAME_DROP),
++	0x2008,
++	0x1001,
++	0x0400,
++	0x0400,
++	0x2000,
++	0x800E,
++	0x0800,
++	0x0B88,
++	0x0800,
++};
++
++#define SET_PHY_INFO(_ctsdur,_ba_rate_idx,_ack_rate_idx,_llength_idx,_llength_enable) \
++         (_ctsdur<<16| \
++         _ba_rate_idx <<10| \
++         _ack_rate_idx<<4| \
++         _llength_idx<<1| \
++         _llength_enable)
++#define SET_PHY_L_LENGTH(_l_ba,_l_rts,_l_cts_ack) (_l_ba<<12|_l_rts<<6 |_l_cts_ack)
++static u32 phy_info_6051z[] = {
++	0x18000000, 0x18000100, 0x18000200, 0x18000300, 0x18000140,
++	0x18000240, 0x18000340, 0x0C000001, 0x0C000101, 0x0C000201,
++	0x0C000301, 0x18000401, 0x18000501, 0x18000601, 0x18000701,
++	0x0C030002, 0x0C030102, 0x0C030202, 0x18030302, 0x18030402,
++	0x18030502, 0x18030602, 0x1C030702, 0x0C030082, 0x0C030182,
++	0x0C030282, 0x18030382, 0x18030482, 0x18030582, 0x18030682,
++	0x1C030782, 0x0C030042, 0x0C030142, 0x0C030242, 0x18030342,
++	0x18030442, 0x18030542, 0x18030642, 0x1C030742
++};
++
++static u32 phy_info_tbl[] = {
++	0x0C000000, 0x0C000100, 0x0C000200, 0x0C000300, 0x0C000140,
++	0x0C000240, 0x0C000340, 0x00000001, 0x00000101, 0x00000201,
++	0x00000301, 0x0C000401, 0x0C000501, 0x0C000601, 0x0C000701,
++	0x00030002, 0x00030102, 0x00030202, 0x0C030302, 0x0C030402,
++	0x0C030502, 0x0C030602, 0x10030702, 0x00030082, 0x00030182,
++	0x00030282, 0x0C030382, 0x0C030482, 0x0C030582, 0x0C030682,
++	0x10030782, 0x00030042, 0x00030142, 0x00030242, 0x0C030342,
++	0x0C030442, 0x0C030542, 0x0C030642, 0x10030742,
++	SET_PHY_INFO(314, 0, 0, 0, 0),
++	SET_PHY_INFO(258, 0, 1, 0, 0),
++	SET_PHY_INFO(223, 0, 1, 0, 0),
++	SET_PHY_INFO(213, 0, 1, 0, 0),
++	SET_PHY_INFO(162, 0, 4, 0, 0),
++	SET_PHY_INFO(127, 0, 4, 0, 0),
++	SET_PHY_INFO(117, 0, 4, 0, 0),
++	SET_PHY_INFO(60, 7, 7, 0, 0),
++	SET_PHY_INFO(52, 7, 7, 0, 0),
++	SET_PHY_INFO(48, 9, 9, 0, 0),
++	SET_PHY_INFO(44, 9, 9, 0, 0),
++	SET_PHY_INFO(44, 11, 11, 0, 0),
++	SET_PHY_INFO(40, 11, 11, 0, 0),
++	SET_PHY_INFO(40, 11, 11, 0, 0),
++	SET_PHY_INFO(40, 11, 11, 0, 0),
++	SET_PHY_INFO(76, 7, 7, 0, 1),
++	SET_PHY_INFO(64, 9, 9, 1, 1),
++	SET_PHY_INFO(60, 9, 9, 2, 1),
++	SET_PHY_INFO(60, 11, 11, 3, 1),
++	SET_PHY_INFO(56, 11, 11, 4, 1),
++	SET_PHY_INFO(56, 11, 11, 5, 1),
++	SET_PHY_INFO(56, 11, 11, 5, 1),
++	SET_PHY_INFO(56, 11, 11, 5, 1),
++	SET_PHY_INFO(76, 7, 7, 6, 1),
++	SET_PHY_INFO(64, 9, 9, 1, 1),
++	SET_PHY_INFO(60, 9, 9, 2, 1),
++	SET_PHY_INFO(60, 11, 11, 3, 1),
++	SET_PHY_INFO(56, 11, 11, 4, 1),
++	SET_PHY_INFO(56, 11, 11, 5, 1),
++	SET_PHY_INFO(56, 11, 11, 5, 1),
++	SET_PHY_INFO(56, 11, 11, 5, 1),
++	SET_PHY_INFO(64, 7, 7, 0, 0),
++	SET_PHY_INFO(52, 9, 9, 0, 0),
++	SET_PHY_INFO(48, 9, 9, 0, 0),
++	SET_PHY_INFO(48, 11, 11, 0, 0),
++	SET_PHY_INFO(44, 11, 11, 0, 0),
++	SET_PHY_INFO(44, 11, 11, 0, 0),
++	SET_PHY_INFO(44, 11, 11, 0, 0),
++	SET_PHY_INFO(44, 11, 11, 0, 0),
++	SET_PHY_L_LENGTH(50, 38, 35),
++	SET_PHY_L_LENGTH(35, 29, 26),
++	SET_PHY_L_LENGTH(29, 26, 23),
++	SET_PHY_L_LENGTH(26, 23, 23),
++	SET_PHY_L_LENGTH(23, 23, 20),
++	SET_PHY_L_LENGTH(23, 20, 20),
++	SET_PHY_L_LENGTH(47, 38, 35),
++	SET_PHY_L_LENGTH(0, 0, 0),
++};
++#endif
+diff --git a/drivers/net/wireless/ssv6051/smac/drv_comm.h b/drivers/net/wireless/ssv6051/smac/drv_comm.h
+new file mode 100644
+index 000000000000..f04fbae004c3
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/drv_comm.h
+@@ -0,0 +1,61 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation, either version 3 of the License, or
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _DRV_COMM_H_
++#define _DRV_COMM_H_
++#define PHY_INFO_TBL1_SIZE 39
++#define PHY_INFO_TBL2_SIZE 39
++#define PHY_INFO_TBL3_SIZE 8
++#define ampdu_fw_rate_info_status_no_use BIT(0)
++#define ampdu_fw_rate_info_status_in_use BIT(1)
++#define ampdu_fw_rate_info_status_reset BIT(2)
++#define SSV_NUM_STA 8
++#define SSV_NUM_VIF 2
++#define SECURITY_KEY_LEN (32)
++enum SSV_CIPHER_E {
++	SSV_CIPHER_NONE,
++	SSV_CIPHER_WEP40,
++	SSV_CIPHER_WEP104,
++	SSV_CIPHER_TKIP,
++	SSV_CIPHER_CCMP,
++	SSV_CIPHER_SMS4,
++	SSV_CIPHER_INVALID = (-1)
++};
++#define ME_NONE 0
++#define ME_WEP40 1
++#define ME_WEP104 2
++#define ME_TKIP 3
++#define ME_CCMP 4
++#define ME_SMS4 5
++struct ssv6xxx_hw_key {
++	u8 key[SECURITY_KEY_LEN];
++	u32 tx_pn_l;
++	u32 tx_pn_h;
++	u32 rx_pn_l;
++	u32 rx_pn_h;
++} __attribute__((packed));
++struct ssv6xxx_hw_sta_key {
++	u8 pair_key_idx:4;
++	u8 group_key_idx:4;
++	u8 valid;
++	u8 reserve[2];
++	struct ssv6xxx_hw_key pair;
++} __attribute__((packed));
++struct ssv6xxx_hw_sec {
++	struct ssv6xxx_hw_key group_key[3];
++	struct ssv6xxx_hw_sta_key sta_key[8];
++} __attribute__((packed));
++#endif
+diff --git a/drivers/net/wireless/ssv6051/smac/efuse.c b/drivers/net/wireless/ssv6051/smac/efuse.c
+new file mode 100644
+index 000000000000..9a1f3f5488f2
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/efuse.c
+@@ -0,0 +1,334 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation, either version 3 of the License, or
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <linux/etherdevice.h>
++#include <ssv6200.h>
++#include "efuse.h"
++
++struct file *openFile(char *path, int flag, int mode)
++{
++	struct file *fp = NULL;
++	fp = filp_open(path, flag, 0);
++	if (IS_ERR(fp))
++		return NULL;
++	else
++		return fp;
++}
++
++int readFile(struct file *fp, char *buf, int readlen)
++{
++	if (fp->f_op && fp->f_op->read)
++		return fp->f_op->read(fp, buf, readlen, &fp->f_pos);
++	else
++		return -1;
++}
++
++int closeFile(struct file *fp)
++{
++	filp_close(fp, NULL);
++	return 0;
++}
++
++void initKernelEnv(void)
++{
++}
++
++void parseMac(char *mac, u_int8_t addr[])
++{
++	long b;
++	int i;
++	for (i = 0; i < 6; i++) {
++		b = simple_strtol(mac + (3 * i), (char **)NULL, 16);
++		addr[i] = (char)b;
++	}
++}
++
++static int readfile_mac(u8 * path, u8 * mac_addr)
++{
++	char buf[128];
++	struct file *fp = NULL;
++	int ret = 0;
++	fp = openFile(path, O_RDONLY, 0);
++	if (fp != NULL) {
++		initKernelEnv();
++		memset(buf, 0, 128);
++		if ((ret = readFile(fp, buf, 128)) > 0) {
++			parseMac(buf, (uint8_t *) mac_addr);
++		} else
++			pr_err("read file error %d=[%s]\n", ret, path);
++		closeFile(fp);
++	} else
++		pr_err("Read open File fail[%s]!!!! \n", path);
++	return ret;
++}
++
++static int write_mac_to_file(u8 * mac_path, u8 * mac_addr)
++{
++	char buf[128];
++	struct file *fp = NULL;
++	int ret = 0, len;
++	fp = openFile(mac_path, O_WRONLY | O_CREAT, 0640);
++	if (fp != NULL) {
++		initKernelEnv();
++		memset(buf, 0, 128);
++		sprintf(buf, "%x:%x:%x:%x:%x:%x", mac_addr[0], mac_addr[1],
++			mac_addr[2], mac_addr[3], mac_addr[4], mac_addr[5]);
++		len = strlen(buf) + 1;
++		fp->f_op->write(fp, (char *)buf, len, &fp->f_pos);
++		closeFile(fp);
++	} else
++		pr_err("Write open File fail!!!![%s] \n", mac_path);
++	return ret;
++}
++
++static struct efuse_map SSV_EFUSE_ITEM_TABLE[] = {
++	{4, 0, 0},
++	{4, 8, 0},
++	{4, 8, 0},
++	{4, 48, 0},
++	{4, 8, 0},
++	{4, 8, 0},
++	{4, 8, 0},
++};
++
++static u8 read_efuse(struct ssv_hw *sh, u8 * pbuf)
++{
++	extern struct ssv6xxx_cfg ssv_cfg;
++	u32 val, i;
++	u32 *temp = (u32 *) pbuf;
++	SMAC_REG_WRITE(sh, 0xC0000328, 0x11);
++	SMAC_REG_WRITE(sh, SSV_EFUSE_ID_READ_SWITCH, 0x1);
++	SMAC_REG_READ(sh, SSV_EFUSE_ID_RAW_DATA_BASE, &val);
++	ssv_cfg.chip_identity = val;
++	SMAC_REG_WRITE(sh, SSV_EFUSE_READ_SWITCH, 0x1);
++	SMAC_REG_READ(sh, SSV_EFUSE_RAW_DATA_BASE, &val);
++	if (val == 0x00) {
++		return 0;
++	}
++	for (i = 0; i < (EFUSE_MAX_SECTION_MAP); i++) {
++		SMAC_REG_WRITE(sh, SSV_EFUSE_READ_SWITCH + i * 4, 0x1);
++		SMAC_REG_READ(sh, SSV_EFUSE_RAW_DATA_BASE + i * 4, &val);
++		*temp++ = val;
++	}
++	SMAC_REG_WRITE(sh, 0xC0000328, 0x1800000a);
++	return 1;
++}
++
++static u16 parser_efuse(u8 * pbuf, u8 * mac_addr)
++{
++	u8 *rtemp8, idx = 0;
++	u16 shift = 0, i;
++	u16 efuse_real_content_len = 0;
++	rtemp8 = pbuf;
++	if (*rtemp8 == 0x00) {
++		return efuse_real_content_len;
++	}
++	do {
++		idx = (*(rtemp8) >> shift) & 0xf;
++		switch (idx) {
++		case EFUSE_R_CALIBRATION_RESULT:
++		case EFUSE_CRYSTAL_FREQUENCY_OFFSET:
++		case EFUSE_TX_POWER_INDEX_1:
++		case EFUSE_TX_POWER_INDEX_2:
++		case EFUSE_SAR_RESULT:
++			if (shift) {
++				rtemp8++;
++				SSV_EFUSE_ITEM_TABLE[idx].value =
++				    (u16) ((u8) (*((u16 *) rtemp8)) &
++					   ((1 <<
++					     SSV_EFUSE_ITEM_TABLE
++					     [idx].byte_cnts) - 1));
++			} else {
++				SSV_EFUSE_ITEM_TABLE[idx].value =
++				    (u16) ((u8) (*((u16 *) rtemp8) >> 4) &
++					   ((1 <<
++					     SSV_EFUSE_ITEM_TABLE
++					     [idx].byte_cnts) - 1));
++			}
++			efuse_real_content_len +=
++			    (SSV_EFUSE_ITEM_TABLE[idx].offset +
++			     SSV_EFUSE_ITEM_TABLE[idx].byte_cnts);
++			break;
++		case EFUSE_MAC:
++			if (shift) {
++				rtemp8++;
++				memcpy(mac_addr, rtemp8, 6);
++			} else {
++				for (i = 0; i < 6; i++) {
++					mac_addr[i] =
++					    (u16) (*((u16 *) rtemp8) >> 4) &
++					    0xff;
++					rtemp8++;
++				}
++			}
++			efuse_real_content_len +=
++			    (SSV_EFUSE_ITEM_TABLE[idx].offset +
++			     SSV_EFUSE_ITEM_TABLE[idx].byte_cnts);
++			break;
++		default:
++			idx = 0;
++			break;
++		}
++		shift = efuse_real_content_len % 8;
++		rtemp8 = &pbuf[efuse_real_content_len / 8];
++	} while (idx != 0);
++	return efuse_real_content_len;
++}
++
++void addr_increase_copy(u8 * dst, u8 * src)
++{
++	u8 *a = (u8 *) dst;
++	const u8 *b = (const u8 *)src;
++	a[0] = b[0];
++	a[1] = b[1];
++	a[2] = b[2];
++	a[3] = b[3];
++	a[4] = b[4];
++	if (b[5] & 0x1)
++		a[5] = b[5] - 1;
++	else
++		a[5] = b[5] + 1;
++}
++
++static u8 key_char2num(u8 ch)
++{
++	if ((ch >= '0') && (ch <= '9'))
++		return ch - '0';
++	else if ((ch >= 'a') && (ch <= 'f'))
++		return ch - 'a' + 10;
++	else if ((ch >= 'A') && (ch <= 'F'))
++		return ch - 'A' + 10;
++	else
++		return 0xff;
++}
++
++u8 key_2char2num(u8 hch, u8 lch)
++{
++	return ((key_char2num(hch) << 4) | key_char2num(lch));
++}
++
++extern struct ssv6xxx_cfg ssv_cfg;
++extern char *ssv_initmac;
++void efuse_read_all_map(struct ssv_hw *sh)
++{
++	u8 mac[ETH_ALEN] = { 0 };
++	int jj, kk;
++	u8 efuse_mapping_table[EFUSE_HWSET_MAX_SIZE / 8];
++#ifndef CONFIG_SSV_RANDOM_MAC
++	u8 pseudo_mac0[ETH_ALEN] = { 0x00, 0x33, 0x33, 0x33, 0x33, 0x33 };
++#endif
++	u8 rom_mac0[ETH_ALEN];
++	memset(rom_mac0, 0x00, ETH_ALEN);
++	memset(efuse_mapping_table, 0x00, EFUSE_HWSET_MAX_SIZE / 8);
++	read_efuse(sh, efuse_mapping_table);
++	parser_efuse(efuse_mapping_table, rom_mac0);
++	ssv_cfg.r_calbration_result =
++	    (u8) SSV_EFUSE_ITEM_TABLE[EFUSE_R_CALIBRATION_RESULT].value;
++	ssv_cfg.sar_result = (u8) SSV_EFUSE_ITEM_TABLE[EFUSE_SAR_RESULT].value;
++	ssv_cfg.crystal_frequency_offset =
++	    (u8) SSV_EFUSE_ITEM_TABLE[EFUSE_CRYSTAL_FREQUENCY_OFFSET].value;
++	ssv_cfg.tx_power_index_1 =
++	    (u8) SSV_EFUSE_ITEM_TABLE[EFUSE_TX_POWER_INDEX_1].value;
++	ssv_cfg.tx_power_index_2 =
++	    (u8) SSV_EFUSE_ITEM_TABLE[EFUSE_TX_POWER_INDEX_2].value;
++	if (!is_valid_ether_addr(&sh->cfg.maddr[0][0])) {
++		if (!sh->cfg.ignore_efuse_mac) {
++			if (is_valid_ether_addr(rom_mac0)) {
++				dev_info(sh->sc->dev, "Using MAC address from e-fuse\n");
++				memcpy(&sh->cfg.maddr[0][0], rom_mac0,
++				       ETH_ALEN);
++				addr_increase_copy(&sh->cfg.maddr[1][0],
++						   rom_mac0);
++				goto Done;
++			}
++		}
++		if (ssv_initmac != NULL) {
++			for (jj = 0, kk = 0; jj < ETH_ALEN; jj++, kk += 3) {
++				mac[jj] =
++				    key_2char2num(ssv_initmac[kk],
++						  ssv_initmac[kk + 1]);
++			}
++			if (is_valid_ether_addr(mac)) {
++				dev_info(sh->sc->dev, "Using MAC address from module option\n");
++				memcpy(&sh->cfg.maddr[0][0], mac, ETH_ALEN);
++				addr_increase_copy(&sh->cfg.maddr[1][0], mac);
++				goto Done;
++			}
++		}
++		if (sh->cfg.mac_address_path[0] != 0x00) {
++			if ((readfile_mac
++			     (sh->cfg.mac_address_path, &sh->cfg.maddr[0][0]))
++			    && (is_valid_ether_addr(&sh->cfg.maddr[0][0]))) {
++				dev_info
++				    (sh->sc->dev, "Using MAC address from configuration file\n");
++				addr_increase_copy(&sh->cfg.maddr[1][0],
++						   &sh->cfg.maddr[0][0]);
++				goto Done;
++			}
++		}
++		switch (sh->cfg.mac_address_mode) {
++		case 1:
++			get_random_bytes(&sh->cfg.maddr[0][0], ETH_ALEN);
++			sh->cfg.maddr[0][0] = sh->cfg.maddr[0][0] & 0xF0;
++			addr_increase_copy(&sh->cfg.maddr[1][0],
++					   &sh->cfg.maddr[0][0]);
++			break;
++		case 2:
++			if ((readfile_mac
++			     (sh->cfg.mac_output_path, &sh->cfg.maddr[0][0]))
++			    && (is_valid_ether_addr(&sh->cfg.maddr[0][0]))) {
++				addr_increase_copy(&sh->cfg.maddr[1][0],
++						   &sh->cfg.maddr[0][0]);
++			} else {
++				{
++					get_random_bytes(&sh->cfg.maddr[0][0],
++							 ETH_ALEN);
++					sh->cfg.maddr[0][0] =
++					    sh->cfg.maddr[0][0] & 0xF0;
++					addr_increase_copy(&sh->cfg.maddr[1][0],
++							   &sh->
++							   cfg.maddr[0][0]);
++					if (sh->cfg.mac_output_path[0] != 0x00)
++						write_mac_to_file(sh->
++								  cfg.mac_output_path,
++								  &sh->
++								  cfg.maddr[0]
++								  [0]);
++				}
++			}
++			break;
++		default:
++			memcpy(&sh->cfg.maddr[0][0], pseudo_mac0, ETH_ALEN);
++			addr_increase_copy(&sh->cfg.maddr[1][0], pseudo_mac0);
++			break;
++		}
++		dev_info(sh->sc->dev, "MAC address from Software MAC mode[%d]\n",
++			sh->cfg.mac_address_mode);
++	}
++ Done:
++	dev_info(sh->sc->dev, "Chip identity from efuse: %08x\n", ssv_cfg.chip_identity);
++	dev_dbg(sh->sc->dev, "r_calbration_result- %x\n", ssv_cfg.r_calbration_result);
++	dev_dbg(sh->sc->dev, "sar_result- %x\n", ssv_cfg.sar_result);
++	dev_dbg(sh->sc->dev, "crystal_frequency_offset- %x\n",
++		 ssv_cfg.crystal_frequency_offset);
++	dev_dbg(sh->sc->dev, "tx_power_index_1- %x\n", ssv_cfg.tx_power_index_1);
++	dev_dbg(sh->sc->dev, "tx_power_index_2- %x\n", ssv_cfg.tx_power_index_2);
++	dev_dbg(sh->sc->dev, "MAC address - %pM\n", rom_mac0);
++	sh->cfg.crystal_frequency_offset = ssv_cfg.crystal_frequency_offset;
++	sh->cfg.tx_power_index_1 = ssv_cfg.tx_power_index_1;
++	sh->cfg.tx_power_index_2 = ssv_cfg.tx_power_index_2;
++	sh->cfg.chip_identity = ssv_cfg.chip_identity;
++}
+diff --git a/drivers/net/wireless/ssv6051/smac/efuse.h b/drivers/net/wireless/ssv6051/smac/efuse.h
+new file mode 100644
+index 000000000000..c25280c5abad
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/efuse.h
+@@ -0,0 +1,40 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation, either version 3 of the License, or
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _SSV_EFUSE_H_
++#define _SSV_EFUSE_H_
++#include "dev.h"
++struct efuse_map {
++	u8 offset;
++	u8 byte_cnts;
++	u16 value;
++};
++enum efuse_data_item {
++	EFUSE_R_CALIBRATION_RESULT = 1,
++	EFUSE_SAR_RESULT,
++	EFUSE_MAC,
++	EFUSE_CRYSTAL_FREQUENCY_OFFSET,
++	EFUSE_TX_POWER_INDEX_1,
++	EFUSE_TX_POWER_INDEX_2
++};
++#define EFUSE_HWSET_MAX_SIZE (256-32)
++#define EFUSE_MAX_SECTION_MAP (EFUSE_HWSET_MAX_SIZE>>5)
++#define SSV_EFUSE_ID_READ_SWITCH 0xC2000128
++#define SSV_EFUSE_ID_RAW_DATA_BASE 0xC200014C
++#define SSV_EFUSE_READ_SWITCH 0xC200012C
++#define SSV_EFUSE_RAW_DATA_BASE 0xC2000150
++void efuse_read_all_map(struct ssv_hw *sh);
++#endif
+diff --git a/drivers/net/wireless/ssv6051/smac/init.c b/drivers/net/wireless/ssv6051/smac/init.c
+new file mode 100644
+index 000000000000..592c52a28381
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/init.c
+@@ -0,0 +1,1347 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation, either version 3 of the License, or
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/nl80211.h>
++#include <linux/kthread.h>
++#include <linux/etherdevice.h>
++#include <linux/version.h>
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,6,0)
++#include <crypto/hash.h>
++#else
++#include <linux/crypto.h>
++#endif
++#include <ssv6200.h>
++#include <hci/hctrl.h>
++#include <ssv_firmware_version.h>
++#include "dev_tbl.h"
++#include "dev.h"
++#include "lib.h"
++#include "ssv_rc.h"
++#include "ap.h"
++#include "efuse.h"
++#include "sar.h"
++#include "ssv_cfgvendor.h"
++
++#include "linux_80211.h"
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++#include "ssv6xxx_debugfs.h"
++#endif
++
++#define WIFI_FIRMWARE_NAME "ssv6051-sw.bin"
++static const struct ieee80211_iface_limit ssv6xxx_p2p_limits[] = {
++	{
++	 .max = 2,
++	 .types = BIT(NL80211_IFTYPE_STATION),
++	 },
++	{
++	 .max = 1,
++	 .types = BIT(NL80211_IFTYPE_P2P_GO) |
++	 BIT(NL80211_IFTYPE_P2P_CLIENT) | BIT(NL80211_IFTYPE_AP),
++	 },
++};
++
++static const struct ieee80211_iface_combination
++ ssv6xxx_iface_combinations_p2p[] = {
++	{.num_different_channels = 1,
++	 .max_interfaces = SSV6200_MAX_VIF,
++	 .beacon_int_infra_match = true,
++	 .limits = ssv6xxx_p2p_limits,
++	 .n_limits = ARRAY_SIZE(ssv6xxx_p2p_limits),
++	 },
++};
++
++#define LBYTESWAP(a) ((((a) & 0x00ff00ff) << 8) | \
++    (((a) & 0xff00ff00) >> 8))
++#define LONGSWAP(a) ((LBYTESWAP(a) << 16) | (LBYTESWAP(a) >> 16))
++#define CHAN2G(_freq,_idx) { \
++    .band = INDEX_80211_BAND_2GHZ, \
++    .center_freq = (_freq), \
++    .hw_value = (_idx), \
++    .max_power = 20, \
++}
++#ifndef WLAN_CIPHER_SUITE_SMS4
++#define WLAN_CIPHER_SUITE_SMS4 0x00147201
++#endif
++#define SHPCHECK(__hw_rate,__flags) \
++    ((__flags & IEEE80211_RATE_SHORT_PREAMBLE) ? (__hw_rate +3 ) : 0)
++#define RATE(_bitrate,_hw_rate,_flags) { \
++    .bitrate = (_bitrate), \
++    .flags = (_flags), \
++    .hw_value = (_hw_rate), \
++    .hw_value_short = SHPCHECK(_hw_rate,_flags) \
++}
++extern struct ssv6xxx_cfg ssv_cfg;
++static const struct ieee80211_channel ssv6200_2ghz_chantable[] = {
++	CHAN2G(2412, 1),
++	CHAN2G(2417, 2),
++	CHAN2G(2422, 3),
++	CHAN2G(2427, 4),
++	CHAN2G(2432, 5),
++	CHAN2G(2437, 6),
++	CHAN2G(2442, 7),
++	CHAN2G(2447, 8),
++	CHAN2G(2452, 9),
++	CHAN2G(2457, 10),
++	CHAN2G(2462, 11),
++	CHAN2G(2467, 12),
++	CHAN2G(2472, 13),
++	CHAN2G(2484, 14),
++};
++
++static struct ieee80211_rate ssv6200_legacy_rates[] = {
++	RATE(10, 0x00, 0),
++	RATE(20, 0x01, IEEE80211_RATE_SHORT_PREAMBLE),
++	RATE(55, 0x02, IEEE80211_RATE_SHORT_PREAMBLE),
++	RATE(110, 0x03, IEEE80211_RATE_SHORT_PREAMBLE),
++	RATE(60, 0x07, 0),
++	RATE(90, 0x08, 0),
++	RATE(120, 0x09, 0),
++	RATE(180, 0x0a, 0),
++	RATE(240, 0x0b, 0),
++	RATE(360, 0x0c, 0),
++	RATE(480, 0x0d, 0),
++	RATE(540, 0x0e, 0),
++};
++
++struct ssv6xxx_ch_cfg ch_cfg_z[] = {
++	{ADR_ABB_REGISTER_1, 0, 0x151559fc},
++	{ADR_LDO_REGISTER, 0, 0x00eb7c1c},
++	{ADR_RX_ADC_REGISTER, 0, 0x20d000d2}
++};
++
++struct ssv6xxx_ch_cfg ch_cfg_p[] = {
++	{ADR_ABB_REGISTER_1, 0, 0x151559fc},
++	{ADR_RX_ADC_REGISTER, 0, 0x20d000d2}
++};
++
++int ssv6xxx_do_iq_calib(struct ssv_hw *sh, struct ssv6xxx_iqk_cfg *p_cfg)
++{
++	struct sk_buff *skb;
++	struct cfg_host_cmd *host_cmd;
++	int ret = 0;
++	dev_dbg(sh->sc->dev, "# Do init_cali (iq)\n");
++	skb =
++	    ssv_skb_alloc(HOST_CMD_HDR_LEN + IQK_CFG_LEN + PHY_SETTING_SIZE +
++			  RF_SETTING_SIZE);
++	if (skb == NULL) {
++		dev_err(sh->sc->dev, "init ssv6xxx_do_iq_calib failure\n");
++		return (-1);
++	}
++	if ((PHY_SETTING_SIZE > MAX_PHY_SETTING_TABLE_SIZE) ||
++	    (RF_SETTING_SIZE > MAX_RF_SETTING_TABLE_SIZE)) {
++		dev_warn(sh->sc->dev, "wrong RF or PHY table size\n");
++		WARN_ON(1);
++		return (-1);
++	}
++	skb->data_len =
++	    HOST_CMD_HDR_LEN + IQK_CFG_LEN + PHY_SETTING_SIZE + RF_SETTING_SIZE;
++	skb->len = skb->data_len;
++	host_cmd = (struct cfg_host_cmd *)skb->data;
++	host_cmd->c_type = HOST_CMD;
++	host_cmd->h_cmd = (u8) SSV6XXX_HOST_CMD_INIT_CALI;
++	host_cmd->len = skb->data_len;
++	p_cfg->phy_tbl_size = PHY_SETTING_SIZE;
++	p_cfg->rf_tbl_size = RF_SETTING_SIZE;
++	memcpy(host_cmd->dat32, p_cfg, IQK_CFG_LEN);
++	memcpy(host_cmd->dat8 + IQK_CFG_LEN, phy_setting, PHY_SETTING_SIZE);
++	memcpy(host_cmd->dat8 + IQK_CFG_LEN + PHY_SETTING_SIZE, ssv6200_rf_tbl,
++	       RF_SETTING_SIZE);
++	sh->hci.hci_ops->hci_send_cmd(skb);
++	ssv_skb_free(skb);
++	{
++		u32 timeout;
++		sh->sc->iq_cali_done = IQ_CALI_RUNNING;
++		set_current_state(TASK_INTERRUPTIBLE);
++		timeout = wait_event_interruptible_timeout(sh->sc->fw_wait_q,
++							   sh->sc->iq_cali_done,
++							   msecs_to_jiffies
++							   (500));
++		set_current_state(TASK_RUNNING);
++		if (timeout == 0)
++			return -ETIME;
++		if (sh->sc->iq_cali_done != IQ_CALI_OK)
++			return (-1);
++	}
++	return ret;
++}
++
++#define HT_CAP_RX_STBC_ONE_STREAM 0x1
++#if defined(CONFIG_PM)
++static const struct wiphy_wowlan_support wowlan_support = {
++#ifdef SSV_WAKEUP_HOST
++	.flags = WIPHY_WOWLAN_ANY,
++#else
++	.flags = WIPHY_WOWLAN_DISCONNECT,
++#endif
++	.n_patterns = 0,
++	.pattern_max_len = 0,
++	.pattern_min_len = 0,
++	.max_pkt_offset = 0,
++};
++#endif
++static void ssv6xxx_set_80211_hw_capab(struct ssv_softc *sc)
++{
++	struct ieee80211_hw *hw = sc->hw;
++	struct ssv_hw *sh = sc->sh;
++	struct ieee80211_sta_ht_cap *ht_info;
++	ieee80211_hw_set(hw, SIGNAL_DBM);
++	hw->rate_control_algorithm = "ssv6xxx_rate_control";
++	//hw->rate_control_algorithm = NULL; // NULL selects default
++	ht_info = &sc->sbands[INDEX_80211_BAND_2GHZ].ht_cap;
++	ampdu_db_log("sh->cfg.hw_caps = 0x%x\n", sh->cfg.hw_caps);
++	if (sh->cfg.hw_caps & SSV6200_HW_CAP_HT) {
++		if (sh->cfg.hw_caps & SSV6200_HW_CAP_AMPDU_RX) {
++			ieee80211_hw_set(hw, AMPDU_AGGREGATION);
++			ampdu_db_log("set IEEE80211_HW_AMPDU_AGGREGATION(%d)\n",
++				     ieee80211_hw_check(hw, AMPDU_AGGREGATION));
++		}
++		ht_info->cap = IEEE80211_HT_CAP_SM_PS;
++		if (sh->cfg.hw_caps & SSV6200_HW_CAP_GF) {
++			ht_info->cap |= IEEE80211_HT_CAP_GRN_FLD;
++			ht_info->cap |=
++			    HT_CAP_RX_STBC_ONE_STREAM <<
++			    IEEE80211_HT_CAP_RX_STBC_SHIFT;
++		}
++		if (sh->cfg.hw_caps & SSV6200_HT_CAP_SGI_20)
++			ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
++		ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_32K;
++		ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
++		memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
++		ht_info->mcs.rx_mask[0] = 0xff;
++		ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
++		ht_info->mcs.rx_highest = cpu_to_le16(SSV6200_RX_HIGHEST_RATE);
++		ht_info->ht_supported = true;
++	}
++	hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
++	if (sh->cfg.hw_caps & SSV6200_HW_CAP_P2P) {
++		hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_P2P_CLIENT);
++		hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_P2P_GO);
++		hw->wiphy->iface_combinations = ssv6xxx_iface_combinations_p2p;
++		hw->wiphy->n_iface_combinations =
++		    ARRAY_SIZE(ssv6xxx_iface_combinations_p2p);
++	}
++	hw->wiphy->flags |= WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL;
++	if (sh->cfg.hw_caps & SSV6200_HW_CAP_AP) {
++		hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_AP);
++		hw->wiphy->flags |= WIPHY_FLAG_AP_UAPSD;
++	}
++	if (sh->cfg.hw_caps & SSV6200_HW_CAP_TDLS) {
++		hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS;
++		hw->wiphy->flags |= WIPHY_FLAG_TDLS_EXTERNAL_SETUP;
++		dev_info(sc->dev, "TDLS function enabled in sta.cfg\n");
++	}
++	hw->queues = 4;
++	hw->max_rates = 4;
++	hw->max_listen_interval = 1;
++	hw->max_rate_tries = HW_MAX_RATE_TRIES;
++	hw->extra_tx_headroom = TXPB_OFFSET + AMPDU_DELIMITER_LEN;
++	if (sizeof(struct ampdu_hdr_st) > SSV_SKB_info_size)
++		hw->extra_tx_headroom += sizeof(struct ampdu_hdr_st);
++	else
++		hw->extra_tx_headroom += SSV_SKB_info_size;
++	if (sh->cfg.hw_caps & SSV6200_HW_CAP_2GHZ) {
++		hw->wiphy->bands[INDEX_80211_BAND_2GHZ] =
++		    &sc->sbands[INDEX_80211_BAND_2GHZ];
++	}
++	if (sh->cfg.hw_caps & SSV6200_HW_CAP_AMPDU_TX)
++#ifdef PREFER_RX
++		hw->max_rx_aggregation_subframes = 64;
++#else
++		hw->max_rx_aggregation_subframes = 16;
++#endif
++	else
++		hw->max_rx_aggregation_subframes = 12;
++	hw->max_tx_aggregation_subframes = 64;
++	hw->sta_data_size = sizeof(struct ssv_sta_priv_data);
++	hw->vif_data_size = sizeof(struct ssv_vif_priv_data);
++	memcpy(sh->maddr[0].addr, &sh->cfg.maddr[0][0], ETH_ALEN);
++	hw->wiphy->addresses = sh->maddr;
++	hw->wiphy->n_addresses = 1;
++	if (sh->cfg.hw_caps & SSV6200_HW_CAP_P2P) {
++		int i;
++		for (i = 1; i < SSV6200_MAX_HW_MAC_ADDR; i++) {
++			memcpy(sh->maddr[i].addr, sh->maddr[i - 1].addr,
++			       ETH_ALEN);
++			sh->maddr[i].addr[5]++;
++			hw->wiphy->n_addresses++;
++		}
++	}
++	if (!is_zero_ether_addr(sh->cfg.maddr[1])) {
++		memcpy(sh->maddr[1].addr, sh->cfg.maddr[1], ETH_ALEN);
++		if (hw->wiphy->n_addresses < 2)
++			hw->wiphy->n_addresses = 2;
++	}
++#if defined(CONFIG_PM)
++	hw->wiphy->wowlan = &wowlan_support;
++#endif
++
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(3, 14, 0)) && defined(CONFIG_SSV_VENDOR_EXT_SUPPORT)
++    {
++        int err = 0;
++        struct ssv_softc *softc = (struct ssv_softc *)hw->priv;
++        if (softc)
++        {
++            set_wiphy_dev(hw->wiphy, softc->dev);
++            *((struct ssv_softc **)wiphy_priv(hw->wiphy)) = softc;
++        }
++       	dev_dbg(sc->dev, "Registering Vendor80211\n");
++       	err = ssv_cfgvendor_attach(hw->wiphy);
++       	if (unlikely(err < 0)) {
++       		dev_err(sc->dev, "Couldn not attach vendor commands (%d)\n", err);
++       	}
++    }
++#endif /* (LINUX_VERSION_CODE > KERNEL_VERSION(3, 14, 0)) || defined(WL_VENDOR_EXT_SUPPORT) */
++}
++
++void ssv6xxx_watchdog_restart_hw(struct ssv_softc *sc)
++{
++	dev_dbg(sc->dev, "%s()\n", __FUNCTION__);
++	sc->restart_counter++;
++	sc->force_triger_reset = true;
++	sc->beacon_info[0].pubf_addr = 0x00;
++	sc->beacon_info[1].pubf_addr = 0x00;
++	ieee80211_restart_hw(sc->hw);
++}
++
++extern struct rssi_res_st rssi_res;
++void ssv6200_watchdog_timeout(struct timer_list *t)
++{
++	static u32 count = 0;
++	struct rssi_res_st *rssi_tmp0 = NULL, *rssi_tmp1 = NULL;
++	struct ssv_softc *sc = from_timer(sc, t, watchdog_timeout);
++	if (sc->watchdog_flag == WD_BARKING) {
++		ssv6xxx_watchdog_restart_hw(sc);
++		mod_timer(&sc->watchdog_timeout, jiffies + WATCHDOG_TIMEOUT);
++		return;
++	}
++	if (sc->watchdog_flag != WD_SLEEP)
++		sc->watchdog_flag = WD_BARKING;
++	count++;
++	if (count == 6) {
++		count = 0;
++		if (list_empty(&rssi_res.rssi_list)) {
++			return;
++		}
++		list_for_each_entry_safe(rssi_tmp0, rssi_tmp1,
++					 &rssi_res.rssi_list, rssi_list) {
++			if (rssi_tmp0->timeout) {
++				list_del_rcu(&rssi_tmp0->rssi_list);
++				kfree(rssi_tmp0);
++			}
++		}
++	}
++	mod_timer(&sc->watchdog_timeout, jiffies + WATCHDOG_TIMEOUT);
++	return;
++}
++
++static void ssv6xxx_preload_sw_cipher(void)
++{
++}
++
++static int ssv6xxx_init_softc(struct ssv_softc *sc)
++{
++	void *channels;
++	int ret = 0;
++	sc->sc_flags = SC_OP_INVALID;
++	mutex_init(&sc->mutex);
++	mutex_init(&sc->mem_mutex);
++	sc->config_wq = create_singlethread_workqueue("ssv6xxx_cong_wq");
++	sc->thermal_wq = create_singlethread_workqueue("ssv6xxx_thermal_wq");
++	INIT_DELAYED_WORK(&sc->thermal_monitor_work, thermal_monitor);
++	INIT_WORK(&sc->set_tim_work, ssv6200_set_tim_work);
++	INIT_WORK(&sc->bcast_start_work, ssv6200_bcast_start_work);
++	INIT_DELAYED_WORK(&sc->bcast_stop_work, ssv6200_bcast_stop_work);
++	INIT_DELAYED_WORK(&sc->bcast_tx_work, ssv6200_bcast_tx_work);
++	INIT_WORK(&sc->set_ampdu_rx_add_work, ssv6xxx_set_ampdu_rx_add_work);
++	INIT_WORK(&sc->set_ampdu_rx_del_work, ssv6xxx_set_ampdu_rx_del_work);
++	sc->mac_deci_tbl = sta_deci_tbl;
++	memset((void *)&sc->tx, 0, sizeof(struct ssv_tx));
++	sc->tx.hw_txqid[WMM_AC_VO] = 3;
++	sc->tx.ac_txqid[3] = WMM_AC_VO;
++	sc->tx.hw_txqid[WMM_AC_VI] = 2;
++	sc->tx.ac_txqid[2] = WMM_AC_VI;
++	sc->tx.hw_txqid[WMM_AC_BE] = 1;
++	sc->tx.ac_txqid[1] = WMM_AC_BE;
++	sc->tx.hw_txqid[WMM_AC_BK] = 0;
++	sc->tx.ac_txqid[0] = WMM_AC_BK;
++	INIT_LIST_HEAD(&sc->tx.ampdu_tx_que);
++	spin_lock_init(&sc->tx.ampdu_tx_que_lock);
++	memset((void *)&sc->rx, 0, sizeof(struct ssv_rx));
++	spin_lock_init(&sc->rx.rxq_lock);
++	skb_queue_head_init(&sc->rx.rxq_head);
++	sc->rx.rx_buf = ssv_skb_alloc(MAX_FRAME_SIZE);
++	if (sc->rx.rx_buf == NULL)
++		return -ENOMEM;
++	memset(&sc->bcast_txq, 0, sizeof(struct ssv6xxx_bcast_txq));
++	spin_lock_init(&sc->bcast_txq.txq_lock);
++	skb_queue_head_init(&sc->bcast_txq.qhead);
++	spin_lock_init(&sc->ps_state_lock);
++#ifdef CONFIG_P2P_NOA
++	spin_lock_init(&sc->p2p_noa.p2p_config_lock);
++#endif
++	if (sc->sh->cfg.hw_caps & SSV6200_HW_CAP_2GHZ) {
++		channels = kmemdup(ssv6200_2ghz_chantable,
++				   sizeof(ssv6200_2ghz_chantable), GFP_KERNEL);
++		if (!channels) {
++			kfree(sc->rx.rx_buf);
++			return -ENOMEM;
++		}
++		sc->sbands[INDEX_80211_BAND_2GHZ].channels = channels;
++		sc->sbands[INDEX_80211_BAND_2GHZ].band = INDEX_80211_BAND_2GHZ;
++		sc->sbands[INDEX_80211_BAND_2GHZ].n_channels =
++		    ARRAY_SIZE(ssv6200_2ghz_chantable);
++		sc->sbands[INDEX_80211_BAND_2GHZ].bitrates =
++		    ssv6200_legacy_rates;
++		sc->sbands[INDEX_80211_BAND_2GHZ].n_bitrates =
++		    ARRAY_SIZE(ssv6200_legacy_rates);
++	}
++	sc->cur_channel = NULL;
++	sc->hw_chan = (-1);
++	ssv6xxx_set_80211_hw_capab(sc);
++	ret = ssv6xxx_rate_control_register();
++	if (ret != 0) {
++		dev_warn(sc->dev, "%s(): Failed to register rc algorithm.\n",__FUNCTION__);
++	}
++	init_waitqueue_head(&sc->tx_wait_q);
++	sc->tx_wait_q_woken = 0;
++	skb_queue_head_init(&sc->tx_skb_q);
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	sc->max_tx_skb_q_len = 0;
++#endif
++	sc->tx_task = kthread_run(ssv6xxx_tx_task, sc, "ssv6xxx_tx_task");
++	sc->tx_q_empty = false;
++	skb_queue_head_init(&sc->tx_done_q);
++	init_waitqueue_head(&sc->rx_wait_q);
++	sc->rx_wait_q_woken = 0;
++	skb_queue_head_init(&sc->rx_skb_q);
++	sc->rx_task = kthread_run(ssv6xxx_rx_task, sc, "ssv6xxx_rx_task");
++	ssv6xxx_preload_sw_cipher();
++	timer_setup(&sc->watchdog_timeout, ssv6200_watchdog_timeout, 0);
++	init_waitqueue_head(&sc->fw_wait_q);
++	INIT_LIST_HEAD(&rssi_res.rssi_list);
++	rssi_res.rssi = 0;
++	mod_timer(&sc->watchdog_timeout, jiffies + WATCHDOG_TIMEOUT);
++	//add_timer(&sc->watchdog_timeout);
++	//if(get_flash_info(sc) == 1)
++	sc->is_sar_enabled = get_flash_info(sc);
++	if (sc->is_sar_enabled)
++		queue_delayed_work(sc->thermal_wq, &sc->thermal_monitor_work,
++				   THERMAL_MONITOR_TIME);
++	//schedule_delayed_work(&sc->thermal_monitor_work, THERMAL_MONITOR_TIME);
++	return ret;
++}
++
++static int ssv6xxx_deinit_softc(struct ssv_softc *sc)
++{
++	void *channels;
++	struct sk_buff *skb;
++	u8 remain_size;
++	dev_dbg(sc->dev, "%s():\n", __FUNCTION__);
++	if (sc->sh->cfg.hw_caps & SSV6200_HW_CAP_2GHZ) {
++		channels = sc->sbands[INDEX_80211_BAND_2GHZ].channels;
++		kfree(channels);
++	}
++	ssv_skb_free(sc->rx.rx_buf);
++	sc->rx.rx_buf = NULL;
++	ssv6xxx_rate_control_unregister();
++	cancel_delayed_work_sync(&sc->bcast_tx_work);
++	//ssv6xxx_watchdog_controller(sc->sh ,(u8)SSV6XXX_HOST_CMD_WATCHDOG_STOP);
++	del_timer_sync(&sc->watchdog_timeout);
++	cancel_delayed_work(&sc->thermal_monitor_work);
++	sc->ps_status = PWRSV_PREPARE;
++	flush_workqueue(sc->thermal_wq);
++	destroy_workqueue(sc->thermal_wq);
++	do {
++		skb = ssv6200_bcast_dequeue(&sc->bcast_txq, &remain_size);
++		if (skb)
++			ssv6xxx_txbuf_free_skb(skb, (void *)sc);
++		else
++			break;
++	} while (remain_size);
++	if (sc->tx_task != NULL) {
++		dev_dbg(sc->dev, "Stopping TX task...\n");
++		kthread_stop(sc->tx_task);
++		sc->tx_task = NULL;
++		dev_dbg(sc->dev, "Stopped TX task.\n");
++	}
++	if (sc->rx_task != NULL) {
++		dev_dbg(sc->dev, "Stopping RX task...\n");
++		kthread_stop(sc->rx_task);
++		sc->rx_task = NULL;
++		dev_dbg(sc->dev, "Stopped RX task.\n");
++	}
++	destroy_workqueue(sc->config_wq);
++	return 0;
++}
++
++static void ssv6xxx_hw_set_replay_ignore(struct ssv_hw *sh, u8 ignore)
++{
++	u32 temp;
++	SMAC_REG_READ(sh, ADR_SCRT_SET, &temp);
++	temp = temp & SCRT_RPLY_IGNORE_I_MSK;
++	temp |= (ignore << SCRT_RPLY_IGNORE_SFT);
++	SMAC_REG_WRITE(sh, ADR_SCRT_SET, temp);
++}
++
++int ssv6xxx_init_mac(struct ssv_hw *sh)
++{
++	struct ssv_softc *sc = sh->sc;
++	int i = 0, ret = 0;
++
++	u32 *ptr, id_len, regval, temp[0x8];
++	char *chip_id = sh->chip_id;
++	SMAC_REG_READ(sh, ADR_IC_TIME_TAG_1, &regval);
++	sh->chip_tag = ((u64) regval << 32);
++	SMAC_REG_READ(sh, ADR_IC_TIME_TAG_0, &regval);
++	sh->chip_tag |= (regval);
++	SMAC_REG_READ(sh, ADR_CHIP_ID_3, &regval);
++	*((u32 *) & chip_id[0]) = (u32) LONGSWAP(regval);
++	SMAC_REG_READ(sh, ADR_CHIP_ID_2, &regval);
++	*((u32 *) & chip_id[4]) = (u32) LONGSWAP(regval);
++	SMAC_REG_READ(sh, ADR_CHIP_ID_1, &regval);
++	*((u32 *) & chip_id[8]) = (u32) LONGSWAP(regval);
++	SMAC_REG_READ(sh, ADR_CHIP_ID_0, &regval);
++	*((u32 *) & chip_id[12]) = (u32) LONGSWAP(regval);
++	chip_id[12 + sizeof(u32)] = 0;
++	dev_info(sh->sc->dev, "chip id: %s, tag: %llx\n", chip_id, sh->chip_tag);
++	if (sc->ps_status == PWRSV_ENABLE) {
++		SMAC_REG_WRITE(sh, ADR_RX_FLOW_DATA,
++			       M_ENG_MACRX | (M_ENG_ENCRYPT_SEC << 4) |
++			       (M_ENG_HWHCI << 8));
++		SMAC_REG_WRITE(sc->sh, ADR_RX_FLOW_MNG,
++			       M_ENG_MACRX | (M_ENG_HWHCI << 4));
++#if Enable_AMPDU_FW_Retry
++		SMAC_REG_WRITE(sh, ADR_RX_FLOW_CTRL,
++			       M_ENG_MACRX | (M_ENG_CPU << 4) | (M_ENG_HWHCI <<
++								 8));
++#else
++		SMAC_REG_WRITE(sh, ADR_RX_FLOW_CTRL,
++			       M_ENG_MACRX | (M_ENG_HWHCI << 4));
++#endif
++		SMAC_REG_WRITE(sc->sh, ADR_MRX_FLT_TB0 + 6 * 4,
++			       (sc->mac_deci_tbl[6]));
++		return ret;
++	}
++	SMAC_REG_SET_BITS(sh, ADR_PHY_EN_1, (0 << RG_PHY_MD_EN_SFT),
++			  RG_PHY_MD_EN_MSK);
++	SMAC_REG_WRITE(sh, ADR_BRG_SW_RST, 1 << MAC_SW_RST_SFT);
++	do {
++		SMAC_REG_READ(sh, ADR_BRG_SW_RST, &regval);
++		i++;
++		if (i > 10000) {
++			dev_err(sh->sc->dev, "MAC reset fail !!!!\n");
++			WARN_ON(1);
++			ret = 1;
++			goto exit;
++		}
++	} while (regval != 0);
++	SMAC_REG_WRITE(sc->sh, ADR_TXQ4_MTX_Q_AIFSN, 0xffff2101);
++	SMAC_REG_SET_BITS(sc->sh, ADR_MTX_BCN_EN_MISC, 0,
++			  MTX_HALT_MNG_UNTIL_DTIM_MSK);
++	SMAC_REG_WRITE(sh, ADR_CONTROL, 0x12000006);
++	SMAC_REG_WRITE(sh, ADR_RX_TIME_STAMP_CFG,
++		       ((28 << MRX_STP_OFST_SFT) | 0x01));
++	SMAC_REG_WRITE(sh, ADR_HCI_TX_RX_INFO_SIZE,
++		       ((u32) (TXPB_OFFSET) << TX_PBOFFSET_SFT) |
++		       ((u32) (sh->tx_desc_len) << TX_INFO_SIZE_SFT) |
++		       ((u32) (sh->rx_desc_len) << RX_INFO_SIZE_SFT) |
++		       ((u32) (sh->rx_pinfo_pad) << RX_LAST_PHY_SIZE_SFT)
++	    );
++	SMAC_REG_READ(sh, ADR_MMU_CTRL, &regval);
++	regval |= (0xff << MMU_SHARE_MCU_SFT);
++	SMAC_REG_WRITE(sh, ADR_MMU_CTRL, regval);
++	SMAC_REG_READ(sh, ADR_MRX_WATCH_DOG, &regval);
++	regval &= 0xfffffff0;
++	SMAC_REG_WRITE(sh, ADR_MRX_WATCH_DOG, regval);
++	SMAC_REG_READ(sh, ADR_TRX_ID_THRESHOLD, &id_len);
++	id_len = (id_len & 0xffff0000) |
++	    (SSV6200_ID_TX_THRESHOLD << TX_ID_THOLD_SFT) |
++	    (SSV6200_ID_RX_THRESHOLD << RX_ID_THOLD_SFT);
++	SMAC_REG_WRITE(sh, ADR_TRX_ID_THRESHOLD, id_len);
++	SMAC_REG_READ(sh, ADR_ID_LEN_THREADSHOLD1, &id_len);
++	id_len = (id_len & 0x0f) |
++	    (SSV6200_PAGE_TX_THRESHOLD << ID_TX_LEN_THOLD_SFT) |
++	    (SSV6200_PAGE_RX_THRESHOLD << ID_RX_LEN_THOLD_SFT);
++	SMAC_REG_WRITE(sh, ADR_ID_LEN_THREADSHOLD1, id_len);
++#ifdef CONFIG_SSV_CABRIO_MB_DEBUG
++	SMAC_REG_READ(sh, ADR_MB_DBG_CFG3, &regval);
++	regval |= (debug_buffer << 0);
++	SMAC_REG_WRITE(sh, ADR_MB_DBG_CFG3, regval);
++	SMAC_REG_READ(sh, ADR_MB_DBG_CFG2, &regval);
++	regval |= (DEBUG_SIZE << 16);
++	SMAC_REG_WRITE(sh, ADR_MB_DBG_CFG2, regval);
++	SMAC_REG_READ(sh, ADR_MB_DBG_CFG1, &regval);
++	regval |= (1 << MB_DBG_EN_SFT);
++	SMAC_REG_WRITE(sh, ADR_MB_DBG_CFG1, regval);
++	SMAC_REG_READ(sh, ADR_MBOX_HALT_CFG, &regval);
++	regval |= (1 << MB_ERR_AUTO_HALT_EN_SFT);
++	SMAC_REG_WRITE(sh, ADR_MBOX_HALT_CFG, regval);
++#endif
++	SMAC_REG_READ(sc->sh, ADR_MTX_BCN_EN_MISC, &regval);
++	regval |= (1 << MTX_TSF_TIMER_EN_SFT);
++	SMAC_REG_WRITE(sc->sh, ADR_MTX_BCN_EN_MISC, regval);
++	SMAC_REG_WRITE(sh, 0xcd010004, 0x1213);
++	for (i = 0; i < SSV_RC_MAX_STA; i++) {
++		if (i == 0) {
++			sh->hw_buf_ptr[i] =
++			    ssv6xxx_pbuf_alloc(sc,
++					       sizeof(phy_info_tbl) +
++					       sizeof(struct ssv6xxx_hw_sec),
++					       NOTYPE_BUF);
++			if ((sh->hw_buf_ptr[i] >> 28) != 8) {
++				dev_err(sh->sc->dev, "opps allocate pbuf error\n");
++				WARN_ON(1);
++				ret = 1;
++				goto exit;
++			}
++		} else {
++			sh->hw_buf_ptr[i] =
++			    ssv6xxx_pbuf_alloc(sc,
++					       sizeof(struct ssv6xxx_hw_sec),
++					       NOTYPE_BUF);
++			if ((sh->hw_buf_ptr[i] >> 28) != 8) {
++				dev_err(sh->sc->dev, "opps allocate pbuf error\n");
++				WARN_ON(1);
++				ret = 1;
++				goto exit;
++			}
++		}
++	}
++	for (i = 0; i < 0x8; i++) {
++		temp[i] = 0;
++		temp[i] = ssv6xxx_pbuf_alloc(sc, 256, NOTYPE_BUF);
++	}
++	for (i = 0; i < 0x8; i++) {
++		if (temp[i] == 0x800e0000)
++			dev_dbg(sh->sc->dev, "Found 0x800e0000 at position %d\n", i);
++		else
++			ssv6xxx_pbuf_free(sc, temp[i]);
++	}
++	for (i = 0; i < SSV_RC_MAX_STA; i++)
++		sh->hw_sec_key[i] = sh->hw_buf_ptr[i];
++	for (i = 0; i < SSV_RC_MAX_STA; i++) {
++		int x;
++		for (x = 0; x < sizeof(struct ssv6xxx_hw_sec); x += 4) {
++			SMAC_REG_WRITE(sh, sh->hw_sec_key[i] + x, 0);
++		}
++	}
++	SMAC_REG_READ(sh, ADR_SCRT_SET, &regval);
++	regval &= SCRT_PKT_ID_I_MSK;
++	regval |= ((sh->hw_sec_key[0] >> 16) << SCRT_PKT_ID_SFT);
++	SMAC_REG_WRITE(sh, ADR_SCRT_SET, regval);
++	sh->hw_pinfo = sh->hw_sec_key[0] + sizeof(struct ssv6xxx_hw_sec);
++	for (i = 0, ptr = phy_info_tbl; i < PHY_INFO_TBL1_SIZE; i++, ptr++) {
++		SMAC_REG_WRITE(sh, ADR_INFO0 + i * 4, *ptr);
++		SMAC_REG_CONFIRM(sh, ADR_INFO0 + i * 4, *ptr);
++	}
++	for (i = 0; i < PHY_INFO_TBL2_SIZE; i++, ptr++) {
++		SMAC_REG_WRITE(sh, sh->hw_pinfo + i * 4, *ptr);
++		SMAC_REG_CONFIRM(sh, sh->hw_pinfo + i * 4, *ptr);
++	}
++	for (i = 0; i < PHY_INFO_TBL3_SIZE; i++, ptr++) {
++		SMAC_REG_WRITE(sh, sh->hw_pinfo +
++			       (PHY_INFO_TBL2_SIZE << 2) + i * 4, *ptr);
++		SMAC_REG_CONFIRM(sh, sh->hw_pinfo +
++				 (PHY_INFO_TBL2_SIZE << 2) + i * 4, *ptr);
++	}
++	SMAC_REG_WRITE(sh, ADR_INFO_RATE_OFFSET, 0x00040000);
++	SMAC_REG_WRITE(sh, ADR_INFO_IDX_ADDR, sh->hw_pinfo);
++	SMAC_REG_WRITE(sh, ADR_INFO_LEN_ADDR,
++		       sh->hw_pinfo + (PHY_INFO_TBL2_SIZE) * 4);
++	dev_dbg(sh->sc->dev, "ADR_INFO_IDX_ADDR[%08x] ADR_INFO_LEN_ADDR[%08x]\n",
++	       sh->hw_pinfo, sh->hw_pinfo + (PHY_INFO_TBL2_SIZE) * 4);
++	SMAC_REG_WRITE(sh, ADR_GLBLE_SET,
++		       (0 << OP_MODE_SFT) | (0 << SNIFFER_MODE_SFT) | (1 <<
++								       DUP_FLT_SFT)
++		       | (SSV6200_TX_PKT_RSVD_SETTING << TX_PKT_RSVD_SFT) |
++		       ((u32) (RXPB_OFFSET) << PB_OFFSET_SFT)
++	    );
++	SMAC_REG_WRITE(sh, ADR_STA_MAC_0, *((u32 *) & sh->cfg.maddr[0][0]));
++	SMAC_REG_WRITE(sh, ADR_STA_MAC_1, *((u32 *) & sh->cfg.maddr[0][4]));
++	SMAC_REG_WRITE(sh, ADR_BSSID_0, *((u32 *) & sc->bssid[0]));
++	SMAC_REG_WRITE(sh, ADR_BSSID_1, *((u32 *) & sc->bssid[4]));
++	SMAC_REG_WRITE(sh, ADR_TX_ETHER_TYPE_0, 0x00000000);
++	SMAC_REG_WRITE(sh, ADR_TX_ETHER_TYPE_1, 0x00000000);
++	SMAC_REG_WRITE(sh, ADR_RX_ETHER_TYPE_0, 0x00000000);
++	SMAC_REG_WRITE(sh, ADR_RX_ETHER_TYPE_1, 0x00000000);
++	SMAC_REG_WRITE(sh, ADR_REASON_TRAP0, 0x7FBC7F87);
++	SMAC_REG_WRITE(sh, ADR_REASON_TRAP1, 0x0000003F);
++	SMAC_REG_WRITE(sh, ADR_TRAP_HW_ID, M_ENG_CPU);
++	SMAC_REG_WRITE(sh, ADR_WSID0, 0x00000000);
++	SMAC_REG_WRITE(sh, ADR_WSID1, 0x00000000);
++	SMAC_REG_WRITE(sh, ADR_RX_FLOW_DATA,
++		       M_ENG_MACRX | (M_ENG_ENCRYPT_SEC << 4) | (M_ENG_HWHCI <<
++								 8));
++#if defined(CONFIG_P2P_NOA) || defined(CONFIG_RX_MGMT_CHECK)
++	SMAC_REG_WRITE(sh, ADR_RX_FLOW_MNG,
++		       M_ENG_MACRX | (M_ENG_CPU << 4) | (M_ENG_HWHCI << 8));
++#else
++	SMAC_REG_WRITE(sh, ADR_RX_FLOW_MNG, M_ENG_MACRX | (M_ENG_HWHCI << 4));
++#endif
++#if Enable_AMPDU_FW_Retry
++	SMAC_REG_WRITE(sh, ADR_RX_FLOW_CTRL,
++		       M_ENG_MACRX | (M_ENG_CPU << 4) | (M_ENG_HWHCI << 8));
++#else
++	SMAC_REG_WRITE(sh, ADR_RX_FLOW_CTRL, M_ENG_MACRX | (M_ENG_HWHCI << 4));
++#endif
++	ssv6xxx_hw_set_replay_ignore(sh, 1);
++	ssv6xxx_update_decision_table(sc);
++	SMAC_REG_SET_BITS(sc->sh, ADR_GLBLE_SET, SSV6200_OPMODE_STA,
++			  OP_MODE_MSK);
++	SMAC_REG_WRITE(sh, ADR_SDIO_MASK, 0xfffe1fff);
++	SMAC_REG_WRITE(sh, ADR_TX_LIMIT_INTR, 0x80000000 |
++		       SSV6200_TX_LOWTHRESHOLD_ID_TRIGGER << 16 |
++		       SSV6200_TX_LOWTHRESHOLD_PAGE_TRIGGER);
++#ifdef CONFIG_SSV_SUPPORT_BTCX
++	SMAC_REG_WRITE(sh, ADR_BTCX0,
++		       COEXIST_EN_MSK | (WIRE_MODE_SZ << WIRE_MODE_SFT)
++		       | WIFI_TX_SW_POL_MSK | BT_SW_POL_MSK);
++	SMAC_REG_WRITE(sh, ADR_BTCX1,
++		       SSV6200_BT_PRI_SMP_TIME | (SSV6200_BT_STA_SMP_TIME <<
++						  BT_STA_SMP_TIME_SFT)
++		       | (SSV6200_WLAN_REMAIN_TIME << WLAN_REMAIN_TIME_SFT));
++	SMAC_REG_WRITE(sh, ADR_SWITCH_CTL, BT_2WIRE_EN_MSK);
++	SMAC_REG_WRITE(sh, ADR_PAD7, 1);
++	SMAC_REG_WRITE(sh, ADR_PAD8, 0);
++	SMAC_REG_WRITE(sh, ADR_PAD9, 1);
++	SMAC_REG_WRITE(sh, ADR_PAD25, 1);
++	SMAC_REG_WRITE(sh, ADR_PAD27, 8);
++	SMAC_REG_WRITE(sh, ADR_PAD28, 8);
++#endif
++	dev_info(sh->sc->dev, "attempt to load firmware %s\n", WIFI_FIRMWARE_NAME);
++	ret = SMAC_LOAD_FW(sh, WIFI_FIRMWARE_NAME, 0);
++
++	SMAC_REG_READ(sh, FW_VERSION_REG, &regval);
++	if (regval == ssv_firmware_version) {
++		SMAC_REG_SET_BITS(sh, ADR_PHY_EN_1, (1 << RG_PHY_MD_EN_SFT),
++				  RG_PHY_MD_EN_MSK);
++		dev_info(sh->sc->dev, "Firmware version %d\n", regval);
++	} else {
++		dev_err(sh->sc->dev, "Firmware version not mapping %d\n", regval);
++		ret = -1;
++	}
++	ssv6xxx_watchdog_controller(sh, (u8) SSV6XXX_HOST_CMD_WATCHDOG_START);
++ exit:
++	return ret;
++}
++
++void ssv6xxx_deinit_mac(struct ssv_softc *sc)
++{
++	int i;
++	for (i = 0; i < SSV_RC_MAX_STA; i++) {
++		if (sc->sh->hw_buf_ptr[i])
++			ssv6xxx_pbuf_free(sc, sc->sh->hw_buf_ptr[i]);
++	}
++}
++
++void inline ssv6xxx_deinit_hw(struct ssv_softc *sc)
++{
++	dev_dbg(sc->dev, "%s(): \n", __FUNCTION__);
++	ssv6xxx_deinit_mac(sc);
++}
++
++void ssv6xxx_restart_hw(struct ssv_softc *sc)
++{
++	dev_info(sc->dev, "Software MAC reset\n");
++	sc->restart_counter++;
++	sc->force_triger_reset = true;
++	HCI_STOP(sc->sh);
++	SMAC_REG_WRITE(sc->sh, 0xce000004, 0x0);
++	sc->beacon_info[0].pubf_addr = 0x00;
++	sc->beacon_info[1].pubf_addr = 0x00;
++	ieee80211_restart_hw(sc->hw);
++}
++
++extern struct ssv6xxx_iqk_cfg init_iqk_cfg;
++static int ssv6xxx_init_hw(struct ssv_hw *sh)
++{
++	int ret = 0, i = 0, x = 0;
++	u32 regval;
++	sh->tx_desc_len = SSV6XXX_TX_DESC_LEN;
++	sh->rx_desc_len = SSV6XXX_RX_DESC_LEN;
++	sh->rx_pinfo_pad = 0x04;
++	sh->tx_page_available = SSV6200_PAGE_TX_THRESHOLD;
++	sh->ampdu_divider = SSV6XXX_AMPDU_DIVIDER;
++	memset(sh->page_count, 0, sizeof(sh->page_count));
++	if (sh->cfg.force_chip_identity) {
++		dev_info(sh->sc->dev, "Force use external RF setting [%08x]\n",
++		       sh->cfg.force_chip_identity);
++		sh->cfg.chip_identity = sh->cfg.force_chip_identity;
++	}
++	if (sh->cfg.chip_identity == SSV6051Z) {
++		sh->p_ch_cfg = &ch_cfg_z[0];
++		sh->ch_cfg_size =
++		    sizeof(ch_cfg_z) / sizeof(struct ssv6xxx_ch_cfg);
++		memcpy(phy_info_tbl, phy_info_6051z, sizeof(phy_info_6051z));
++	} else if (sh->cfg.chip_identity == SSV6051P) {
++		sh->p_ch_cfg = &ch_cfg_p[0];
++		sh->ch_cfg_size =
++		    sizeof(ch_cfg_p) / sizeof(struct ssv6xxx_ch_cfg);
++	}
++	switch (sh->cfg.chip_identity) {
++	case SSV6051Q_P1:
++	case SSV6051Q_P2:
++	case SSV6051Q:
++		dev_info(sh->sc->dev, "Using SSV6051Q setting\n");
++		for (i = 0;
++		     i <
++		     sizeof(ssv6200_rf_tbl) / sizeof(struct ssv6xxx_dev_table);
++		     i++) {
++			if (ssv6200_rf_tbl[i].address == 0xCE010008)
++				ssv6200_rf_tbl[i].data = 0x008DF61B;
++			if (ssv6200_rf_tbl[i].address == 0xCE010014)
++				ssv6200_rf_tbl[i].data = 0x3D3E84FE;
++			if (ssv6200_rf_tbl[i].address == 0xCE010018)
++				ssv6200_rf_tbl[i].data = 0x01457D79;
++			if (ssv6200_rf_tbl[i].address == 0xCE01001C)
++				ssv6200_rf_tbl[i].data = 0x000103A7;
++			if (ssv6200_rf_tbl[i].address == 0xCE010020)
++				ssv6200_rf_tbl[i].data = 0x000103A6;
++			if (ssv6200_rf_tbl[i].address == 0xCE01002C)
++				ssv6200_rf_tbl[i].data = 0x00032CA8;
++			if (ssv6200_rf_tbl[i].address == 0xCE010048)
++				ssv6200_rf_tbl[i].data = 0xFCCCCF27;
++			if (ssv6200_rf_tbl[i].address == 0xCE010050)
++				ssv6200_rf_tbl[i].data = 0x0047C000;
++		}
++		break;
++	case SSV6051Z:
++		dev_info(sh->sc->dev, "Using SSV6051Z setting\n");
++		for (i = 0;
++		     i <
++		     sizeof(ssv6200_rf_tbl) / sizeof(struct ssv6xxx_dev_table);
++		     i++) {
++			if (ssv6200_rf_tbl[i].address == 0xCE010008)
++				ssv6200_rf_tbl[i].data = 0x004D561C;
++			if (ssv6200_rf_tbl[i].address == 0xCE010014)
++				ssv6200_rf_tbl[i].data = 0x3D9E84FE;
++			if (ssv6200_rf_tbl[i].address == 0xCE010018)
++				ssv6200_rf_tbl[i].data = 0x00457D79;
++			if (ssv6200_rf_tbl[i].address == 0xCE01001C)
++				ssv6200_rf_tbl[i].data = 0x000103EB;
++			if (ssv6200_rf_tbl[i].address == 0xCE010020)
++				ssv6200_rf_tbl[i].data = 0x000103EA;
++			if (ssv6200_rf_tbl[i].address == 0xCE01002C)
++				ssv6200_rf_tbl[i].data = 0x00062CA8;
++			if (ssv6200_rf_tbl[i].address == 0xCE010048)
++				ssv6200_rf_tbl[i].data = 0xFCCCCF27;
++			if (ssv6200_rf_tbl[i].address == 0xCE010050)
++				ssv6200_rf_tbl[i].data = 0x0047C000;
++		}
++		break;
++	case SSV6051P:
++		dev_info(sh->sc->dev, "Using SSV6051P setting\n");
++		for (i = 0;
++		     i <
++		     sizeof(ssv6200_rf_tbl) / sizeof(struct ssv6xxx_dev_table);
++		     i++) {
++			if (ssv6200_rf_tbl[i].address == 0xCE010008)
++				ssv6200_rf_tbl[i].data = 0x008B7C1C;
++			if (ssv6200_rf_tbl[i].address == 0xCE010014)
++				ssv6200_rf_tbl[i].data = 0x3D7E84FE;
++			if (ssv6200_rf_tbl[i].address == 0xCE010018)
++				ssv6200_rf_tbl[i].data = 0x01457D79;
++			if (ssv6200_rf_tbl[i].address == 0xCE01001C)
++				ssv6200_rf_tbl[i].data = 0x000103EB;
++			if (ssv6200_rf_tbl[i].address == 0xCE010020)
++				ssv6200_rf_tbl[i].data = 0x000103EA;
++			if (ssv6200_rf_tbl[i].address == 0xCE01002C)
++				ssv6200_rf_tbl[i].data = 0x00032CA8;
++			if (ssv6200_rf_tbl[i].address == 0xCE010048)
++				ssv6200_rf_tbl[i].data = 0xFCCCCC27;
++			if (ssv6200_rf_tbl[i].address == 0xCE010050)
++				ssv6200_rf_tbl[i].data = 0x0047C000;
++			if (ssv6200_rf_tbl[i].address == 0xC0001D00)
++				ssv6200_rf_tbl[i].data = 0x5E000040;
++		}
++		break;
++	default:
++		dev_err(sh->sc->dev, "No RF setting\n");
++		break;
++	}
++	if (sh->cfg.crystal_type == SSV6XXX_IQK_CFG_XTAL_26M) {
++		init_iqk_cfg.cfg_xtal = SSV6XXX_IQK_CFG_XTAL_26M;
++		dev_info(sh->sc->dev, "Crystal frequency: 26 Mhz\n");
++	} else if (sh->cfg.crystal_type == SSV6XXX_IQK_CFG_XTAL_40M) {
++		init_iqk_cfg.cfg_xtal = SSV6XXX_IQK_CFG_XTAL_40M;
++		dev_info(sh->sc->dev, "Crystal frequency: 40 Mhz\n");
++	} else if (sh->cfg.crystal_type == SSV6XXX_IQK_CFG_XTAL_24M) {
++		init_iqk_cfg.cfg_xtal = SSV6XXX_IQK_CFG_XTAL_24M;
++		dev_info(sh->sc->dev, "Crystal frequency: 24 Mhz\n");
++		for (i = 0;
++		     i <
++		     sizeof(ssv6200_rf_tbl) / sizeof(struct ssv6xxx_dev_table);
++		     i++) {
++			if (ssv6200_rf_tbl[i].address == ADR_SX_ENABLE_REGISTER)
++				ssv6200_rf_tbl[i].data = 0x0003E07C;
++			if (ssv6200_rf_tbl[i].address ==
++			    ADR_DPLL_DIVIDER_REGISTER)
++				ssv6200_rf_tbl[i].data = 0x00406000;
++			if (ssv6200_rf_tbl[i].address ==
++			    ADR_DPLL_FB_DIVIDER_REGISTERS_I)
++				ssv6200_rf_tbl[i].data = 0x00000028;
++			if (ssv6200_rf_tbl[i].address ==
++			    ADR_DPLL_FB_DIVIDER_REGISTERS_II)
++				ssv6200_rf_tbl[i].data = 0x00000000;
++		}
++	} else {
++		dev_warn(sh->sc->dev, "Illegal crystal setting, using default value of 26 Mhz\n");
++	}
++	for (i = 0;
++	     i < sizeof(ssv6200_rf_tbl) / sizeof(struct ssv6xxx_dev_table);
++	     i++) {
++		if (ssv6200_rf_tbl[i].address ==
++		    ADR_SYN_KVCO_XO_FINE_TUNE_CBANK) {
++			if (sh->cfg.crystal_frequency_offset) {
++				ssv6200_rf_tbl[i].data &=
++				    RG_XOSC_CBANK_XO_I_MSK;
++				ssv6200_rf_tbl[i].data |=
++				    (sh->cfg.
++				     crystal_frequency_offset <<
++				     RG_XOSC_CBANK_XO_SFT);
++			}
++		}
++	}
++	for (i = 0; i < sizeof(phy_setting) / sizeof(struct ssv6xxx_dev_table);
++	     i++) {
++		if (phy_setting[i].address == ADR_TX_GAIN_FACTOR) {
++			switch (sh->cfg.chip_identity) {
++			case SSV6051Q_P1:
++			case SSV6051Q_P2:
++			case SSV6051Q:
++				dev_dbg(sh->sc->dev, "SSV6051Q setting [0x5B606C72]\n");
++				phy_setting[i].data = 0x5B606C72;
++				break;
++			case SSV6051Z:
++				dev_dbg(sh->sc->dev, "SSV6051Z setting [0x60606060]\n");
++				phy_setting[i].data = 0x60606060;
++				break;
++			case SSV6051P:
++				dev_dbg(sh->sc->dev, "SSV6051P setting [0x6C726C72]\n");
++				phy_setting[i].data = 0x6C726C72;
++				break;
++			default:
++				dev_dbg(sh->sc->dev, "Use default power setting\n");
++				break;
++			}
++			if (sh->cfg.wifi_tx_gain_level_b) {
++				phy_setting[i].data &= 0xffff0000;
++				phy_setting[i].data |=
++				    wifi_tx_gain[sh->cfg.
++						 wifi_tx_gain_level_b] &
++				    0x0000ffff;
++			}
++			if (sh->cfg.wifi_tx_gain_level_gn) {
++				phy_setting[i].data &= 0x0000ffff;
++				phy_setting[i].data |=
++				    wifi_tx_gain[sh->cfg.
++						 wifi_tx_gain_level_gn] &
++				    0xffff0000;
++			}
++			dev_dbg(sh->sc->dev, "TX power setting 0x%x\n", phy_setting[i].data);
++			init_iqk_cfg.cfg_def_tx_scale_11b =
++			    (phy_setting[i].data >> 0) & 0xff;
++			init_iqk_cfg.cfg_def_tx_scale_11b_p0d5 =
++			    (phy_setting[i].data >> 8) & 0xff;
++			init_iqk_cfg.cfg_def_tx_scale_11g =
++			    (phy_setting[i].data >> 16) & 0xff;
++			init_iqk_cfg.cfg_def_tx_scale_11g_p0d5 =
++			    (phy_setting[i].data >> 24) & 0xff;
++			break;
++		}
++	}
++	if (sh->cfg.volt_regulator == SSV6XXX_VOLT_LDO_CONVERT) {
++		dev_info(sh->sc->dev, "Using LDO voltage regulator\n");
++		for (i = 0;
++		     i <
++		     sizeof(ssv6200_rf_tbl) / sizeof(struct ssv6xxx_dev_table);
++		     i++) {
++			if (ssv6200_rf_tbl[i].address == ADR_PMU_2) {
++				ssv6200_rf_tbl[i].data &= 0xFFFFFFFE;
++				ssv6200_rf_tbl[i].data |= 0x00000000;
++			}
++		}
++	} else if (sh->cfg.volt_regulator == SSV6XXX_VOLT_DCDC_CONVERT) {
++		dev_info(sh->sc->dev, "Using DCDC buck regulator\n");
++		for (i = 0;
++		     i <
++		     sizeof(ssv6200_rf_tbl) / sizeof(struct ssv6xxx_dev_table);
++		     i++) {
++			if (ssv6200_rf_tbl[i].address == ADR_PMU_2) {
++				ssv6200_rf_tbl[i].data &= 0xFFFFFFFE;
++				ssv6200_rf_tbl[i].data |= 0x00000001;
++			}
++		}
++	} else {
++		dev_warn(sh->sc->dev, "Illegal regulator setting, using DCDC buck as default\n");
++	}
++	while (ssv_cfg.configuration[x][0]) {
++		for (i = 0;
++		     i <
++		     sizeof(ssv6200_rf_tbl) / sizeof(struct ssv6xxx_dev_table);
++		     i++) {
++			if (ssv6200_rf_tbl[i].address ==
++			    ssv_cfg.configuration[x][0]) {
++				ssv6200_rf_tbl[i].data =
++				    ssv_cfg.configuration[x][1];
++				break;
++			}
++		}
++		for (i = 0;
++		     i < sizeof(phy_setting) / sizeof(struct ssv6xxx_dev_table);
++		     i++) {
++			if (phy_setting[i].address ==
++			    ssv_cfg.configuration[x][0]) {
++				phy_setting[i].data =
++				    ssv_cfg.configuration[x][1];
++				break;
++			}
++		}
++		x++;
++	};
++	if (ret == 0)
++		ret = SSV6XXX_SET_HW_TABLE(sh, ssv6200_rf_tbl);
++	if (ret == 0)
++		ret = SMAC_REG_WRITE(sh, ADR_PHY_EN_1, 0x00000000);
++	SMAC_REG_READ(sh, ADR_PHY_EN_0, &regval);
++	if (regval & (1 << RG_RF_BB_CLK_SEL_SFT)) {
++		dev_dbg(sh->sc->dev, "already do clock switch\n");
++	} else {
++		dev_dbg(sh->sc->dev, "reset PLL\n");
++		SMAC_REG_READ(sh, ADR_DPLL_CP_PFD_REGISTER, &regval);
++		regval |=
++		    ((1 << RG_DP_BBPLL_PD_SFT) |
++		     (1 << RG_DP_BBPLL_SDM_EDGE_SFT));
++		SMAC_REG_WRITE(sh, ADR_DPLL_CP_PFD_REGISTER, regval);
++		regval &=
++		    ~((1 << RG_DP_BBPLL_PD_SFT) |
++		      (1 << RG_DP_BBPLL_SDM_EDGE_SFT));
++		SMAC_REG_WRITE(sh, ADR_DPLL_CP_PFD_REGISTER, regval);
++		mdelay(10);
++	}
++	if (ret == 0)
++		ret = SSV6XXX_SET_HW_TABLE(sh, ssv6200_phy_tbl);
++	if (ret == 0)
++		ret = SMAC_REG_WRITE(sh, ADR_TRX_DUMMY_REGISTER, 0xEAAAAAAA);
++	SMAC_REG_READ(sh, ADR_TRX_DUMMY_REGISTER, &regval);
++	if (regval != 0xEAAAAAAA) {
++		dev_warn(sh->sc->dev, "Unexpected register value\n");
++		WARN_ON(1);
++	}
++	if (ret == 0)
++		ret = SMAC_REG_WRITE(sh, ADR_PAD53, 0x21);
++	if (ret == 0)
++		ret = SMAC_REG_WRITE(sh, ADR_PAD54, 0x3000);
++	if (ret == 0)
++		ret = SMAC_REG_WRITE(sh, ADR_PIN_SEL_0, 0x4000);
++	if (ret == 0)
++		ret = SMAC_REG_WRITE(sh, 0xc0000304, 0x01);
++	if (ret == 0)
++		ret = SMAC_REG_WRITE(sh, 0xc0000308, 0x01);
++	if (ret == 0)
++		ret = SMAC_REG_WRITE(sh, ADR_CLOCK_SELECTION, 0x3);
++	if (ret == 0)
++		ret = SMAC_REG_WRITE(sh, ADR_TRX_DUMMY_REGISTER, 0xAAAAAAAA);
++	if ((ret = ssv6xxx_set_channel(sh->sc, sh->cfg.def_chan)))
++		return ret;
++	if (ret == 0)
++		ret = SMAC_REG_WRITE(sh, ADR_PHY_EN_1,
++				     (RG_PHYRX_MD_EN_MSK | RG_PHYTX_MD_EN_MSK |
++				      RG_PHY11GN_MD_EN_MSK | RG_PHY11B_MD_EN_MSK
++				      | RG_PHYRXFIFO_MD_EN_MSK |
++				      RG_PHYTXFIFO_MD_EN_MSK |
++				      RG_PHY11BGN_MD_EN_MSK));
++	return ret;
++}
++
++static void ssv6xxx_check_mac2(struct ssv_hw *sh)
++{
++	const u8 addr_mask[6] = { 0xfd, 0xff, 0xff, 0xff, 0xff, 0xfc };
++	u8 i;
++	bool invalid = false;
++	for (i = 0; i < 6; i++) {
++		if ((ssv_cfg.maddr[0][i] & addr_mask[i]) !=
++		    (ssv_cfg.maddr[1][i] & addr_mask[i])) {
++			invalid = true;
++			dev_dbg(sh->sc->dev, " i %d , mac1[i] %x, mac2[i] %x, mask %x \n", i,
++			       ssv_cfg.maddr[0][i], ssv_cfg.maddr[1][i],
++			       addr_mask[i]);
++			break;
++		}
++	}
++	if (invalid) {
++		memcpy(&ssv_cfg.maddr[1][0], &ssv_cfg.maddr[0][0], 6);
++		ssv_cfg.maddr[1][5] ^= 0x01;
++		if (ssv_cfg.maddr[1][5] < ssv_cfg.maddr[0][5]) {
++			u8 temp;
++			temp = ssv_cfg.maddr[0][5];
++			ssv_cfg.maddr[0][5] = ssv_cfg.maddr[1][5];
++			ssv_cfg.maddr[1][5] = temp;
++			sh->cfg.maddr[0][5] = ssv_cfg.maddr[0][5];
++		}
++		dev_warn(sh->sc->dev, "MAC 2 address invalid!!\n");
++		dev_warn(sh->sc->dev, "After modification, MAC1 %pM, MAC2 %pM\n",
++		       ssv_cfg.maddr[0], ssv_cfg.maddr[1]);
++	}
++}
++
++static int ssv6xxx_read_configuration(struct ssv_hw *sh)
++{
++	extern u32 sdio_sr_bhvr;
++	if (is_valid_ether_addr(&ssv_cfg.maddr[0][0]))
++		memcpy(&sh->cfg.maddr[0][0], &ssv_cfg.maddr[0][0], ETH_ALEN);
++	if (is_valid_ether_addr(&ssv_cfg.maddr[1][0])) {
++		ssv6xxx_check_mac2(sh);
++		memcpy(&sh->cfg.maddr[1][0], &ssv_cfg.maddr[1][0], ETH_ALEN);
++	}
++	if (ssv_cfg.hw_caps)
++		sh->cfg.hw_caps = ssv_cfg.hw_caps;
++	else
++		sh->cfg.hw_caps = SSV6200_HW_CAP_HT |
++		    SSV6200_HW_CAP_2GHZ |
++		    SSV6200_HW_CAP_SECURITY |
++		    SSV6200_HW_CAP_P2P |
++		    SSV6200_HT_CAP_SGI_20 |
++		    SSV6200_HW_CAP_AMPDU_RX |
++		    SSV6200_HW_CAP_AMPDU_TX | SSV6200_HW_CAP_AP;
++	if (ssv_cfg.def_chan)
++		sh->cfg.def_chan = ssv_cfg.def_chan;
++	else
++		sh->cfg.def_chan = 6;
++	sh->cfg.use_wpa2_only = ssv_cfg.use_wpa2_only;
++	if (ssv_cfg.crystal_type == 26)
++		sh->cfg.crystal_type = SSV6XXX_IQK_CFG_XTAL_26M;
++	else if (ssv_cfg.crystal_type == 40)
++		sh->cfg.crystal_type = SSV6XXX_IQK_CFG_XTAL_40M;
++	else if (ssv_cfg.crystal_type == 24)
++		sh->cfg.crystal_type = SSV6XXX_IQK_CFG_XTAL_24M;
++	else {
++		dev_warn(sh->sc->dev, "Please redefine xtal_clock(wifi.cfg)!!\n");
++		WARN_ON(1);
++		return 1;
++	}
++	if (ssv_cfg.volt_regulator < 2)
++		sh->cfg.volt_regulator = ssv_cfg.volt_regulator;
++	else {
++		dev_warn(sh->sc->dev, "Please redefine volt_regulator(wifi.cfg)!!\n");
++		WARN_ON(1);
++		return 1;
++	}
++	sh->cfg.wifi_tx_gain_level_gn = ssv_cfg.wifi_tx_gain_level_gn;
++	sh->cfg.wifi_tx_gain_level_b = ssv_cfg.wifi_tx_gain_level_b;
++	sh->cfg.rssi_ctl = ssv_cfg.rssi_ctl;
++	sh->cfg.sr_bhvr = ssv_cfg.sr_bhvr;
++	sdio_sr_bhvr = ssv_cfg.sr_bhvr;
++	sh->cfg.force_chip_identity = ssv_cfg.force_chip_identity;
++	strncpy(sh->cfg.firmware_path, ssv_cfg.firmware_path,
++		sizeof(sh->cfg.firmware_path) - 1);
++	strncpy(sh->cfg.flash_bin_path, ssv_cfg.flash_bin_path,
++		sizeof(sh->cfg.flash_bin_path) - 1);
++	strncpy(sh->cfg.mac_address_path, ssv_cfg.mac_address_path,
++		sizeof(sh->cfg.mac_address_path) - 1);
++	strncpy(sh->cfg.mac_output_path, ssv_cfg.mac_output_path,
++		sizeof(sh->cfg.mac_output_path) - 1);
++	sh->cfg.ignore_efuse_mac = ssv_cfg.ignore_efuse_mac;
++	sh->cfg.mac_address_mode = ssv_cfg.mac_address_mode;
++	return 0;
++}
++
++static int ssv6xxx_read_hw_info(struct ssv_softc *sc)
++{
++	struct ssv_hw *sh;
++	sh = kzalloc(sizeof(struct ssv_hw), GFP_KERNEL);
++	if (sh == NULL)
++		return -ENOMEM;
++	memset((void *)sh, 0, sizeof(struct ssv_hw));
++	sc->sh = sh;
++	sh->sc = sc;
++	sh->priv = sc->dev->platform_data;
++	if (ssv6xxx_read_configuration(sh))
++		return -ENOMEM;
++	sh->hci.dev = sc->dev;
++	sh->hci.hci_ops = NULL;
++	sh->hci.hci_rx_cb = ssv6200_rx;
++	sh->hci.rx_cb_args = (void *)sc;
++	sh->hci.hci_tx_cb = ssv6xxx_tx_cb;
++	sh->hci.tx_cb_args = (void *)sc;
++	sh->hci.hci_skb_update_cb = ssv6xxx_tx_rate_update;
++	sh->hci.skb_update_args = (void *)sc;
++	sh->hci.hci_tx_flow_ctrl_cb = ssv6200_tx_flow_control;
++	sh->hci.tx_fctrl_cb_args = (void *)sc;
++	sh->hci.hci_tx_q_empty_cb = ssv6xxx_tx_q_empty_cb;
++	sh->hci.tx_q_empty_args = (void *)sc;
++	sh->hci.if_ops = sh->priv->ops;
++	sh->hci.hci_tx_buf_free_cb = ssv6xxx_txbuf_free_skb;
++	sh->hci.tx_buf_free_args = (void *)sc;
++	return 0;
++}
++
++static int ssv6xxx_init_device(struct ssv_softc *sc, const char *name)
++{
++	struct ieee80211_hw *hw = sc->hw;
++	struct ssv_hw *sh;
++	int error = 0;
++	BUG_ON(!sc->dev->platform_data);
++	if ((error = ssv6xxx_read_hw_info(sc)) != 0) {
++		return error;
++	}
++	sh = sc->sh;
++	if (sh->cfg.hw_caps == 0)
++		return -1;
++	ssv6xxx_hci_register(&sh->hci);
++	efuse_read_all_map(sh);
++	if ((error = ssv6xxx_init_softc(sc)) != 0) {
++		ssv6xxx_deinit_softc(sc);
++		ssv6xxx_hci_deregister();
++		kfree(sh);
++		return error;
++	}
++	if ((error = ssv6xxx_init_hw(sc->sh)) != 0) {
++		ssv6xxx_deinit_hw(sc);
++		ssv6xxx_deinit_softc(sc);
++		ssv6xxx_hci_deregister();
++		kfree(sh);
++		return error;
++	}
++	if ((error = ieee80211_register_hw(hw)) != 0) {
++		dev_err(sc->dev, "Failed to register ieee80211 wireless device. ret=%d.\n", error);
++		ssv6xxx_deinit_hw(sc);
++		ssv6xxx_deinit_softc(sc);
++		ssv6xxx_hci_deregister();
++		kfree(sh);
++		return error;
++	}
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	ssv6xxx_init_debugfs(sc, name);
++#endif
++	return 0;
++}
++
++static void ssv6xxx_deinit_device(struct ssv_softc *sc)
++{
++	dev_dbg(sc->dev, "%s(): \n", __FUNCTION__);
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	ssv6xxx_deinit_debugfs(sc);
++#endif
++	ssv6xxx_rf_disable(sc->sh);
++	ieee80211_unregister_hw(sc->hw);
++	ssv6xxx_deinit_hw(sc);
++	ssv6xxx_deinit_softc(sc);
++	ssv6xxx_hci_deregister();
++	kfree(sc->sh);
++}
++
++extern struct ieee80211_ops ssv6200_ops;
++int ssv6xxx_dev_probe(struct platform_device *pdev)
++{
++#ifdef CONFIG_SSV6200_CLI_ENABLE
++	extern struct ssv_softc *ssv_dbg_sc;
++#endif
++#ifdef CONFIG_SSV_SMARTLINK
++	extern struct ssv_softc *ssv_smartlink_sc;
++#endif
++	struct ssv_softc *softc;
++	struct ieee80211_hw *hw;
++	int ret;
++	if (!pdev->dev.platform_data) {
++		dev_err(&pdev->dev, "no platform data specified!\n");
++		return -EINVAL;
++	}
++	hw = ieee80211_alloc_hw(sizeof(struct ssv_softc), &ssv6200_ops);
++	if (hw == NULL) {
++		dev_err(&pdev->dev, "Could not allocate memory for ieee80211 wireless device\n");
++		return -ENOMEM;
++	}
++	SET_IEEE80211_DEV(hw, &pdev->dev);
++	dev_set_drvdata(&pdev->dev, hw);
++	memset((void *)hw->priv, 0, sizeof(struct ssv_softc));
++	softc = hw->priv;
++	softc->hw = hw;
++	softc->dev = &pdev->dev;
++	//SET_IEEE80211_PERM_ADDR(hw, (const u8 *)&softc->sh->maddr[0]);
++	ret = ssv6xxx_init_device(softc, pdev->name);
++	if (ret) {
++		dev_err(&pdev->dev, "Failed to initialize device\n");
++		ieee80211_free_hw(hw);
++		return ret;
++	}
++#ifdef CONFIG_SSV6200_CLI_ENABLE
++	ssv_dbg_sc = softc;
++#endif
++#ifdef CONFIG_SSV_SMARTLINK
++	ssv_smartlink_sc = softc;
++#endif
++	wiphy_info(hw->wiphy, "%s\n", "SSV6200 of South Silicon Valley");
++	return 0;
++}
++
++EXPORT_SYMBOL(ssv6xxx_dev_probe);
++void ssv6xxx_dev_remove(struct platform_device *pdev)
++{
++	struct ieee80211_hw *hw = dev_get_drvdata(&pdev->dev);
++	struct ssv_softc *softc = hw->priv;
++	dev_dbg(&pdev->dev, "ssv6xxx_dev_remove(): pdev=%p, hw=%p\n", pdev, hw);
++	ssv6xxx_deinit_device(softc);
++	dev_dbg(&pdev->dev, "ieee80211_free_hw(): \n");
++	ieee80211_free_hw(hw);
++	dev_info(&pdev->dev, "driver unloaded\n");
++	//return 0;
++}
++
++EXPORT_SYMBOL(ssv6xxx_dev_remove);
++static const struct platform_device_id ssv6xxx_id_table[] = {
++	{
++	 .name = "ssv6200",
++	 .driver_data = 0x00,
++	 },
++	{},
++};
++
++MODULE_DEVICE_TABLE(platform, ssv6xxx_id_table);
++static struct platform_driver ssv6xxx_driver = {
++	.probe = ssv6xxx_dev_probe,
++	.remove = ssv6xxx_dev_remove,
++	.id_table = ssv6xxx_id_table,
++	.driver = {
++		   .name = "SSV WLAN driver",
++		   .owner = THIS_MODULE,
++		   }
++};
++
++int ssv6xxx_init(void)
++{
++	extern void *ssv_dbg_phy_table;
++	extern u32 ssv_dbg_phy_len;
++	extern void *ssv_dbg_rf_table;
++	extern u32 ssv_dbg_rf_len;
++	ssv_dbg_phy_table = (void *)ssv6200_phy_tbl;
++	ssv_dbg_phy_len =
++	    sizeof(ssv6200_phy_tbl) / sizeof(struct ssv6xxx_dev_table);
++	ssv_dbg_rf_table = (void *)ssv6200_rf_tbl;
++	ssv_dbg_rf_len =
++	    sizeof(ssv6200_rf_tbl) / sizeof(struct ssv6xxx_dev_table);
++	return platform_driver_register(&ssv6xxx_driver);
++}
++
++void ssv6xxx_exit(void)
++{
++	platform_driver_unregister(&ssv6xxx_driver);
++}
++
++EXPORT_SYMBOL(ssv6xxx_init);
++EXPORT_SYMBOL(ssv6xxx_exit);
+diff --git a/drivers/net/wireless/ssv6051/smac/init.h b/drivers/net/wireless/ssv6051/smac/init.h
+new file mode 100644
+index 000000000000..97994d00d4da
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/init.h
+@@ -0,0 +1,23 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation, either version 3 of the License, or
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _INIT_H_
++#define _INIT_H_
++int ssv6xxx_init_mac(struct ssv_hw *sh);
++int ssv6xxx_do_iq_calib(struct ssv_hw *sh, struct ssv6xxx_iqk_cfg *p_cfg);
++void ssv6xxx_deinit_mac(struct ssv_softc *sc);
++void ssv6xxx_restart_hw(struct ssv_softc *sc);
++#endif
+diff --git a/drivers/net/wireless/ssv6051/smac/lib.c b/drivers/net/wireless/ssv6051/smac/lib.c
+new file mode 100644
+index 000000000000..ccf0974b0f20
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/lib.c
+@@ -0,0 +1,33 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation, either version 3 of the License, or
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <ssv6200.h>
++#include "lib.h"
++struct sk_buff *ssv_skb_alloc(s32 len)
++{
++	struct sk_buff *skb;
++	skb = __dev_alloc_skb(len + 128, GFP_KERNEL);
++	if (skb != NULL) {
++		skb_put(skb, 0x20);
++		skb_pull(skb, 0x20);
++	}
++	return skb;
++}
++
++void ssv_skb_free(struct sk_buff *skb)
++{
++	dev_kfree_skb_any(skb);
++}
+diff --git a/drivers/net/wireless/ssv6051/smac/lib.h b/drivers/net/wireless/ssv6051/smac/lib.h
+new file mode 100644
+index 000000000000..266cf7afac95
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/lib.h
+@@ -0,0 +1,23 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation, either version 3 of the License, or
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _LIB_H_
++#define _LIB_H_
++#include <linux/skbuff.h>
++#include <linux/netdevice.h>
++struct sk_buff *ssv_skb_alloc(s32 len);
++void ssv_skb_free(struct sk_buff *skb);
++#endif
+diff --git a/drivers/net/wireless/ssv6051/smac/linux_80211.h b/drivers/net/wireless/ssv6051/smac/linux_80211.h
+new file mode 100644
+index 000000000000..e268808e3c93
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/linux_80211.h
+@@ -0,0 +1,24 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation, either version 3 of the License, or
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _LINUX_80211_H_
++#define _LINUX_80211_H_
++#if LINUX_VERSION_CODE < KERNEL_VERSION(4,7,0)
++#define INDEX_80211_BAND_2GHZ IEEE80211_BAND_2GHZ
++#else
++#define INDEX_80211_BAND_2GHZ NL80211_BAND_2GHZ
++#endif
++#endif
+diff --git a/drivers/net/wireless/ssv6051/smac/p2p.c b/drivers/net/wireless/ssv6051/smac/p2p.c
+new file mode 100644
+index 000000000000..60fd8effd6ec
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/p2p.c
+@@ -0,0 +1,305 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation, either version 3 of the License, or
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <ssv6200.h>
++#include <linux/types.h>
++#include <linux/nl80211.h>
++#include <net/mac80211.h>
++#include <linux/nl80211.h>
++#include <linux/etherdevice.h>
++#include <linux/delay.h>
++#include <linux/version.h>
++#include <linux/time.h>
++#include <linux/kthread.h>
++#include <net/mac80211.h>
++#include <ssv6200.h>
++#include "p2p.h"
++#include "dev.h"
++#include "lib.h"
++#ifdef CONFIG_P2P_NOA
++#define P2P_IE_VENDOR_TYPE 0x506f9a09
++#define P2P_NOA_DETECT_INTERVAL (5 * HZ)
++#ifndef MAC2STR
++#define MAC2STR(a) (a)[0], (a)[1], (a)[2], (a)[3], (a)[4], (a)[5]
++#define MACSTR "%02x:%02x:%02x:%02x:%02x:%02x"
++#define COMPACT_MACSTR "%02x%02x%02x%02x%02x%02x"
++#endif
++void ssv6xxx_send_noa_cmd(struct ssv_softc *sc,
++			  struct ssv6xxx_p2p_noa_param *p2p_noa_param);
++static inline u32 WPA_GET_BE32(const u8 * a)
++{
++	return (a[0] << 24) | (a[1] << 16) | (a[2] << 8) | a[3];
++}
++
++static inline u16 WPA_GET_LE16(const u8 * a)
++{
++	return (a[1] << 8) | a[0];
++}
++
++static inline u32 WPA_GET_LE32(const u8 * a)
++{
++	return (a[3] << 24) | (a[2] << 16) | (a[1] << 8) | a[0];
++}
++
++#define IEEE80211_HDRLEN 24
++enum p2p_attr_id {
++	P2P_ATTR_STATUS = 0,
++	P2P_ATTR_MINOR_REASON_CODE = 1,
++	P2P_ATTR_CAPABILITY = 2,
++	P2P_ATTR_DEVICE_ID = 3,
++	P2P_ATTR_GROUP_OWNER_INTENT = 4,
++	P2P_ATTR_CONFIGURATION_TIMEOUT = 5,
++	P2P_ATTR_LISTEN_CHANNEL = 6,
++	P2P_ATTR_GROUP_BSSID = 7,
++	P2P_ATTR_EXT_LISTEN_TIMING = 8,
++	P2P_ATTR_INTENDED_INTERFACE_ADDR = 9,
++	P2P_ATTR_MANAGEABILITY = 10,
++	P2P_ATTR_CHANNEL_LIST = 11,
++	P2P_ATTR_NOTICE_OF_ABSENCE = 12,
++	P2P_ATTR_DEVICE_INFO = 13,
++	P2P_ATTR_GROUP_INFO = 14,
++	P2P_ATTR_GROUP_ID = 15,
++	P2P_ATTR_INTERFACE = 16,
++	P2P_ATTR_OPERATING_CHANNEL = 17,
++	P2P_ATTR_INVITATION_FLAGS = 18,
++	P2P_ATTR_OOB_GO_NEG_CHANNEL = 19,
++	P2P_ATTR_VENDOR_SPECIFIC = 221
++};
++struct ssv6xxx_p2p_noa_attribute {
++	u8 index;
++	u16 ctwindows_oppps;
++	struct ssv6xxx_p2p_noa_param noa_param;
++};
++extern void _ssv6xxx_hexdump(const char *title, const u8 * buf, size_t len);
++bool p2p_find_noa(const u8 * ies, struct ssv6xxx_p2p_noa_attribute *noa_attr)
++{
++	const u8 *end, *pos, *ie;
++	u32 len;
++	len = ie[1] - 4;
++	pos = ie + 6;
++	end = pos + len;
++	while (pos < end) {
++		u16 attr_len;
++		if (pos + 2 >= end) {
++			return false;
++		}
++		attr_len = WPA_GET_LE16(pos + 1);
++		if (pos + 3 + attr_len > end) {
++			return false;
++		}
++		if (pos[0] != P2P_ATTR_NOTICE_OF_ABSENCE) {
++			pos += 3 + attr_len;
++			continue;
++		}
++		if (attr_len < 15) {
++			printk
++			    ("*********************NOA descriptor does not exist len[%d]\n",
++			     attr_len);
++			break;
++		}
++		if (attr_len > 15)
++			printk("More than one NOA descriptor\n");
++		noa_attr->index = pos[3];
++		noa_attr->ctwindows_oppps = pos[4];
++		noa_attr->noa_param.count = pos[5];
++		noa_attr->noa_param.duration = WPA_GET_LE32(&pos[6]);
++		noa_attr->noa_param.interval = WPA_GET_LE32(&pos[10]);
++		noa_attr->noa_param.start_time = WPA_GET_LE32(&pos[14]);
++		return true;
++	}
++	return false;
++}
++
++bool p2p_get_attribute_noa(const u8 * ies, u32 oui_type,
++			   struct ssv6xxx_p2p_noa_attribute *noa_attr)
++{
++	const u8 *end, *pos, *ie;
++	u32 len;
++	pos = ies;
++	end = ies + ies_len;
++	ie = NULL;
++	while (pos + 1 < end) {
++		if (pos + 2 + pos[1] > end)
++			return false;
++		if (pos[0] == WLAN_EID_VENDOR_SPECIFIC && pos[1] >= 4 &&
++		    WPA_GET_BE32(&pos[2]) == oui_type) {
++			ie = pos;
++			if (p2p_find_noa(ie, 0, noa_attr) == true)
++				return true;
++		}
++		pos += 2 + pos[1];
++	}
++	return false;
++}
++
++void ssv6xxx_process_noa_event(struct ssv_softc *sc, struct sk_buff *skb)
++{
++	struct cfg_host_event *host_event;
++	struct ssv62xx_noa_evt *noa_evt;
++	host_event = (struct cfg_host_event *)skb->data;
++	noa_evt = (struct ssv62xx_noa_evt *)&host_event->dat[0];
++	switch (noa_evt->evt_id) {
++	case SSV6XXX_NOA_START:
++		sc->p2p_noa.active_noa_vif |= (1 << noa_evt->vif);
++		printk("SSV6XXX_NOA_START===>[%08x]\n",
++		       sc->p2p_noa.active_noa_vif);
++		break;
++	case SSV6XXX_NOA_STOP:
++		sc->p2p_noa.active_noa_vif &= ~(1 << noa_evt->vif);
++		printk("SSV6XXX_NOA_STOP===>[%08x]\n",
++		       sc->p2p_noa.active_noa_vif);
++		break;
++	default:
++		printk("--------->NOA wrong command<---------\n");
++		break;
++	}
++}
++
++void ssv6xxx_noa_reset(struct ssv_softc *sc)
++{
++	unsigned long flags;
++	printk("Reset NOA param...\n");
++	spin_lock_irqsave(&sc->p2p_noa.p2p_config_lock, flags);
++	memset(&sc->p2p_noa.noa_detect, 0,
++	       sizeof(struct ssv_p2p_noa_detect) * SSV_NUM_VIF);
++	sc->p2p_noa.active_noa_vif = 0;
++	sc->p2p_noa.monitor_noa_vif = 0;
++	spin_unlock_irqrestore(&sc->p2p_noa.p2p_config_lock, flags);
++}
++
++void ssv6xxx_noa_host_stop_noa(struct ssv_softc *sc, u8 vif_id)
++{
++	struct ssv6xxx_p2p_noa_attribute noa_attr;
++	if (sc->p2p_noa.noa_detect[vif_id].p2p_noa_index >= 0) {
++		sc->p2p_noa.noa_detect[vif_id].p2p_noa_index = -1;
++		sc->p2p_noa.active_noa_vif &= ~(1 << vif_id);
++		memset(&sc->p2p_noa.noa_detect[vif_id].noa_param_cmd, 0,
++		       sizeof(struct ssv6xxx_p2p_noa_param));
++		printk("->remove NOA operating vif[%d]\n", vif_id);
++		noa_attr.noa_param.enable = 0;
++		noa_attr.noa_param.vif_id = vif_id;
++		ssv6xxx_send_noa_cmd(sc, &noa_attr.noa_param);
++	}
++}
++
++void ssv6xxx_noa_detect(struct ssv_softc *sc, struct ieee80211_hdr *hdr,
++			u32 len)
++{
++	int i;
++	unsigned long flags;
++	struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)hdr;
++	struct ssv6xxx_p2p_noa_attribute noa_attr;
++	spin_lock_irqsave(&sc->p2p_noa.p2p_config_lock, flags);
++	if (sc->p2p_noa.monitor_noa_vif == 0)
++		goto out;
++	for (i = 0; i < SSV_NUM_VIF; i++) {
++		if (sc->p2p_noa.noa_detect[i].noa_addr == NULL)
++			continue;
++		if (memcmp(mgmt->bssid, sc->p2p_noa.noa_detect[i].noa_addr, 6)
++		    != 0)
++			continue;
++		if (sc->p2p_noa.active_noa_vif &&
++		    ((sc->p2p_noa.active_noa_vif & 1 << i) == 0))
++			continue;
++		sc->p2p_noa.noa_detect[i].last_rx = jiffies;
++		if (p2p_get_attribute_noa((const u8 *)mgmt->u.beacon.variable,
++					  len - (IEEE80211_HDRLEN +
++						 sizeof(mgmt->u.beacon)),
++					  P2P_IE_VENDOR_TYPE,
++					  &noa_attr) == false) {
++			continue;
++		}
++		if (sc->p2p_noa.noa_detect[i].p2p_noa_index == noa_attr.index) {
++			goto out;
++		}
++		printk(MACSTR "->set NOA element\n", MAC2STR(mgmt->bssid));
++		sc->p2p_noa.active_noa_vif |= (1 << i);
++		sc->p2p_noa.noa_detect[i].p2p_noa_index = noa_attr.index;
++		memcpy(&sc->p2p_noa.noa_detect[i].noa_param_cmd,
++		       &noa_attr.noa_param,
++		       sizeof(struct ssv6xxx_p2p_noa_param));
++		noa_attr.noa_param.enable = 1;
++		noa_attr.noa_param.vif_id = i;
++		memcpy(noa_attr.noa_param.addr, hdr->addr2, 6);
++		ssv6xxx_send_noa_cmd(sc, &noa_attr.noa_param);
++	}
++ out:
++	spin_unlock_irqrestore(&sc->p2p_noa.p2p_config_lock, flags);
++}
++
++void ssv6xxx_noa_hdl_bss_change(struct ssv_softc *sc,
++				enum ssv6xxx_noa_conf conf, u8 vif_idx)
++{
++	unsigned long flags;
++	if (sc->vif_info[vif_idx].vif->type != NL80211_IFTYPE_STATION ||
++	    sc->vif_info[vif_idx].vif->p2p != true)
++		return;
++	spin_lock_irqsave(&sc->p2p_noa.p2p_config_lock, flags);
++	printk("====>[NOA]ssv6xxx_noa_hdl_bss_change conf[%d] vif_idx[%d]\n",
++	       conf, vif_idx);
++	switch (conf) {
++	case MONITOR_NOA_CONF_ADD:
++		memset(&sc->p2p_noa.noa_detect[vif_idx], 0,
++		       sizeof(struct ssv_p2p_noa_detect));
++		sc->p2p_noa.noa_detect[vif_idx].noa_addr =
++		    sc->vif_info[vif_idx].vif->bss_conf.bssid;
++		sc->p2p_noa.noa_detect[vif_idx].p2p_noa_index = -1;
++		sc->p2p_noa.noa_detect[vif_idx].last_rx = jiffies;
++		sc->p2p_noa.monitor_noa_vif |= 1 << vif_idx;
++		break;
++	case MONITOR_NOA_CONF_REMOVE:
++		sc->p2p_noa.monitor_noa_vif &= ~(1 << vif_idx);
++		sc->p2p_noa.noa_detect[vif_idx].noa_addr = NULL;
++		ssv6xxx_noa_host_stop_noa(sc, vif_idx);
++		break;
++	default:
++		break;
++	}
++	spin_unlock_irqrestore(&sc->p2p_noa.p2p_config_lock, flags);
++}
++
++void ssv6xxx_send_noa_cmd(struct ssv_softc *sc,
++			  struct ssv6xxx_p2p_noa_param *p2p_noa_param)
++{
++	struct sk_buff *skb;
++	struct cfg_host_cmd *host_cmd;
++	int retry_cnt = 5;
++	skb =
++	    ssv_skb_alloc(HOST_CMD_HDR_LEN +
++			  sizeof(struct ssv6xxx_p2p_noa_param));
++	skb->data_len = HOST_CMD_HDR_LEN + sizeof(struct ssv6xxx_p2p_noa_param);
++	skb->len = skb->data_len;
++	host_cmd = (struct cfg_host_cmd *)skb->data;
++	host_cmd->c_type = HOST_CMD;
++	host_cmd->h_cmd = (u8) SSV6XXX_HOST_CMD_SET_NOA;
++	host_cmd->len = skb->data_len;
++	memcpy(host_cmd->dat32, p2p_noa_param,
++	       sizeof(struct ssv6xxx_p2p_noa_param));
++	printk
++	    ("Noa cmd NOA Parameter:\nEnable=%d\nInterval=%d\nDuration=%d\nStart_time=0x%08x\nCount=%d\nAddr=[%02x:%02x:%02x:%02x:%02x:%02x]vif[%d]\n\n",
++	     p2p_noa_param->enable, p2p_noa_param->interval,
++	     p2p_noa_param->duration, p2p_noa_param->start_time,
++	     p2p_noa_param->count, p2p_noa_param->addr[0],
++	     p2p_noa_param->addr[1], p2p_noa_param->addr[2],
++	     p2p_noa_param->addr[3], p2p_noa_param->addr[4],
++	     p2p_noa_param->addr[5], p2p_noa_param->vif_id);
++	while ((HCI_SEND_CMD(sc->sh, skb) != 0) && (retry_cnt)) {
++		printk(KERN_INFO "NOA cmd retry=%d!!\n", retry_cnt);
++		retry_cnt--;
++	}
++	ssv_skb_free(skb);
++}
++#endif
+diff --git a/drivers/net/wireless/ssv6051/smac/p2p.h b/drivers/net/wireless/ssv6051/smac/p2p.h
+new file mode 100644
+index 000000000000..a5bb99c61bb0
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/p2p.h
+@@ -0,0 +1,58 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation, either version 3 of the License, or
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _P2P_H_
++#define _P2P_H_
++#include <net/mac80211.h>
++#include <ssv6200.h>
++#include "drv_comm.h"
++#ifdef CONFIG_P2P_NOA
++#define P2P_MAX_NOA_INTERFACE 1
++struct ssv_p2p_noa_detect {
++	const u8 *noa_addr;
++	s16 p2p_noa_index;
++	unsigned long last_rx;
++	struct ssv6xxx_p2p_noa_param noa_param_cmd;
++};
++struct ssv_p2p_noa {
++	spinlock_t p2p_config_lock;
++	struct ssv_p2p_noa_detect noa_detect[SSV_NUM_VIF];
++	u8 active_noa_vif;
++	u8 monitor_noa_vif;
++};
++enum ssv_cmd_state {
++	SSC_CMD_STATE_IDLE,
++	SSC_CMD_STATE_WAIT_RSP,
++};
++struct ssv_cmd_Info {
++	struct sk_buff_head cmd_que;
++	struct sk_buff_head evt_que;
++	enum ssv_cmd_state state;
++};
++enum ssv6xxx_noa_conf {
++	MONITOR_NOA_CONF_ADD,
++	MONITOR_NOA_CONF_REMOVE,
++};
++struct ssv_softc;
++void ssv6xxx_process_noa_event(struct ssv_softc *sc, struct sk_buff *skb);
++void ssv6xxx_noa_hdl_bss_change(struct ssv_softc *sc,
++				enum ssv6xxx_noa_conf conf, u8 vif_idx);
++void ssv6xxx_process_noa_event(struct ssv_softc *sc, struct sk_buff *skb);
++void ssv6xxx_noa_detect(struct ssv_softc *sc, struct ieee80211_hdr *hdr,
++			u32 len);
++void ssv6xxx_noa_reset(struct ssv_softc *sc);
++#endif
++#endif
+diff --git a/drivers/net/wireless/ssv6051/smac/sar.c b/drivers/net/wireless/ssv6051/smac/sar.c
+new file mode 100644
+index 000000000000..44a47a5c7a0f
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/sar.c
+@@ -0,0 +1,208 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation, either version 3 of the License, or
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <ssv6200_reg.h>
++#include <ssv6200_aux.h>
++#include <linux/fs.h>
++#include "dev.h"
++#include "sar.h"
++
++WIFI_FLASH_CCFG flash_cfg = {
++	//16bytes
++	0x6051, 0x3009, 0x20170519, 0x1, 0x0, 0x0,
++	{			//16bytes
++	 {0x47c000, 0x47c000, 0x47c000, 0x9, 0x1d, 0x0},
++	 //16bytes
++	 {0x79807980, 0x79807980, 0x79807980, 0x9, 0x1d, 0x0}
++	 }
++};
++
++WIFI_FLASH_CCFG *pflash_cfg;
++
++struct t_sar_info sar_info[] = {
++	{SAR_LVL_INVALID, 0x0047c000, NULL},
++	{SAR_LVL_INVALID, 0x79807980, NULL}
++};
++
++int sar_info_size = sizeof(sar_info) / sizeof(sar_info[0]);
++
++static u8 get_sar_lvl(u32 sar)
++{
++	static u32 prev_sar = 0;
++	int i;
++	u8 changed = 0x0;
++
++	if (sar == prev_sar)
++		return changed;
++
++	pr_debug("[thermal_sar] %d\n", (int)sar);
++
++	for (i = 0; i < sar_info_size; i++) {
++		if (sar_info[i].lvl == SAR_LVL_INVALID) {	//if driver loaded under LT/HT env, it would cause wrong settings at this time.
++			sar_info[i].lvl = SAR_LVL_RT;
++			sar_info[i].value = sar_info[i].p->rt;
++			changed |= BIT(i);
++		} else if (sar_info[i].lvl == SAR_LVL_RT) {
++			if (sar < prev_sar) {
++				if (sar <= (u32) (sar_info[i].p->lt_ts - 2)) {	//we need check if (g_tt_lt - 1) < SAR_MIN
++					sar_info[i].lvl = SAR_LVL_LT;
++					sar_info[i].value = sar_info[i].p->lt;
++					changed |= BIT(i);
++				}
++			} else if (sar > prev_sar) {
++				if (sar >= (u32) (sar_info[i].p->ht_ts + 2)) {	//we need check if (g_tt_lt + 1) > SAR_MAX
++					sar_info[i].lvl = SAR_LVL_HT;
++					sar_info[i].value = sar_info[i].p->ht;
++					changed |= BIT(i);
++				}
++			}
++		} else if (sar_info[i].lvl == SAR_LVL_LT) {
++			if (sar >= (u32) (sar_info[i].p->lt_ts + 2)) {
++				sar_info[i].lvl = SAR_LVL_RT;
++				sar_info[i].value = sar_info[i].p->rt;
++				changed |= BIT(i);
++			}
++		} else if (sar_info[i].lvl == SAR_LVL_HT) {
++			if (sar <= (u32) (sar_info[i].p->ht_ts - 2)) {
++				sar_info[i].lvl = SAR_LVL_RT;
++				sar_info[i].value = sar_info[i].p->rt;
++				changed |= BIT(i);
++			}
++		}
++	}
++	if (changed) {
++		pr_debug("changed: 0x%x\n", changed);
++	}
++	prev_sar = sar;
++	return changed;
++}
++
++void sar_monitor(u32 curr_sar, struct ssv_softc *sc)
++{
++	//static u32 prev_sar_lvl = SAR_LVL_INVALID; //sar = 0, temparature < -25C
++	u8 changed;
++	changed = get_sar_lvl(curr_sar);
++
++	if (changed & BIT(SAR_TXGAIN_INDEX)) {
++		dev_dbg(sc->dev, "TXGAIN: 0x%08x\n", sar_info[SAR_TXGAIN_INDEX].value);
++		SMAC_REG_WRITE(sc->sh, ADR_TX_GAIN_FACTOR,
++			       sar_info[SAR_TXGAIN_INDEX].value);
++	}
++	if (changed & BIT(SAR_XTAL_INDEX)) {
++		dev_dbg(sc->dev, "XTAL: 0x%08x\n", sar_info[SAR_XTAL_INDEX].value);
++		SMAC_REG_WRITE(sc->sh, ADR_SYN_KVCO_XO_FINE_TUNE_CBANK,
++			       sar_info[SAR_XTAL_INDEX].value);
++	}
++}
++
++/*
++    SET_RG_SARADC_THERMAL(1);     //ce010030[26]
++    SET_RG_EN_SARADC(1);          //ce010030[30]
++    while(!GET_SAR_ADC_FSM_RDY);  //ce010094[23]
++    sar_code = GET_RG_SARADC_BIT; //ce010094[21:16]
++    SET_RG_SARADC_THERMAL(0);
++    SET_RG_EN_SARADC(0);
++*/
++void thermal_monitor(struct work_struct *work)
++{
++	struct ssv_softc *sc =
++	    container_of(work, struct ssv_softc, thermal_monitor_work.work);
++	u32 curr_sar;
++
++	u32 temp;
++	if (sc->ps_status == PWRSV_PREPARE) {
++		dev_dbg(sc->dev, "sar PWRSV_PREPARE\n");
++		return;
++	}
++
++	mutex_lock(&sc->mutex);
++	SMAC_REG_READ(sc->sh, ADR_RX_11B_CCA_1, &temp);
++	if (temp == RX_11B_CCA_IN_SCAN) {
++		dev_dbg(sc->dev, "in scan\n");
++		mutex_unlock(&sc->mutex);
++		queue_delayed_work(sc->thermal_wq, &sc->thermal_monitor_work,
++				   THERMAL_MONITOR_TIME);
++		return;
++	}
++	SMAC_REG_READ(sc->sh, ADR_RX_ADC_REGISTER, &temp);
++	//printk("ori %08x:%08x\n", ADR_RX_ADC_REGISTER, temp);
++	SMAC_REG_SET_BITS(sc->sh, ADR_RX_ADC_REGISTER,
++			  (1 << RG_SARADC_THERMAL_SFT), RG_SARADC_THERMAL_MSK);
++	SMAC_REG_SET_BITS(sc->sh, ADR_RX_ADC_REGISTER, (1 << RG_EN_SARADC_SFT),
++			  RG_EN_SARADC_MSK);
++
++	do {
++		msleep(1);
++		SMAC_REG_READ(sc->sh, ADR_READ_ONLY_FLAGS_1, &temp);
++	} while (((temp & SAR_ADC_FSM_RDY_MSK) >> SAR_ADC_FSM_RDY_SFT) != 1);
++	//printk("SAR_ADC_FSM_RDY_STAT %d\n", (temp & SAR_ADC_FSM_RDY_MSK) >> SAR_ADC_FSM_RDY_SFT);
++	curr_sar = (temp & RG_SARADC_BIT_MSK) >> RG_SARADC_BIT_SFT;
++	SMAC_REG_READ(sc->sh, ADR_RX_ADC_REGISTER, &temp);
++
++	//printk("new %08x:%08x\n", ADR_RX_ADC_REGISTER, temp);
++
++	SMAC_REG_SET_BITS(sc->sh, ADR_RX_ADC_REGISTER,
++			  (0 << RG_SARADC_THERMAL_SFT), RG_SARADC_THERMAL_MSK);
++	SMAC_REG_SET_BITS(sc->sh, ADR_RX_ADC_REGISTER, (0 << RG_EN_SARADC_SFT),
++			  RG_EN_SARADC_MSK);
++	sar_monitor(curr_sar, sc);
++
++	mutex_unlock(&sc->mutex);
++
++	queue_delayed_work(sc->thermal_wq, &sc->thermal_monitor_work,
++			   THERMAL_MONITOR_TIME);
++}
++
++int get_flash_info(struct ssv_softc *sc)
++{
++	struct file *fp = (struct file *)NULL;
++	int i, ret;
++
++	pflash_cfg = &flash_cfg;
++
++	if (sc->sh->cfg.flash_bin_path[0] != 0x00) {
++		fp = filp_open(sc->sh->cfg.flash_bin_path, O_RDONLY, 0);
++		if (IS_ERR(fp) || fp == NULL) {
++			fp = filp_open(SEC_CFG_BIN_NAME, O_RDONLY, 0);
++		}
++	} else {
++		fp = filp_open(DEFAULT_CFG_BIN_NAME, O_RDONLY, 0);
++		if (IS_ERR(fp) || fp == NULL) {
++			fp = filp_open(SEC_CFG_BIN_NAME, O_RDONLY, 0);
++		}
++	}
++	if (IS_ERR(fp) || fp == NULL) {
++		dev_info(sc->dev, "flash_file %s not found, disable sar\n",
++		       DEFAULT_CFG_BIN_NAME);
++		//WARN_ON(1);
++		ret = 0;
++		return ret;
++	}
++
++	fp->f_op->read(fp, (char *)pflash_cfg, sizeof(flash_cfg), &fp->f_pos);
++
++	filp_close(fp, NULL);
++	ret = 1;
++
++	for (i = 0; i < sar_info_size; i++) {
++		sar_info[i].p = &flash_cfg.sar_rlh[i];
++		dev_dbg(sc->dev, "rt = %x, lt = %x, ht = %x\n", sar_info[i].p->rt,
++		       sar_info[i].p->lt, sar_info[i].p->ht);
++		dev_dbg(sc->dev, "lt_ts = %x, ht_ts = %x\n", sar_info[i].p->lt_ts,
++		       sar_info[i].p->ht_ts);
++	}
++	return ret;
++}
+diff --git a/drivers/net/wireless/ssv6051/smac/sar.h b/drivers/net/wireless/ssv6051/smac/sar.h
+new file mode 100644
+index 000000000000..291d58f236eb
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/sar.h
+@@ -0,0 +1,63 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation, either version 3 of the License, or
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _CFG_H_
++#define _CFG_H_
++#include <linux/kthread.h>
++
++#define SAR_XTAL_INDEX     (0)
++#define SAR_TXGAIN_INDEX    (1)
++#define THERMAL_MONITOR_TIME (10 * HZ)
++#define DEFAULT_CFG_BIN_NAME "/lib/firmware/ssv6051_sar.bin"
++#define SEC_CFG_BIN_NAME "/lib/firmware/ssv6xxx_sar.bin"
++enum {
++	SAR_LVL_LT,
++	SAR_LVL_RT,
++	SAR_LVL_HT,
++	SAR_LVL_INVALID
++};
++
++struct flash_thermal_info {
++	u32 rt;
++	u32 lt;
++	u32 ht;
++	u8 lt_ts;
++	u8 ht_ts;
++	u16 reserve;
++};
++typedef struct t_WIFI_FLASH_CCFG {
++	//16bytes
++	u16 chip_id;
++	u16 sid;
++	u32 date;
++	u16 version;
++	u16 reserve_1;
++	u32 reserve_2;
++	//16bytes
++	struct flash_thermal_info sar_rlh[2];
++} WIFI_FLASH_CCFG;
++
++struct t_sar_info {
++	u32 lvl;
++	u32 value;
++	struct flash_thermal_info *p;
++};
++
++void thermal_monitor(struct work_struct *work);
++int get_flash_info(struct ssv_softc *sc);
++void flash_hexdump(void);
++
++#endif
+diff --git a/drivers/net/wireless/ssv6051/smac/sec.h b/drivers/net/wireless/ssv6051/smac/sec.h
+new file mode 100644
+index 000000000000..04a0f47c8ce2
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/sec.h
+@@ -0,0 +1,52 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation, either version 3 of the License, or
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef SEC_H
++#define SEC_H
++#include <linux/types.h>
++#include <linux/ieee80211.h>
++#include <net/mac80211.h>
++#define CCMP_TK_LEN 16
++#define TKIP_KEY_LEN 32
++#define WEP_KEY_LEN 13
++struct ssv_crypto_ops {
++	const char *name;
++	struct list_head list;
++	void *(*init)(int keyidx);
++	void (*deinit)(void *priv);
++	int (*encrypt_mpdu)(struct sk_buff * skb, int hdr_len, void *priv);
++	int (*decrypt_mpdu)(struct sk_buff * skb, int hdr_len, void *priv);
++	int (*encrypt_msdu)(struct sk_buff * skb, int hdr_len, void *priv);
++	int (*decrypt_msdu)(struct sk_buff * skb, int keyidx, int hdr_len,
++			    void *priv);
++	int (*set_tx_pn)(u8 * seq, void *priv);
++	int (*set_key)(void *key, int len, u8 * seq, void *priv);
++	int (*get_key)(void *key, int len, u8 * seq, void *priv);
++	char *(*print_stats)(char *p, void *priv);
++	unsigned long (*get_flags)(void *priv);
++	unsigned long (*set_flags)(unsigned long flags, void *priv);
++	int extra_mpdu_prefix_len, extra_mpdu_postfix_len;
++	int extra_msdu_prefix_len, extra_msdu_postfix_len;
++};
++struct ssv_crypto_data {
++	struct ssv_crypto_ops *ops;
++	void *priv;
++	rwlock_t lock;
++};
++struct ssv_crypto_ops *get_crypto_ccmp_ops(void);
++struct ssv_crypto_ops *get_crypto_tkip_ops(void);
++struct ssv_crypto_ops *get_crypto_wep_ops(void);
++#endif
+diff --git a/drivers/net/wireless/ssv6051/smac/smartlink.c b/drivers/net/wireless/ssv6051/smac/smartlink.c
+new file mode 100644
+index 000000000000..69e8d5118e09
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/smartlink.c
+@@ -0,0 +1,340 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation, either version 3 of the License, or
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <net/sock.h>
++#include <linux/socket.h>
++#include <linux/net.h>
++#include <asm/types.h>
++#include <linux/netlink.h>
++#include <linux/skbuff.h>
++#include <linux/version.h>
++#include <ssv6200.h>
++#include "lib.h"
++#include "dev.h"
++#define NETLINK_SMARTLINK (31)
++#define MAX_PAYLOAD (2048)
++static struct sock *nl_sk = NULL;
++struct ssv_softc *ssv_smartlink_sc = NULL;
++EXPORT_SYMBOL(ssv_smartlink_sc);
++u32 ssv_smartlink_status = 0;
++static int _ksmartlink_start_smartlink(u8 * pInBuf, u32 inBufLen, u8 * pOutBuf,
++				       u32 * pOutBufLen)
++{
++#ifdef KSMARTLINK_DEBUG
++	printk(KERN_INFO "%s\n", __FUNCTION__);
++#endif
++	ssv_smartlink_status = 1;
++	*pOutBufLen = 0;
++	return 0;
++}
++
++int ksmartlink_smartlink_started(void)
++{
++	return ssv_smartlink_status;
++}
++
++EXPORT_SYMBOL(ksmartlink_smartlink_started);
++static int _ksmartlink_stop_smartlink(u8 * pInBuf, u32 inBufLen, u8 * pOutBuf,
++				      u32 * pOutBufLen)
++{
++#ifdef KSMARTLINK_DEBUG
++	printk(KERN_INFO "%s\n", __FUNCTION__);
++#endif
++	ssv_smartlink_status = 0;
++	*pOutBufLen = 0;
++	return 0;
++}
++
++static int _ksmartlink_set_channel(u8 * pInBuf, u32 inBufLen, u8 * pOutBuf,
++				   u32 * pOutBufLen)
++{
++	int ret = -10;
++	int ch = (int)(*pInBuf);
++	struct ssv_softc *sc = ssv_smartlink_sc;
++#ifdef KSMARTLINK_DEBUG
++	printk(KERN_INFO "%s %d\n", __FUNCTION__, ch);
++#endif
++	if (!sc) {
++		goto out;
++	}
++	mutex_lock(&sc->mutex);
++	ret = ssv6xxx_set_channel(sc, ch);
++	mutex_unlock(&sc->mutex);
++	*pOutBufLen = 0;
++ out:
++	return ret;
++}
++
++static int _ksmartlink_get_channel(u8 * pInBuf, u32 inBufLen, u8 * pOutBuf,
++				   u32 * pOutBufLen)
++{
++	int ret = -10;
++	int ch = 0;
++	struct ssv_softc *sc = ssv_smartlink_sc;
++#ifdef KSMARTLINK_DEBUG
++	printk(KERN_INFO "%s\n", __FUNCTION__);
++#endif
++	if (!sc) {
++		goto out;
++	}
++	mutex_lock(&sc->mutex);
++	ret = ssv6xxx_get_channel(sc, &ch);
++	mutex_unlock(&sc->mutex);
++	*pOutBuf = ch;
++	*pOutBufLen = 1;
++#ifdef KSMARTLINK_DEBUG
++	printk(KERN_INFO "%s %d\n", __FUNCTION__, ch);
++#endif
++ out:
++	return ret;
++}
++
++static int _ksmartlink_set_promisc(u8 * pInBuf, u32 inBufLen, u8 * pOutBuf,
++				   u32 * pOutBufLen)
++{
++	int ret = -10;
++	int accept = (int)(*pInBuf);
++	struct ssv_softc *sc = ssv_smartlink_sc;
++#ifdef KSMARTLINK_DEBUG
++	printk(KERN_INFO "%s %d\n", __FUNCTION__, accept);
++#endif
++	if (!sc) {
++		goto out;
++	}
++	mutex_lock(&sc->mutex);
++	ret = ssv6xxx_set_promisc(sc, accept);
++	mutex_unlock(&sc->mutex);
++	*pOutBufLen = 0;
++ out:
++	return ret;
++}
++
++static int _ksmartlink_get_promisc(u8 * pInBuf, u32 inBufLen, u8 * pOutBuf,
++				   u32 * pOutBufLen)
++{
++	int ret = -10;
++	int accept = (int)(*pInBuf);
++	struct ssv_softc *sc = ssv_smartlink_sc;
++#ifdef KSMARTLINK_DEBUG
++	printk(KERN_INFO "%s\n", __FUNCTION__);
++#endif
++	if (!sc) {
++		goto out;
++	}
++	mutex_lock(&sc->mutex);
++	ret = ssv6xxx_get_promisc(sc, &accept);
++	mutex_unlock(&sc->mutex);
++	*pOutBuf = accept;
++	*pOutBufLen = 1;
++#ifdef KSMARTLINK_DEBUG
++	printk(KERN_INFO "%s %d\n", __FUNCTION__, accept);
++#endif
++ out:
++	return ret;
++}
++
++#define SMARTLINK_CMD_FIXED_LEN (10)
++#define SMARTLINK_CMD_FIXED_TOT_LEN (SMARTLINK_CMD_FIXED_LEN+1)
++#define SMARTLINK_RES_FIXED_LEN (SMARTLINK_CMD_FIXED_LEN)
++#define SMARTLINK_RES_FIXED_TOT_LEN (SMARTLINK_RES_FIXED_LEN+2)
++struct ksmartlink_cmd {
++	char *cmd;
++	int (*process_func)(u8 *, u32, u8 *, u32 *);
++};
++static struct ksmartlink_cmd _ksmartlink_cmd_table[] = {
++	{"startairki", _ksmartlink_start_smartlink},
++	{"stopairkis", _ksmartlink_stop_smartlink},
++	{"setchannel", _ksmartlink_set_channel},
++	{"getchannel", _ksmartlink_get_channel},
++	{"setpromisc", _ksmartlink_set_promisc},
++	{"getpromisc", _ksmartlink_get_promisc},
++};
++
++static u32 _ksmartlink_cmd_table_size =
++    sizeof(_ksmartlink_cmd_table) / sizeof(struct ksmartlink_cmd);
++#ifdef KSMARTLINK_DEBUG
++static void _ksmartlink_hex_dump(u8 * pInBuf, u32 inBufLen)
++{
++	u32 i = 0;
++	printk(KERN_INFO "\nKernel Hex Dump(len=%d):\n", inBufLen);
++	printk(KERN_INFO ">>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
++	for (i = 0; i < inBufLen; i++) {
++		if ((i) && ((i & 0xf) == 0)) {
++			printk("\n");
++		}
++		printk("%02x ", pInBuf[i]);
++	}
++	printk(KERN_INFO "<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n");
++}
++#endif
++static int _ksmartlink_process_msg(u8 * pInBuf, u32 inBufLen, u8 * pOutBuf,
++				   u32 * pOutBufLen)
++{
++	int ret = 0;
++	u32 i = 0;
++	struct ksmartlink_cmd *pCmd;
++	if (!pInBuf || !pOutBuf || !pOutBufLen) {
++		printk(KERN_ERR "NULL pointer\n");
++		return -1;
++	}
++	for (i = 0; i < _ksmartlink_cmd_table_size; i++) {
++		if (!strncmp
++		    (_ksmartlink_cmd_table[i].cmd, pInBuf,
++		     SMARTLINK_CMD_FIXED_LEN)) {
++			break;
++		}
++	}
++	if (i < _ksmartlink_cmd_table_size) {
++		pCmd = &_ksmartlink_cmd_table[i];
++		if (!pCmd->process_func) {
++			printk(KERN_ERR "CMD %s has NULL process_func\n",
++			       pCmd->cmd);
++			return -3;
++		}
++		ret =
++		    pCmd->process_func(pInBuf + SMARTLINK_CMD_FIXED_LEN,
++				       inBufLen, pOutBuf, pOutBufLen);
++#ifdef CONFIG_SSV_NETLINK_RESPONSE
++		if (ret < 0) {
++			*pOutBufLen = SMARTLINK_RES_FIXED_TOT_LEN;
++		} else {
++			if (*pOutBufLen > 0) {
++				pOutBuf[SMARTLINK_RES_FIXED_LEN] = (u8) ret;
++				pOutBuf[SMARTLINK_RES_FIXED_LEN + 1] = *pOutBuf;
++			} else {
++				pOutBuf[SMARTLINK_RES_FIXED_LEN] = (u8) ret;
++				pOutBuf[SMARTLINK_RES_FIXED_LEN + 1] = 0;
++			}
++			*pOutBufLen = SMARTLINK_RES_FIXED_TOT_LEN;
++		}
++		memcpy(pOutBuf, pCmd->cmd, SMARTLINK_RES_FIXED_LEN);
++#else
++		(void)pOutBuf;
++		(void)pOutBufLen;
++#endif
++		return 0;
++	} else {
++		printk(KERN_INFO "Unknow CMD or Packet?\n");
++	}
++	return 0;
++}
++static u8 gkBuf[MAX_PAYLOAD] = { 0 };
++
++static int ssv_usr_pid = 0;
++void smartlink_nl_recv_msg(struct sk_buff *skb)
++{
++	struct nlmsghdr *nlh;
++#ifdef CONFIG_SSV_NETLINK_RESPONSE
++	struct sk_buff *skb_out;
++#endif
++	int ret = 0;
++	u8 *pInBuf = NULL;
++	u32 inBufLen = 0;
++	u32 outBufLen = 0;
++	nlh = (struct nlmsghdr *)skb->data;
++	ssv_usr_pid = nlh->nlmsg_pid;
++	pInBuf = (u8 *) nlmsg_data(nlh);
++	inBufLen = nlmsg_len(nlh);
++#ifdef KSMARTLINK_DEBUG
++	_ksmartlink_hex_dump(pInBuf, inBufLen);
++#endif
++	outBufLen = 0;
++	memset(gkBuf, 0, MAX_PAYLOAD);
++	ret = _ksmartlink_process_msg(pInBuf, inBufLen, gkBuf, &outBufLen);
++#ifdef CONFIG_SSV_NETLINK_RESPONSE
++	if (outBufLen == 0) {
++		memcpy(gkBuf, "Nothing", 8);
++		outBufLen = strlen(gkBuf);
++	}
++	skb_out = nlmsg_new(outBufLen, 0);
++	if (!skb_out) {
++		printk(KERN_ERR "Failed to allocate new skb\n");
++		return;
++	}
++	nlh = nlmsg_put(skb_out, 0, 0, NLMSG_DONE, outBufLen, 0);
++	NETLINK_CB(skb_out).dst_group = 0;
++	memcpy(nlmsg_data(nlh), gkBuf, outBufLen);
++	ret = nlmsg_unicast(nl_sk, skb_out, ssv_usr_pid);
++	if (ret < 0) {
++		printk(KERN_ERR "Error while sending bak to user\n");
++	}
++#endif
++	return;
++}
++
++void smartlink_nl_send_msg(struct sk_buff *skb)
++{
++	struct nlmsghdr *nlh;
++	struct sk_buff *skb_out;
++	int ret = 0;
++	u8 *pOutBuf = skb->data;
++	u32 outBufLen = skb->len;
++#ifdef KSMARTLINK_DEBUG
++#endif
++	skb_out = nlmsg_new(outBufLen, 0);
++	if (!skb_out) {
++		printk(KERN_ERR "Allocate new skb failed!\n");
++		return;
++	}
++	nlh = nlmsg_put(skb_out, 0, 0, NLMSG_DONE, outBufLen, 0);
++	NETLINK_CB(skb_out).dst_group = 0;
++	memcpy(nlmsg_data(nlh), pOutBuf, outBufLen);
++	ret = nlmsg_unicast(nl_sk, skb_out, ssv_usr_pid);
++	if (ret < 0) {
++		printk(KERN_ERR "nlmsg_unicast failed!\n");
++	}
++	kfree_skb(skb);
++	return;
++}
++
++EXPORT_SYMBOL(smartlink_nl_send_msg);
++int ksmartlink_init(void)
++{
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3,6,0)
++	nl_sk = netlink_kernel_create(&init_net,
++				      NETLINK_SMARTLINK,
++				      0,
++				      smartlink_nl_recv_msg, NULL, THIS_MODULE);
++#else
++	struct netlink_kernel_cfg cfg = {
++		.groups = 0,
++		.input = smartlink_nl_recv_msg,
++	};
++	nl_sk = netlink_kernel_create(&init_net, NETLINK_SMARTLINK, &cfg);
++#endif
++	printk(KERN_INFO "***************SmartLink Init-S**************\n");
++	if (!nl_sk) {
++		printk(KERN_ERR "Error creating socket.\n");
++		return -10;
++	}
++	printk(KERN_INFO "***************SmartLink Init-E**************\n");
++	return 0;
++}
++
++void ksmartlink_exit(void)
++{
++	printk(KERN_INFO "%s\n", __FUNCTION__);
++	if (nl_sk) {
++		netlink_kernel_release(nl_sk);
++		nl_sk = NULL;
++	}
++}
++
++EXPORT_SYMBOL(ksmartlink_init);
++EXPORT_SYMBOL(ksmartlink_exit);
+diff --git a/drivers/net/wireless/ssv6051/smac/ssv6xxx_debugfs.c b/drivers/net/wireless/ssv6051/smac/ssv6xxx_debugfs.c
+new file mode 100644
+index 000000000000..9be5ea96e7f9
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/ssv6xxx_debugfs.c
+@@ -0,0 +1,223 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation, either version 3 of the License, or
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <linux/nl80211.h>
++#include <linux/etherdevice.h>
++#include <linux/delay.h>
++#include <linux/version.h>
++#include <linux/time.h>
++#include <net/mac80211.h>
++#include <ssv6200.h>
++#include "dev.h"
++#include "ssv6xxx_debugfs.h"
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++#define QUEUE_STATUS_BUF_SIZE (4096)
++static ssize_t queue_status_read(struct file *file,
++				 char __user * user_buf, size_t count,
++				 loff_t * ppos)
++{
++	struct ssv_softc *sc = (struct ssv_softc *)file->private_data;
++	char *status_buf = kzalloc(QUEUE_STATUS_BUF_SIZE, GFP_KERNEL);
++	ssize_t status_size;
++	ssize_t ret;
++	if (!status_buf)
++		return -ENOMEM;
++	status_size = ssv6xxx_tx_queue_status_dump(sc, status_buf,
++						   QUEUE_STATUS_BUF_SIZE);
++	ret = simple_read_from_buffer(user_buf, count, ppos, status_buf,
++				      status_size);
++	kfree(status_buf);
++	return ret;
++}
++
++static int queue_status_open(struct inode *inode, struct file *file)
++{
++	file->private_data = inode->i_private;
++	return 0;
++}
++
++static const struct file_operations queue_status_fops
++    = {.read = queue_status_read,
++	.open = queue_status_open
++};
++#endif
++int ssv6xxx_init_debugfs(struct ssv_softc *sc, const char *name)
++{
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	struct ieee80211_hw *hw = sc->hw;
++	struct dentry *phy_debugfs_dir = hw->wiphy->debugfsdir;
++	struct dentry *drv_debugfs_dir;
++	drv_debugfs_dir = debugfs_create_dir(name, phy_debugfs_dir);
++	if (!drv_debugfs_dir) {
++		dev_err(sc->dev, "Failed to create debugfs.\n");
++		return -ENOMEM;
++	}
++	sc->debugfs_dir = drv_debugfs_dir;
++	sc->sh->hci.hci_ops->hci_init_debugfs(sc->debugfs_dir);
++	debugfs_create_file("queue_status", 00444, drv_debugfs_dir,
++			    sc, &queue_status_fops);
++#endif
++	return 0;
++}
++
++void ssv6xxx_deinit_debugfs(struct ssv_softc *sc)
++{
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	if (!sc->debugfs_dir)
++		return;
++	sc->sh->hci.hci_ops->hci_deinit_debugfs();
++	debugfs_remove_recursive(sc->debugfs_dir);
++	sc->debugfs_dir = NULL;
++#endif
++}
++
++int ssv6xxx_debugfs_add_interface(struct ssv_softc *sc,
++				  struct ieee80211_vif *vif)
++{
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	struct dentry *drv_debugfs_dir = sc->debugfs_dir;
++	struct dentry *vif_debugfs_dir;
++	char vif_addr[18];
++	struct ssv_vif_priv_data *vif_priv =
++	    (struct ssv_vif_priv_data *)vif->drv_priv;
++	struct ssv_vif_info *vif_info = &sc->vif_info[vif_priv->vif_idx];
++	snprintf(vif_addr, sizeof(vif_addr), "%02X-%02X-%02X-%02X-%02X-%02X",
++		 vif->addr[0], vif->addr[1], vif->addr[2],
++		 vif->addr[3], vif->addr[4], vif->addr[5]);
++	vif_debugfs_dir = debugfs_create_dir(vif_addr, drv_debugfs_dir);
++	if (!vif_debugfs_dir) {
++		dev_err(sc->dev, "Failed to create interface debugfs for %s.\n",
++			vif_addr);
++		return -ENOMEM;
++	}
++	sc->debugfs_dir = drv_debugfs_dir;
++	vif_info->debugfs_dir = vif_debugfs_dir;
++#endif
++	return 0;
++}
++
++int ssv6xxx_debugfs_remove_interface(struct ssv_softc *sc,
++				     struct ieee80211_vif *vif)
++{
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	struct ssv_vif_priv_data *vif_priv =
++	    (struct ssv_vif_priv_data *)vif->drv_priv;
++	struct ssv_vif_info *vif_info = &sc->vif_info[vif_priv->vif_idx];
++	if ((vif_info->debugfs_dir == NULL) || (sc->debugfs_dir == NULL))
++		return 0;
++	debugfs_remove_recursive(vif_info->debugfs_dir);
++	vif_info->debugfs_dir = NULL;
++#endif
++	return 0;
++}
++
++int ssv6xxx_debugfs_remove_sta(struct ssv_softc *sc, struct ssv_sta_info *sta)
++{
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	struct ssv_vif_priv_data *vif_priv =
++	    (struct ssv_vif_priv_data *)sta->vif->drv_priv;
++	struct ssv_vif_info *vif_info = &sc->vif_info[vif_priv->vif_idx];
++	if ((sc->debugfs_dir == NULL) || (vif_info->debugfs_dir == NULL)
++	    || (sta->debugfs_dir == NULL))
++		return 0;
++	debugfs_remove_recursive(sta->debugfs_dir);
++	sta->debugfs_dir = NULL;
++#endif
++	return 0;
++}
++
++int ssv6xxx_debugfs_add_sta(struct ssv_softc *sc, struct ssv_sta_info *sta)
++{
++#ifdef CONFIG_SSV6XXX_DEBUGFS
++	struct ssv_vif_priv_data *vif_priv =
++	    (struct ssv_vif_priv_data *)sta->vif->drv_priv;
++	struct ssv_vif_info *vif_info = &sc->vif_info[vif_priv->vif_idx];
++	struct dentry *vif_debugfs_dir = vif_info->debugfs_dir;
++	struct dentry *sta_debugfs_dir;
++	char sta_addr[18];
++	if (vif_debugfs_dir == NULL)
++		return 0;
++	snprintf(sta_addr, sizeof(sta_addr), "%02X-%02X-%02X-%02X-%02X-%02X",
++		 sta->sta->addr[0], sta->sta->addr[1], sta->sta->addr[2],
++		 sta->sta->addr[3], sta->sta->addr[4], sta->sta->addr[5]);
++	sta_debugfs_dir = debugfs_create_dir(sta_addr, vif_debugfs_dir);
++	if (!sta_debugfs_dir) {
++		dev_err(sc->dev, "Failed to create interface debugfs for %s.\n",
++			sta_addr);
++		return -ENOMEM;
++	}
++	sta->debugfs_dir = sta_debugfs_dir;
++#endif
++	return 0;
++}
++
++#define DEBUGFS_ADD_FILE(name,parent,mode) do { \
++    if (!debugfs_create_file(#name, mode, parent, priv, \
++                 &ssv_dbgfs_##name##_ops)) \
++        goto err; \
++} while (0)
++#define DEBUGFS_ADD_BOOL(name,parent,ptr) do { \
++    struct dentry *__tmp; \
++    __tmp = debugfs_create_bool(#name, S_IWUSR | S_IRUSR, \
++                    parent, ptr); \
++    if (IS_ERR(__tmp) || !__tmp) \
++        goto err; \
++} while (0)
++#define DEBUGFS_ADD_X32(name,parent,ptr) do { \
++    struct dentry *__tmp; \
++    __tmp = debugfs_create_x32(#name, S_IWUSR | S_IRUSR, \
++                   parent, ptr); \
++    if (IS_ERR(__tmp) || !__tmp) \
++        goto err; \
++} while (0)
++#define DEBUGFS_ADD_U32(name,parent,ptr,mode) do { \
++    struct dentry *__tmp; \
++    __tmp = debugfs_create_u32(#name, mode, \
++                   parent, ptr); \
++    if (IS_ERR(__tmp) || !__tmp) \
++        goto err; \
++} while (0)
++#define DEBUGFS_READ_FUNC(name) \
++static ssize_t ssv_dbgfs_##name##_read(struct file *file, \
++                    char __user *user_buf, \
++                    size_t count, loff_t *ppos);
++#define DEBUGFS_WRITE_FUNC(name) \
++static ssize_t ssv_dbgfs_##name##_write(struct file *file, \
++                    const char __user *user_buf, \
++                    size_t count, loff_t *ppos);
++#define DEBUGFS_READ_FILE_OPS(name) \
++    DEBUGFS_READ_FUNC(name); \
++static const struct file_operations ssv_dbgfs_##name##_ops = { \
++    .read = ssv_dbgfs_##name##_read, \
++    .open = ssv_dbgfs_open_file_generic, \
++    .llseek = generic_file_llseek, \
++};
++#define DEBUGFS_WRITE_FILE_OPS(name) \
++    DEBUGFS_WRITE_FUNC(name); \
++static const struct file_operations ssv_dbgfs_##name##_ops = { \
++    .write = ssv_dbgfs_##name##_write, \
++    .open = ssv_dbgfs_open_file_generic, \
++    .llseek = generic_file_llseek, \
++};
++#define DEBUGFS_READ_WRITE_FILE_OPS(name) \
++    DEBUGFS_READ_FUNC(name); \
++    DEBUGFS_WRITE_FUNC(name); \
++static const struct file_operations ssv_dbgfs_##name##_ops = { \
++    .write = ssv_dbgfs_##name##_write, \
++    .read = ssv_dbgfs_##name##_read, \
++    .open = ssv_dbgfs_open_file_generic, \
++    .llseek = generic_file_llseek, \
++};
+diff --git a/drivers/net/wireless/ssv6051/smac/ssv6xxx_debugfs.h b/drivers/net/wireless/ssv6051/smac/ssv6xxx_debugfs.h
+new file mode 100644
+index 000000000000..39caceadda4a
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/ssv6xxx_debugfs.h
+@@ -0,0 +1,27 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation, either version 3 of the License, or
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef __SSV6XXX_DBGFS_H__
++#define __SSV6XXX_DBGFS_H__
++int ssv6xxx_init_debugfs(struct ssv_softc *sc, const char *name);
++void ssv6xxx_deinit_debugfs(struct ssv_softc *sc);
++int ssv6xxx_debugfs_remove_interface(struct ssv_softc *sc,
++				     struct ieee80211_vif *vif);
++int ssv6xxx_debugfs_add_interface(struct ssv_softc *sc,
++				  struct ieee80211_vif *vif);
++int ssv6xxx_debugfs_remove_sta(struct ssv_softc *sc, struct ssv_sta_info *sta);
++int ssv6xxx_debugfs_add_sta(struct ssv_softc *sc, struct ssv_sta_info *sta);
++#endif
+diff --git a/drivers/net/wireless/ssv6051/smac/ssv_cfgvendor.c b/drivers/net/wireless/ssv6051/smac/ssv_cfgvendor.c
+new file mode 100644
+index 000000000000..f0135447b1f3
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/ssv_cfgvendor.c
+@@ -0,0 +1,1384 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2012 - 2018 icomm Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++
++#include "dev.h"
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) || defined(CONFIG_SSV_VENDOR_EXT_SUPPORT)
++
++#include <linux/kernel.h>
++#include <linux/if_arp.h>
++#include <asm/uaccess.h>
++
++#include <linux/kernel.h>
++#include <linux/kthread.h>
++#include <linux/netdevice.h>
++#include <linux/sched.h>
++#include <linux/etherdevice.h>
++#include <linux/wireless.h>
++#include <linux/ieee80211.h>
++#include <linux/wait.h>
++#include <net/cfg80211.h>
++
++#include <net/rtnetlink.h>
++#include "ssv_cfgvendor.h"
++
++#define wiphy_to_softc(x) (*((struct ssv_softc**)wiphy_priv(x)))
++#define FUNC_NDEV_FMT "%s"
++#define FUNC_NDEV_ARG(ndev) __func__
++
++#define _drv_always_		1
++#define _drv_emerg_			2
++#define _drv_alert_			3
++#define _drv_crit_			4
++#define _drv_err_			5
++#define _drv_warning_		6
++#define _drv_notice_		7
++#define _drv_info_			8
++#define _drv_dump_			9
++#define _drv_debug_			10
++
++struct sk_buff *ssv_cfg80211_vendor_event_alloc(struct wiphy *wiphy, int len,
++						int event_id, gfp_t gfp)
++{
++	struct sk_buff *skb;
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 1, 0))
++	skb = cfg80211_vendor_event_alloc(wiphy, len, event_id, gfp);
++#else
++	skb = cfg80211_vendor_event_alloc(wiphy, NULL, len, event_id, gfp);
++#endif
++	return skb;
++}
++
++#define ssv_cfg80211_vendor_event(skb, gfp) \
++	cfg80211_vendor_event(skb, gfp)
++
++#define ssv_cfg80211_vendor_cmd_alloc_reply_skb(wiphy, len) \
++	cfg80211_vendor_cmd_alloc_reply_skb(wiphy, len)
++
++#define ssv_cfg80211_vendor_cmd_reply(skb) \
++	cfg80211_vendor_cmd_reply(skb)
++
++/*
++ * This API is to be used for asynchronous vendor events. This
++ * shouldn't be used in response to a vendor command from its
++ * do_it handler context (instead ssv_cfgvendor_send_cmd_reply should
++ * be used).
++ */
++int ssv_cfgvendor_send_async_event(struct wiphy *wiphy,
++				   struct net_device *dev, int event_id,
++				   const void *data, int len)
++{
++	u16 kflags;
++	struct sk_buff *skb;
++
++	kflags = in_atomic()? GFP_ATOMIC : GFP_KERNEL;
++
++	/* Alloc the SKB for vendor_event */
++	skb = ssv_cfg80211_vendor_event_alloc(wiphy, len, event_id, kflags);
++	if (!skb) {
++		dev_err(&wiphy->dev, "skb alloc failed\n");
++		return -ENOMEM;
++	}
++
++	/* Push the data to the skb */
++	nla_put_nohdr(skb, len, data);
++
++	ssv_cfg80211_vendor_event(skb, kflags);
++
++	return 0;
++}
++
++static int ssv_cfgvendor_send_cmd_reply(struct wiphy *wiphy,
++					struct net_device *dev,
++					const void *data, int len)
++{
++	struct sk_buff *skb;
++
++	/* Alloc the SKB for vendor_event */
++	skb = ssv_cfg80211_vendor_cmd_alloc_reply_skb(wiphy, len);
++	if (unlikely(!skb)) {
++		dev_err(&wiphy->dev, "skb alloc failed");
++		return -ENOMEM;
++	}
++
++	/* Push the data to the skb */
++	nla_put_nohdr(skb, len, data);
++
++	return ssv_cfg80211_vendor_cmd_reply(skb);
++}
++
++#define WIFI_FEATURE_INFRA              0x0001	/* Basic infrastructure mode        */
++#define WIFI_FEATURE_INFRA_5G           0x0002	/* Support for 5 GHz Band           */
++#define WIFI_FEATURE_HOTSPOT            0x0004	/* Support for GAS/ANQP             */
++#define WIFI_FEATURE_P2P                0x0008	/* Wifi-Direct                      */
++#define WIFI_FEATURE_SOFT_AP            0x0010	/* Soft AP                          */
++#define WIFI_FEATURE_GSCAN              0x0020	/* Google-Scan APIs                 */
++#define WIFI_FEATURE_NAN                0x0040	/* Neighbor Awareness Networking    */
++#define WIFI_FEATURE_D2D_RTT            0x0080	/* Device-to-device RTT             */
++#define WIFI_FEATURE_D2AP_RTT           0x0100	/* Device-to-AP RTT                 */
++#define WIFI_FEATURE_BATCH_SCAN         0x0200	/* Batched Scan (legacy)            */
++#define WIFI_FEATURE_PNO                0x0400	/* Preferred network offload        */
++#define WIFI_FEATURE_ADDITIONAL_STA     0x0800	/* Support for two STAs             */
++#define WIFI_FEATURE_TDLS               0x1000	/* Tunnel directed link setup       */
++#define WIFI_FEATURE_TDLS_OFFCHANNEL    0x2000	/* Support for TDLS off channel     */
++#define WIFI_FEATURE_EPR                0x4000	/* Enhanced power reporting         */
++#define WIFI_FEATURE_AP_STA             0x8000	/* Support for AP STA Concurrency   */
++
++#define MAX_FEATURE_SET_CONCURRRENT_GROUPS  3
++
++int ssv_dev_get_feature_set(struct net_device *dev)
++{
++	int feature_set = 0;
++
++	feature_set |= WIFI_FEATURE_INFRA;
++
++	feature_set |= WIFI_FEATURE_P2P;
++	feature_set |= WIFI_FEATURE_SOFT_AP;
++
++#if defined(GSCAN_SUPPORT)
++	feature_set |= WIFI_FEATURE_GSCAN;
++#endif
++
++#if defined(RTT_SUPPORT)
++	feature_set |= WIFI_FEATURE_NAN;
++	feature_set |= WIFI_FEATURE_D2D_RTT;
++	feature_set |= WIFI_FEATURE_D2AP_RTT;
++#endif
++
++	return feature_set;
++}
++
++int *ssv_dev_get_feature_set_matrix(struct net_device *dev, int *num)
++{
++	int feature_set_full, mem_needed;
++	int *ret;
++
++	*num = 0;
++	mem_needed = sizeof(int) * MAX_FEATURE_SET_CONCURRRENT_GROUPS;
++	ret =
++	    (int *)kmalloc(mem_needed, in_interrupt()? GFP_ATOMIC : GFP_KERNEL);
++
++	if (!ret) {
++		dev_err(&dev->dev, "failed to allocate %d bytes\n", mem_needed);
++		return ret;
++	}
++
++	feature_set_full = ssv_dev_get_feature_set(dev);
++
++	ret[0] = (feature_set_full & WIFI_FEATURE_INFRA) |
++	    (feature_set_full & WIFI_FEATURE_INFRA_5G) |
++	    (feature_set_full & WIFI_FEATURE_NAN) |
++	    (feature_set_full & WIFI_FEATURE_D2D_RTT) |
++	    (feature_set_full & WIFI_FEATURE_D2AP_RTT) |
++	    (feature_set_full & WIFI_FEATURE_PNO) |
++	    (feature_set_full & WIFI_FEATURE_BATCH_SCAN) |
++	    (feature_set_full & WIFI_FEATURE_GSCAN) |
++	    (feature_set_full & WIFI_FEATURE_HOTSPOT) |
++	    (feature_set_full & WIFI_FEATURE_ADDITIONAL_STA) |
++	    (feature_set_full & WIFI_FEATURE_EPR);
++
++	ret[1] = (feature_set_full & WIFI_FEATURE_INFRA) |
++	    (feature_set_full & WIFI_FEATURE_INFRA_5G) |
++	    /* Not yet verified NAN with P2P */
++	    /* (feature_set_full & WIFI_FEATURE_NAN) | */
++	    (feature_set_full & WIFI_FEATURE_P2P) |
++	    (feature_set_full & WIFI_FEATURE_D2AP_RTT) |
++	    (feature_set_full & WIFI_FEATURE_D2D_RTT) |
++	    (feature_set_full & WIFI_FEATURE_EPR);
++
++	ret[2] = (feature_set_full & WIFI_FEATURE_INFRA) |
++	    (feature_set_full & WIFI_FEATURE_INFRA_5G) |
++	    (feature_set_full & WIFI_FEATURE_NAN) |
++	    (feature_set_full & WIFI_FEATURE_D2D_RTT) |
++	    (feature_set_full & WIFI_FEATURE_D2AP_RTT) |
++	    (feature_set_full & WIFI_FEATURE_TDLS) |
++	    (feature_set_full & WIFI_FEATURE_TDLS_OFFCHANNEL) |
++	    (feature_set_full & WIFI_FEATURE_EPR);
++	*num = MAX_FEATURE_SET_CONCURRRENT_GROUPS;
++
++	return ret;
++}
++
++#define wdev_to_ndev(wdev) NULL
++
++static int ssv_cfgvendor_get_feature_set(struct wiphy *wiphy,
++					 struct wireless_dev *wdev,
++					 const void *data, int len)
++{
++	int err = 0;
++	int reply;
++
++	reply = ssv_dev_get_feature_set(wdev_to_ndev(wdev));
++
++	err =
++	    ssv_cfgvendor_send_cmd_reply(wiphy, wdev_to_ndev(wdev), &reply,
++					 sizeof(int));
++
++	if (unlikely(err))
++		dev_err(&wiphy->dev, "vendor Command reply failed, ret:%d\n", err);
++
++	return err;
++}
++
++static int ssv_cfgvendor_get_feature_set_matrix(struct wiphy *wiphy,
++						struct wireless_dev *wdev,
++						const void *data, int len)
++{
++	int err = 0;
++	struct sk_buff *skb;
++	int *reply;
++	int num, mem_needed, i;
++
++	reply = ssv_dev_get_feature_set_matrix(wdev_to_ndev(wdev), &num);
++
++	if (!reply) {
++		dev_err(&wiphy->dev, "could not get feature list matrix\n");
++		err = -EINVAL;
++		return err;
++	}
++
++	mem_needed = VENDOR_REPLY_OVERHEAD + (ATTRIBUTE_U32_LEN * num) +
++	    ATTRIBUTE_U32_LEN;
++
++	/* Alloc the SKB for vendor_event */
++	skb = ssv_cfg80211_vendor_cmd_alloc_reply_skb(wiphy, mem_needed);
++	if (unlikely(!skb)) {
++		dev_err(&wiphy->dev, "skb alloc failed\n");
++		err = -ENOMEM;
++		goto exit;
++	}
++
++	nla_put_u32(skb, ANDR_WIFI_ATTRIBUTE_NUM_FEATURE_SET, num);
++	for (i = 0; i < num; i++) {
++		nla_put_u32(skb, ANDR_WIFI_ATTRIBUTE_FEATURE_SET, reply[i]);
++	}
++
++	err = ssv_cfg80211_vendor_cmd_reply(skb);
++
++	if (unlikely(err))
++		dev_err(&wiphy->dev, "vendor Command reply failed, ret=%d\n", err);
++ exit:
++	kfree((void *)reply);
++	return err;
++}
++
++#if defined(GSCAN_SUPPORT) && 0
++int wl_cfgvendor_send_hotlist_event(struct wiphy *wiphy,
++				    struct net_device *dev, void *data, int len,
++				    wl_vendor_event_t event)
++{
++	u16 kflags;
++	const void *ptr;
++	struct sk_buff *skb;
++	int malloc_len, total, iter_cnt_to_send, cnt;
++	gscan_results_cache_t *cache = (gscan_results_cache_t *) data;
++
++	total = len / sizeof(wifi_gscan_result_t);
++	while (total > 0) {
++		malloc_len =
++		    (total * sizeof(wifi_gscan_result_t)) +
++		    VENDOR_DATA_OVERHEAD;
++		if (malloc_len > NLMSG_DEFAULT_SIZE) {
++			malloc_len = NLMSG_DEFAULT_SIZE;
++		}
++		iter_cnt_to_send =
++		    (malloc_len -
++		     VENDOR_DATA_OVERHEAD) / sizeof(wifi_gscan_result_t);
++		total = total - iter_cnt_to_send;
++
++		kflags = in_atomic()? GFP_ATOMIC : GFP_KERNEL;
++
++		/* Alloc the SKB for vendor_event */
++		skb =
++		    ssv_cfg80211_vendor_event_alloc(wiphy, malloc_len, event,
++						    kflags);
++		if (!skb) {
++			WL_ERR(("skb alloc failed"));
++			return -ENOMEM;
++		}
++
++		while (cache && iter_cnt_to_send) {
++			ptr =
++			    (const void *)&cache->results[cache->tot_consumed];
++
++			if (iter_cnt_to_send <
++			    (cache->tot_count - cache->tot_consumed))
++				cnt = iter_cnt_to_send;
++			else
++				cnt = (cache->tot_count - cache->tot_consumed);
++
++			iter_cnt_to_send -= cnt;
++			cache->tot_consumed += cnt;
++			/* Push the data to the skb */
++			nla_append(skb, cnt * sizeof(wifi_gscan_result_t), ptr);
++			if (cache->tot_consumed == cache->tot_count)
++				cache = cache->next;
++
++		}
++
++		ssv_cfg80211_vendor_event(skb, kflags);
++	}
++
++	return 0;
++}
++
++static int wl_cfgvendor_gscan_get_capabilities(struct wiphy *wiphy,
++					       struct wireless_dev *wdev,
++					       const void *data, int len)
++{
++	int err = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	dhd_pno_gscan_capabilities_t *reply = NULL;
++	uint32 reply_len = 0;
++
++	reply = dhd_dev_pno_get_gscan(bcmcfg_to_prmry_ndev(cfg),
++				      DHD_PNO_GET_CAPABILITIES, NULL,
++				      &reply_len);
++	if (!reply) {
++		WL_ERR(("Could not get capabilities\n"));
++		err = -EINVAL;
++		return err;
++	}
++
++	err = ssv_cfgvendor_send_cmd_reply(wiphy, bcmcfg_to_prmry_ndev(cfg),
++					   reply, reply_len);
++
++	if (unlikely(err))
++		WL_ERR(("Vendor Command reply failed ret:%d \n", err));
++
++	kfree(reply);
++	return err;
++}
++
++static int wl_cfgvendor_gscan_get_channel_list(struct wiphy *wiphy,
++					       struct wireless_dev *wdev,
++					       const void *data, int len)
++{
++	int err = 0, type, band;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	uint16 *reply = NULL;
++	uint32 reply_len = 0, num_channels, mem_needed;
++	struct sk_buff *skb;
++
++	type = nla_type(data);
++
++	if (type == GSCAN_ATTRIBUTE_BAND) {
++		band = nla_get_u32(data);
++	} else {
++		return -1;
++	}
++
++	reply = dhd_dev_pno_get_gscan(bcmcfg_to_prmry_ndev(cfg),
++				      DHD_PNO_GET_CHANNEL_LIST, &band,
++				      &reply_len);
++
++	if (!reply) {
++		WL_ERR(("Could not get channel list\n"));
++		err = -EINVAL;
++		return err;
++	}
++	num_channels = reply_len / sizeof(uint32);
++	mem_needed =
++	    reply_len + VENDOR_REPLY_OVERHEAD + (ATTRIBUTE_U32_LEN * 2);
++
++	/* Alloc the SKB for vendor_event */
++	skb = ssv_cfg80211_vendor_cmd_alloc_reply_skb(wiphy, mem_needed);
++	if (unlikely(!skb)) {
++		WL_ERR(("skb alloc failed"));
++		err = -ENOMEM;
++		goto exit;
++	}
++
++	nla_put_u32(skb, GSCAN_ATTRIBUTE_NUM_CHANNELS, num_channels);
++	nla_put(skb, GSCAN_ATTRIBUTE_CHANNEL_LIST, reply_len, reply);
++
++	err = ssv_cfg80211_vendor_cmd_reply(skb);
++
++	if (unlikely(err))
++		WL_ERR(("Vendor Command reply failed ret:%d \n", err));
++ exit:
++	kfree(reply);
++	return err;
++}
++
++static int wl_cfgvendor_gscan_get_batch_results(struct wiphy *wiphy,
++						struct wireless_dev *wdev,
++						const void *data, int len)
++{
++	int err = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	gscan_results_cache_t *results, *iter;
++	uint32 reply_len, complete = 0, num_results_iter;
++	int32 mem_needed;
++	wifi_gscan_result_t *ptr;
++	uint16 num_scan_ids, num_results;
++	struct sk_buff *skb;
++	struct nlattr *scan_hdr;
++
++	dhd_dev_wait_batch_results_complete(bcmcfg_to_prmry_ndev(cfg));
++	dhd_dev_pno_lock_access_batch_results(bcmcfg_to_prmry_ndev(cfg));
++	results = dhd_dev_pno_get_gscan(bcmcfg_to_prmry_ndev(cfg),
++					DHD_PNO_GET_BATCH_RESULTS, NULL,
++					&reply_len);
++
++	if (!results) {
++		WL_ERR(("No results to send %d\n", err));
++		err =
++		    ssv_cfgvendor_send_cmd_reply(wiphy,
++						 bcmcfg_to_prmry_ndev(cfg),
++						 results, 0);
++
++		if (unlikely(err))
++			WL_ERR(("Vendor Command reply failed ret:%d \n", err));
++		dhd_dev_pno_unlock_access_batch_results(bcmcfg_to_prmry_ndev
++							(cfg));
++		return err;
++	}
++	num_scan_ids = reply_len & 0xFFFF;
++	num_results = (reply_len & 0xFFFF0000) >> 16;
++	mem_needed = (num_results * sizeof(wifi_gscan_result_t)) +
++	    (num_scan_ids * GSCAN_BATCH_RESULT_HDR_LEN) +
++	    VENDOR_REPLY_OVERHEAD + SCAN_RESULTS_COMPLETE_FLAG_LEN;
++
++	if (mem_needed > (int32) NLMSG_DEFAULT_SIZE) {
++		mem_needed = (int32) NLMSG_DEFAULT_SIZE;
++		complete = 0;
++	} else {
++		complete = 1;
++	}
++
++	WL_TRACE(("complete %d mem_needed %d max_mem %d\n", complete,
++		  mem_needed, (int)NLMSG_DEFAULT_SIZE));
++	/* Alloc the SKB for vendor_event */
++	skb = ssv_cfg80211_vendor_cmd_alloc_reply_skb(wiphy, mem_needed);
++	if (unlikely(!skb)) {
++		WL_ERR(("skb alloc failed"));
++		dhd_dev_pno_unlock_access_batch_results(bcmcfg_to_prmry_ndev
++							(cfg));
++		return -ENOMEM;
++	}
++	iter = results;
++
++	nla_put_u32(skb, GSCAN_ATTRIBUTE_SCAN_RESULTS_COMPLETE, complete);
++
++	mem_needed =
++	    mem_needed - (SCAN_RESULTS_COMPLETE_FLAG_LEN +
++			  VENDOR_REPLY_OVERHEAD);
++
++	while (iter && ((mem_needed - GSCAN_BATCH_RESULT_HDR_LEN) > 0)) {
++		scan_hdr = nla_nest_start(skb, GSCAN_ATTRIBUTE_SCAN_RESULTS);
++		nla_put_u32(skb, GSCAN_ATTRIBUTE_SCAN_ID, iter->scan_id);
++		nla_put_u8(skb, GSCAN_ATTRIBUTE_SCAN_FLAGS, iter->flag);
++		num_results_iter =
++		    (mem_needed -
++		     GSCAN_BATCH_RESULT_HDR_LEN) / sizeof(wifi_gscan_result_t);
++
++		if ((iter->tot_count - iter->tot_consumed) < num_results_iter)
++			num_results_iter = iter->tot_count - iter->tot_consumed;
++
++		nla_put_u32(skb, GSCAN_ATTRIBUTE_NUM_OF_RESULTS,
++			    num_results_iter);
++		if (num_results_iter) {
++			ptr = &iter->results[iter->tot_consumed];
++			iter->tot_consumed += num_results_iter;
++			nla_put(skb, GSCAN_ATTRIBUTE_SCAN_RESULTS,
++				num_results_iter * sizeof(wifi_gscan_result_t),
++				ptr);
++		}
++		nla_nest_end(skb, scan_hdr);
++		mem_needed -= GSCAN_BATCH_RESULT_HDR_LEN +
++		    (num_results_iter * sizeof(wifi_gscan_result_t));
++		iter = iter->next;
++	}
++
++	dhd_dev_gscan_batch_cache_cleanup(bcmcfg_to_prmry_ndev(cfg));
++	dhd_dev_pno_unlock_access_batch_results(bcmcfg_to_prmry_ndev(cfg));
++
++	return ssv_cfg80211_vendor_cmd_reply(skb);
++}
++
++static int wl_cfgvendor_initiate_gscan(struct wiphy *wiphy,
++				       struct wireless_dev *wdev,
++				       const void *data, int len)
++{
++	int err = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	int type, tmp = len;
++	int run = 0xFF;
++	int flush = 0;
++	const struct nlattr *iter;
++
++	nla_for_each_attr(iter, data, len, tmp) {
++		type = nla_type(iter);
++		if (type == GSCAN_ATTRIBUTE_ENABLE_FEATURE)
++			run = nla_get_u32(iter);
++		else if (type == GSCAN_ATTRIBUTE_FLUSH_FEATURE)
++			flush = nla_get_u32(iter);
++	}
++
++	if (run != 0xFF) {
++		err =
++		    dhd_dev_pno_run_gscan(bcmcfg_to_prmry_ndev(cfg), run,
++					  flush);
++
++		if (unlikely(err))
++			WL_ERR(("Could not run gscan:%d \n", err));
++		return err;
++	} else {
++		return -1;
++	}
++
++}
++
++static int wl_cfgvendor_enable_full_scan_result(struct wiphy *wiphy,
++						struct wireless_dev *wdev,
++						const void *data, int len)
++{
++	int err = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	int type;
++	bool real_time = FALSE;
++
++	type = nla_type(data);
++
++	if (type == GSCAN_ATTRIBUTE_ENABLE_FULL_SCAN_RESULTS) {
++		real_time = nla_get_u32(data);
++
++		err =
++		    dhd_dev_pno_enable_full_scan_result(bcmcfg_to_prmry_ndev
++							(cfg), real_time);
++
++		if (unlikely(err))
++			WL_ERR(("Could not run gscan:%d \n", err));
++
++	} else {
++		err = -1;
++	}
++
++	return err;
++}
++
++static int wl_cfgvendor_set_scan_cfg(struct wiphy *wiphy,
++				     struct wireless_dev *wdev,
++				     const void *data, int len)
++{
++	int err = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	gscan_scan_params_t *scan_param;
++	int j = 0;
++	int type, tmp, tmp1, tmp2, k = 0;
++	const struct nlattr *iter, *iter1, *iter2;
++	struct dhd_pno_gscan_channel_bucket *ch_bucket;
++
++	scan_param = kzalloc(sizeof(gscan_scan_params_t), GFP_KERNEL);
++	if (!scan_param) {
++		WL_ERR(("Could not set GSCAN scan cfg, mem alloc failure\n"));
++		err = -EINVAL;
++		return err;
++
++	}
++
++	scan_param->scan_fr = PNO_SCAN_MIN_FW_SEC;
++	nla_for_each_attr(iter, data, len, tmp) {
++		type = nla_type(iter);
++
++		if (j >= GSCAN_MAX_CH_BUCKETS)
++			break;
++
++		switch (type) {
++		case GSCAN_ATTRIBUTE_BASE_PERIOD:
++			scan_param->scan_fr = nla_get_u32(iter) / 1000;
++			break;
++		case GSCAN_ATTRIBUTE_NUM_BUCKETS:
++			scan_param->nchannel_buckets = nla_get_u32(iter);
++			break;
++		case GSCAN_ATTRIBUTE_CH_BUCKET_1:
++		case GSCAN_ATTRIBUTE_CH_BUCKET_2:
++		case GSCAN_ATTRIBUTE_CH_BUCKET_3:
++		case GSCAN_ATTRIBUTE_CH_BUCKET_4:
++		case GSCAN_ATTRIBUTE_CH_BUCKET_5:
++		case GSCAN_ATTRIBUTE_CH_BUCKET_6:
++		case GSCAN_ATTRIBUTE_CH_BUCKET_7:
++			nla_for_each_nested(iter1, iter, tmp1) {
++				type = nla_type(iter1);
++				ch_bucket = scan_param->channel_bucket;
++
++				switch (type) {
++				case GSCAN_ATTRIBUTE_BUCKET_ID:
++					break;
++				case GSCAN_ATTRIBUTE_BUCKET_PERIOD:
++					ch_bucket[j].bucket_freq_multiple =
++					    nla_get_u32(iter1) / 1000;
++					break;
++				case GSCAN_ATTRIBUTE_BUCKET_NUM_CHANNELS:
++					ch_bucket[j].num_channels =
++					    nla_get_u32(iter1);
++					break;
++				case GSCAN_ATTRIBUTE_BUCKET_CHANNELS:
++					nla_for_each_nested(iter2, iter1, tmp2) {
++						if (k >=
++						    PFN_SWC_RSSI_WINDOW_MAX)
++							break;
++						ch_bucket[j].chan_list[k] =
++						    nla_get_u32(iter2);
++						k++;
++					}
++					k = 0;
++					break;
++				case GSCAN_ATTRIBUTE_BUCKETS_BAND:
++					ch_bucket[j].band = (uint16)
++					    nla_get_u32(iter1);
++					break;
++				case GSCAN_ATTRIBUTE_REPORT_EVENTS:
++					ch_bucket[j].report_flag = (uint8)
++					    nla_get_u32(iter1);
++					break;
++				}
++			}
++			j++;
++			break;
++		}
++	}
++
++	if (dhd_dev_pno_set_cfg_gscan(bcmcfg_to_prmry_ndev(cfg),
++				      DHD_PNO_SCAN_CFG_ID, scan_param, 0) < 0) {
++		WL_ERR(("Could not set GSCAN scan cfg\n"));
++		err = -EINVAL;
++	}
++
++	kfree(scan_param);
++	return err;
++
++}
++
++static int wl_cfgvendor_hotlist_cfg(struct wiphy *wiphy,
++				    struct wireless_dev *wdev, const void *data,
++				    int len)
++{
++	int err = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	gscan_hotlist_scan_params_t *hotlist_params;
++	int tmp, tmp1, tmp2, type, j = 0, dummy;
++	const struct nlattr *outer, *inner, *iter;
++	uint8 flush = 0;
++	struct bssid_t *pbssid;
++
++	hotlist_params =
++	    (gscan_hotlist_scan_params_t *) kzalloc(len, GFP_KERNEL);
++	if (!hotlist_params) {
++		WL_ERR(("Cannot Malloc mem to parse config commands size - %d bytes \n", len));
++		return -1;
++	}
++
++	hotlist_params->lost_ap_window = GSCAN_LOST_AP_WINDOW_DEFAULT;
++
++	nla_for_each_attr(iter, data, len, tmp2) {
++		type = nla_type(iter);
++		switch (type) {
++		case GSCAN_ATTRIBUTE_HOTLIST_BSSIDS:
++			pbssid = hotlist_params->bssid;
++			nla_for_each_nested(outer, iter, tmp) {
++				nla_for_each_nested(inner, outer, tmp1) {
++					type = nla_type(inner);
++
++					switch (type) {
++					case GSCAN_ATTRIBUTE_BSSID:
++						memcpy(&(pbssid[j].macaddr),
++						       nla_data(inner),
++						       ETHER_ADDR_LEN);
++						break;
++					case GSCAN_ATTRIBUTE_RSSI_LOW:
++						pbssid[j].
++						    rssi_reporting_threshold =
++						    (int8) nla_get_u8(inner);
++						break;
++					case GSCAN_ATTRIBUTE_RSSI_HIGH:
++						dummy =
++						    (int8) nla_get_u8(inner);
++						break;
++					}
++				}
++				j++;
++			}
++			hotlist_params->nbssid = j;
++			break;
++		case GSCAN_ATTRIBUTE_HOTLIST_FLUSH:
++			flush = nla_get_u8(iter);
++			break;
++		case GSCAN_ATTRIBUTE_LOST_AP_SAMPLE_SIZE:
++			hotlist_params->lost_ap_window = nla_get_u32(iter);
++			break;
++		}
++
++	}
++
++	if (dhd_dev_pno_set_cfg_gscan(bcmcfg_to_prmry_ndev(cfg),
++				      DHD_PNO_GEOFENCE_SCAN_CFG_ID,
++				      hotlist_params, flush) < 0) {
++		WL_ERR(("Could not set GSCAN HOTLIST cfg\n"));
++		err = -EINVAL;
++		goto exit;
++	}
++ exit:
++	kfree(hotlist_params);
++	return err;
++}
++
++static int wl_cfgvendor_set_batch_scan_cfg(struct wiphy *wiphy,
++					   struct wireless_dev *wdev,
++					   const void *data, int len)
++{
++	int err = 0, tmp, type;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	gscan_batch_params_t batch_param;
++	const struct nlattr *iter;
++
++	batch_param.mscan = batch_param.bestn = 0;
++	batch_param.buffer_threshold = GSCAN_BATCH_NO_THR_SET;
++
++	nla_for_each_attr(iter, data, len, tmp) {
++		type = nla_type(iter);
++
++		switch (type) {
++		case GSCAN_ATTRIBUTE_NUM_AP_PER_SCAN:
++			batch_param.bestn = nla_get_u32(iter);
++			break;
++		case GSCAN_ATTRIBUTE_NUM_SCANS_TO_CACHE:
++			batch_param.mscan = nla_get_u32(iter);
++			break;
++		case GSCAN_ATTRIBUTE_REPORT_THRESHOLD:
++			batch_param.buffer_threshold = nla_get_u32(iter);
++			break;
++		}
++	}
++
++	if (dhd_dev_pno_set_cfg_gscan(bcmcfg_to_prmry_ndev(cfg),
++				      DHD_PNO_BATCH_SCAN_CFG_ID, &batch_param,
++				      0) < 0) {
++		WL_ERR(("Could not set batch cfg\n"));
++		err = -EINVAL;
++		return err;
++	}
++
++	return err;
++}
++
++static int wl_cfgvendor_significant_change_cfg(struct wiphy *wiphy,
++					       struct wireless_dev *wdev,
++					       const void *data, int len)
++{
++	int err = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	gscan_swc_params_t *significant_params;
++	int tmp, tmp1, tmp2, type, j = 0;
++	const struct nlattr *outer, *inner, *iter;
++	uint8 flush = 0;
++	wl_pfn_significant_bssid_t *pbssid;
++
++	significant_params = (gscan_swc_params_t *) kzalloc(len, GFP_KERNEL);
++	if (!significant_params) {
++		WL_ERR(("Cannot Malloc mem to parse config commands size - %d bytes \n", len));
++		return -1;
++	}
++
++	nla_for_each_attr(iter, data, len, tmp2) {
++		type = nla_type(iter);
++
++		switch (type) {
++		case GSCAN_ATTRIBUTE_SIGNIFICANT_CHANGE_FLUSH:
++			flush = nla_get_u8(iter);
++			break;
++		case GSCAN_ATTRIBUTE_RSSI_SAMPLE_SIZE:
++			significant_params->rssi_window = nla_get_u16(iter);
++			break;
++		case GSCAN_ATTRIBUTE_LOST_AP_SAMPLE_SIZE:
++			significant_params->lost_ap_window = nla_get_u16(iter);
++			break;
++		case GSCAN_ATTRIBUTE_MIN_BREACHING:
++			significant_params->swc_threshold = nla_get_u16(iter);
++			break;
++		case GSCAN_ATTRIBUTE_SIGNIFICANT_CHANGE_BSSIDS:
++			pbssid = significant_params->bssid_elem_list;
++			nla_for_each_nested(outer, iter, tmp) {
++				nla_for_each_nested(inner, outer, tmp1) {
++					switch (nla_type(inner)) {
++					case GSCAN_ATTRIBUTE_BSSID:
++						memcpy(&(pbssid[j].macaddr),
++						       nla_data(inner),
++						       ETHER_ADDR_LEN);
++						break;
++					case GSCAN_ATTRIBUTE_RSSI_HIGH:
++						pbssid[j].rssi_high_threshold =
++						    (int8) nla_get_u8(inner);
++						break;
++					case GSCAN_ATTRIBUTE_RSSI_LOW:
++						pbssid[j].rssi_low_threshold =
++						    (int8) nla_get_u8(inner);
++						break;
++					}
++				}
++				j++;
++			}
++			break;
++		}
++	}
++	significant_params->nbssid = j;
++
++	if (dhd_dev_pno_set_cfg_gscan(bcmcfg_to_prmry_ndev(cfg),
++				      DHD_PNO_SIGNIFICANT_SCAN_CFG_ID,
++				      significant_params, flush) < 0) {
++		WL_ERR(("Could not set GSCAN significant cfg\n"));
++		err = -EINVAL;
++		goto exit;
++	}
++ exit:
++	kfree(significant_params);
++	return err;
++}
++#endif				/* GSCAN_SUPPORT */
++
++#if defined(RTT_SUPPORT) && 0
++void wl_cfgvendor_rtt_evt(void *ctx, void *rtt_data)
++{
++	struct wireless_dev *wdev = (struct wireless_dev *)ctx;
++	struct wiphy *wiphy;
++	struct sk_buff *skb;
++	uint32 tot_len = NLMSG_DEFAULT_SIZE, entry_len = 0;
++	gfp_t kflags;
++	rtt_report_t *rtt_report = NULL;
++	rtt_result_t *rtt_result = NULL;
++	struct list_head *rtt_list;
++	wiphy = wdev->wiphy;
++
++	WL_DBG(("In\n"));
++	/* Push the data to the skb */
++	if (!rtt_data) {
++		WL_ERR(("rtt_data is NULL\n"));
++		goto exit;
++	}
++	rtt_list = (struct list_head *)rtt_data;
++	kflags = in_atomic()? GFP_ATOMIC : GFP_KERNEL;
++	/* Alloc the SKB for vendor_event */
++	skb =
++	    ssv_cfg80211_vendor_event_alloc(wiphy, tot_len,
++					    GOOGLE_RTT_COMPLETE_EVENT, kflags);
++	if (!skb) {
++		WL_ERR(("skb alloc failed"));
++		goto exit;
++	}
++	/* fill in the rtt results on each entry */
++	list_for_each_entry(rtt_result, rtt_list, list) {
++		entry_len = 0;
++		if (rtt_result->TOF_type == TOF_TYPE_ONE_WAY) {
++			entry_len = sizeof(rtt_report_t);
++			rtt_report = kzalloc(entry_len, kflags);
++			if (!rtt_report) {
++				WL_ERR(("rtt_report alloc failed"));
++				goto exit;
++			}
++			rtt_report->addr = rtt_result->peer_mac;
++			rtt_report->num_measurement = 1;	/* ONE SHOT */
++			rtt_report->status = rtt_result->err_code;
++			rtt_report->type =
++			    (rtt_result->TOF_type ==
++			     TOF_TYPE_ONE_WAY) ? RTT_ONE_WAY : RTT_TWO_WAY;
++			rtt_report->peer = rtt_result->target_info->peer;
++			rtt_report->channel = rtt_result->target_info->channel;
++			rtt_report->rssi = rtt_result->avg_rssi;
++			/* tx_rate */
++			rtt_report->tx_rate = rtt_result->tx_rate;
++			/* RTT */
++			rtt_report->rtt = rtt_result->meanrtt;
++			rtt_report->rtt_sd = rtt_result->sdrtt;
++			/* convert to centi meter */
++			if (rtt_result->distance != 0xffffffff)
++				rtt_report->distance =
++				    (rtt_result->distance >> 2) * 25;
++			else	/* invalid distance */
++				rtt_report->distance = -1;
++
++			rtt_report->ts = rtt_result->ts;
++			nla_append(skb, entry_len, rtt_report);
++			kfree(rtt_report);
++		}
++	}
++	ssv_cfg80211_vendor_event(skb, kflags);
++ exit:
++	return;
++}
++
++static int wl_cfgvendor_rtt_set_config(struct wiphy *wiphy,
++				       struct wireless_dev *wdev,
++				       const void *data, int len)
++{
++	int err = 0, rem, rem1, rem2, type;
++	rtt_config_params_t rtt_param;
++	rtt_target_info_t *rtt_target = NULL;
++	const struct nlattr *iter, *iter1, *iter2;
++	int8 eabuf[ETHER_ADDR_STR_LEN];
++	int8 chanbuf[CHANSPEC_STR_LEN];
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++
++	WL_DBG(("In\n"));
++	err =
++	    dhd_dev_rtt_register_noti_callback(wdev->netdev, wdev,
++					       wl_cfgvendor_rtt_evt);
++	if (err < 0) {
++		WL_ERR(("failed to register rtt_noti_callback\n"));
++		goto exit;
++	}
++	memset(&rtt_param, 0, sizeof(rtt_param));
++	nla_for_each_attr(iter, data, len, rem) {
++		type = nla_type(iter);
++		switch (type) {
++		case RTT_ATTRIBUTE_TARGET_CNT:
++			rtt_param.rtt_target_cnt = nla_get_u8(iter);
++			if (rtt_param.rtt_target_cnt > RTT_MAX_TARGET_CNT) {
++				WL_ERR(("exceed max target count : %d\n",
++					rtt_param.rtt_target_cnt));
++				err = BCME_RANGE;
++			}
++			break;
++		case RTT_ATTRIBUTE_TARGET_INFO:
++			rtt_target = rtt_param.target_info;
++			nla_for_each_nested(iter1, iter, rem1) {
++				nla_for_each_nested(iter2, iter1, rem2) {
++					type = nla_type(iter2);
++					switch (type) {
++					case RTT_ATTRIBUTE_TARGET_MAC:
++						memcpy(&rtt_target->addr,
++						       nla_data(iter2),
++						       ETHER_ADDR_LEN);
++						break;
++					case RTT_ATTRIBUTE_TARGET_TYPE:
++						rtt_target->type =
++						    nla_get_u8(iter2);
++						break;
++					case RTT_ATTRIBUTE_TARGET_PEER:
++						rtt_target->peer =
++						    nla_get_u8(iter2);
++						break;
++					case RTT_ATTRIBUTE_TARGET_CHAN:
++						memcpy(&rtt_target->channel,
++						       nla_data(iter2),
++						       sizeof(rtt_target->
++							      channel));
++						break;
++					case RTT_ATTRIBUTE_TARGET_MODE:
++						rtt_target->continuous =
++						    nla_get_u8(iter2);
++						break;
++					case RTT_ATTRIBUTE_TARGET_INTERVAL:
++						rtt_target->interval =
++						    nla_get_u32(iter2);
++						break;
++					case RTT_ATTRIBUTE_TARGET_NUM_MEASUREMENT:
++						rtt_target->measure_cnt =
++						    nla_get_u32(iter2);
++						break;
++					case RTT_ATTRIBUTE_TARGET_NUM_PKT:
++						rtt_target->ftm_cnt =
++						    nla_get_u32(iter2);
++						break;
++					case RTT_ATTRIBUTE_TARGET_NUM_RETRY:
++						rtt_target->retry_cnt =
++						    nla_get_u32(iter2);
++					}
++				}
++				/* convert to chanspec value */
++				rtt_target->chanspec =
++				    dhd_rtt_convert_to_chspec(rtt_target->
++							      channel);
++				if (rtt_target->chanspec == 0) {
++					WL_ERR(("Channel is not valid \n"));
++					goto exit;
++				}
++				WL_INFORM(("Target addr %s, Channel : %s for RTT \n", bcm_ether_ntoa((const struct ether_addr *)&rtt_target->addr, eabuf), wf_chspec_ntoa(rtt_target->chanspec, chanbuf)));
++				rtt_target++;
++			}
++			break;
++		}
++	}
++	WL_DBG(("leave :target_cnt : %d\n", rtt_param.rtt_target_cnt));
++	if (dhd_dev_rtt_set_cfg(bcmcfg_to_prmry_ndev(cfg), &rtt_param) < 0) {
++		WL_ERR(("Could not set RTT configuration\n"));
++		err = -EINVAL;
++	}
++ exit:
++	return err;
++}
++
++static int wl_cfgvendor_rtt_cancel_config(struct wiphy *wiphy,
++					  struct wireless_dev *wdev,
++					  const void *data, int len)
++{
++	int err = 0, rem, type, target_cnt = 0;
++	const struct nlattr *iter;
++	struct ether_addr *mac_list = NULL, *mac_addr = NULL;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++
++	nla_for_each_attr(iter, data, len, rem) {
++		type = nla_type(iter);
++		switch (type) {
++		case RTT_ATTRIBUTE_TARGET_CNT:
++			target_cnt = nla_get_u8(iter);
++			mac_list =
++			    (struct ether_addr *)kzalloc(target_cnt *
++							 ETHER_ADDR_LEN,
++							 GFP_KERNEL);
++			if (mac_list == NULL) {
++				WL_ERR(("failed to allocate mem for mac list\n"));
++				goto exit;
++			}
++			mac_addr = &mac_list[0];
++			break;
++		case RTT_ATTRIBUTE_TARGET_MAC:
++			if (mac_addr)
++				memcpy(mac_addr++, nla_data(iter),
++				       ETHER_ADDR_LEN);
++			else {
++				WL_ERR(("mac_list is NULL\n"));
++				goto exit;
++			}
++			break;
++		}
++		if (dhd_dev_rtt_cancel_cfg
++		    (bcmcfg_to_prmry_ndev(cfg), mac_list, target_cnt) < 0) {
++			WL_ERR(("Could not cancel RTT configuration\n"));
++			err = -EINVAL;
++			goto exit;
++		}
++	}
++ exit:
++	if (mac_list)
++		kfree(mac_list);
++	return err;
++}
++
++static int wl_cfgvendor_rtt_get_capability(struct wiphy *wiphy,
++					   struct wireless_dev *wdev,
++					   const void *data, int len)
++{
++	int err = 0;
++	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
++	rtt_capabilities_t capability;
++
++	err = dhd_dev_rtt_capability(bcmcfg_to_prmry_ndev(cfg), &capability);
++	if (unlikely(err)) {
++		WL_ERR(("Vendor Command reply failed ret:%d \n", err));
++		goto exit;
++	}
++	err = ssv_cfgvendor_send_cmd_reply(wiphy, bcmcfg_to_prmry_ndev(cfg),
++					   &capability, sizeof(capability));
++
++	if (unlikely(err)) {
++		WL_ERR(("Vendor Command reply failed ret:%d \n", err));
++	}
++ exit:
++	return err;
++}
++
++#endif				/* RTT_SUPPORT */
++static int wl_cfgvendor_priv_string_handler(struct wiphy *wiphy,
++					    struct wireless_dev *wdev,
++					    const void *data, int len)
++{
++	int err = 0;
++	u8 resp[1] = { '\0' };
++
++	dev_dbg(&wiphy->dev, "%s\n", (char *)data);
++	err = ssv_cfgvendor_send_cmd_reply(wiphy, wdev_to_ndev(wdev), resp, 1);
++	if (unlikely(err))
++		dev_err(&wiphy->dev, "vendor Command reply failed, ret=:%d\n", err);
++
++	return err;
++}
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,3,0)
++static const struct wiphy_vendor_command ssv_vendor_cmds[] = {
++	{
++	 {
++	  .vendor_id = OUI_SSV,
++	  .subcmd = RTK_VENDOR_SCMD_PRIV_STR},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = wl_cfgvendor_priv_string_handler,
++	 .policy = VENDOR_CMD_RAW_DATA},
++#if defined(GSCAN_SUPPORT) && 0
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = GSCAN_SUBCMD_GET_CAPABILITIES},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = wl_cfgvendor_gscan_get_capabilities,
++	 .policy = VENDOR_CMD_RAW_DATA},
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = GSCAN_SUBCMD_SET_CONFIG},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = wl_cfgvendor_set_scan_cfg,
++	 .policy = VENDOR_CMD_RAW_DATA},
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = GSCAN_SUBCMD_SET_SCAN_CONFIG},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = wl_cfgvendor_set_batch_scan_cfg,
++	 .policy = VENDOR_CMD_RAW_DATA},
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = GSCAN_SUBCMD_ENABLE_GSCAN},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = wl_cfgvendor_initiate_gscan,
++	 .policy = VENDOR_CMD_RAW_DATA},
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = GSCAN_SUBCMD_ENABLE_FULL_SCAN_RESULTS},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = wl_cfgvendor_enable_full_scan_result,
++	 .policy = VENDOR_CMD_RAW_DATA},
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = GSCAN_SUBCMD_SET_HOTLIST},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = wl_cfgvendor_hotlist_cfg,
++	 .policy = VENDOR_CMD_RAW_DATA},
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = GSCAN_SUBCMD_SET_SIGNIFICANT_CHANGE_CONFIG},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = wl_cfgvendor_significant_change_cfg,
++	 .policy = VENDOR_CMD_RAW_DATA},
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = GSCAN_SUBCMD_GET_SCAN_RESULTS},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = wl_cfgvendor_gscan_get_batch_results,
++	 .policy = VENDOR_CMD_RAW_DATA},
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = GSCAN_SUBCMD_GET_CHANNEL_LIST},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = wl_cfgvendor_gscan_get_channel_list,
++	 .policy = VENDOR_CMD_RAW_DATA},
++#endif				/* GSCAN_SUPPORT */
++#if defined(RTT_SUPPORT) && 0
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = RTT_SUBCMD_SET_CONFIG},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = wl_cfgvendor_rtt_set_config,
++	 .policy = VENDOR_CMD_RAW_DATA},
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = RTT_SUBCMD_CANCEL_CONFIG},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = wl_cfgvendor_rtt_cancel_config,
++	 .policy = VENDOR_CMD_RAW_DATA},
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = RTT_SUBCMD_GETCAPABILITY},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = wl_cfgvendor_rtt_get_capability,
++	 .policy = VENDOR_CMD_RAW_DATA},
++#endif				/* RTT_SUPPORT */
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = ANDR_WIFI_SUBCMD_GET_FEATURE_SET},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = ssv_cfgvendor_get_feature_set,
++	 .policy = VENDOR_CMD_RAW_DATA},
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = ANDR_WIFI_SUBCMD_GET_FEATURE_SET_MATRIX},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = ssv_cfgvendor_get_feature_set_matrix,
++	 .policy = VENDOR_CMD_RAW_DATA}
++};
++#else
++static const struct wiphy_vendor_command ssv_vendor_cmds[] = {
++	{
++	 {
++	  .vendor_id = OUI_SSV,
++	  .subcmd = RTK_VENDOR_SCMD_PRIV_STR},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = wl_cfgvendor_priv_string_handler
++	},
++#if defined(GSCAN_SUPPORT) && 0
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = GSCAN_SUBCMD_GET_CAPABILITIES},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = wl_cfgvendor_gscan_get_capabilities
++	},
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = GSCAN_SUBCMD_SET_CONFIG},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = wl_cfgvendor_set_scan_cfg
++	},
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = GSCAN_SUBCMD_SET_SCAN_CONFIG},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = wl_cfgvendor_set_batch_scan_cfg
++	},
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = GSCAN_SUBCMD_ENABLE_GSCAN},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = wl_cfgvendor_initiate_gscan
++	},
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = GSCAN_SUBCMD_ENABLE_FULL_SCAN_RESULTS},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = wl_cfgvendor_enable_full_scan_result
++	},
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = GSCAN_SUBCMD_SET_HOTLIST},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = wl_cfgvendor_hotlist_cfg
++	},
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = GSCAN_SUBCMD_SET_SIGNIFICANT_CHANGE_CONFIG},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = wl_cfgvendor_significant_change_cfg
++	},
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = GSCAN_SUBCMD_GET_SCAN_RESULTS},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = wl_cfgvendor_gscan_get_batch_results
++	},
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = GSCAN_SUBCMD_GET_CHANNEL_LIST},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = wl_cfgvendor_gscan_get_channel_list
++	},
++#endif				/* GSCAN_SUPPORT */
++#if defined(RTT_SUPPORT) && 0
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = RTT_SUBCMD_SET_CONFIG},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = wl_cfgvendor_rtt_set_config
++	},
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = RTT_SUBCMD_CANCEL_CONFIG},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = wl_cfgvendor_rtt_cancel_config
++	},
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = RTT_SUBCMD_GETCAPABILITY},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = wl_cfgvendor_rtt_get_capability
++	},
++#endif				/* RTT_SUPPORT */
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = ANDR_WIFI_SUBCMD_GET_FEATURE_SET},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = ssv_cfgvendor_get_feature_set
++	},
++	{
++	 {
++	  .vendor_id = OUI_GOOGLE,
++	  .subcmd = ANDR_WIFI_SUBCMD_GET_FEATURE_SET_MATRIX},
++	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
++	 .doit = ssv_cfgvendor_get_feature_set_matrix
++	}
++};
++#endif
++
++static const struct nl80211_vendor_cmd_info ssv_vendor_events[] = {
++	{OUI_SSV, RTK_VENDOR_EVENT_UNSPEC},
++	{OUI_SSV, RTK_VENDOR_EVENT_PRIV_STR},
++#if defined(GSCAN_SUPPORT) && 0
++	{OUI_GOOGLE, GOOGLE_GSCAN_SIGNIFICANT_EVENT},
++	{OUI_GOOGLE, GOOGLE_GSCAN_GEOFENCE_FOUND_EVENT},
++	{OUI_GOOGLE, GOOGLE_GSCAN_BATCH_SCAN_EVENT},
++	{OUI_GOOGLE, GOOGLE_SCAN_FULL_RESULTS_EVENT},
++#endif				/* GSCAN_SUPPORT */
++#if defined(RTT_SUPPORT) && 0
++	{OUI_GOOGLE, GOOGLE_RTT_COMPLETE_EVENT},
++#endif				/* RTT_SUPPORT */
++#if defined(GSCAN_SUPPORT) && 0
++	{OUI_GOOGLE, GOOGLE_SCAN_COMPLETE_EVENT},
++	{OUI_GOOGLE, GOOGLE_GSCAN_GEOFENCE_LOST_EVENT}
++#endif				/* GSCAN_SUPPORT */
++};
++
++int ssv_cfgvendor_attach(struct wiphy *wiphy)
++{
++
++	dev_info(&wiphy->dev, "register SSV cfg80211 vendor cmd(0x%x) interface\n",
++		NL80211_CMD_VENDOR);
++
++	wiphy->vendor_commands = ssv_vendor_cmds;
++	wiphy->n_vendor_commands = ARRAY_SIZE(ssv_vendor_cmds);
++	wiphy->vendor_events = ssv_vendor_events;
++	wiphy->n_vendor_events = ARRAY_SIZE(ssv_vendor_events);
++
++	return 0;
++}
++
++int ssv_cfgvendor_detach(struct wiphy *wiphy)
++{
++	dev_info(&wiphy->dev, "unregister SSV cfg80211 vendor interface\n");
++
++	wiphy->vendor_commands = NULL;
++	wiphy->vendor_events = NULL;
++	wiphy->n_vendor_commands = 0;
++	wiphy->n_vendor_events = 0;
++
++	return 0;
++}
++#endif				/* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) || defined(SSV_VENDOR_EXT_SUPPORT) */
+diff --git a/drivers/net/wireless/ssv6051/smac/ssv_cfgvendor.h b/drivers/net/wireless/ssv6051/smac/ssv_cfgvendor.h
+new file mode 100644
+index 000000000000..6d8696fcd220
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/ssv_cfgvendor.h
+@@ -0,0 +1,247 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2014 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++
++#ifndef _RTW_CFGVENDOR_H_
++#define _RTW_CFGVENDOR_H_
++
++#define OUI_SSV		0x00E04C
++#define OUI_GOOGLE	0x001A11
++#define ATTRIBUTE_U32_LEN                  (NLA_HDRLEN  + 4)
++#define VENDOR_ID_OVERHEAD                 ATTRIBUTE_U32_LEN
++#define VENDOR_SUBCMD_OVERHEAD             ATTRIBUTE_U32_LEN
++#define VENDOR_DATA_OVERHEAD               (NLA_HDRLEN)
++
++#define SCAN_RESULTS_COMPLETE_FLAG_LEN       ATTRIBUTE_U32_LEN
++#define SCAN_INDEX_HDR_LEN                   (NLA_HDRLEN)
++#define SCAN_ID_HDR_LEN                      ATTRIBUTE_U32_LEN
++#define SCAN_FLAGS_HDR_LEN                   ATTRIBUTE_U32_LEN
++#define GSCAN_NUM_RESULTS_HDR_LEN            ATTRIBUTE_U32_LEN
++#define GSCAN_RESULTS_HDR_LEN                (NLA_HDRLEN)
++#define GSCAN_BATCH_RESULT_HDR_LEN  (SCAN_INDEX_HDR_LEN + SCAN_ID_HDR_LEN + \
++									SCAN_FLAGS_HDR_LEN + \
++							        GSCAN_NUM_RESULTS_HDR_LEN + \
++									GSCAN_RESULTS_HDR_LEN)
++
++#define VENDOR_REPLY_OVERHEAD       (VENDOR_ID_OVERHEAD + \
++									VENDOR_SUBCMD_OVERHEAD + \
++									VENDOR_DATA_OVERHEAD)
++typedef enum {
++	/* don't use 0 as a valid subcommand */
++	VENDOR_NL80211_SUBCMD_UNSPECIFIED,
++
++	/* define all vendor startup commands between 0x0 and 0x0FFF */
++	VENDOR_NL80211_SUBCMD_RANGE_START = 0x0001,
++	VENDOR_NL80211_SUBCMD_RANGE_END = 0x0FFF,
++
++	/* define all GScan related commands between 0x1000 and 0x10FF */
++	ANDROID_NL80211_SUBCMD_GSCAN_RANGE_START = 0x1000,
++	ANDROID_NL80211_SUBCMD_GSCAN_RANGE_END = 0x10FF,
++
++	/* define all NearbyDiscovery related commands between 0x1100 and 0x11FF */
++	ANDROID_NL80211_SUBCMD_NBD_RANGE_START = 0x1100,
++	ANDROID_NL80211_SUBCMD_NBD_RANGE_END = 0x11FF,
++
++	/* define all RTT related commands between 0x1100 and 0x11FF */
++	ANDROID_NL80211_SUBCMD_RTT_RANGE_START = 0x1100,
++	ANDROID_NL80211_SUBCMD_RTT_RANGE_END = 0x11FF,
++
++	ANDROID_NL80211_SUBCMD_LSTATS_RANGE_START = 0x1200,
++	ANDROID_NL80211_SUBCMD_LSTATS_RANGE_END = 0x12FF,
++
++	ANDROID_NL80211_SUBCMD_TDLS_RANGE_START = 0x1300,
++	ANDROID_NL80211_SUBCMD_TDLS_RANGE_END = 0x13FF,
++	/* This is reserved for future usage */
++
++} ANDROID_VENDOR_SUB_COMMAND;
++
++enum wl_vendor_subcmd {
++	RTK_VENDOR_SCMD_UNSPEC,
++	RTK_VENDOR_SCMD_PRIV_STR,
++	GSCAN_SUBCMD_GET_CAPABILITIES =
++	    ANDROID_NL80211_SUBCMD_GSCAN_RANGE_START,
++	GSCAN_SUBCMD_SET_CONFIG,
++	GSCAN_SUBCMD_SET_SCAN_CONFIG,
++	GSCAN_SUBCMD_ENABLE_GSCAN,
++	GSCAN_SUBCMD_GET_SCAN_RESULTS,
++	GSCAN_SUBCMD_SCAN_RESULTS,
++	GSCAN_SUBCMD_SET_HOTLIST,
++	GSCAN_SUBCMD_SET_SIGNIFICANT_CHANGE_CONFIG,
++	GSCAN_SUBCMD_ENABLE_FULL_SCAN_RESULTS,
++	GSCAN_SUBCMD_GET_CHANNEL_LIST,
++	ANDR_WIFI_SUBCMD_GET_FEATURE_SET,
++	ANDR_WIFI_SUBCMD_GET_FEATURE_SET_MATRIX,
++	RTT_SUBCMD_SET_CONFIG = ANDROID_NL80211_SUBCMD_RTT_RANGE_START,
++	RTT_SUBCMD_CANCEL_CONFIG,
++	RTT_SUBCMD_GETCAPABILITY,
++	/* Add more sub commands here */
++	VENDOR_SUBCMD_MAX
++};
++
++enum gscan_attributes {
++	GSCAN_ATTRIBUTE_NUM_BUCKETS = 10,
++	GSCAN_ATTRIBUTE_BASE_PERIOD,
++	GSCAN_ATTRIBUTE_BUCKETS_BAND,
++	GSCAN_ATTRIBUTE_BUCKET_ID,
++	GSCAN_ATTRIBUTE_BUCKET_PERIOD,
++	GSCAN_ATTRIBUTE_BUCKET_NUM_CHANNELS,
++	GSCAN_ATTRIBUTE_BUCKET_CHANNELS,
++	GSCAN_ATTRIBUTE_NUM_AP_PER_SCAN,
++	GSCAN_ATTRIBUTE_REPORT_THRESHOLD,
++	GSCAN_ATTRIBUTE_NUM_SCANS_TO_CACHE,
++	GSCAN_ATTRIBUTE_BAND = GSCAN_ATTRIBUTE_BUCKETS_BAND,
++
++	GSCAN_ATTRIBUTE_ENABLE_FEATURE = 20,
++	GSCAN_ATTRIBUTE_SCAN_RESULTS_COMPLETE,
++	GSCAN_ATTRIBUTE_FLUSH_FEATURE,
++	GSCAN_ATTRIBUTE_ENABLE_FULL_SCAN_RESULTS,
++	GSCAN_ATTRIBUTE_REPORT_EVENTS,
++	/* remaining reserved for additional attributes */
++	GSCAN_ATTRIBUTE_NUM_OF_RESULTS = 30,
++	GSCAN_ATTRIBUTE_FLUSH_RESULTS,
++	GSCAN_ATTRIBUTE_SCAN_RESULTS,	/* flat array of wifi_scan_result */
++	GSCAN_ATTRIBUTE_SCAN_ID,	/* indicates scan number */
++	GSCAN_ATTRIBUTE_SCAN_FLAGS,	/* indicates if scan was aborted */
++	GSCAN_ATTRIBUTE_AP_FLAGS,	/* flags on significant change event */
++	GSCAN_ATTRIBUTE_NUM_CHANNELS,
++	GSCAN_ATTRIBUTE_CHANNEL_LIST,
++
++	/* remaining reserved for additional attributes */
++
++	GSCAN_ATTRIBUTE_SSID = 40,
++	GSCAN_ATTRIBUTE_BSSID,
++	GSCAN_ATTRIBUTE_CHANNEL,
++	GSCAN_ATTRIBUTE_RSSI,
++	GSCAN_ATTRIBUTE_TIMESTAMP,
++	GSCAN_ATTRIBUTE_RTT,
++	GSCAN_ATTRIBUTE_RTTSD,
++
++	/* remaining reserved for additional attributes */
++
++	GSCAN_ATTRIBUTE_HOTLIST_BSSIDS = 50,
++	GSCAN_ATTRIBUTE_RSSI_LOW,
++	GSCAN_ATTRIBUTE_RSSI_HIGH,
++	GSCAN_ATTRIBUTE_HOSTLIST_BSSID_ELEM,
++	GSCAN_ATTRIBUTE_HOTLIST_FLUSH,
++
++	/* remaining reserved for additional attributes */
++	GSCAN_ATTRIBUTE_RSSI_SAMPLE_SIZE = 60,
++	GSCAN_ATTRIBUTE_LOST_AP_SAMPLE_SIZE,
++	GSCAN_ATTRIBUTE_MIN_BREACHING,
++	GSCAN_ATTRIBUTE_SIGNIFICANT_CHANGE_BSSIDS,
++	GSCAN_ATTRIBUTE_SIGNIFICANT_CHANGE_FLUSH,
++	GSCAN_ATTRIBUTE_MAX
++};
++
++enum gscan_bucket_attributes {
++	GSCAN_ATTRIBUTE_CH_BUCKET_1,
++	GSCAN_ATTRIBUTE_CH_BUCKET_2,
++	GSCAN_ATTRIBUTE_CH_BUCKET_3,
++	GSCAN_ATTRIBUTE_CH_BUCKET_4,
++	GSCAN_ATTRIBUTE_CH_BUCKET_5,
++	GSCAN_ATTRIBUTE_CH_BUCKET_6,
++	GSCAN_ATTRIBUTE_CH_BUCKET_7
++};
++
++enum gscan_ch_attributes {
++	GSCAN_ATTRIBUTE_CH_ID_1,
++	GSCAN_ATTRIBUTE_CH_ID_2,
++	GSCAN_ATTRIBUTE_CH_ID_3,
++	GSCAN_ATTRIBUTE_CH_ID_4,
++	GSCAN_ATTRIBUTE_CH_ID_5,
++	GSCAN_ATTRIBUTE_CH_ID_6,
++	GSCAN_ATTRIBUTE_CH_ID_7
++};
++
++enum rtt_attributes {
++	RTT_ATTRIBUTE_TARGET_CNT,
++	RTT_ATTRIBUTE_TARGET_INFO,
++	RTT_ATTRIBUTE_TARGET_MAC,
++	RTT_ATTRIBUTE_TARGET_TYPE,
++	RTT_ATTRIBUTE_TARGET_PEER,
++	RTT_ATTRIBUTE_TARGET_CHAN,
++	RTT_ATTRIBUTE_TARGET_MODE,
++	RTT_ATTRIBUTE_TARGET_INTERVAL,
++	RTT_ATTRIBUTE_TARGET_NUM_MEASUREMENT,
++	RTT_ATTRIBUTE_TARGET_NUM_PKT,
++	RTT_ATTRIBUTE_TARGET_NUM_RETRY
++};
++
++typedef enum wl_vendor_event {
++	RTK_VENDOR_EVENT_UNSPEC,
++	RTK_VENDOR_EVENT_PRIV_STR,
++	GOOGLE_GSCAN_SIGNIFICANT_EVENT,
++	GOOGLE_GSCAN_GEOFENCE_FOUND_EVENT,
++	GOOGLE_GSCAN_BATCH_SCAN_EVENT,
++	GOOGLE_SCAN_FULL_RESULTS_EVENT,
++	GOOGLE_RTT_COMPLETE_EVENT,
++	GOOGLE_SCAN_COMPLETE_EVENT,
++	GOOGLE_GSCAN_GEOFENCE_LOST_EVENT
++} wl_vendor_event_t;
++
++enum andr_wifi_feature_set_attr {
++	ANDR_WIFI_ATTRIBUTE_NUM_FEATURE_SET,
++	ANDR_WIFI_ATTRIBUTE_FEATURE_SET
++};
++
++typedef enum wl_vendor_gscan_attribute {
++	ATTR_START_GSCAN,
++	ATTR_STOP_GSCAN,
++	ATTR_SET_SCAN_BATCH_CFG_ID,	/* set batch scan params */
++	ATTR_SET_SCAN_GEOFENCE_CFG_ID,	/* set list of bssids to track */
++	ATTR_SET_SCAN_SIGNIFICANT_CFG_ID,	/* set list of bssids, rssi threshold etc.. */
++	ATTR_SET_SCAN_CFG_ID,	/* set common scan config params here */
++	ATTR_GET_GSCAN_CAPABILITIES_ID,
++	/* Add more sub commands here */
++	ATTR_GSCAN_MAX
++} wl_vendor_gscan_attribute_t;
++
++typedef enum gscan_batch_attribute {
++	ATTR_GSCAN_BATCH_BESTN,
++	ATTR_GSCAN_BATCH_MSCAN,
++	ATTR_GSCAN_BATCH_BUFFER_THRESHOLD
++} gscan_batch_attribute_t;
++
++typedef enum gscan_geofence_attribute {
++	ATTR_GSCAN_NUM_HOTLIST_BSSID,
++	ATTR_GSCAN_HOTLIST_BSSID
++} gscan_geofence_attribute_t;
++
++typedef enum gscan_complete_event {
++	WIFI_SCAN_BUFFER_FULL,
++	WIFI_SCAN_COMPLETE
++} gscan_complete_event_t;
++
++/* Capture the RTK_VENDOR_SUBCMD_PRIV_STRINGS* here */
++#define RTK_VENDOR_SCMD_CAPA	"cap"
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) || defined(SSV_VENDOR_EXT_SUPPORT)
++extern int ssv_cfgvendor_attach(struct wiphy *wiphy);
++extern int ssv_cfgvendor_detach(struct wiphy *wiphy);
++extern int ssv_cfgvendor_send_async_event(struct wiphy *wiphy,
++					  struct net_device *dev, int event_id,
++					  const void *data, int len);
++#if defined(GSCAN_SUPPORT) && 0
++extern int wl_cfgvendor_send_hotlist_event(struct wiphy *wiphy,
++					   struct net_device *dev, void *data,
++					   int len, wl_vendor_event_t event);
++#endif
++#endif				/* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) || defined(RTW_VENDOR_EXT_SUPPORT) */
++
++#endif				/* _RTW_CFGVENDOR_H_ */
+diff --git a/drivers/net/wireless/ssv6051/smac/ssv_ht_rc.c b/drivers/net/wireless/ssv6051/smac/ssv_ht_rc.c
+new file mode 100644
+index 000000000000..fae819c43400
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/ssv_ht_rc.c
+@@ -0,0 +1,546 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation, either version 3 of the License, or
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <linux/version.h>
++#include <ssv6200.h>
++#include "dev.h"
++#include "ssv_ht_rc.h"
++#include "ssv_rc.h"
++#define SAMPLE_COUNT 4
++#define HT_CW_MIN 15
++#define HT_SEGMENT_SIZE 6000
++#define AVG_PKT_SIZE 12000
++#define SAMPLE_COLUMNS 10
++#define EWMA_LEVEL 75
++#define MCS_NBITS (AVG_PKT_SIZE << 3)
++#define MCS_NSYMS(bps) ((MCS_NBITS + (bps) - 1) / (bps))
++#define MCS_SYMBOL_TIME(sgi,syms) \
++    (sgi ? \
++      ((syms) * 18 + 4) / 5 : \
++      (syms) << 2 \
++    )
++#define MCS_DURATION(streams,sgi,bps) MCS_SYMBOL_TIME(sgi, MCS_NSYMS((streams) * (bps)))
++#define MCS_GROUP(_streams,_sgi,_ht40) { \
++    .duration = { \
++        MCS_DURATION(_streams, _sgi, _ht40 ? 54 : 26), \
++        MCS_DURATION(_streams, _sgi, _ht40 ? 108 : 52), \
++        MCS_DURATION(_streams, _sgi, _ht40 ? 162 : 78), \
++        MCS_DURATION(_streams, _sgi, _ht40 ? 216 : 104), \
++        MCS_DURATION(_streams, _sgi, _ht40 ? 324 : 156), \
++        MCS_DURATION(_streams, _sgi, _ht40 ? 432 : 208), \
++        MCS_DURATION(_streams, _sgi, _ht40 ? 486 : 234), \
++        MCS_DURATION(_streams, _sgi, _ht40 ? 540 : 260) \
++    } \
++}
++const struct mcs_group minstrel_mcs_groups_ssv[] = {
++	MCS_GROUP(1, 0, 0),
++	MCS_GROUP(1, 1, 0),
++};
++
++const u16 ampdu_max_transmit_length[RATE_TABLE_SIZE] = {
++	0, 0, 0, 0, 0, 0, 0,
++	0, 0, 0, 0, 0, 0, 0, 0,
++	4600, 9200, 13800, 18500, 27700, 37000, 41600, 46200,
++	5100, 10200, 15400, 20500, 30800, 41100, 46200, 51300,
++	4600, 9200, 13800, 18500, 27700, 37000, 41600, 46200
++};
++
++static u8 sample_table[SAMPLE_COLUMNS][MCS_GROUP_RATES];
++static int minstrel_ewma(int old, int new, int weight)
++{
++	return (new * (100 - weight) + old * weight) / 100;
++}
++
++static inline struct minstrel_rate_stats *minstrel_get_ratestats(struct
++								 ssv62xx_ht *mi,
++								 int index)
++{
++	return &mi->groups.rates[index % MCS_GROUP_RATES];
++}
++
++static void minstrel_calc_rate_ewma(struct minstrel_rate_stats *mr)
++{
++	if (unlikely(mr->attempts > 0)) {
++		mr->sample_skipped = 0;
++		mr->cur_prob = MINSTREL_FRAC(mr->success, mr->attempts);
++		if (!mr->att_hist)
++			mr->probability = mr->cur_prob;
++		else
++			mr->probability = minstrel_ewma(mr->probability,
++							mr->cur_prob,
++							EWMA_LEVEL);
++		mr->att_hist += mr->attempts;
++		mr->succ_hist += mr->success;
++	} else {
++		mr->sample_skipped++;
++	}
++	mr->last_success = mr->success;
++	mr->last_attempts = mr->attempts;
++	mr->success = 0;
++	mr->attempts = 0;
++}
++
++static void minstrel_ht_calc_tp(struct ssv62xx_ht *mi,
++				struct ssv_sta_rc_info *rc_sta, int rate)
++{
++	struct minstrel_rate_stats *mr;
++	unsigned int usecs, group_id;
++	if (rc_sta->ht_rc_type == RC_TYPE_HT_LGI_20)
++		group_id = 0;
++	else
++		group_id = 1;
++	mr = &mi->groups.rates[rate];
++	if (mr->probability < MINSTREL_FRAC(1, 10)) {
++		mr->cur_tp = 0;
++		return;
++	}
++	usecs = mi->overhead / MINSTREL_TRUNC(mi->avg_ampdu_len);
++	usecs += minstrel_mcs_groups_ssv[group_id].duration[rate];
++	mr->cur_tp = MINSTREL_TRUNC((1000000 / usecs) * mr->probability);
++}
++
++static void rate_control_ht_sample(struct ssv62xx_ht *mi,
++				   struct ssv_sta_rc_info *rc_sta)
++{
++	struct minstrel_mcs_group_data *mg;
++	struct minstrel_rate_stats *mr;
++	int cur_prob, cur_prob_tp, cur_tp, cur_tp2;
++	int i, index;
++	if (mi->ampdu_packets > 0) {
++		mi->avg_ampdu_len = minstrel_ewma(mi->avg_ampdu_len,
++						  MINSTREL_FRAC(mi->ampdu_len,
++								mi->
++								ampdu_packets),
++						  EWMA_LEVEL);
++		mi->ampdu_len = 0;
++		mi->ampdu_packets = 0;
++	} else
++		return;
++	mi->sample_slow = 0;
++	mi->sample_count = 0;
++	{
++		cur_prob = 0;
++		cur_prob_tp = 0;
++		cur_tp = 0;
++		cur_tp2 = 0;
++		mg = &mi->groups;
++		mg->max_tp_rate = 0;
++		mg->max_tp_rate2 = 0;
++		mg->max_prob_rate = 0;
++		for (i = 0; i < MCS_GROUP_RATES; i++) {
++			if (!(rc_sta->ht_supp_rates & BIT(i)))
++				continue;
++			mr = &mg->rates[i];
++			index = i;
++			minstrel_calc_rate_ewma(mr);
++			minstrel_ht_calc_tp(mi, rc_sta, i);
++#ifdef RATE_CONTROL_HT_PARAMETER_DEBUG
++			if (mr->cur_prob)
++				pr_debug
++				    ("rate[%d]probability[%08d]cur_prob[%08d]TP[%04d]\n",
++				     i, mr->probability, mr->cur_prob,
++				     mr->cur_tp);
++#endif
++#ifdef RATE_CONTROL_HT_STUPID_DEBUG
++			pr_debug
++			    ("HT sample result max_tp_rate[%d]max_tp_rate2[%d]max_prob_rate[%d]\n",
++			     mg->max_tp_rate, mg->max_tp_rate2,
++			     mg->max_prob_rate);
++			pr_debug("rate[%d]probability[%08d]TP[%d]\n", i,
++			       mr->probability, mr->cur_tp);
++#endif
++			if (!mr->cur_tp)
++				continue;
++#ifdef RATE_CONTROL_HT_STUPID_DEBUG
++			pr_debug("HT--1 mr->cur_tp[%d]cur_prob_tp[%d]\n",
++			       mr->cur_tp, cur_prob_tp);
++#endif
++			if ((mr->cur_tp > cur_prob_tp && mr->probability >
++			     MINSTREL_FRAC(3, 4))
++			    || mr->probability > cur_prob) {
++				mg->max_prob_rate = index;
++				cur_prob = mr->probability;
++				cur_prob_tp = mr->cur_tp;
++			}
++#ifdef RATE_CONTROL_HT_STUPID_DEBUG
++			pr_debug("HT--2 mr->cur_tp[%d]cur_tp[%d]\n", mr->cur_tp,
++			       cur_tp);
++#endif
++			if (mr->cur_tp > cur_tp) {
++				swap(index, mg->max_tp_rate);
++				cur_tp = mr->cur_tp;
++				mr = minstrel_get_ratestats(mi, index);
++			}
++#ifdef RATE_CONTROL_HT_STUPID_DEBUG
++			if (index != i)
++				pr_debug
++				    ("HT--3 index[%d]i[%d]mg->max_tp_rate[%d]\n",
++				     index, i, mg->max_tp_rate);
++#endif
++			if (index >= mg->max_tp_rate)
++				continue;
++#ifdef RATE_CONTROL_HT_STUPID_DEBUG
++			if (index != i)
++				pr_debug("HT--4 mr->cur_tp[%d]cur_tp2[%d]\n",
++				       mr->cur_tp, cur_tp2);
++#endif
++			if (mr->cur_tp > cur_tp2) {
++				mg->max_tp_rate2 = index;
++				cur_tp2 = mr->cur_tp;
++			}
++		}
++	}
++	mi->sample_count = SAMPLE_COUNT;
++	mi->max_tp_rate = mg->max_tp_rate;
++	mi->max_tp_rate2 = mg->max_tp_rate2;
++	mi->max_prob_rate = mg->max_prob_rate;
++#ifdef RATE_CONTROL_HT_STUPID_DEBUG
++	pr_debug
++	    ("HT sample result max_tp_rate[%d]max_tp_rate2[%d]max_prob_rate[%d]\n",
++	     mi->max_tp_rate, mi->max_tp_rate2, mi->max_prob_rate);
++#endif
++	mi->stats_update = jiffies;
++}
++
++static void minstrel_ht_set_rate(struct ssv62xx_ht *mi,
++				 struct fw_rc_retry_params *rate, int index,
++				 bool sample, bool rtscts,
++				 struct ssv_sta_rc_info *rc_sta,
++				 struct ssv_rate_ctrl *ssv_rc)
++{
++	struct minstrel_rate_stats *mr;
++	mr = minstrel_get_ratestats(mi, index);
++	rate->drate = ssv_rc->rc_table[mr->rc_index].hw_rate_idx;
++	rate->crate = ssv_rc->rc_table[mr->rc_index].ctrl_rate_idx;
++}
++
++static inline int minstrel_get_duration(int index,
++					struct ssv_sta_rc_info *rc_sta)
++{
++	unsigned int group_id;
++	const struct mcs_group *group;
++	if (rc_sta->ht_rc_type == RC_TYPE_HT_LGI_20)
++		group_id = 0;
++	else
++		group_id = 1;
++	group = &minstrel_mcs_groups_ssv[group_id];
++	return group->duration[index % MCS_GROUP_RATES];
++}
++
++static void minstrel_next_sample_idx(struct ssv62xx_ht *mi)
++{
++	struct minstrel_mcs_group_data *mg;
++	for (;;) {
++		mg = &mi->groups;
++		if (++mg->index >= MCS_GROUP_RATES) {
++			mg->index = 0;
++			if (++mg->column >= ARRAY_SIZE(sample_table))
++				mg->column = 0;
++		}
++		break;
++	}
++}
++
++static int minstrel_get_sample_rate(struct ssv62xx_ht *mi,
++				    struct ssv_sta_rc_info *rc_sta)
++{
++	struct minstrel_rate_stats *mr;
++	struct minstrel_mcs_group_data *mg;
++	int sample_idx = 0;
++	if (mi->sample_wait > 0) {
++		mi->sample_wait--;
++		return -1;
++	}
++	if (!mi->sample_tries)
++		return -1;
++	mi->sample_tries--;
++	mg = &mi->groups;
++	sample_idx = sample_table[mg->column][mg->index];
++	mr = &mg->rates[sample_idx];
++	minstrel_next_sample_idx(mi);
++	if (minstrel_get_duration(sample_idx, rc_sta) >
++	    minstrel_get_duration(mi->max_tp_rate, rc_sta)) {
++		if (mr->sample_skipped < 20) {
++			return -1;
++		}
++		if (mi->sample_slow++ > 2) {
++			return -1;
++		}
++	}
++	return sample_idx;
++}
++
++static void _fill_txinfo_rates(struct ssv_rate_ctrl *ssv_rc,
++			       struct sk_buff *skb,
++			       struct fw_rc_retry_params *ar)
++{
++	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
++	info->control.rates[0].idx =
++	    ssv_rc->rc_table[ar[0].drate].dot11_rate_idx;
++	info->control.rates[0].count = 1;
++	info->control.rates[SSV_DRATE_IDX].count = ar[0].drate;
++	info->control.rates[SSV_CRATE_IDX].count = ar[0].crate;
++}
++
++extern const u16 ssv6xxx_rc_rate_set[RC_TYPE_MAX][13];
++s32 ssv62xx_ht_rate_update(struct sk_buff *skb, struct ssv_softc *sc,
++			   struct fw_rc_retry_params *ar)
++{
++	struct ssv_rate_ctrl *ssv_rc = sc->rc;
++	struct SKB_info_st *skb_info = (struct SKB_info_st *)skb->head;
++	struct ieee80211_sta *sta = skb_info->sta;
++	struct ssv62xx_ht *mi = NULL;
++	int sample_idx;
++	bool sample = false;
++	struct ssv_sta_rc_info *rc_sta;
++	struct ssv_sta_priv_data *sta_priv;
++	struct rc_pid_sta_info *spinfo;
++	int ret = 0;
++	if (sc->sc_flags & SC_OP_FIXED_RATE) {
++		ar[0].count = 3;
++		ar[0].drate = ssv_rc->rc_table[sc->max_rate_idx].hw_rate_idx;
++		ar[0].crate = ssv_rc->rc_table[sc->max_rate_idx].ctrl_rate_idx;
++		ar[1].count = 2;
++		ar[1].drate = ssv_rc->rc_table[sc->max_rate_idx].hw_rate_idx;
++		ar[1].crate = ssv_rc->rc_table[sc->max_rate_idx].ctrl_rate_idx;
++		ar[2].count = 2;
++		ar[2].drate = ssv_rc->rc_table[sc->max_rate_idx].hw_rate_idx;
++		ar[2].crate = ssv_rc->rc_table[sc->max_rate_idx].ctrl_rate_idx;
++		_fill_txinfo_rates(ssv_rc, skb, ar);
++		return ssv_rc->rc_table[sc->max_rate_idx].hw_rate_idx;
++	}
++	if (sta == NULL) {
++		dev_err(sc->dev, "Station NULL\n");
++		BUG_ON(1);
++	}
++	sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
++	rc_sta = &ssv_rc->sta_rc_info[sta_priv->rc_idx];
++	spinfo = &rc_sta->spinfo;
++	if ((rc_sta->rc_wsid >= SSV_RC_MAX_HARDWARE_SUPPORT)
++	    || (rc_sta->rc_wsid < 0)) {
++		struct ssv_sta_priv_data *ssv_sta_priv;
++		int rateidx = 99;
++		ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
++		{
++			if ((rc_sta->ht_rc_type >= RC_TYPE_HT_SGI_20) &&
++			    (ssv_sta_priv->rx_data_rate <
++			     SSV62XX_RATE_MCS_INDEX)) {
++				if (ssv6xxx_rc_rate_set[rc_sta->ht_rc_type][0]
++				    == 12)
++					rateidx =
++					    (int)rc_sta->pinfo.rinfo[4].
++					    rc_index;
++				else
++					rateidx =
++					    (int)rc_sta->pinfo.rinfo[0].
++					    rc_index;
++			} else {
++				rateidx = (int)ssv_sta_priv->rx_data_rate;
++				rateidx -= SSV62XX_RATE_MCS_INDEX;
++				rateidx %= 8;
++				if (rc_sta->ht_rc_type == RC_TYPE_HT_SGI_20)
++					rateidx += SSV62XX_RATE_MCS_SGI_INDEX;
++				else if (rc_sta->ht_rc_type ==
++					 RC_TYPE_HT_LGI_20)
++					rateidx += SSV62XX_RATE_MCS_LGI_INDEX;
++				else
++					rateidx +=
++					    SSV62XX_RATE_MCS_GREENFIELD_INDEX;
++			}
++		}
++		ar[0].count = 3;
++		ar[2].drate = ar[1].drate = ar[0].drate =
++		    ssv_rc->rc_table[rateidx].hw_rate_idx;
++		ar[2].crate = ar[1].crate = ar[0].crate =
++		    ssv_rc->rc_table[rateidx].ctrl_rate_idx;
++		ar[1].count = 2;
++		ar[2].count = 2;
++		_fill_txinfo_rates(ssv_rc, skb, ar);
++		return rateidx;
++	}
++	mi = &rc_sta->ht;
++	sample_idx = minstrel_get_sample_rate(mi, rc_sta);
++	if (sample_idx >= 0) {
++		sample = true;
++		minstrel_ht_set_rate(mi, &ar[0], sample_idx,
++				     true, false, rc_sta, ssv_rc);
++	} else {
++		minstrel_ht_set_rate(mi, &ar[0], mi->max_tp_rate,
++				     false, false, rc_sta, ssv_rc);
++	}
++	ar[0].count = mi->first_try_count;
++	ret = ar[0].drate;
++	{
++		if (sample_idx >= 0)
++			minstrel_ht_set_rate(mi, &ar[1], mi->max_tp_rate,
++					     false, false, rc_sta, ssv_rc);
++		else
++			minstrel_ht_set_rate(mi, &ar[1], mi->max_tp_rate2,
++					     false, true, rc_sta, ssv_rc);
++		ar[1].count = mi->second_try_count;
++		if (ret > ar[1].drate)
++			ret = ar[1].drate;
++		minstrel_ht_set_rate(mi, &ar[2], mi->max_prob_rate,
++				     false, !sample, rc_sta, ssv_rc);
++		ar[2].count = mi->other_try_count;
++		if (ret > ar[2].drate)
++			ret = ar[2].drate;
++	}
++	mi->total_packets++;
++	if (mi->total_packets == ~0) {
++		mi->total_packets = 0;
++		mi->sample_packets = 0;
++	}
++	if (spinfo->real_hw_index < SSV62XX_RATE_MCS_INDEX)
++		return spinfo->real_hw_index;
++	_fill_txinfo_rates(ssv_rc, skb, ar);
++	return ret;
++}
++
++static void init_sample_table(void)
++{
++	int col, i, new_idx;
++	u8 rnd[MCS_GROUP_RATES];
++	memset(sample_table, 0xff, sizeof(sample_table));
++	for (col = 0; col < SAMPLE_COLUMNS; col++) {
++		for (i = 0; i < MCS_GROUP_RATES; i++) {
++			get_random_bytes(rnd, sizeof(rnd));
++			new_idx = (i + rnd[i]) % MCS_GROUP_RATES;
++			while (sample_table[col][new_idx] != 0xff)
++				new_idx = (new_idx + 1) % MCS_GROUP_RATES;
++			sample_table[col][new_idx] = i;
++		}
++	}
++}
++
++void ssv62xx_ht_rc_caps(const u16 ssv6xxx_rc_rate_set[RC_TYPE_MAX][13],
++			struct ssv_sta_rc_info *rc_sta)
++{
++	struct ssv62xx_ht *mi = &rc_sta->ht;
++	int ack_dur;
++	int i;
++	unsigned int group_id;
++	if (rc_sta->ht_rc_type == RC_TYPE_HT_LGI_20)
++		group_id = 0;
++	else
++		group_id = 1;
++	for (i = 0; i < MCS_GROUP_RATES; i++) {
++		pr_debug("[RC]HT duration[%d][%d]\n", i,
++		       minstrel_mcs_groups_ssv[group_id].duration[i]);
++	}
++	init_sample_table();
++	memset(mi, 0, sizeof(*mi));
++	mi->stats_update = jiffies;
++	ack_dur = pide_frame_duration(10, 60, 0, 0);
++	mi->overhead = pide_frame_duration(0, 60, 0, 0) + ack_dur;
++	mi->overhead_rtscts = mi->overhead + 2 * ack_dur;
++	mi->avg_ampdu_len = MINSTREL_FRAC(1, 1);
++	mi->sample_count = 16;
++	mi->sample_wait = 0;
++	mi->sample_tries = 4;
++#ifdef DISABLE_RATE_CONTROL_SAMPLE
++	mi->max_tp_rate = MCS_GROUP_RATES - 1;
++	mi->max_tp_rate2 = MCS_GROUP_RATES - 1;
++	mi->max_prob_rate = MCS_GROUP_RATES - 1;
++#endif
++#if (HW_MAX_RATE_TRIES == 7)
++	{
++		mi->first_try_count = 3;
++		mi->second_try_count = 2;
++		mi->other_try_count = 2;
++	}
++#else
++	{
++		mi->first_try_count = 2;
++		mi->second_try_count = 1;
++		mi->other_try_count = 1;
++	}
++#endif
++	for (i = 0; i < MCS_GROUP_RATES; i++) {
++		mi->groups.rates[i].rc_index =
++		    ssv6xxx_rc_rate_set[rc_sta->ht_rc_type][i + 1];
++	}
++}
++
++static bool minstrel_ht_txstat_valid(struct ssv62xx_tx_rate *rate)
++{
++	if (!rate->count)
++		return false;
++	if (rate->data_rate < 0)
++		return false;
++	return true;
++}
++
++void ssv6xxx_ht_report_handler(struct ssv_softc *sc, struct sk_buff *skb,
++			       struct ssv_sta_rc_info *rc_sta)
++{
++	struct cfg_host_event *host_event;
++	struct firmware_rate_control_report_data *report_data;
++	struct ssv62xx_ht *mi;
++	struct minstrel_rate_stats *rate;
++	bool last = false;
++	int i = 0;
++	u16 report_ampdu_packets = 0;
++	unsigned long period;
++	host_event = (struct cfg_host_event *)skb->data;
++	report_data =
++	    (struct firmware_rate_control_report_data *)&host_event->dat[0];
++	if (host_event->h_event == SOC_EVT_RC_AMPDU_REPORT) {
++		report_ampdu_packets = 1;
++	} else if (host_event->h_event == SOC_EVT_RC_MPDU_REPORT) {
++		report_data->ampdu_len = 1;
++		report_ampdu_packets = report_data->ampdu_len;
++	} else {
++		dev_warn(sc->dev, "rate control report handler got garbage\n");
++		return;
++	}
++	mi = &rc_sta->ht;
++	mi->ampdu_packets += report_ampdu_packets;
++	mi->ampdu_len += report_data->ampdu_len;
++	if (!mi->sample_wait && !mi->sample_tries && mi->sample_count > 0) {
++		mi->sample_wait = 16 + 2 * MINSTREL_TRUNC(mi->avg_ampdu_len);
++		mi->sample_tries = 2;
++		mi->sample_count--;
++	}
++	for (i = 0; !last; i++) {
++		last = (i == SSV62XX_TX_MAX_RATES - 1) ||
++		    !minstrel_ht_txstat_valid(&report_data->rates[i + 1]);
++		if (!minstrel_ht_txstat_valid(&report_data->rates[i]))
++			break;
++#ifdef RATE_CONTROL_DEBUG
++		if ((report_data->rates[i].data_rate < SSV62XX_RATE_MCS_INDEX)
++		    || (report_data->rates[i].data_rate >=
++			SSV62XX_RATE_MCS_GREENFIELD_INDEX)) {
++			dev_dbg
++			    (sc->dev, "[RC]ssv6xxx_ht_report_handler get error report rate[%d]\n",
++			     report_data->rates[i].data_rate);
++			break;
++		}
++#endif
++		rate =
++		    &mi->groups.
++		    rates[(report_data->rates[i].data_rate -
++			   SSV62XX_RATE_MCS_INDEX) % MCS_GROUP_RATES];
++		if (last)
++			rate->success += report_data->ampdu_ack_len;
++		rate->attempts +=
++		    report_data->rates[i].count * report_data->ampdu_len;
++	}
++	period = msecs_to_jiffies(SSV_RC_HT_INTERVAL / 2);
++	if (time_after(jiffies, mi->stats_update + period)) {
++		rate_control_ht_sample(mi, rc_sta);
++	}
++}
+diff --git a/drivers/net/wireless/ssv6051/smac/ssv_ht_rc.h b/drivers/net/wireless/ssv6051/smac/ssv_ht_rc.h
+new file mode 100644
+index 000000000000..275c3356e036
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/ssv_ht_rc.h
+@@ -0,0 +1,31 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation, either version 3 of the License, or
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _SSV_RC_HT_H_
++#define _SSV_RC_HT_H_
++#include "ssv_rc_common.h"
++#define MINSTREL_SCALE 16
++#define MINSTREL_FRAC(val,div) (((val) << MINSTREL_SCALE) / div)
++#define MINSTREL_TRUNC(val) ((val) >> MINSTREL_SCALE)
++#define SSV_RC_HT_INTERVAL 100
++extern const u16 ampdu_max_transmit_length[];
++s32 ssv62xx_ht_rate_update(struct sk_buff *skb, struct ssv_softc *sc,
++			   struct fw_rc_retry_params *ar);
++void ssv62xx_ht_rc_caps(const u16 ssv6xxx_rc_rate_set[RC_TYPE_MAX][13],
++			struct ssv_sta_rc_info *rc_sta);
++void ssv6xxx_ht_report_handler(struct ssv_softc *sc, struct sk_buff *skb,
++			       struct ssv_sta_rc_info *rc_sta);
++#endif
+diff --git a/drivers/net/wireless/ssv6051/smac/ssv_pm.c b/drivers/net/wireless/ssv6051/smac/ssv_pm.c
+new file mode 100644
+index 000000000000..fc3be2013f61
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/ssv_pm.c
+@@ -0,0 +1,19 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation, either version 3 of the License, or
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <ssv6200.h>
++#include "dev.h"
++#include "sar.h"
+diff --git a/drivers/net/wireless/ssv6051/smac/ssv_pm.h b/drivers/net/wireless/ssv6051/smac/ssv_pm.h
+new file mode 100644
+index 000000000000..9be260dd904e
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/ssv_pm.h
+@@ -0,0 +1,20 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation, either version 3 of the License, or
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _SSV_PM_H_
++#define _SSV_PM_H_
++#include <linux/version.h>
++#endif
+diff --git a/drivers/net/wireless/ssv6051/smac/ssv_rc.c b/drivers/net/wireless/ssv6051/smac/ssv_rc.c
+new file mode 100644
+index 000000000000..9c3574285364
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/ssv_rc.c
+@@ -0,0 +1,1716 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation, either version 3 of the License, or
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <linux/version.h>
++#include <ssv6200.h>
++#include "dev.h"
++#include "ssv_ht_rc.h"
++#include "ssv_rc.h"
++#include "ssv_rc_common.h"
++static struct ssv_rc_rate ssv_11bgn_rate_table[] = {
++	[0] = {.rc_flags = RC_FLAG_LEGACY,
++	       .phy_type = WLAN_RC_PHY_CCK,
++	       .rate_kbps = 1000,
++	       .dot11_rate_idx = 0,
++	       .ctrl_rate_idx = 0,
++	       .hw_rate_idx = 0,
++	       .arith_shift = 8,
++	       .target_pf = 26,
++	       },
++	[1] = {.rc_flags = RC_FLAG_LEGACY,
++	       .phy_type = WLAN_RC_PHY_CCK,
++	       .rate_kbps = 2000,
++	       .dot11_rate_idx = 1,
++	       .ctrl_rate_idx = 1,
++	       .hw_rate_idx = 1,
++	       .arith_shift = 8,
++	       .target_pf = 26,
++	       },
++	[2] = {.rc_flags = RC_FLAG_LEGACY,
++	       .phy_type = WLAN_RC_PHY_CCK,
++	       .rate_kbps = 5500,
++	       .dot11_rate_idx = 2,
++	       .ctrl_rate_idx = 1,
++	       .hw_rate_idx = 2,
++	       .arith_shift = 8,
++	       .target_pf = 26,
++	       },
++	[3] = {.rc_flags = RC_FLAG_LEGACY,
++	       .phy_type = WLAN_RC_PHY_CCK,
++	       .rate_kbps = 11000,
++	       .dot11_rate_idx = 3,
++	       .ctrl_rate_idx = 1,
++	       .hw_rate_idx = 3,
++	       .arith_shift = 8,
++	       .target_pf = 26,
++	       },
++	[4] = {.rc_flags = RC_FLAG_LEGACY | RC_FLAG_SHORT_PREAMBLE,
++	       .phy_type = WLAN_RC_PHY_CCK,
++	       .rate_kbps = 2000,
++	       .dot11_rate_idx = 1,
++	       .ctrl_rate_idx = 4,
++	       .hw_rate_idx = 4,
++	       .arith_shift = 8,
++	       .target_pf = 26,
++	       },
++	[5] = {.rc_flags = RC_FLAG_LEGACY | RC_FLAG_SHORT_PREAMBLE,
++	       .phy_type = WLAN_RC_PHY_CCK,
++	       .rate_kbps = 5500,
++	       .dot11_rate_idx = 2,
++	       .ctrl_rate_idx = 4,
++	       .hw_rate_idx = 5,
++	       .arith_shift = 8,
++	       .target_pf = 26,
++	       },
++	[6] = {.rc_flags = RC_FLAG_LEGACY | RC_FLAG_SHORT_PREAMBLE,
++	       .phy_type = WLAN_RC_PHY_CCK,
++	       .rate_kbps = 11000,
++	       .dot11_rate_idx = 3,
++	       .ctrl_rate_idx = 4,
++	       .hw_rate_idx = 6,
++	       .arith_shift = 8,
++	       .target_pf = 26,
++	       },
++	[7] = {.rc_flags = RC_FLAG_LEGACY,
++	       .phy_type = WLAN_RC_PHY_OFDM,
++	       .rate_kbps = 6000,
++	       .dot11_rate_idx = 4,
++	       .ctrl_rate_idx = 7,
++	       .hw_rate_idx = 7,
++	       .arith_shift = 8,
++	       .target_pf = 26,
++	       },
++	[8] = {.rc_flags = RC_FLAG_LEGACY,
++	       .phy_type = WLAN_RC_PHY_OFDM,
++	       .rate_kbps = 9000,
++	       .dot11_rate_idx = 5,
++	       .ctrl_rate_idx = 7,
++	       .hw_rate_idx = 8,
++	       .arith_shift = 8,
++	       .target_pf = 26,
++	       },
++	[9] = {.rc_flags = RC_FLAG_LEGACY,
++	       .phy_type = WLAN_RC_PHY_OFDM,
++	       .rate_kbps = 12000,
++	       .dot11_rate_idx = 6,
++	       .ctrl_rate_idx = 9,
++	       .hw_rate_idx = 9,
++	       .arith_shift = 8,
++	       .target_pf = 26,
++	       },
++	[10] = {.rc_flags = RC_FLAG_LEGACY,
++		.phy_type = WLAN_RC_PHY_OFDM,
++		.rate_kbps = 18000,
++		.dot11_rate_idx = 7,
++		.ctrl_rate_idx = 9,
++		.hw_rate_idx = 10,
++		.arith_shift = 8,
++		.target_pf = 26,
++		},
++	[11] = {.rc_flags = RC_FLAG_LEGACY,
++		.phy_type = WLAN_RC_PHY_OFDM,
++		.rate_kbps = 24000,
++		.dot11_rate_idx = 8,
++		.ctrl_rate_idx = 11,
++		.hw_rate_idx = 11,
++		.arith_shift = 8,
++		.target_pf = 26,
++		},
++	[12] = {.rc_flags = RC_FLAG_LEGACY,
++		.phy_type = WLAN_RC_PHY_OFDM,
++		.rate_kbps = 36000,
++		.dot11_rate_idx = 9,
++		.ctrl_rate_idx = 11,
++		.hw_rate_idx = 12,
++		.arith_shift = 8,
++		.target_pf = 26,
++		},
++	[13] = {.rc_flags = RC_FLAG_LEGACY,
++		.phy_type = WLAN_RC_PHY_OFDM,
++		.rate_kbps = 48000,
++		.dot11_rate_idx = 10,
++		.ctrl_rate_idx = 11,
++		.hw_rate_idx = 13,
++		.arith_shift = 8,
++		.target_pf = 26,
++		},
++	[14] = {.rc_flags = RC_FLAG_LEGACY,
++		.phy_type = WLAN_RC_PHY_OFDM,
++		.rate_kbps = 54000,
++		.dot11_rate_idx = 11,
++		.ctrl_rate_idx = 11,
++		.hw_rate_idx = 14,
++		.arith_shift = 8,
++		.target_pf = 8},
++	[15] = {.rc_flags = RC_FLAG_HT,
++		.phy_type = WLAN_RC_PHY_HT_20_SS_LGI,
++		.rate_kbps = 6500,
++		.dot11_rate_idx = 0,
++		.ctrl_rate_idx = 7,
++		.hw_rate_idx = 15,
++		.arith_shift = 8,
++		.target_pf = 26,
++		},
++	[16] = {.rc_flags = RC_FLAG_HT,
++		.phy_type = WLAN_RC_PHY_HT_20_SS_LGI,
++		.rate_kbps = 13000,
++		.dot11_rate_idx = 1,
++		.ctrl_rate_idx = 9,
++		.hw_rate_idx = 16,
++		.arith_shift = 8,
++		.target_pf = 26,
++		},
++	[17] = {.rc_flags = RC_FLAG_HT,
++		.phy_type = WLAN_RC_PHY_HT_20_SS_LGI,
++		.rate_kbps = 19500,
++		.dot11_rate_idx = 2,
++		.ctrl_rate_idx = 9,
++		.hw_rate_idx = 17,
++		.arith_shift = 8,
++		.target_pf = 26,
++		},
++	[18] = {.rc_flags = RC_FLAG_HT,
++		.phy_type = WLAN_RC_PHY_HT_20_SS_LGI,
++		.rate_kbps = 26000,
++		.dot11_rate_idx = 3,
++		.ctrl_rate_idx = 11,
++		.hw_rate_idx = 18,
++		.arith_shift = 8,
++		.target_pf = 26,
++		},
++	[19] = {.rc_flags = RC_FLAG_HT,
++		.phy_type = WLAN_RC_PHY_HT_20_SS_LGI,
++		.rate_kbps = 39000,
++		.dot11_rate_idx = 4,
++		.ctrl_rate_idx = 11,
++		.hw_rate_idx = 19,
++		.arith_shift = 8,
++		.target_pf = 26,
++		},
++	[20] = {.rc_flags = RC_FLAG_HT,
++		.phy_type = WLAN_RC_PHY_HT_20_SS_LGI,
++		.rate_kbps = 52000,
++		.dot11_rate_idx = 5,
++		.ctrl_rate_idx = 11,
++		.hw_rate_idx = 20,
++		.arith_shift = 8,
++		.target_pf = 26,
++		},
++	[21] = {.rc_flags = RC_FLAG_HT,
++		.phy_type = WLAN_RC_PHY_HT_20_SS_LGI,
++		.rate_kbps = 58500,
++		.dot11_rate_idx = 6,
++		.ctrl_rate_idx = 11,
++		.hw_rate_idx = 21,
++		.arith_shift = 8,
++		.target_pf = 26,
++		},
++	[22] = {.rc_flags = RC_FLAG_HT,
++		.phy_type = WLAN_RC_PHY_HT_20_SS_LGI,
++		.rate_kbps = 65000,
++		.dot11_rate_idx = 7,
++		.ctrl_rate_idx = 11,
++		.hw_rate_idx = 22,
++		.arith_shift = 8,
++		.target_pf = 8},
++	[23] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_SGI,
++		.phy_type = WLAN_RC_PHY_HT_20_SS_SGI,
++		.rate_kbps = 7200,
++		.dot11_rate_idx = 0,
++		.ctrl_rate_idx = 7,
++		.hw_rate_idx = 23,
++		.arith_shift = 8,
++		.target_pf = 26,
++		},
++	[24] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_SGI,
++		.phy_type = WLAN_RC_PHY_HT_20_SS_SGI,
++		.rate_kbps = 14400,
++		.dot11_rate_idx = 1,
++		.ctrl_rate_idx = 9,
++		.hw_rate_idx = 24,
++		.arith_shift = 8,
++		.target_pf = 26,
++		},
++	[25] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_SGI,
++		.phy_type = WLAN_RC_PHY_HT_20_SS_SGI,
++		.rate_kbps = 21700,
++		.dot11_rate_idx = 2,
++		.ctrl_rate_idx = 9,
++		.hw_rate_idx = 25,
++		.arith_shift = 8,
++		.target_pf = 26,
++		},
++	[26] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_SGI,
++		.phy_type = WLAN_RC_PHY_HT_20_SS_SGI,
++		.rate_kbps = 28900,
++		.dot11_rate_idx = 3,
++		.ctrl_rate_idx = 11,
++		.hw_rate_idx = 26,
++		.arith_shift = 8,
++		.target_pf = 26,
++		},
++	[27] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_SGI,
++		.phy_type = WLAN_RC_PHY_HT_20_SS_SGI,
++		.rate_kbps = 43300,
++		.dot11_rate_idx = 4,
++		.ctrl_rate_idx = 11,
++		.hw_rate_idx = 27,
++		.arith_shift = 8,
++		.target_pf = 26,
++		},
++	[28] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_SGI,
++		.phy_type = WLAN_RC_PHY_HT_20_SS_SGI,
++		.rate_kbps = 57800,
++		.dot11_rate_idx = 5,
++		.ctrl_rate_idx = 11,
++		.hw_rate_idx = 28,
++		.arith_shift = 8,
++		.target_pf = 26,
++		},
++	[29] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_SGI,
++		.phy_type = WLAN_RC_PHY_HT_20_SS_SGI,
++		.rate_kbps = 65000,
++		.dot11_rate_idx = 6,
++		.ctrl_rate_idx = 11,
++		.hw_rate_idx = 29,
++		.arith_shift = 8,
++		.target_pf = 26,
++		},
++	[30] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_SGI,
++		.phy_type = WLAN_RC_PHY_HT_20_SS_SGI,
++		.rate_kbps = 72200,
++		.dot11_rate_idx = 7,
++		.ctrl_rate_idx = 11,
++		.hw_rate_idx = 30,
++		.arith_shift = 8,
++		.target_pf = 8},
++	[31] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_GF,
++		.phy_type = WLAN_RC_PHY_HT_20_SS_GF,
++		.rate_kbps = 6500,
++		.dot11_rate_idx = 0,
++		.ctrl_rate_idx = 7,
++		.hw_rate_idx = 31,
++		.arith_shift = 8,
++		.target_pf = 26,
++		},
++	[32] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_GF,
++		.phy_type = WLAN_RC_PHY_HT_20_SS_GF,
++		.rate_kbps = 13000,
++		.dot11_rate_idx = 1,
++		.ctrl_rate_idx = 9,
++		.hw_rate_idx = 32,
++		.arith_shift = 8,
++		.target_pf = 26,
++		},
++	[33] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_GF,
++		.phy_type = WLAN_RC_PHY_HT_20_SS_GF,
++		.rate_kbps = 19500,
++		.dot11_rate_idx = 2,
++		.ctrl_rate_idx = 9,
++		.hw_rate_idx = 33,
++		.arith_shift = 8,
++		.target_pf = 26,
++		},
++	[34] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_GF,
++		.phy_type = WLAN_RC_PHY_HT_20_SS_GF,
++		.rate_kbps = 26000,
++		.dot11_rate_idx = 3,
++		.ctrl_rate_idx = 11,
++		.hw_rate_idx = 34,
++		.arith_shift = 8,
++		.target_pf = 26,
++		},
++	[35] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_GF,
++		.phy_type = WLAN_RC_PHY_HT_20_SS_GF,
++		.rate_kbps = 39000,
++		.dot11_rate_idx = 4,
++		.ctrl_rate_idx = 11,
++		.hw_rate_idx = 35,
++		.arith_shift = 8,
++		.target_pf = 26,
++		},
++	[36] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_GF,
++		.phy_type = WLAN_RC_PHY_HT_20_SS_GF,
++		.rate_kbps = 52000,
++		.dot11_rate_idx = 5,
++		.ctrl_rate_idx = 11,
++		.hw_rate_idx = 36,
++		.arith_shift = 8,
++		.target_pf = 26,
++		},
++	[37] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_GF,
++		.phy_type = WLAN_RC_PHY_HT_20_SS_GF,
++		.rate_kbps = 58500,
++		.dot11_rate_idx = 6,
++		.ctrl_rate_idx = 11,
++		.hw_rate_idx = 37,
++		.arith_shift = 8,
++		.target_pf = 26,
++		},
++	[38] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_GF,
++		.phy_type = WLAN_RC_PHY_HT_20_SS_GF,
++		.rate_kbps = 65000,
++		.dot11_rate_idx = 7,
++		.ctrl_rate_idx = 11,
++		.hw_rate_idx = 38,
++		.arith_shift = 8,
++		.target_pf = 8},
++};
++
++const u16 ssv6xxx_rc_rate_set[RC_TYPE_MAX][13] = {
++	[RC_TYPE_B_ONLY] = {4, 0, 1, 2, 3},
++	[RC_TYPE_LEGACY_GB] = {12, 0, 1, 2, 7, 8, 3, 9, 10, 11, 12, 13, 14},
++	[RC_TYPE_SGI_20] = {8, 23, 24, 25, 26, 27, 28, 29, 30},
++	[RC_TYPE_LGI_20] = {8, 15, 16, 17, 18, 19, 20, 21, 22},
++	[RC_TYPE_HT_SGI_20] = {8, 23, 24, 25, 26, 27, 28, 29, 30},
++	[RC_TYPE_HT_LGI_20] = {8, 15, 16, 17, 18, 19, 20, 21, 22},
++	[RC_TYPE_HT_GF] = {8, 31, 32, 33, 34, 35, 36, 37, 38},
++};
++
++static u32 ssv6xxx_rate_supported(struct ssv_sta_rc_info *rc_sta, u32 index)
++{
++	return (rc_sta->rc_supp_rates & BIT(index));
++}
++
++static u8 ssv6xxx_rate_lowest_index(struct ssv_sta_rc_info *rc_sta)
++{
++	int i;
++	for (i = 0; i < rc_sta->rc_num_rate; i++)
++		if (ssv6xxx_rate_supported(rc_sta, i))
++			return i;
++	return 0;
++}
++
++#ifdef DISABLE_RATE_CONTROL_SAMPLE
++static u8 ssv6xxx_rate_highest_index(struct ssv_sta_rc_info *rc_sta)
++{
++	int i;
++	for (i = rc_sta->rc_num_rate - 1; i >= 0; i--)
++		if (ssv6xxx_rate_supported(rc_sta, i))
++			return i;
++	return 0;
++}
++#endif
++static void rate_control_pid_adjust_rate(struct ssv_sta_rc_info *rc_sta,
++					 struct rc_pid_sta_info *spinfo,
++					 int adj, struct rc_pid_rateinfo *rinfo)
++{
++	int cur_sorted, new_sorted, probe, tmp, n_bitrates;
++	int cur = spinfo->txrate_idx;
++	n_bitrates = rc_sta->rc_num_rate;
++	cur_sorted = rinfo[cur].index;
++	new_sorted = cur_sorted + adj;
++	if (new_sorted < 0)
++		new_sorted = rinfo[0].index;
++	else if (new_sorted >= n_bitrates)
++		new_sorted = rinfo[n_bitrates - 1].index;
++	tmp = new_sorted;
++	if (adj < 0) {
++		for (probe = cur_sorted; probe >= new_sorted; probe--)
++			if (rinfo[probe].diff <= rinfo[cur_sorted].diff &&
++			    ssv6xxx_rate_supported(rc_sta, rinfo[probe].index))
++				tmp = probe;
++	} else {
++		for (probe = new_sorted + 1; probe < n_bitrates; probe++)
++			if (rinfo[probe].diff <= rinfo[new_sorted].diff &&
++			    ssv6xxx_rate_supported(rc_sta, rinfo[probe].index))
++				tmp = probe;
++	}
++	BUG_ON(tmp < 0 || tmp >= n_bitrates);
++	do {
++		if (ssv6xxx_rate_supported(rc_sta, rinfo[tmp].index)) {
++			spinfo->tmp_rate_idx = rinfo[tmp].index;
++			break;
++		}
++		if (adj < 0)
++			tmp--;
++		else
++			tmp++;
++	} while (tmp < n_bitrates && tmp >= 0);
++	spinfo->oldrate = spinfo->txrate_idx;
++	if (spinfo->tmp_rate_idx != spinfo->txrate_idx) {
++		spinfo->monitoring = 1;
++#ifdef RATE_CONTROL_PARAMETER_DEBUG
++		pr_debug("Trigger monitor tmp_rate_idx=[%d]\n",
++		       spinfo->tmp_rate_idx);
++#endif
++		spinfo->probe_cnt = MAXPROBES;
++	}
++}
++
++static void rate_control_pid_normalize(struct rc_pid_info *pinfo, int l)
++{
++	int i, norm_offset = RC_PID_NORM_OFFSET;
++	struct rc_pid_rateinfo *r = pinfo->rinfo;
++	if (r[0].diff > norm_offset)
++		r[0].diff -= norm_offset;
++	else if (r[0].diff < -norm_offset)
++		r[0].diff += norm_offset;
++	for (i = 0; i < l - 1; i++)
++		if (r[i + 1].diff > r[i].diff + norm_offset)
++			r[i + 1].diff -= norm_offset;
++		else if (r[i + 1].diff <= r[i].diff)
++			r[i + 1].diff += norm_offset;
++}
++
++#ifdef RATE_CONTROL_DEBUG
++unsigned int txrate_dlr = 0;
++#endif
++static void rate_control_pid_sample(struct ssv_rate_ctrl *ssv_rc,
++				    struct rc_pid_info *pinfo,
++				    struct ssv_sta_rc_info *rc_sta,
++				    struct rc_pid_sta_info *spinfo)
++{
++	struct rc_pid_rateinfo *rinfo = pinfo->rinfo;
++	u8 pf;
++	s32 err_avg;
++	s32 err_prop;
++	s32 err_int;
++	s32 err_der;
++	int adj, i, j, tmp;
++	struct ssv_rc_rate *rc_table;
++	unsigned int dlr;
++	unsigned int perfect_time = 0;
++	unsigned int this_thp, ewma_thp;
++	struct rc_pid_rateinfo *rate;
++	if (!spinfo->monitoring) {
++		if (spinfo->tx_num_xmit == 0)
++			return;
++		spinfo->last_sample = jiffies;
++		pf = spinfo->tx_num_failed * 100 / spinfo->tx_num_xmit;
++		if (pinfo->rinfo[spinfo->txrate_idx].this_attempt > 0) {
++			rate = &pinfo->rinfo[spinfo->txrate_idx];
++			rc_table = &ssv_rc->rc_table[spinfo->txrate_idx];
++			dlr = 100 - rate->this_fail * 100 / rate->this_attempt;
++			perfect_time = rate->perfect_tx_time;
++			if (!perfect_time)
++				perfect_time = 1000000;
++			this_thp = dlr * (1000000 / perfect_time);
++			ewma_thp = rate->throughput;
++			if (ewma_thp == 0)
++				rate->throughput = this_thp;
++			else
++				rate->throughput = (ewma_thp + this_thp) >> 1;
++			rate->attempt += rate->this_attempt;
++			rate->success += rate->this_success;
++			rate->fail += rate->this_fail;
++			spinfo->tx_num_xmit = 0;
++			spinfo->tx_num_failed = 0;
++			rate->this_fail = 0;
++			rate->this_success = 0;
++			rate->this_attempt = 0;
++			if (pinfo->oldrate < 0
++			    || pinfo->oldrate >= rc_sta->rc_num_rate) {
++				WARN_ON(1);
++			}
++			if (spinfo->txrate_idx < 0
++			    || spinfo->txrate_idx >= rc_sta->rc_num_rate) {
++				WARN_ON(1);
++			}
++			if (pinfo->oldrate != spinfo->txrate_idx) {
++				i = rinfo[pinfo->oldrate].index;
++				j = rinfo[spinfo->txrate_idx].index;
++				tmp = (pf - spinfo->last_pf);
++				tmp =
++				    RC_PID_DO_ARITH_RIGHT_SHIFT(tmp,
++								rc_table->arith_shift);
++				rinfo[j].diff = rinfo[i].diff + tmp;
++				pinfo->oldrate = spinfo->txrate_idx;
++			}
++			rate_control_pid_normalize(pinfo, rc_sta->rc_num_rate);
++			err_prop =
++			    (rc_table->target_pf - pf) << rc_table->arith_shift;
++			err_avg = spinfo->err_avg_sc >> RC_PID_SMOOTHING_SHIFT;
++			spinfo->err_avg_sc =
++			    spinfo->err_avg_sc - err_avg + err_prop;
++			err_int = spinfo->err_avg_sc >> RC_PID_SMOOTHING_SHIFT;
++			err_der = pf - spinfo->last_pf;
++			spinfo->last_pf = pf;
++			spinfo->last_dlr = dlr;
++			spinfo->oldrate = spinfo->txrate_idx;
++			adj =
++			    (err_prop * RC_PID_COEFF_P +
++			     err_int * RC_PID_COEFF_I +
++			     err_der * RC_PID_COEFF_D);
++			adj =
++			    RC_PID_DO_ARITH_RIGHT_SHIFT(adj,
++							rc_table->arith_shift <<
++							1);
++			if (adj) {
++#ifdef RATE_CONTROL_PARAMETER_DEBUG
++				if ((spinfo->txrate_idx != 11)
++				    || ((spinfo->txrate_idx == 11)
++					&& (adj < 0)))
++					pr_debug
++					    ("[RC]Probe adjust[%d] dlr[%d%%] this_thp[%d] ewma_thp[%d] index[%d]\n",
++					     adj, dlr, this_thp, ewma_thp,
++					     spinfo->txrate_idx);
++#endif
++				rate_control_pid_adjust_rate(rc_sta, spinfo,
++							     adj, rinfo);
++			}
++		}
++	} else {
++		if ((spinfo->feedback_probes >= MAXPROBES)
++		    || (spinfo->feedback_probes && spinfo->probe_cnt)) {
++			rate = &pinfo->rinfo[spinfo->txrate_idx];
++			spinfo->last_sample = jiffies;
++			if (rate->this_attempt > 0) {
++				dlr =
++				    100 -
++				    rate->this_fail * 100 / rate->this_attempt;
++#ifdef RATE_CONTROL_DEBUG
++#ifdef PROBE
++				txrate_dlr = dlr;
++#endif
++#endif
++				spinfo->last_dlr = dlr;
++				perfect_time = rate->perfect_tx_time;
++				if (!perfect_time)
++					perfect_time = 1000000;
++				this_thp = dlr * (1000000 / perfect_time);
++				ewma_thp = rate->throughput;
++				if (ewma_thp == 0)
++					rate->throughput = this_thp;
++				else
++					rate->throughput =
++					    (ewma_thp + this_thp) >> 1;
++				rate->attempt += rate->this_attempt;
++				rate->success += rate->this_success;
++				rinfo[spinfo->txrate_idx].fail +=
++				    rate->this_fail;
++				rate->this_fail = 0;
++				rate->this_success = 0;
++				rate->this_attempt = 0;
++			} else {
++#ifdef RATE_CONTROL_DEBUG
++#ifdef PROBE
++				txrate_dlr = 0;
++#endif
++#endif
++			}
++			rate = &pinfo->rinfo[spinfo->tmp_rate_idx];
++			if (rate->this_attempt > 0) {
++				dlr =
++				    100 -
++				    ((rate->this_fail * 100) /
++				     rate->this_attempt);
++				{
++					perfect_time = rate->perfect_tx_time;
++					if (!perfect_time)
++						perfect_time = 1000000;
++					if (dlr)
++						this_thp =
++						    dlr * (1000000 /
++							   perfect_time);
++					else
++						this_thp = 0;
++					ewma_thp = rate->throughput;
++					if (ewma_thp == 0)
++						rate->throughput = this_thp;
++					else
++						rate->throughput =
++						    (ewma_thp + this_thp) >> 1;
++					if (rate->throughput >
++					    pinfo->rinfo[spinfo->
++							 txrate_idx].throughput)
++					{
++#ifdef RATE_CONTROL_PARAMETER_DEBUG
++						pr_debug
++						    ("[RC]UPDATE probe rate idx[%d] [%d][%d%%] Old idx[%d] [%d][%d%%] feedback[%d] \n",
++						     spinfo->tmp_rate_idx,
++						     rate->throughput, dlr,
++						     spinfo->txrate_idx,
++						     pinfo->
++						     rinfo
++						     [spinfo->txrate_idx].throughput,
++						     txrate_dlr,
++						     spinfo->feedback_probes);
++#endif
++						spinfo->txrate_idx =
++						    spinfo->tmp_rate_idx;
++					} else {
++#ifdef RATE_CONTROL_PARAMETER_DEBUG
++						pr_debug
++						    ("[RC]Fail probe rate idx[%d] [%d][%d%%] Old idx[%d] [%d][%d%%] feedback[%d] \n",
++						     spinfo->tmp_rate_idx,
++						     rate->throughput, dlr,
++						     spinfo->txrate_idx,
++						     pinfo->
++						     rinfo
++						     [spinfo->txrate_idx].throughput,
++						     txrate_dlr,
++						     spinfo->feedback_probes);
++#endif
++						;
++					}
++					rate->attempt += rate->this_attempt;
++					rate->success += rate->this_success;
++					rate->fail += rate->this_fail;
++					rate->this_fail = 0;
++					rate->this_success = 0;
++					rate->this_attempt = 0;
++					spinfo->oldrate = spinfo->txrate_idx;
++				}
++			}
++#ifdef RATE_CONTROL_DEBUG
++			else
++				pr_err("Unexpected error\n");
++#endif
++			spinfo->feedback_probes = 0;
++			spinfo->tx_num_xmit = 0;
++			spinfo->tx_num_failed = 0;
++			spinfo->monitoring = 0;
++#ifdef RATE_CONTROL_PARAMETER_DEBUG
++			pr_debug("Disable monitor\n");
++#endif
++			spinfo->probe_report_flag = 0;
++			spinfo->probe_wating_times = 0;
++		} else {
++			spinfo->probe_wating_times++;
++#ifdef RATE_CONTROL_DEBUG
++			if (spinfo->probe_wating_times > 3) {
++				pr_debug
++				    ("[RC]@@@@@ PROBE LOSE @@@@@ feedback=[%d] need=[%d] probe_cnt=[%d] wating times[%d]\n",
++				     spinfo->feedback_probes, MAXPROBES,
++				     spinfo->probe_cnt,
++				     spinfo->probe_wating_times);
++				spinfo->feedback_probes = 0;
++				spinfo->tx_num_xmit = 0;
++				spinfo->tx_num_failed = 0;
++				spinfo->monitoring = 0;
++				spinfo->probe_report_flag = 0;
++				spinfo->probe_wating_times = 0;
++			}
++#else
++			if (spinfo->probe_wating_times > 3) {
++				spinfo->feedback_probes = 0;
++				spinfo->tx_num_xmit = 0;
++				spinfo->tx_num_failed = 0;
++				spinfo->monitoring = 0;
++				spinfo->probe_report_flag = 0;
++				spinfo->probe_wating_times = 0;
++			}
++#endif
++		}
++	}
++}
++
++#ifdef RATE_CONTROL_PERCENTAGE_TRACE
++int percentage = 0;
++int percentageCounter = 0;
++#endif
++void ssv6xxx_legacy_report_handler(struct ssv_softc *sc, struct sk_buff *skb,
++				   struct ssv_sta_rc_info *rc_sta)
++{
++	struct ssv_rate_ctrl *ssv_rc = sc->rc;
++	struct cfg_host_event *host_event;
++	struct firmware_rate_control_report_data *report_data;
++	struct rc_pid_info *pinfo;
++	struct rc_pid_sta_info *spinfo;
++	struct rc_pid_rateinfo *pidrate;
++	struct rc_pid_rateinfo *rate;
++	s32 report_data_index = 0;
++	unsigned long period;
++	host_event = (struct cfg_host_event *)skb->data;
++	report_data =
++	    (struct firmware_rate_control_report_data *)&host_event->dat[0];
++	if ((report_data->wsid != (-1))
++	    && sc->sta_info[report_data->wsid].sta == NULL) {
++		dev_warn(sc->dev, "RC report has no valid STA.(%d)\n",
++			 report_data->wsid);
++		return;
++	}
++	pinfo = &rc_sta->pinfo;
++	spinfo = &rc_sta->spinfo;
++	pidrate = rc_sta->pinfo.rinfo;
++	if (host_event->h_event == SOC_EVT_RC_AMPDU_REPORT) {
++		period = msecs_to_jiffies(HT_RC_UPDATE_INTERVAL);
++		if (time_after(jiffies, spinfo->last_sample + period)) {
++			if (rc_sta->rc_num_rate == 12)
++				spinfo->txrate_idx = rc_sta->ht.max_tp_rate + 4;
++			else
++				spinfo->txrate_idx = rc_sta->ht.max_tp_rate;
++#ifdef RATE_CONTROL_DEBUG
++			pr_debug("MPDU rate update time txrate_idx[%d]!!\n",
++			       spinfo->txrate_idx);
++#endif
++			spinfo->last_sample = jiffies;
++		}
++		return;
++	} else if (host_event->h_event == SOC_EVT_RC_MPDU_REPORT) {
++		;
++	} else {
++		dev_warn(sc->dev, "RC report handler got garbage\n");
++		return;
++	}
++	if (report_data->rates[0].data_rate < 7) {
++		if (report_data->rates[0].data_rate > 3) {
++			report_data->rates[0].data_rate -= 3;
++		}
++	}
++	if (ssv_rc->
++	    rc_table[rc_sta->pinfo.rinfo[spinfo->txrate_idx].
++		     rc_index].hw_rate_idx == report_data->rates[0].data_rate) {
++		report_data_index =
++		    rc_sta->pinfo.rinfo[spinfo->txrate_idx].index;
++	} else
++	    if (ssv_rc->rc_table
++		[rc_sta->pinfo.rinfo[spinfo->tmp_rate_idx].
++		 rc_index].hw_rate_idx == report_data->rates[0].data_rate) {
++		report_data_index =
++		    rc_sta->pinfo.rinfo[spinfo->tmp_rate_idx].index;
++	}
++	if ((report_data_index != spinfo->tmp_rate_idx)
++	    && (report_data_index != spinfo->txrate_idx)) {
++#ifdef RATE_CONTROL_DEBUG
++		dev_dbg
++		    (sc->dev, "Rate control report mismatch report_rate_idx[%d] tmp_rate_idx[%d]rate[%d] txrate_idx[%d]rate[%d]!!\n",
++		     report_data->rates[0].data_rate, spinfo->tmp_rate_idx,
++		     ssv_rc->rc_table[rc_sta->pinfo.
++				      rinfo[spinfo->tmp_rate_idx].rc_index].
++		     hw_rate_idx, spinfo->txrate_idx,
++		     ssv_rc->rc_table[rc_sta->pinfo.
++				      rinfo[spinfo->txrate_idx].rc_index].
++		     hw_rate_idx);
++#endif
++		return;
++	}
++	if (report_data_index == spinfo->txrate_idx) {
++		spinfo->tx_num_xmit += report_data->rates[0].count;
++		spinfo->tx_num_failed +=
++		    (report_data->rates[0].count - report_data->ampdu_ack_len);
++		rate = &pidrate[spinfo->txrate_idx];
++		rate->this_fail +=
++		    (report_data->rates[0].count - report_data->ampdu_ack_len);
++		rate->this_attempt += report_data->rates[0].count;
++		rate->this_success += report_data->ampdu_ack_len;
++	}
++	if (report_data_index != spinfo->txrate_idx
++	    && report_data_index == spinfo->tmp_rate_idx) {
++		spinfo->feedback_probes += report_data->ampdu_len;
++		rate = &pidrate[spinfo->tmp_rate_idx];
++		rate->this_fail +=
++		    (report_data->rates[0].count - report_data->ampdu_ack_len);
++		rate->this_attempt += report_data->rates[0].count;
++		rate->this_success += report_data->ampdu_ack_len;
++	}
++	period = msecs_to_jiffies(RC_PID_INTERVAL);
++	if (time_after(jiffies, spinfo->last_sample + period)) {
++#ifdef RATE_CONTROL_PERCENTAGE_TRACE
++		rate = &pidrate[spinfo->txrate_idx];
++		if (rate->this_success > rate->this_attempt) {
++			dev_dbg(sc->dev, "this_success[%ld] this_attempt[%ld]\n",
++			       rate->this_success, rate->this_attempt);
++		} else {
++			if (percentage == 0)
++				percentage =
++				    (int)((rate->this_success * 100) /
++					  rate->this_attempt);
++			else
++				percentage =
++				    (percentage +
++				     (int)((rate->this_success * 100) /
++					   rate->this_attempt)) / 2;
++			deb_dbg(sc->dev, "Percentage[%d]\n", percentage);
++			if ((percentageCounter % 16) == 1)
++				percentage = 0;
++		}
++#endif
++#ifdef RATE_CONTROL_STUPID_DEBUG
++		if (spinfo->txrate_idx != spinfo->tmp_rate_idx) {
++			rate = &pidrate[spinfo->tmp_rate_idx];
++			if (spinfo->monitoring && ((rate->this_attempt == 0)
++						   || (rate->this_attempt !=
++						       MAXPROBES))) {
++				dev_dbg(sc->dev, "Probe result a[%ld]s[%ld]f[%ld]",
++				       rate->this_attempt, rate->this_success,
++				       rate->this_fail);
++			}
++			rate = &pidrate[spinfo->txrate_idx];
++			dev_dbg(sc->dev, "New a[%ld]s[%ld]f[%ld] \n", rate->this_attempt,
++			       rate->this_success, rate->this_fail);
++		} else {
++			rate = &pidrate[spinfo->txrate_idx];
++			dev_dbg(sc->dev, "New a[%ld]s[%ld]f[%ld] \n", rate->this_attempt,
++			       rate->this_success, rate->this_fail);
++		}
++		dev_dbg(sc->dev, "w[%d]x%03d-f%03d\n", rc_sta->rc_wsid,
++		       spinfo->tx_num_xmit, spinfo->tx_num_failed);
++#endif
++		rate_control_pid_sample(sc->rc, pinfo, rc_sta, spinfo);
++	}
++}
++
++void ssv6xxx_sample_work(struct work_struct *work)
++{
++	struct ssv_softc *sc =
++	    container_of(work, struct ssv_softc, rc_sample_work);
++	struct ssv_rate_ctrl *ssv_rc = sc->rc;
++	struct sk_buff *skb;
++	struct cfg_host_event *host_event;
++	struct ssv_sta_rc_info *rc_sta = NULL;
++	struct firmware_rate_control_report_data *report_data;
++	struct ssv_sta_info *ssv_sta;
++	u8 hw_wsid = 0;
++	sc->rc_sample_sechedule = 1;
++	while (1) {
++		skb = skb_dequeue(&sc->rc_report_queue);
++		if (skb == NULL)
++			break;
++#ifdef DISABLE_RATE_CONTROL_SAMPLE
++		{
++			dev_kfree_skb_any(skb);
++			continue;
++		}
++#endif
++		host_event = (struct cfg_host_event *)skb->data;
++		if ((host_event->h_event == SOC_EVT_RC_AMPDU_REPORT)
++		    || (host_event->h_event == SOC_EVT_RC_MPDU_REPORT)) {
++			report_data =
++			    (struct firmware_rate_control_report_data *)
++			    &host_event->dat[0];
++			hw_wsid = report_data->wsid;
++		} else {
++			dev_warn(sc->dev, "rate control sampling got garbage\n");
++			dev_kfree_skb_any(skb);
++			continue;
++		}
++		if (hw_wsid >= SSV_RC_MAX_HARDWARE_SUPPORT) {
++#ifdef RATE_CONTROL_DEBUG
++			dev_dbg(sc->dev, "[RC]rc_sta is NULL pointer Check-0!!\n");
++#endif
++			dev_kfree_skb_any(skb);
++			continue;
++		}
++		ssv_sta = &sc->sta_info[hw_wsid];
++		if (ssv_sta->sta == NULL) {
++			dev_err(sc->dev, "Null STA %d for RC report.\n",
++				hw_wsid);
++			rc_sta = NULL;
++		} else {
++			struct ssv_sta_priv_data *ssv_sta_priv =
++			    (struct ssv_sta_priv_data *)ssv_sta->sta->drv_priv;
++			rc_sta = &ssv_rc->sta_rc_info[ssv_sta_priv->rc_idx];
++			if (rc_sta->rc_wsid != hw_wsid) {
++				rc_sta = NULL;
++			}
++		}
++		if (rc_sta == NULL) {
++			dev_err(sc->dev,
++				"[RC]rc_sta is NULL pointer Check-1!!\n");
++			dev_kfree_skb_any(skb);
++			continue;
++		}
++		if (rc_sta == NULL) {
++#ifdef RATE_CONTROL_DEBUG
++			dev_dbg(sc->dev, "[RC]rc_sta is NULL pointer Check-2!!\n");
++#endif
++			dev_kfree_skb_any(skb);
++			continue;
++		}
++		if (rc_sta->is_ht) {
++			ssv6xxx_legacy_report_handler(sc, skb, rc_sta);
++			ssv6xxx_ht_report_handler(sc, skb, rc_sta);
++		} else
++			ssv6xxx_legacy_report_handler(sc, skb, rc_sta);
++		dev_kfree_skb_any(skb);
++	}
++	sc->rc_sample_sechedule = 0;
++}
++
++static void ssv6xxx_tx_status(void *priv,
++			      struct ieee80211_supported_band *sband,
++			      struct ieee80211_sta *sta, void *priv_sta,
++			      struct sk_buff *skb)
++{
++	struct ssv_softc *sc;
++	struct ieee80211_hdr *hdr;
++	__le16 fc;
++	hdr = (struct ieee80211_hdr *)skb->data;
++	fc = hdr->frame_control;
++	if (!priv_sta || !ieee80211_is_data_qos(fc))
++		return;
++	sc = (struct ssv_softc *)priv;
++	if (conf_is_ht(&sc->hw->conf)
++	    && (!(skb->protocol == cpu_to_be16(ETH_P_PAE)))) {
++		if (skb_get_queue_mapping(skb) != IEEE80211_AC_VO)
++			ssv6200_ampdu_tx_update_state(priv, sta, skb);
++	}
++	return;
++}
++
++static void rateControlGetRate(u8 rateIndex, char *pointer)
++{
++	switch (rateIndex) {
++	case 0:
++		sprintf(pointer, "1Mbps");
++		return;
++	case 1:
++	case 4:
++		sprintf(pointer, "2Mbps");
++		return;
++	case 2:
++	case 5:
++		sprintf(pointer, "5.5Mbps");
++		return;
++	case 3:
++	case 6:
++		sprintf(pointer, "11Mbps");
++		return;
++	case 7:
++		sprintf(pointer, "6Mbps");
++		return;
++	case 8:
++		sprintf(pointer, "9Mbps");
++		return;
++	case 9:
++		sprintf(pointer, "12Mbps");
++		return;
++	case 10:
++		sprintf(pointer, "18Mbps");
++		return;
++	case 11:
++		sprintf(pointer, "24Mbps");
++		return;
++	case 12:
++		sprintf(pointer, "36Mbps");
++		return;
++	case 13:
++		sprintf(pointer, "48Mbps");
++		return;
++	case 14:
++		sprintf(pointer, "54Mbps");
++		return;
++	case 15:
++	case 31:
++		sprintf(pointer, "MCS0-l");
++		return;
++	case 16:
++	case 32:
++		sprintf(pointer, "MCS1-l");
++		return;
++	case 17:
++	case 33:
++		sprintf(pointer, "MCS2-l");
++		return;
++	case 18:
++	case 34:
++		sprintf(pointer, "MCS3-l");
++		return;
++	case 19:
++	case 35:
++		sprintf(pointer, "MCS4-l");
++		return;
++	case 20:
++	case 36:
++		sprintf(pointer, "MCS5-l");
++		return;
++	case 21:
++	case 37:
++		sprintf(pointer, "MCS6-l");
++		return;
++	case 22:
++	case 38:
++		sprintf(pointer, "MCS7-l");
++		return;
++	case 23:
++		sprintf(pointer, "MCS0-s");
++		return;
++	case 24:
++		sprintf(pointer, "MCS1-s");
++		return;
++	case 25:
++		sprintf(pointer, "MCS2-s");
++		return;
++	case 26:
++		sprintf(pointer, "MCS3-s");
++		return;
++	case 27:
++		sprintf(pointer, "MCS4-s");
++		return;
++	case 28:
++		sprintf(pointer, "MCS5-s");
++		return;
++	case 29:
++		sprintf(pointer, "MCS6-s");
++		return;
++	case 30:
++		sprintf(pointer, "MCS7-s");
++		return;
++	default:
++		sprintf(pointer, "Unknow");
++		return;
++	};
++}
++
++static void ssv6xxx_get_rate(void *priv, struct ieee80211_sta *sta,
++			     void *priv_sta,
++			     struct ieee80211_tx_rate_control *txrc)
++{
++	struct ssv_softc *sc = priv;
++	struct ssv_rate_ctrl *ssv_rc = sc->rc;
++	struct ssv_sta_rc_info *rc_sta = priv_sta;
++	struct sk_buff *skb = txrc->skb;
++	struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
++	struct ieee80211_tx_rate *rates = tx_info->control.rates;
++	struct rc_pid_sta_info *spinfo = &rc_sta->spinfo;
++	struct ssv_rc_rate *rc_rate = NULL;
++	struct ssv_sta_priv_data *ssv_sta_priv;
++	int rateidx = 99;
++#if LINUX_VERSION_CODE < KERNEL_VERSION(5,2,0)
++	if (rate_control_send_low(sta, priv_sta, txrc)) {
++		int i = 0;
++		int total_rates =
++		    (sizeof(ssv_11bgn_rate_table) /
++		     sizeof(ssv_11bgn_rate_table[0]));
++#if 1
++		if ((txrc->rate_idx_mask & (1 << rates[0].idx)) == 0) {
++			u32 rate_idx = rates[0].idx + 1;
++			u32 rate_idx_mask = txrc->rate_idx_mask >> rate_idx;
++			while (rate_idx_mask && (rate_idx_mask & 1) == 0) {
++				rate_idx_mask >>= 1;
++				rate_idx++;
++			}
++			if (rate_idx_mask)
++				rates[0].idx = rate_idx;
++			else {
++				WARN_ON(rate_idx_mask == 0);
++			}
++		}
++#endif
++		for (i = 0; i < total_rates; i++) {
++			if (rates[0].idx ==
++			    ssv_11bgn_rate_table[i].dot11_rate_idx) {
++				break;
++			}
++		}
++		if (i < total_rates)
++			rc_rate = &ssv_rc->rc_table[i];
++		else {
++			WARN_ON("Failed to find matching low rate.");
++		}
++	}
++#endif
++	if (rc_rate == NULL) {
++		if (conf_is_ht(&sc->hw->conf) &&
++		    (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING))
++			tx_info->flags |= IEEE80211_TX_CTL_LDPC;
++		if (conf_is_ht(&sc->hw->conf) &&
++		    (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_TX_STBC))
++			tx_info->flags |= (1 << IEEE80211_TX_CTL_STBC_SHIFT);
++		if (sc->sc_flags & SC_OP_FIXED_RATE) {
++			rateidx = sc->max_rate_idx;
++		} else {
++			if (rc_sta->rc_valid == false) {
++				rateidx = 0;
++			} else {
++				if ((rc_sta->rc_wsid >=
++				     SSV_RC_MAX_HARDWARE_SUPPORT)
++				    || (rc_sta->rc_wsid < 0)) {
++					ssv_sta_priv =
++					    (struct ssv_sta_priv_data *)
++					    sta->drv_priv;
++					{
++						if ((rc_sta->ht_rc_type >=
++						     RC_TYPE_HT_SGI_20)
++						    &&
++						    (ssv_sta_priv->rx_data_rate
++						     <
++						     SSV62XX_RATE_MCS_INDEX)) {
++							rateidx =
++							    rc_sta->
++							    pinfo.rinfo
++							    [spinfo->txrate_idx].rc_index;
++						} else {
++							rateidx =
++							    ssv_sta_priv->rx_data_rate;
++						}
++					}
++				} else {
++					if (rc_sta->is_ht) {
++#ifdef DISABLE_RATE_CONTROL_SAMPLE
++						rateidx =
++						    rc_sta->ht.
++						    groups.rates[MCS_GROUP_RATES
++								 - 1].rc_index;
++#else
++						rateidx =
++						    rc_sta->pinfo.
++						    rinfo
++						    [spinfo->txrate_idx].rc_index;
++#endif
++					} else {
++						{
++							BUG_ON
++							    (spinfo->txrate_idx
++							     >=
++							     rc_sta->rc_num_rate);
++							rateidx =
++							    rc_sta->
++							    pinfo.rinfo
++							    [spinfo->txrate_idx].rc_index;
++						}
++						if (rateidx < 4) {
++							if (rateidx) {
++								if ((sc->sc_flags & SC_OP_SHORT_PREAMBLE)
++								    ||
++								    (txrc->short_preamble))
++								{
++									rateidx
++									    +=
++									    3;
++								}
++							}
++						}
++					}
++				}
++			}
++		}
++		rc_rate = &ssv_rc->rc_table[rateidx];
++		if (spinfo->real_hw_index != rc_rate->hw_rate_idx) {
++			char string[24];
++			rateControlGetRate(rc_rate->hw_rate_idx, string);
++		}
++		spinfo->real_hw_index = rc_rate->hw_rate_idx;
++		rates[0].count = 4;
++		rates[0].idx = rc_rate->dot11_rate_idx;
++		tx_info->control.rts_cts_rate_idx =
++		    ssv_rc->rc_table[rc_rate->ctrl_rate_idx].dot11_rate_idx;
++		if (rc_rate->rc_flags & RC_FLAG_SHORT_PREAMBLE)
++			rates[0].flags |= IEEE80211_TX_RC_USE_SHORT_PREAMBLE;
++		if (rc_rate->rc_flags & RC_FLAG_HT) {
++			rates[0].flags |= IEEE80211_TX_RC_MCS;
++			if (rc_rate->rc_flags & RC_FLAG_HT_SGI)
++				rates[0].flags |= IEEE80211_TX_RC_SHORT_GI;
++			if (rc_rate->rc_flags & RC_FLAG_HT_GF)
++				rates[0].flags |= IEEE80211_TX_RC_GREEN_FIELD;
++		}
++	}
++	rates[1].count = 0;
++	rates[1].idx = -1;
++	rates[SSV_DRATE_IDX].count = rc_rate->hw_rate_idx;
++	rc_rate = &ssv_rc->rc_table[rc_rate->ctrl_rate_idx];
++	rates[SSV_CRATE_IDX].count = rc_rate->hw_rate_idx;
++}
++
++int pide_frame_duration(size_t len, int rate, int short_preamble, int flags)
++{
++	int dur = 0;
++	if (flags == WLAN_RC_PHY_CCK) {
++		dur = 10;
++		dur += short_preamble ? (72 + 24) : (144 + 48);
++		dur += DIV_ROUND_UP(8 * (len + 4) * 10, rate);
++	} else {
++		dur = 16;
++		dur += 16;
++		dur += 4;
++		dur += 4 * DIV_ROUND_UP((16 + 8 * (len + 4) + 6) * 10,
++					4 * rate);
++	}
++	return dur;
++}
++
++static void ssv62xx_rc_caps(struct ssv_sta_rc_info *rc_sta)
++{
++	struct rc_pid_sta_info *spinfo;
++	struct rc_pid_info *pinfo;
++	struct rc_pid_rateinfo *rinfo;
++	int i;
++	spinfo = &rc_sta->spinfo;
++	pinfo = &rc_sta->pinfo;
++	memset(spinfo, 0, sizeof(struct rc_pid_sta_info));
++	memset(pinfo, 0, sizeof(struct rc_pid_info));
++	rinfo = rc_sta->pinfo.rinfo;
++	for (i = 0; i < rc_sta->rc_num_rate; i++) {
++		rinfo[i].rc_index = ssv6xxx_rc_rate_set[rc_sta->rc_type][i + 1];
++		rinfo[i].diff = i * RC_PID_NORM_OFFSET;
++		rinfo[i].index = (u16) i;
++		rinfo[i].perfect_tx_time =
++		    TDIFS + (TSLOT * 15 >> 1) + pide_frame_duration(1530,
++								    ssv_11bgn_rate_table
++								    [rinfo
++								     [i].rc_index].rate_kbps
++								    / 100, 1,
++								    ssv_11bgn_rate_table
++								    [rinfo
++								     [i].rc_index].phy_type)
++		    + pide_frame_duration(10,
++					  ssv_11bgn_rate_table[rinfo[i].
++							       rc_index].rate_kbps
++					  / 100, 1,
++					  ssv_11bgn_rate_table[rinfo[i].
++							       rc_index].phy_type);
++		pr_debug("[RC]Init perfect_tx_time[%d][%d]\n", i,
++		       rinfo[i].perfect_tx_time);
++		rinfo[i].throughput = 0;
++	}
++	if (rc_sta->is_ht) {
++		if (ssv6xxx_rc_rate_set[rc_sta->ht_rc_type][0] == 12)
++			spinfo->txrate_idx = 4;
++		else
++			spinfo->txrate_idx = 0;
++	} else {
++		spinfo->txrate_idx = ssv6xxx_rate_lowest_index(rc_sta);
++#ifdef DISABLE_RATE_CONTROL_SAMPLE
++		spinfo->txrate_idx = ssv6xxx_rate_highest_index(rc_sta);
++#endif
++	}
++	spinfo->real_hw_index = 0;
++	spinfo->probe_cnt = MAXPROBES;
++	spinfo->tmp_rate_idx = spinfo->txrate_idx;
++	spinfo->oldrate = spinfo->txrate_idx;
++	spinfo->last_sample = jiffies;
++	spinfo->last_report = jiffies;
++}
++
++static void ssv6xxx_rate_update_rc_type(void *priv,
++					struct ieee80211_supported_band *sband,
++					struct ieee80211_sta *sta,
++					void *priv_sta)
++{
++	struct ssv_softc *sc = priv;
++	struct ssv_hw *sh = sc->sh;
++	struct ssv_sta_rc_info *rc_sta = priv_sta;
++	int i;
++	u32 ht_supp_rates = 0;
++	BUG_ON(rc_sta->rc_valid == false);
++	dev_dbg(sc->dev, "[I] %s(): \n", __FUNCTION__);
++	rc_sta->ht_supp_rates = 0;
++	rc_sta->rc_supp_rates = 0;
++	rc_sta->is_ht = 0;
++#ifndef CONFIG_CH14_SUPPORT_GN_MODE
++	if (sc->cur_channel->hw_value == 14) {
++		dev_dbg(sc->dev, "[RC init ]Channel 14 support\n");
++		if ((sta->deflink.supp_rates[sband->band] & (~0xfL)) == 0x0) {
++			dev_dbg(sc->dev, "[RC init ]B only mode\n");
++			rc_sta->rc_type = RC_TYPE_B_ONLY;
++		} else {
++			dev_dbg(sc->dev, "[RC init ]GB mode\n");
++			rc_sta->rc_type = RC_TYPE_LEGACY_GB;
++		}
++	} else
++#endif
++	if (sta->deflink.ht_cap.ht_supported == true) {
++		dev_dbg(sc->dev, "[RC init ]HT support wsid\n");
++		for (i = 0; i < SSV_HT_RATE_MAX; i++) {
++			if (sta->deflink.ht_cap.mcs.rx_mask[i /
++						    MCS_GROUP_RATES] & (1 << (i
++									      %
++									      MCS_GROUP_RATES)))
++				ht_supp_rates |= BIT(i);
++		}
++		rc_sta->ht_supp_rates = ht_supp_rates;
++		if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_GRN_FLD) {
++			rc_sta->rc_type = RC_TYPE_HT_GF;
++			rc_sta->ht_rc_type = RC_TYPE_HT_GF;
++		} else if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20) {
++			rc_sta->rc_type = RC_TYPE_SGI_20;
++			rc_sta->ht_rc_type = RC_TYPE_HT_SGI_20;
++		} else {
++			rc_sta->rc_type = RC_TYPE_LGI_20;
++			rc_sta->ht_rc_type = RC_TYPE_HT_LGI_20;
++		}
++	} else {
++		if ((sta->deflink.supp_rates[sband->band] & (~0xfL)) == 0x0) {
++			rc_sta->rc_type = RC_TYPE_B_ONLY;
++			dev_dbg(sc->dev, "[RC init ]B only mode\n");
++		} else {
++			rc_sta->rc_type = RC_TYPE_LEGACY_GB;
++			dev_dbg(sc->dev, "[RC init ]legacy G mode\n");
++		}
++	}
++#ifdef CONFIG_SSV_DPD
++	if (rc_sta->rc_type == RC_TYPE_B_ONLY) {
++		SMAC_REG_WRITE(sh, ADR_TX_FE_REGISTER, 0x3D3E84FE);
++		SMAC_REG_WRITE(sh, ADR_RX_FE_REGISTER_1, 0x1457D79);
++		SMAC_REG_WRITE(sh, ADR_DPD_CONTROL, 0x0);
++	} else {
++		SMAC_REG_WRITE(sh, ADR_TX_FE_REGISTER, 0x3CBE84FE);
++		SMAC_REG_WRITE(sh, ADR_RX_FE_REGISTER_1, 0x4507F9);
++		SMAC_REG_WRITE(sh, ADR_DPD_CONTROL, 0x3);
++	}
++#endif
++	if ((rc_sta->rc_type != RC_TYPE_B_ONLY)
++	    && (rc_sta->rc_type != RC_TYPE_LEGACY_GB)) {
++		if ((sta->deflink.ht_cap.ht_supported)
++		    && (sh->cfg.hw_caps & SSV6200_HW_CAP_AMPDU_TX)) {
++			rc_sta->is_ht = 1;
++			ssv62xx_ht_rc_caps(ssv6xxx_rc_rate_set, rc_sta);
++		}
++	}
++	{
++		rc_sta->rc_num_rate =
++		    (u8) ssv6xxx_rc_rate_set[rc_sta->rc_type][0];
++		if ((rc_sta->rc_type == RC_TYPE_HT_GF)
++		    || (rc_sta->rc_type == RC_TYPE_LGI_20)
++		    || (rc_sta->rc_type == RC_TYPE_SGI_20)) {
++			if (rc_sta->rc_num_rate == 12) {
++				rc_sta->rc_supp_rates =
++				    sta->deflink.supp_rates[sband->band] & 0xfL;
++				rc_sta->rc_supp_rates |= (ht_supp_rates << 4);
++			} else
++				rc_sta->rc_supp_rates = ht_supp_rates;
++		} else if (rc_sta->rc_type == RC_TYPE_LEGACY_GB)
++			rc_sta->rc_supp_rates = sta->deflink.supp_rates[sband->band];
++		else if (rc_sta->rc_type == RC_TYPE_B_ONLY)
++			rc_sta->rc_supp_rates =
++			    sta->deflink.supp_rates[sband->band] & 0xfL;
++		ssv62xx_rc_caps(rc_sta);
++	}
++}
++
++static void ssv6xxx_rate_update(void *priv,
++				struct ieee80211_supported_band *sband,
++				struct cfg80211_chan_def *chandef,
++				struct ieee80211_sta *sta, void *priv_sta,
++				u32 changed)
++{
++	pr_debug("%s: changed=%d\n", __FUNCTION__, changed);
++	return;
++}
++
++static void ssv6xxx_rate_init(void *priv,
++			      struct ieee80211_supported_band *sband,
++			      struct cfg80211_chan_def *chandef,
++			      struct ieee80211_sta *sta, void *priv_sta)
++{
++	ssv6xxx_rate_update_rc_type(priv, sband, sta, priv_sta);
++}
++
++static void *ssv6xxx_rate_alloc_sta(void *priv, struct ieee80211_sta *sta,
++				    gfp_t gfp)
++{
++	struct ssv_sta_priv_data *sta_priv =
++	    (struct ssv_sta_priv_data *)sta->drv_priv;
++#ifndef RC_STA_DIRECT_MAP
++	struct ssv_softc *sc = priv;
++	struct ssv_rate_ctrl *ssv_rc = sc->rc;
++	int s;
++	sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
++	for (s = 0; s < SSV_RC_MAX_STA; s++) {
++		if (ssv_rc->sta_rc_info[s].rc_valid == false) {
++			dev_dbg(sc->dev, "%s(): use index %d\n", __FUNCTION__, s);
++			memset(&ssv_rc->sta_rc_info[s], 0,
++			       sizeof(struct ssv_sta_rc_info));
++			ssv_rc->sta_rc_info[s].rc_valid = true;
++			ssv_rc->sta_rc_info[s].rc_wsid = -1;
++			sta_priv->rc_idx = s;
++			return &ssv_rc->sta_rc_info[s];
++		}
++	}
++	return NULL;
++#else
++	sta_priv->rc_idx = (-1);
++	return sta_priv;
++#endif
++}
++
++static void ssv6xxx_rate_free_sta(void *priv, struct ieee80211_sta *sta,
++				  void *priv_sta)
++{
++	struct ssv_sta_rc_info *rc_sta = priv_sta;
++	rc_sta->rc_valid = false;
++}
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,14,0)
++static void *ssv6xxx_rate_alloc(struct ieee80211_hw *hw)
++#else
++static void *ssv6xxx_rate_alloc(struct ieee80211_hw *hw,
++				struct dentry *debugfsdir)
++#endif
++{
++	struct ssv_softc *sc = hw->priv;
++	struct ssv_rate_ctrl *ssv_rc;
++	sc->rc = kzalloc(sizeof(struct ssv_rate_ctrl), GFP_KERNEL);
++	if (!sc->rc) {
++		pr_err("%s(): Unable to allocate RC structure !\n",
++		       __FUNCTION__);
++		return NULL;
++	}
++	memset(sc->rc, 0, sizeof(struct ssv_rate_ctrl));
++	ssv_rc = (struct ssv_rate_ctrl *)sc->rc;
++	ssv_rc->rc_table = ssv_11bgn_rate_table;
++	skb_queue_head_init(&sc->rc_report_queue);
++	INIT_WORK(&sc->rc_sample_work, ssv6xxx_sample_work);
++	sc->rc_sample_workqueue = create_workqueue("ssv6xxx_rc_sample");
++	sc->rc_sample_sechedule = 0;
++	return hw->priv;
++}
++
++static void ssv6xxx_rate_free(void *priv)
++{
++	struct ssv_softc *sc = priv;
++	if (sc->rc) {
++		kfree(sc->rc);
++		sc->rc = NULL;
++	}
++	sc->rc_sample_sechedule = 0;
++	cancel_work_sync(&sc->rc_sample_work);
++	flush_workqueue(sc->rc_sample_workqueue);
++	destroy_workqueue(sc->rc_sample_workqueue);
++}
++
++static struct rate_control_ops ssv_rate_ops = {
++	.name = "ssv6xxx_rate_control",
++	.tx_status = ssv6xxx_tx_status,
++	.get_rate = ssv6xxx_get_rate,
++	.rate_init = ssv6xxx_rate_init,
++	.rate_update = ssv6xxx_rate_update,
++	.alloc = ssv6xxx_rate_alloc,
++	.free = ssv6xxx_rate_free,
++	.alloc_sta = ssv6xxx_rate_alloc_sta,
++	.free_sta = ssv6xxx_rate_free_sta,
++};
++
++void ssv6xxx_rc_mac8011_rate_idx(struct ssv_softc *sc,
++				 int hw_rate_idx,
++				 struct ieee80211_rx_status *rxs)
++{
++	struct ssv_rate_ctrl *ssv_rc = sc->rc;
++	struct ssv_rc_rate *rc_rate;
++	BUG_ON(hw_rate_idx >= RATE_TABLE_SIZE && hw_rate_idx < 0);
++	rc_rate = &ssv_rc->rc_table[hw_rate_idx];
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,12,0)
++	if (rc_rate->rc_flags & RC_FLAG_HT) {
++		// rxs->flag |= RC_FLAG_HT;
++		if (rc_rate->rc_flags & RC_FLAG_HT_SGI)
++			rxs->enc_flags |= RX_ENC_FLAG_SHORT_GI;
++	} else {
++		if (rc_rate->rc_flags & RC_FLAG_SHORT_PREAMBLE)
++			rxs->enc_flags |= RX_ENC_FLAG_SHORTPRE;
++	}
++#else
++	if (rc_rate->rc_flags & RC_FLAG_HT) {
++		rxs->flag |= RC_FLAG_HT;
++		if (rc_rate->rc_flags & RC_FLAG_HT_SGI)
++			rxs->flag |= RX_FLAG_SHORT_GI;
++	} else {
++		if (rc_rate->rc_flags & RC_FLAG_SHORT_PREAMBLE)
++			rxs->flag |= RX_FLAG_SHORTPRE;
++	}
++#endif
++	rxs->rate_idx = rc_rate->dot11_rate_idx;
++}
++
++void ssv6xxx_rc_hw_rate_idx(struct ssv_softc *sc,
++			    struct ieee80211_tx_info *info,
++			    struct ssv_rate_info *sr)
++{
++	struct ieee80211_tx_rate *tx_rate;
++	struct ssv_rate_ctrl *ssv_rc = sc->rc;
++	tx_rate = &info->control.rates[0];
++	sr->d_flags =
++	    (ssv_rc->rc_table[tx_rate[SSV_DRATE_IDX].count].phy_type ==
++	     WLAN_RC_PHY_OFDM) ? IEEE80211_RATE_ERP_G : 0;
++	sr->d_flags |=
++	    (ssv_rc->
++	     rc_table[tx_rate[SSV_DRATE_IDX].
++		      count].rc_flags & RC_FLAG_SHORT_PREAMBLE) ?
++	    IEEE80211_RATE_SHORT_PREAMBLE : 0;
++	sr->c_flags =
++	    (ssv_rc->rc_table[tx_rate[SSV_CRATE_IDX].count].phy_type ==
++	     WLAN_RC_PHY_OFDM) ? IEEE80211_RATE_ERP_G : 0;
++	sr->c_flags |=
++	    (ssv_rc->
++	     rc_table[tx_rate[SSV_CRATE_IDX].
++		      count].rc_flags & RC_FLAG_SHORT_PREAMBLE) ?
++	    IEEE80211_RATE_SHORT_PREAMBLE : 0;
++	sr->drate_kbps =
++	    ssv_rc->rc_table[tx_rate[SSV_DRATE_IDX].count].rate_kbps;
++	sr->drate_hw_idx = tx_rate[SSV_DRATE_IDX].count;
++	sr->crate_kbps =
++	    ssv_rc->rc_table[tx_rate[SSV_CRATE_IDX].count].rate_kbps;
++	sr->crate_hw_idx = tx_rate[SSV_CRATE_IDX].count;
++}
++
++u8 ssv6xxx_rc_hw_rate_update_check(struct sk_buff *skb, struct ssv_softc *sc,
++				   u32 do_rts_cts)
++{
++	int ret = 0;
++	struct ssv_rate_ctrl *ssv_rc = sc->rc;
++	struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
++	struct SKB_info_st *skb_info = (struct SKB_info_st *)skb->head;
++	struct ieee80211_sta *sta = skb_info->sta;
++	struct ieee80211_tx_rate *rates = &tx_info->control.rates[0];
++	struct ssv_rc_rate *rc_rate = NULL;
++	u8 rateidx = 0;
++	struct ssv_sta_rc_info *rc_sta = NULL;
++	struct rc_pid_sta_info *spinfo;
++	struct ssv_sta_priv_data *sta_priv = NULL;
++	unsigned long period = 0;
++	if (sc->sc_flags & SC_OP_FIXED_RATE)
++		return ret;
++	if (sta == NULL)
++		return ret;
++	sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
++	if (sta_priv == NULL) {
++#ifdef RATE_CONTROL_DEBUG
++		dev_dbg(rc->dev, "%s sta_priv == NULL \n\r", __FUNCTION__);
++#endif
++		return ret;
++	}
++	if ((sta_priv->rc_idx < 0) || (sta_priv->rc_idx >= SSV_RC_MAX_STA)) {
++#ifdef RATE_CONTROL_DEBUG
++		dev_dbg(sc->dev, "%s rc_idx %x illegal \n\r", __FUNCTION__,
++		       sta_priv->rc_idx);
++#endif
++		return ret;
++	}
++	rc_sta = &ssv_rc->sta_rc_info[sta_priv->rc_idx];
++	if (rc_sta->rc_valid == false) {
++#ifdef RATE_CONTROL_DEBUG
++		dev_dbg(sc->dev, "%s rc_valid false \n\r", __FUNCTION__);
++#endif
++		return ret;
++	}
++	spinfo = &rc_sta->spinfo;
++	period = msecs_to_jiffies(RC_PID_REPORT_INTERVAL);
++	if (time_after(jiffies, spinfo->last_report + period)) {
++		ret |= RC_FIRMWARE_REPORT_FLAG;
++		spinfo->last_report = jiffies;
++	}
++	{
++		if (spinfo->monitoring) {
++			if (spinfo->probe_report_flag == 0) {
++				ret |= RC_FIRMWARE_REPORT_FLAG;
++				spinfo->last_report = jiffies;
++				spinfo->probe_report_flag = 1;
++				rateidx = spinfo->real_hw_index;
++			} else if (spinfo->probe_cnt > 0
++				   && spinfo->probe_report_flag) {
++				rateidx =
++				    rc_sta->pinfo.rinfo[spinfo->
++							tmp_rate_idx].rc_index;
++				spinfo->probe_cnt--;
++				if (spinfo->probe_cnt == 0) {
++					ret |= RC_FIRMWARE_REPORT_FLAG;
++					spinfo->last_report = jiffies;
++				}
++			} else
++				rateidx = spinfo->real_hw_index;
++		} else
++			rateidx = spinfo->real_hw_index;
++	}
++	if (rateidx >= RATE_TABLE_SIZE) {
++		dev_err(sc->dev, "rateidx over range\n");
++		return 0;
++	}
++	rc_rate = &ssv_rc->rc_table[rateidx];
++#ifdef RATE_CONTROL_STUPID_DEBUG
++	if (spinfo->monitoring && (spinfo->probe_cnt)) {
++		char string[24];
++		rateControlGetRate(rc_rate->hw_rate_idx, string);
++		dev_dbg(sc->dev, "[RC]Probe rate[%s]\n", string);
++	}
++#endif
++	if (rc_rate == NULL)
++		return ret;
++	if (rc_rate->hw_rate_idx != rates[SSV_DRATE_IDX].count) {
++		rates[0].flags = 0;
++		if (rc_rate->rc_flags & RC_FLAG_SHORT_PREAMBLE)
++			rates[0].flags |= IEEE80211_TX_RC_USE_SHORT_PREAMBLE;
++		if (rc_rate->rc_flags & RC_FLAG_HT) {
++			rates[0].flags |= IEEE80211_TX_RC_MCS;
++			if (rc_rate->rc_flags & RC_FLAG_HT_SGI)
++				rates[0].flags |= IEEE80211_TX_RC_SHORT_GI;
++			if (rc_rate->rc_flags & RC_FLAG_HT_GF)
++				rates[0].flags |= IEEE80211_TX_RC_GREEN_FIELD;
++		}
++		rates[SSV_DRATE_IDX].count = rc_rate->hw_rate_idx;
++		if (do_rts_cts & IEEE80211_TX_RC_USE_CTS_PROTECT) {
++			rates[SSV_CRATE_IDX].count = 0;
++		} else {
++			rc_rate = &ssv_rc->rc_table[rc_rate->ctrl_rate_idx];
++			rates[SSV_CRATE_IDX].count = rc_rate->hw_rate_idx;
++		}
++		ret |= 0x1;
++	}
++	return ret;
++}
++
++void ssv6xxx_rc_hw_reset(struct ssv_softc *sc, int rc_idx, int hwidx)
++{
++	struct ssv_rate_ctrl *ssv_rc = sc->rc;
++	struct ssv_sta_rc_info *rc_sta;
++	u32 rc_hw_reg[] = { ADR_MTX_MIB_WSID0, ADR_MTX_MIB_WSID1 };
++	BUG_ON(rc_idx >= SSV_RC_MAX_STA);
++	rc_sta = &ssv_rc->sta_rc_info[rc_idx];
++	if (hwidx >= 0 && hwidx < SSV_NUM_HW_STA) {
++		rc_sta->rc_wsid = hwidx;
++		dev_dbg(sc->dev, "rc_wsid[%d] rc_idx[%d]\n", rc_sta[rc_idx].rc_wsid,
++		       rc_idx);
++		SMAC_REG_WRITE(sc->sh, rc_hw_reg[hwidx], 0x40000000);
++	} else {
++		rc_sta->rc_wsid = -1;
++	}
++}
++
++#define UPDATE_PHY_INFO_ACK_RATE(_phy_info,_ack_rate_idx) ( _phy_info = (_phy_info&0xfffffc0f)|(_ack_rate_idx<<4))
++int ssv6xxx_rc_update_bmode_ctrl_rate(struct ssv_softc *sc, int rate_tbl_idx,
++				      int ctrl_rate_idx)
++{
++	u32 temp32;
++	struct ssv_hw *sh = sc->sh;
++	u32 addr;
++	addr = sh->hw_pinfo + rate_tbl_idx * 4;
++	ssv_11bgn_rate_table[rate_tbl_idx].ctrl_rate_idx = ctrl_rate_idx;
++	SMAC_REG_READ(sh, addr, &temp32);
++	UPDATE_PHY_INFO_ACK_RATE(temp32, ctrl_rate_idx);
++	SMAC_REG_WRITE(sh, addr, temp32);
++	SMAC_REG_CONFIRM(sh, addr, temp32);
++	return 0;
++}
++
++void ssv6xxx_rc_update_basic_rate(struct ssv_softc *sc, u32 basic_rates)
++{
++	int i;
++	int rate_idx, pre_rate_idx = 0;
++	for (i = 0; i < 4; i++) {
++		if (((basic_rates >> i) & 0x01)) {
++			rate_idx = i;
++			pre_rate_idx = i;
++		} else
++			rate_idx = pre_rate_idx;
++		ssv6xxx_rc_update_bmode_ctrl_rate(sc, i, rate_idx);
++		if (i)
++			ssv6xxx_rc_update_bmode_ctrl_rate(sc, i + 3, rate_idx);
++	}
++}
++
++int ssv6xxx_rate_control_register(void)
++{
++	return ieee80211_rate_control_register(&ssv_rate_ops);
++}
++
++void ssv6xxx_rate_control_unregister(void)
++{
++	ieee80211_rate_control_unregister(&ssv_rate_ops);
++}
++
++void ssv6xxx_rc_rx_data_handler(struct ieee80211_hw *hw, struct sk_buff *skb,
++				u32 rate_index)
++{
++	struct ssv_softc *sc = hw->priv;
++	struct ieee80211_sta *sta;
++	struct ssv_sta_priv_data *ssv_sta_priv;
++	sta = ssv6xxx_find_sta_by_rx_skb(sc, skb);
++	if (sta == NULL) {
++		return;
++	}
++	ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
++	ssv_sta_priv->rx_data_rate = rate_index;
++}
+diff --git a/drivers/net/wireless/ssv6051/smac/ssv_rc.h b/drivers/net/wireless/ssv6051/smac/ssv_rc.h
+new file mode 100644
+index 000000000000..911c182897fa
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/ssv_rc.h
+@@ -0,0 +1,50 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation, either version 3 of the License, or
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _SSV_RC_H_
++#define _SSV_RC_H_
++#include "ssv_rc_common.h"
++#define RC_PID_REPORT_INTERVAL 40
++#define RC_PID_INTERVAL 125
++#define RC_PID_DO_ARITH_RIGHT_SHIFT(x,y) \
++ ((x) < 0 ? -((-(x)) >> (y)) : (x) >> (y))
++#define RC_PID_NORM_OFFSET 3
++#define RC_PID_SMOOTHING_SHIFT 1
++#define RC_PID_SMOOTHING (1 << RC_PID_SMOOTHING_SHIFT)
++#define RC_PID_COEFF_P 15
++#define RC_PID_COEFF_I 15
++#define RC_PID_COEFF_D 5
++#define MAXPROBES 3
++#define SSV_DRATE_IDX (2)
++#define SSV_CRATE_IDX (3)
++
++struct ssv_softc;
++struct ssv_rc_rate *ssv6xxx_rc_get_rate(int rc_index);
++void ssv6xxx_rc_hw_rate_idx(struct ssv_softc *sc,
++			    struct ieee80211_tx_info *info,
++			    struct ssv_rate_info *sr);
++u8 ssv6xxx_rc_hw_rate_update_check(struct sk_buff *skb, struct ssv_softc *sc,
++				   u32 do_rts_cts);
++void ssv6xxx_rc_mac8011_rate_idx(struct ssv_softc *sc, int hw_rate_idx,
++				 struct ieee80211_rx_status *rxs);
++void ssv6xxx_rc_hw_reset(struct ssv_softc *sc, int rc_idx, int hwidx);
++void ssv6xxx_rc_update_basic_rate(struct ssv_softc *sc, u32 basic_rates);
++int ssv6xxx_rate_control_register(void);
++void ssv6xxx_rate_control_unregister(void);
++void ssv6xxx_rc_rx_data_handler(struct ieee80211_hw *hw, struct sk_buff *skb,
++				u32 rate_index);
++int pide_frame_duration(size_t len, int rate, int short_preamble, int flags);
++#endif
+diff --git a/drivers/net/wireless/ssv6051/smac/ssv_rc_common.h b/drivers/net/wireless/ssv6051/smac/ssv_rc_common.h
+new file mode 100644
+index 000000000000..13f3fdd8072b
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/smac/ssv_rc_common.h
+@@ -0,0 +1,175 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation, either version 3 of the License, or
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _SSV_RC_COM_H_
++#define _SSV_RC_COM_H_
++#define SSV_RC_MAX_STA 8
++#define MCS_GROUP_RATES 8
++#define SSV_HT_RATE_MAX 8
++#define TDIFS 34
++#define TSLOT 9
++#define SSV_RC_MAX_HARDWARE_SUPPORT 2
++#define RC_FIRMWARE_REPORT_FLAG 0x80
++#define RC_FLAG_INVALID 0x00000001
++#define RC_FLAG_LEGACY 0x00000002
++#define RC_FLAG_HT 0x00000004
++#define RC_FLAG_HT_SGI 0x00000008
++#define RC_FLAG_HT_GF 0x00000010
++#define RC_FLAG_SHORT_PREAMBLE 0x00000020
++enum ssv6xxx_rc_phy_type {
++	WLAN_RC_PHY_CCK,
++	WLAN_RC_PHY_OFDM,
++	WLAN_RC_PHY_HT_20_SS_LGI,
++	WLAN_RC_PHY_HT_20_SS_SGI,
++	WLAN_RC_PHY_HT_20_SS_GF,
++};
++#define RATE_TABLE_SIZE 39
++#define RC_STA_VALID 0x00000001
++#define RC_STA_CAP_HT 0x00000002
++#define RC_STA_CAP_GF 0x00000004
++#define RC_STA_CAP_SGI_20 0x00000008
++#define RC_STA_CAP_SHORT_PREAMBLE 0x00000010
++#define SSV62XX_G_RATE_INDEX 7
++#define SSV62XX_RATE_MCS_INDEX 15
++#define SSV62XX_RATE_MCS_LGI_INDEX 15
++#define SSV62XX_RATE_MCS_SGI_INDEX 23
++#define SSV62XX_RATE_MCS_GREENFIELD_INDEX 31
++enum ssv_rc_rate_type {
++	RC_TYPE_B_ONLY = 0,
++	RC_TYPE_LEGACY_GB,
++	RC_TYPE_SGI_20,
++	RC_TYPE_LGI_20,
++	RC_TYPE_HT_SGI_20,
++	RC_TYPE_HT_LGI_20,
++	RC_TYPE_HT_GF,
++	RC_TYPE_MAX,
++};
++struct ssv_rate_info {
++	int crate_kbps;
++	int crate_hw_idx;
++	int drate_kbps;
++	int drate_hw_idx;
++	u32 d_flags;
++	u32 c_flags;
++};
++struct ssv_rc_rate {
++	u32 rc_flags;
++	u16 phy_type;
++	u32 rate_kbps;
++	u8 dot11_rate_idx;
++	u8 ctrl_rate_idx;
++	u8 hw_rate_idx;
++	u8 arith_shift;
++	u8 target_pf;
++};
++struct rc_pid_sta_info {
++	unsigned long last_sample;
++	unsigned long last_report;
++	u16 tx_num_failed;
++	u16 tx_num_xmit;
++	u8 probe_report_flag;
++	u8 probe_wating_times;
++	u8 real_hw_index;
++	int txrate_idx;
++	u8 last_pf;
++	s32 err_avg_sc;
++	int last_dlr;
++	u8 feedback_probes;
++	u8 monitoring;
++	u8 oldrate;
++	u8 tmp_rate_idx;
++	u8 probe_cnt;
++};
++struct rc_pid_rateinfo {
++	u16 rc_index;
++	u16 index;
++	s32 diff;
++	u16 perfect_tx_time;
++	u32 throughput;
++	unsigned long this_attempt;
++	unsigned long this_success;
++	unsigned long this_fail;
++	u64 attempt;
++	u64 success;
++	u64 fail;
++};
++struct rc_pid_info {
++	unsigned int target;
++	int oldrate;
++	struct rc_pid_rateinfo rinfo[12];
++};
++struct mcs_group {
++	unsigned int duration[MCS_GROUP_RATES];
++};
++struct minstrel_rate_stats {
++	u16 rc_index;
++	unsigned int attempts, last_attempts;
++	unsigned int success, last_success;
++	u64 att_hist, succ_hist;
++	unsigned int cur_tp;
++	unsigned int cur_prob, probability;
++	unsigned int retry_count;
++	unsigned int retry_count_rtscts;
++	u8 sample_skipped;
++};
++struct minstrel_mcs_group_data {
++	u8 index;
++	u8 column;
++	unsigned int max_tp_rate;
++	unsigned int max_tp_rate2;
++	unsigned int max_prob_rate;
++	struct minstrel_rate_stats rates[MCS_GROUP_RATES];
++};
++struct ssv62xx_ht {
++	unsigned int ampdu_len;
++	unsigned int ampdu_packets;
++	unsigned int avg_ampdu_len;
++	unsigned int max_tp_rate;
++	unsigned int max_tp_rate2;
++	unsigned int max_prob_rate;
++	int first_try_count;
++	int second_try_count;
++	int other_try_count;
++	unsigned long stats_update;
++	unsigned int overhead;
++	unsigned int overhead_rtscts;
++	unsigned int total_packets;
++	unsigned int sample_packets;
++	u8 sample_wait;
++	u8 sample_tries;
++	u8 sample_count;
++	u8 sample_slow;
++	struct minstrel_mcs_group_data groups;
++};
++struct ssv_sta_rc_info {
++	u8 rc_valid;
++	u8 rc_type;
++	u8 rc_num_rate;
++	s8 rc_wsid;
++	u8 ht_rc_type;
++	u8 is_ht;
++	u32 rc_supp_rates;
++	u32 ht_supp_rates;
++	struct rc_pid_info pinfo;
++	struct rc_pid_sta_info spinfo;
++	struct ssv62xx_ht ht;
++};
++struct ssv_rate_ctrl {
++	struct ssv_rc_rate *rc_table;
++	struct ssv_sta_rc_info sta_rc_info[SSV_RC_MAX_STA];
++};
++#define HT_RC_UPDATE_INTERVAL 1000
++#endif
+diff --git a/drivers/net/wireless/ssv6051/ssv6051-generic-wlan.c b/drivers/net/wireless/ssv6051/ssv6051-generic-wlan.c
+new file mode 100644
+index 000000000000..10a9a77081db
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/ssv6051-generic-wlan.c
+@@ -0,0 +1,76 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation, either version 3 of the License, or
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <linux/irq.h>
++#include <linux/version.h>
++#include <linux/module.h>
++#include <linux/vmalloc.h>
++#include <linux/gpio.h>
++#include <linux/mmc/host.h>
++#include <linux/delay.h>
++#include <linux/regulator/consumer.h>
++#include <asm/io.h>
++#include <linux/printk.h>
++#include <linux/err.h>
++
++static int g_wifidev_registered = 0;
++extern int ssvdevice_init(void);
++extern void ssvdevice_exit(void);
++extern int ssv6xxx_get_dev_status(void);
++
++static __init int ssv_init_module(void)
++{
++	int ret = 0;
++	int time = 5;
++
++	msleep(120);
++
++	g_wifidev_registered = 1;
++	ret = ssvdevice_init();
++
++	while(time-- > 0){
++		msleep(500);
++		if(ssv6xxx_get_dev_status() == 1)
++			break;
++		pr_info("%s : Retry to carddetect\n",__func__);
++	}
++
++	return ret;
++
++}
++static __exit void ssv_exit_module(void)
++{
++
++	if (g_wifidev_registered)
++    {
++        ssvdevice_exit();
++        msleep(50);
++        g_wifidev_registered = 0;
++    }
++
++    return;
++
++}
++
++module_init(ssv_init_module);
++module_exit(ssv_exit_module);
++
++MODULE_AUTHOR("iComm Semiconductor Co., Ltd");
++MODULE_FIRMWARE("ssv*-sw.bin");
++MODULE_FIRMWARE("ssv*-wifi.cfg");
++MODULE_DESCRIPTION("Shared library for SSV wireless LAN cards.");
++MODULE_LICENSE("Dual BSD/GPL");
++
+diff --git a/drivers/net/wireless/ssv6051/ssvdevice/ssv_cmd.c b/drivers/net/wireless/ssv6051/ssvdevice/ssv_cmd.c
+new file mode 100644
+index 000000000000..503df1ea6dc3
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/ssvdevice/ssv_cmd.c
+@@ -0,0 +1,1765 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation, either version 3 of the License, or
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <linux/kernel.h>
++#include <linux/version.h>
++#include <linux/export.h>
++#include <linux/platform_device.h>
++#include <linux/string.h>
++#include <ssv6200_reg.h>
++#include <ssv6200.h>
++#include <hci/hctrl.h>
++#include <smac/dev.h>
++#include "ssv_cmd.h"
++#include <ssv_version.h>
++#include <ssv6200_configuration.h>
++#define SSV_CMD_PRINTF()
++struct ssv6xxx_dev_table {
++	u32 address;
++	u32 val;
++};
++struct ssv6xxx_debug {
++	struct device *dev;
++	struct platform_device *pdev;
++	struct ssv6xxx_hwif_ops *ifops;
++};
++static struct ssv6xxx_debug *ssv6xxx_debug_ifops;
++static char sg_cmd_buffer[CLI_BUFFER_SIZE + 1];
++static char *sg_argv[CLI_ARG_SIZE];
++static u32 sg_argc;
++extern char *ssv6xxx_result_buf;
++#if defined (CONFIG_ARM64) || defined (__x86_64__)
++u64 ssv6xxx_ifdebug_info[3] = { 0, 0, 0 };
++#else
++u32 ssv6xxx_ifdebug_info[3] = { 0, 0, 0 };
++#endif
++EXPORT_SYMBOL(ssv6xxx_ifdebug_info);
++struct sk_buff *ssvdevice_skb_alloc(s32 len)
++{
++	struct sk_buff *skb;
++	skb = __dev_alloc_skb(len + SSV6200_ALLOC_RSVD, GFP_KERNEL);
++	if (skb != NULL) {
++		skb_put(skb, 0x20);
++		skb_pull(skb, 0x20);
++	}
++	return skb;
++}
++
++void ssvdevice_skb_free(struct sk_buff *skb)
++{
++	dev_kfree_skb_any(skb);
++}
++
++static int ssv_cmd_help(int argc, char *argv[])
++{
++	extern struct ssv_cmd_table cmd_table[];
++	struct ssv_cmd_table *sc_tbl;
++	char tmpbf[161];
++	int total_cmd = 0;
++	{
++		sprintf(ssv6xxx_result_buf, "Usage:\n");
++		for (sc_tbl = &cmd_table[3]; sc_tbl->cmd; sc_tbl++) {
++			sprintf(tmpbf, "%-20s\t\t%s\n", sc_tbl->cmd,
++				sc_tbl->usage);
++			strcat(ssv6xxx_result_buf, tmpbf);
++			total_cmd++;
++		}
++		sprintf(tmpbf,
++			"Total CMDs: %d\n\nType cli help [CMD] for more detail command.\n\n",
++			total_cmd);
++		strcat(ssv6xxx_result_buf, tmpbf);
++	}
++	return 0;
++}
++
++static int ssv_cmd_reg(int argc, char *argv[])
++{
++	u32 addr, value, count;
++	char tmpbf[64], *endp;
++	int s;
++	if (argc == 4 && strcmp(argv[1], "w") == 0) {
++		addr = simple_strtoul(argv[2], &endp, 16);
++		value = simple_strtoul(argv[3], &endp, 16);
++		if (SSV_REG_WRITE1(ssv6xxx_debug_ifops, addr, value)) ;
++		sprintf(ssv6xxx_result_buf, " => write [0x%08x]: 0x%08x\n",
++			addr, value);
++		return 0;
++	} else if ((argc == 4 || argc == 3) && strcmp(argv[1], "r") == 0) {
++		count = (argc == 3) ? 1 : simple_strtoul(argv[3], &endp, 10);
++		addr = simple_strtoul(argv[2], &endp, 16);
++		sprintf(ssv6xxx_result_buf, "ADDRESS: 0x%08x\n", addr);
++		for (s = 0; s < count; s++, addr += 4) {
++			if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, &value)) ;
++			sprintf(tmpbf, "%08x ", value);
++			strcat(ssv6xxx_result_buf, tmpbf);
++			if (((s + 1) & 0x07) == 0)
++				strcat(ssv6xxx_result_buf, "\n");
++		}
++		strcat(ssv6xxx_result_buf, "\n");
++		return 0;
++	} else {
++		sprintf(tmpbf, "reg [r|w] [address] [value|word-count]\n\n");
++		strcat(ssv6xxx_result_buf, tmpbf);
++		return 0;
++	}
++	return -1;
++}
++
++struct ssv6xxx_cfg ssv_cfg;
++EXPORT_SYMBOL(ssv_cfg);
++static int __string2u32(u8 * u8str, void *val, u32 arg)
++{
++	char *endp;
++	int base = 10;
++	if (u8str[0] == '0' && ((u8str[1] == 'x') || (u8str[1] == 'X')))
++		base = 16;
++	*(u32 *) val = simple_strtoul(u8str, &endp, base);
++	return 0;
++}
++
++static int __string2flag32(u8 * flag_str, void *flag, u32 arg)
++{
++	u32 *val = (u32 *) flag;
++	if (arg >= (sizeof(u32) << 3))
++		return -1;
++	if (strcmp(flag_str, "on") == 0) {
++		*val |= (1 << arg);
++		return 0;
++	}
++	if (strcmp(flag_str, "off") == 0) {
++		*val &= ~(1 << arg);
++		return 0;
++	}
++	return -1;
++}
++
++static int __string2mac(u8 * mac_str, void *val, u32 arg)
++{
++	int s, macaddr[6];
++	u8 *mac = (u8 *) val;
++	s = sscanf(mac_str, "%02x:%02x:%02x:%02x:%02x:%02x",
++		   &macaddr[0], &macaddr[1], &macaddr[2],
++		   &macaddr[3], &macaddr[4], &macaddr[5]);
++	if (s != 6)
++		return -1;
++	mac[0] = (u8) macaddr[0], mac[1] = (u8) macaddr[1];
++	mac[2] = (u8) macaddr[2], mac[3] = (u8) macaddr[3];
++	mac[4] = (u8) macaddr[4], mac[5] = (u8) macaddr[5];
++	return 0;
++}
++
++static int __string2str(u8 * path, void *val, u32 arg)
++{
++	u8 *temp = (u8 *) val;
++	sprintf(temp, "%s", path);
++	return 0;
++}
++
++static int __string2configuration(u8 * mac_str, void *val, u32 arg)
++{
++	unsigned int address, value;
++	int i;
++	i = sscanf(mac_str, "%08x:%08x", &address, &value);
++	if (i != 2)
++		return -1;
++	for (i = 0; i < EXTERNEL_CONFIG_SUPPORT; i++) {
++		if (ssv_cfg.configuration[i][0] == 0x0) {
++			ssv_cfg.configuration[i][0] = address;
++			ssv_cfg.configuration[i][1] = value;
++			return 0;
++		}
++	}
++	return 0;
++}
++
++struct ssv6xxx_cfg_cmd_table cfg_cmds[] = {
++	{"hw_mac", (void *)&ssv_cfg.maddr[0][0], 0, __string2mac},
++	{"hw_mac_2", (void *)&ssv_cfg.maddr[1][0], 0, __string2mac},
++	{"def_chan", (void *)&ssv_cfg.def_chan, 0, __string2u32},
++	{"hw_cap_ht", (void *)&ssv_cfg.hw_caps, 0, __string2flag32},
++	{"hw_cap_gf", (void *)&ssv_cfg.hw_caps, 1, __string2flag32},
++	{"hw_cap_2ghz", (void *)&ssv_cfg.hw_caps, 2, __string2flag32},
++	{"hw_cap_5ghz", (void *)&ssv_cfg.hw_caps, 3, __string2flag32},
++	{"hw_cap_security", (void *)&ssv_cfg.hw_caps, 4, __string2flag32},
++	{"hw_cap_sgi_20", (void *)&ssv_cfg.hw_caps, 5, __string2flag32},
++	{"hw_cap_sgi_40", (void *)&ssv_cfg.hw_caps, 6, __string2flag32},
++	{"hw_cap_ap", (void *)&ssv_cfg.hw_caps, 7, __string2flag32},
++	{"hw_cap_p2p", (void *)&ssv_cfg.hw_caps, 8, __string2flag32},
++	{"hw_cap_ampdu_rx", (void *)&ssv_cfg.hw_caps, 9, __string2flag32},
++	{"hw_cap_ampdu_tx", (void *)&ssv_cfg.hw_caps, 10, __string2flag32},
++	{"hw_cap_tdls", (void *)&ssv_cfg.hw_caps, 11, __string2flag32},
++	{"use_wpa2_only", (void *)&ssv_cfg.use_wpa2_only, 0, __string2u32},
++	{"wifi_tx_gain_level_gn", (void *)&ssv_cfg.wifi_tx_gain_level_gn, 0,
++	 __string2u32},
++	{"wifi_tx_gain_level_b", (void *)&ssv_cfg.wifi_tx_gain_level_b, 0,
++	 __string2u32},
++	{"rssi_ctl", (void *)&ssv_cfg.rssi_ctl, 0, __string2u32},
++	{"xtal_clock", (void *)&ssv_cfg.crystal_type, 0, __string2u32},
++	{"volt_regulator", (void *)&ssv_cfg.volt_regulator, 0, __string2u32},
++	{"force_chip_identity", (void *)&ssv_cfg.force_chip_identity, 0,
++	 __string2u32},
++	{"firmware_path", (void *)&ssv_cfg.firmware_path[0], 0, __string2str},
++	{"flash_bin_path", (void *)&ssv_cfg.flash_bin_path[0], 0, __string2str},
++	{"mac_address_path", (void *)&ssv_cfg.mac_address_path[0], 0,
++	 __string2str},
++	{"mac_output_path", (void *)&ssv_cfg.mac_output_path[0], 0,
++	 __string2str},
++	{"ignore_efuse_mac", (void *)&ssv_cfg.ignore_efuse_mac, 0,
++	 __string2u32},
++	{"mac_address_mode", (void *)&ssv_cfg.mac_address_mode, 0,
++	 __string2u32},
++	{"sr_bhvr", (void *)&ssv_cfg.sr_bhvr, 0, __string2u32},
++	{"register", NULL, 0, __string2configuration},
++	{NULL, NULL, 0, NULL},
++};
++
++EXPORT_SYMBOL(cfg_cmds);
++static int ssv_cmd_cfg(int argc, char *argv[])
++{
++	char temp_buf[64];
++	int s;
++	if (argc == 2 && strcmp(argv[1], "reset") == 0) {
++		memset(&ssv_cfg, 0, sizeof(ssv_cfg));
++		return 0;
++	} else if (argc == 2 && strcmp(argv[1], "show") == 0) {
++		strcpy(ssv6xxx_result_buf, ">> ssv6xxx config:\n");
++		sprintf(temp_buf, "    hw_caps = 0x%08x\n", ssv_cfg.hw_caps);
++		strcat(ssv6xxx_result_buf, temp_buf);
++		sprintf(temp_buf, "    def_chan = %d\n", ssv_cfg.def_chan);
++		strcat(ssv6xxx_result_buf, temp_buf);
++		sprintf(temp_buf, "    wifi_tx_gain_level_gn = %d\n",
++			ssv_cfg.wifi_tx_gain_level_gn);
++		strcat(ssv6xxx_result_buf, temp_buf);
++		sprintf(temp_buf, "    wifi_tx_gain_level_b = %d\n",
++			ssv_cfg.wifi_tx_gain_level_b);
++		strcat(ssv6xxx_result_buf, temp_buf);
++		sprintf(temp_buf, "    rssi_ctl = %d\n", ssv_cfg.rssi_ctl);
++		strcat(ssv6xxx_result_buf, temp_buf);
++		sprintf(temp_buf, "    sr_bhvr = %d\n", ssv_cfg.sr_bhvr);
++		strcat(ssv6xxx_result_buf, temp_buf);
++		sprintf(temp_buf, "    sta-mac = %02x:%02x:%02x:%02x:%02x:%02x",
++			ssv_cfg.maddr[0][0], ssv_cfg.maddr[0][1],
++			ssv_cfg.maddr[0][2], ssv_cfg.maddr[0][3],
++			ssv_cfg.maddr[0][4], ssv_cfg.maddr[0][5]);
++		strcat(ssv6xxx_result_buf, temp_buf);
++		strcat(ssv6xxx_result_buf, "\n");
++		return 0;
++	}
++	if (argc != 4)
++		return -1;
++	for (s = 0; cfg_cmds[s].cfg_cmd != NULL; s++) {
++		if (strcmp(cfg_cmds[s].cfg_cmd, argv[1]) == 0) {
++			cfg_cmds[s].translate_func(argv[3],
++						   cfg_cmds[s].var,
++						   cfg_cmds[s].arg);
++			strcpy(ssv6xxx_result_buf, "");
++			return 0;
++		}
++	}
++	return -1;
++}
++
++void *ssv_dbg_phy_table = NULL;
++EXPORT_SYMBOL(ssv_dbg_phy_table);
++u32 ssv_dbg_phy_len = 0;
++EXPORT_SYMBOL(ssv_dbg_phy_len);
++void *ssv_dbg_rf_table = NULL;
++EXPORT_SYMBOL(ssv_dbg_rf_table);
++u32 ssv_dbg_rf_len = 0;
++EXPORT_SYMBOL(ssv_dbg_rf_len);
++struct ssv_softc *ssv_dbg_sc = NULL;
++EXPORT_SYMBOL(ssv_dbg_sc);
++struct ssv6xxx_hci_ctrl *ssv_dbg_ctrl_hci = NULL;
++EXPORT_SYMBOL(ssv_dbg_ctrl_hci);
++struct Dump_Sta_Info {
++	char *dump_buf;
++	int sta_idx;
++};
++static void _dump_sta_info(struct ssv_softc *sc,
++			   struct ssv_vif_info *vif_info,
++			   struct ssv_sta_info *sta_info, void *param)
++{
++	char tmpbf[128];
++	struct Dump_Sta_Info *dump_sta_info = (struct Dump_Sta_Info *)param;
++	struct ssv_sta_priv_data *priv_sta =
++	    (struct ssv_sta_priv_data *)sta_info->sta->drv_priv;
++	if ((sta_info->s_flags & STA_FLAG_VALID) == 0)
++		sprintf(tmpbf,
++			"        Station %d: %d is not valid\n",
++			dump_sta_info->sta_idx, priv_sta->sta_idx);
++	else
++		sprintf(tmpbf,
++			"        Station %d: %d\n"
++			"             Address: %02X:%02X:%02X:%02X:%02X:%02X\n"
++			"             WISD: %d\n"
++			"             AID: %d\n"
++			"             Sleep: %d\n",
++			dump_sta_info->sta_idx, priv_sta->sta_idx,
++			sta_info->sta->addr[0], sta_info->sta->addr[1],
++			sta_info->sta->addr[2], sta_info->sta->addr[3],
++			sta_info->sta->addr[4], sta_info->sta->addr[5],
++			sta_info->hw_wsid, sta_info->aid, sta_info->sleeping);
++	dump_sta_info->sta_idx++;
++	strcat(dump_sta_info->dump_buf, tmpbf);
++}
++
++void ssv6xxx_dump_sta_info(struct ssv_softc *sc, char *target_buf)
++{
++	int j;
++	char tmpbf[128];
++	struct Dump_Sta_Info dump_sta_info = { target_buf, 0 };
++	sprintf(tmpbf, "  >>>> bcast queue len[%d]\n", sc->bcast_txq.cur_qsize);
++	strcat(target_buf, tmpbf);
++	for (j = 0; j < SSV6200_MAX_VIF; j++) {
++		struct ieee80211_vif *vif = sc->vif_info[j].vif;
++		struct ssv_vif_priv_data *priv_vif;
++		struct ssv_sta_priv_data *sta_priv_iter;
++		if (vif == NULL) {
++			sprintf(tmpbf, "    VIF: %d is not used.\n", j);
++			strcat(target_buf, tmpbf);
++			continue;
++		}
++		sprintf(tmpbf,
++			"    VIF: %d - [%02X:%02X:%02X:%02X:%02X:%02X] type[%d] p2p[%d]\n",
++			j, vif->addr[0], vif->addr[1], vif->addr[2],
++			vif->addr[3], vif->addr[4], vif->addr[5], vif->type,
++			vif->p2p);
++		strcat(target_buf, tmpbf);
++		priv_vif = (struct ssv_vif_priv_data *)(vif->drv_priv);
++		list_for_each_entry(sta_priv_iter, &priv_vif->sta_list, list) {
++			if ((sta_priv_iter->sta_info->
++			     s_flags & STA_FLAG_VALID) == 0) {
++				sprintf(tmpbf, "    VIF: %d  is not valid.\n",
++					j);
++				strcat(target_buf, tmpbf);
++				continue;
++			}
++			_dump_sta_info(sc, &sc->vif_info[priv_vif->vif_idx],
++				       sta_priv_iter->sta_info, &dump_sta_info);
++		}
++	}
++}
++
++static int ssv_cmd_sta(int argc, char *argv[])
++{
++	if (argc >= 2 && strcmp(argv[1], "show") == 0)
++		ssv6xxx_dump_sta_info(ssv_dbg_sc, ssv6xxx_result_buf);
++	else
++		strcat(ssv6xxx_result_buf, "sta show\n\n");
++	return 0;
++}
++
++static int ssv_cmd_dump(int argc, char *argv[])
++{
++	u32 addr, regval;
++	char tmpbf[64];
++	int s;
++	if (!ssv6xxx_result_buf) {
++		pr_warn("ssv6xxx_result_buf = NULL!!\n");
++		return -1;
++	}
++	if (argc != 2) {
++		sprintf(tmpbf,
++			"dump [wsid|decision|phy-info|phy-reg|rf-reg]\n");
++		strcat(ssv6xxx_result_buf, tmpbf);
++		return 0;
++	}
++	if (strcmp(argv[1], "wsid") == 0) {
++		const u32 reg_wsid[] = { ADR_WSID0, ADR_WSID1 };
++		const u32 reg_wsid_tid0[] =
++		    { ADR_WSID0_TID0_RX_SEQ, ADR_WSID1_TID0_RX_SEQ };
++		const u32 reg_wsid_tid7[] =
++		    { ADR_WSID0_TID7_RX_SEQ, ADR_WSID1_TID7_RX_SEQ };
++		const u8 *op_mode_str[] = { "STA", "AP", "AD-HOC", "WDS" };
++		const u8 *ht_mode_str[] =
++		    { "Non-HT", "HT-MF", "HT-GF", "RSVD" };
++		for (s = 0; s < SSV_NUM_HW_STA; s++) {
++			if (SSV_REG_READ1
++			    (ssv6xxx_debug_ifops, reg_wsid[s], &regval)) ;
++			sprintf(tmpbf,
++				"==>WSID[%d]\n\tvalid[%d] qos[%d] op_mode[%s] ht_mode[%s]\n",
++				s, regval & 0x1, (regval >> 1) & 0x1,
++				op_mode_str[((regval >> 2) & 3)],
++				ht_mode_str[((regval >> 4) & 3)]);
++			strcat(ssv6xxx_result_buf, tmpbf);
++			if (SSV_REG_READ1
++			    (ssv6xxx_debug_ifops, reg_wsid[s] + 4, &regval)) ;
++			sprintf(tmpbf, "\tMAC[%02x:%02x:%02x:%02x:",
++				(regval & 0xff), ((regval >> 8) & 0xff),
++				((regval >> 16) & 0xff),
++				((regval >> 24) & 0xff));
++			strcat(ssv6xxx_result_buf, tmpbf);
++			if (SSV_REG_READ1
++			    (ssv6xxx_debug_ifops, reg_wsid[s] + 8, &regval)) ;
++			sprintf(tmpbf, "%02x:%02x]\n", (regval & 0xff),
++				((regval >> 8) & 0xff));
++			strcat(ssv6xxx_result_buf, tmpbf);
++			for (addr = reg_wsid_tid0[s]; addr <= reg_wsid_tid7[s];
++			     addr += 4) {
++				if (SSV_REG_READ1
++				    (ssv6xxx_debug_ifops, addr, &regval)) ;
++				sprintf(tmpbf, "\trx_seq%d[%d]\n",
++					((addr - reg_wsid_tid0[s]) >> 2),
++					((regval) & 0xffff));
++				strcat(ssv6xxx_result_buf, tmpbf);
++			}
++		}
++		return 0;
++	}
++	if (strcmp(argv[1], "decision") == 0) {
++		strcpy(ssv6xxx_result_buf, ">> Decision Table:\n");
++		for (s = 0, addr = ADR_MRX_FLT_TB0; s < 16; s++, addr += 4) {
++			if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, &regval)) ;
++			sprintf(tmpbf, "   [%d]: ADDR[0x%08x] = 0x%08x\n",
++				s, addr, regval);
++			strcat(ssv6xxx_result_buf, tmpbf);
++		}
++		strcat(ssv6xxx_result_buf, "\n\n>> Decision Mask:\n");
++		for (s = 0, addr = ADR_MRX_FLT_EN0; s < 9; s++, addr += 4) {
++			if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, &regval)) ;
++			sprintf(tmpbf, "   [%d]: ADDR[0x%08x] = 0x%08x\n",
++				s, addr, regval);
++			strcat(ssv6xxx_result_buf, tmpbf);
++		}
++		strcat(ssv6xxx_result_buf, "\n\n");
++		return 0;
++	}
++	if (strcmp(argv[1], "phy-info") == 0) {
++		return 0;
++	}
++	if (strcmp(argv[1], "phy-reg") == 0) {
++		struct ssv6xxx_dev_table *raw;
++		raw = (struct ssv6xxx_dev_table *)ssv_dbg_phy_table;
++		strcpy(ssv6xxx_result_buf, ">> PHY Register Table:\n");
++		for (s = 0; s < ssv_dbg_phy_len; s++, raw++) {
++			if (SSV_REG_READ1
++			    (ssv6xxx_debug_ifops, raw->address, &regval)) ;
++			sprintf(tmpbf, "   ADDR[0x%08x] = 0x%08x\n",
++				raw->address, regval);
++			strcat(ssv6xxx_result_buf, tmpbf);
++		}
++		strcat(ssv6xxx_result_buf, "\n\n");
++		return 0;
++	}
++	if (strcmp(argv[1], "rf-reg") == 0) {
++		struct ssv6xxx_dev_table *raw;
++		raw = (struct ssv6xxx_dev_table *)ssv_dbg_rf_table;
++		strcpy(ssv6xxx_result_buf, ">> RF Register Table:\n");
++		for (s = 0; s < ssv_dbg_rf_len; s++, raw++) {
++			if (SSV_REG_READ1
++			    (ssv6xxx_debug_ifops, raw->address, &regval)) ;
++			sprintf(tmpbf, "   ADDR[0x%08x] = 0x%08x\n",
++				raw->address, regval);
++			strcat(ssv6xxx_result_buf, tmpbf);
++		}
++		strcat(ssv6xxx_result_buf, "\n\n");
++		return 0;
++	}
++	return -1;
++}
++
++static int ssv_cmd_irq(int argc, char *argv[])
++{
++	char *endp;
++	u32 irq_sts;
++	if (argc >= 3 && strcmp(argv[1], "set") == 0) {
++		if (strcmp(argv[2], "mask") == 0 && argc == 4) {
++			irq_sts = simple_strtoul(argv[3], &endp, 16);
++			if (!ssv6xxx_debug_ifops->ifops->irq_setmask) {
++				sprintf(ssv6xxx_result_buf,
++					"The interface doesn't provide irq_setmask operation.\n");
++				return 0;
++			}
++			ssv6xxx_debug_ifops->ifops->
++			    irq_setmask(ssv6xxx_debug_ifops->dev, irq_sts);
++			sprintf(ssv6xxx_result_buf,
++				"set sdio irq mask to 0x%08x\n", irq_sts);
++			return 0;
++		}
++		if (strcmp(argv[2], "enable") == 0) {
++			if (!ssv6xxx_debug_ifops->ifops->irq_enable) {
++				sprintf(ssv6xxx_result_buf,
++					"The interface doesn't provide irq_enable operation.\n");
++				return 0;
++			}
++			ssv6xxx_debug_ifops->ifops->
++			    irq_enable(ssv6xxx_debug_ifops->dev);
++			strcpy(ssv6xxx_result_buf, "enable sdio irq.\n");
++			return 0;
++		}
++		if (strcmp(argv[2], "disable") == 0) {
++			if (!ssv6xxx_debug_ifops->ifops->irq_disable) {
++				sprintf(ssv6xxx_result_buf,
++					"The interface doesn't provide irq_disable operation.\n");
++				return 0;
++			}
++			ssv6xxx_debug_ifops->ifops->
++			    irq_disable(ssv6xxx_debug_ifops->dev, false);
++			strcpy(ssv6xxx_result_buf, "disable sdio irq.\n");
++			return 0;
++		}
++		return -1;
++	} else if (argc == 3 && strcmp(argv[1], "get") == 0) {
++		if (strcmp(argv[2], "mask") == 0) {
++			if (!ssv6xxx_debug_ifops->ifops->irq_getmask) {
++				sprintf(ssv6xxx_result_buf,
++					"The interface doesn't provide irq_getmask operation.\n");
++				return 0;
++			}
++			ssv6xxx_debug_ifops->ifops->
++			    irq_getmask(ssv6xxx_debug_ifops->dev, &irq_sts);
++			sprintf(ssv6xxx_result_buf,
++				"sdio irq mask: 0x%08x, int_mask=0x%08x\n",
++				irq_sts, ssv_dbg_ctrl_hci->int_mask);
++			return 0;
++		}
++		if (strcmp(argv[2], "status") == 0) {
++			if (!ssv6xxx_debug_ifops->ifops->irq_getstatus) {
++				sprintf(ssv6xxx_result_buf,
++					"The interface doesn't provide irq_getstatus operation.\n");
++				return 0;
++			}
++			ssv6xxx_debug_ifops->ifops->
++			    irq_getstatus(ssv6xxx_debug_ifops->dev, &irq_sts);
++			sprintf(ssv6xxx_result_buf, "sdio irq status: 0x%08x\n",
++				irq_sts);
++			return 0;
++		}
++		return -1;
++	} else {
++		sprintf(ssv6xxx_result_buf,
++			"irq [set|get] [mask|enable|disable|status]\n");
++	}
++	return 0;
++}
++
++static int ssv_cmd_mac(int argc, char *argv[])
++{
++	char temp_str[128], *endp;
++	u32 s;
++	int i;
++	if (argc == 3 && !strcmp(argv[1], "wsid") && !strcmp(argv[2], "show")) {
++		for (s = 0; s < SSV_NUM_HW_STA; s++) {
++		}
++		return 0;
++	} else if (argc == 3 && !strcmp(argv[1], "rx")) {
++		if (!strcmp(argv[2], "enable")) {
++			ssv_dbg_sc->dbg_rx_frame = 1;
++		} else {
++			ssv_dbg_sc->dbg_rx_frame = 0;
++		}
++		sprintf(temp_str, "  dbg_rx_frame %d\n",
++			ssv_dbg_sc->dbg_rx_frame);
++		strcat(ssv6xxx_result_buf, temp_str);
++		return 0;
++	} else if (argc == 3 && !strcmp(argv[1], "tx")) {
++		if (!strcmp(argv[2], "enable")) {
++			ssv_dbg_sc->dbg_tx_frame = 1;
++		} else {
++			ssv_dbg_sc->dbg_tx_frame = 0;
++		}
++		sprintf(temp_str, "  dbg_tx_frame %d\n",
++			ssv_dbg_sc->dbg_tx_frame);
++		strcat(ssv6xxx_result_buf, temp_str);
++		return 0;
++	} else if (argc == 3 && !strcmp(argv[1], "rxq")
++		   && !strcmp(argv[2], "show")) {
++		sprintf(temp_str, ">> MAC RXQ: (%s)\n    cur_qsize=%d\n",
++			((ssv_dbg_sc->
++			  sc_flags & SC_OP_OFFCHAN) ? "off channel" :
++			 "on channel"), ssv_dbg_sc->rx.rxq_count);
++		strcat(ssv6xxx_result_buf, temp_str);
++		return 0;
++	} else if (argc == 4 && !strcmp(argv[1], "set")
++		   && !strcmp(argv[2], "rate")) {
++		if (strcmp(argv[3], "auto") == 0) {
++			ssv_dbg_sc->sc_flags &= ~SC_OP_FIXED_RATE;
++			return 0;
++		}
++		i = simple_strtoul(argv[3], &endp, 10);
++		if (i < 0 || i > 38) {
++			strcpy(ssv6xxx_result_buf, " Invalid rat index !!\n");
++			return -1;
++		}
++		ssv_dbg_sc->max_rate_idx = i;
++		ssv_dbg_sc->sc_flags |= SC_OP_FIXED_RATE;
++		sprintf(temp_str, " Set rate to index %d\n", i);
++		strcat(ssv6xxx_result_buf, temp_str);
++		return 0;
++	} else if (argc == 3 && !strcmp(argv[1], "get")
++		   && !strcmp(argv[2], "rate")) {
++		if (ssv_dbg_sc->sc_flags & SC_OP_FIXED_RATE)
++			sprintf(temp_str, " Current Rate Index: %d\n",
++				ssv_dbg_sc->max_rate_idx);
++		else
++			sprintf(temp_str, "  Current Rate Index: auto\n");
++		strcpy(ssv6xxx_result_buf, temp_str);
++		return 0;
++	} else {
++		sprintf(temp_str, "mac [security|wsid|rxq]  [show]\n");
++		strcat(ssv6xxx_result_buf, temp_str);
++		sprintf(temp_str, "mac [set|get] [rate] [auto|idx]\n");
++		strcat(ssv6xxx_result_buf, temp_str);
++		sprintf(temp_str, "mac [rx|tx] [eable|disable]\n");
++		strcat(ssv6xxx_result_buf, temp_str);
++	}
++	return 0;
++}
++
++#ifdef CONFIG_IRQ_DEBUG_COUNT
++void print_irq_count(void)
++{
++	char temp_str[512];
++	sprintf(temp_str, "irq debug (%s)\n",
++		ssv_dbg_ctrl_hci->irq_enable ? "enable" : "disable");
++	strcat(ssv6xxx_result_buf, temp_str);
++	sprintf(temp_str, "total irq (%d)\n", ssv_dbg_ctrl_hci->irq_count);
++	strcat(ssv6xxx_result_buf, temp_str);
++	sprintf(temp_str, "invalid irq (%d)\n",
++		ssv_dbg_ctrl_hci->invalid_irq_count);
++	strcat(ssv6xxx_result_buf, temp_str);
++	sprintf(temp_str, "rx irq (%d)\n", ssv_dbg_ctrl_hci->rx_irq_count);
++	strcat(ssv6xxx_result_buf, temp_str);
++	sprintf(temp_str, "tx irq (%d)\n", ssv_dbg_ctrl_hci->tx_irq_count);
++	strcat(ssv6xxx_result_buf, temp_str);
++	sprintf(temp_str, "real tx count irq (%d)\n",
++		ssv_dbg_ctrl_hci->real_tx_irq_count);
++	strcat(ssv6xxx_result_buf, temp_str);
++	sprintf(temp_str, "tx  packet count (%d)\n",
++		ssv_dbg_ctrl_hci->irq_tx_pkt_count);
++	strcat(ssv6xxx_result_buf, temp_str);
++	sprintf(temp_str, "rx packet (%d)\n",
++		ssv_dbg_ctrl_hci->irq_rx_pkt_count);
++	strcat(ssv6xxx_result_buf, temp_str);
++}
++#endif
++void print_isr_info(void)
++{
++	char temp_str[512];
++	sprintf(temp_str, ">>>> HCI Calculate ISR TIME(%s) unit:us\n",
++		((ssv_dbg_ctrl_hci->isr_summary_eable) ? "enable" : "disable"));
++	strcat(ssv6xxx_result_buf, temp_str);
++	sprintf(temp_str, "isr_routine_time(%d)\n",
++		jiffies_to_usecs(ssv_dbg_ctrl_hci->isr_routine_time));
++	strcat(ssv6xxx_result_buf, temp_str);
++	sprintf(temp_str, "isr_tx_time(%d)\n",
++		jiffies_to_usecs(ssv_dbg_ctrl_hci->isr_tx_time));
++	strcat(ssv6xxx_result_buf, temp_str);
++	sprintf(temp_str, "isr_rx_time(%d)\n",
++		jiffies_to_usecs(ssv_dbg_ctrl_hci->isr_rx_time));
++	strcat(ssv6xxx_result_buf, temp_str);
++	sprintf(temp_str, "isr_idle_time(%d)\n",
++		jiffies_to_usecs(ssv_dbg_ctrl_hci->isr_idle_time));
++	strcat(ssv6xxx_result_buf, temp_str);
++	sprintf(temp_str, "isr_rx_idle_time(%d)\n",
++		jiffies_to_usecs(ssv_dbg_ctrl_hci->isr_rx_idle_time));
++	strcat(ssv6xxx_result_buf, temp_str);
++	sprintf(temp_str, "isr_miss_cnt(%d)\n", ssv_dbg_ctrl_hci->isr_miss_cnt);
++	strcat(ssv6xxx_result_buf, temp_str);
++	sprintf(temp_str, "prev_isr_jiffes(%lu)\n",
++		ssv_dbg_ctrl_hci->prev_isr_jiffes);
++	strcat(ssv6xxx_result_buf, temp_str);
++	sprintf(temp_str, "prev_rx_isr_jiffes(%lu)\n",
++		ssv_dbg_ctrl_hci->prev_rx_isr_jiffes);
++	strcat(ssv6xxx_result_buf, temp_str);
++}
++
++static int ssv_cmd_hci(int argc, char *argv[])
++{
++	struct ssv_hw_txq *txq;
++	char temp_str[512];
++	int s, ac = 0;
++	if (argc == 3 && !strcmp(argv[1], "txq") && !strcmp(argv[2], "show")) {
++		for (s = 0; s < WMM_NUM_AC; s++) {
++			if (ssv_dbg_sc != NULL)
++				ac = ssv_dbg_sc->tx.ac_txqid[s];
++			txq = &ssv_dbg_ctrl_hci->hw_txq[s];
++			sprintf(temp_str, ">> txq[%d]", txq->txq_no);
++			if (ssv_dbg_sc != NULL)
++				sprintf(temp_str, "(%s): ",
++					((ssv_dbg_sc->
++					  sc_flags & SC_OP_OFFCHAN) ?
++					 "off channel" : "on channel"));
++			sprintf(temp_str, "cur_qsize=%d\n",
++				skb_queue_len(&txq->qhead));
++			strcat(ssv6xxx_result_buf, temp_str);
++			sprintf(temp_str,
++				"            max_qsize=%d, pause=%d, resume_thres=%d",
++				txq->max_qsize, txq->paused, txq->resum_thres);
++			if (ssv_dbg_sc != NULL)
++				sprintf(temp_str, " flow_control[%d]\n",
++					!!(ssv_dbg_sc->tx.
++					   flow_ctrl_status & (1 << ac)));
++			strcat(ssv6xxx_result_buf, temp_str);
++			sprintf(temp_str, "            Total %d frame sent\n",
++				txq->tx_pkt);
++			strcat(ssv6xxx_result_buf, temp_str);
++		}
++		sprintf(temp_str,
++			">> HCI Debug Counters:\n    read_rs0_info_fail=%d, read_rs1_info_fail=%d\n",
++			ssv_dbg_ctrl_hci->read_rs0_info_fail,
++			ssv_dbg_ctrl_hci->read_rs1_info_fail);
++		strcat(ssv6xxx_result_buf, temp_str);
++		sprintf(temp_str,
++			"    rx_work_running=%d, isr_running=%d, xmit_running=%d\n",
++			ssv_dbg_ctrl_hci->rx_work_running,
++			ssv_dbg_ctrl_hci->isr_running,
++			ssv_dbg_ctrl_hci->xmit_running);
++		strcat(ssv6xxx_result_buf, temp_str);
++		if (ssv_dbg_sc != NULL)
++			sprintf(temp_str, "    flow_ctrl_status=%08x\n",
++				ssv_dbg_sc->tx.flow_ctrl_status);
++		strcat(ssv6xxx_result_buf, temp_str);
++		return 0;
++	} else if (argc == 3 && !strcmp(argv[1], "rxq")
++		   && !strcmp(argv[2], "show")) {
++		sprintf(temp_str, ">> HCI RX Queue (%s): cur_qsize=%d\n",
++			((ssv_dbg_sc->
++			  sc_flags & SC_OP_OFFCHAN) ? "off channel" :
++			 "on channel"), ssv_dbg_ctrl_hci->rx_pkt);
++		strcat(ssv6xxx_result_buf, temp_str);
++		return 0;
++	} else if (argc == 3 && !strcmp(argv[1], "isr_time")
++		   && !strcmp(argv[2], "start")) {
++		ssv_dbg_ctrl_hci->isr_summary_eable = 1;
++		ssv_dbg_ctrl_hci->isr_routine_time = 0;
++		ssv_dbg_ctrl_hci->isr_tx_time = 0;
++		ssv_dbg_ctrl_hci->isr_rx_time = 0;
++		ssv_dbg_ctrl_hci->isr_idle_time = 0;
++		ssv_dbg_ctrl_hci->isr_rx_idle_time = 0;
++		ssv_dbg_ctrl_hci->isr_miss_cnt = 0;
++		ssv_dbg_ctrl_hci->prev_isr_jiffes = 0;
++		ssv_dbg_ctrl_hci->prev_rx_isr_jiffes = 0;
++		print_isr_info();
++		return 0;
++	} else if (argc == 3 && !strcmp(argv[1], "isr_time")
++		   && !strcmp(argv[2], "stop")) {
++		ssv_dbg_ctrl_hci->isr_summary_eable = 0;
++		print_isr_info();
++		return 0;
++	} else if (argc == 3 && !strcmp(argv[1], "isr_time")
++		   && !strcmp(argv[2], "show")) {
++		print_isr_info();
++		return 0;
++	}
++#ifdef CONFIG_IRQ_DEBUG_COUNT
++	else if (argc == 3 && !strcmp(argv[1], "isr_debug")
++		 && !strcmp(argv[2], "reset")) {
++		ssv_dbg_ctrl_hci->irq_enable = 0;
++		ssv_dbg_ctrl_hci->irq_count = 0;
++		ssv_dbg_ctrl_hci->invalid_irq_count = 0;
++		ssv_dbg_ctrl_hci->tx_irq_count = 0;
++		ssv_dbg_ctrl_hci->real_tx_irq_count = 0;
++		ssv_dbg_ctrl_hci->rx_irq_count = 0;
++		ssv_dbg_ctrl_hci->isr_rx_idle_time = 0;
++		ssv_dbg_ctrl_hci->irq_rx_pkt_count = 0;
++		ssv_dbg_ctrl_hci->irq_tx_pkt_count = 0;
++		strcat(ssv6xxx_result_buf, "irq debug reset count\n");
++		return 0;
++	} else if (argc == 3 && !strcmp(argv[1], "isr_debug")
++		   && !strcmp(argv[2], "show")) {
++		print_irq_count();
++		return 0;
++	} else if (argc == 3 && !strcmp(argv[1], "isr_debug")
++		   && !strcmp(argv[2], "stop")) {
++		ssv_dbg_ctrl_hci->irq_enable = 0;
++		strcat(ssv6xxx_result_buf, "irq debug stop\n");
++		return 0;
++	} else if (argc == 3 && !strcmp(argv[1], "isr_debug")
++		   && !strcmp(argv[2], "start")) {
++		ssv_dbg_ctrl_hci->irq_enable = 1;
++		strcat(ssv6xxx_result_buf, "irq debug start\n");
++		return 0;
++	}
++#endif
++	else {
++		strcat(ssv6xxx_result_buf,
++		       "hci [txq|rxq] [show]\nhci [isr_time] [start|stop|show]\n\n");
++		return 0;
++	}
++	return -1;
++}
++
++static int ssv_cmd_hwq(int argc, char *argv[])
++{
++#undef GET_FFO0_CNT
++#undef GET_FFO1_CNT
++#undef GET_FFO2_CNT
++#undef GET_FFO3_CNT
++#undef GET_FFO4_CNT
++#undef GET_FFO5_CNT
++#undef GET_FFO6_CNT
++#undef GET_FFO7_CNT
++#undef GET_FFO8_CNT
++#undef GET_FFO9_CNT
++#undef GET_FFO10_CNT
++#undef GET_FFO11_CNT
++#undef GET_FFO12_CNT
++#undef GET_FFO13_CNT
++#undef GET_FFO14_CNT
++#undef GET_FFO15_CNT
++#undef GET_FF0_CNT
++#undef GET_FF1_CNT
++#undef GET_FF3_CNT
++#undef GET_FF5_CNT
++#undef GET_FF6_CNT
++#undef GET_FF7_CNT
++#undef GET_FF8_CNT
++#undef GET_FF9_CNT
++#undef GET_FF10_CNT
++#undef GET_FF11_CNT
++#undef GET_FF12_CNT
++#undef GET_FF13_CNT
++#undef GET_FF14_CNT
++#undef GET_FF15_CNT
++#undef GET_FF4_CNT
++#undef GET_FF2_CNT
++#undef GET_TX_ID_ALC_LEN
++#undef GET_RX_ID_ALC_LEN
++#undef GET_AVA_TAG
++#define GET_FFO0_CNT ((value & 0x0000001f ) >> 0)
++#define GET_FFO1_CNT ((value & 0x000003e0 ) >> 5)
++#define GET_FFO2_CNT ((value & 0x00000c00 ) >> 10)
++#define GET_FFO3_CNT ((value & 0x000f8000 ) >> 15)
++#define GET_FFO4_CNT ((value & 0x00300000 ) >> 20)
++#define GET_FFO5_CNT ((value & 0x0e000000 ) >> 25)
++#define GET_FFO6_CNT ((value1 & 0x0000000f ) >> 0)
++#define GET_FFO7_CNT ((value1 & 0x000003e0 ) >> 5)
++#define GET_FFO8_CNT ((value1 & 0x00007c00 ) >> 10)
++#define GET_FFO9_CNT ((value1 & 0x000f8000 ) >> 15)
++#define GET_FFO10_CNT ((value1 & 0x00f00000 ) >> 20)
++#define GET_FFO11_CNT ((value1 & 0x3e000000 ) >> 25)
++#define GET_FFO12_CNT ((value2 & 0x00000007 ) >> 0)
++#define GET_FFO13_CNT ((value2 & 0x00000060 ) >> 5)
++#define GET_FFO14_CNT ((value2 & 0x00000c00 ) >> 10)
++#define GET_FFO15_CNT ((value2 & 0x001f8000 ) >> 15)
++#define GET_FF0_CNT ((value & 0x0000001f ) >> 0)
++#define GET_FF1_CNT ((value & 0x000001e0 ) >> 5)
++#define GET_FF3_CNT ((value & 0x00003800 ) >> 11)
++#define GET_FF5_CNT ((value & 0x000e0000 ) >> 17)
++#define GET_FF6_CNT ((value & 0x00700000 ) >> 20)
++#define GET_FF7_CNT ((value & 0x03800000 ) >> 23)
++#define GET_FF8_CNT ((value & 0x1c000000 ) >> 26)
++#define GET_FF9_CNT ((value & 0xe0000000 ) >> 29)
++#define GET_FF10_CNT ((value1 & 0x00000007 ) >> 0)
++#define GET_FF11_CNT ((value1 & 0x00000038 ) >> 3)
++#define GET_FF12_CNT ((value1 & 0x000001c0 ) >> 6)
++#define GET_FF13_CNT ((value1 & 0x00000600 ) >> 9)
++#define GET_FF14_CNT ((value1 & 0x00001800 ) >> 11)
++#define GET_FF15_CNT ((value1 & 0x00006000 ) >> 13)
++#define GET_FF4_CNT ((value1 & 0x000f8000 ) >> 15)
++#define GET_FF2_CNT ((value1 & 0x00700000 ) >> 20)
++#define GET_TX_ID_ALC_LEN ((value & 0x0003fe00 ) >> 9)
++#define GET_RX_ID_ALC_LEN ((value & 0x07fc0000 ) >> 18)
++#define GET_AVA_TAG ((value1 & 0x01ff0000 ) >> 16)
++	u32 addr, value, value1, value2;
++	char temp_str[512];
++	addr = ADR_RD_FFOUT_CNT1;
++	if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, &value)) ;
++	addr = ADR_RD_FFOUT_CNT2;
++	if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, &value1)) ;
++	addr = ADR_RD_FFOUT_CNT3;
++	if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, &value2)) ;
++	sprintf(temp_str,
++		"\n[TAG]  MCU - HCI - SEC -  RX - MIC - TX0 - TX1 - TX2 - TX3 - TX4 - SEC - MIC - TSH\n");
++	strcat(ssv6xxx_result_buf, temp_str);
++	sprintf(temp_str,
++		"OUTPUT %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d\n",
++		GET_FFO0_CNT, GET_FFO1_CNT, GET_FFO3_CNT, GET_FFO4_CNT,
++		GET_FFO5_CNT, GET_FFO6_CNT, GET_FFO7_CNT, GET_FFO8_CNT,
++		GET_FFO9_CNT, GET_FFO10_CNT, GET_FFO11_CNT, GET_FFO12_CNT,
++		GET_FFO15_CNT);
++	strcat(ssv6xxx_result_buf, temp_str);
++	addr = ADR_RD_IN_FFCNT1;
++	if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, &value)) ;
++	addr = ADR_RD_IN_FFCNT2;
++	if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, &value1)) ;
++	sprintf(temp_str,
++		"INPUT  %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d\n",
++		GET_FF0_CNT, GET_FF1_CNT, GET_FF3_CNT, GET_FF4_CNT, GET_FF5_CNT,
++		GET_FF6_CNT, GET_FF7_CNT, GET_FF8_CNT, GET_FF9_CNT,
++		GET_FF10_CNT, GET_FF11_CNT, GET_FF12_CNT, GET_FF15_CNT);
++	strcat(ssv6xxx_result_buf, temp_str);
++	addr = ADR_ID_LEN_THREADSHOLD2;
++	if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, &value)) ;
++	addr = ADR_TAG_STATUS;
++	if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, &value1)) ;
++	sprintf(temp_str, "TX[%d]RX[%d]AVA[%d]\n", GET_TX_ID_ALC_LEN,
++		GET_RX_ID_ALC_LEN, GET_AVA_TAG);
++	strcat(ssv6xxx_result_buf, temp_str);
++	return 0;
++}
++
++#ifdef CONFIG_P2P_NOA
++static struct ssv6xxx_p2p_noa_param cmd_noa_param = {
++	50,
++	100,
++	0x12345678,
++	1,
++	255,
++	{0x4c, 0xe6, 0x76, 0xa2, 0x4e, 0x7c}
++};
++
++void noa_dump(char *temp_str)
++{
++	sprintf(temp_str,
++		"NOA Parameter:\nEnable=%d\nInterval=%d\nDuration=%d\nStart_time=0x%08x\nCount=%d\nAddr=[%02x:%02x:%02x:%02x:%02x:%02x]\n",
++		cmd_noa_param.enable, cmd_noa_param.interval,
++		cmd_noa_param.duration, cmd_noa_param.start_time,
++		cmd_noa_param.count, cmd_noa_param.addr[0],
++		cmd_noa_param.addr[1], cmd_noa_param.addr[2],
++		cmd_noa_param.addr[3], cmd_noa_param.addr[4],
++		cmd_noa_param.addr[5]);
++	strcat(ssv6xxx_result_buf, temp_str);
++}
++
++void ssv6xxx_send_noa_cmd(struct ssv_softc *sc,
++			  struct ssv6xxx_p2p_noa_param *p2p_noa_param)
++{
++	struct sk_buff *skb;
++	struct cfg_host_cmd *host_cmd;
++	int retry_cnt = 5;
++	skb =
++	    ssvdevice_skb_alloc(HOST_CMD_HDR_LEN +
++				sizeof(struct ssv6xxx_p2p_noa_param));
++	skb->data_len = HOST_CMD_HDR_LEN + sizeof(struct ssv6xxx_p2p_noa_param);
++	skb->len = skb->data_len;
++	host_cmd = (struct cfg_host_cmd *)skb->data;
++	host_cmd->c_type = HOST_CMD;
++	host_cmd->h_cmd = (u8) SSV6XXX_HOST_CMD_SET_NOA;
++	host_cmd->len = skb->data_len;
++	memcpy(host_cmd->dat32, p2p_noa_param,
++	       sizeof(struct ssv6xxx_p2p_noa_param));
++	while ((HCI_SEND_CMD(sc->sh, skb) != 0) && (retry_cnt)) {
++		pr_debug("NOA cmd retry=%d\n", retry_cnt);
++		retry_cnt--;
++	}
++	ssvdevice_skb_free(skb);
++}
++
++static int ssv_cmd_noa(int argc, char *argv[])
++{
++	char temp_str[512];
++	char *endp;
++	if (argc == 2 && !strcmp(argv[1], "show")) {
++		;
++	} else if (argc == 3 && !strcmp(argv[1], "duration")) {
++		cmd_noa_param.duration = simple_strtoul(argv[2], &endp, 0);
++	} else if (argc == 3 && !strcmp(argv[1], "interval")) {
++		cmd_noa_param.interval = simple_strtoul(argv[2], &endp, 0);
++	} else if (argc == 3 && !strcmp(argv[1], "start")) {
++		cmd_noa_param.start_time = simple_strtoul(argv[2], &endp, 0);
++	} else if (argc == 3 && !strcmp(argv[1], "enable")) {
++		cmd_noa_param.enable = simple_strtoul(argv[2], &endp, 0);
++	} else if (argc == 3 && !strcmp(argv[1], "count")) {
++		cmd_noa_param.count = simple_strtoul(argv[2], &endp, 0);
++	} else if (argc == 8 && !strcmp(argv[1], "addr")) {
++		cmd_noa_param.addr[0] = simple_strtoul(argv[2], &endp, 16);
++		cmd_noa_param.addr[1] = simple_strtoul(argv[3], &endp, 16);
++		cmd_noa_param.addr[2] = simple_strtoul(argv[4], &endp, 16);
++		cmd_noa_param.addr[3] = simple_strtoul(argv[5], &endp, 16);
++		cmd_noa_param.addr[4] = simple_strtoul(argv[6], &endp, 16);
++		cmd_noa_param.addr[5] = simple_strtoul(argv[7], &endp, 16);
++	} else if (argc == 2 && !strcmp(argv[1], "send")) {
++		ssv6xxx_send_noa_cmd(ssv_dbg_sc, &cmd_noa_param);
++	} else {
++		sprintf(temp_str, "## wrong command\n");
++		strcat(ssv6xxx_result_buf, temp_str);
++		return 0;
++	}
++	noa_dump(temp_str);
++	return 0;
++}
++#endif
++static int ssv_cmd_mib(int argc, char *argv[])
++{
++	u32 addr, value;
++	char temp_str[512];
++	int i;
++	if (argc == 2 && !strcmp(argv[1], "reset")) {
++		addr = MIB_REG_BASE;
++		value = 0x0;
++		if (SSV_REG_WRITE1(ssv6xxx_debug_ifops, MIB_REG_BASE, value)) ;
++		value = 0xffffffff;
++		if (SSV_REG_WRITE1(ssv6xxx_debug_ifops, MIB_REG_BASE, value)) ;
++		value = 0x0;
++		if (SSV_REG_WRITE1(ssv6xxx_debug_ifops, 0xCE0023F8, value)) ;
++		value = 0x100000;
++		if (SSV_REG_WRITE1(ssv6xxx_debug_ifops, 0xCE0023F8, value)) ;
++		value = 0x0;
++		if (SSV_REG_WRITE1(ssv6xxx_debug_ifops, 0xCE0043F8, value)) ;
++		value = 0x100000;
++		if (SSV_REG_WRITE1(ssv6xxx_debug_ifops, 0xCE0043F8, value)) ;
++		value = 0x0;
++		if (SSV_REG_WRITE1(ssv6xxx_debug_ifops, 0xCE000088, value)) ;
++		value = 0x80000000;
++		if (SSV_REG_WRITE1(ssv6xxx_debug_ifops, 0xCE000088, value)) ;
++		sprintf(temp_str, " => MIB reseted\n");
++		strcat(ssv6xxx_result_buf, temp_str);
++	} else if (argc == 2 && !strcmp(argv[1], "list")) {
++		addr = MIB_REG_BASE;
++		for (i = 0; i < 120; i++, addr += 4) {
++			if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, &value)) ;
++			sprintf(temp_str, "%08x ", value);
++			strcat(ssv6xxx_result_buf, temp_str);
++			if (((i + 1) & 0x07) == 0)
++				strcat(ssv6xxx_result_buf, "\n");
++		}
++		strcat(ssv6xxx_result_buf, "\n");
++	} else if (argc == 2 && strcmp(argv[1], "rx") == 0) {
++		sprintf(temp_str, "%-10s\t\t%-10s\t\t%-10s\t\t%-10s\n",
++			"MRX_FCS_SUCC", "MRX_FCS_ERR", "MRX_ALC_FAIL",
++			"MRX_MISS");
++		strcat(ssv6xxx_result_buf, temp_str);
++		if (SSV_REG_READ1
++		    (ssv6xxx_debug_ifops, ADR_MRX_FCS_SUCC, &value)) {
++			sprintf(temp_str, "[%08x]\t\t", value);
++			strcat(ssv6xxx_result_buf, temp_str);
++		}
++		if (SSV_REG_READ1(ssv6xxx_debug_ifops, ADR_MRX_FCS_ERR, &value)) {
++			sprintf(temp_str, "[%08x]\t\t", value);
++			strcat(ssv6xxx_result_buf, temp_str);
++		}
++		if (SSV_REG_READ1
++		    (ssv6xxx_debug_ifops, ADR_MRX_ALC_FAIL, &value)) {
++			sprintf(temp_str, "[%08x]\t\t", value);
++			strcat(ssv6xxx_result_buf, temp_str);
++		}
++		if (SSV_REG_READ1(ssv6xxx_debug_ifops, ADR_MRX_MISS, &value)) {
++			sprintf(temp_str, "[%08x]\n", value);
++			strcat(ssv6xxx_result_buf, temp_str);
++			sprintf(temp_str, "%-10s\t\t%-10s\t\t%-10s\t%-10s\n",
++				"MRX_MB_MISS", "MRX_NIDLE_MISS",
++				"DBG_LEN_ALC_FAIL", "DBG_LEN_CRC_FAIL");
++			strcat(ssv6xxx_result_buf, temp_str);
++		}
++		if (SSV_REG_READ1(ssv6xxx_debug_ifops, ADR_MRX_MB_MISS, &value)) {
++			sprintf(temp_str, "[%08x]\t\t", value);
++			strcat(ssv6xxx_result_buf, temp_str);
++		}
++		if (SSV_REG_READ1
++		    (ssv6xxx_debug_ifops, ADR_MRX_NIDLE_MISS, &value)) {
++			sprintf(temp_str, "[%08x]\t\t", value);
++			strcat(ssv6xxx_result_buf, temp_str);
++		}
++		if (SSV_REG_READ1
++		    (ssv6xxx_debug_ifops, ADR_DBG_LEN_ALC_FAIL, &value)) {
++			sprintf(temp_str, "[%08x]\t\t", value);
++			strcat(ssv6xxx_result_buf, temp_str);
++		}
++		if (SSV_REG_READ1
++		    (ssv6xxx_debug_ifops, ADR_DBG_LEN_CRC_FAIL, &value)) {
++			sprintf(temp_str, "[%08x]\n\n", value);
++			strcat(ssv6xxx_result_buf, temp_str);
++			strcat(ssv6xxx_result_buf, temp_str);
++		}
++		if (SSV_REG_READ1
++		    (ssv6xxx_debug_ifops, ADR_DBG_AMPDU_PASS, &value)) {
++			sprintf(temp_str, "[%08x]\t\t", value);
++			strcat(ssv6xxx_result_buf, temp_str);
++		}
++		if (SSV_REG_READ1
++		    (ssv6xxx_debug_ifops, ADR_DBG_AMPDU_FAIL, &value)) {
++			sprintf(temp_str, "[%08x]\t\t", value);
++			strcat(ssv6xxx_result_buf, temp_str);
++		}
++		if (SSV_REG_READ1
++		    (ssv6xxx_debug_ifops, ADR_ID_ALC_FAIL1, &value)) {
++			sprintf(temp_str, "[%08x]\t\t", value);
++			strcat(ssv6xxx_result_buf, temp_str);
++		}
++		if (SSV_REG_READ1
++		    (ssv6xxx_debug_ifops, ADR_ID_ALC_FAIL2, &value)) {
++			sprintf(temp_str, "[%08x]\n\n", value);
++			strcat(ssv6xxx_result_buf, temp_str);
++			sprintf(temp_str, "PHY B mode:\n");
++			strcat(ssv6xxx_result_buf, temp_str);
++			sprintf(temp_str, "%-10s\t\t%-10s\t\t%-10s\n",
++				"CRC error", "CCA", "counter");
++			strcat(ssv6xxx_result_buf, temp_str);
++		}
++		if (SSV_REG_READ1(ssv6xxx_debug_ifops, 0xCE0023E8, &value)) {
++			sprintf(temp_str, "[%08x]\t\t", value & 0xffff);
++			strcat(ssv6xxx_result_buf, temp_str);
++		}
++		if (SSV_REG_READ1(ssv6xxx_debug_ifops, 0xCE0023EC, &value)) {
++			sprintf(temp_str, "[%08x]\t\t", (value >> 16) & 0xffff);
++			strcat(ssv6xxx_result_buf, temp_str);
++			sprintf(temp_str, "[%08x]\t\t\n\n", value & 0xffff);
++			strcat(ssv6xxx_result_buf, temp_str);
++			sprintf(temp_str, "PHY G/N mode:\n");
++			strcat(ssv6xxx_result_buf, temp_str);
++			sprintf(temp_str, "%-10s\t\t%-10s\t\t%-10s\n",
++				"CRC error", "CCA", "counter");
++			strcat(ssv6xxx_result_buf, temp_str);
++		}
++		if (SSV_REG_READ1(ssv6xxx_debug_ifops, 0xCE0043E8, &value)) {
++			sprintf(temp_str, "[%08x]\t\t", value & 0xffff);
++			strcat(ssv6xxx_result_buf, temp_str);
++		}
++		if (SSV_REG_READ1(ssv6xxx_debug_ifops, 0xCE0043EC, &value)) {
++			sprintf(temp_str, "[%08x]\t\t", (value >> 16) & 0xffff);
++			strcat(ssv6xxx_result_buf, temp_str);
++			sprintf(temp_str, "[%08x]\t\t\n\n", value & 0xffff);
++			strcat(ssv6xxx_result_buf, temp_str);
++		}
++	} else {
++		sprintf(temp_str, "mib [reset|list|rx]\n\n");
++		strcat(ssv6xxx_result_buf, temp_str);
++	}
++	return 0;
++}
++
++static int ssv_cmd_sdio(int argc, char *argv[])
++{
++	u32 addr, value;
++	char temp_str[512], *endp;
++	int ret = 0;
++	if (argc == 4 && !strcmp(argv[1], "reg") && !strcmp(argv[2], "r")) {
++		addr = simple_strtoul(argv[3], &endp, 16);
++		if (!ssv6xxx_debug_ifops->ifops->cmd52_read) {
++			sprintf(temp_str,
++				"The interface doesn't provide cmd52 read\n");
++			strcat(ssv6xxx_result_buf, temp_str);
++			return 0;
++		}
++		ret =
++		    ssv6xxx_debug_ifops->ifops->cmd52_read(ssv6xxx_debug_ifops->
++							   dev, addr, &value);
++		if (ret >= 0) {
++			sprintf(temp_str, "  ==> %x\n", value);
++			strcat(ssv6xxx_result_buf, temp_str);
++			return 0;
++		}
++	} else if (argc == 5 && !strcmp(argv[1], "reg")
++		   && !strcmp(argv[2], "w")) {
++		addr = simple_strtoul(argv[3], &endp, 16);
++		value = simple_strtoul(argv[4], &endp, 16);
++		if (!ssv6xxx_debug_ifops->ifops->cmd52_write) {
++			sprintf(temp_str,
++				"The interface doesn't provide cmd52 write\n");
++			strcat(ssv6xxx_result_buf, temp_str);
++			return 0;
++		}
++		ret =
++		    ssv6xxx_debug_ifops->ifops->
++		    cmd52_write(ssv6xxx_debug_ifops->dev, addr, value);
++		if (ret >= 0) {
++			sprintf(temp_str, "  ==> write odne.\n");
++			strcat(ssv6xxx_result_buf, temp_str);
++			return 0;
++		}
++	}
++	sprintf(temp_str, "sdio cmd52 fail: %d\n", ret);
++	strcat(ssv6xxx_result_buf, temp_str);
++	return 0;
++}
++
++static struct ssv6xxx_iqk_cfg cmd_iqk_cfg = {
++	SSV6XXX_IQK_CFG_XTAL_26M,
++	SSV6XXX_IQK_CFG_PA_DEF,
++	0,
++	0,
++	26,
++	3,
++	0x75,
++	0x75,
++	0x80,
++	0x80,
++	SSV6XXX_IQK_CMD_INIT_CALI,
++	{SSV6XXX_IQK_TEMPERATURE
++	 + SSV6XXX_IQK_RXDC
++	 + SSV6XXX_IQK_RXRC
++	 + SSV6XXX_IQK_TXDC + SSV6XXX_IQK_TXIQ + SSV6XXX_IQK_RXIQ},
++};
++
++static int ssv_cmd_iqk(int argc, char *argv[])
++{
++	char temp_str[512], *endp;
++	struct sk_buff *skb;
++	struct cfg_host_cmd *host_cmd;
++	u32 rxcnt_total, rxcnt_error;
++	sprintf(temp_str, "# got iqk command\n");
++	strcat(ssv6xxx_result_buf, temp_str);
++	if ((argc == 3) && (strcmp(argv[1], "cfg-pa") == 0)) {
++		cmd_iqk_cfg.cfg_pa = simple_strtoul(argv[2], &endp, 0);
++		sprintf(temp_str, "## set cfg_pa as %d\n", cmd_iqk_cfg.cfg_pa);
++		strcat(ssv6xxx_result_buf, temp_str);
++		return 0;
++	} else if ((argc == 3) && (strcmp(argv[1], "cfg-tssi-trgt") == 0)) {
++		cmd_iqk_cfg.cfg_tssi_trgt = simple_strtoul(argv[2], &endp, 0);
++		sprintf(temp_str, "## set cfg_tssi_trgt as %d\n",
++			cmd_iqk_cfg.cfg_tssi_trgt);
++		strcat(ssv6xxx_result_buf, temp_str);
++		return 0;
++	} else if ((argc == 3) && (strcmp(argv[1], "init-cali") == 0)) {
++		cmd_iqk_cfg.cmd_sel = SSV6XXX_IQK_CMD_INIT_CALI;
++		cmd_iqk_cfg.fx_sel = simple_strtoul(argv[2], &endp, 0);
++		sprintf(temp_str, "## do init-cali\n");
++		strcat(ssv6xxx_result_buf, temp_str);
++	} else if ((argc == 3) && (strcmp(argv[1], "rtbl-load") == 0)) {
++		cmd_iqk_cfg.cmd_sel = SSV6XXX_IQK_CMD_RTBL_LOAD;
++		cmd_iqk_cfg.fx_sel = simple_strtoul(argv[2], &endp, 0);
++		sprintf(temp_str, "## do rtbl-load\n");
++		strcat(ssv6xxx_result_buf, temp_str);
++	} else if ((argc == 3) && (strcmp(argv[1], "rtbl-load-def") == 0)) {
++		cmd_iqk_cfg.cmd_sel = SSV6XXX_IQK_CMD_RTBL_LOAD_DEF;
++		cmd_iqk_cfg.fx_sel = simple_strtoul(argv[2], &endp, 0);
++		sprintf(temp_str, "## do rtbl-load\n");
++		strcat(ssv6xxx_result_buf, temp_str);
++	} else if ((argc == 3) && (strcmp(argv[1], "rtbl-reset") == 0)) {
++		cmd_iqk_cfg.cmd_sel = SSV6XXX_IQK_CMD_RTBL_RESET;
++		cmd_iqk_cfg.fx_sel = simple_strtoul(argv[2], &endp, 0);
++		sprintf(temp_str, "## do rtbl-reset\n");
++		strcat(ssv6xxx_result_buf, temp_str);
++	} else if ((argc == 3) && (strcmp(argv[1], "rtbl-set") == 0)) {
++		cmd_iqk_cfg.cmd_sel = SSV6XXX_IQK_CMD_RTBL_SET;
++		cmd_iqk_cfg.fx_sel = simple_strtoul(argv[2], &endp, 0);
++		sprintf(temp_str, "## do rtbl-set\n");
++		strcat(ssv6xxx_result_buf, temp_str);
++	} else if ((argc == 3) && (strcmp(argv[1], "rtbl-export") == 0)) {
++		cmd_iqk_cfg.cmd_sel = SSV6XXX_IQK_CMD_RTBL_EXPORT;
++		cmd_iqk_cfg.fx_sel = simple_strtoul(argv[2], &endp, 0);
++		sprintf(temp_str, "## do rtbl-export\n");
++		strcat(ssv6xxx_result_buf, temp_str);
++	} else if ((argc == 3) && (strcmp(argv[1], "tk-evm") == 0)) {
++		cmd_iqk_cfg.cmd_sel = SSV6XXX_IQK_CMD_TK_EVM;
++		cmd_iqk_cfg.argv = simple_strtoul(argv[2], &endp, 0);
++		sprintf(temp_str, "## do tk-evm\n");
++		strcat(ssv6xxx_result_buf, temp_str);
++	} else if ((argc == 3) && (strcmp(argv[1], "tk-tone") == 0)) {
++		cmd_iqk_cfg.cmd_sel = SSV6XXX_IQK_CMD_TK_TONE;
++		cmd_iqk_cfg.argv = simple_strtoul(argv[2], &endp, 0);
++		sprintf(temp_str, "## do tk-tone\n");
++		strcat(ssv6xxx_result_buf, temp_str);
++	} else if ((argc == 3) && (strcmp(argv[1], "channel") == 0)) {
++		cmd_iqk_cfg.cmd_sel = SSV6XXX_IQK_CMD_TK_CHCH;
++		cmd_iqk_cfg.argv = simple_strtoul(argv[2], &endp, 0);
++		sprintf(temp_str, "## do change channel\n");
++		strcat(ssv6xxx_result_buf, temp_str);
++	} else if ((argc == 2) && (strcmp(argv[1], "tk-rxcnt-report") == 0)) {
++		if (SSV_REG_READ1
++		    (ssv6xxx_debug_ifops, 0xCE0043E8, &rxcnt_error)) ;
++		if (SSV_REG_READ1
++		    (ssv6xxx_debug_ifops, 0xCE0043EC, &rxcnt_total)) ;
++		sprintf(temp_str, "## GN Rx error rate = (%06d/%06d)\n",
++			rxcnt_error, rxcnt_total);
++		strcat(ssv6xxx_result_buf, temp_str);
++		if (SSV_REG_READ1
++		    (ssv6xxx_debug_ifops, 0xCE0023E8, &rxcnt_error)) ;
++		if (SSV_REG_READ1
++		    (ssv6xxx_debug_ifops, 0xCE0023EC, &rxcnt_total)) ;
++		sprintf(temp_str, "## B Rx error rate = (%06d/%06d)\n",
++			rxcnt_error, rxcnt_total);
++		strcat(ssv6xxx_result_buf, temp_str);
++		return 0;
++	} else {
++		sprintf(temp_str, "## invalid iqk command\n");
++		strcat(ssv6xxx_result_buf, temp_str);
++		sprintf(temp_str, "## cmd: cfg-pa/cfg-tssi-trgt\n");
++		strcat(ssv6xxx_result_buf, temp_str);
++		sprintf(temp_str,
++			"## cmd: init-cali/rtbl-load/rtbl-load-def/rtbl-reset/rtbl-set/rtbl-export/tk-evm/tk-tone/tk-channel\n");
++		strcat(ssv6xxx_result_buf, temp_str);
++		sprintf(temp_str, "## fx_sel: 0x0008: RXDC\n");
++		strcat(ssv6xxx_result_buf, temp_str);
++		sprintf(temp_str, "           0x0010: RXRC\n");
++		strcat(ssv6xxx_result_buf, temp_str);
++		sprintf(temp_str, "           0x0020: TXDC\n");
++		strcat(ssv6xxx_result_buf, temp_str);
++		sprintf(temp_str, "           0x0040: TXIQ\n");
++		strcat(ssv6xxx_result_buf, temp_str);
++		sprintf(temp_str, "           0x0080: RXIQ\n");
++		strcat(ssv6xxx_result_buf, temp_str);
++		sprintf(temp_str, "           0x0100: TSSI\n");
++		strcat(ssv6xxx_result_buf, temp_str);
++		sprintf(temp_str, "           0x0200: PAPD\n");
++		strcat(ssv6xxx_result_buf, temp_str);
++		return 0;
++	}
++	skb =
++	    ssvdevice_skb_alloc(HOST_CMD_HDR_LEN + IQK_CFG_LEN +
++				PHY_SETTING_SIZE + RF_SETTING_SIZE);
++	if (skb == NULL) {
++		pr_err("ssv command ssvdevice_skb_alloc failure\n");
++		return 0;
++	}
++	if ((PHY_SETTING_SIZE > MAX_PHY_SETTING_TABLE_SIZE) ||
++	    (RF_SETTING_SIZE > MAX_RF_SETTING_TABLE_SIZE)) {
++		pr_err("Please check RF or PHY table size\n");
++		BUG_ON(1);
++		return 0;
++	}
++	skb->data_len =
++	    HOST_CMD_HDR_LEN + IQK_CFG_LEN + PHY_SETTING_SIZE + RF_SETTING_SIZE;
++	skb->len = skb->data_len;
++	host_cmd = (struct cfg_host_cmd *)skb->data;
++	host_cmd->c_type = HOST_CMD;
++	host_cmd->h_cmd = (u8) SSV6XXX_HOST_CMD_INIT_CALI;
++	host_cmd->len = skb->data_len;
++	cmd_iqk_cfg.phy_tbl_size = PHY_SETTING_SIZE;
++	cmd_iqk_cfg.rf_tbl_size = RF_SETTING_SIZE;
++	memcpy(host_cmd->dat32, &cmd_iqk_cfg, IQK_CFG_LEN);
++	memcpy(host_cmd->dat8 + IQK_CFG_LEN, phy_setting, PHY_SETTING_SIZE);
++	memcpy(host_cmd->dat8 + IQK_CFG_LEN + PHY_SETTING_SIZE, asic_rf_setting,
++	       RF_SETTING_SIZE);
++	if (ssv_dbg_ctrl_hci->shi->hci_ops->hci_send_cmd(skb) == 0) {
++		sprintf(temp_str, "## hci send cmd success\n");
++		strcat(ssv6xxx_result_buf, temp_str);
++	} else {
++		sprintf(temp_str, "## hci send cmd fail\n");
++		strcat(ssv6xxx_result_buf, temp_str);
++	}
++	ssvdevice_skb_free(skb);
++	return 0;
++}
++
++#define LBYTESWAP(a) ((((a) & 0x00ff00ff) << 8) | \
++    (((a) & 0xff00ff00) >> 8))
++#define LONGSWAP(a) ((LBYTESWAP(a) << 16) | (LBYTESWAP(a) >> 16))
++static int ssv_cmd_version(int argc, char *argv[])
++{
++	char temp_str[256];
++	u32 regval;
++	u64 chip_tag = 0;
++	char chip_id[24] = "";
++	if (SSV_REG_READ1(ssv6xxx_debug_ifops, ADR_IC_TIME_TAG_1, &regval)) ;
++	chip_tag = ((u64) regval << 32);
++	if (SSV_REG_READ1(ssv6xxx_debug_ifops, ADR_IC_TIME_TAG_0, &regval)) ;
++	chip_tag |= (regval);
++	sprintf(temp_str, "CHIP TAG: %llx \n", chip_tag);
++	strcat(ssv6xxx_result_buf, temp_str);
++	if (SSV_REG_READ1(ssv6xxx_debug_ifops, ADR_CHIP_ID_3, &regval)) ;
++	*((u32 *) & chip_id[0]) = (u32) LONGSWAP(regval);
++	if (SSV_REG_READ1(ssv6xxx_debug_ifops, ADR_CHIP_ID_2, &regval)) ;
++	*((u32 *) & chip_id[4]) = (u32) LONGSWAP(regval);
++	if (SSV_REG_READ1(ssv6xxx_debug_ifops, ADR_CHIP_ID_1, &regval)) ;
++	*((u32 *) & chip_id[8]) = (u32) LONGSWAP(regval);
++	if (SSV_REG_READ1(ssv6xxx_debug_ifops, ADR_CHIP_ID_0, &regval)) ;
++	*((u32 *) & chip_id[12]) = (u32) LONGSWAP(regval);
++	sprintf(temp_str, "CHIP ID: %s \n", chip_id);
++	strcat(ssv6xxx_result_buf, temp_str);
++	sprintf(temp_str, "# current Software mac version: %d\n",
++		ssv_root_version);
++	strcat(ssv6xxx_result_buf, temp_str);
++	sprintf(temp_str, "SVN ROOT URL %s \n", SSV_ROOT_URl);
++	strcat(ssv6xxx_result_buf, temp_str);
++	sprintf(temp_str, "COMPILER HOST %s \n", COMPILERHOST);
++	strcat(ssv6xxx_result_buf, temp_str);
++	sprintf(temp_str, "COMPILER DATE %s \n", COMPILERDATE);
++	strcat(ssv6xxx_result_buf, temp_str);
++	sprintf(temp_str, "COMPILER OS %s \n", COMPILEROS);
++	strcat(ssv6xxx_result_buf, temp_str);
++	sprintf(temp_str, "COMPILER OS ARCH %s \n", COMPILEROSARCH);
++	strcat(ssv6xxx_result_buf, temp_str);
++	if (SSV_REG_READ1(ssv6xxx_debug_ifops, FW_VERSION_REG, &regval)) ;
++	sprintf(temp_str, "Firmware image version: %d\n", regval);
++	strcat(ssv6xxx_result_buf, temp_str);
++	sprintf(temp_str, "\n[Compiler Option!!]\n");
++	strcat(ssv6xxx_result_buf, temp_str);
++	return 0;
++}
++
++static int ssv_cmd_tool(int argc, char *argv[])
++{
++	u32 addr, value, count;
++	char tmpbf[12], *endp;
++	int s;
++	if (argc == 4 && strcmp(argv[1], "w") == 0) {
++		addr = simple_strtoul(argv[2], &endp, 16);
++		value = simple_strtoul(argv[3], &endp, 16);
++		if (SSV_REG_WRITE1(ssv6xxx_debug_ifops, addr, value)) ;
++		sprintf(ssv6xxx_result_buf, "ok");
++		return 0;
++	}
++	if ((argc == 4 || argc == 3) && strcmp(argv[1], "r") == 0) {
++		count = (argc == 3) ? 1 : simple_strtoul(argv[3], &endp, 10);
++		addr = simple_strtoul(argv[2], &endp, 16);
++		for (s = 0; s < count; s++, addr += 4) {
++			if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, &value)) ;
++			sprintf(tmpbf, "%08x\n", value);
++			strcat(ssv6xxx_result_buf, tmpbf);
++		}
++		return 0;
++	}
++	return -1;
++}
++
++struct _ssv6xxx_txtput {
++	struct task_struct *txtput_tsk;
++	struct sk_buff *skb;
++	u32 size_per_frame;
++	u32 loop_times;
++	u32 occupied_tx_pages;
++};
++struct _ssv6xxx_txtput *ssv6xxx_txtput;
++struct _ssv6xxx_txtput ssv_txtput = { NULL, NULL, 0, 0, 0 };
++
++static int txtput_thread_m2(void *data)
++{
++#define Q_DELAY_MS 20
++	struct sk_buff *skb = NULL;
++	struct ssv6200_tx_desc *tx_desc;
++	int qlen = 0, max_qlen, q_delay_urange[2];
++	max_qlen =
++	    (200 * 1000 / 8 * Q_DELAY_MS) / ssv6xxx_txtput->size_per_frame;
++	q_delay_urange[0] = Q_DELAY_MS * 1000;
++	q_delay_urange[1] = q_delay_urange[0] + 1000;
++	pr_debug("max_qlen: %d\n", max_qlen);
++	while (!kthread_should_stop() && ssv6xxx_txtput->loop_times > 0) {
++		ssv6xxx_txtput->loop_times--;
++		skb = ssvdevice_skb_alloc(ssv6xxx_txtput->size_per_frame);
++		if (skb == NULL) {
++			pr_debug("ssv command txtput_generate_m2 "
++			       "ssvdevice_skb_alloc fail!!!\n");
++			goto end;
++		}
++		skb->data_len = ssv6xxx_txtput->size_per_frame;
++		skb->len = ssv6xxx_txtput->size_per_frame;
++		tx_desc = (struct ssv6200_tx_desc *)skb->data;
++		memset((void *)tx_desc, 0xff, SSV6XXX_TX_DESC_LEN);
++		tx_desc->len = skb->len;
++		tx_desc->c_type = M2_TXREQ;
++		tx_desc->fCmd = (M_ENG_CPU << 4) | M_ENG_HWHCI;
++		tx_desc->reason = ID_TRAP_SW_TXTPUT;
++		qlen = ssv_dbg_ctrl_hci->shi->hci_ops->hci_tx(skb, 0, 0);
++		if (qlen >= max_qlen) {
++			usleep_range(q_delay_urange[0], q_delay_urange[1]);
++		}
++	}
++ end:
++	ssv6xxx_txtput->txtput_tsk = NULL;
++	return 0;
++}
++
++static int txtput_thread(void *data)
++{
++	struct sk_buff *skb = ssv6xxx_txtput->skb;
++	struct ssv6xxx_hci_txq_info2 txq_info2;
++	u32 ret = 0, free_tx_page;
++	int send_cnt;
++	unsigned long start_time, end_time, throughput, time_elapse;
++	throughput =
++	    ssv6xxx_txtput->loop_times * ssv6xxx_txtput->size_per_frame * 8;
++	start_time = jiffies;
++	while (!kthread_should_stop() && ssv6xxx_txtput->loop_times > 0) {
++		ret =
++		    SSV_REG_READ1(ssv6xxx_debug_ifops, ADR_TX_ID_ALL_INFO2,
++				  (u32 *) & txq_info2);
++		if (ret < 0) {
++			pr_debug("%s, read ADR_TX_ID_ALL_INFO2 failed\n",
++			       __func__);
++			goto end;
++		}
++		free_tx_page =
++		    SSV6200_PAGE_TX_THRESHOLD - txq_info2.tx_use_page;
++		send_cnt = free_tx_page / ssv6xxx_txtput->occupied_tx_pages;
++		while (send_cnt > 0 && ssv6xxx_txtput->loop_times > 0) {
++			send_cnt--;
++			ssv6xxx_txtput->loop_times--;
++			ssv_dbg_ctrl_hci->shi->hci_ops->hci_send_cmd(skb);
++		}
++	}
++	end_time = jiffies;
++	ssvdevice_skb_free(skb);
++	time_elapse = ((end_time - start_time) * 1000) / HZ;
++	if (time_elapse > 0) {
++		throughput = throughput / time_elapse;
++		pr_debug("duration %ldms, avg. throughput %d Kbps\n", time_elapse,
++		       (int)throughput);
++	}
++ end:
++	ssv6xxx_txtput->txtput_tsk = NULL;
++	return 0;
++}
++
++int txtput_generate_m2(u32 size_per_frame, u32 loop_times)
++{
++	ssv6xxx_txtput->size_per_frame = size_per_frame;
++	ssv6xxx_txtput->loop_times = loop_times;
++	ssv6xxx_txtput->txtput_tsk =
++	    kthread_run(txtput_thread_m2, NULL, "txtput_thread_m2");
++	return 0;
++}
++
++int txtput_generate_host_cmd(u32 size_per_frame, u32 loop_times)
++{
++#define PAGESIZE 256
++	struct cfg_host_cmd *host_cmd;
++	struct sk_buff *skb;
++	skb = ssvdevice_skb_alloc(size_per_frame);
++	if (skb == NULL) {
++		pr_debug
++		    ("ssv command txtput_generate_host_cmd ssvdevice_skb_alloc fail!!!\n");
++		return 0;
++	}
++	skb->data_len = size_per_frame;
++	skb->len = skb->data_len;
++	host_cmd = (struct cfg_host_cmd *)skb->data;
++	host_cmd->c_type = TEST_CMD;
++	host_cmd->h_cmd = (u8) SSV6XXX_HOST_CMD_TX_TPUT;
++	host_cmd->len = skb->data_len;
++	memcpy(host_cmd->dat32, skb->data, size_per_frame);
++	ssv6xxx_txtput->occupied_tx_pages =
++	    (size_per_frame / PAGESIZE) + ((size_per_frame % PAGESIZE) != 0);
++	ssv6xxx_txtput->size_per_frame = size_per_frame;
++	ssv6xxx_txtput->loop_times = loop_times;
++	ssv6xxx_txtput->skb = skb;
++	ssv6xxx_txtput->txtput_tsk =
++	    kthread_run(txtput_thread, NULL, "txtput_thread");
++	return 0;
++}
++
++int txtput_tsk_cleanup(void)
++{
++	int ret = 0;
++	if (ssv6xxx_txtput->txtput_tsk) {
++		ret = kthread_stop(ssv6xxx_txtput->txtput_tsk);
++		ssv6xxx_txtput->txtput_tsk = NULL;
++	}
++	return ret;
++}
++
++int watchdog_controller(struct ssv_hw *sh, u8 flag)
++{
++	struct sk_buff *skb;
++	struct cfg_host_cmd *host_cmd;
++	int ret = 0;
++	pr_debug("watchdog_controller %d\n", flag);
++	skb = ssvdevice_skb_alloc(HOST_CMD_HDR_LEN);
++	if (skb == NULL) {
++		pr_err("init watchdog_controller failure\n");
++		return (-1);
++	}
++	skb->data_len = HOST_CMD_HDR_LEN;
++	skb->len = skb->data_len;
++	host_cmd = (struct cfg_host_cmd *)skb->data;
++	host_cmd->c_type = HOST_CMD;
++	host_cmd->h_cmd = (u8) flag;
++	host_cmd->len = skb->data_len;
++	sh->hci.hci_ops->hci_send_cmd(skb);
++	ssvdevice_skb_free(skb);
++	return ret;
++}
++
++static int ssv_cmd_txtput(int argc, char *argv[])
++{
++	char tmpbf[64], *endp;
++	u32 size_per_frame, loop_times, pkt_type;
++	ssv6xxx_txtput = &ssv_txtput;
++	if (argc == 2 && !strcmp(argv[1], "stop")) {
++		txtput_tsk_cleanup();
++		return 0;
++	}
++	if (argc != 4) {
++		sprintf(tmpbf, "* txtput stop\n");
++		strcat(ssv6xxx_result_buf, tmpbf);
++		sprintf(tmpbf, "* txtput [type] [size] [frames]\n");
++		strcat(ssv6xxx_result_buf, tmpbf);
++		sprintf(tmpbf, "    type(packet type):\n");
++		strcat(ssv6xxx_result_buf, tmpbf);
++		sprintf(tmpbf, "         0 = host_cmd\n");
++		strcat(ssv6xxx_result_buf, tmpbf);
++		sprintf(tmpbf, "         1 = m2_type \n");
++		strcat(ssv6xxx_result_buf, tmpbf);
++		sprintf(tmpbf, " EX: txtput 1 14000 9999 \n");
++		strcat(ssv6xxx_result_buf, tmpbf);
++		return 0;
++	}
++	pkt_type = simple_strtoul(argv[1], &endp, 10);
++	size_per_frame = simple_strtoul(argv[2], &endp, 10);
++	loop_times = simple_strtoul(argv[3], &endp, 10);
++	sprintf(tmpbf, "type&size&frames:%d&%d&%d\n", pkt_type, size_per_frame,
++		loop_times);
++	strcat(ssv6xxx_result_buf, tmpbf);
++	if (ssv6xxx_txtput->txtput_tsk) {
++		sprintf(tmpbf, "txtput already in progress\n");
++		strcat(ssv6xxx_result_buf, tmpbf);
++		return 0;
++	}
++	watchdog_controller(((struct ssv_softc *)ssv_dbg_sc)->sh,
++			    (u8) SSV6XXX_HOST_CMD_WATCHDOG_STOP);
++	((struct ssv_softc *)ssv_dbg_sc)->watchdog_flag = WD_SLEEP;
++	if (pkt_type)
++		txtput_generate_m2(size_per_frame + SSV6XXX_TX_DESC_LEN,
++				   loop_times);
++	else
++		txtput_generate_host_cmd(size_per_frame + HOST_CMD_HDR_LEN,
++					 loop_times);
++	return 0;
++}
++
++static int ssv_cmd_rxtput(int argc, char *argv[])
++{
++	struct sk_buff *skb;
++	struct cfg_host_cmd *host_cmd;
++	struct sdio_rxtput_cfg cmd_rxtput_cfg;
++	char tmpbf[32], *endp;
++	if (argc != 3) {
++		sprintf(ssv6xxx_result_buf, "rxtput [size] [frames]\n");
++		return 0;
++	}
++	skb =
++	    ssvdevice_skb_alloc(HOST_CMD_HDR_LEN +
++				sizeof(struct sdio_rxtput_cfg));
++	if (skb == NULL) {
++		pr_err("ssv command ssvdevice_skb_alloc fail\n");
++		return 0;
++	}
++	watchdog_controller(((struct ssv_softc *)ssv_dbg_sc)->sh,
++			    (u8) SSV6XXX_HOST_CMD_WATCHDOG_STOP);
++	((struct ssv_softc *)ssv_dbg_sc)->watchdog_flag = WD_SLEEP;
++	cmd_rxtput_cfg.size_per_frame = simple_strtoul(argv[1], &endp, 10);
++	cmd_rxtput_cfg.total_frames = simple_strtoul(argv[2], &endp, 10);
++	sprintf(tmpbf, "size&frames:%d&%d\n", cmd_rxtput_cfg.size_per_frame,
++		cmd_rxtput_cfg.total_frames);
++	strcat(ssv6xxx_result_buf, tmpbf);
++	skb->data_len = HOST_CMD_HDR_LEN + sizeof(struct sdio_rxtput_cfg);
++	skb->len = skb->data_len;
++	host_cmd = (struct cfg_host_cmd *)skb->data;
++	host_cmd->c_type = HOST_CMD;
++	host_cmd->h_cmd = (u8) SSV6XXX_HOST_CMD_RX_TPUT;
++	host_cmd->len = skb->data_len;
++	memcpy(host_cmd->dat32, &cmd_rxtput_cfg,
++	       sizeof(struct sdio_rxtput_cfg));
++	if (ssv_dbg_ctrl_hci->shi->hci_ops->hci_send_cmd(skb) == 0) {
++		strcat(ssv6xxx_result_buf,
++		       "## hci cmd was sent successfully\n");
++	} else {
++		strcat(ssv6xxx_result_buf, "## hci cmd was sent failed\n");
++	}
++	ssvdevice_skb_free(skb);
++	return 0;
++}
++
++static int ssv_cmd_check(int argc, char *argv[])
++{
++	u32 size, i, j, x, y, id, value, address, id_value;
++	char *endp;
++	u32 id_base_address[4];
++	id_base_address[0] = 0xcd010008;
++	id_base_address[1] = 0xcd01000c;
++	id_base_address[2] = 0xcd010054;
++	id_base_address[3] = 0xcd010058;
++	if (argc != 2) {
++		sprintf(ssv6xxx_result_buf, "check [packet size]\n");
++		return 0;
++	}
++	size = simple_strtoul(argv[1], &endp, 10);
++	size = size >> 2;
++	for (x = 0; x < 4; x++) {
++		if (SSV_REG_READ1
++		    (ssv6xxx_debug_ifops, id_base_address[x], &id_value)) ;
++		for (y = 0; y < 32 && id_value; y++, id_value >>= 1) {
++			if (id_value & 0x1) {
++				id = 32 * x + y;
++				address = 0x80000000 + (id << 16);
++				{
++					for (i = 0; i < size; i += 8) {
++						if (SSV_REG_READ1
++						    (ssv6xxx_debug_ifops,
++						     address, &value)) ;
++						address += 4;
++						for (j = 1; j < 8; j++) {
++							if (SSV_REG_READ1
++							    (ssv6xxx_debug_ifops,
++							     address, &value)) ;
++							address += 4;
++						}
++					}
++				}
++			}
++		}
++	}
++	return 0;
++}
++
++struct ssv_cmd_table cmd_table[] = {
++	{"help", ssv_cmd_help, "ssv6200 command usage."},
++	{"-h", ssv_cmd_help, "ssv6200 command usage."},
++	{"--help", ssv_cmd_help, "ssv6200 command usage."},
++	{"reg", ssv_cmd_reg, "ssv6200 register read/write."},
++	{"cfg", ssv_cmd_cfg, "ssv6200 configuration."},
++	{"sta", ssv_cmd_sta, "svv6200 station info."},
++	{"dump", ssv_cmd_dump, "dump ssv6200 tables."},
++	{"hwq", ssv_cmd_hwq, "hardware queue staus"},
++#ifdef CONFIG_P2P_NOA
++	{"noa", ssv_cmd_noa, "config noa param"},
++#endif
++	{"irq", ssv_cmd_irq, "get sdio irq status."},
++	{"mac", ssv_cmd_mac, "ieee80211 swmac."},
++	{"hci", ssv_cmd_hci, "HCI command."},
++	{"sdio", ssv_cmd_sdio, "SDIO command."},
++	{"iqk", ssv_cmd_iqk, "iqk command"},
++	{"version", ssv_cmd_version, "version information"},
++	{"mib", ssv_cmd_mib, "mib counter related"},
++	{"tool", ssv_cmd_tool, "ssv6200 tool register read/write."},
++	{"rxtput", ssv_cmd_rxtput, "test rx sdio throughput"},
++	{"txtput", ssv_cmd_txtput, "test tx sdio throughput"},
++	{"check", ssv_cmd_check, "dump all allocate packet buffer"},
++	{NULL, NULL, NULL},
++};
++
++int ssv_cmd_submit(char *cmd)
++{
++	struct ssv_cmd_table *sc_tbl;
++	char *pch, ch;
++	int ret;
++	ssv6xxx_debug_ifops = (void *)ssv6xxx_ifdebug_info;
++	strcpy(sg_cmd_buffer, cmd);
++	for (sg_argc = 0, ch = 0, pch = sg_cmd_buffer;
++	     (*pch != 0x00) && (sg_argc < CLI_ARG_SIZE); pch++) {
++		if ((ch == 0) && (*pch != ' ')) {
++			ch = 1;
++			sg_argv[sg_argc] = pch;
++		}
++		if ((ch == 1) && (*pch == ' ')) {
++			*pch = 0x00;
++			ch = 0;
++			sg_argc++;
++		}
++	}
++	if (ch == 1) {
++		sg_argc++;
++	} else if (sg_argc > 0) {
++		*(pch - 1) = ' ';
++	}
++	if (sg_argc > 0) {
++		for (sc_tbl = cmd_table; sc_tbl->cmd; sc_tbl++) {
++			if (!strcmp(sg_argv[0], sc_tbl->cmd)) {
++				if ((sc_tbl->cmd_func_ptr != ssv_cmd_cfg) &&
++				    (!ssv6xxx_debug_ifops->dev ||
++				     !ssv6xxx_debug_ifops->ifops ||
++				     !ssv6xxx_debug_ifops->pdev)) {
++					strcpy(ssv6xxx_result_buf,
++					       "Member of ssv6xxx_ifdebug_info is NULL !\n");
++					return -1;
++				}
++				ssv6xxx_result_buf[0] = 0x00;
++				ret = sc_tbl->cmd_func_ptr(sg_argc, sg_argv);
++				if (ret < 0) {
++					strcpy(ssv6xxx_result_buf,
++					       "Invalid command !\n");
++				}
++				return 0;
++			}
++		}
++		strcpy(ssv6xxx_result_buf, "Command not found !\n");
++	} else {
++		strcpy(ssv6xxx_result_buf, "./cli -h\n");
++	}
++	return 0;
++}
+diff --git a/drivers/net/wireless/ssv6051/ssvdevice/ssv_cmd.h b/drivers/net/wireless/ssv6051/ssvdevice/ssv_cmd.h
+new file mode 100644
+index 000000000000..d96bfcc54954
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/ssvdevice/ssv_cmd.h
+@@ -0,0 +1,50 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation, either version 3 of the License, or
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _SSV_CMD_H_
++#define _SSV_CMD_H_
++#define CLI_BUFFER_SIZE 256
++#define CLI_ARG_SIZE 10
++#define CLI_RESULT_BUF_SIZE (4096)
++#define DEBUG_DIR_ENTRY "ssv"
++#define DEBUG_DEVICETYPE_ENTRY "ssv_devicetype"
++#define DEBUG_CMD_ENTRY "ssv_cmd"
++#define MAX_CHARS_PER_LINE 256
++struct ssv_cmd_table {
++	const char *cmd;
++	int (*cmd_func_ptr)(int, char **);
++	const char *usage;
++};
++struct ssv6xxx_cfg_cmd_table {
++	u8 *cfg_cmd;
++	void *var;
++	u32 arg;
++	int (*translate_func)(u8 *, void *, u32);
++};
++#define SSV_REG_READ1(ops,reg,val) \
++        (ops)->ifops->readreg((ops)->dev, reg, val)
++#define SSV_REG_WRITE1(ops,reg,val) \
++        (ops)->ifops->writereg((ops)->dev, reg, val)
++#define SSV_REG_SET_BITS1(ops,reg,set,clr) \
++    { \
++        u32 reg_val; \
++        SSV_REG_READ(ops, reg, &reg_val); \
++        reg_val &= ~(clr); \
++        reg_val |= (set); \
++        SSV_REG_WRITE(ops, reg, reg_val); \
++    }
++int ssv_cmd_submit(char *cmd);
++#endif
+diff --git a/drivers/net/wireless/ssv6051/ssvdevice/ssvdevice.c b/drivers/net/wireless/ssv6051/ssvdevice/ssvdevice.c
+new file mode 100644
+index 000000000000..eb848553798f
+--- /dev/null
++++ b/drivers/net/wireless/ssv6051/ssvdevice/ssvdevice.c
+@@ -0,0 +1,256 @@
++/*
++ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
++ * Copyright (c) 2015 iComm Corporation
++ *
++ * This program is free software: you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation, either version 3 of the License, or
++ * (at your option) any later version.
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
++ * See the GNU General Public License for more details.
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <linux/kernel.h>
++#include <linux/version.h>
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/slab.h>
++#include <asm/uaccess.h>
++#include <linux/errno.h>
++#include "ssv_cmd.h"
++#include "ssv_cfg.h"
++#include <linux/fs.h>
++#include <asm/uaccess.h>
++#include <linux/buffer_head.h>
++#include <linux/ctype.h>
++
++#ifdef CONFIG_DEBUG_FS
++#include <linux/debugfs.h>
++#endif
++
++char *ssv_initmac = NULL;
++EXPORT_SYMBOL(ssv_initmac);
++module_param(ssv_initmac, charp, 0644);
++MODULE_PARM_DESC(ssv_initmac, "Wi-Fi MAC address");
++
++u32 ssv_devicetype = 0;
++EXPORT_SYMBOL(ssv_devicetype);
++
++#ifdef CONFIG_DEBUG_FS
++static struct dentry *debugfs;
++#endif
++
++struct proc_dir_entry *procfs;
++static char *ssv6xxx_cmd_buf;
++char *ssv6xxx_result_buf;
++extern struct ssv6xxx_cfg_cmd_table cfg_cmds[];
++extern struct ssv6xxx_cfg ssv_cfg;
++char DEFAULT_CFG_PATH[] = "/lib/firmware/ssv6051-wifi.cfg";
++static int ssv6xxx_dbg_open(struct inode *inode, struct file *filp)
++{
++	filp->private_data = inode->i_private;
++	return 0;
++}
++
++static ssize_t ssv6xxx_dbg_read(struct file *filp, char __user * buffer,
++				size_t count, loff_t * ppos)
++{
++	int len;
++	if (*ppos != 0)
++		return 0;
++	len = strlen(ssv6xxx_result_buf) + 1;
++	if (len == 1)
++		return 0;
++	if (copy_to_user(buffer, ssv6xxx_result_buf, len))
++		return -EFAULT;
++	ssv6xxx_result_buf[0] = 0x00;
++	return len;
++}
++
++static ssize_t ssv6xxx_dbg_write(struct file *filp, const char __user * buffer,
++				 size_t count, loff_t * ppos)
++{
++	if (*ppos != 0 || count > 255)
++		return 0;
++	if (copy_from_user(ssv6xxx_cmd_buf, buffer, count))
++		return -EFAULT;
++	ssv6xxx_cmd_buf[count - 1] = 0x00;
++	ssv_cmd_submit(ssv6xxx_cmd_buf);
++	return count;
++}
++
++size_t read_line(struct file * fp, char *buf, size_t size)
++{
++	size_t num_read = 0;
++	size_t total_read = 0;
++	char *buffer;
++	char ch;
++	size_t start_ignore = 0;
++	if (size <= 0 || buf == NULL) {
++		total_read = -EINVAL;
++		return -EINVAL;
++	}
++	buffer = buf;
++	for (;;) {
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,14,0)
++		num_read = kernel_read(fp, &ch, 1, &fp->f_pos);
++#else
++		mm_segment_t fs;
++		fs = get_fs();
++		set_fs(KERNEL_DS);
++		num_read = vfs_read(fp, &ch, 1, &fp->f_pos);
++		set_fs(fs);
++#endif
++		if (num_read < 0) {
++			if (num_read == EINTR)
++				continue;
++			else
++				return -1;
++		} else if (num_read == 0) {
++			if (total_read == 0)
++				return 0;
++			else
++				break;
++		} else {
++			if (ch == '#')
++				start_ignore = 1;
++			if (total_read < size - 1) {
++				total_read++;
++				if (start_ignore)
++					*buffer++ = '\0';
++				else
++					*buffer++ = ch;
++			}
++			if (ch == '\n')
++				break;
++		}
++	}
++	*buffer = '\0';
++	return total_read;
++}
++
++int ischar(char *c)
++{
++	int is_char = 1;
++	while (*c) {
++		if (isalpha(*c) || isdigit(*c) || *c == '_' || *c == ':'
++		    || *c == '/' || *c == '.' || *c == '-')
++			c++;
++		else {
++			is_char = 0;
++			break;
++		}
++	}
++	return is_char;
++}
++
++void sta_cfg_set(void)
++{
++	struct file *fp = (struct file *)NULL;
++	char buf[MAX_CHARS_PER_LINE], cfg_cmd[32], cfg_value[32];
++	size_t s, read_len = 0, is_cmd_support = 0;
++
++	memset(&ssv_cfg, 0, sizeof(ssv_cfg));
++	memset(buf, 0, sizeof(buf));
++	fp = filp_open(DEFAULT_CFG_PATH, O_RDONLY, 0);
++	if (IS_ERR(fp) || fp == NULL) {
++		WARN_ON(1);
++		return;
++	}
++	if (fp->f_path.dentry == NULL) {
++		WARN_ON(1);
++		return;
++	}
++	do {
++		memset(cfg_cmd, '\0', sizeof(cfg_cmd));
++		memset(cfg_value, '\0', sizeof(cfg_value));
++		read_len = read_line(fp, buf, MAX_CHARS_PER_LINE);
++		sscanf(buf, "%s = %s", cfg_cmd, cfg_value);
++		if (!ischar(cfg_cmd) || !ischar(cfg_value)) {
++			pr_warn("Invalid configuration parameter: %s\n", buf);
++			continue;
++		}
++		is_cmd_support = 0;
++		for (s = 0; cfg_cmds[s].cfg_cmd != NULL; s++) {
++			if (strcmp(cfg_cmds[s].cfg_cmd, cfg_cmd) == 0) {
++				cfg_cmds[s].translate_func(cfg_value,
++							   cfg_cmds[s].var,
++							   cfg_cmds[s].arg);
++				is_cmd_support = 1;
++				break;
++			}
++		}
++		if (!is_cmd_support && strlen(cfg_cmd) > 0) {
++			pr_warn("Unsupported configuration command: %s", cfg_cmd);
++		}
++	} while (read_len > 0);
++	filp_close(fp, NULL);
++}
++
++static const struct file_operations ssv6xxx_dbg_fops = {
++	.owner = THIS_MODULE,
++	.open = ssv6xxx_dbg_open,
++	.read = ssv6xxx_dbg_read,
++	.write = ssv6xxx_dbg_write,
++};
++
++extern int ssv6xxx_hci_init(void);
++extern void ssv6xxx_hci_exit(void);
++extern int ssv6xxx_init(void);
++extern void ssv6xxx_exit(void);
++extern int ssv6xxx_sdio_init(void);
++extern void ssv6xxx_sdio_exit(void);
++
++int ssvdevice_init(void)
++{
++	ssv6xxx_cmd_buf =
++	    (char *)kzalloc(CLI_BUFFER_SIZE + CLI_RESULT_BUF_SIZE, GFP_KERNEL);
++	if (!ssv6xxx_cmd_buf)
++		return -ENOMEM;
++	ssv6xxx_result_buf = ssv6xxx_cmd_buf + CLI_BUFFER_SIZE;
++	ssv6xxx_cmd_buf[0] = 0x00;
++	ssv6xxx_result_buf[0] = 0x00;
++#ifdef CONFIG_DEBUG_FS
++	debugfs = debugfs_create_dir(DEBUG_DIR_ENTRY, NULL);
++	if (!debugfs)
++		return -ENOMEM;
++	debugfs_create_u32(DEBUG_DEVICETYPE_ENTRY, S_IRUGO | S_IWUSR, debugfs,
++			   &ssv_devicetype);
++	debugfs_create_file(DEBUG_CMD_ENTRY, S_IRUGO | S_IWUSR, debugfs, NULL,
++			    &ssv6xxx_dbg_fops);
++#endif
++	sta_cfg_set();
++	{
++		int ret;
++		ret = ssv6xxx_hci_init();
++		if (!ret) {
++			ret = ssv6xxx_init();
++		}
++		if (!ret) {
++			ret = ssv6xxx_sdio_init();
++		}
++		return ret;
++	}
++
++	return 0;
++}
++
++void ssvdevice_exit(void)
++{
++
++	ssv6xxx_exit();
++	ssv6xxx_hci_exit();
++	ssv6xxx_sdio_exit();
++
++#ifdef CONFIG_DEBUG_FS
++	debugfs_remove_recursive(debugfs);
++#endif
++	kfree(ssv6xxx_cmd_buf);
++}
++
++EXPORT_SYMBOL(ssvdevice_init);
++EXPORT_SYMBOL(ssvdevice_exit);
+--
+2.34.1
diff --git a/projects/Rockchip/devices/RK322X/patches/linux/default/linux-4004-add-dmc-driver.patch b/projects/Rockchip/devices/RK322X/patches/linux/default/linux-4004-add-dmc-driver.patch
new file mode 100644
index 0000000000..34acaf3a68
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/patches/linux/default/linux-4004-add-dmc-driver.patch
@@ -0,0 +1,1020 @@
+From e7c97c57e2d5040e90662459239bc28c8ea89be5 Mon Sep 17 00:00:00 2001
+From: Paolo Sabatino <paolo.sabatino@gmail.com>
+Date: Wed, 7 Jul 2021 19:27:03 +0000
+Subject: [PATCH] rk3228/rk3328: add dmc driver
+
+---
+ arch/arm/boot/dts/rockchip/rk322x.dtsi                |  69 +-
+ drivers/devfreq/Kconfig                      |  24 +
+ drivers/devfreq/Makefile                     |   2 +
+ drivers/devfreq/rk3228_dmc.c                 | 623 ++++++++++++++
+  include/dt-bindings/clock/rockchip-ddr.h     |  63 ++
+ include/dt-bindings/memory/rockchip,rk322x.h |  90 ++
+ 7 files changed, 1714 insertions(+), 3 deletions(-)
+ create mode 100644 drivers/devfreq/rk3228_dmc.c
+ create mode 100644 drivers/devfreq/rk3328_dmc.c
+ create mode 100644 include/dt-bindings/clock/rockchip-ddr.h
+ create mode 100644 include/dt-bindings/memory/rockchip,rk322x.h
+
+diff --git a/arch/arm/boot/dts/rockchip/rk322x.dtsi b/arch/arm/boot/dts/rockchip/rk322x.dtsi
+index 88e33eb11..22da2e3cd 100644
+--- a/arch/arm/boot/dts/rockchip/rk322x.dtsi
++++ b/arch/arm/boot/dts/rockchip/rk322x.dtsi
+@@ -7,6 +7,8 @@
+ #include <dt-bindings/clock/rk3228-cru.h>
+ #include <dt-bindings/thermal/thermal.h>
+ #include <dt-bindings/power/rk3228-power.h>
++#include <dt-bindings/clock/rockchip-ddr.h>
++#include <dt-bindings/memory/rockchip,rk322x.h>
+
+ / {
+	#address-cells = <1>;
+@@ -106,6 +106,68 @@ dfi: dfi@11210000 {
+		status = "okay";
+	};
+
++	dmc: dmc@11200000 {
++		compatible = "rockchip,rk3228-dmc", "rockchip,rk322x-dram";
++		reg = <0x11200000 0x400>;
++		clocks = <&cru SCLK_DDRCLK>;
++		clock-names = "ddr_sclk";
++		operating-points-v2 = <&dmc_opp_table>;
++		rockchip,dram_timing = <&dram_timing>;
++		rockchip,grf = <&grf>;
++		devfreq-events = <&dfi>;
++		upthreshold = <15>;
++		downdifferential = <10>;
++		#cooling-cells = <2>;
++		status = "disabled";
++	};
++
++	dmc_opp_table: dmc-opp-table {
++		compatible = "operating-points-v2";
++
++		opp-330000000 {
++			opp-hz = /bits/ 64 <330000000>;
++			opp-microvolt = <1050000 1000000 1200000>;
++		};
++		opp-534000000 {
++			opp-hz = /bits/ 64 <534000000>;
++			opp-microvolt = <1050000 1000000 1200000>;
++		};
++		opp-660000000 {
++			opp-hz = /bits/ 64 <660000000>;
++			opp-microvolt = <1100000 1000000 1200000>;
++		};
++		opp-786000000 {
++			opp-hz = /bits/ 64 <786000000>;
++			opp-microvolt = <1150000 1000000 1200000>;
++			status = "disabled";
++		};
++	};
++
++	dram_timing: dram-timing {
++		compatible = "rockchip,dram-timing";
++		dram_spd_bin = <DDR3_DEFAULT>;
++		sr_idle = <0x18>;
++		pd_idle = <0x20>;
++		dram_dll_disb_freq = <300>;
++		phy_dll_disb_freq = <400>;
++		dram_odt_disb_freq = <333>;
++		phy_odt_disb_freq = <333>;
++		ddr3_drv = <DDR3_DS_40ohm>;
++		ddr3_odt = <DDR3_ODT_120ohm>;
++		lpddr3_drv = <LP3_DS_34ohm>;
++		lpddr3_odt = <LP3_ODT_240ohm>;
++		lpddr2_drv = <LP2_DS_34ohm>;
++		/* lpddr2 not supported odt */
++		phy_ddr3_clk_drv = <PHY_DDR3_RON_RTT_45ohm>;
++		phy_ddr3_cmd_drv = <PHY_DDR3_RON_RTT_45ohm>;
++		phy_ddr3_dqs_drv = <PHY_DDR3_RON_RTT_34ohm>;
++		phy_ddr3_odt = <PHY_DDR3_RON_RTT_225ohm>;
++		phy_lp23_clk_drv = <PHY_LP23_RON_RTT_43ohm>;
++		phy_lp23_cmd_drv = <PHY_LP23_RON_RTT_34ohm>;
++		phy_lp23_dqs_drv = <PHY_LP23_RON_RTT_34ohm>;
++		phy_lp3_odt = <PHY_LP23_RON_RTT_240ohm>;
++	};
++
+	arm-pmu {
+		compatible = "arm,cortex-a7-pmu";
+		interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
+
+diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig
+index 37dc40d1f..5f864a855 100644
+--- a/drivers/devfreq/Kconfig
++++ b/drivers/devfreq/Kconfig
+@@ -131,6 +131,18 @@ config ARM_TEGRA20_DEVFREQ
+	  It reads Memory Controller counters and adjusts the operating
+	  frequencies and voltages with OPP support.
+
++config ARM_RK3228_DMC_DEVFREQ
++	tristate "ARM RK3228 DMC DEVFREQ Driver"
++	depends on ARCH_ROCKCHIP
++	select DEVFREQ_EVENT_ROCKCHIP_DFI
++	select DEVFREQ_GOV_SIMPLE_ONDEMAND
++	select PM_DEVFREQ_EVENT
++	select PM_OPP
++	help
++	  This adds the DEVFREQ driver for the RK3228 DMC(Dynamic Memory Controller).
++	  It sets the frequency for the memory controller and reads the usage counts
++	  from hardware.
++
+ config ARM_RK3399_DMC_DEVFREQ
+	tristate "ARM RK3399 DMC DEVFREQ Driver"
+	depends on (ARCH_ROCKCHIP && HAVE_ARM_SMCCC) || \
+diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile
+index bf40d04928d..059712bfe5f 100644
+--- a/drivers/devfreq/Makefile
++++ b/drivers/devfreq/Makefile
+@@ -13,6 +13,7 @@ obj-$(CONFIG_ARM_IMX_BUS_DEVFREQ)	+= imx-bus.o
+ obj-$(CONFIG_ARM_IMX8M_DDRC_DEVFREQ)	+= imx8m-ddrc.o
+ obj-$(CONFIG_ARM_MEDIATEK_CCI_DEVFREQ)	+= mtk-cci-devfreq.o
+ obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ)	+= rk3399_dmc.o
++obj-$(CONFIG_ARM_RK3228_DMC_DEVFREQ)	+= rk3228_dmc.o
+ obj-$(CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ)	+= sun8i-a33-mbus.o
+ obj-$(CONFIG_ARM_TEGRA_DEVFREQ)		+= tegra30-devfreq.o
+
+diff --git a/include/dt-bindings/clock/rockchip-ddr.h b/include/dt-bindings/clock/rockchip-ddr.h
+new file mode 100644
+index 000000000..b065432e7
+--- /dev/null
++++ b/include/dt-bindings/clock/rockchip-ddr.h
+@@ -0,0 +1,63 @@
++/*
++ *
++ * Copyright (C) 2017 ROCKCHIP, Inc.
++ *
++ * This software is licensed under the terms of the GNU General Public
++ * License version 2, as published by the Free Software Foundation, and
++ * may be copied, distributed, and modified under those terms.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ */
++
++#ifndef _DT_BINDINGS_CLOCK_ROCKCHIP_DDR_H
++#define _DT_BINDINGS_CLOCK_ROCKCHIP_DDR_H
++
++#define DDR2_DEFAULT	(0)
++
++#define DDR3_800D	(0)	/* 5-5-5 */
++#define DDR3_800E	(1)	/* 6-6-6 */
++#define DDR3_1066E	(2)	/* 6-6-6 */
++#define DDR3_1066F	(3)	/* 7-7-7 */
++#define DDR3_1066G	(4)	/* 8-8-8 */
++#define DDR3_1333F	(5)	/* 7-7-7 */
++#define DDR3_1333G	(6)	/* 8-8-8 */
++#define DDR3_1333H	(7)	/* 9-9-9 */
++#define DDR3_1333J	(8)	/* 10-10-10 */
++#define DDR3_1600G	(9)	/* 8-8-8 */
++#define DDR3_1600H	(10)	/* 9-9-9 */
++#define DDR3_1600J	(11)	/* 10-10-10 */
++#define DDR3_1600K	(12)	/* 11-11-11 */
++#define DDR3_1866J	(13)	/* 10-10-10 */
++#define DDR3_1866K	(14)	/* 11-11-11 */
++#define DDR3_1866L	(15)	/* 12-12-12 */
++#define DDR3_1866M	(16)	/* 13-13-13 */
++#define DDR3_2133K	(17)	/* 11-11-11 */
++#define DDR3_2133L	(18)	/* 12-12-12 */
++#define DDR3_2133M	(19)	/* 13-13-13 */
++#define DDR3_2133N	(20)	/* 14-14-14 */
++#define DDR3_DEFAULT	(21)
++#define DDR_DDR2	(22)
++#define DDR_LPDDR	(23)
++#define DDR_LPDDR2	(24)
++
++#define DDR4_1600J	(0)	/* 10-10-10 */
++#define DDR4_1600K	(1)	/* 11-11-11 */
++#define DDR4_1600L	(2)	/* 12-12-12 */
++#define DDR4_1866L	(3)	/* 12-12-12 */
++#define DDR4_1866M	(4)	/* 13-13-13 */
++#define DDR4_1866N	(5)	/* 14-14-14 */
++#define DDR4_2133N	(6)	/* 14-14-14 */
++#define DDR4_2133P	(7)	/* 15-15-15 */
++#define DDR4_2133R	(8)	/* 16-16-16 */
++#define DDR4_2400P	(9)	/* 15-15-15 */
++#define DDR4_2400R	(10)	/* 16-16-16 */
++#define DDR4_2400U	(11)	/* 18-18-18 */
++#define DDR4_DEFAULT	(12)
++
++#define PAUSE_CPU_STACK_SIZE	16
++
++#endif
+diff --git a/include/dt-bindings/memory/rockchip,rk322x.h b/include/dt-bindings/memory/rockchip,rk322x.h
+new file mode 100644
+index 000000000..1ab3317d7
+--- /dev/null
++++ b/include/dt-bindings/memory/rockchip,rk322x.h
+@@ -0,0 +1,90 @@
++/*
++ * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++#ifndef _DT_BINDINGS_DRAM_ROCKCHIP_RK322X_H
++#define _DT_BINDINGS_DRAM_ROCKCHIP_RK322X_H
++
++#define DDR3_DS_34ohm		(1 << 1)
++#define DDR3_DS_40ohm		(0x0)
++
++#define LP2_DS_34ohm		(0x1)
++#define LP2_DS_40ohm		(0x2)
++#define LP2_DS_48ohm		(0x3)
++#define LP2_DS_60ohm		(0x4)
++#define LP2_DS_68_6ohm		(0x5)/* optional */
++#define LP2_DS_80ohm		(0x6)
++#define LP2_DS_120ohm		(0x7)/* optional */
++
++#define LP3_DS_34ohm		(0x1)
++#define LP3_DS_40ohm		(0x2)
++#define LP3_DS_48ohm		(0x3)
++#define LP3_DS_60ohm		(0x4)
++#define LP3_DS_80ohm		(0x6)
++#define LP3_DS_34D_40U		(0x9)
++#define LP3_DS_40D_48U		(0xa)
++#define LP3_DS_34D_48U		(0xb)
++
++#define DDR3_ODT_DIS		(0)
++#define DDR3_ODT_40ohm		((1 << 2) | (1 << 6))
++#define DDR3_ODT_60ohm		(1 << 2)
++#define DDR3_ODT_120ohm		(1 << 6)
++
++#define LP3_ODT_DIS		(0)
++#define LP3_ODT_60ohm		(1)
++#define LP3_ODT_120ohm		(2)
++#define LP3_ODT_240ohm		(3)
++
++#define PHY_DDR3_RON_RTT_DISABLE	(0)
++#define PHY_DDR3_RON_RTT_451ohm		(1)
++#define PHY_DDR3_RON_RTT_225ohm		(2)
++#define PHY_DDR3_RON_RTT_150ohm		(3)
++#define PHY_DDR3_RON_RTT_112ohm		(4)
++#define PHY_DDR3_RON_RTT_90ohm		(5)
++#define PHY_DDR3_RON_RTT_75ohm		(6)
++#define PHY_DDR3_RON_RTT_64ohm		(7)
++#define PHY_DDR3_RON_RTT_56ohm		(16)
++#define PHY_DDR3_RON_RTT_50ohm		(17)
++#define PHY_DDR3_RON_RTT_45ohm		(18)
++#define PHY_DDR3_RON_RTT_41ohm		(19)
++#define PHY_DDR3_RON_RTT_37ohm		(20)
++#define PHY_DDR3_RON_RTT_34ohm		(21)
++#define PHY_DDR3_RON_RTT_33ohm		(22)
++#define PHY_DDR3_RON_RTT_30ohm		(23)
++#define PHY_DDR3_RON_RTT_28ohm		(24)
++#define PHY_DDR3_RON_RTT_26ohm		(25)
++#define PHY_DDR3_RON_RTT_25ohm		(26)
++#define PHY_DDR3_RON_RTT_23ohm		(27)
++#define PHY_DDR3_RON_RTT_22ohm		(28)
++#define PHY_DDR3_RON_RTT_21ohm		(29)
++#define PHY_DDR3_RON_RTT_20ohm		(30)
++#define PHY_DDR3_RON_RTT_19ohm		(31)
++
++#define PHY_LP23_RON_RTT_DISABLE	(0)
++#define PHY_LP23_RON_RTT_480ohm		(1)
++#define PHY_LP23_RON_RTT_240ohm		(2)
++#define PHY_LP23_RON_RTT_160ohm		(3)
++#define PHY_LP23_RON_RTT_120ohm		(4)
++#define PHY_LP23_RON_RTT_96ohm		(5)
++#define PHY_LP23_RON_RTT_80ohm		(6)
++#define PHY_LP23_RON_RTT_68ohm		(7)
++#define PHY_LP23_RON_RTT_60ohm		(16)
++#define PHY_LP23_RON_RTT_53ohm		(17)
++#define PHY_LP23_RON_RTT_48ohm		(18)
++#define PHY_LP23_RON_RTT_43ohm		(19)
++#define PHY_LP23_RON_RTT_40ohm		(20)
++#define PHY_LP23_RON_RTT_37ohm		(21)
++#define PHY_LP23_RON_RTT_34ohm		(22)
++#define PHY_LP23_RON_RTT_32ohm		(23)
++#define PHY_LP23_RON_RTT_30ohm		(24)
++#define PHY_LP23_RON_RTT_28ohm		(25)
++#define PHY_LP23_RON_RTT_26ohm		(26)
++#define PHY_LP23_RON_RTT_25ohm		(27)
++#define PHY_LP23_RON_RTT_24ohm		(28)
++#define PHY_LP23_RON_RTT_22ohm		(29)
++#define PHY_LP23_RON_RTT_21ohm		(30)
++#define PHY_LP23_RON_RTT_20ohm		(31)
++
++#endif /* _DT_BINDINGS_DRAM_ROCKCHIP_RK322X_H */
+
+diff --git a/drivers/devfreq/rk3228_dmc.c b/drivers/devfreq/rk3228_dmc.c
+new file mode 100644
+index 00000000000..e8106f36404
+--- /dev/null
++++ b/drivers/devfreq/rk3228_dmc.c
+@@ -0,0 +1,709 @@
++// SPDX-License-Identifier: GPL-2.0-only
++/*
++ * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd.
++ * Author: Lin Huang <hl@rock-chips.com>
++ */
++
++#include <linux/arm-smccc.h>
++#include <linux/clk.h>
++#include <linux/delay.h>
++#include <linux/devfreq.h>
++#include <linux/devfreq-event.h>
++#include <linux/devfreq_cooling.h>
++#include <linux/interrupt.h>
++#include <linux/mfd/syscon.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/platform_device.h>
++#include <linux/pm_opp.h>
++#include <linux/regmap.h>
++#include <linux/regulator/consumer.h>
++#include <linux/rwsem.h>
++#include <linux/suspend.h>
++
++#include <soc/rockchip/rockchip_sip.h>
++
++#define DTS_PAR_OFFSET		(4096)
++
++#define RK3228_GRF_OS_REG2	0x5d0
++#define DDR_PCTL_MCFG		0x80
++#define DDR_PCTL_TCL		0xe8
++#define DDR_PCTL_TRAS		0xf0
++#define DDR_PCTL_TRCD		0xf8
++#define DDR_PCTL_TRP		0xdc
++
++/* MCFG */
++#define MDDR_LPDDR2_CLK_STOP_IDLE_SHIFT	24
++#define PD_IDLE_SHIFT			8
++#define MDDR_EN				(2 << 22)
++#define LPDDR2_EN			(3 << 22)
++#define LPDDR3_EN			(1 << 22)
++#define DDR2_EN				(0 << 5)
++#define DDR3_EN				(1 << 5)
++#define LPDDR2_S2			(0 << 6)
++#define LPDDR2_S4			(1 << 6)
++#define MDDR_LPDDR2_BL_2		(0 << 20)
++#define MDDR_LPDDR2_BL_4		(1 << 20)
++#define MDDR_LPDDR2_BL_8		(2 << 20)
++#define MDDR_LPDDR2_BL_16		(3 << 20)
++#define DDR2_DDR3_BL_4			0
++#define DDR2_DDR3_BL_8			1
++#define TFAW_SHIFT			18
++#define PD_EXIT_SLOW			(0 << 17)
++#define PD_EXIT_FAST			(1 << 17)
++#define PD_TYPE_SHIFT			16
++#define BURSTLENGTH_SHIFT		20
++
++#define MCFG_CR_2T_BIT(x)		((x & (1 << 3)) >> 3)
++#define MCFG_DDR_MASK			0x60
++#define MCFG_DDR_SHIFT			5
++#define MCFG_LPDDR_MASK			0xC00000
++#define MCFG_LPDDR_SHIFT		22
++
++#define MCFG_LPDDR2_S2			0x0
++#define MCFG_DDR3			0x1
++#define MCFG_LPDDR2_S4			0x2
++
++#define READ_DRAMTYPE_INFO(n)	(((n) >> 13) & 0x7)
++
++enum {
++	DDR4 = 0,
++	DDR2 = 2,
++	DDR3 = 3,
++	LPDDR2 = 5,
++	LPDDR3 = 6,
++	LPDDR4 = 7,
++	UNUSED = 0xFF
++};
++
++struct share_params {
++	u32 hz;
++	u32 lcdc_type;
++	u32 vop;
++	u32 vop_dclk_mode;
++	u32 sr_idle_en;
++	u32 addr_mcu_el3;
++	/*
++	 * 1: need to wait flag1
++	 * 0: never wait flag1
++	 */
++	u32 wait_flag1;
++	/*
++	 * 1: need to wait flag1
++	 * 0: never wait flag1
++	 */
++	u32 wait_flag0;
++	u32 complt_hwirq;
++	/* if need, add parameter after */
++};
++
++static struct share_params *ddr_psci_param = NULL;
++
++static const char * const rk3228_dts_timing[] = {
++	"dram_spd_bin",
++	"sr_idle",
++	"pd_idle",
++	"dram_dll_disb_freq",
++	"phy_dll_disb_freq",
++	"dram_odt_disb_freq",
++	"phy_odt_disb_freq",
++	"ddr3_drv",
++	"ddr3_odt",
++	"lpddr3_drv",
++	"lpddr3_odt",
++	"lpddr2_drv",
++	"phy_ddr3_clk_drv",
++	"phy_ddr3_cmd_drv",
++	"phy_ddr3_dqs_drv",
++	"phy_ddr3_odt",
++	"phy_lp23_clk_drv",
++	"phy_lp23_cmd_drv",
++	"phy_lp23_dqs_drv",
++	"phy_lp3_odt"
++};
++
++struct rk3228_ddr_dts_config_timing {
++	u32 dram_spd_bin;
++	u32 sr_idle;
++	u32 pd_idle;
++	u32 dram_dll_dis_freq;
++	u32 phy_dll_dis_freq;
++	u32 dram_odt_dis_freq;
++	u32 phy_odt_dis_freq;
++	u32 ddr3_drv;
++	u32 ddr3_odt;
++	u32 lpddr3_drv;
++	u32 lpddr3_odt;
++	u32 lpddr2_drv;
++	u32 phy_ddr3_clk_drv;
++	u32 phy_ddr3_cmd_drv;
++	u32 phy_ddr3_dqs_drv;
++	u32 phy_ddr3_odt;
++	u32 phy_lp23_clk_drv;
++	u32 phy_lp23_cmd_drv;
++	u32 phy_lp23_dqs_drv;
++	u32 phy_lp3_odt;
++};
++
++struct rk3228_devfreq {
++	struct devfreq *devfreq;
++	struct thermal_cooling_device *cooling;
++};
++
++struct rk3228_dmc {
++	struct device *dev;
++	void __iomem *iomem;
++
++	int rate;
++	struct devfreq_simple_ondemand_data ondemand_data;
++	struct devfreq_event_dev *edev;
++	struct clk *dmc_clk;
++	struct rk3228_devfreq devfreq;
++
++	uint32_t dram_type;
++
++	//struct mutex lock;
++
++	int (*set_auto_self_refresh)(u32 en);
++};
++
++static uint32_t of_get_rk3228_timings(struct device *dev,
++				      struct device_node *np, uint32_t *timing)
++{
++	struct device_node *np_tim;
++	uint32_t offset;
++	int ret = 0;
++	u32 idx;
++
++	// first 4kb page is reserved for interface parameters, we calculate an offset
++	// after which the timing parameters start
++	offset = DTS_PAR_OFFSET / sizeof(uint32_t);
++
++	np_tim = of_parse_phandle(np, "rockchip,dram_timing", 0);
++
++	if (!np_tim) {
++		ret = -EINVAL;
++		goto end;
++	}
++
++	for (idx = 0; idx < ARRAY_SIZE(rk3228_dts_timing); idx++)
++		ret |= of_property_read_u32(np_tim, rk3228_dts_timing[idx], &timing[offset + idx]);
++
++end:
++	if (ret)
++		dev_err(dev, "of_get_ddr_timings: fail\n");
++
++	of_node_put(np_tim);
++
++	return ret;
++
++}
++
++static int rockchip_ddr_set_auto_self_refresh(uint32_t en)
++{
++	struct arm_smccc_res res;
++
++	ddr_psci_param->sr_idle_en = en;
++
++	arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ,
++		      SHARE_PAGE_TYPE_DDR, 0, ROCKCHIP_SIP_CONFIG_DRAM_SET_AT_SR,
++		      0, 0, 0, 0, &res);
++
++	return res.a0;
++}
++
++static int rk3228_dmc_target(struct device *dev, unsigned long *freq,
++				 u32 flags)
++{
++
++	struct rk3228_dmc *rdev = dev_get_drvdata(dev);
++	struct dev_pm_opp *opp;
++	int err;
++
++	opp = devfreq_recommended_opp(dev, freq, flags);
++	if (IS_ERR(opp))
++		return PTR_ERR(opp);
++	dev_pm_opp_put(opp);
++
++	err = dev_pm_opp_set_rate(dev, *freq);
++	if (err)
++		return err;
++
++	rdev->rate = *freq;
++
++	return 0;
++
++}
++
++static int rk3228_dmc_get_dev_status(struct device *dev,
++					 struct devfreq_dev_status *stat)
++{
++	struct rk3228_dmc *rdev = dev_get_drvdata(dev);
++	struct devfreq_event_data edata;
++	int ret = 0;
++
++	ret = devfreq_event_get_event(rdev->edev, &edata);
++	if (ret < 0)
++		return ret;
++
++	stat->current_frequency = rdev->rate;
++	stat->busy_time = edata.load_count;
++	stat->total_time = edata.total_count;
++
++	return ret;
++}
++
++static int rk3228_dmc_get_cur_freq(struct device *dev, unsigned long *freq)
++{
++	struct rk3228_dmc *rdev = dev_get_drvdata(dev);
++
++	*freq = rdev->rate;
++
++	return 0;
++}
++
++static struct devfreq_dev_profile rk3228_devfreq_profile = {
++	.polling_ms	= 50,
++	.target		= rk3228_dmc_target,
++	.get_dev_status	= rk3228_dmc_get_dev_status,
++	.get_cur_freq	= rk3228_dmc_get_cur_freq,
++};
++
++void rk3228_devfreq_fini(struct rk3228_dmc *rdev)
++{
++	struct rk3228_devfreq *devfreq = &rdev->devfreq;
++
++	if (devfreq->cooling) {
++		devfreq_cooling_unregister(devfreq->cooling);
++		devfreq->cooling = NULL;
++	}
++
++	if (devfreq->devfreq) {
++		devm_devfreq_remove_device(rdev->dev, devfreq->devfreq);
++		devfreq->devfreq = NULL;
++	}
++
++}
++
++int rk3228_devfreq_init(struct rk3228_dmc *rdev)
++{
++	struct thermal_cooling_device *cooling;
++	struct device *dev = rdev->dev;
++	struct devfreq *devfreq;
++	struct rk3228_devfreq *rdevfreq = &rdev->devfreq;
++	const char *regulator_names[] = { "logic", NULL };
++
++	struct dev_pm_opp *opp;
++	unsigned long cur_freq;
++	int ret;
++
++	if (!device_property_present(dev, "operating-points-v2"))
++		/* Optional, continue without devfreq */
++		return 0;
++
++	ret = devm_pm_opp_set_clkname(dev, "ddr_sclk");
++	if (ret)
++		goto err_fini;
++
++	ret = devm_pm_opp_set_regulators(dev, regulator_names);
++
++	/* Continue if the optional regulator is missing */
++	if (ret && ret != -ENODEV)
++		goto err_fini;
++
++	ret = devm_pm_opp_of_add_table(dev);
++	if (ret)
++		goto err_fini;
++
++	cur_freq = 0;
++
++	opp = devfreq_recommended_opp(dev, &cur_freq, 0);
++	if (IS_ERR(opp)) {
++		ret = PTR_ERR(opp);
++		goto err_fini;
++	}
++
++	rk3228_devfreq_profile.initial_freq = cur_freq;
++	dev_pm_opp_put(opp);
++
++	rdev->ondemand_data.upthreshold = 15;
++	rdev->ondemand_data.downdifferential = 10;
++
++	devfreq = devm_devfreq_add_device(dev, &rk3228_devfreq_profile,
++					  DEVFREQ_GOV_SIMPLE_ONDEMAND, &rdev->ondemand_data);
++	if (IS_ERR(devfreq)) {
++		dev_err(dev, "Couldn't initialize GPU devfreq\n");
++		ret = PTR_ERR(devfreq);
++		goto err_fini;
++	}
++
++	rdevfreq->devfreq = devfreq;
++
++	cooling = of_devfreq_cooling_register(dev->of_node, devfreq);
++	if (IS_ERR(cooling))
++		dev_warn(dev, "Failed to register cooling device\n");
++	else
++		rdevfreq->cooling = cooling;
++
++	return 0;
++
++err_fini:
++	rk3228_devfreq_fini(rdev);
++	return ret;
++}
++
++static int rk3228_dmc_init(struct platform_device *pdev,
++			   struct rk3228_dmc *rdev)
++{
++	struct arm_smccc_res res;
++	u32 page_num;
++
++	// Count of pages to request to trust os, in pages of 4kb
++	page_num = DIV_ROUND_UP(sizeof(struct rk3228_ddr_dts_config_timing), PAGE_SIZE) + 1;
++
++	dev_dbg(&pdev->dev, "trying to allocate %d pages\n", page_num);
++
++	// Do request to trust OS. res.a0 contains error code, res.a1 the *physical*
++	// initial location of pages
++	arm_smccc_smc(
++		ROCKCHIP_SIP_SHARE_MEM,
++		page_num, SHARE_PAGE_TYPE_DDR, 0,
++		0, 0, 0, 0, &res
++	);
++
++	if (res.a0) {
++		dev_err(&pdev->dev, "no ATF memory for init\n");
++		return -ENOMEM;
++	}
++
++	dev_dbg(&pdev->dev, "allocated %d shared memory pages\n", page_num);
++
++	// Remap the physical location to kernel space using ioremap
++	ddr_psci_param = (struct share_params *)ioremap(res.a1, page_num << PAGE_SHIFT);
++
++	if (of_get_rk3228_timings(&pdev->dev, pdev->dev.of_node,
++				  (uint32_t *)ddr_psci_param))
++		return -ENOMEM;
++
++	// Reset Hz value
++	ddr_psci_param->hz = 0;
++
++	arm_smccc_smc(
++		ROCKCHIP_SIP_DRAM_FREQ,
++		SHARE_PAGE_TYPE_DDR, 0, ROCKCHIP_SIP_CONFIG_DRAM_INIT,
++		0, 0, 0, 0, &res
++	);
++
++	if (res.a0) {
++		dev_err(&pdev->dev, "rockchip_sip_config_dram_init error:%lx\n",
++			res.a0);
++		return -EINVAL;
++	}
++
++	dev_notice(&pdev->dev, "TEE DRAM configuration initialized\n");
++
++	rdev->set_auto_self_refresh = rockchip_ddr_set_auto_self_refresh;
++
++	return 0;
++
++}
++
++static __maybe_unused int rk3228_dmc_suspend(struct device *dev)
++{
++	struct rk3228_dmc *rdev = dev_get_drvdata(dev);
++	int ret = 0;
++
++	ret = devfreq_event_disable_edev(rdev->edev);
++	if (ret < 0) {
++		dev_err(dev, "failed to disable the devfreq-event devices\n");
++		return ret;
++	}
++
++	ret = devfreq_suspend_device(rdev->devfreq.devfreq);
++	if (ret < 0) {
++		dev_err(dev, "failed to suspend the devfreq devices\n");
++		return ret;
++	}
++
++	return 0;
++}
++
++static __maybe_unused int rk3228_dmc_resume(struct device *dev)
++{
++	struct rk3228_dmc *rdev = dev_get_drvdata(dev);
++	int ret = 0;
++
++	ret = devfreq_event_enable_edev(rdev->edev);
++	if (ret < 0) {
++		dev_err(dev, "failed to enable the devfreq-event devices\n");
++		return ret;
++	}
++
++	ret = devfreq_resume_device(rdev->devfreq.devfreq);
++	if (ret < 0) {
++		dev_err(dev, "failed to resume the devfreq devices\n");
++		return ret;
++	}
++	return ret;
++}
++
++static uint32_t rk3228_get_dram_type(struct device *dev, struct device_node *node_grf, struct rk3228_dmc *data)
++{
++
++	struct regmap *regmap_grf;
++	uint32_t dram_type;
++	uint32_t val;
++
++	dram_type = UNUSED;
++
++	regmap_grf = syscon_node_to_regmap(node_grf);
++
++	if (IS_ERR(regmap_grf)) {
++		dev_err(dev, "Cannot map rockchip,grf\n");
++		goto err;
++	}
++
++	regmap_read(regmap_grf, RK3228_GRF_OS_REG2, &val);
++	dram_type = READ_DRAMTYPE_INFO(val);
++
++err:
++
++	return dram_type;
++
++}
++
++static SIMPLE_DEV_PM_OPS(rk3228_dmc_pm, rk3228_dmc_suspend,
++			 rk3228_dmc_resume);
++
++static int rk3328_dmc_print_info(struct rk3228_dmc *rdev)
++{
++
++	u32 tcl;
++	u32 tras;
++	u32 trp;
++	u32 trcd;
++
++	u32 mcfg;
++	u32 reg_ddr_type1;
++	u32 reg_ddr_type2;
++
++	u32 dram_type;
++	u32 cr;
++
++	const char * const dram_types[] = {
++		"LPDDR2 S2",
++		"LPDDR2 S4",
++		"DDR3",
++		"LPDDR3",
++		"Unknown"
++	};
++
++	const char * const cr_types[] = {
++		"1T",
++		"2T"
++	};
++
++
++	tcl = readl(rdev->iomem + DDR_PCTL_TCL) & 0xf;
++	tras = readl(rdev->iomem + DDR_PCTL_TRAS) & 0x3f;
++	trp = readl(rdev->iomem + DDR_PCTL_TRP) & 0xf;
++	trcd = readl(rdev->iomem + DDR_PCTL_TRCD) & 0xf;
++
++	mcfg = readl(rdev->iomem + DDR_PCTL_MCFG);
++
++	reg_ddr_type1 = (mcfg & MCFG_DDR_MASK) >> MCFG_DDR_SHIFT;
++	reg_ddr_type2 = (mcfg & MCFG_LPDDR_MASK) >> MCFG_LPDDR_SHIFT;
++	cr = MCFG_CR_2T_BIT(mcfg);
++
++	switch (reg_ddr_type1) {
++		case MCFG_LPDDR2_S2:
++			dram_type = 0;
++			break;
++		case MCFG_LPDDR2_S4:
++			dram_type = 1;
++			break;
++		case MCFG_DDR3:
++			dram_type = reg_ddr_type2 == LPDDR3_EN ? 3 : 2;
++			break;
++		default:
++			dram_type = 4;
++			break;
++	}
++
++	dev_info(rdev->dev,
++		"memory type %s, timings (tCL, tRCD, tRP, tRAS): CL%d-%d-%d-%d command rate: %s (mcfg register: 0x%x)\n",
++		dram_types[dram_type], tcl, trcd, trp, tras, cr_types[cr], mcfg);
++
++	return 0;
++
++}
++
++static int rk3228_dmc_probe(struct platform_device *pdev)
++{
++	struct device *dev = &pdev->dev;
++	struct device_node *np = pdev->dev.of_node;
++	struct rk3228_dmc *data;
++	struct device_node *node_grf;
++	int ret;
++
++	data = devm_kzalloc(dev, sizeof(struct rk3228_dmc), GFP_KERNEL);
++	if (!data)
++		return -ENOMEM;
++
++	//mutex_init(&data->lock);
++
++	data->dmc_clk = devm_clk_get(dev, "ddr_sclk");
++	if (IS_ERR(data->dmc_clk)) {
++		if (PTR_ERR(data->dmc_clk) == -EPROBE_DEFER)
++			return -EPROBE_DEFER;
++
++		dev_err(dev, "Cannot get the clk dmc_clk\n");
++		return PTR_ERR(data->dmc_clk);
++	}
++
++	data->edev = devfreq_event_get_edev_by_phandle(dev, "devfreq-events", 0);
++	if (IS_ERR(data->edev))
++		return -EPROBE_DEFER;
++
++	data->iomem = devm_platform_ioremap_resource(pdev, 0);
++	if (IS_ERR(data->iomem)) {
++		dev_err(dev, "fail to ioremap iomem\n");
++		ret = PTR_ERR(data->iomem);
++		return ret;
++	}
++
++	data->dev = dev;
++
++	rk3328_dmc_print_info(data);
++
++	node_grf = of_parse_phandle(np, "rockchip,grf", 0);
++	if (node_grf) {
++
++		data->dram_type = rk3228_get_dram_type(dev, node_grf, data);
++
++		if (data->dram_type == LPDDR2) {
++			dev_warn(dev, "detected LPDDR2 memory\n");
++		} else if (data->dram_type == DDR2) {
++			dev_warn(dev, "detected DDR2 memory\n");
++		} else if (data->dram_type == DDR3) {
++			dev_info(dev, "detected DDR3 memory\n");
++		} else if (data->dram_type == LPDDR3) {
++			dev_info(dev, "detected LPDDR3 memory\n");
++		} else if (data->dram_type == DDR4) {
++			dev_info(dev, "detected DDR4 memory\n");
++		} else if (data->dram_type == LPDDR4) {
++			dev_info(dev, "detected LPDDR4 memory\n");
++		} else if (data->dram_type == UNUSED) {
++			dev_info(dev, "memory type not detected\n");
++		} else {
++			dev_info(dev, "unknown memory type: 0x%x\n", data->dram_type);
++		}
++
++	} else {
++
++		dev_warn(dev, "Cannot get rockchip,grf\n");
++		data->dram_type = UNUSED;
++
++	}
++
++	if (data->dram_type == DDR3 ||
++		data->dram_type == LPDDR3 ||
++		data->dram_type == DDR4 ||
++		data->dram_type == LPDDR4) {
++
++		ret = devfreq_event_enable_edev(data->edev);
++		if (ret < 0) {
++			dev_err(dev, "failed to enable devfreq-event devices\n");
++			return ret;
++		}
++
++		ret = rk3228_dmc_init(pdev, data);
++		if (ret)
++			return ret;
++
++
++
++		ret = rk3228_devfreq_init(data);
++		if (ret)
++			return ret;
++
++	} else {
++
++		dev_warn(dev, "detected memory type does not support clock scaling\n");
++
++	}
++
++	platform_set_drvdata(pdev, data);
++
++	return 0;
++
++}
++
++static void rk3228_dmc_remove(struct platform_device *pdev)
++{
++	struct rk3228_dmc *rdev = dev_get_drvdata(&pdev->dev);
++
++	/*
++	 * Before remove the opp table we need to unregister the opp notifier.
++	 */
++	rk3228_devfreq_fini(rdev);
++
++	if (ddr_psci_param)
++		iounmap(ddr_psci_param);
++
++	if (rdev->iomem)
++		iounmap(rdev->iomem);
++
++	//return 0;
++}
++
++static const struct of_device_id rk3228_dmc_of_match[] = {
++	{ .compatible = "rockchip,rk3228-dmc" },
++	{ },
++};
++MODULE_DEVICE_TABLE(of, rk3228_dmc_of_match);
++
++static struct platform_driver rk3228_dmc_driver = {
++	.probe	= rk3228_dmc_probe,
++	.remove = rk3228_dmc_remove,
++	.driver = {
++		.name	= "rk3228-dmc",
++		.pm	= &rk3228_dmc_pm,
++		.of_match_table = rk3228_dmc_of_match,
++	},
++};
++module_platform_driver(rk3228_dmc_driver);
++
++#ifdef CONFIG_ARM
++static __init int sip_firmware_init(void)
++{
++	struct arm_smccc_res res;
++
++	/*
++	 * OP-TEE works on kernel 3.10 and 4.4 and we have different sip
++	 * implement. We should tell OP-TEE the current rockchip sip version.
++	 */
++
++	/*
++	 *
++	 * 	res = __invoke_sip_fn_smc(ROCKCHIP_SIP_SIP_VERSION, ROCKCHIP_SIP_IMPLEMENT_V2,
++				  SECURE_REG_WR, 0);
++
++		arm_smccc_smc(function_id, arg0, arg1, arg2, 0, 0, 0, 0, &res);
++	*/
++
++	arm_smccc_smc(ROCKCHIP_SIP_SIP_VERSION, ROCKCHIP_SIP_IMPLEMENT_V2, SECURE_REG_WR, 0, 0, 0, 0, 0, &res);
++
++	if (res.a0)
++		pr_err("%s: set rockchip sip version v2 failed\n", __func__);
++
++	pr_notice("Rockchip SIP initialized, version 0x%lx\n", res.a1);
++
++	return 0;
++}
++arch_initcall(sip_firmware_init);
++#endif
++
++MODULE_LICENSE("GPL v2");
++MODULE_AUTHOR("Lin Huang <hl@rock-chips.com>");
++MODULE_DESCRIPTION("RK3228 dmcfreq driver with devfreq framework");
+
+--
+2.25.1
diff --git a/projects/Rockchip/devices/RK322X/patches/linux/default/linux-4004-esp8089-kernel-driver.patch b/projects/Rockchip/devices/RK322X/patches/linux/default/linux-4004-esp8089-kernel-driver.patch
new file mode 100644
index 0000000000..212a31ad2e
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/patches/linux/default/linux-4004-esp8089-kernel-driver.patch
@@ -0,0 +1,10930 @@
+From 2d6165af6e9d5ed5026cdf250536c0a00d84fd75 Mon Sep 17 00:00:00 2001
+From: Paolo Sabatino <paolo.sabatino@gmail.com>
+Date: Sat, 1 Oct 2022 12:43:53 +0000
+Subject: [PATCH] add esp8089 kernel driver
+
+---
+ drivers/net/wireless/Kconfig                  |    1 +
+ drivers/net/wireless/Makefile                 |    1 +
+ drivers/net/wireless/esp8089/.gitignore       |    7 +
+ drivers/net/wireless/esp8089/Kconfig          |   13 +
+ drivers/net/wireless/esp8089/LICENSE          |  340 +++
+ drivers/net/wireless/esp8089/Makefile         |    7 +
+ drivers/net/wireless/esp8089/Makefile.old     |   99 +
+ drivers/net/wireless/esp8089/README.md        |   31 +
+ drivers/net/wireless/esp8089/esp_ctrl.c       |  801 ++++++
+ drivers/net/wireless/esp8089/esp_ctrl.h       |   58 +
+ drivers/net/wireless/esp8089/esp_debug.c      |  297 ++
+ drivers/net/wireless/esp8089/esp_debug.h      |  101 +
+ drivers/net/wireless/esp8089/esp_ext.c        |  542 ++++
+ drivers/net/wireless/esp8089/esp_ext.h        |  100 +
+ drivers/net/wireless/esp8089/esp_file.c       |  258 ++
+ drivers/net/wireless/esp8089/esp_file.h       |   43 +
+ drivers/net/wireless/esp8089/esp_init_data.h  |    7 +
+ drivers/net/wireless/esp8089/esp_io.c         |  639 +++++
+ drivers/net/wireless/esp8089/esp_mac80211.c   | 1727 ++++++++++++
+ drivers/net/wireless/esp8089/esp_mac80211.h   |   38 +
+ drivers/net/wireless/esp8089/esp_main.c       |  263 ++
+ drivers/net/wireless/esp8089/esp_path.h       |    6 +
+ drivers/net/wireless/esp8089/esp_pub.h        |  222 ++
+ drivers/net/wireless/esp8089/esp_sif.h        |  207 ++
+ drivers/net/wireless/esp8089/esp_sip.c        | 2418 +++++++++++++++++
+ drivers/net/wireless/esp8089/esp_sip.h        |  171 ++
+ drivers/net/wireless/esp8089/esp_utils.c      |  262 ++
+ drivers/net/wireless/esp8089/esp_utils.h      |   41 +
+ drivers/net/wireless/esp8089/esp_version.h    |    1 +
+ drivers/net/wireless/esp8089/esp_wl.h         |   63 +
+ drivers/net/wireless/esp8089/esp_wmac.h       |   92 +
+ .../wireless/esp8089/firmware/LICENSE-2.0.txt |  203 ++
+ drivers/net/wireless/esp8089/sdio_sif_esp.c   |  811 ++++++
+ drivers/net/wireless/esp8089/sip2_common.h    |  475 ++++
+ .../net/wireless/esp8089/slc_host_register.h  |  271 ++
+ 35 files changed, 10616 insertions(+)
+ create mode 100644 drivers/net/wireless/esp8089/.gitignore
+ create mode 100644 drivers/net/wireless/esp8089/Kconfig
+ create mode 100644 drivers/net/wireless/esp8089/LICENSE
+ create mode 100644 drivers/net/wireless/esp8089/Makefile
+ create mode 100644 drivers/net/wireless/esp8089/Makefile.old
+ create mode 100644 drivers/net/wireless/esp8089/README.md
+ create mode 100644 drivers/net/wireless/esp8089/esp_ctrl.c
+ create mode 100644 drivers/net/wireless/esp8089/esp_ctrl.h
+ create mode 100644 drivers/net/wireless/esp8089/esp_debug.c
+ create mode 100644 drivers/net/wireless/esp8089/esp_debug.h
+ create mode 100644 drivers/net/wireless/esp8089/esp_ext.c
+ create mode 100644 drivers/net/wireless/esp8089/esp_ext.h
+ create mode 100644 drivers/net/wireless/esp8089/esp_file.c
+ create mode 100644 drivers/net/wireless/esp8089/esp_file.h
+ create mode 100644 drivers/net/wireless/esp8089/esp_init_data.h
+ create mode 100644 drivers/net/wireless/esp8089/esp_io.c
+ create mode 100644 drivers/net/wireless/esp8089/esp_mac80211.c
+ create mode 100644 drivers/net/wireless/esp8089/esp_mac80211.h
+ create mode 100644 drivers/net/wireless/esp8089/esp_main.c
+ create mode 100644 drivers/net/wireless/esp8089/esp_path.h
+ create mode 100644 drivers/net/wireless/esp8089/esp_pub.h
+ create mode 100644 drivers/net/wireless/esp8089/esp_sif.h
+ create mode 100644 drivers/net/wireless/esp8089/esp_sip.c
+ create mode 100644 drivers/net/wireless/esp8089/esp_sip.h
+ create mode 100644 drivers/net/wireless/esp8089/esp_utils.c
+ create mode 100644 drivers/net/wireless/esp8089/esp_utils.h
+ create mode 100644 drivers/net/wireless/esp8089/esp_version.h
+ create mode 100644 drivers/net/wireless/esp8089/esp_wl.h
+ create mode 100644 drivers/net/wireless/esp8089/esp_wmac.h
+ create mode 100644 drivers/net/wireless/esp8089/firmware/LICENSE-2.0.txt
+ create mode 100644 drivers/net/wireless/esp8089/sdio_sif_esp.c
+ create mode 100644 drivers/net/wireless/esp8089/sip2_common.h
+ create mode 100644 drivers/net/wireless/esp8089/slc_host_register.h
+
+diff --git a/drivers/net/wireless/Kconfig b/drivers/net/wireless/Kconfig
+index cb1c15012dd0..de5e37846397 100644
+--- a/drivers/net/wireless/Kconfig
++++ b/drivers/net/wireless/Kconfig
+@@ -37,6 +37,7 @@ source "drivers/net/wireless/st/Kconfig"
+ source "drivers/net/wireless/ti/Kconfig"
+ source "drivers/net/wireless/zydas/Kconfig"
+ source "drivers/net/wireless/quantenna/Kconfig"
++source "drivers/net/wireless/esp8089/Kconfig"
+
+ config PCMCIA_RAYCS
+	tristate "Aviator/Raytheon 2.4GHz wireless support"
+diff --git a/drivers/net/wireless/Makefile b/drivers/net/wireless/Makefile
+index a61cf6c90343..92ffd2cef51c 100644
+--- a/drivers/net/wireless/Makefile
++++ b/drivers/net/wireless/Makefile
+@@ -22,6 +22,7 @@ obj-$(CONFIG_WLAN_VENDOR_SILABS) += silabs/
+ obj-$(CONFIG_WLAN_VENDOR_ST) += st/
+ obj-$(CONFIG_WLAN_VENDOR_TI) += ti/
+ obj-$(CONFIG_WLAN_VENDOR_ZYDAS) += zydas/
++obj-$(CONFIG_ESP8089) += esp8089/
+
+ # 16-bit wireless PCMCIA client drivers
+ obj-$(CONFIG_PCMCIA_RAYCS)	+= ray_cs.o
+diff --git a/drivers/net/wireless/esp8089/.gitignore b/drivers/net/wireless/esp8089/.gitignore
+new file mode 100644
+index 000000000000..eae6529085d0
+--- /dev/null
++++ b/drivers/net/wireless/esp8089/.gitignore
+@@ -0,0 +1,7 @@
++*.cmd
++*.o
++Module.symvers
++modules.order
++.tmp_versions
++*.ko
++*.mod.c
+diff --git a/drivers/net/wireless/esp8089/Kconfig b/drivers/net/wireless/esp8089/Kconfig
+new file mode 100644
+index 000000000000..8db1fc54712d
+--- /dev/null
++++ b/drivers/net/wireless/esp8089/Kconfig
+@@ -0,0 +1,13 @@
++config ESP8089
++	tristate "Espressif ESP8089 SDIO WiFi"
++	depends on MAC80211
++	help
++	  ESP8089 is a low-budget 2.4GHz WiFi chip by Espressif, used in many
++	  cheap tablets with Allwinner or Rockchip SoC
++
++config ESP8089_DEBUG_FS
++	bool "Enable DebugFS support for ESP8089"
++	depends on ESP8089
++	default y
++	help
++	  DebugFS support for ESP8089
+diff --git a/drivers/net/wireless/esp8089/LICENSE b/drivers/net/wireless/esp8089/LICENSE
+new file mode 100644
+index 000000000000..d6a93266f748
+--- /dev/null
++++ b/drivers/net/wireless/esp8089/LICENSE
+@@ -0,0 +1,340 @@
++GNU GENERAL PUBLIC LICENSE
++                       Version 2, June 1991
++
++ Copyright (C) 1989, 1991 Free Software Foundation, Inc., <http://fsf.org/>
++ 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
++ Everyone is permitted to copy and distribute verbatim copies
++ of this license document, but changing it is not allowed.
++
++                            Preamble
++
++  The licenses for most software are designed to take away your
++freedom to share and change it.  By contrast, the GNU General Public
++License is intended to guarantee your freedom to share and change free
++software--to make sure the software is free for all its users.  This
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++Foundation's software and to any other program whose authors commit to
++using it.  (Some other Free Software Foundation software is covered by
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++your programs, too.
++
++  When we speak of free software, we are referring to freedom, not
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++   TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
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++  `Gnomovision' (which makes passes at compilers) written by James Hacker.
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++  {signature of Ty Coon}, 1 April 1989
++  Ty Coon, President of Vice
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++consider it more useful to permit linking proprietary applications with the
++library.  If this is what you want to do, use the GNU Lesser General
++Public License instead of this License.
++
+diff --git a/drivers/net/wireless/esp8089/Makefile b/drivers/net/wireless/esp8089/Makefile
+new file mode 100644
+index 000000000000..36decfd20ecd
+--- /dev/null
++++ b/drivers/net/wireless/esp8089/Makefile
+@@ -0,0 +1,7 @@
++MODULE_NAME = esp8089
++
++$(MODULE_NAME)-y := esp_debug.o sdio_sif_esp.o esp_io.o \
++    esp_file.o esp_main.o esp_sip.o esp_ext.o esp_ctrl.o \
++    esp_mac80211.o esp_debug.o esp_utils.o
++
++obj-$(CONFIG_ESP8089) := esp8089.o
+diff --git a/drivers/net/wireless/esp8089/Makefile.old b/drivers/net/wireless/esp8089/Makefile.old
+new file mode 100644
+index 000000000000..b7b1a47b159c
+--- /dev/null
++++ b/drivers/net/wireless/esp8089/Makefile.old
+@@ -0,0 +1,99 @@
++MODNAME = esp8089
++
++# By default, we try to compile the modules for the currently running
++# kernel.  But it's the first approximation, as we will re-read the
++# version from the kernel sources.
++KVERS_UNAME ?= $(shell uname -r)
++
++# KBUILD is the path to the Linux kernel build tree.  It is usually the
++# same as the kernel source tree, except when the kernel was compiled in
++# a separate directory.
++KBUILD ?= $(shell readlink -f /lib/modules/$(KVERS_UNAME)/build)
++
++ifeq (,$(KBUILD))
++$(error Kernel build tree not found - please set KBUILD to configured kernel)
++endif
++
++KCONFIG := $(KBUILD)/.config
++ifeq (,$(wildcard $(KCONFIG)))
++$(error No .config found in $(KBUILD), please set KBUILD to configured kernel)
++endif
++
++ifneq (,$(wildcard $(KBUILD)/include/linux/version.h))
++ifneq (,$(wildcard $(KBUILD)/include/generated/uapi/linux/version.h))
++$(error Multiple copies of version.h found, please clean your build tree)
++endif
++endif
++
++# Kernel Makefile doesn't always know the exact kernel version, so we
++# get it from the kernel headers instead and pass it to make.
++VERSION_H := $(KBUILD)/include/generated/utsrelease.h
++ifeq (,$(wildcard $(VERSION_H)))
++VERSION_H := $(KBUILD)/include/linux/utsrelease.h
++endif
++ifeq (,$(wildcard $(VERSION_H)))
++VERSION_H := $(KBUILD)/include/linux/version.h
++endif
++ifeq (,$(wildcard $(VERSION_H)))
++$(error Please run 'make modules_prepare' in $(KBUILD))
++endif
++
++KVERS := $(shell sed -ne 's/"//g;s/^\#define UTS_RELEASE //p' $(VERSION_H))
++
++ifeq (,$(KVERS))
++$(error Cannot find UTS_RELEASE in $(VERSION_H), please report)
++endif
++
++INST_DIR = /lib/modules/$(KVERS)/misc
++
++SRC_DIR=$(shell pwd)
++
++include $(KCONFIG)
++
++EXTRA_CFLAGS += -DCONFIG_ESP8089_DEBUG_FS
++
++OBJS = esp_debug.o sdio_sif_esp.o esp_io.o \
++    esp_file.o esp_main.o esp_sip.o esp_ext.o esp_ctrl.o \
++    esp_mac80211.o esp_debug.o esp_utils.o esp_pm.o
++
++all: config_check modules
++
++MODULE := $(MODNAME).ko
++obj-m := $(MODNAME).o
++
++$(MODNAME)-objs := $(OBJS)
++
++config_check:
++	@if [ -z "$(CONFIG_WIRELESS_EXT)$(CONFIG_NET_RADIO)" ]; then \
++		echo; echo; \
++		echo "*** WARNING: This kernel lacks wireless extensions."; \
++		echo "Wireless drivers will not work properly."; \
++		echo; echo; \
++	fi
++
++modules:
++	$(MAKE) -C $(KBUILD) M=$(SRC_DIR)
++
++$(MODULE):
++	$(MAKE) modules
++
++clean:
++	rm -f *.o *.ko .*.cmd *.mod.c *.symvers modules.order
++	rm -rf .tmp_versions
++
++install: config_check $(MODULE)
++	@/sbin/modinfo $(MODULE) | grep -q "^vermagic: *$(KVERS) " || \
++		{ echo "$(MODULE)" is not for Linux $(KVERS); exit 1; }
++	mkdir -p -m 755 $(DESTDIR)$(INST_DIR)
++	install -m 0644 $(MODULE) $(DESTDIR)$(INST_DIR)
++ifndef DESTDIR
++	-/sbin/depmod -a $(KVERS)
++endif
++
++uninstall:
++	rm -f $(DESTDIR)$(INST_DIR)/$(MODULE)
++ifndef DESTDIR
++	-/sbin/depmod -a $(KVERS)
++endif
++
++.PHONY: all modules clean install config_check
+diff --git a/drivers/net/wireless/esp8089/README.md b/drivers/net/wireless/esp8089/README.md
+new file mode 100644
+index 000000000000..56b40db272f3
+--- /dev/null
++++ b/drivers/net/wireless/esp8089/README.md
+@@ -0,0 +1,31 @@
++esp8089
++======
++
++ESP8089 Linux driver
++
++v1.9 imported from the Rockchip Linux kernel github repo
++
++Modified to build as a standalone module for SDIO devices.
++
++
++
++
++Building:
++
++ make
++
++Using:
++
++Must load mac80211.ko first if not baked in.
++
++ sudo modprobe esp8089.ko
++
++If you get a wlan interface, but scanning shows no networks try using:
++
++ sudo modprobe esp8089.ko config=crystal_26M_en=1
++
++or:
++
++ sudo modprobe esp8089.ko config=crystal_26M_en=2
++
++To load the module.
+diff --git a/drivers/net/wireless/esp8089/esp_ctrl.c b/drivers/net/wireless/esp8089/esp_ctrl.c
+new file mode 100644
+index 000000000000..a19d2437dd82
+--- /dev/null
++++ b/drivers/net/wireless/esp8089/esp_ctrl.c
+@@ -0,0 +1,801 @@
++/*
++ * Copyright (c) 2009 - 2014 Espressif System.
++ *
++ * SIP ctrl packet parse and pack
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++
++#include <net/mac80211.h>
++#include <net/cfg80211.h>
++#include <linux/skbuff.h>
++#include <linux/bitops.h>
++#include <linux/firmware.h>
++
++#include "esp_pub.h"
++#include "esp_sip.h"
++#include "esp_ctrl.h"
++#include "esp_sif.h"
++#include "esp_debug.h"
++#include "esp_wmac.h"
++#include "esp_utils.h"
++#include "esp_wl.h"
++#include "esp_file.h"
++#include "esp_path.h"
++#ifdef TEST_MODE
++#include "testmode.h"
++#endif				/* TEST_MODE */
++#include "esp_version.h"
++
++extern struct completion *gl_bootup_cplx;
++
++static void esp_tx_ba_session_op(struct esp_sip *sip,
++				 struct esp_node *node,
++				 trc_ampdu_state_t state, u8 tid)
++{
++	struct esp_tx_tid *txtid;
++
++	txtid = &node->tid[tid];
++	if (state == TRC_TX_AMPDU_STOPPED) {
++		if (txtid->state == ESP_TID_STATE_OPERATIONAL) {
++			esp_dbg(ESP_DBG_TXAMPDU,
++				"%s tid %d TXAMPDU GOT STOP EVT\n",
++				__func__, tid);
++
++			spin_lock_bh(&sip->epub->tx_ampdu_lock);
++			txtid->state = ESP_TID_STATE_WAIT_STOP;
++			spin_unlock_bh(&sip->epub->tx_ampdu_lock);
++			ieee80211_stop_tx_ba_session(node->sta, (u16) tid);
++		} else {
++			esp_dbg(ESP_DBG_TXAMPDU,
++				"%s tid %d TXAMPDU GOT STOP EVT IN WRONG STATE %d\n",
++				__func__, tid, txtid->state);
++		}
++	} else if (state == TRC_TX_AMPDU_OPERATIONAL) {
++		if (txtid->state == ESP_TID_STATE_STOP) {
++			esp_dbg(ESP_DBG_TXAMPDU,
++				"%s tid %d TXAMPDU GOT OPERATIONAL\n",
++				__func__, tid);
++
++			spin_lock_bh(&sip->epub->tx_ampdu_lock);
++			txtid->state = ESP_TID_STATE_TRIGGER;
++			spin_unlock_bh(&sip->epub->tx_ampdu_lock);
++			ieee80211_start_tx_ba_session(node->sta, (u16) tid,
++						      0);
++
++		} else if (txtid->state == ESP_TID_STATE_OPERATIONAL) {
++			sip_send_ampdu_action(sip->epub,
++					      SIP_AMPDU_TX_OPERATIONAL,
++					      node->sta->addr, tid,
++					      node->ifidx, 0);
++		} else {
++			esp_dbg(ESP_DBG_TXAMPDU,
++				"%s tid %d TXAMPDU GOT OPERATIONAL EVT IN WRONG STATE %d\n",
++				__func__, tid, txtid->state);
++		}
++	}
++}
++
++int sip_parse_events(struct esp_sip *sip, u8 * buf)
++{
++	struct sip_hdr *hdr = (struct sip_hdr *) buf;
++
++	switch (hdr->c_evtid) {
++	case SIP_EVT_TARGET_ON:{
++			/* use rx work queue to send... */
++			if (atomic_read(&sip->state) == SIP_PREPARE_BOOT
++			    || atomic_read(&sip->state) == SIP_BOOT) {
++				atomic_set(&sip->state, SIP_SEND_INIT);
++				queue_work(sip->epub->esp_wkq,
++					   &sip->rx_process_work);
++			} else {
++				esp_dbg(ESP_DBG_ERROR,
++					"%s boot during wrong state %d\n",
++					__func__,
++					atomic_read(&sip->state));
++			}
++			break;
++		}
++
++	case SIP_EVT_BOOTUP:{
++			struct sip_evt_bootup2 *bootup_evt =
++			    (struct sip_evt_bootup2 *) (buf +
++							SIP_CTRL_HDR_LEN);
++			if (sip->rawbuf)
++				kfree(sip->rawbuf);
++
++			sip_post_init(sip, bootup_evt);
++
++			if (gl_bootup_cplx)
++				complete(gl_bootup_cplx);
++
++			break;
++		}
++	case SIP_EVT_RESETTING:{
++			sip->epub->wait_reset = 1;
++			if (gl_bootup_cplx)
++				complete(gl_bootup_cplx);
++			break;
++		}
++	case SIP_EVT_SLEEP:{
++			//atomic_set(&sip->epub->ps.state, ESP_PM_ON);
++			break;
++		}
++	case SIP_EVT_TXIDLE:{
++			//struct sip_evt_txidle *txidle = (struct sip_evt_txidle *)(buf + SIP_CTRL_HDR_LEN);
++			//sip_txdone_clear(sip, txidle->last_seq);
++			break;
++		}
++
++	case SIP_EVT_SCAN_RESULT:{
++			struct sip_evt_scan_report *report =
++			    (struct sip_evt_scan_report *) (buf +
++							    SIP_CTRL_HDR_LEN);
++			if (atomic_read(&sip->epub->wl.off)) {
++				esp_dbg(ESP_DBG_ERROR,
++					"%s scan result while wlan off\n",
++					__func__);
++				return 0;
++			}
++			sip_scandone_process(sip, report);
++
++			break;
++		}
++
++	case SIP_EVT_ROC:{
++			struct sip_evt_roc *report =
++			    (struct sip_evt_roc *) (buf +
++						    SIP_CTRL_HDR_LEN);
++			esp_rocdone_process(sip->epub->hw, report);
++			break;
++		}
++
++
++#ifdef ESP_RX_COPYBACK_TEST
++
++	case SIP_EVT_COPYBACK:{
++			u32 len = hdr->len - SIP_CTRL_HDR_LEN;
++
++			esp_dbg(ESP_DBG_TRACE,
++				"%s copyback len %d   seq %u\n", __func__,
++				len, hdr->seq);
++
++			memcpy(copyback_buf + copyback_offset,
++			       pkt->buf + SIP_CTRL_HDR_LEN, len);
++			copyback_offset += len;
++
++			//show_buf(pkt->buf, 256);
++
++			//how about totlen % 256 == 0??
++			if (hdr->hdr.len < 256) {
++				kfree(copyback_buf);
++			}
++		}
++		break;
++#endif				/* ESP_RX_COPYBACK_TEST */
++	case SIP_EVT_CREDIT_RPT:
++		break;
++
++#ifdef TEST_MODE
++	case SIP_EVT_WAKEUP:{
++			u8 check_str[12];
++			struct sip_evt_wakeup *wakeup_evt =
++			    (struct sip_evt_wakeup *) (buf +
++						       SIP_CTRL_HDR_LEN);
++			sprintf((char *) &check_str, "%d",
++				wakeup_evt->check_data);
++			esp_test_cmd_event(TEST_CMD_WAKEUP,
++					   (char *) &check_str);
++			break;
++		}
++
++	case SIP_EVT_DEBUG:{
++			u8 check_str[640];
++			sip_parse_event_debug(sip->epub, buf, check_str);
++			esp_dbg(ESP_DBG_TRACE, "%s", check_str);
++			esp_test_cmd_event(TEST_CMD_DEBUG,
++					   (char *) &check_str);
++			break;
++		}
++
++	case SIP_EVT_LOOPBACK:{
++			u8 check_str[12];
++			struct sip_evt_loopback *loopback_evt =
++			    (struct sip_evt_loopback *) (buf +
++							 SIP_CTRL_HDR_LEN);
++			esp_dbg(ESP_DBG_LOG, "%s loopback len %d seq %u\n",
++				__func__, hdr->len, hdr->seq);
++
++			if (loopback_evt->pack_id != get_loopback_id()) {
++				sprintf((char *) &check_str,
++					"seq id error %d, expect %d",
++					loopback_evt->pack_id,
++					get_loopback_id());
++				esp_test_cmd_event(TEST_CMD_LOOPBACK,
++						   (char *) &check_str);
++			}
++
++			if ((loopback_evt->pack_id + 1) <
++			    get_loopback_num()) {
++				inc_loopback_id();
++				sip_send_loopback_mblk(sip,
++						       loopback_evt->txlen,
++						       loopback_evt->rxlen,
++						       get_loopback_id());
++			} else {
++				sprintf((char *) &check_str, "test over!");
++				esp_test_cmd_event(TEST_CMD_LOOPBACK,
++						   (char *) &check_str);
++			}
++			break;
++		}
++#endif				/*TEST_MODE */
++
++	case SIP_EVT_SNPRINTF_TO_HOST:{
++			u8 *p =
++			    (buf + sizeof(struct sip_hdr) + sizeof(u16));
++			u16 *len = (u16 *) (buf + sizeof(struct sip_hdr));
++			char test_res_str[560];
++			sprintf(test_res_str,
++				"esp_host:%llx\nesp_target: %.*s",
++				DRIVER_VER, *len, p);
++
++			esp_dbg(ESP_DBG_TRACE, "%s\n", test_res_str);
++			if (*len
++			    && sip->epub->sdio_state ==
++			    ESP_SDIO_STATE_FIRST_INIT) {
++				char filename[256];
++				if (mod_eagle_path_get() == NULL)
++					sprintf(filename, "%s/%s", FWPATH,
++						"test_results");
++				else
++					sprintf(filename, "%s/%s",
++						mod_eagle_path_get(),
++						"test_results");
++				esp_dbg(ESP_DBG_TRACE,
++					"SNPRINTF TO HOST: %s\n",
++					test_res_str);
++			}
++			break;
++		}
++	case SIP_EVT_TRC_AMPDU:{
++			struct sip_evt_trc_ampdu *ep =
++			    (struct sip_evt_trc_ampdu *) (buf +
++							  SIP_CTRL_HDR_LEN);
++			struct esp_node *node = NULL;
++			int i = 0;
++
++			if (atomic_read(&sip->epub->wl.off)) {
++				esp_dbg(ESP_DBG_ERROR,
++					"%s scan result while wlan off\n",
++					__func__);
++				return 0;
++			}
++
++			node = esp_get_node_by_addr(sip->epub, ep->addr);
++			if (node == NULL)
++				break;
++			for (i = 0; i < 8; i++) {
++				if (ep->tid & (1 << i)) {
++					esp_tx_ba_session_op(sip, node,
++							     ep->state, i);
++				}
++			}
++			break;
++		}
++
++#ifdef TEST_MODE
++	case SIP_EVT_EP:{
++			char *ep = (char *) (buf + SIP_CTRL_HDR_LEN);
++			static int counter = 0;
++
++			esp_dbg(ESP_ATE, "%s EVT_EP \n\n", __func__);
++			if (counter++ < 2) {
++				esp_dbg(ESP_ATE, "ATE: %s \n", ep);
++			}
++
++			esp_test_ate_done_cb(ep);
++
++			break;
++		}
++#endif				/*TEST_MODE */
++
++	case SIP_EVT_INIT_EP:{
++			char *ep = (char *) (buf + SIP_CTRL_HDR_LEN);
++			esp_dbg(ESP_ATE, "Phy Init: %s \n", ep);
++			break;
++		}
++
++	case SIP_EVT_NOISEFLOOR:{
++			struct sip_evt_noisefloor *ep =
++			    (struct sip_evt_noisefloor *) (buf +
++							   SIP_CTRL_HDR_LEN);
++			atomic_set(&sip->noise_floor, ep->noise_floor);
++			break;
++		}
++	default:
++		break;
++	}
++
++	return 0;
++}
++
++#include "esp_init_data.h"
++
++void sip_send_chip_init(struct esp_sip *sip)
++{
++	size_t size = 0;
++	size = sizeof(esp_init_data);
++
++	esp_conf_upload_second(esp_init_data, size);
++
++	atomic_sub(1, &sip->tx_credits);
++
++	sip_send_cmd(sip, SIP_CMD_INIT, size, (void *) esp_init_data);
++
++}
++
++int sip_send_config(struct esp_pub *epub, struct ieee80211_conf *conf)
++{
++	struct sk_buff *skb = NULL;
++	struct sip_cmd_config *configcmd;
++
++	skb =
++	    sip_alloc_ctrl_skbuf(epub->sip,
++				 sizeof(struct sip_cmd_config) +
++				 sizeof(struct sip_hdr), SIP_CMD_CONFIG);
++	if (!skb)
++		return -EINVAL;
++	esp_dbg(ESP_DBG_TRACE, "%s config center freq %d\n", __func__,
++		conf->chandef.chan->center_freq);
++	configcmd =
++	    (struct sip_cmd_config *) (skb->data + sizeof(struct sip_hdr));
++	configcmd->center_freq = conf->chandef.chan->center_freq;
++	configcmd->duration = 0;
++	return sip_cmd_enqueue(epub->sip, skb, ENQUEUE_PRIOR_TAIL);
++}
++
++int sip_send_bss_info_update(struct esp_pub *epub, struct esp_vif *evif,
++			     u8 * bssid, int assoc)
++{
++	struct sk_buff *skb = NULL;
++	struct sip_cmd_bss_info_update *bsscmd;
++
++	skb =
++	    sip_alloc_ctrl_skbuf(epub->sip,
++				 sizeof(struct sip_cmd_bss_info_update) +
++				 sizeof(struct sip_hdr),
++				 SIP_CMD_BSS_INFO_UPDATE);
++	if (!skb)
++		return -EINVAL;
++
++	bsscmd =
++	    (struct sip_cmd_bss_info_update *) (skb->data +
++						sizeof(struct sip_hdr));
++	if (assoc == 2) {	//hack for softAP mode
++		bsscmd->beacon_int = evif->beacon_interval;
++	} else if (assoc == 1) {
++		set_bit(ESP_WL_FLAG_CONNECT, &epub->wl.flags);
++	} else {
++		clear_bit(ESP_WL_FLAG_CONNECT, &epub->wl.flags);
++	}
++	bsscmd->bssid_no = evif->index;
++	bsscmd->isassoc = assoc;
++	bsscmd->beacon_int = evif->beacon_interval;
++	memcpy(bsscmd->bssid, bssid, ETH_ALEN);
++	return sip_cmd_enqueue(epub->sip, skb, ENQUEUE_PRIOR_TAIL);
++}
++
++int sip_send_wmm_params(struct esp_pub *epub, u8 aci,
++			const struct ieee80211_tx_queue_params *params)
++{
++	struct sk_buff *skb = NULL;
++	struct sip_cmd_set_wmm_params *bsscmd;
++	skb =
++	    sip_alloc_ctrl_skbuf(epub->sip,
++				 sizeof(struct sip_cmd_set_wmm_params) +
++				 sizeof(struct sip_hdr),
++				 SIP_CMD_SET_WMM_PARAM);
++	if (!skb)
++		return -EINVAL;
++
++	bsscmd =
++	    (struct sip_cmd_set_wmm_params *) (skb->data +
++					       sizeof(struct sip_hdr));
++	bsscmd->aci = aci;
++	bsscmd->aifs = params->aifs;
++	bsscmd->txop_us = params->txop * 32;
++
++	bsscmd->ecw_min = 32 - __builtin_clz(params->cw_min);
++	bsscmd->ecw_max = 32 - __builtin_clz(params->cw_max);
++
++	return sip_cmd_enqueue(epub->sip, skb, ENQUEUE_PRIOR_TAIL);
++}
++
++int sip_send_ampdu_action(struct esp_pub *epub, u8 action_num,
++			  const u8 * addr, u16 tid, u16 ssn, u8 buf_size)
++{
++	int index = 0;
++	struct sk_buff *skb = NULL;
++	struct sip_cmd_ampdu_action *action;
++	if (action_num == SIP_AMPDU_RX_START) {
++		index = esp_get_empty_rxampdu(epub, addr, tid);
++	} else if (action_num == SIP_AMPDU_RX_STOP) {
++		index = esp_get_exist_rxampdu(epub, addr, tid);
++	}
++	if (index < 0)
++		return -EACCES;
++	skb =
++	    sip_alloc_ctrl_skbuf(epub->sip,
++				 sizeof(struct sip_cmd_ampdu_action) +
++				 sizeof(struct sip_hdr),
++				 SIP_CMD_AMPDU_ACTION);
++	if (!skb)
++		return -EINVAL;
++
++	action =
++	    (struct sip_cmd_ampdu_action *) (skb->data +
++					     sizeof(struct sip_hdr));
++	action->action = action_num;
++	//for TX, it means interface index
++	action->index = ssn;
++
++	switch (action_num) {
++	case SIP_AMPDU_RX_START:
++		action->ssn = ssn;
++		// fall through
++	case SIP_AMPDU_RX_STOP:
++		action->index = index;
++		// fall through
++	case SIP_AMPDU_TX_OPERATIONAL:
++	case SIP_AMPDU_TX_STOP:
++		action->win_size = buf_size;
++		action->tid = tid;
++		memcpy(action->addr, addr, ETH_ALEN);
++		break;
++	}
++
++	return sip_cmd_enqueue(epub->sip, skb, ENQUEUE_PRIOR_TAIL);
++}
++
++#ifdef HW_SCAN
++/*send cmd to target, if aborted is true, inform target stop scan, report scan complete imediately
++  return 1: complete over, 0: success, still have next scan, -1: hardware failure
++  */
++int sip_send_scan(struct esp_pub *epub)
++{
++	struct cfg80211_scan_request *scan_req = epub->wl.scan_req;
++	struct sk_buff *skb = NULL;
++	struct sip_cmd_scan *scancmd;
++	u8 *ptr = NULL;
++	int i;
++	u8 append_len, ssid_len;
++
++	ESSERT(scan_req != NULL);
++	ssid_len = scan_req->n_ssids == 0 ? 0 :
++	    (scan_req->n_ssids ==
++	     1 ? scan_req->ssids->ssid_len : scan_req->ssids->ssid_len +
++	     (scan_req->ssids + 1)->ssid_len);
++	append_len = ssid_len + scan_req->n_channels + scan_req->ie_len;
++
++	skb =
++	    sip_alloc_ctrl_skbuf(epub->sip,
++				 sizeof(struct sip_cmd_scan) +
++				 sizeof(struct sip_hdr) + append_len,
++				 SIP_CMD_SCAN);
++
++	if (!skb)
++		return -EINVAL;
++
++	ptr = skb->data;
++	scancmd = (struct sip_cmd_scan *) (ptr + sizeof(struct sip_hdr));
++	ptr += sizeof(struct sip_hdr);
++
++	scancmd->aborted = false;
++
++	if (scancmd->aborted == false) {
++		ptr += sizeof(struct sip_cmd_scan);
++		if (scan_req->n_ssids <= 0
++		    || (scan_req->n_ssids == 1 && ssid_len == 0)) {
++			scancmd->ssid_len = 0;
++		} else {
++			scancmd->ssid_len = ssid_len;
++			if (scan_req->ssids->ssid_len == ssid_len)
++				memcpy(ptr, scan_req->ssids->ssid,
++				       scancmd->ssid_len);
++			else
++				memcpy(ptr, (scan_req->ssids + 1)->ssid,
++				       scancmd->ssid_len);
++		}
++
++		ptr += scancmd->ssid_len;
++		scancmd->n_channels = scan_req->n_channels;
++		for (i = 0; i < scan_req->n_channels; i++)
++			ptr[i] = scan_req->channels[i]->hw_value;
++
++		ptr += scancmd->n_channels;
++		if (scan_req->ie_len && scan_req->ie != NULL) {
++			scancmd->ie_len = scan_req->ie_len;
++			memcpy(ptr, scan_req->ie, scan_req->ie_len);
++		} else {
++			scancmd->ie_len = 0;
++		}
++		//add a flag that support two ssids,
++		if (scan_req->n_ssids > 1)
++			scancmd->ssid_len |= 0x80;
++
++	}
++
++	return sip_cmd_enqueue(epub->sip, skb, ENQUEUE_PRIOR_TAIL);
++}
++#endif
++
++int sip_send_suspend_config(struct esp_pub *epub, u8 suspend)
++{
++	struct sip_cmd_suspend *cmd = NULL;
++	struct sk_buff *skb = NULL;
++
++	skb =
++	    sip_alloc_ctrl_skbuf(epub->sip,
++				 sizeof(struct sip_cmd_suspend) +
++				 sizeof(struct sip_hdr), SIP_CMD_SUSPEND);
++
++	if (!skb)
++		return -EINVAL;
++
++	cmd =
++	    (struct sip_cmd_suspend *) (skb->data +
++					sizeof(struct sip_hdr));
++	cmd->suspend = suspend;
++	return sip_cmd_enqueue(epub->sip, skb, ENQUEUE_PRIOR_TAIL);
++}
++
++int sip_send_ps_config(struct esp_pub *epub, struct esp_ps *ps)
++{
++	struct sip_cmd_ps *pscmd = NULL;
++	struct sk_buff *skb = NULL;
++	struct sip_hdr *shdr = NULL;
++
++	skb =
++	    sip_alloc_ctrl_skbuf(epub->sip,
++				 sizeof(struct sip_cmd_ps) +
++				 sizeof(struct sip_hdr), SIP_CMD_PS);
++
++	if (!skb)
++		return -EINVAL;
++
++
++	shdr = (struct sip_hdr *) skb->data;
++	pscmd = (struct sip_cmd_ps *) (skb->data + sizeof(struct sip_hdr));
++
++	pscmd->dtim_period = ps->dtim_period;
++	pscmd->max_sleep_period = ps->max_sleep_period;
++
++	return sip_cmd_enqueue(epub->sip, skb, ENQUEUE_PRIOR_TAIL);
++}
++
++void sip_scandone_process(struct esp_sip *sip,
++			  struct sip_evt_scan_report *scan_report)
++{
++	struct esp_pub *epub = sip->epub;
++
++	esp_dbg(ESP_DBG_TRACE, "eagle hw scan report\n");
++
++	if (epub->wl.scan_req) {
++		hw_scan_done(epub, scan_report->aborted);
++		epub->wl.scan_req = NULL;
++	}
++}
++
++int sip_send_setkey(struct esp_pub *epub, u8 bssid_no, u8 * peer_addr,
++		    struct ieee80211_key_conf *key, u8 isvalid)
++{
++	struct sip_cmd_setkey *setkeycmd;
++	struct sk_buff *skb = NULL;
++
++	skb =
++	    sip_alloc_ctrl_skbuf(epub->sip,
++				 sizeof(struct sip_cmd_setkey) +
++				 sizeof(struct sip_hdr), SIP_CMD_SETKEY);
++
++	if (!skb)
++		return -EINVAL;
++
++	setkeycmd =
++	    (struct sip_cmd_setkey *) (skb->data + sizeof(struct sip_hdr));
++
++	if (peer_addr) {
++		memcpy(setkeycmd->addr, peer_addr, ETH_ALEN);
++	} else {
++		memset(setkeycmd->addr, 0, ETH_ALEN);
++	}
++
++	setkeycmd->bssid_no = bssid_no;
++	setkeycmd->hw_key_idx = key->hw_key_idx;
++
++	if (isvalid) {
++		setkeycmd->alg = esp_cipher2alg(key->cipher);
++		setkeycmd->keyidx = key->keyidx;
++		setkeycmd->keylen = key->keylen;
++		if (key->cipher == WLAN_CIPHER_SUITE_TKIP) {
++			memcpy(setkeycmd->key, key->key, 16);
++			memcpy(setkeycmd->key + 16, key->key + 24, 8);
++			memcpy(setkeycmd->key + 24, key->key + 16, 8);
++		} else {
++			memcpy(setkeycmd->key, key->key, key->keylen);
++		}
++
++		setkeycmd->flags = 1;
++	} else {
++		setkeycmd->flags = 0;
++	}
++	return sip_cmd_enqueue(epub->sip, skb, ENQUEUE_PRIOR_TAIL);
++}
++
++#ifdef FPGA_LOOPBACK
++#define LOOPBACK_PKT_LEN 200
++int sip_send_loopback_cmd_mblk(struct esp_sip *sip)
++{
++	int cnt, ret;
++
++	for (cnt = 0; cnt < 4; cnt++) {
++		if (0 !=
++		    (ret =
++		     sip_send_loopback_mblk(sip, LOOPBACK_PKT_LEN,
++					    LOOPBACK_PKT_LEN, 0)))
++			return ret;
++	}
++	return 0;
++}
++#endif				/* FPGA_LOOPBACK */
++
++int sip_send_loopback_mblk(struct esp_sip *sip, int txpacket_len,
++			   int rxpacket_len, int packet_id)
++{
++	struct sk_buff *skb = NULL;
++	struct sip_cmd_loopback *cmd;
++	u8 *ptr = NULL;
++	int i, ret;
++
++	//send 100 loopback pkt
++	if (txpacket_len)
++		skb =
++		    sip_alloc_ctrl_skbuf(sip,
++					 sizeof(struct sip_cmd_loopback) +
++					 sizeof(struct sip_hdr) +
++					 txpacket_len, SIP_CMD_LOOPBACK);
++	else
++		skb =
++		    sip_alloc_ctrl_skbuf(sip,
++					 sizeof(struct sip_cmd_loopback) +
++					 sizeof(struct sip_hdr),
++					 SIP_CMD_LOOPBACK);
++
++	if (!skb)
++		return -ENOMEM;
++
++	ptr = skb->data;
++	cmd = (struct sip_cmd_loopback *) (ptr + sizeof(struct sip_hdr));
++	ptr += sizeof(struct sip_hdr);
++	cmd->txlen = txpacket_len;
++	cmd->rxlen = rxpacket_len;
++	cmd->pack_id = packet_id;
++
++	if (txpacket_len) {
++		ptr += sizeof(struct sip_cmd_loopback);
++		/* fill up pkt payload */
++		for (i = 0; i < txpacket_len; i++) {
++			ptr[i] = i;
++		}
++	}
++
++	ret = sip_cmd_enqueue(sip, skb, ENQUEUE_PRIOR_TAIL);
++	if (ret < 0)
++		return ret;
++
++	return 0;
++}
++
++//remain_on_channel
++int sip_send_roc(struct esp_pub *epub, u16 center_freq, u16 duration)
++{
++	struct sk_buff *skb = NULL;
++	struct sip_cmd_config *configcmd;
++
++	skb =
++	    sip_alloc_ctrl_skbuf(epub->sip,
++				 sizeof(struct sip_cmd_config) +
++				 sizeof(struct sip_hdr), SIP_CMD_CONFIG);
++	if (!skb)
++		return -EINVAL;
++
++	configcmd =
++	    (struct sip_cmd_config *) (skb->data + sizeof(struct sip_hdr));
++	configcmd->center_freq = center_freq;
++	configcmd->duration = duration;
++	return sip_cmd_enqueue(epub->sip, skb, ENQUEUE_PRIOR_TAIL);
++}
++
++int sip_send_set_sta(struct esp_pub *epub, u8 ifidx, u8 set,
++		     struct ieee80211_sta *sta, struct ieee80211_vif *vif,
++		     u8 index)
++{
++	struct sk_buff *skb = NULL;
++	struct sip_cmd_setsta *setstacmd;
++	skb =
++	    sip_alloc_ctrl_skbuf(epub->sip,
++				 sizeof(struct sip_cmd_setsta) +
++				 sizeof(struct sip_hdr), SIP_CMD_SETSTA);
++	if (!skb)
++		return -EINVAL;
++
++	setstacmd =
++	    (struct sip_cmd_setsta *) (skb->data + sizeof(struct sip_hdr));
++	setstacmd->ifidx = ifidx;
++	setstacmd->index = index;
++	setstacmd->set = set;
++	if (sta->aid == 0)
++		setstacmd->aid = vif->cfg.aid;
++	else
++		setstacmd->aid = sta->aid;
++	memcpy(setstacmd->mac, sta->addr, ETH_ALEN);
++	if (set) {
++		if (sta->deflink.ht_cap.ht_supported) {
++			if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20)
++				setstacmd->phymode =
++				    ESP_IEEE80211_T_HT20_S;
++			else
++				setstacmd->phymode =
++				    ESP_IEEE80211_T_HT20_L;
++			setstacmd->ampdu_factor = sta->deflink.ht_cap.ampdu_factor;
++			setstacmd->ampdu_density =
++			    sta->deflink.ht_cap.ampdu_density;
++		} else {
++			if (sta->deflink.supp_rates[NL80211_BAND_2GHZ] & (~(u32)
++							       CONF_HW_BIT_RATE_11B_MASK))
++			{
++				setstacmd->phymode = ESP_IEEE80211_T_OFDM;
++			} else {
++				setstacmd->phymode = ESP_IEEE80211_T_CCK;
++			}
++		}
++	}
++	return sip_cmd_enqueue(epub->sip, skb, ENQUEUE_PRIOR_TAIL);
++}
++
++int sip_send_recalc_credit(struct esp_pub *epub)
++{
++	struct sk_buff *skb = NULL;
++
++	skb =
++	    sip_alloc_ctrl_skbuf(epub->sip, 0 + sizeof(struct sip_hdr),
++				 SIP_CMD_RECALC_CREDIT);
++	if (!skb)
++		return -ENOMEM;
++
++	return sip_cmd_enqueue(epub->sip, skb, ENQUEUE_PRIOR_HEAD);
++}
++
++int sip_cmd(struct esp_pub *epub, enum sip_cmd_id cmd_id, u8 * cmd_buf,
++	    u8 cmd_len)
++{
++	struct sk_buff *skb = NULL;
++
++	skb =
++	    sip_alloc_ctrl_skbuf(epub->sip,
++				 cmd_len + sizeof(struct sip_hdr), cmd_id);
++	if (!skb)
++		return -ENOMEM;
++
++	memcpy(skb->data + sizeof(struct sip_hdr), cmd_buf, cmd_len);
++
++	return sip_cmd_enqueue(epub->sip, skb, ENQUEUE_PRIOR_TAIL);
++}
+diff --git a/drivers/net/wireless/esp8089/esp_ctrl.h b/drivers/net/wireless/esp8089/esp_ctrl.h
+new file mode 100644
+index 000000000000..29c18caa9ede
+--- /dev/null
++++ b/drivers/net/wireless/esp8089/esp_ctrl.h
+@@ -0,0 +1,58 @@
++/*
++ *  Copyright (c) 2009- 2014 Espressif System.
++ *
++ *  SIP ctrl packet parse and pack
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++#ifndef _ESP_CTRL_H_
++#define _ESP_CTRL_H_
++
++int sip_send_loopback_mblk(struct esp_sip *sip, int txpacket_len,
++			   int rxpacket_len, int packet_id);
++
++int sip_send_config(struct esp_pub *epub, struct ieee80211_conf *conf);
++
++int sip_send_setkey(struct esp_pub *epub, u8 bssid_no, u8 * peer_addr,
++		    struct ieee80211_key_conf *key, u8 isvalid);
++
++int sip_send_scan(struct esp_pub *epub);
++
++void sip_scandone_process(struct esp_sip *sip,
++			  struct sip_evt_scan_report *scan_report);
++
++int sip_send_bss_info_update(struct esp_pub *epub, struct esp_vif *evif,
++			     u8 * bssid, int assoc);
++
++int sip_send_wmm_params(struct esp_pub *epub, u8 aci,
++			const struct ieee80211_tx_queue_params *params);
++
++int sip_send_ampdu_action(struct esp_pub *epub, u8 action_num,
++			  const u8 * addr, u16 tid, u16 ssn, u8 buf_size);
++
++int sip_send_roc(struct esp_pub *epub, u16 center_freq, u16 duration);
++
++int sip_send_set_sta(struct esp_pub *epub, u8 ifidx, u8 set,
++		     struct ieee80211_sta *sta, struct ieee80211_vif *vif,
++		     u8 index);
++
++int sip_send_suspend_config(struct esp_pub *epub, u8 suspend);
++
++int sip_send_ps_config(struct esp_pub *epub, struct esp_ps *ps);
++
++int sip_parse_events(struct esp_sip *sip, u8 * buf);
++
++int sip_send_recalc_credit(struct esp_pub *epub);
++
++int sip_cmd(struct esp_pub *epub, enum sip_cmd_id cmd_id, u8 * cmd_buf,
++	    u8 cmd_len);
++
++#endif				/* _ESP_CTRL_H_ */
+diff --git a/drivers/net/wireless/esp8089/esp_debug.c b/drivers/net/wireless/esp8089/esp_debug.c
+new file mode 100644
+index 000000000000..5ce8fd2ebd6b
+--- /dev/null
++++ b/drivers/net/wireless/esp8089/esp_debug.c
+@@ -0,0 +1,297 @@
++/*
++ * Copyright (c) 2011-2014 Espressif System.
++ *
++ * esp debug interface
++ *  - debugfs
++ *  - debug level control
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++
++#include <linux/types.h>
++#include <linux/kernel.h>
++
++#include <net/mac80211.h>
++#include "sip2_common.h"
++
++#include "esp_debug.h"
++
++#if defined(CONFIG_DEBUG_FS) && defined(CONFIG_ESP8089_DEBUG_FS)
++
++static struct dentry *esp_debugfs_root = NULL;
++
++static int esp_debugfs_open(struct inode *inode, struct file *filp)
++{
++	filp->private_data = inode->i_private;
++	return 0;
++}
++
++static ssize_t esp_debugfs_read(struct file *filp, char __user * buffer,
++				size_t count, loff_t * ppos)
++{
++	if (*ppos >= 32)
++		return 0;
++	if (*ppos + count > 32)
++		count = 32 - *ppos;
++
++	if (copy_to_user(buffer, filp->private_data + *ppos, count))
++		return -EFAULT;
++
++	*ppos += count;
++
++	return count;
++}
++
++static ssize_t esp_debugfs_write(struct file *filp,
++				 const char __user * buffer, size_t count,
++				 loff_t * ppos)
++{
++	if (*ppos >= 32)
++		return 0;
++	if (*ppos + count > 32)
++		count = 32 - *ppos;
++
++	if (copy_from_user(filp->private_data + *ppos, buffer, count))
++		return -EFAULT;
++
++	*ppos += count;
++
++	return count;
++}
++
++struct file_operations esp_debugfs_fops = {
++	.owner = THIS_MODULE,
++	.open = esp_debugfs_open,
++	.read = esp_debugfs_read,
++	.write = esp_debugfs_write,
++};
++
++
++void esp_dump_var(const char *name, struct dentry *parent,
++			    void *value, esp_type type)
++{
++	umode_t mode = 0644;
++
++	if (!esp_debugfs_root)
++		return;
++
++	if (!parent)
++		parent = esp_debugfs_root;
++
++	switch (type) {
++	case ESP_U8:
++		debugfs_create_u8(name, mode, parent, (u8 *) value);
++		break;
++	case ESP_U16:
++		debugfs_create_u16(name, mode, parent, (u16 *) value);
++		break;
++	case ESP_U32:
++		debugfs_create_u32(name, mode, parent, (u32 *) value);
++		break;
++	case ESP_U64:
++		debugfs_create_u64(name, mode, parent, (u64 *) value);
++		break;
++	case ESP_BOOL:
++		debugfs_create_bool(name, mode, parent,
++					 (bool *) value);
++		break;
++	default:		//32
++		debugfs_create_u32(name, mode, parent, (u32 *) value);
++	}
++
++	return;
++
++}
++
++void esp_dump_array(const char *name, struct dentry *parent,
++			      struct debugfs_blob_wrapper *blob)
++{
++	umode_t mode = 0644;
++
++	if (!esp_debugfs_root)
++		return;
++
++	if (!parent)
++		parent = esp_debugfs_root;
++
++	debugfs_create_blob(name, mode, parent, blob);
++
++}
++
++void esp_dump(const char *name, struct dentry *parent,
++			void *data, int size)
++{
++	umode_t mode = 0644;
++
++	if (!esp_debugfs_root)
++		return;
++
++	if (!parent)
++		parent = esp_debugfs_root;
++
++	debugfs_create_file(name, mode, parent, data,
++				 &esp_debugfs_fops);
++
++}
++
++struct dentry *esp_debugfs_add_sub_dir(const char *name)
++{
++	struct dentry *sub_dir = NULL;
++
++	sub_dir = debugfs_create_dir(name, esp_debugfs_root);
++
++	if (!sub_dir)
++		goto Fail;
++
++	return sub_dir;
++
++      Fail:
++	debugfs_remove_recursive(esp_debugfs_root);
++	esp_debugfs_root = NULL;
++	esp_dbg(ESP_DBG_ERROR,
++		"%s failed, debugfs root removed; dir name: %s\n",
++		__FUNCTION__, name);
++	return NULL;
++
++}
++
++int esp_debugfs_init(void)
++{
++	esp_dbg(ESP_DBG, "esp debugfs init\n");
++	esp_debugfs_root = debugfs_create_dir("esp_debug", NULL);
++
++	if (!esp_debugfs_root || IS_ERR_OR_NULL(esp_debugfs_root)) {
++		return -ENOENT;
++	}
++
++	return 0;
++}
++
++void esp_debugfs_exit(void)
++{
++	esp_dbg(ESP_DBG, "esp debugfs exit");
++
++	debugfs_remove_recursive(esp_debugfs_root);
++
++	return;
++}
++
++#else
++
++inline struct dentry *esp_dump_var(const char *name, struct dentry *parent,
++				   void *value, esp_type type)
++{
++	return NULL;
++}
++
++inline struct dentry *esp_dump_array(const char *name,
++				     struct dentry *parent,
++				     struct debugfs_blob_wrapper *blob)
++{
++	return NULL;
++}
++
++inline struct dentry *esp_dump(const char *name, struct dentry *parent,
++			       void *data, int size)
++{
++	return NULL;
++}
++
++struct dentry *esp_debugfs_add_sub_dir(const char *name)
++{
++	return NULL;
++}
++
++inline int esp_debugfs_init(void)
++{
++	return -EPERM;
++}
++
++inline void esp_debugfs_exit(void)
++{
++
++}
++
++#endif
++
++
++void show_buf(u8 * buf, u32 len)
++{
++//      print_hex_dump(KERN_DEBUG, "",  DUMP_PREFIX_OFFSET, 16, 1, buf, len, true);
++#if 1
++	int i = 0, j;
++
++	printk(KERN_INFO "\n++++++++++++++++show rbuf+++++++++++++++\n");
++	for (i = 0; i < (len / 16); i++) {
++		j = i * 16;
++		printk(KERN_INFO
++		       "0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x \n",
++		       buf[j], buf[j + 1], buf[j + 2], buf[j + 3],
++		       buf[j + 4], buf[j + 5], buf[j + 6], buf[j + 7],
++		       buf[j + 8], buf[j + 9], buf[j + 10], buf[j + 11],
++		       buf[j + 12], buf[j + 13], buf[j + 14], buf[j + 15]);
++	}
++	printk(KERN_INFO "\n++++++++++++++++++++++++++++++++++++++++\n");
++#endif				//0000
++}
++
++#ifdef HOST_RC
++static u8 get_cnt(u32 cnt_store, int idx)
++{
++	int shift = idx << 2;
++
++	return (u8) ((cnt_store >> shift) & 0xf);
++}
++
++void esp_show_rcstatus(struct sip_rc_status *rcstatus)
++{
++	int i;
++	char msg[82];
++	char rcstr[16];
++	u32 cnt_store = rcstatus->rc_cnt_store;
++
++	memset(msg, 0, sizeof(msg));
++	memset(rcstr, 0, sizeof(rcstr));
++
++	printk(KERN_INFO "rcstatus map 0x%08x cntStore 0x%08x\n",
++	       rcstatus->rc_map, rcstatus->rc_cnt_store);
++
++	for (i = 0; i < IEEE80211_TX_MAX_RATES; i++) {
++		if (rcstatus->rc_map & BIT(i)) {
++			sprintf(rcstr, "rcIdx %d, cnt %d ", i,
++				get_cnt(cnt_store, i));
++			strcat(msg, rcstr);
++		}
++	}
++	printk(KERN_INFO "%s \n", msg);
++}
++
++void esp_show_tx_rates(struct ieee80211_tx_rate *rates)
++{
++	int i;
++	char msg[128];
++	char rcstr[32];
++
++	memset(msg, 0, sizeof(msg));
++	memset(rcstr, 0, sizeof(rcstr));
++
++	for (i = 0; i < IEEE80211_TX_MAX_RATES; i++) {
++		if (rates->idx != -1) {
++			sprintf(rcstr, "Idx %d, cnt %d, flag %02x ",
++				rates->idx, rates->count, rates->flags);
++			strcat(msg, rcstr);
++		}
++		rates++;
++	}
++	strcat(msg, "\n");
++	printk(KERN_INFO "%s \n", msg);
++}
++#endif				/* HOST_RC */
+diff --git a/drivers/net/wireless/esp8089/esp_debug.h b/drivers/net/wireless/esp8089/esp_debug.h
+new file mode 100644
+index 000000000000..bab695d34bfb
+--- /dev/null
++++ b/drivers/net/wireless/esp8089/esp_debug.h
+@@ -0,0 +1,101 @@
++/*
++ * Copyright (c) 2011-2014 Espressif System.
++ *
++ * esp debug
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++
++#ifndef _DEBUG_H_
++
++#ifdef ASSERT_PANIC
++#define ESSERT(v) BUG_ON(!(v))
++#else
++#define ESSERT(v) if(!(v)) printk("ESSERT:%s %d\n", __FILE__, __LINE__)
++#endif
++
++
++#include <linux/slab.h>
++#include <linux/debugfs.h>
++#include <asm/uaccess.h>
++
++typedef enum esp_type {
++	ESP_BOOL,
++	ESP_U8,
++	ESP_U16,
++	ESP_U32,
++	ESP_U64
++} esp_type;
++
++void esp_dump_var(const char *name, struct dentry *parent,
++			    void *value, esp_type type);
++
++void esp_dump_array(const char *name, struct dentry *parent,
++			      struct debugfs_blob_wrapper *blob);
++
++void esp_dump(const char *name, struct dentry *parent,
++			void *data, int size);
++
++struct dentry *esp_debugfs_add_sub_dir(const char *name);
++
++int esp_debugfs_init(void);
++
++void esp_debugfs_exit(void);
++
++enum {
++	ESP_DBG_ERROR = BIT(0),
++	ESP_DBG_TRACE = BIT(1),
++	ESP_DBG_LOG = BIT(2),
++	ESP_DBG = BIT(3),
++	ESP_SHOW = BIT(4),
++	ESP_DBG_TXAMPDU = BIT(5),
++	ESP_DBG_OP = BIT(6),
++	ESP_DBG_PS = BIT(7),
++	ESP_ATE = BIT(8),
++	ESP_DBG_ALL = 0xffffffff
++};
++
++extern unsigned int esp_msg_level;
++
++#ifdef ESP_ANDROID_LOGGER
++extern bool log_off;
++#endif				/* ESP_ANDROID_LOGGER */
++
++#ifdef ESP_ANDROID_LOGGER
++#include "esp_file.h"
++#define esp_dbg(mask, fmt, args...) do {                  \
++        if (esp_msg_level & mask)   			  \
++	{						  \
++		if (log_off)      		          \
++			printk(fmt, ##args);              \
++		else 					              \
++            		logger_write(4, "esp_wifi", fmt, ##args);     \
++	}							      \
++    } while (0)
++#else
++#define esp_dbg(mask, fmt, args...) do {                  \
++        if (esp_msg_level & mask)                         \
++            printk("esp8089: " fmt, ##args);                          \
++    } while (0)
++#endif				/* ESP_ANDROID_LOGGER */
++
++void show_buf(u8 * buf, u32 len);
++
++#ifdef HOST_RC
++struct sip_rc_status;
++struct ieee80211_tx_rate;
++
++void esp_show_rcstatus(struct sip_rc_status *rcstatus);
++
++void esp_show_tx_rates(struct ieee80211_tx_rate *rates);
++#endif				/* HOST_RC */
++
++#endif				/* _DEBUG_H_ */
+diff --git a/drivers/net/wireless/esp8089/esp_ext.c b/drivers/net/wireless/esp8089/esp_ext.c
+new file mode 100644
+index 000000000000..541f27a6853f
+--- /dev/null
++++ b/drivers/net/wireless/esp8089/esp_ext.c
+@@ -0,0 +1,542 @@
++/*
++ * Copyright (c) 2010 -2013 Espressif System.
++ *
++ *   extended gpio
++ *    - interface for other driver or kernel
++ *    - gpio control
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++
++#ifdef USE_EXT_GPIO
++
++#include <net/cfg80211.h>
++#include <linux/skbuff.h>
++#include <linux/bitops.h>
++#include <linux/version.h>
++#include <linux/mmc/card.h>
++#include <linux/mmc/mmc.h>
++#include <linux/mmc/host.h>
++#include <linux/mmc/sdio_func.h>
++#include <linux/mmc/sdio_ids.h>
++#include <linux/mmc/sdio.h>
++#include <linux/mmc/sd.h>
++#include <linux/completion.h>
++
++#include "esp_ext.h"
++#include "esp_debug.h"
++#include "esp_sip.h"
++#include "esp_sif.h"
++
++#ifdef EXT_GPIO_OPS
++extern void register_ext_gpio_ops(struct esp_ext_gpio_ops *ops);
++extern void unregister_ext_gpio_ops(void);
++
++static struct esp_ext_gpio_ops ext_gpio_ops = {
++	.gpio_request = ext_gpio_request,	/* gpio_request gpio_no from 0x0 to 0xf */
++	.gpio_release = ext_gpio_release,	/* gpio_release */
++	.gpio_set_mode = ext_gpio_set_mode,	/* gpio_set_mode, data is irq_func of irq_mode , default level of output_mode */
++	.gpio_get_mode = ext_gpio_get_mode,	/* gpio_get_mode, current mode */
++	.gpio_set_state = ext_gpio_set_output_state,	/* only output state, high level or low level */
++	.gpio_get_state = ext_gpio_get_state,	/* current state */
++	.irq_ack = ext_irq_ack,	/* ack interrupt */
++};
++
++
++#endif
++
++static struct esp_pub *ext_epub = NULL;
++
++static u16 intr_mask_reg = 0x0000;
++struct workqueue_struct *ext_irq_wkq = NULL;
++struct work_struct ext_irq_work;
++static struct mutex ext_mutex_lock;
++
++static struct ext_gpio_info gpio_list[EXT_GPIO_MAX_NUM] = {
++	{0, EXT_GPIO_MODE_DISABLE, EXT_GPIO_STATE_IDLE, NULL},
++	{1, EXT_GPIO_MODE_DISABLE, EXT_GPIO_STATE_IDLE, NULL},
++	{2, EXT_GPIO_MODE_DISABLE, EXT_GPIO_STATE_IDLE, NULL},
++	{3, EXT_GPIO_MODE_DISABLE, EXT_GPIO_STATE_IDLE, NULL},
++	{4, EXT_GPIO_MODE_DISABLE, EXT_GPIO_STATE_IDLE, NULL},
++	{5, EXT_GPIO_MODE_DISABLE, EXT_GPIO_STATE_IDLE, NULL},
++	{6, EXT_GPIO_MODE_DISABLE, EXT_GPIO_STATE_IDLE, NULL},
++	{7, EXT_GPIO_MODE_DISABLE, EXT_GPIO_STATE_IDLE, NULL},
++	{8, EXT_GPIO_MODE_DISABLE, EXT_GPIO_STATE_IDLE, NULL},
++	{9, EXT_GPIO_MODE_DISABLE, EXT_GPIO_STATE_IDLE, NULL},
++	{10, EXT_GPIO_MODE_DISABLE, EXT_GPIO_STATE_IDLE, NULL},
++	{11, EXT_GPIO_MODE_DISABLE, EXT_GPIO_STATE_IDLE, NULL},
++	{12, EXT_GPIO_MODE_DISABLE, EXT_GPIO_STATE_IDLE, NULL},
++	{13, EXT_GPIO_MODE_DISABLE, EXT_GPIO_STATE_IDLE, NULL},
++	{14, EXT_GPIO_MODE_DISABLE, EXT_GPIO_STATE_IDLE, NULL},
++	{15, EXT_GPIO_MODE_DISABLE, EXT_GPIO_STATE_IDLE, NULL},
++};
++
++static struct pending_intr_list_info esp_pending_intr_list = {
++	.start_pos = 0,
++	.end_pos = 0,
++	.curr_num = 0,
++};
++
++u16 ext_gpio_get_int_mask_reg(void)
++{
++	return intr_mask_reg;
++}
++
++int ext_gpio_request(int gpio_no)
++{
++	if (ext_epub == NULL || ext_epub->sip == NULL ||
++	    atomic_read(&ext_epub->sip->state) != SIP_RUN) {
++		esp_dbg(ESP_DBG_ERROR, "%s esp state is not ok\n",
++			__func__);
++		return -ENOTRECOVERABLE;
++	}
++
++	mutex_lock(&ext_mutex_lock);
++
++	if (gpio_no >= EXT_GPIO_MAX_NUM || gpio_no < 0) {
++		mutex_unlock(&ext_mutex_lock);
++		esp_dbg(ESP_DBG_ERROR, "%s unkown gpio num\n", __func__);
++		return -ERANGE;
++	}
++
++	if (gpio_list[gpio_no].gpio_mode != EXT_GPIO_MODE_DISABLE) {
++		mutex_unlock(&ext_mutex_lock);
++		esp_dbg(ESP_DBG_ERROR,
++			"%s gpio is already in used by other\n", __func__);
++		return -EPERM;
++	} else {
++		gpio_list[gpio_no].gpio_mode = EXT_GPIO_MODE_MAX;
++		mutex_unlock(&ext_mutex_lock);
++		return 0;
++	}
++}
++
++EXPORT_SYMBOL(ext_gpio_request);
++
++int ext_gpio_release(int gpio_no)
++{
++	int ret;
++
++	if (ext_epub == NULL || ext_epub->sip == NULL ||
++	    atomic_read(&ext_epub->sip->state) != SIP_RUN) {
++		esp_dbg(ESP_DBG_ERROR, "%s esp state is not ok\n",
++			__func__);
++		return -ENOTRECOVERABLE;
++	}
++
++	mutex_lock(&ext_mutex_lock);
++
++	if (gpio_no >= EXT_GPIO_MAX_NUM || gpio_no < 0) {
++		mutex_unlock(&ext_mutex_lock);
++		esp_dbg(ESP_DBG_ERROR, "%s unkown gpio num\n", __func__);
++		return -ERANGE;
++	}
++	sif_lock_bus(ext_epub);
++	ret =
++	    sif_config_gpio_mode(ext_epub, (u8) gpio_no,
++				 EXT_GPIO_MODE_DISABLE);
++	sif_unlock_bus(ext_epub);
++	if (ret) {
++		esp_dbg(ESP_DBG_ERROR, "%s gpio release error\n",
++			__func__);
++		mutex_unlock(&ext_mutex_lock);
++		return ret;
++	}
++
++	gpio_list[gpio_no].gpio_mode = EXT_GPIO_MODE_DISABLE;
++	gpio_list[gpio_no].gpio_state = EXT_GPIO_STATE_IDLE;
++	gpio_list[gpio_no].irq_handler = NULL;
++	intr_mask_reg &= ~(1 << gpio_no);
++
++	mutex_unlock(&ext_mutex_lock);
++
++	return 0;
++}
++
++EXPORT_SYMBOL(ext_gpio_release);
++
++int ext_gpio_set_mode(int gpio_no, int mode, void *data)
++{
++	u8 gpio_mode;
++	int ret;
++	struct ext_gpio_info backup_info;
++
++	if (ext_epub == NULL || ext_epub->sip == NULL ||
++	    atomic_read(&ext_epub->sip->state) != SIP_RUN) {
++		esp_dbg(ESP_DBG_LOG, "%s esp state is not ok\n", __func__);
++		return -ENOTRECOVERABLE;
++	}
++
++	mutex_lock(&ext_mutex_lock);
++
++	if (gpio_no >= EXT_GPIO_MAX_NUM || gpio_no < 0) {
++		mutex_unlock(&ext_mutex_lock);
++		esp_dbg(ESP_DBG_ERROR, "%s unkown gpio num\n", __func__);
++		return -ERANGE;
++	}
++
++	if (gpio_list[gpio_no].gpio_mode == EXT_GPIO_MODE_DISABLE) {
++		mutex_unlock(&ext_mutex_lock);
++		esp_dbg(ESP_DBG_ERROR,
++			"%s gpio is not in occupy, please request gpio\n",
++			__func__);
++		return -ENOTRECOVERABLE;
++	}
++
++	if (mode <= EXT_GPIO_MODE_OOB || mode >= EXT_GPIO_MODE_MAX) {
++		mutex_unlock(&ext_mutex_lock);
++		esp_dbg(ESP_DBG_ERROR, "%s gpio mode unknown\n", __func__);
++		return -EOPNOTSUPP;
++	}
++
++	memcpy(&backup_info, &gpio_list[gpio_no],
++	       sizeof(struct ext_gpio_info));
++
++	gpio_list[gpio_no].gpio_mode = mode;
++	gpio_mode = (u8) mode;
++
++	switch (mode) {
++	case EXT_GPIO_MODE_INTR_POSEDGE:
++	case EXT_GPIO_MODE_INTR_NEGEDGE:
++	case EXT_GPIO_MODE_INTR_LOLEVEL:
++	case EXT_GPIO_MODE_INTR_HILEVEL:
++		if (!data) {
++			memcpy(&gpio_list[gpio_no], &backup_info,
++			       sizeof(struct ext_gpio_info));
++			esp_dbg(ESP_DBG_ERROR, "%s irq_handler is NULL\n",
++				__func__);
++			mutex_unlock(&ext_mutex_lock);
++			return -EINVAL;
++		}
++		gpio_list[gpio_no].irq_handler = (ext_irq_handler_t) data;
++		intr_mask_reg |= (1 << gpio_no);
++		break;
++	case EXT_GPIO_MODE_OUTPUT:
++		if (!data) {
++			memcpy(&gpio_list[gpio_no], &backup_info,
++			       sizeof(struct ext_gpio_info));
++			esp_dbg(ESP_DBG_ERROR,
++				"%s output default value is NULL\n",
++				__func__);
++			mutex_unlock(&ext_mutex_lock);
++			return -EINVAL;
++		}
++		*(int *) data = (*(int *) data == 0 ? 0 : 1);
++		gpio_mode = (u8) (((*(int *) data) << 4) | gpio_mode);
++	default:
++		gpio_list[gpio_no].irq_handler = NULL;
++		intr_mask_reg &= ~(1 << gpio_no);
++		break;
++	}
++
++	sif_lock_bus(ext_epub);
++	ret = sif_config_gpio_mode(ext_epub, (u8) gpio_no, gpio_mode);
++	sif_unlock_bus(ext_epub);
++	if (ret) {
++		memcpy(&gpio_list[gpio_no], &backup_info,
++		       sizeof(struct ext_gpio_info));
++		esp_dbg(ESP_DBG_ERROR, "%s gpio set error\n", __func__);
++		mutex_unlock(&ext_mutex_lock);
++		return ret;
++	}
++
++	mutex_unlock(&ext_mutex_lock);
++	return 0;
++}
++
++EXPORT_SYMBOL(ext_gpio_set_mode);
++
++int ext_gpio_get_mode(int gpio_no)
++{
++	int gpio_mode;
++
++	if (ext_epub == NULL || ext_epub->sip == NULL ||
++	    atomic_read(&ext_epub->sip->state) != SIP_RUN) {
++		esp_dbg(ESP_DBG_LOG, "%s esp state is not ok\n", __func__);
++		return -ENOTRECOVERABLE;
++	}
++
++	mutex_lock(&ext_mutex_lock);
++
++	if (gpio_no >= EXT_GPIO_MAX_NUM || gpio_no < 0) {
++		esp_dbg(ESP_DBG_ERROR, "%s unkown gpio num\n", __func__);
++		mutex_unlock(&ext_mutex_lock);
++		return -ERANGE;
++	}
++
++	gpio_mode = gpio_list[gpio_no].gpio_mode;
++
++	mutex_unlock(&ext_mutex_lock);
++
++	return gpio_mode;
++}
++
++EXPORT_SYMBOL(ext_gpio_get_mode);
++
++
++int ext_gpio_set_output_state(int gpio_no, int state)
++{
++	int ret;
++
++	if (ext_epub == NULL || ext_epub->sip == NULL ||
++	    atomic_read(&ext_epub->sip->state) != SIP_RUN) {
++		esp_dbg(ESP_DBG_LOG, "%s esp state is not ok\n", __func__);
++		return -ENOTRECOVERABLE;
++	}
++
++	mutex_lock(&ext_mutex_lock);
++
++	if (gpio_no >= EXT_GPIO_MAX_NUM || gpio_no < 0) {
++		mutex_unlock(&ext_mutex_lock);
++		esp_dbg(ESP_DBG_ERROR, "%s unkown gpio num\n", __func__);
++		return -ERANGE;
++	}
++
++	if (gpio_list[gpio_no].gpio_mode != EXT_GPIO_MODE_OUTPUT) {
++		mutex_unlock(&ext_mutex_lock);
++		esp_dbg(ESP_DBG_ERROR,
++			"%s gpio is not in output state, please request gpio or set output state\n",
++			__func__);
++		return -EOPNOTSUPP;
++	}
++
++	if (state != EXT_GPIO_STATE_LOW && state != EXT_GPIO_STATE_HIGH) {
++		mutex_unlock(&ext_mutex_lock);
++		esp_dbg(ESP_DBG_ERROR, "%s gpio state unknown\n",
++			__func__);
++		return -ENOTRECOVERABLE;
++	}
++
++	sif_lock_bus(ext_epub);
++	ret =
++	    sif_set_gpio_output(ext_epub, 1 << gpio_no, state << gpio_no);
++	sif_unlock_bus(ext_epub);
++	if (ret) {
++		esp_dbg(ESP_DBG_ERROR, "%s gpio state set error\n",
++			__func__);
++		mutex_unlock(&ext_mutex_lock);
++		return ret;
++	}
++	gpio_list[gpio_no].gpio_state = state;
++
++	mutex_unlock(&ext_mutex_lock);
++
++	return 0;
++}
++
++EXPORT_SYMBOL(ext_gpio_set_output_state);
++
++int ext_gpio_get_state(int gpio_no)
++{
++	int ret;
++	u16 state;
++	u16 mask;
++
++	if (ext_epub == NULL || ext_epub->sip == NULL ||
++	    atomic_read(&ext_epub->sip->state) != SIP_RUN) {
++		esp_dbg(ESP_DBG_LOG, "%s esp state is not ok\n", __func__);
++		return -ENOTRECOVERABLE;
++	}
++
++	mutex_lock(&ext_mutex_lock);
++
++	if (gpio_no >= EXT_GPIO_MAX_NUM || gpio_no < 0) {
++		esp_dbg(ESP_DBG_ERROR, "%s unkown gpio num\n", __func__);
++		mutex_unlock(&ext_mutex_lock);
++		return -ERANGE;
++	}
++
++	if (gpio_list[gpio_no].gpio_mode == EXT_GPIO_MODE_OUTPUT) {
++		state = gpio_list[gpio_no].gpio_state;
++	} else if (gpio_list[gpio_no].gpio_mode == EXT_GPIO_MODE_INPUT) {
++		sif_lock_bus(ext_epub);
++		ret = sif_get_gpio_input(ext_epub, &mask, &state);
++		sif_unlock_bus(ext_epub);
++		if (ret) {
++			esp_dbg(ESP_DBG_ERROR,
++				"%s get gpio_input state error\n",
++				__func__);
++			mutex_unlock(&ext_mutex_lock);
++			return ret;
++		}
++	} else {
++		esp_dbg(ESP_DBG_ERROR,
++			"%s gpio_state is not input or output\n",
++			__func__);
++		mutex_unlock(&ext_mutex_lock);
++		return -EOPNOTSUPP;
++	}
++	mutex_unlock(&ext_mutex_lock);
++
++	return (state & (1 << gpio_no)) ? 1 : 0;
++}
++
++EXPORT_SYMBOL(ext_gpio_get_state);
++
++int ext_irq_ack(int gpio_no)
++{
++	int ret;
++
++	if (ext_epub == NULL || ext_epub->sip == NULL ||
++	    atomic_read(&ext_epub->sip->state) != SIP_RUN) {
++		esp_dbg(ESP_DBG_LOG, "%s esp state is not ok\n", __func__);
++		return -ENOTRECOVERABLE;
++	}
++
++	mutex_lock(&ext_mutex_lock);
++	if (gpio_no >= EXT_GPIO_MAX_NUM || gpio_no < 0) {
++		esp_dbg(ESP_DBG_ERROR, "%s unkown gpio num\n", __func__);
++		mutex_unlock(&ext_mutex_lock);
++		return -ERANGE;
++	}
++
++	if (gpio_list[gpio_no].gpio_mode != EXT_GPIO_MODE_INTR_POSEDGE
++	    && gpio_list[gpio_no].gpio_mode != EXT_GPIO_MODE_INTR_NEGEDGE
++	    && gpio_list[gpio_no].gpio_mode != EXT_GPIO_MODE_INTR_LOLEVEL
++	    && gpio_list[gpio_no].gpio_mode !=
++	    EXT_GPIO_MODE_INTR_HILEVEL) {
++		esp_dbg(ESP_DBG_ERROR, "%s gpio mode is not intr mode\n",
++			__func__);
++		mutex_unlock(&ext_mutex_lock);
++		return -ENOTRECOVERABLE;
++	}
++
++	sif_lock_bus(ext_epub);
++	ret = sif_set_gpio_output(ext_epub, 0x00, 1 << gpio_no);
++	sif_unlock_bus(ext_epub);
++	if (ret) {
++		esp_dbg(ESP_DBG_ERROR, "%s gpio intr ack error\n",
++			__func__);
++		mutex_unlock(&ext_mutex_lock);
++		return ret;
++	}
++
++	mutex_unlock(&ext_mutex_lock);
++	return 0;
++}
++
++EXPORT_SYMBOL(ext_irq_ack);
++
++void show_status(void)
++{
++	int i = 0;
++	for (i = 0; i < MAX_PENDING_INTR_LIST; i++)
++		esp_dbg(ESP_DBG_ERROR, "status[%d] = [0x%04x]\n", i,
++			esp_pending_intr_list.pending_intr_list[i]);
++
++	esp_dbg(ESP_DBG_ERROR, "start_pos[%d]\n",
++		esp_pending_intr_list.start_pos);
++	esp_dbg(ESP_DBG_ERROR, "end_pos[%d]\n",
++		esp_pending_intr_list.end_pos);
++	esp_dbg(ESP_DBG_ERROR, "curr_num[%d]\n",
++		esp_pending_intr_list.curr_num);
++
++}
++void esp_tx_work(struct work_struct *work)
++{
++	int i;
++	u16 tmp_intr_status_reg;
++
++	esp_dbg(ESP_DBG_TRACE, "%s enter\n", __func__);
++
++	spin_lock(&esp_pending_intr_list.spin_lock);
++
++	tmp_intr_status_reg =
++	    esp_pending_intr_list.pending_intr_list[esp_pending_intr_list.
++						    start_pos];
++
++	esp_pending_intr_list.pending_intr_list[esp_pending_intr_list.
++						start_pos] = 0x0000;
++	esp_pending_intr_list.start_pos =
++	    (esp_pending_intr_list.start_pos + 1) % MAX_PENDING_INTR_LIST;
++	esp_pending_intr_list.curr_num--;
++
++	spin_unlock(&esp_pending_intr_list.spin_lock);
++
++	for (i = 0; i < EXT_GPIO_MAX_NUM; i++) {
++		if (tmp_intr_status_reg & (1 << i)
++		    && (gpio_list[i].irq_handler))
++			gpio_list[i].irq_handler();
++	}
++
++	spin_lock(&esp_pending_intr_list.spin_lock);
++	if (esp_pending_intr_list.curr_num > 0)
++		queue_work(ext_irq_wkq, &ext_irq_work);
++	spin_unlock(&esp_pending_intr_list.spin_lock);
++}
++
++void ext_gpio_int_process(u16 value)
++{
++	if (value == 0x00)
++		return;
++
++	esp_dbg(ESP_DBG_TRACE, "%s enter\n", __func__);
++
++	/* intr cycle queue is full, wait */
++	while (esp_pending_intr_list.curr_num >= MAX_PENDING_INTR_LIST) {
++		udelay(1);
++	}
++
++	spin_lock(&esp_pending_intr_list.spin_lock);
++
++	esp_pending_intr_list.pending_intr_list[esp_pending_intr_list.
++						end_pos] = value;
++	esp_pending_intr_list.end_pos =
++	    (esp_pending_intr_list.end_pos + 1) % MAX_PENDING_INTR_LIST;
++	esp_pending_intr_list.curr_num++;
++
++	queue_work(ext_irq_wkq, &ext_irq_work);
++
++	spin_unlock(&esp_pending_intr_list.spin_lock);
++}
++
++int ext_gpio_init(struct esp_pub *epub)
++{
++	esp_dbg(ESP_DBG_ERROR, "%s enter\n", __func__);
++
++	ext_irq_wkq = create_singlethread_workqueue("esp_ext_irq_wkq");
++	if (ext_irq_wkq == NULL) {
++		esp_dbg(ESP_DBG_ERROR, "%s create workqueue error\n",
++			__func__);
++		return -EACCES;
++	}
++
++	INIT_WORK(&ext_irq_work, esp_tx_work);
++	mutex_init(&ext_mutex_lock);
++
++	ext_epub = epub;
++
++	if (ext_epub == NULL)
++		return -EINVAL;
++
++#ifdef EXT_GPIO_OPS
++	register_ext_gpio_ops(&ext_gpio_ops);
++#endif
++
++	return 0;
++}
++
++void ext_gpio_deinit(void)
++{
++	esp_dbg(ESP_DBG_ERROR, "%s enter\n", __func__);
++
++#ifdef EXT_GPIO_OPS
++	unregister_ext_gpio_ops();
++#endif
++	ext_epub = NULL;
++	cancel_work_sync(&ext_irq_work);
++
++	if (ext_irq_wkq)
++		destroy_workqueue(ext_irq_wkq);
++
++}
++
++#endif				/* USE_EXT_GPIO */
+diff --git a/drivers/net/wireless/esp8089/esp_ext.h b/drivers/net/wireless/esp8089/esp_ext.h
+new file mode 100644
+index 000000000000..0eeba4d22111
+--- /dev/null
++++ b/drivers/net/wireless/esp8089/esp_ext.h
+@@ -0,0 +1,100 @@
++#ifdef USE_EXT_GPIO
++
++#ifndef _ESP_EXT_H_
++#define _ESP_EXT_H_
++
++#include <linux/interrupt.h>
++#include <linux/module.h>
++#include "esp_sip.h"
++
++#define MAX_PENDING_INTR_LIST 16
++
++#ifdef EXT_GPIO_OPS
++typedef struct esp_ext_gpio_ops {
++	int (*gpio_request) (int gpio_no);	/* gpio_request gpio_no from 0x0 to 0xf */
++	int (*gpio_release) (int gpio_no);	/* gpio_release */
++	int (*gpio_set_mode) (int gpio_no, int mode, void *data);	/* gpio_set_mode, data is irq_func of irq_mode , default level of output_mode */
++	int (*gpio_get_mode) (int gpio_no);	/* gpio_get_mode, current mode */
++	int (*gpio_set_state) (int gpio_no, int state);	/* only output state, high level or low level */
++	int (*gpio_get_state) (int gpio_no);	/* current state */
++	int (*irq_ack) (int gpio_no);	/* ack interrupt */
++} esp_ext_gpio_ops_t;
++#endif
++
++typedef enum EXT_GPIO_NO {
++	EXT_GPIO_GPIO0 = 0,
++	EXT_GPIO_U0TXD,
++	EXT_GPIO_GPIO2,
++	EXT_GPIO_U0RXD,
++	EXT_GPIO_GPIO4,
++	EXT_GPIO_GPIO5,
++	EXT_GPIO_SD_CLK,
++	EXT_GPIO_SD_DATA0,
++	EXT_GPIO_SD_DATA1,
++	EXT_GPIO_SD_DATA2,
++	EXT_GPIO_SD_DATA3,
++	EXT_GPIO_SD_CMD,
++	EXT_GPIO_MTDI,
++	EXT_GPIO_MTCK,
++	EXT_GPIO_MTMS,
++	EXT_GPIO_MTDO,
++	EXT_GPIO_MAX_NUM
++} EXT_GPIO_NO_T;
++
++typedef enum EXT_GPIO_MODE {	//dir           def     pullup  mode    wake
++	EXT_GPIO_MODE_OOB = 0,	//output        1       0       n/a     n/a
++	EXT_GPIO_MODE_OUTPUT,	//output        /       0       n/a     n/a
++	EXT_GPIO_MODE_DISABLE,	//input         n/a     0       DIS     n/a
++	EXT_GPIO_MODE_INTR_POSEDGE,	//input         n/a     0       POS     1
++	EXT_GPIO_MODE_INTR_NEGEDGE,	//input         n/a     1       NEG     1
++	EXT_GPIO_MODE_INPUT,	//input         n/a     0       ANY     1
++	EXT_GPIO_MODE_INTR_LOLEVEL,	//input         n/a     1       LOW     1
++	EXT_GPIO_MODE_INTR_HILEVEL,	//input         n/a     0       HIGH    1
++	EXT_GPIO_MODE_MAX,
++} EXT_GPIO_MODE_T;
++
++typedef enum EXT_GPIO_STATE {
++	EXT_GPIO_STATE_LOW,
++	EXT_GPIO_STATE_HIGH,
++	EXT_GPIO_STATE_IDLE
++} EXT_GPIO_STATE_T;
++
++typedef irqreturn_t(*ext_irq_handler_t) (void);
++
++struct ext_gpio_info {
++	int gpio_no;
++	int gpio_mode;
++	int gpio_state;
++	ext_irq_handler_t irq_handler;
++};
++
++struct pending_intr_list_info {
++	u16 pending_intr_list[MAX_PENDING_INTR_LIST];
++	int start_pos;
++	int end_pos;
++	int curr_num;
++	spinlock_t spin_lock;
++};
++
++u16 ext_gpio_get_int_mask_reg(void);
++
++/* for extern user start */
++int ext_gpio_request(int gpio_no);
++int ext_gpio_release(int gpio_no);
++
++int ext_gpio_set_mode(int gpio_no, int mode, void *data);
++int ext_gpio_get_mode(int gpio_no);
++
++int ext_gpio_set_output_state(int gpio_no, int state);
++int ext_gpio_get_state(int gpio_no);
++
++int ext_irq_ack(int gpio_no);
++/* for extern user end */
++
++void ext_gpio_int_process(u16 value);
++
++int ext_gpio_init(struct esp_pub *epub);
++void ext_gpio_deinit(void);
++#endif				/* _ESP_EXT_H_ */
++
++#endif				/* USE_EXT_GPIO */
+diff --git a/drivers/net/wireless/esp8089/esp_file.c b/drivers/net/wireless/esp8089/esp_file.c
+new file mode 100644
+index 000000000000..ea702f010eec
+--- /dev/null
++++ b/drivers/net/wireless/esp8089/esp_file.c
+@@ -0,0 +1,258 @@
++/*
++ * Copyright (c) 2010 -2014 Espressif System.
++ *
++ *   file operation in kernel space
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++
++#include <linux/fs.h>
++#include <linux/vmalloc.h>
++#include <linux/kernel.h>
++#include <linux/version.h>
++#include <linux/moduleparam.h>
++#include <linux/firmware.h>
++#include <linux/netdevice.h>
++#include <linux/aio.h>
++#include <linux/property.h>
++#include <linux/of.h>
++#include "esp_file.h"
++#include "esp_debug.h"
++#include "esp_sif.h"
++
++static int mod_parm_crystal = -1;
++module_param_named(crystal, mod_parm_crystal, int, 0444);
++MODULE_PARM_DESC(crystal, "crystal frequency: 0=40MHz, 1=26MHz, 2=24MHz");
++
++struct esp_init_table_elem esp_init_table[MAX_ATTR_NUM] = {
++	/*
++	 * Crystal type:
++	 * 0: 40MHz (default)
++	 * 1: 26MHz (ESP8266 ESP-12F)
++	 * 2: 24MHz
++	 */
++	{"crystal_26M_en", 48, 0},
++	/*
++	 * Output crystal clock to pin:
++	 * 0: None
++	 * 1: GPIO1
++	 * 2: URXD0
++	 */
++	{"test_xtal", 49, 0},
++	/*
++	 * Host SDIO mode:
++	 * 0: Auto by pin strapping
++	 * 1: SDIO data output on negative edges (SDIO v1.1)
++	 * 2: SDIO data output on positive edges (SDIO v2.0)
++	 */
++	{"sdio_configure", 50, 2},
++	/*
++	 * WiFi/Bluetooth co-existence with BK3515A BT chip
++	 * 0: None
++	 * 1: GPIO0->WLAN_ACTIVE, MTMS->BT_ACTIVE, MTDI->BT_PRIORITY,
++	 *    U0TXD->ANT_SEL_BT, U0RXD->ANT_SEL_WIFI
++	 */
++	{"bt_configure", 51, 0},
++	/*
++	 * Antenna selection:
++	 * 0: Antenna is for WiFi
++	 * 1: Antenna is for Bluetooth
++	 */
++	{"bt_protocol", 52, 0},
++	/*
++	 * Dual antenna configuration mode:
++	 * 0: None
++	 * 1: U0RXD + XPD_DCDC
++	 * 2: U0RXD + GPIO0
++	 * 3: U0RXD + U0TXD
++	 */
++	{"dual_ant_configure", 53, 0},
++	/*
++	 * Firmware debugging output pin:
++	 * 0: None
++	 * 1: UART TX on GPIO2
++	 * 2: UART TX on U0TXD
++	 */
++	{"test_uart_configure", 54, 2},
++	/*
++	 * Whether to share crystal clock with BT (in sleep mode):
++	 * 0: no
++	 * 1: always on
++	 * 2: automatically on according to XPD_DCDC
++	 */
++	{"share_xtal", 55, 0},
++	/*
++	 * Allow chip to be woken up during sleep on pin:
++	 * 0: None
++	 * 1: XPD_DCDC
++	 * 2: GPIO0
++	 * 3: Both XPD_DCDC and GPIO0
++	 */
++	{"gpio_wake", 56, 0},
++	{"no_auto_sleep", 57, 0},
++	{"speed_suspend", 58, 0},
++	{"attr11", -1, -1},
++	{"attr12", -1, -1},
++	{"attr13", -1, -1},
++	{"attr14", -1, -1},
++	{"attr15", -1, -1},
++	//attr that is not send to target
++	/*
++	 * Allow chip to be reset by GPIO pin:
++	 * 0: no
++	 * 1: yes
++	 */
++	{"ext_rst", -1, 0},
++	{"wakeup_gpio", -1, 12},
++	{"ate_test", -1, 0},
++	{"attr19", -1, -1},
++	{"attr20", -1, -1},
++	{"attr21", -1, -1},
++	{"attr22", -1, -1},
++	{"attr23", -1, -1},
++};
++
++/*
++ * Export part of the configuration related to first initiliazition to the esp8089
++ */
++void esp_conf_upload_first(void)
++{
++	int i;
++
++	for (i = 0; i < MAX_ATTR_NUM; i++) {
++		if (esp_init_table[i].value < 0)
++			continue;
++
++		if (!strcmp(esp_init_table[i].attr, "share_xtal"))
++			sif_record_bt_config(esp_init_table[i].value);
++		else if (!strcmp(esp_init_table[i].attr, "ext_rst"))
++			sif_record_rst_config(esp_init_table[i].value);
++		else if (!strcmp(esp_init_table[i].attr, "wakeup_gpio"))
++			sif_record_wakeup_gpio_config(esp_init_table[i].value);
++		else if (!strcmp(esp_init_table[i].attr, "ate_test"))
++			sif_record_ate_config(esp_init_table[i].value);
++	}
++}
++
++/*
++ * Export part of the configuration related to second initiliazition
++ */
++void esp_conf_upload_second(u8 * init_data_buf, int buf_size)
++{
++	int i;
++
++	for (i = 0; i < MAX_FIX_ATTR_NUM; i++) {
++		if (esp_init_table[i].offset > -1
++		    && esp_init_table[i].offset < buf_size
++		    && esp_init_table[i].value > -1) {
++			*(u8 *) (init_data_buf +
++				 esp_init_table[i].offset) =
++			    esp_init_table[i].value;
++		} else if (esp_init_table[i].offset > buf_size) {
++			esp_dbg(ESP_DBG_ERROR,
++				"%s: offset[%d] longer than init_data_buf len[%d] Ignore\n",
++				__FUNCTION__, esp_init_table[i].offset,
++				buf_size);
++		}
++	}
++
++}
++
++
++void esp_conf_init(struct device *dev)
++{
++
++	struct device_node *np = dev->of_node;
++
++	if (np) {
++
++		u32 value;
++
++		if (!of_property_read_u32(np, "esp,crystal-26M-en", &value))
++			esp_conf_set_attr("crystal_26M_en", value);
++
++		if (!of_property_read_u32(np, "esp,sdio-configure", &value))
++			esp_conf_set_attr("sdio_configure", value);
++
++		if (of_property_read_bool(np, "esp,shared-xtal"))
++			esp_conf_set_attr("share_xtal", 1);
++
++		if (!of_property_read_u32(np, "esp,gpio-wake", &value))
++			esp_conf_set_attr("gpio_wake", value);
++
++		if (!of_property_read_u32(np, "esp,wakeup-gpio", &value))
++			esp_conf_set_attr("wakeup_gpio", value);
++
++		if (of_property_read_bool(np, "esp,configure-dual-antenna"))
++			esp_conf_set_attr("dual_ant_configure", 1);
++
++		if (of_property_read_bool(np, "esp,no-auto-sleep"))
++			esp_conf_set_attr("no_auto_sleep", 1);
++
++		if (of_property_read_bool(np, "esp,test-xtal"))
++			esp_conf_set_attr("test_xtal", 1);
++
++		if (of_property_read_bool(np, "esp,bt-configure"))
++			esp_conf_set_attr("bt_configure", 1);
++
++		if (!of_property_read_u32(np, "esp,bt-protocol", &value))
++			esp_conf_set_attr("bt_protocol", value);
++
++		if (of_property_read_bool(np, "esp,test-uart-configure"))
++			esp_conf_set_attr("test_uart_configure", 1);
++
++		if (of_property_read_bool(np, "esp,speed-suspend"))
++			esp_conf_set_attr("speed_suspend", 1);
++
++		if (of_property_read_bool(np, "esp,ate-test"))
++			esp_conf_set_attr("ate_test", 1);
++
++		if (!of_property_read_u32(np, "esp,ext-rst", &value))
++			esp_conf_set_attr("ext_rst", value);
++
++	}
++
++	if (mod_parm_crystal >= 0 && mod_parm_crystal <= 2)
++		esp_conf_set_attr("crystal_26M_en", mod_parm_crystal);
++
++
++	esp_conf_show_attrs();
++
++}
++
++int esp_conf_set_attr(char *name, u8 value) {
++
++	int i;
++
++	for (i = 0; i < MAX_ATTR_NUM; i++) {
++
++		if (strcmp(esp_init_table[i].attr, name) == 0) {
++			esp_dbg(ESP_DBG, "set config: %s value: %d", name, value);
++			esp_init_table[i].value = value;
++			return 0;
++		}
++
++	}
++
++	return -1;
++
++}
++
++void esp_conf_show_attrs(void)
++{
++	int i;
++	for (i = 0; i < MAX_ATTR_NUM; i++)
++		if (esp_init_table[i].offset > -1)
++			esp_dbg(ESP_SHOW, "config parm:%s (id:%d), value: %d\n",
++				esp_init_table[i].attr,
++				esp_init_table[i].offset,
++				esp_init_table[i].value);
++}
+diff --git a/drivers/net/wireless/esp8089/esp_file.h b/drivers/net/wireless/esp8089/esp_file.h
+new file mode 100644
+index 000000000000..5ba39c626baa
+--- /dev/null
++++ b/drivers/net/wireless/esp8089/esp_file.h
+@@ -0,0 +1,43 @@
++/*
++ * Copyright (c) 2010 -2014 Espressif System.
++ *
++ *   file operation in kernel space
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++
++#ifndef _ESP_FILE_H_
++#define _ESP_FILE_H_
++
++#include <linux/version.h>
++#include <linux/firmware.h>
++
++#define E_ROUND_UP(x, y)  ((((x) + ((y) - 1)) / (y)) * (y))
++
++#define CONF_ATTR_LEN 24
++#define CONF_VAL_LEN 3
++#define MAX_ATTR_NUM 24
++#define MAX_FIX_ATTR_NUM 16
++#define MAX_BUF_LEN ((CONF_ATTR_LEN + CONF_VAL_LEN + 2) * MAX_ATTR_NUM + 2)
++
++struct esp_init_table_elem {
++	char attr[CONF_ATTR_LEN];
++	int offset;
++	short value;
++};
++
++void esp_conf_init(struct device *dev);
++void esp_conf_upload_first(void);
++void esp_conf_upload_second(u8 * init_data_buf, int buf_size);
++int esp_conf_set_attr(char *name, u8 value);
++void esp_conf_show_attrs(void);
++
++#endif				/* _ESP_FILE_H_ */
+diff --git a/drivers/net/wireless/esp8089/esp_init_data.h b/drivers/net/wireless/esp8089/esp_init_data.h
+new file mode 100644
+index 000000000000..16f451affd1e
+--- /dev/null
++++ b/drivers/net/wireless/esp8089/esp_init_data.h
+@@ -0,0 +1,7 @@
++static char esp_init_data[] =
++    { 0x5, 0x0, 4, 2, 5, 5, 5, 2, 5, 0, 4, 5, 5, 4, 5, 5, 4, -2, -3, -1,
++-16, -16, -16, -32, -32, -32, 204, 1, 0xff, 0xff, 0, 0, 0, 0, 82, 78, 74, 68, 64, 56, 0,
++0, 1, 1, 2, 3, 4, 5, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 240, 10, 0x0, 0x0,
++0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++0 };
+diff --git a/drivers/net/wireless/esp8089/esp_io.c b/drivers/net/wireless/esp8089/esp_io.c
+new file mode 100644
+index 000000000000..6c5c01aad4e5
+--- /dev/null
++++ b/drivers/net/wireless/esp8089/esp_io.c
+@@ -0,0 +1,639 @@
++/*
++ * Copyright (c) 2009 - 2014 Espressif System.
++ *   IO interface
++ *    - sdio/spi common i/f driver
++ *    - target sdio hal
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++
++#include <linux/mmc/sdio_func.h>
++#include "esp_sif.h"
++#include "slc_host_register.h"
++#include "esp_debug.h"
++
++#ifdef SIF_DEBUG_DSR_DUMP_REG
++static void dump_slc_regs(struct slc_host_regs *regs);
++#endif				/* SIF_DEBUG_DSR_DUMP_REG */
++
++int esp_common_read(struct esp_pub *epub, u8 * buf, u32 len, int sync,
++		    bool noround)
++{
++	if (sync) {
++		return sif_lldesc_read_sync(epub, buf, len);
++	} else {
++		return sif_lldesc_read_raw(epub, buf, len, noround);
++	}
++}
++
++
++int esp_common_write(struct esp_pub *epub, u8 * buf, u32 len, int sync)
++{
++	if (sync) {
++		return sif_lldesc_write_sync(epub, buf, len);
++	} else {
++		return sif_lldesc_write_raw(epub, buf, len);
++	}
++}
++
++
++int esp_common_read_with_addr(struct esp_pub *epub, u32 addr, u8 * buf,
++			      u32 len, int sync)
++{
++	if (sync) {
++		return sif_io_sync(epub, addr, buf, len,
++				   SIF_FROM_DEVICE | SIF_SYNC |
++				   SIF_BYTE_BASIS | SIF_INC_ADDR);
++	} else {
++		return sif_io_raw(epub, addr, buf, len,
++				  SIF_FROM_DEVICE | SIF_BYTE_BASIS |
++				  SIF_INC_ADDR);
++	}
++
++}
++
++
++int esp_common_write_with_addr(struct esp_pub *epub, u32 addr, u8 * buf,
++			       u32 len, int sync)
++{
++	if (sync) {
++		return sif_io_sync(epub, addr, buf, len,
++				   SIF_TO_DEVICE | SIF_SYNC |
++				   SIF_BYTE_BASIS | SIF_INC_ADDR);
++	} else {
++		return sif_io_raw(epub, addr, buf, len,
++				  SIF_TO_DEVICE | SIF_BYTE_BASIS |
++				  SIF_INC_ADDR);
++	}
++}
++
++int esp_common_readbyte_with_addr(struct esp_pub *epub, u32 addr, u8 * buf,
++				  int sync)
++{
++	if (sync) {
++		int res;
++		sif_lock_bus(epub);
++		*buf = sdio_io_readb(epub, addr, &res);
++		sif_unlock_bus(epub);
++		return res;
++	} else {
++		int res;
++		*buf = sdio_io_readb(epub, addr, &res);
++		return res;
++	}
++
++}
++
++
++
++int esp_common_writebyte_with_addr(struct esp_pub *epub, u32 addr, u8 buf,
++				   int sync)
++{
++	if (sync) {
++		int res;
++		sif_lock_bus(epub);
++		sdio_io_writeb(epub, buf, addr, &res);
++		sif_unlock_bus(epub);
++		return res;
++	} else {
++		int res;
++		sdio_io_writeb(epub, buf, addr, &res);
++		return res;
++	}
++}
++
++int sif_read_reg_window(struct esp_pub *epub, unsigned int reg_addr,
++			u8 * value)
++{
++	u8 *p_tbuf = NULL;
++	int ret = 0;
++	int retry = 20;
++
++	reg_addr >>= 2;
++	if (reg_addr > 0x1f)
++		return -1;
++
++	p_tbuf = kzalloc(4, GFP_KERNEL);
++	if (p_tbuf == NULL)
++		return -ENOMEM;
++
++	p_tbuf[0] = 0x80 | (reg_addr & 0x1f);
++
++	ret =
++	    esp_common_write_with_addr(epub, SLC_HOST_WIN_CMD, p_tbuf, 1,
++				       ESP_SIF_NOSYNC);
++
++	if (ret == 0) {
++		do {
++			if (retry < 20)
++				mdelay(10);
++			retry--;
++			ret =
++			    esp_common_read_with_addr(epub,
++						      SLC_HOST_STATE_W0,
++						      p_tbuf, 4,
++						      ESP_SIF_NOSYNC);
++		} while (retry > 0 && ret != 0);
++	}
++
++	if (ret == 0)
++		memcpy(value, p_tbuf, 4);
++
++	kfree(p_tbuf);
++	return ret;
++}
++
++int sif_write_reg_window(struct esp_pub *epub, unsigned int reg_addr,
++			 u8 * value)
++{
++	u8 *p_tbuf = NULL;
++	int ret = 0;
++
++	reg_addr >>= 2;
++	if (reg_addr > 0x1f)
++		return -1;
++
++	p_tbuf = kzalloc(8, GFP_KERNEL);
++	if (p_tbuf == NULL)
++		return -ENOMEM;
++	memcpy(p_tbuf, value, 4);
++	p_tbuf[4] = 0xc0 | (reg_addr & 0x1f);
++
++	ret =
++	    esp_common_write_with_addr(epub, SLC_HOST_CONF_W5, p_tbuf, 5,
++				       ESP_SIF_NOSYNC);
++
++	kfree(p_tbuf);
++	return ret;
++}
++
++int sif_ack_target_read_err(struct esp_pub *epub)
++{
++	u32 value[1];
++	int ret;
++
++	ret = sif_read_reg_window(epub, SLC_RX_LINK, (u8 *) value);
++	if (ret)
++		return ret;
++	value[0] |= SLC_RXLINK_START;
++	ret = sif_write_reg_window(epub, SLC_RX_LINK, (u8 *) value);
++	return ret;
++}
++
++int sif_had_io_enable(struct esp_pub *epub)
++{
++	u32 *p_tbuf = NULL;
++	int ret;
++
++	p_tbuf = kzalloc(sizeof(u32), GFP_KERNEL);
++	if (p_tbuf == NULL)
++		return -ENOMEM;
++
++	*p_tbuf =
++	    SLC_TXEOF_ENA | (0x4 << SLC_FIFO_MAP_ENA_S) | SLC_TX_DUMMY_MODE
++	    | SLC_HDA_MAP_128K | (0xFE << SLC_TX_PUSH_IDLE_NUM_S);
++	ret = sif_write_reg_window(epub, SLC_BRIDGE_CONF, (u8 *) p_tbuf);
++
++	if (ret)
++		goto _err;
++
++	*p_tbuf = 0x30;
++	ret =
++	    esp_common_write_with_addr((epub), SLC_HOST_CONF_W4 + 1,
++				       (u8 *) p_tbuf, 1, ESP_SIF_NOSYNC);
++
++	if (ret)
++		goto _err;
++	//set w3 0
++	*p_tbuf = 0x1;
++	ret =
++	    esp_common_write_with_addr((epub), SLC_HOST_CONF_W3,
++				       (u8 *) p_tbuf, 1, ESP_SIF_NOSYNC);
++
++      _err:
++	kfree(p_tbuf);
++	return ret;
++}
++
++typedef enum _SDIO_INTR_MODE {
++	SDIO_INTR_IB = 0,
++	SDIO_INTR_OOB_TOGGLE,
++	SDIO_INTR_OOB_HIGH_LEVEL,
++	SDIO_INTR_OOB_LOW_LEVEL,
++} SDIO_INTR_MODE;
++
++#define GEN_GPIO_SEL(_gpio_num, _sel_func, _intr_mode, _offset) (((_offset)<< 9 ) |((_intr_mode) << 7)|((_sel_func) << 4)|(_gpio_num))
++//bit[3:0] = gpio num, 2
++//bit[6:4] = gpio sel func, 0
++//bit[8:7] = gpio intr mode, SDIO_INTR_OOB_TOGGLE
++//bit[15:9] = register offset, 0x38
++
++u16 gpio_sel_sets[17] = {
++	GEN_GPIO_SEL(0, 0, SDIO_INTR_OOB_TOGGLE, 0x34),	//GPIO0
++	GEN_GPIO_SEL(1, 3, SDIO_INTR_OOB_TOGGLE, 0x18),	//U0TXD
++	GEN_GPIO_SEL(2, 0, SDIO_INTR_OOB_TOGGLE, 0x38),	//GPIO2
++	GEN_GPIO_SEL(3, 3, SDIO_INTR_OOB_TOGGLE, 0x14),	//U0RXD
++	GEN_GPIO_SEL(4, 0, SDIO_INTR_OOB_TOGGLE, 0x3C),	//GPIO4
++	GEN_GPIO_SEL(5, 0, SDIO_INTR_OOB_TOGGLE, 0x40),	//GPIO5
++	GEN_GPIO_SEL(6, 3, SDIO_INTR_OOB_TOGGLE, 0x1C),	//SD_CLK
++	GEN_GPIO_SEL(7, 3, SDIO_INTR_OOB_TOGGLE, 0x20),	//SD_DATA0
++	GEN_GPIO_SEL(8, 3, SDIO_INTR_OOB_TOGGLE, 0x24),	//SD_DATA1
++	GEN_GPIO_SEL(9, 3, SDIO_INTR_OOB_TOGGLE, 0x28),	//SD_DATA2
++	GEN_GPIO_SEL(10, 3, SDIO_INTR_OOB_TOGGLE, 0x2C),	//SD_DATA3
++	GEN_GPIO_SEL(11, 3, SDIO_INTR_OOB_TOGGLE, 0x30),	//SD_CMD
++	GEN_GPIO_SEL(12, 3, SDIO_INTR_OOB_TOGGLE, 0x04),	//MTDI
++	GEN_GPIO_SEL(13, 3, SDIO_INTR_OOB_TOGGLE, 0x08),	//MTCK
++	GEN_GPIO_SEL(14, 3, SDIO_INTR_OOB_TOGGLE, 0x0C),	//MTMS
++	GEN_GPIO_SEL(15, 3, SDIO_INTR_OOB_TOGGLE, 0x10),	//MTDO
++	//pls do not change sel before, if you want to change intr mode,change the one blow
++	//GEN_GPIO_SEL(2, 0, SDIO_INTR_OOB_TOGGLE, 0x38)
++	GEN_GPIO_SEL(2, 0, SDIO_INTR_OOB_LOW_LEVEL, 0x38)
++};
++
++#if defined(USE_EXT_GPIO)
++u16 gpio_forbidden = 0;
++#endif
++
++int sif_interrupt_target(struct esp_pub *epub, u8 index)
++{
++	u8 low_byte = BIT(index);
++	return esp_common_writebyte_with_addr(epub, SLC_HOST_CONF_W4 + 2,
++					      low_byte, ESP_SIF_NOSYNC);
++
++}
++
++#ifdef USE_EXT_GPIO
++int sif_config_gpio_mode(struct esp_pub *epub, u8 gpio_num, u8 gpio_mode)
++{
++	u32 *p_tbuf = NULL;
++	int err;
++
++	if ((BIT(gpio_num) & gpio_forbidden) || gpio_num > 15)
++		return -EINVAL;
++
++	p_tbuf = kzalloc(sizeof(u32), GFP_KERNEL);
++	if (p_tbuf == NULL)
++		return -ENOMEM;
++	*p_tbuf = (gpio_mode << 16) | gpio_sel_sets[gpio_num];
++	err =
++	    esp_common_write_with_addr(epub, SLC_HOST_CONF_W1,
++				       (u8 *) p_tbuf, sizeof(u32),
++				       ESP_SIF_NOSYNC);
++	kfree(p_tbuf);
++	if (err)
++		return err;
++
++	return sif_interrupt_target(epub, 4);
++}
++
++int sif_set_gpio_output(struct esp_pub *epub, u16 mask, u16 value)
++{
++	u32 *p_tbuf = NULL;
++	int err;
++
++	mask &= ~gpio_forbidden;
++	p_tbuf = kzalloc(sizeof(u32), GFP_KERNEL);
++	if (p_tbuf == NULL)
++		return -ENOMEM;
++	*p_tbuf = (mask << 16) | value;
++	err =
++	    esp_common_write_with_addr(epub, SLC_HOST_CONF_W2,
++				       (u8 *) p_tbuf, sizeof(u32),
++				       ESP_SIF_NOSYNC);
++	kfree(p_tbuf);
++	if (err)
++		return err;
++
++	return sif_interrupt_target(epub, 5);
++}
++
++int sif_get_gpio_intr(struct esp_pub *epub, u16 intr_mask, u16 * value)
++{
++	u32 *p_tbuf = NULL;
++	int err;
++
++	p_tbuf = kzalloc(sizeof(u32), GFP_KERNEL);
++	if (p_tbuf == NULL)
++		return -ENOMEM;
++	*p_tbuf = 0;
++	err =
++	    esp_common_read_with_addr(epub, SLC_HOST_CONF_W3,
++				      (u8 *) p_tbuf, sizeof(u32),
++				      ESP_SIF_NOSYNC);
++	if (err) {
++		kfree(p_tbuf);
++		return err;
++	}
++
++	*value = *p_tbuf & intr_mask;
++	kfree(p_tbuf);
++	if (*value == 0)
++		return 0;
++	return sif_interrupt_target(epub, 6);
++}
++
++int sif_get_gpio_input(struct esp_pub *epub, u16 * mask, u16 * value)
++{
++	u32 *p_tbuf = NULL;
++	int err;
++
++	err = sif_interrupt_target(epub, 3);
++	if (err)
++		return err;
++
++	udelay(20);
++	p_tbuf = kzalloc(sizeof(u32), GFP_KERNEL);
++	if (p_tbuf == NULL)
++		return -ENOMEM;
++	*p_tbuf = 0;
++	err =
++	    esp_common_read_with_addr(epub, SLC_HOST_CONF_W3,
++				      (u8 *) p_tbuf, sizeof(u32),
++				      ESP_SIF_NOSYNC);
++	if (err) {
++		kfree(p_tbuf);
++		return err;
++	}
++
++	*mask = *p_tbuf >> 16;
++	*value = *p_tbuf & *mask;
++	kfree(p_tbuf);
++
++	return 0;
++}
++#endif
++
++void check_target_id(struct esp_pub *epub)
++{
++	u32 date;
++	int err = 0;
++	int i;
++
++	EPUB_CTRL_CHECK(epub, _err);
++
++	sif_lock_bus(epub);
++
++	for (i = 0; i < 4; i++) {
++		err =
++		    esp_common_readbyte_with_addr(epub, SLC_HOST_DATE + i,
++						  (u8 *) & date + i,
++						  ESP_SIF_NOSYNC);
++		err =
++		    esp_common_readbyte_with_addr(epub, SLC_HOST_ID + i,
++						  (u8 *) &
++						  EPUB_TO_CTRL(epub)->
++						  target_id + i,
++						  ESP_SIF_NOSYNC);
++	}
++
++	sif_unlock_bus(epub);
++
++	esp_dbg(ESP_DBG_LOG, "\n\n \t\t SLC data 0x%08x, ID 0x%08x\n\n",
++		date, EPUB_TO_CTRL(epub)->target_id);
++
++	switch (EPUB_TO_CTRL(epub)->target_id) {
++	case 0x100:
++		EPUB_TO_CTRL(epub)->slc_window_end_addr = 0x20000;
++		break;
++	case 0x600:
++		EPUB_TO_CTRL(epub)->slc_window_end_addr = 0x20000 - 0x800;
++
++		do {
++			u16 gpio_sel;
++			u8 low_byte = 0;
++			u8 high_byte = 0;
++			u8 byte2 = 0;
++			u8 byte3 = 0;
++#ifdef USE_OOB_INTR
++			gpio_sel = gpio_sel_sets[16];
++			low_byte = gpio_sel;
++			high_byte = gpio_sel >> 8;
++#ifdef USE_EXT_GPIO
++			gpio_forbidden |= BIT(gpio_sel & 0xf);
++#endif				/* USE_EXT_GPIO */
++#endif				/* USE_OOB_INTR */
++
++			if (sif_get_bt_config() == 1
++			    && sif_get_rst_config() != 1) {
++				u8 gpio_num = sif_get_wakeup_gpio_config();
++				gpio_sel = gpio_sel_sets[gpio_num];
++				byte2 = gpio_sel;
++				byte3 = gpio_sel >> 8;
++#ifdef USE_EXT_GPIO
++				gpio_forbidden |= BIT(gpio_num);
++#endif
++			}
++			sif_lock_bus(epub);
++			err =
++			    esp_common_writebyte_with_addr(epub,
++							   SLC_HOST_CONF_W1,
++							   low_byte,
++							   ESP_SIF_NOSYNC);
++			err =
++			    esp_common_writebyte_with_addr(epub,
++							   SLC_HOST_CONF_W1
++							   + 1, high_byte,
++							   ESP_SIF_NOSYNC);
++			err =
++			    esp_common_writebyte_with_addr(epub,
++							   SLC_HOST_CONF_W1
++							   + 2, byte2,
++							   ESP_SIF_NOSYNC);
++			err =
++			    esp_common_writebyte_with_addr(epub,
++							   SLC_HOST_CONF_W1
++							   + 3, byte3,
++							   ESP_SIF_NOSYNC);
++			sif_unlock_bus(epub);
++		} while (0);
++		break;
++	default:
++		EPUB_TO_CTRL(epub)->slc_window_end_addr = 0x20000;
++		break;
++	}
++      _err:
++	return;
++}
++
++u32 sif_get_blksz(struct esp_pub * epub)
++{
++	EPUB_CTRL_CHECK(epub, _err);
++
++	return EPUB_TO_CTRL(epub)->slc_blk_sz;
++      _err:
++	return 512;
++}
++
++u32 sif_get_target_id(struct esp_pub * epub)
++{
++	EPUB_CTRL_CHECK(epub, _err);
++
++	return EPUB_TO_CTRL(epub)->target_id;
++      _err:
++	return 0x600;
++}
++
++void sif_dsr(struct sdio_func *func)
++{
++	struct esp_sdio_ctrl *sctrl = sdio_get_drvdata(func);
++	static int dsr_cnt = 0, real_intr_cnt = 0, bogus_intr_cnt = 0;
++	struct slc_host_regs *regs = &(sctrl->slc_regs);
++	esp_dbg(ESP_DBG_TRACE, " %s enter %d \n", __func__, dsr_cnt++);
++
++	sdio_release_host(sctrl->func);
++
++
++	sif_lock_bus(sctrl->epub);
++
++
++	do {
++		int ret = 0;
++
++		memset(regs, 0x0, sizeof(struct slc_host_regs));
++
++		ret =
++		    esp_common_read_with_addr(sctrl->epub,
++					      REG_SLC_HOST_BASE + 8,
++					      (u8 *) regs,
++					      sizeof(struct slc_host_regs),
++					      ESP_SIF_NOSYNC);
++
++		if ((regs->intr_raw & SLC_HOST_RX_ST) && (ret == 0)) {
++			esp_dbg(ESP_DBG_TRACE, "%s eal intr cnt: %d",
++				__func__, ++real_intr_cnt);
++
++			esp_dsr(sctrl->epub);
++
++		} else {
++			sif_unlock_bus(sctrl->epub);
++
++			esp_dbg(ESP_DBG_TRACE, "%s bogus_intr_cnt %d\n",
++				__func__, ++bogus_intr_cnt);
++		}
++
++#ifdef SIF_DEBUG_DSR_DUMP_REG
++		dump_slc_regs(regs);
++#endif				/* SIF_DEBUG_DUMP_DSR */
++
++	} while (0);
++
++	sdio_claim_host(func);
++
++	atomic_set(&sctrl->irq_handling, 0);
++}
++
++
++struct slc_host_regs *sif_get_regs(struct esp_pub *epub)
++{
++	EPUB_CTRL_CHECK(epub, _err);
++
++	return &EPUB_TO_CTRL(epub)->slc_regs;
++      _err:
++	return NULL;
++}
++
++void sif_disable_target_interrupt(struct esp_pub *epub)
++{
++	EPUB_FUNC_CHECK(epub, _exit);
++	sif_lock_bus(epub);
++#ifdef HOST_RESET_BUG
++	mdelay(10);
++#endif
++	memset(EPUB_TO_CTRL(epub)->dma_buffer, 0x00, sizeof(u32));
++	esp_common_write_with_addr(epub, SLC_HOST_INT_ENA,
++				   EPUB_TO_CTRL(epub)->dma_buffer,
++				   sizeof(u32), ESP_SIF_NOSYNC);
++#ifdef HOST_RESET_BUG
++	mdelay(10);
++#endif
++
++	sif_unlock_bus(epub);
++
++	mdelay(1);
++
++	sif_lock_bus(epub);
++	sif_interrupt_target(epub, 7);
++	sif_unlock_bus(epub);
++      _exit:
++	return;
++}
++
++#ifdef SIF_DEBUG_DSR_DUMP_REG
++static void dump_slc_regs(struct slc_host_regs *regs)
++{
++	esp_dbg(ESP_DBG_TRACE, "\n\n ------- %s --------------\n",
++		__func__);
++
++	esp_dbg(ESP_DBG_TRACE, " \
++                        intr_raw 0x%08X \t \n  \
++                        state_w0 0x%08X \t state_w1 0x%08X \n  \
++                        config_w0 0x%08X \t config_w1 0x%08X \n \
++                        intr_status 0x%08X \t config_w2 0x%08X \n \
++                        config_w3 0x%08X \t config_w4 0x%08X \n \
++                        token_wdata 0x%08X \t intr_clear 0x%08X \n \
++                        intr_enable 0x%08X \n\n", regs->intr_raw, regs->state_w0, regs->state_w1, regs->config_w0, regs->config_w1, regs->intr_status, regs->config_w2, regs->config_w3, regs->config_w4, regs->token_wdata, regs->intr_clear, regs->intr_enable);
++}
++#endif				/* SIF_DEBUG_DSR_DUMP_REG */
++
++static int bt_config = 0;
++void sif_record_bt_config(int value)
++{
++	bt_config = value;
++}
++
++int sif_get_bt_config(void)
++{
++	return bt_config;
++}
++
++static int rst_config = 0;
++void sif_record_rst_config(int value)
++{
++	rst_config = value;
++}
++
++int sif_get_rst_config(void)
++{
++	return rst_config;
++}
++
++static int ate_test = 0;
++void sif_record_ate_config(int value)
++{
++	ate_test = value;
++}
++
++int sif_get_ate_config(void)
++{
++	return ate_test;
++}
++
++static int retry_reset = 0;
++void sif_record_retry_config(void)
++{
++	retry_reset = 1;
++}
++
++int sif_get_retry_config(void)
++{
++	return retry_reset;
++}
++
++static int wakeup_gpio = 12;
++void sif_record_wakeup_gpio_config(int value)
++{
++	wakeup_gpio = value;
++}
++
++int sif_get_wakeup_gpio_config(void)
++{
++	return wakeup_gpio;
++}
+diff --git a/drivers/net/wireless/esp8089/esp_mac80211.c b/drivers/net/wireless/esp8089/esp_mac80211.c
+new file mode 100644
+index 000000000000..14186365fdd4
+--- /dev/null
++++ b/drivers/net/wireless/esp8089/esp_mac80211.c
+@@ -0,0 +1,1728 @@
++/*
++ * Copyright (c) 2011-2014 Espressif System.
++ *
++ *     MAC80211 support module
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++
++#include <linux/etherdevice.h>
++#include <linux/workqueue.h>
++#include <linux/nl80211.h>
++#include <linux/ieee80211.h>
++#include <linux/slab.h>
++#include <net/cfg80211.h>
++#include <net/mac80211.h>
++#include <linux/version.h>
++#include <net/regulatory.h>
++#include "esp_pub.h"
++#include "esp_sip.h"
++#include "esp_ctrl.h"
++#include "esp_sif.h"
++#include "esp_debug.h"
++#include "esp_wl.h"
++#include "esp_utils.h"
++
++#define ESP_IEEE80211_DBG esp_dbg
++
++#define GET_NEXT_SEQ(seq) (((seq) +1) & 0x0fff)
++
++static u8 esp_mac_addr[ETH_ALEN * 2];
++static u8 getaddr_index(u8 * addr, struct esp_pub *epub);
++
++static
++void
++esp_op_tx(struct ieee80211_hw *hw, struct ieee80211_tx_control *control,
++	  struct sk_buff *skb)
++{
++	struct esp_pub *epub = (struct esp_pub *) hw->priv;
++
++	ESP_IEEE80211_DBG(ESP_DBG_LOG, "%s enter\n", __func__);
++	if (!mod_support_no_txampdu() &&
++	    cfg80211_get_chandef_type(&epub->hw->conf.chandef) !=
++	    NL80211_CHAN_NO_HT) {
++		struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
++		struct ieee80211_hdr *wh =
++		    (struct ieee80211_hdr *) skb->data;
++		if (ieee80211_is_data_qos(wh->frame_control)) {
++			if (!(tx_info->flags & IEEE80211_TX_CTL_AMPDU)) {
++				u8 tidno =
++				    ieee80211_get_qos_ctl(wh)[0] &
++				    IEEE80211_QOS_CTL_TID_MASK;
++				struct esp_node *node =
++				    esp_get_node_by_addr(epub, wh->addr1);
++				{
++					struct esp_tx_tid *tid =
++					    &node->tid[tidno];
++					//record ssn
++					spin_lock_bh(&epub->tx_ampdu_lock);
++					tid->ssn =
++					    GET_NEXT_SEQ(le16_to_cpu
++							 (wh->
++							  seq_ctrl) >> 4);
++					ESP_IEEE80211_DBG(ESP_DBG_TRACE,
++							  "tidno:%u,ssn:%u\n",
++							  tidno, tid->ssn);
++					spin_unlock_bh(&epub->
++						       tx_ampdu_lock);
++				}
++			} else {
++				ESP_IEEE80211_DBG(ESP_DBG_TRACE,
++						  "tx ampdu pkt, sn:%u, %u\n",
++						  le16_to_cpu(wh->
++							      seq_ctrl) >>
++						  4, skb->len);
++			}
++		}
++	}
++#ifdef GEN_ERR_CHECKSUM
++	esp_gen_err_checksum(skb);
++#endif
++
++	sip_tx_data_pkt_enqueue(epub, skb);
++	if (epub)
++		ieee80211_queue_work(hw, &epub->tx_work);
++}
++
++static int esp_op_start(struct ieee80211_hw *hw)
++{
++	struct esp_pub *epub;
++
++	ESP_IEEE80211_DBG(ESP_DBG_OP, "%s\n", __func__);
++
++	if (!hw) {
++		ESP_IEEE80211_DBG(ESP_DBG_ERROR, "%s no hw!\n", __func__);
++		return -EINVAL;
++	}
++
++	epub = (struct esp_pub *) hw->priv;
++
++	if (!epub) {
++		ESP_IEEE80211_DBG(ESP_DBG_ERROR, "%s no epub!\n",
++				  __func__);
++		return EINVAL;
++	}
++	/*add rfkill poll function */
++
++	atomic_set(&epub->wl.off, 0);
++	wiphy_rfkill_start_polling(hw->wiphy);
++	return 0;
++}
++
++static void esp_op_stop(struct ieee80211_hw *hw)
++{
++	struct esp_pub *epub;
++
++	ESP_IEEE80211_DBG(ESP_DBG_OP, "%s\n", __func__);
++
++	if (!hw) {
++		ESP_IEEE80211_DBG(ESP_DBG_ERROR, "%s no hw!\n", __func__);
++		return;
++	}
++
++	epub = (struct esp_pub *) hw->priv;
++
++	if (!epub) {
++		ESP_IEEE80211_DBG(ESP_DBG_ERROR, "%s no epub!\n",
++				  __func__);
++		return;
++	}
++
++	atomic_set(&epub->wl.off, 1);
++
++#ifdef HOST_RESET_BUG
++	mdelay(200);
++#endif
++
++	if (epub->wl.scan_req) {
++		hw_scan_done(epub, true);
++		epub->wl.scan_req = NULL;
++		//msleep(2);
++	}
++}
++
++#ifdef CONFIG_PM
++static int esp_op_suspend(struct ieee80211_hw *hw,
++			  struct cfg80211_wowlan *wowlan)
++{
++	esp_dbg(ESP_DBG_OP, "%s\n", __func__);
++
++	return 0;
++}
++
++static int esp_op_resume(struct ieee80211_hw *hw)
++{
++	esp_dbg(ESP_DBG_OP, "%s\n", __func__);
++
++	return 0;
++}
++#endif				//CONFIG_PM
++
++static int esp_op_add_interface(struct ieee80211_hw *hw,
++				struct ieee80211_vif *vif)
++{
++	struct esp_pub *epub = (struct esp_pub *) hw->priv;
++	struct esp_vif *evif = (struct esp_vif *) vif->drv_priv;
++	struct sip_cmd_setvif svif;
++
++	ESP_IEEE80211_DBG(ESP_DBG_OP, "%s enter: type %d, addr %pM\n",
++			  __func__, vif->type, vif->addr);
++
++	memset(&svif, 0, sizeof(struct sip_cmd_setvif));
++	memcpy(svif.mac, vif->addr, ETH_ALEN);
++	evif->index = svif.index = getaddr_index(vif->addr, epub);
++	evif->epub = epub;
++	epub->vif = vif;
++	svif.set = 1;
++	if ((1 << svif.index) & epub->vif_slot) {
++		ESP_IEEE80211_DBG(ESP_DBG_ERROR,
++				  "%s interface %d already used\n",
++				  __func__, svif.index);
++		return -EOPNOTSUPP;
++	}
++	epub->vif_slot |= 1 << svif.index;
++
++	if (svif.index == ESP_PUB_MAX_VIF) {
++		ESP_IEEE80211_DBG(ESP_DBG_ERROR,
++				  "%s only support MAX %d interface\n",
++				  __func__, ESP_PUB_MAX_VIF);
++		return -EOPNOTSUPP;
++	}
++
++	switch (vif->type) {
++	case NL80211_IFTYPE_STATION:
++		//if (svif.index == 1)
++		//      vif->type = NL80211_IFTYPE_UNSPECIFIED;
++		ESP_IEEE80211_DBG(ESP_DBG_TRACE, "%s STA \n", __func__);
++		svif.op_mode = 0;
++		svif.is_p2p = 0;
++		break;
++	case NL80211_IFTYPE_AP:
++		ESP_IEEE80211_DBG(ESP_DBG_TRACE, "%s AP \n", __func__);
++		svif.op_mode = 1;
++		svif.is_p2p = 0;
++		break;
++	case NL80211_IFTYPE_P2P_CLIENT:
++		ESP_IEEE80211_DBG(ESP_DBG_TRACE, "%s P2P_CLIENT \n", __func__);
++		svif.op_mode = 0;
++		svif.is_p2p = 1;
++		break;
++	case NL80211_IFTYPE_P2P_GO:
++		ESP_IEEE80211_DBG(ESP_DBG_TRACE, "%s P2P_GO \n", __func__);
++		svif.op_mode = 1;
++		svif.is_p2p = 1;
++		break;
++	case NL80211_IFTYPE_UNSPECIFIED:
++	case NL80211_IFTYPE_ADHOC:
++	case NL80211_IFTYPE_AP_VLAN:
++	case NL80211_IFTYPE_WDS:
++	case NL80211_IFTYPE_MONITOR:
++	default:
++		ESP_IEEE80211_DBG(ESP_DBG_ERROR,
++				  "%s does NOT support type %d\n",
++				  __func__, vif->type);
++		return -EOPNOTSUPP;
++	}
++
++	sip_cmd(epub, SIP_CMD_SETVIF, (u8 *) & svif,
++		sizeof(struct sip_cmd_setvif));
++	return 0;
++}
++
++static int esp_op_change_interface(struct ieee80211_hw *hw,
++				   struct ieee80211_vif *vif,
++				   enum nl80211_iftype new_type, bool p2p)
++{
++	struct esp_pub *epub = (struct esp_pub *) hw->priv;
++	struct esp_vif *evif = (struct esp_vif *) vif->drv_priv;
++	struct sip_cmd_setvif svif;
++	ESP_IEEE80211_DBG(ESP_DBG_OP, "%s enter,change to if:%d \n",
++			  __func__, new_type);
++
++	if (new_type == NL80211_IFTYPE_AP) {
++		ESP_IEEE80211_DBG(ESP_DBG_TRACE, "%s enter,change to AP \n",
++				  __func__);
++	}
++
++	if (vif->type != new_type) {
++		ESP_IEEE80211_DBG(ESP_DBG_TRACE, "%s type from %d to %d\n",
++				  __func__, vif->type, new_type);
++	}
++
++	memset(&svif, 0, sizeof(struct sip_cmd_setvif));
++	memcpy(svif.mac, vif->addr, ETH_ALEN);
++	svif.index = evif->index;
++	svif.set = 2;
++
++	switch (new_type) {
++	case NL80211_IFTYPE_STATION:
++		svif.op_mode = 0;
++		svif.is_p2p = p2p;
++		break;
++	case NL80211_IFTYPE_AP:
++		svif.op_mode = 1;
++		svif.is_p2p = p2p;
++		break;
++	case NL80211_IFTYPE_P2P_CLIENT:
++		svif.op_mode = 0;
++		svif.is_p2p = 1;
++		break;
++	case NL80211_IFTYPE_P2P_GO:
++		svif.op_mode = 1;
++		svif.is_p2p = 1;
++		break;
++	case NL80211_IFTYPE_UNSPECIFIED:
++	case NL80211_IFTYPE_ADHOC:
++	case NL80211_IFTYPE_AP_VLAN:
++	case NL80211_IFTYPE_WDS:
++	case NL80211_IFTYPE_MONITOR:
++	default:
++		ESP_IEEE80211_DBG(ESP_DBG_ERROR,
++				  "%s does NOT support type %d\n",
++				  __func__, vif->type);
++		return -EOPNOTSUPP;
++	}
++	sip_cmd(epub, SIP_CMD_SETVIF, (u8 *) & svif,
++		sizeof(struct sip_cmd_setvif));
++	return 0;
++}
++
++static void esp_op_remove_interface(struct ieee80211_hw *hw,
++				    struct ieee80211_vif *vif)
++{
++	struct esp_pub *epub = (struct esp_pub *) hw->priv;
++	struct esp_vif *evif = (struct esp_vif *) vif->drv_priv;
++	struct sip_cmd_setvif svif;
++
++	ESP_IEEE80211_DBG(ESP_DBG_OP,
++			  "%s enter, vif addr %pM, beacon enable %x\n",
++			  __func__, vif->addr,
++			  vif->bss_conf.enable_beacon);
++
++	memset(&svif, 0, sizeof(struct sip_cmd_setvif));
++	svif.index = evif->index;
++	epub->vif_slot &= ~(1 << svif.index);
++
++	if (evif->ap_up) {
++		evif->beacon_interval = 0;
++		del_timer_sync(&evif->beacon_timer);
++		evif->ap_up = false;
++	}
++	epub->vif = NULL;
++	evif->epub = NULL;
++
++	sip_cmd(epub, SIP_CMD_SETVIF, (u8 *) & svif,
++		sizeof(struct sip_cmd_setvif));
++
++	/* clean up tx/rx queue */
++
++}
++
++#define BEACON_TIM_SAVE_MAX 20
++u8 beacon_tim_saved[BEACON_TIM_SAVE_MAX];
++int beacon_tim_count;
++static void beacon_tim_init(void)
++{
++	memset(beacon_tim_saved, 0, BEACON_TIM_SAVE_MAX);
++	beacon_tim_count = 0;
++}
++
++static u8 beacon_tim_save(u8 this_tim)
++{
++	u8 all_tim = 0;
++	int i;
++	beacon_tim_saved[beacon_tim_count] = this_tim;
++	if (++beacon_tim_count >= BEACON_TIM_SAVE_MAX)
++		beacon_tim_count = 0;
++	for (i = 0; i < BEACON_TIM_SAVE_MAX; i++)
++		all_tim |= beacon_tim_saved[i];
++	return all_tim;
++}
++
++static bool beacon_tim_alter(struct sk_buff *beacon)
++{
++	u8 *p, *tim_end;
++	u8 tim_count;
++	int len;
++	int remain_len;
++	struct ieee80211_mgmt *mgmt;
++
++	if (beacon == NULL)
++		return false;
++
++	mgmt = (struct ieee80211_mgmt *) ((u8 *) beacon->data);
++
++	remain_len =
++	    beacon->len - ((u8 *) mgmt->u.beacon.variable - (u8 *) mgmt +
++			   12);
++	p = mgmt->u.beacon.variable;
++
++	while (remain_len > 0) {
++		len = *(++p);
++		if (*p == WLAN_EID_TIM) {	// tim field
++			tim_end = p + len;
++			tim_count = *(++p);
++			p += 2;
++			//multicast
++			if (tim_count == 0)
++				*p |= 0x1;
++			if ((*p & 0xfe) == 0 && tim_end >= p + 1) {	// we only support 8 sta in this case
++				p++;
++				*p = beacon_tim_save(*p);
++			}
++			return tim_count == 0;
++		}
++		p += (len + 1);
++		remain_len -= (2 + len);
++	}
++
++	return false;
++}
++
++unsigned long init_jiffies;
++unsigned long cycle_beacon_count;
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0))
++static void drv_handle_beacon(struct timer_list *t)
++#else
++static void drv_handle_beacon(unsigned long data)
++#endif
++{
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0))
++	struct esp_vif *evif = from_timer(evif, t, beacon_timer);
++	struct ieee80211_vif *vif = evif->epub->vif;
++#else
++	struct ieee80211_vif *vif = (struct ieee80211_vif *) data;
++	struct esp_vif *evif = (struct esp_vif *) vif->drv_priv;
++#endif
++	struct sk_buff *beacon;
++	struct sk_buff *skb;
++	static int dbgcnt = 0;
++	bool tim_reach = false;
++
++	if (evif->epub == NULL)
++		return;
++
++	mdelay(2400 * (cycle_beacon_count % 25) % 10000 / 1000);
++
++	beacon = ieee80211_beacon_get(evif->epub->hw, vif, 0);
++
++	tim_reach = beacon_tim_alter(beacon);
++
++	if (beacon && !(dbgcnt++ % 600)) {
++		ESP_IEEE80211_DBG(ESP_DBG_TRACE, " beacon length:%d,fc:0x%x\n",
++				  beacon->len,
++				  ((struct ieee80211_mgmt *) (beacon->
++							      data))->
++				  frame_control);
++
++	}
++
++	if (beacon)
++		sip_tx_data_pkt_enqueue(evif->epub, beacon);
++
++	if (cycle_beacon_count++ == 100) {
++		init_jiffies = jiffies;
++		cycle_beacon_count -= 100;
++	}
++	mod_timer(&evif->beacon_timer,
++		  init_jiffies +
++		  msecs_to_jiffies(cycle_beacon_count *
++				   vif->bss_conf.beacon_int * 1024 /
++				   1000));
++	//FIXME:the packets must be sent at home channel
++	//send buffer mcast frames
++	if (tim_reach) {
++		skb = ieee80211_get_buffered_bc(evif->epub->hw, vif);
++		while (skb) {
++			sip_tx_data_pkt_enqueue(evif->epub, skb);
++			skb =
++			    ieee80211_get_buffered_bc(evif->epub->hw, vif);
++		}
++	}
++}
++
++static void init_beacon_timer(struct ieee80211_vif *vif)
++{
++	struct esp_vif *evif = (struct esp_vif *) vif->drv_priv;
++
++	ESP_IEEE80211_DBG(ESP_DBG_OP, " %s enter: beacon interval %x\n",
++			  __func__, evif->beacon_interval);
++
++	beacon_tim_init();
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0))
++	timer_setup(&evif->beacon_timer, drv_handle_beacon, 0);
++#else
++	init_timer(&evif->beacon_timer);	//TBD, not init here...
++	evif->beacon_timer.data = (unsigned long) vif;
++	evif->beacon_timer.function = drv_handle_beacon;
++#endif
++	cycle_beacon_count = 1;
++	init_jiffies = jiffies;
++	evif->beacon_timer.expires =
++	    init_jiffies +
++	    msecs_to_jiffies(cycle_beacon_count *
++			     vif->bss_conf.beacon_int * 1024 / 1000);
++	add_timer(&evif->beacon_timer);
++}
++
++static int esp_op_config(struct ieee80211_hw *hw, u32 changed)
++{
++	//struct ieee80211_conf *conf = &hw->conf;
++
++	struct esp_pub *epub = (struct esp_pub *) hw->priv;
++
++	ESP_IEEE80211_DBG(ESP_DBG_TRACE, "%s enter 0x%08x\n", __func__,
++			  changed);
++
++	if (changed &
++	    (IEEE80211_CONF_CHANGE_CHANNEL | IEEE80211_CONF_CHANGE_IDLE)) {
++		sip_send_config(epub, &hw->conf);
++	}
++
++	return 0;
++}
++
++static void esp_op_bss_info_changed(struct ieee80211_hw *hw,
++				    struct ieee80211_vif *vif,
++				    struct ieee80211_bss_conf *info,
++				    u64 changed)
++{
++	struct esp_pub *epub = (struct esp_pub *) hw->priv;
++	struct esp_vif *evif = (struct esp_vif *) vif->drv_priv;
++
++	// ieee80211_bss_conf(include/net/mac80211.h) is included in ieee80211_sub_if_data(net/mac80211/ieee80211_i.h) , does bssid=ieee80211_if_ap's ssid ?
++	// in 2.6.27, ieee80211_sub_if_data has ieee80211_bss_conf while in 2.6.32 ieee80211_sub_if_data don't have ieee80211_bss_conf
++	// in 2.6.27, ieee80211_bss_conf->enable_beacon don't exist, does it mean it support beacon always?
++	// ESP_IEEE80211_DBG(ESP_DBG_OP, " %s enter: vif addr %pM, changed %x, assoc %x, bssid %pM\n", __func__, vif->addr, changed, vif->cfg.assoc, info->bssid);
++	// sdata->u.sta.bssid
++
++	ESP_IEEE80211_DBG(ESP_DBG_OP,
++			  " %s enter: changed %x, assoc %x, bssid %pM\n",
++			  __func__, changed, vif->cfg.assoc, info->bssid);
++
++	if (vif->type == NL80211_IFTYPE_STATION) {
++		if ((changed & BSS_CHANGED_BSSID) ||
++		    ((changed & BSS_CHANGED_ASSOC) && (vif->cfg.assoc))) {
++			ESP_IEEE80211_DBG(ESP_DBG_TRACE,
++					  " %s STA change bssid or assoc\n",
++					  __func__);
++			evif->beacon_interval = vif->cfg.aid;
++			memcpy(epub->wl.bssid, (u8 *) info->bssid,
++			       ETH_ALEN);
++			sip_send_bss_info_update(epub, evif,
++						 (u8 *) info->bssid,
++						 vif->cfg.assoc);
++		} else if ((changed & BSS_CHANGED_ASSOC) && (!vif->cfg.assoc)) {
++			ESP_IEEE80211_DBG(ESP_DBG_TRACE,
++					  " %s STA change disassoc\n",
++					  __func__);
++			evif->beacon_interval = 0;
++			memset(epub->wl.bssid, 0, ETH_ALEN);
++			sip_send_bss_info_update(epub, evif,
++						 (u8 *) info->bssid,
++						 vif->cfg.assoc);
++		} else {
++			ESP_IEEE80211_DBG(ESP_DBG_TRACE,
++					  "%s wrong mode of STA mode\n",
++					  __func__);
++		}
++	} else if (vif->type == NL80211_IFTYPE_AP) {
++		if ((changed & BSS_CHANGED_BEACON_ENABLED) ||
++		    (changed & BSS_CHANGED_BEACON_INT)) {
++			ESP_IEEE80211_DBG(ESP_DBG_TRACE,
++					  " %s AP change enable %d, interval is %d, bssid %pM\n",
++					  __func__, info->enable_beacon,
++					  info->beacon_int, info->bssid);
++			if (info->enable_beacon && evif->ap_up != true) {
++				evif->beacon_interval = info->beacon_int;
++				init_beacon_timer(vif);
++				sip_send_bss_info_update(epub, evif,
++							 (u8 *) info->
++							 bssid, 2);
++				evif->ap_up = true;
++			} else if (!info->enable_beacon && evif->ap_up &&
++				!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)
++			    ) {
++				ESP_IEEE80211_DBG(ESP_DBG_TRACE,
++						  " %s AP disable beacon, interval is %d\n",
++						  __func__,
++						  info->beacon_int);
++				evif->beacon_interval = 0;
++				del_timer_sync(&evif->beacon_timer);
++				sip_send_bss_info_update(epub, evif,
++							 (u8 *) info->
++							 bssid, 2);
++				evif->ap_up = false;
++			}
++		}
++	} else {
++		ESP_IEEE80211_DBG(ESP_DBG_ERROR,
++				  "%s op mode unspecified\n", __func__);
++	}
++}
++
++
++static u64 esp_op_prepare_multicast(struct ieee80211_hw *hw,
++				    struct netdev_hw_addr_list *mc_list)
++{
++	ESP_IEEE80211_DBG(ESP_DBG_TRACE, "%s enter \n", __func__);
++
++	return 0;
++}
++
++static void esp_op_configure_filter(struct ieee80211_hw *hw,
++				    unsigned int changed_flags,
++				    unsigned int *total_flags,
++				    u64 multicast)
++{
++	struct esp_pub *epub = (struct esp_pub *) hw->priv;
++
++	ESP_IEEE80211_DBG(ESP_DBG_TRACE, "%s enter \n", __func__);
++
++	epub->rx_filter = 0;
++
++	if (*total_flags & FIF_ALLMULTI)
++		epub->rx_filter |= FIF_ALLMULTI;
++
++	*total_flags = epub->rx_filter;
++}
++
++static int esp_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
++			  struct ieee80211_vif *vif,
++			  struct ieee80211_sta *sta,
++			  struct ieee80211_key_conf *key)
++{
++	u8 i;
++	int ret;
++	struct esp_pub *epub = (struct esp_pub *) hw->priv;
++	struct esp_vif *evif = (struct esp_vif *) vif->drv_priv;
++	u8 ifidx = evif->index;
++	u8 *peer_addr, isvalid;
++
++	ESP_IEEE80211_DBG(ESP_DBG_OP,
++			  "%s enter, flags = %x keyindx = %x cmd = %x mac = %pM cipher = %x\n",
++			  __func__, key->flags, key->keyidx, cmd,
++			  vif->addr, key->cipher);
++
++	key->flags = key->flags | IEEE80211_KEY_FLAG_GENERATE_IV;
++
++	if (sta) {
++		if (memcmp(sta->addr, epub->wl.bssid, ETH_ALEN))
++			peer_addr = sta->addr;
++		else
++			peer_addr = epub->wl.bssid;
++	} else {
++		peer_addr = epub->wl.bssid;
++	}
++	isvalid = (cmd == SET_KEY) ? 1 : 0;
++
++	if ((key->flags & IEEE80211_KEY_FLAG_PAIRWISE)
++	    || (key->cipher == WLAN_CIPHER_SUITE_WEP40
++		|| key->cipher == WLAN_CIPHER_SUITE_WEP104)) {
++		if (isvalid) {
++			for (i = 0; i < 19; i++) {
++				if (epub->hi_map[i].flag == 0) {
++					epub->hi_map[i].flag = 1;
++					key->hw_key_idx = i + 6;
++					memcpy(epub->hi_map[i].mac,
++					       peer_addr, ETH_ALEN);
++					break;
++				}
++			}
++		} else {
++			u8 index = key->hw_key_idx - 6;
++			epub->hi_map[index].flag = 0;
++			memset(epub->hi_map[index].mac, 0, ETH_ALEN);
++		}
++	} else {
++		if (isvalid) {
++			for (i = 0; i < 2; i++)
++				if (epub->low_map[ifidx][i].flag == 0) {
++					epub->low_map[ifidx][i].flag = 1;
++					key->hw_key_idx =
++					    i + ifidx * 2 + 2;
++					memcpy(epub->low_map[ifidx][i].mac,
++					       peer_addr, ETH_ALEN);
++					break;
++				}
++		} else {
++			u8 index = key->hw_key_idx - 2 - ifidx * 2;
++			epub->low_map[ifidx][index].flag = 0;
++			memset(epub->low_map[ifidx][index].mac, 0,
++			       ETH_ALEN);
++		}
++		//key->hw_key_idx = key->keyidx + ifidx * 2 + 1;
++	}
++
++	if (key->hw_key_idx >= 6) {
++		/*send sub_scan task to target */
++		//epub->wl.ptk = (cmd==SET_KEY) ? key : NULL;
++		if (isvalid)
++			atomic_inc(&epub->wl.ptk_cnt);
++		else
++			atomic_dec(&epub->wl.ptk_cnt);
++		if (key->cipher == WLAN_CIPHER_SUITE_WEP40
++		    || key->cipher == WLAN_CIPHER_SUITE_WEP104) {
++			if (isvalid)
++				atomic_inc(&epub->wl.gtk_cnt);
++			else
++				atomic_dec(&epub->wl.gtk_cnt);
++		}
++	} else {
++		/*send sub_scan task to target */
++		if (isvalid)
++			atomic_inc(&epub->wl.gtk_cnt);
++		else
++			atomic_dec(&epub->wl.gtk_cnt);
++
++		if ((key->cipher == WLAN_CIPHER_SUITE_WEP40
++		     || key->cipher == WLAN_CIPHER_SUITE_WEP104)) {
++			if (isvalid)
++				atomic_inc(&epub->wl.ptk_cnt);
++			else
++				atomic_dec(&epub->wl.ptk_cnt);
++			//epub->wl.ptk = (cmd==SET_KEY) ? key : NULL;
++		}
++	}
++
++	ret = sip_send_setkey(epub, ifidx, peer_addr, key, isvalid);
++
++	if ((key->cipher == WLAN_CIPHER_SUITE_TKIP
++	     || key->cipher == WLAN_CIPHER_SUITE_TKIP)) {
++		if (ret == 0)
++			atomic_set(&epub->wl.tkip_key_set, 1);
++	}
++
++	ESP_IEEE80211_DBG(ESP_DBG_OP, "%s exit\n", __func__);
++	return ret;
++}
++
++static void esp_op_update_tkip_key(struct ieee80211_hw *hw,
++				   struct ieee80211_vif *vif,
++				   struct ieee80211_key_conf *conf,
++				   struct ieee80211_sta *sta,
++				   u32 iv32, u16 * phase1key)
++{
++	ESP_IEEE80211_DBG(ESP_DBG_TRACE, "%s enter \n", __func__);
++
++}
++
++void hw_scan_done(struct esp_pub *epub, bool aborted)
++{
++	cancel_delayed_work_sync(&epub->scan_timeout_work);
++
++	ESSERT(epub->wl.scan_req != NULL);
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 8, 0))
++	{
++		struct cfg80211_scan_info info = {
++			.aborted = aborted,
++		};
++
++		ieee80211_scan_completed(epub->hw, &info);
++	}
++#else
++	ieee80211_scan_completed(epub->hw, aborted);
++#endif
++	if (test_and_clear_bit(ESP_WL_FLAG_STOP_TXQ, &epub->wl.flags)) {
++		sip_trigger_txq_process(epub->sip);
++	}
++}
++
++static void hw_scan_timeout_report(struct work_struct *work)
++{
++	struct esp_pub *epub =
++	    container_of(work, struct esp_pub, scan_timeout_work.work);
++	bool aborted;
++
++	ESP_IEEE80211_DBG(ESP_DBG_TRACE, "eagle hw scan done\n");
++
++	if (test_and_clear_bit(ESP_WL_FLAG_STOP_TXQ, &epub->wl.flags)) {
++		sip_trigger_txq_process(epub->sip);
++	}
++	/*check if normally complete or aborted like timeout/hw error */
++	aborted = (epub->wl.scan_req) ? true : false;
++
++	if (aborted == true) {
++		epub->wl.scan_req = NULL;
++	}
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 8, 0))
++	{
++		struct cfg80211_scan_info info = {
++			.aborted = aborted,
++		};
++
++		ieee80211_scan_completed(epub->hw, &info);
++	}
++#else
++	ieee80211_scan_completed(epub->hw, aborted);
++#endif
++}
++
++static int esp_op_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
++{
++	ESP_IEEE80211_DBG(ESP_DBG_TRACE, "%s enter \n", __func__);
++
++	return 0;
++}
++
++static int esp_node_attach(struct ieee80211_hw *hw, u8 ifidx,
++			   struct ieee80211_sta *sta)
++{
++	struct esp_pub *epub = (struct esp_pub *) hw->priv;
++	struct esp_node *node;
++	u8 tidno;
++	struct esp_tx_tid *tid;
++	int i;
++
++	spin_lock_bh(&epub->tx_ampdu_lock);
++
++	if (hweight32(epub->enodes_maps[ifidx]) < ESP_PUB_MAX_STA
++	    && (i = ffz(epub->enodes_map)) < ESP_PUB_MAX_STA + 1) {
++		epub->enodes_map |= (1 << i);
++		epub->enodes_maps[ifidx] |= (1 << i);
++		node = (struct esp_node *) sta->drv_priv;
++		epub->enodes[i] = node;
++		node->sta = sta;
++		node->ifidx = ifidx;
++		node->index = i;
++
++		for (tidno = 0, tid = &node->tid[tidno];
++		     tidno < WME_NUM_TID; tidno++) {
++			tid->ssn = 0;
++			tid->cnt = 0;
++			tid->state = ESP_TID_STATE_INIT;
++		}
++
++
++	} else {
++		i = -1;
++	}
++
++	spin_unlock_bh(&epub->tx_ampdu_lock);
++	return i;
++}
++
++static int esp_node_detach(struct ieee80211_hw *hw, u8 ifidx,
++			   struct ieee80211_sta *sta)
++{
++	struct esp_pub *epub = (struct esp_pub *) hw->priv;
++	u32 map;
++	int i;
++	struct esp_node *node = NULL;
++
++	spin_lock_bh(&epub->tx_ampdu_lock);
++	map = epub->enodes_maps[ifidx];
++	while (map != 0) {
++		i = ffs(map) - 1;
++		if (epub->enodes[i]->sta == sta) {
++			epub->enodes[i]->sta = NULL;
++			node = epub->enodes[i];
++			epub->enodes[i] = NULL;
++			epub->enodes_map &= ~(1 << i);
++			epub->enodes_maps[ifidx] &= ~(1 << i);
++
++			spin_unlock_bh(&epub->tx_ampdu_lock);
++			return i;
++		}
++		map &= ~(1 << i);
++	}
++
++	spin_unlock_bh(&epub->tx_ampdu_lock);
++	return -1;
++}
++
++struct esp_node *esp_get_node_by_addr(struct esp_pub *epub,
++				      const u8 * addr)
++{
++	int i;
++	u32 map;
++	struct esp_node *node = NULL;
++	if (addr == NULL)
++		return NULL;
++	spin_lock_bh(&epub->tx_ampdu_lock);
++	map = epub->enodes_map;
++	while (map != 0) {
++		i = ffs(map) - 1;
++		if (i < 0) {
++			spin_unlock_bh(&epub->tx_ampdu_lock);
++			return NULL;
++		}
++		map &= ~(1 << i);
++		if (memcmp(epub->enodes[i]->sta->addr, addr, ETH_ALEN) ==
++		    0) {
++			node = epub->enodes[i];
++			break;
++		}
++	}
++
++	spin_unlock_bh(&epub->tx_ampdu_lock);
++	return node;
++}
++
++struct esp_node *esp_get_node_by_index(struct esp_pub *epub, u8 index)
++{
++	u32 map;
++	struct esp_node *node = NULL;
++
++	if (epub == NULL)
++		return NULL;
++
++	spin_lock_bh(&epub->tx_ampdu_lock);
++	map = epub->enodes_map;
++	if (map & BIT(index)) {
++		node = epub->enodes[index];
++	} else {
++		spin_unlock_bh(&epub->tx_ampdu_lock);
++		return NULL;
++	}
++
++	spin_unlock_bh(&epub->tx_ampdu_lock);
++	return node;
++}
++
++int esp_get_empty_rxampdu(struct esp_pub *epub, const u8 * addr, u8 tid)
++{
++	int index = -1;
++	if (addr == NULL)
++		return index;
++	spin_lock_bh(&epub->rx_ampdu_lock);
++	if ((index = ffz(epub->rxampdu_map)) < ESP_PUB_MAX_RXAMPDU) {
++		epub->rxampdu_map |= BIT(index);
++		epub->rxampdu_node[index] =
++		    esp_get_node_by_addr(epub, addr);
++		epub->rxampdu_tid[index] = tid;
++	} else {
++		index = -1;
++	}
++	spin_unlock_bh(&epub->rx_ampdu_lock);
++	return index;
++}
++
++int esp_get_exist_rxampdu(struct esp_pub *epub, const u8 * addr, u8 tid)
++{
++	u8 map;
++	int index = -1;
++	int i;
++	if (addr == NULL)
++		return index;
++	spin_lock_bh(&epub->rx_ampdu_lock);
++	map = epub->rxampdu_map;
++	while (map != 0) {
++		i = ffs(map) - 1;
++		if (i < 0) {
++			spin_unlock_bh(&epub->rx_ampdu_lock);
++			return index;
++		}
++		map &= ~BIT(i);
++		if (epub->rxampdu_tid[i] == tid &&
++		    memcmp(epub->rxampdu_node[i]->sta->addr, addr,
++			   ETH_ALEN) == 0) {
++			index = i;
++			break;
++		}
++	}
++
++	epub->rxampdu_map &= ~BIT(index);
++	spin_unlock_bh(&epub->rx_ampdu_lock);
++	return index;
++
++}
++
++static int esp_op_sta_add(struct ieee80211_hw *hw,
++			  struct ieee80211_vif *vif,
++			  struct ieee80211_sta *sta)
++{
++	struct esp_pub *epub = (struct esp_pub *) hw->priv;
++	struct esp_vif *evif = (struct esp_vif *) vif->drv_priv;
++	int index;
++	ESP_IEEE80211_DBG(ESP_DBG_OP,
++			  "%s enter, vif addr %pM, sta addr %pM\n",
++			  __func__, vif->addr, sta->addr);
++	index = esp_node_attach(hw, evif->index, sta);
++
++	if (index < 0)
++		return -1;
++	sip_send_set_sta(epub, evif->index, 1, sta, vif, (u8) index);
++	return 0;
++}
++
++static void esp_op_sta_remove(struct ieee80211_hw *hw,
++			     struct ieee80211_vif *vif,
++			     struct ieee80211_sta *sta)
++{
++	struct esp_pub *epub = (struct esp_pub *) hw->priv;
++	struct esp_vif *evif = (struct esp_vif *) vif->drv_priv;
++	int index;
++
++	ESP_IEEE80211_DBG(ESP_DBG_OP,
++			  "%s enter, vif addr %pM, sta addr %pM\n",
++			  __func__, vif->addr, sta->addr);
++
++	//remove a connect in target
++	index = esp_node_detach(hw, evif->index, sta);
++	sip_send_set_sta(epub, evif->index, 0, sta, vif, (u8) index);
++
++	//return 0;
++}
++
++
++static void esp_op_sta_notify(struct ieee80211_hw *hw,
++			      struct ieee80211_vif *vif,
++			      enum sta_notify_cmd cmd,
++			      struct ieee80211_sta *sta)
++{
++
++	ESP_IEEE80211_DBG(ESP_DBG_TRACE, "%s enter \n", __func__);
++
++	switch (cmd) {
++	case STA_NOTIFY_SLEEP:
++		break;
++
++	case STA_NOTIFY_AWAKE:
++		break;
++
++	default:
++		break;
++	}
++}
++
++
++static int esp_op_conf_tx(struct ieee80211_hw *hw,
++			  struct ieee80211_vif *vif,
++			  u32 link_id, u16 queue,
++			  const struct ieee80211_tx_queue_params *params)
++{
++	struct esp_pub *epub = (struct esp_pub *) hw->priv;
++	ESP_IEEE80211_DBG(ESP_DBG_TRACE, "%s enter \n", __func__);
++	return sip_send_wmm_params(epub, queue, params);
++}
++
++static u64 esp_op_get_tsf(struct ieee80211_hw *hw,
++			  struct ieee80211_vif *vif)
++{
++	ESP_IEEE80211_DBG(ESP_DBG_TRACE, "%s enter \n", __func__);
++
++	return 0;
++}
++
++static void esp_op_set_tsf(struct ieee80211_hw *hw,
++			   struct ieee80211_vif *vif, u64 tsf)
++{
++	ESP_IEEE80211_DBG(ESP_DBG_TRACE, "%s enter \n", __func__);
++}
++
++static void esp_op_reset_tsf(struct ieee80211_hw *hw,
++			     struct ieee80211_vif *vif)
++{
++	ESP_IEEE80211_DBG(ESP_DBG_TRACE, "%s enter \n", __func__);
++
++}
++
++static void esp_op_rfkill_poll(struct ieee80211_hw *hw)
++{
++	struct esp_pub *epub = (struct esp_pub *) hw->priv;
++
++	ESP_IEEE80211_DBG(ESP_DBG_TRACE, "%s enter \n", __func__);
++
++	wiphy_rfkill_set_hw_state(hw->wiphy,
++				  test_bit(ESP_WL_FLAG_RFKILL,
++					   &epub->wl.
++					   flags) ? true : false);
++}
++
++#ifdef HW_SCAN
++static int esp_op_hw_scan(struct ieee80211_hw *hw,
++			  struct ieee80211_vif *vif,
++			  struct cfg80211_scan_request *req)
++{
++	struct esp_pub *epub = (struct esp_pub *) hw->priv;
++	int i, ret;
++	bool scan_often = true;
++
++	ESP_IEEE80211_DBG(ESP_DBG_OP, "%s\n", __func__);
++
++	ESP_IEEE80211_DBG(ESP_DBG_TRACE, "scan, %d\n", req->n_ssids);
++	ESP_IEEE80211_DBG(ESP_DBG_TRACE, "scan, len 1:%d,ssid 1:%s\n",
++			  req->ssids->ssid_len,
++			  req->ssids->ssid_len ==
++			  0 ? "" : (char *) req->ssids->ssid);
++	if (req->n_ssids > 1)
++		ESP_IEEE80211_DBG(ESP_DBG_TRACE,
++				  "scan, len 2:%d,ssid 2:%s\n",
++				  (req->ssids + 1)->ssid_len,
++				  (req->ssids + 1)->ssid_len ==
++				  0 ? "" : (char *) (req->ssids +
++						     1)->ssid);
++
++	/*scan_request is keep allocate untill scan_done,record it
++	   to split request into multi sdio_cmd */
++	if (atomic_read(&epub->wl.off)) {
++		esp_dbg(ESP_DBG_ERROR, "%s scan but wl off \n", __func__);
++		return -EPERM;
++	}
++
++	if (req->n_ssids > 1) {
++		struct cfg80211_ssid *ssid2 = req->ssids + 1;
++		if ((req->ssids->ssid_len > 0 && ssid2->ssid_len > 0)
++		    || req->n_ssids > 2) {
++			ESP_IEEE80211_DBG(ESP_DBG_ERROR,
++					  "scan ssid num: %d, ssid1:%s, ssid2:%s,not support\n",
++					  req->n_ssids,
++					  req->ssids->ssid_len ==
++					  0 ? "" : (char *) req->ssids->
++					  ssid,
++					  ssid2->ssid_len ==
++					  0 ? "" : (char *) ssid2->ssid);
++			return -EINVAL;
++		}
++	}
++
++	epub->wl.scan_req = req;
++
++	for (i = 0; i < req->n_channels; i++)
++		ESP_IEEE80211_DBG(ESP_DBG_TRACE, "eagle hw_scan freq %d\n",
++				  req->channels[i]->center_freq);
++#if 0
++	for (i = 0; i < req->n_ssids; i++) {
++		if (req->ssids->ssid_len > 0) {
++			req->ssids->ssid[req->ssids->ssid_len] = '\0';
++			ESP_IEEE80211_DBG(ESP_DBG_TRACE,
++					  "scan_ssid %d:%s\n", i,
++					  req->ssids->ssid);
++		}
++	}
++#endif
++
++	/*in connect state, suspend tx data */
++	if (epub->sip->support_bgscan &&
++	    test_bit(ESP_WL_FLAG_CONNECT, &epub->wl.flags) &&
++	    req->n_channels > 0) {
++
++		scan_often = epub->scan_permit_valid
++		    && time_before(jiffies, epub->scan_permit);
++		epub->scan_permit_valid = true;
++
++		if (!scan_often) {
++/*                        epub->scan_permit = jiffies + msecs_to_jiffies(900);
++                        set_bit(ESP_WL_FLAG_STOP_TXQ, &epub->wl.flags);
++                        if (atomic_read(&epub->txq_stopped) == false) {
++                                atomic_set(&epub->txq_stopped, true);
++                                ieee80211_stop_queues(hw);
++                        }
++*/
++		} else {
++			ESP_IEEE80211_DBG(ESP_DBG_LOG, "scan too often\n");
++			return -EACCES;
++		}
++	} else {
++		scan_often = false;
++	}
++
++	/*send sub_scan task to target */
++	ret = sip_send_scan(epub);
++
++	if (ret) {
++		ESP_IEEE80211_DBG(ESP_DBG_ERROR,
++				  "fail to send scan_cmd\n");
++		return ret;
++	} else {
++		if (!scan_often) {
++			epub->scan_permit =
++			    jiffies + msecs_to_jiffies(900);
++			set_bit(ESP_WL_FLAG_STOP_TXQ, &epub->wl.flags);
++			if (atomic_read(&epub->txq_stopped) == false) {
++				atomic_set(&epub->txq_stopped, true);
++				ieee80211_stop_queues(hw);
++			}
++			/*force scan complete in case target fail to report in time */
++			ieee80211_queue_delayed_work(hw,
++						     &epub->
++						     scan_timeout_work,
++						     req->n_channels * HZ /
++						     4);
++		}
++	}
++
++	return 0;
++}
++
++static int esp_op_remain_on_channel(struct ieee80211_hw *hw,
++				    struct ieee80211_channel *chan,
++				    enum nl80211_channel_type channel_type,
++				    int duration)
++{
++	struct esp_pub *epub = (struct esp_pub *) hw->priv;
++
++	ESP_IEEE80211_DBG(ESP_DBG_OP,
++			  "%s enter, center_freq = %d duration = %d\n",
++			  __func__, chan->center_freq, duration);
++	sip_send_roc(epub, chan->center_freq, duration);
++	return 0;
++}
++
++static int esp_op_cancel_remain_on_channel(struct ieee80211_hw *hw)
++{
++	struct esp_pub *epub = (struct esp_pub *) hw->priv;
++
++	ESP_IEEE80211_DBG(ESP_DBG_OP, "%s enter \n", __func__);
++	epub->roc_flags = 0;	// to disable roc state
++	sip_send_roc(epub, 0, 0);
++	return 0;
++}
++#endif
++
++void esp_rocdone_process(struct ieee80211_hw *hw,
++			 struct sip_evt_roc *report)
++{
++	struct esp_pub *epub = (struct esp_pub *) hw->priv;
++
++	ESP_IEEE80211_DBG(ESP_DBG_OP, "%s enter, state = %d is_ok = %d\n",
++			  __func__, report->state, report->is_ok);
++
++	//roc process begin
++	if ((report->state == 1) && (report->is_ok == 1)) {
++		epub->roc_flags = 1;	//flags in roc state, to fix channel, not change
++		ieee80211_ready_on_channel(hw);
++	} else if ((report->state == 0) && (report->is_ok == 1))	//roc process timeout
++	{
++		epub->roc_flags = 0;	// to disable roc state
++		ieee80211_remain_on_channel_expired(hw);
++	}
++}
++
++static int esp_op_set_bitrate_mask(struct ieee80211_hw *hw,
++				   struct ieee80211_vif *vif,
++				   const struct cfg80211_bitrate_mask
++				   *mask)
++{
++	ESP_IEEE80211_DBG(ESP_DBG_OP, "%s enter \n", __func__);
++	ESP_IEEE80211_DBG(ESP_DBG_OP, "%s vif->macaddr[%pM], mask[%d]\n",
++			  __func__, vif->addr, mask->control[0].legacy);
++
++	return 0;
++}
++
++void esp_op_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
++		  u32 queues, bool drop)
++{
++
++	ESP_IEEE80211_DBG(ESP_DBG_OP, "%s enter \n", __func__);
++	do {
++
++		struct esp_pub *epub = (struct esp_pub *) hw->priv;
++		unsigned long time = jiffies + msecs_to_jiffies(15);
++		while (atomic_read(&epub->sip->tx_data_pkt_queued)) {
++			if (!time_before(jiffies, time)) {
++				break;
++			}
++			if (sif_get_ate_config() == 0) {
++				ieee80211_queue_work(epub->hw,
++						     &epub->tx_work);
++			} else {
++				queue_work(epub->esp_wkq, &epub->tx_work);
++			}
++			//sip_txq_process(epub);
++		}
++		mdelay(10);
++
++	} while (0);
++}
++
++static int esp_op_ampdu_action(struct ieee80211_hw *hw,
++			       struct ieee80211_vif *vif,
++			       struct ieee80211_ampdu_params *params)
++{
++	int ret = -EOPNOTSUPP;
++	enum ieee80211_ampdu_mlme_action action = params->action;
++	struct ieee80211_sta *sta = params->sta;
++	u16 tid = params->tid;
++	u16 *ssn = &params->ssn;
++	u8 buf_size = params->buf_size;
++	struct esp_pub *epub = (struct esp_pub *) hw->priv;
++	struct esp_node *node = (struct esp_node *) sta->drv_priv;
++	struct esp_tx_tid *tid_info = &node->tid[tid];
++
++	ESP_IEEE80211_DBG(ESP_DBG_OP, "%s enter \n", __func__);
++	switch (action) {
++	case IEEE80211_AMPDU_TX_START:
++		if (mod_support_no_txampdu() ||
++		    cfg80211_get_chandef_type(&epub->hw->conf.chandef) ==
++		    NL80211_CHAN_NO_HT || !sta->deflink.ht_cap.ht_supported)
++			return ret;
++
++		//if (vif->p2p || vif->type != NL80211_IFTYPE_STATION)
++		//      return ret;
++
++		ESP_IEEE80211_DBG(ESP_DBG_TRACE,
++				  "%s TX START, addr:%pM,tid:%u,state:%d\n",
++				  __func__, sta->addr, tid,
++				  tid_info->state);
++		spin_lock_bh(&epub->tx_ampdu_lock);
++		ESSERT(tid_info->state == ESP_TID_STATE_TRIGGER);
++		*ssn = tid_info->ssn;
++		tid_info->state = ESP_TID_STATE_PROGRESS;
++
++		ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
++		spin_unlock_bh(&epub->tx_ampdu_lock);
++		ret = 0;
++		break;
++	case IEEE80211_AMPDU_TX_STOP_CONT:
++		ESP_IEEE80211_DBG(ESP_DBG_TRACE,
++				  "%s TX STOP, addr:%pM,tid:%u,state:%d\n",
++				  __func__, sta->addr, tid,
++				  tid_info->state);
++		spin_lock_bh(&epub->tx_ampdu_lock);
++		if (tid_info->state == ESP_TID_STATE_WAIT_STOP)
++			tid_info->state = ESP_TID_STATE_STOP;
++		else
++			tid_info->state = ESP_TID_STATE_INIT;
++		ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
++		spin_unlock_bh(&epub->tx_ampdu_lock);
++		ret =
++		    sip_send_ampdu_action(epub, SIP_AMPDU_TX_STOP,
++					  sta->addr, tid, node->ifidx, 0);
++		break;
++	case IEEE80211_AMPDU_TX_STOP_FLUSH:
++	case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
++		if (tid_info->state == ESP_TID_STATE_WAIT_STOP)
++			tid_info->state = ESP_TID_STATE_STOP;
++		else
++			tid_info->state = ESP_TID_STATE_INIT;
++		ret =
++		    sip_send_ampdu_action(epub, SIP_AMPDU_TX_STOP,
++					  sta->addr, tid, node->ifidx, 0);
++		break;
++	case IEEE80211_AMPDU_TX_OPERATIONAL:
++		ESP_IEEE80211_DBG(ESP_DBG_TRACE,
++				  "%s TX OPERATION, addr:%pM,tid:%u,state:%d\n",
++				  __func__, sta->addr, tid,
++				  tid_info->state);
++		spin_lock_bh(&epub->tx_ampdu_lock);
++
++		if (tid_info->state != ESP_TID_STATE_PROGRESS) {
++			if (tid_info->state == ESP_TID_STATE_INIT) {
++				printk(KERN_ERR "%s WIFI RESET, IGNORE\n",
++				       __func__);
++				spin_unlock_bh(&epub->tx_ampdu_lock);
++				return -ENETRESET;
++			} else {
++				ESSERT(0);
++			}
++		}
++
++		tid_info->state = ESP_TID_STATE_OPERATIONAL;
++		spin_unlock_bh(&epub->tx_ampdu_lock);
++		ret =
++		    sip_send_ampdu_action(epub, SIP_AMPDU_TX_OPERATIONAL,
++					  sta->addr, tid, node->ifidx,
++					  buf_size);
++		break;
++	case IEEE80211_AMPDU_RX_START:
++		if (mod_support_no_rxampdu() ||
++		    cfg80211_get_chandef_type(&epub->hw->conf.chandef) ==
++		    NL80211_CHAN_NO_HT || !sta->deflink.ht_cap.ht_supported)
++			return ret;
++
++		if ((vif->p2p && false)
++		    || (vif->type != NL80211_IFTYPE_STATION && false)
++		    )
++			return ret;
++		ESP_IEEE80211_DBG(ESP_DBG_TRACE,
++				  "%s RX START %pM tid %u %u\n", __func__,
++				  sta->addr, tid, *ssn);
++		ret =
++		    sip_send_ampdu_action(epub, SIP_AMPDU_RX_START,
++					  sta->addr, tid, *ssn, 64);
++		break;
++	case IEEE80211_AMPDU_RX_STOP:
++		ESP_IEEE80211_DBG(ESP_DBG_TRACE, "%s RX STOP %pM tid %u\n",
++				  __func__, sta->addr, tid);
++		ret =
++		    sip_send_ampdu_action(epub, SIP_AMPDU_RX_STOP,
++					  sta->addr, tid, 0, 0);
++		break;
++	default:
++		break;
++	}
++	return ret;
++}
++
++static void esp_tx_work(struct work_struct *work)
++{
++	struct esp_pub *epub = container_of(work, struct esp_pub, tx_work);
++
++	mutex_lock(&epub->tx_mtx);
++	sip_txq_process(epub);
++	mutex_unlock(&epub->tx_mtx);
++}
++
++static const struct ieee80211_ops esp_mac80211_ops = {
++	.tx = esp_op_tx,
++	.start = esp_op_start,
++	.stop = esp_op_stop,
++#ifdef CONFIG_PM
++	.suspend = esp_op_suspend,
++	.resume = esp_op_resume,
++#endif
++	.add_interface = esp_op_add_interface,
++	.remove_interface = esp_op_remove_interface,
++	.config = esp_op_config,
++
++	.bss_info_changed = esp_op_bss_info_changed,
++	.prepare_multicast = esp_op_prepare_multicast,
++	.configure_filter = esp_op_configure_filter,
++	.set_key = esp_op_set_key,
++	.update_tkip_key = esp_op_update_tkip_key,
++	//.sched_scan_start = esp_op_sched_scan_start,
++	//.sched_scan_stop = esp_op_sched_scan_stop,
++	.set_rts_threshold = esp_op_set_rts_threshold,
++	.sta_notify = esp_op_sta_notify,
++	.conf_tx = esp_op_conf_tx,
++	.change_interface = esp_op_change_interface,
++	.get_tsf = esp_op_get_tsf,
++	.set_tsf = esp_op_set_tsf,
++	.reset_tsf = esp_op_reset_tsf,
++	.rfkill_poll = esp_op_rfkill_poll,
++#ifdef HW_SCAN
++	.hw_scan = esp_op_hw_scan,
++	.remain_on_channel = esp_op_remain_on_channel,
++	.cancel_remain_on_channel = esp_op_cancel_remain_on_channel,
++#endif
++	.ampdu_action = esp_op_ampdu_action,
++	//.get_survey = esp_op_get_survey,
++	.sta_add = esp_op_sta_add,
++	.sta_remove = esp_op_sta_remove,
++#ifdef CONFIG_NL80211_TESTMODE
++	//CFG80211_TESTMODE_CMD(esp_op_tm_cmd)
++#endif
++	.set_bitrate_mask = esp_op_set_bitrate_mask,
++	.flush = esp_op_flush,
++	.wake_tx_queue = ieee80211_handle_wake_tx_queue,
++};
++
++struct esp_pub *esp_pub_alloc_mac80211(struct device *dev)
++{
++	struct ieee80211_hw *hw;
++	struct esp_pub *epub;
++	int ret = 0;
++
++	hw = ieee80211_alloc_hw(sizeof(struct esp_pub), &esp_mac80211_ops);
++
++	if (hw == NULL) {
++		esp_dbg(ESP_DBG_ERROR, "ieee80211 can't alloc hw!\n");
++		ret = -ENOMEM;
++		return ERR_PTR(ret);
++	}
++	hw->wiphy->flags |= WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL;
++
++	epub = hw->priv;
++	memset(epub, 0, sizeof(*epub));
++	epub->hw = hw;
++	SET_IEEE80211_DEV(hw, dev);
++	epub->dev = dev;
++
++	skb_queue_head_init(&epub->txq);
++	skb_queue_head_init(&epub->txdoneq);
++	skb_queue_head_init(&epub->rxq);
++
++	spin_lock_init(&epub->tx_ampdu_lock);
++	spin_lock_init(&epub->rx_ampdu_lock);
++	spin_lock_init(&epub->tx_lock);
++	mutex_init(&epub->tx_mtx);
++	spin_lock_init(&epub->rx_lock);
++
++	INIT_WORK(&epub->tx_work, esp_tx_work);
++
++	//epub->esp_wkq = create_freezable_workqueue("esp_wkq");
++	epub->esp_wkq = create_singlethread_workqueue("esp_wkq");
++
++	if (epub->esp_wkq == NULL) {
++		ret = -ENOMEM;
++		return ERR_PTR(ret);
++	}
++	epub->scan_permit_valid = false;
++	INIT_DELAYED_WORK(&epub->scan_timeout_work,
++			  hw_scan_timeout_report);
++
++	return epub;
++}
++
++
++int esp_pub_dealloc_mac80211(struct esp_pub *epub)
++{
++	set_bit(ESP_WL_FLAG_RFKILL, &epub->wl.flags);
++
++	destroy_workqueue(epub->esp_wkq);
++	mutex_destroy(&epub->tx_mtx);
++
++#ifdef ESP_NO_MAC80211
++	free_netdev(epub->net_dev);
++	wiphy_free(epub->wdev->wiphy);
++	kfree(epub->wdev);
++#else
++	if (epub->hw) {
++		ieee80211_free_hw(epub->hw);
++	}
++#endif
++
++	return 0;
++}
++
++#if 0
++static int esp_reg_notifier(struct wiphy *wiphy,
++			    struct regulatory_request *request)
++{
++	struct ieee80211_supported_band *sband;
++	struct ieee80211_channel *ch;
++	int i;
++
++	ESP_IEEE80211_DBG(ESP_DBG_TRACE, "%s enter %d\n", __func__,
++			  request->initiator);
++
++	//TBD
++}
++#endif
++
++/* 2G band channels */
++static struct ieee80211_channel esp_channels_2ghz[] = {
++	{.hw_value = 1,.center_freq = 2412,.max_power = 25},
++	{.hw_value = 2,.center_freq = 2417,.max_power = 25},
++	{.hw_value = 3,.center_freq = 2422,.max_power = 25},
++	{.hw_value = 4,.center_freq = 2427,.max_power = 25},
++	{.hw_value = 5,.center_freq = 2432,.max_power = 25},
++	{.hw_value = 6,.center_freq = 2437,.max_power = 25},
++	{.hw_value = 7,.center_freq = 2442,.max_power = 25},
++	{.hw_value = 8,.center_freq = 2447,.max_power = 25},
++	{.hw_value = 9,.center_freq = 2452,.max_power = 25},
++	{.hw_value = 10,.center_freq = 2457,.max_power = 25},
++	{.hw_value = 11,.center_freq = 2462,.max_power = 25},
++	{.hw_value = 12,.center_freq = 2467,.max_power = 25},
++	{.hw_value = 13,.center_freq = 2472,.max_power = 25},
++	//{ .hw_value = 14, .center_freq = 2484, .max_power = 25 },
++};
++
++/* 11G rate */
++static struct ieee80211_rate esp_rates_2ghz[] = {
++	{
++	 .bitrate = 10,
++	 .hw_value = CONF_HW_BIT_RATE_1MBPS,
++	 .hw_value_short = CONF_HW_BIT_RATE_1MBPS,
++	 },
++	{
++	 .bitrate = 20,
++	 .hw_value = CONF_HW_BIT_RATE_2MBPS,
++	 .hw_value_short = CONF_HW_BIT_RATE_2MBPS,
++	 .flags = IEEE80211_RATE_SHORT_PREAMBLE},
++	{
++	 .bitrate = 55,
++	 .hw_value = CONF_HW_BIT_RATE_5_5MBPS,
++	 .hw_value_short = CONF_HW_BIT_RATE_5_5MBPS,
++	 .flags = IEEE80211_RATE_SHORT_PREAMBLE},
++	{
++	 .bitrate = 110,
++	 .hw_value = CONF_HW_BIT_RATE_11MBPS,
++	 .hw_value_short = CONF_HW_BIT_RATE_11MBPS,
++	 .flags = IEEE80211_RATE_SHORT_PREAMBLE},
++	{
++	 .bitrate = 60,
++	 .hw_value = CONF_HW_BIT_RATE_6MBPS,
++	 .hw_value_short = CONF_HW_BIT_RATE_6MBPS,
++	 },
++	{
++	 .bitrate = 90,
++	 .hw_value = CONF_HW_BIT_RATE_9MBPS,
++	 .hw_value_short = CONF_HW_BIT_RATE_9MBPS,
++	 },
++	{
++	 .bitrate = 120,
++	 .hw_value = CONF_HW_BIT_RATE_12MBPS,
++	 .hw_value_short = CONF_HW_BIT_RATE_12MBPS,
++	 },
++	{
++	 .bitrate = 180,
++	 .hw_value = CONF_HW_BIT_RATE_18MBPS,
++	 .hw_value_short = CONF_HW_BIT_RATE_18MBPS,
++	 },
++	{
++	 .bitrate = 240,
++	 .hw_value = CONF_HW_BIT_RATE_24MBPS,
++	 .hw_value_short = CONF_HW_BIT_RATE_24MBPS,
++	 },
++	{
++	 .bitrate = 360,
++	 .hw_value = CONF_HW_BIT_RATE_36MBPS,
++	 .hw_value_short = CONF_HW_BIT_RATE_36MBPS,
++	 },
++	{
++	 .bitrate = 480,
++	 .hw_value = CONF_HW_BIT_RATE_48MBPS,
++	 .hw_value_short = CONF_HW_BIT_RATE_48MBPS,
++	 },
++	{
++	 .bitrate = 540,
++	 .hw_value = CONF_HW_BIT_RATE_54MBPS,
++	 .hw_value_short = CONF_HW_BIT_RATE_54MBPS,
++	 },
++};
++
++static void esp_pub_init_mac80211(struct esp_pub *epub)
++{
++	struct ieee80211_hw *hw = epub->hw;
++
++	static const u32 cipher_suites[] = {
++		WLAN_CIPHER_SUITE_WEP40,
++		WLAN_CIPHER_SUITE_WEP104,
++		WLAN_CIPHER_SUITE_TKIP,
++		WLAN_CIPHER_SUITE_CCMP,
++	};
++
++	hw->max_listen_interval = 10;
++
++	ieee80211_hw_set(hw, SIGNAL_DBM);
++	ieee80211_hw_set(hw, HAS_RATE_CONTROL);
++	ieee80211_hw_set(hw, SUPPORTS_PS);
++	ieee80211_hw_set(hw, AMPDU_AGGREGATION);
++	ieee80211_hw_set(hw, HOST_BROADCAST_PS_BUFFERING);
++	//IEEE80211_HW_PS_NULLFUNC_STACK |
++	//IEEE80211_HW_CONNECTION_MONITOR |
++	//IEEE80211_HW_BEACON_FILTER |
++	//IEEE80211_HW_AMPDU_AGGREGATION |
++	//IEEE80211_HW_REPORTS_TX_ACK_STATUS;
++	hw->max_rx_aggregation_subframes = 0x40;
++	hw->max_tx_aggregation_subframes = 0x40;
++
++	hw->wiphy->cipher_suites = cipher_suites;
++	hw->wiphy->n_cipher_suites = ARRAY_SIZE(cipher_suites);
++	hw->wiphy->max_scan_ie_len =
++	    epub->sip->tx_blksz - sizeof(struct sip_hdr) -
++	    sizeof(struct sip_cmd_scan);
++
++	/* ONLY station for now, support P2P soon... */
++	hw->wiphy->interface_modes =
++	    BIT(NL80211_IFTYPE_P2P_GO) |
++	    BIT(NL80211_IFTYPE_P2P_CLIENT) |
++	    BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_AP);
++
++	hw->wiphy->max_scan_ssids = 2;
++	//hw->wiphy->max_sched_scan_ssids = 16;
++	//hw->wiphy->max_match_sets = 16;
++
++	hw->wiphy->max_remain_on_channel_duration = 5000;
++
++	atomic_set(&epub->wl.off, 1);
++
++	epub->wl.sbands[NL80211_BAND_2GHZ].band = NL80211_BAND_2GHZ;
++	epub->wl.sbands[NL80211_BAND_2GHZ].channels = esp_channels_2ghz;
++	epub->wl.sbands[NL80211_BAND_2GHZ].bitrates = esp_rates_2ghz;
++	epub->wl.sbands[NL80211_BAND_2GHZ].n_channels =
++	    ARRAY_SIZE(esp_channels_2ghz);
++	epub->wl.sbands[NL80211_BAND_2GHZ].n_bitrates =
++	    ARRAY_SIZE(esp_rates_2ghz);
++	/*add to support 11n */
++	epub->wl.sbands[NL80211_BAND_2GHZ].ht_cap.ht_supported = true;
++	epub->wl.sbands[NL80211_BAND_2GHZ].ht_cap.cap = 0x116C;	//IEEE80211_HT_CAP_RX_STBC; //IEEE80211_HT_CAP_SGI_20;
++	epub->wl.sbands[NL80211_BAND_2GHZ].ht_cap.ampdu_factor =
++	    IEEE80211_HT_MAX_AMPDU_16K;
++	epub->wl.sbands[NL80211_BAND_2GHZ].ht_cap.ampdu_density =
++	    IEEE80211_HT_MPDU_DENSITY_NONE;
++	memset(&epub->wl.sbands[NL80211_BAND_2GHZ].ht_cap.mcs, 0,
++	       sizeof(epub->wl.sbands[NL80211_BAND_2GHZ].ht_cap.mcs));
++	epub->wl.sbands[NL80211_BAND_2GHZ].ht_cap.mcs.rx_mask[0] = 0xff;
++	//epub->wl.sbands[NL80211_BAND_2GHZ].ht_cap.mcs.rx_highest = 7;
++	//epub->wl.sbands[NL80211_BAND_2GHZ].ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
++
++	/* BAND_5GHZ TBD */
++
++	hw->wiphy->bands[NL80211_BAND_2GHZ] =
++	    &epub->wl.sbands[NL80211_BAND_2GHZ];
++	/* BAND_5GHZ TBD */
++
++	/*no fragment */
++	hw->wiphy->frag_threshold = IEEE80211_MAX_FRAG_THRESHOLD;
++
++	/* handle AC queue in f/w */
++	hw->queues = 4;
++	hw->max_rates = 4;
++	//hw->wiphy->reg_notifier = esp_reg_notify;
++
++	hw->vif_data_size = sizeof(struct esp_vif);
++	hw->sta_data_size = sizeof(struct esp_node);
++
++	//hw->max_rx_aggregation_subframes = 8;
++}
++
++int esp_register_mac80211(struct esp_pub *epub)
++{
++	int ret = 0;
++	u8 *wlan_addr;
++	u8 *p2p_addr;
++	int idx;
++
++	esp_pub_init_mac80211(epub);
++
++	epub->hw->wiphy->addresses = (struct mac_address *) esp_mac_addr;
++	memcpy(&epub->hw->wiphy->addresses[0], epub->mac_addr, ETH_ALEN);
++	memcpy(&epub->hw->wiphy->addresses[1], epub->mac_addr, ETH_ALEN);
++	wlan_addr = (u8 *) & epub->hw->wiphy->addresses[0];
++	p2p_addr = (u8 *) & epub->hw->wiphy->addresses[1];
++
++	for (idx = 0; idx < 64; idx++) {
++		p2p_addr[0] = wlan_addr[0] | 0x02;
++		p2p_addr[0] ^= idx << 2;
++		if (strncmp(p2p_addr, wlan_addr, 6) != 0)
++			break;
++	}
++
++	epub->hw->wiphy->n_addresses = 2;
++
++	ret = ieee80211_register_hw(epub->hw);
++
++	if (ret < 0) {
++		ESP_IEEE80211_DBG(ESP_DBG_ERROR,
++				  "unable to register mac80211 hw: %d\n",
++				  ret);
++		return ret;
++	} else {
++#ifdef MAC80211_NO_CHANGE
++		rtnl_lock();
++		if (epub->hw->wiphy->interface_modes &
++		    (BIT(NL80211_IFTYPE_P2P_GO) |
++		     BIT(NL80211_IFTYPE_P2P_CLIENT))) {
++			ret =
++			    ieee80211_if_add(hw_to_local(epub->hw),
++					     "p2p%d", NULL,
++					     NL80211_IFTYPE_STATION, NULL);
++			if (ret)
++				wiphy_warn(epub->hw->wiphy,
++					   "Failed to add default virtual iface\n");
++		}
++
++		rtnl_unlock();
++#endif
++	}
++
++	set_bit(ESP_WL_FLAG_HW_REGISTERED, &epub->wl.flags);
++
++	return ret;
++}
++
++static u8 getaddr_index(u8 * addr, struct esp_pub *epub)
++{
++	int i;
++	for (i = 0; i < ESP_PUB_MAX_VIF; i++)
++		if (memcmp
++		    (addr, (u8 *) & epub->hw->wiphy->addresses[i],
++		     ETH_ALEN) == 0)
++			return i;
++	return ESP_PUB_MAX_VIF;
++}
+diff --git a/drivers/net/wireless/esp8089/esp_mac80211.h b/drivers/net/wireless/esp8089/esp_mac80211.h
+new file mode 100644
+index 000000000000..699b27dcadd1
+--- /dev/null
++++ b/drivers/net/wireless/esp8089/esp_mac80211.h
+@@ -0,0 +1,38 @@
++/*
++ * Copyright (c) 2011-2014 Espressif System.
++ *
++ *     MAC80211 support module
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++#ifndef _ESP_MAC80211_H_
++#define _ESP_MAC80211_H_
++
++struct esp_80211_wmm_ac_param {
++	u8 aci_aifsn;		/* AIFSN, ACM, ACI */
++	u8 cw;			/* ECWmin, ECWmax (CW = 2^ECW - 1) */
++	u16 txop_limit;
++};
++
++struct esp_80211_wmm_param_element {
++	/* Element ID： 221 (0xdd); length: 24 */
++	/* required fields for WMM version 1 */
++	u8 oui[3];		/* 00:50:f2 */
++	u8 oui_type;		/* 2 */
++	u8 oui_subtype;		/* 1 */
++	u8 version;		/* 1 for WMM version 1.0 */
++	u8 qos_info;		/* AP/STA specif QoS info */
++	u8 reserved;		/* 0 */
++	struct esp_80211_wmm_ac_param ac[4];	/* AC_BE, AC_BK, AC_VI, AC_VO */
++};
++
++
++#endif				/* _ESP_MAC80211_H_ */
+diff --git a/drivers/net/wireless/esp8089/esp_main.c b/drivers/net/wireless/esp8089/esp_main.c
+new file mode 100644
+index 000000000000..404e0d7a6f54
+--- /dev/null
++++ b/drivers/net/wireless/esp8089/esp_main.c
+@@ -0,0 +1,263 @@
++/*
++ * Copyright (c) 2010 - 2014 Espressif System.
++ *
++ * main routine
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++
++#include <linux/netdevice.h>
++#include <linux/etherdevice.h>
++#include <linux/rtnetlink.h>
++#include <linux/firmware.h>
++#include <linux/sched.h>
++#include <linux/module.h>
++#include <net/cfg80211.h>
++#include <net/mac80211.h>
++#include <linux/time.h>
++#include <linux/moduleparam.h>
++
++#include "esp_pub.h"
++#include "esp_sip.h"
++#include "esp_sif.h"
++#include "esp_debug.h"
++#include "esp_file.h"
++#include "esp_wl.h"
++
++struct completion *gl_bootup_cplx = NULL;
++
++#ifndef FPGA_DEBUG
++static int esp_download_fw(struct esp_pub *epub);
++#endif				/* !FGPA_DEBUG */
++
++static int modparam_no_txampdu = 0;
++static int modparam_no_rxampdu = 0;
++module_param_named(no_txampdu, modparam_no_txampdu, int, 0444);
++MODULE_PARM_DESC(no_txampdu, "Disable tx ampdu.");
++module_param_named(no_rxampdu, modparam_no_rxampdu, int, 0444);
++MODULE_PARM_DESC(no_rxampdu, "Disable rx ampdu.");
++
++static char *modparam_eagle_path = "/lib/firmware";
++module_param_named(eagle_path, modparam_eagle_path, charp, 0444);
++MODULE_PARM_DESC(eagle_path, "eagle path");
++
++bool mod_support_no_txampdu()
++{
++	return modparam_no_txampdu;
++}
++
++bool mod_support_no_rxampdu()
++{
++	return modparam_no_rxampdu;
++}
++
++void mod_support_no_txampdu_set(bool value)
++{
++	modparam_no_txampdu = value;
++}
++
++char *mod_eagle_path_get(void)
++{
++	if (modparam_eagle_path[0] == '\0')
++		return NULL;
++
++	return modparam_eagle_path;
++}
++
++int esp_pub_init_all(struct esp_pub *epub)
++{
++	int ret = 0;
++
++	/* completion for bootup event poll */
++	DECLARE_COMPLETION_ONSTACK(complete);
++	atomic_set(&epub->ps.state, ESP_PM_OFF);
++	if (epub->sdio_state == ESP_SDIO_STATE_FIRST_INIT) {
++		epub->sip = sip_attach(epub);
++		if (epub->sip == NULL) {
++			printk(KERN_ERR "%s sip alloc failed\n", __func__);
++			return -ENOMEM;
++		}
++
++		esp_dump_var("esp_msg_level", NULL, &esp_msg_level,
++			     ESP_U32);
++
++#ifdef ESP_ANDROID_LOGGER
++		esp_dump_var("log_off", NULL, &log_off, ESP_U32);
++#endif				/* ESP_ANDROID_LOGGER */
++	} else {
++		atomic_set(&epub->sip->state, SIP_PREPARE_BOOT);
++		atomic_set(&epub->sip->tx_credits, 0);
++	}
++
++	epub->sip->to_host_seq = 0;
++
++#ifdef TEST_MODE
++	if (sif_get_ate_config() != 0 && sif_get_ate_config() != 1
++	    && sif_get_ate_config() != 6) {
++		esp_test_init(epub);
++		return -1;
++	}
++#endif
++
++#ifndef FPGA_DEBUG
++	ret = esp_download_fw(epub);
++#ifdef TEST_MODE
++	if (sif_get_ate_config() == 6) {
++		sif_enable_irq(epub);
++		mdelay(500);
++		sif_disable_irq(epub);
++		mdelay(1000);
++		esp_test_init(epub);
++		return -1;
++	}
++#endif
++	if (ret) {
++		esp_dbg(ESP_DBG_ERROR, "download firmware failed\n");
++		return ret;
++	}
++
++	esp_dbg(ESP_DBG_TRACE, "download firmware OK \n");
++#else
++	sip_send_bootup(epub->sip);
++#endif				/* FPGA_DEBUG */
++
++	gl_bootup_cplx = &complete;
++	epub->wait_reset = 0;
++	sif_enable_irq(epub);
++
++	if (epub->sdio_state == ESP_SDIO_STATE_SECOND_INIT
++	    || sif_get_ate_config() == 1) {
++		ret = sip_poll_bootup_event(epub->sip);
++	} else {
++		ret = sip_poll_resetting_event(epub->sip);
++		if (ret == 0) {
++			sif_lock_bus(epub);
++			sif_interrupt_target(epub, 7);
++			sif_unlock_bus(epub);
++		}
++
++	}
++
++	gl_bootup_cplx = NULL;
++
++	if (sif_get_ate_config() == 1)
++		ret = -EOPNOTSUPP;
++
++	return ret;
++}
++
++void esp_dsr(struct esp_pub *epub)
++{
++	sip_rx(epub);
++}
++
++
++struct esp_fw_hdr {
++	u8 magic;
++	u8 blocks;
++	u8 pad[2];
++	u32 entry_addr;
++} __packed;
++
++struct esp_fw_blk_hdr {
++	u32 load_addr;
++	u32 data_len;
++} __packed;
++
++#define ESP_FW_NAME1 "eagle_fw_ate_config_v19.bin"
++#define ESP_FW_NAME2 "eagle_fw_first_init_v19.bin"
++#define ESP_FW_NAME3 "eagle_fw_second_init_v19.bin"
++
++#ifndef FPGA_DEBUG
++static int esp_download_fw(struct esp_pub *epub)
++{
++	const struct firmware *fw_entry;
++	u8 *fw_buf = NULL;
++	u32 offset = 0;
++	int ret = 0;
++	u8 blocks;
++	struct esp_fw_hdr *fhdr;
++	struct esp_fw_blk_hdr *bhdr = NULL;
++	struct sip_cmd_bootup bootcmd;
++	char *esp_fw_name;
++
++	if (sif_get_ate_config() == 1) {
++		esp_fw_name = ESP_FW_NAME3;
++	} else {
++		esp_fw_name =
++		    epub->sdio_state ==
++		    ESP_SDIO_STATE_FIRST_INIT ? ESP_FW_NAME1 :
++		    ESP_FW_NAME2;
++	}
++	ret = request_firmware(&fw_entry, esp_fw_name, epub->dev);
++
++	if (ret)
++		return ret;
++
++	fw_buf = kmemdup(fw_entry->data, fw_entry->size, GFP_KERNEL);
++
++	release_firmware(fw_entry);
++
++	if (fw_buf == NULL) {
++		return -ENOMEM;
++	}
++
++	fhdr = (struct esp_fw_hdr *) fw_buf;
++
++	if (fhdr->magic != 0xE9) {
++		esp_dbg(ESP_DBG_ERROR, "%s wrong magic! \n", __func__);
++		goto _err;
++	}
++
++	blocks = fhdr->blocks;
++	offset += sizeof(struct esp_fw_hdr);
++
++	while (blocks) {
++
++		bhdr = (struct esp_fw_blk_hdr *) (&fw_buf[offset]);
++		offset += sizeof(struct esp_fw_blk_hdr);
++
++		ret =
++		    sip_write_memory(epub->sip, bhdr->load_addr,
++				     &fw_buf[offset], bhdr->data_len);
++
++		if (ret) {
++			esp_dbg(ESP_DBG_ERROR,
++				"%s Failed to write fw, err: %d\n",
++				__func__, ret);
++			goto _err;
++		}
++
++		blocks--;
++		offset += bhdr->data_len;
++	}
++
++	/* TODO: last byte should be the checksum and skip checksum for now */
++
++	bootcmd.boot_addr = fhdr->entry_addr;
++	ret =
++	    sip_send_cmd(epub->sip, SIP_CMD_BOOTUP,
++			 sizeof(struct sip_cmd_bootup), &bootcmd);
++
++	if (ret)
++		goto _err;
++
++      _err:
++	kfree(fw_buf);
++
++	return ret;
++
++}
++
++MODULE_FIRMWARE(ESP_FW_NAME1);
++MODULE_FIRMWARE(ESP_FW_NAME2);
++MODULE_FIRMWARE(ESP_FW_NAME3);
++#endif				/* !FPGA_DEBUG */
+diff --git a/drivers/net/wireless/esp8089/esp_path.h b/drivers/net/wireless/esp8089/esp_path.h
+new file mode 100644
+index 000000000000..1ceb14bc3b15
+--- /dev/null
++++ b/drivers/net/wireless/esp8089/esp_path.h
+@@ -0,0 +1,6 @@
++#ifndef _ESP_PATH_H_
++#define _ESP_PATH_H_
++#define FWPATH "/lib/firmware"
++//module_param_string(fwpath, fwpath, sizeof(fwpath), 0644);
++
++#endif				/* _ESP_PATH_H_ */
+diff --git a/drivers/net/wireless/esp8089/esp_pub.h b/drivers/net/wireless/esp8089/esp_pub.h
+new file mode 100644
+index 000000000000..0d3ad3655cf4
+--- /dev/null
++++ b/drivers/net/wireless/esp8089/esp_pub.h
+@@ -0,0 +1,222 @@
++/*
++ * Copyright (c) 2011-2014 Espressif System.
++ *
++ *   wlan device header file
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++
++#ifndef _ESP_PUB_H_
++#define _ESP_PUB_H_
++
++#include <linux/etherdevice.h>
++#include <linux/rtnetlink.h>
++#include <linux/firmware.h>
++#include <linux/sched.h>
++#include <net/mac80211.h>
++#include <net/cfg80211.h>
++#include <linux/version.h>
++#include "sip2_common.h"
++
++enum esp_sdio_state {
++	ESP_SDIO_STATE_FIRST_INIT,
++	ESP_SDIO_STATE_FIRST_NORMAL_EXIT,
++	ESP_SDIO_STATE_FIRST_ERROR_EXIT,
++	ESP_SDIO_STATE_SECOND_INIT,
++	ESP_SDIO_STATE_SECOND_ERROR_EXIT,
++};
++
++enum esp_tid_state {
++	ESP_TID_STATE_INIT,
++	ESP_TID_STATE_TRIGGER,
++	ESP_TID_STATE_PROGRESS,
++	ESP_TID_STATE_OPERATIONAL,
++	ESP_TID_STATE_WAIT_STOP,
++	ESP_TID_STATE_STOP,
++};
++
++struct esp_tx_tid {
++	u8 state;
++	u8 cnt;
++	u16 ssn;
++};
++
++#define WME_NUM_TID 16
++struct esp_node {
++	struct esp_tx_tid tid[WME_NUM_TID];
++	struct ieee80211_sta *sta;
++	u8 ifidx;
++	u8 index;
++};
++
++#define WME_AC_BE 2
++#define WME_AC_BK 3
++#define WME_AC_VI 1
++#define WME_AC_VO 0
++
++struct llc_snap_hdr {
++	u8 dsap;
++	u8 ssap;
++	u8 cntl;
++	u8 org_code[3];
++	__be16 eth_type;
++} __packed;
++
++struct esp_vif {
++	struct esp_pub *epub;
++	u8 index;
++	u32 beacon_interval;
++	bool ap_up;
++	struct timer_list beacon_timer;
++};
++
++/* WLAN related, mostly... */
++/*struct hw_scan_timeout {
++        struct delayed_work w;
++        struct ieee80211_hw *hw;
++};*/
++
++typedef struct esp_wl {
++	u8 bssid[ETH_ALEN];
++	u8 req_bssid[ETH_ALEN];
++
++	//struct hw_scan_timeout *hsd;
++	struct cfg80211_scan_request *scan_req;
++	atomic_t ptk_cnt;
++	atomic_t gtk_cnt;
++	atomic_t tkip_key_set;
++
++	/* so far only 2G band */
++	struct ieee80211_supported_band sbands[NUM_NL80211_BANDS];
++
++	unsigned long flags;
++	atomic_t off;
++} esp_wl_t;
++
++typedef struct esp_hw_idx_map {
++	u8 mac[ETH_ALEN];
++	u8 flag;
++} esp_hw_idx_map_t;
++
++#define ESP_WL_FLAG_RFKILL                	BIT(0)
++#define ESP_WL_FLAG_HW_REGISTERED   		BIT(1)
++#define ESP_WL_FLAG_CONNECT              		BIT(2)
++#define ESP_WL_FLAG_STOP_TXQ          		BIT(3)
++
++#define ESP_PUB_MAX_VIF		2
++#define ESP_PUB_MAX_STA		16	//for one interface
++#define ESP_PUB_MAX_RXAMPDU	8	//for all interfaces
++
++enum {
++	ESP_PM_OFF = 0,
++	ESP_PM_TURNING_ON,
++	ESP_PM_ON,
++	ESP_PM_TURNING_OFF,	/* Do NOT change the order */
++};
++
++struct esp_ps {
++	u32 dtim_period;
++	u32 max_sleep_period;
++	unsigned long last_config_time;
++	atomic_t state;
++	bool nulldata_pm_on;
++};
++
++struct esp_mac_prefix {
++	u8 mac_index;
++	u8 mac_addr_prefix[3];
++};
++
++struct esp_pub {
++	struct device *dev;
++#ifdef ESP_NO_MAC80211
++	struct net_device *net_dev;
++	struct wireless_dev *wdev;
++	struct net_device_stats *net_stats;
++#else
++	struct ieee80211_hw *hw;
++	struct ieee80211_vif *vif;
++	u8 vif_slot;
++#endif				/* ESP_MAC80211 */
++
++	void *sif;		/* serial interface control block, e.g. sdio */
++	enum esp_sdio_state sdio_state;
++	struct esp_sip *sip;
++	struct esp_wl wl;
++	struct esp_hw_idx_map hi_map[19];
++	struct esp_hw_idx_map low_map[ESP_PUB_MAX_VIF][2];
++	//u32 flags; //flags to represent rfkill switch,start
++	u8 roc_flags;		//0: not in remain on channel state, 1: in roc state
++
++	struct work_struct tx_work;	/* attach to ieee80211 workqueue */
++	/* latest mac80211 has multiple tx queue, but we stick with single queue now */
++	spinlock_t rx_lock;
++	spinlock_t tx_ampdu_lock;
++	spinlock_t rx_ampdu_lock;
++	spinlock_t tx_lock;
++	struct mutex tx_mtx;
++	struct sk_buff_head txq;
++	atomic_t txq_stopped;
++
++	struct work_struct sendup_work;	/* attach to ieee80211 workqueue */
++	struct sk_buff_head txdoneq;
++	struct sk_buff_head rxq;
++
++	struct workqueue_struct *esp_wkq;
++
++	//u8 bssid[ETH_ALEN];
++	u8 mac_addr[ETH_ALEN];
++
++	u32 rx_filter;
++	unsigned long scan_permit;
++	bool scan_permit_valid;
++	struct delayed_work scan_timeout_work;
++	u32 enodes_map;
++	u8 rxampdu_map;
++	u32 enodes_maps[ESP_PUB_MAX_VIF];
++	struct esp_node *enodes[ESP_PUB_MAX_STA + 1];
++	struct esp_node *rxampdu_node[ESP_PUB_MAX_RXAMPDU];
++	u8 rxampdu_tid[ESP_PUB_MAX_RXAMPDU];
++	struct esp_ps ps;
++	int enable_int;
++	int wait_reset;
++};
++
++typedef struct esp_pub esp_pub_t;
++
++struct esp_pub *esp_pub_alloc_mac80211(struct device *dev);
++int esp_pub_dealloc_mac80211(struct esp_pub *epub);
++int esp_register_mac80211(struct esp_pub *epub);
++
++int esp_pub_init_all(struct esp_pub *epub);
++
++char *mod_eagle_path_get(void);
++
++void esp_dsr(struct esp_pub *epub);
++void hw_scan_done(struct esp_pub *epub, bool aborted);
++void esp_rocdone_process(struct ieee80211_hw *hw,
++			 struct sip_evt_roc *report);
++
++void esp_ps_config(struct esp_pub *epub, struct esp_ps *ps, bool on);
++
++struct esp_node *esp_get_node_by_addr(struct esp_pub *epub,
++				      const u8 * addr);
++struct esp_node *esp_get_node_by_index(struct esp_pub *epub, u8 index);
++int esp_get_empty_rxampdu(struct esp_pub *epub, const u8 * addr, u8 tid);
++int esp_get_exist_rxampdu(struct esp_pub *epub, const u8 * addr, u8 tid);
++
++#ifdef TEST_MODE
++int test_init_netlink(struct esp_sip *sip);
++void test_exit_netlink(void);
++void esp_test_cmd_event(u32 cmd_type, char *reply_info);
++void esp_test_init(struct esp_pub *epub);
++#endif
++#endif				/* _ESP_PUB_H_ */
+diff --git a/drivers/net/wireless/esp8089/esp_sif.h b/drivers/net/wireless/esp8089/esp_sif.h
+new file mode 100644
+index 000000000000..2d49f2bc8035
+--- /dev/null
++++ b/drivers/net/wireless/esp8089/esp_sif.h
+@@ -0,0 +1,207 @@
++/*
++ * Copyright (c) 2011 - 2014 Espressif System.
++ *
++ *   Serial I/F wrapper layer for eagle WLAN device,
++ *    abstraction of buses like SDIO/SIP, and provides
++ *    flow control for tx/rx layer
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++
++#ifndef _ESP_SIF_H_
++#define _ESP_SIF_H_
++
++#include "esp_pub.h"
++#include <linux/mmc/host.h>
++#include <linux/spi/spi.h>
++
++/*
++ *  H/W SLC module definitions
++ */
++
++#define SIF_SLC_BLOCK_SIZE                512
++
++
++/* S/W struct mapping to slc registers */
++typedef struct slc_host_regs {
++	/* do NOT read token_rdata
++	 *
++	 u32 pf_data;
++	 u32 token_rdata;
++	 */
++	u32 intr_raw;
++	u32 state_w0;
++	u32 state_w1;
++	u32 config_w0;
++	u32 config_w1;
++	u32 intr_status;
++	u32 config_w2;
++	u32 config_w3;
++	u32 config_w4;
++	u32 token_wdata;
++	u32 intr_clear;
++	u32 intr_enable;
++} sif_slc_reg_t;
++
++
++enum io_sync_type {
++	ESP_SIF_NOSYNC = 0,
++	ESP_SIF_SYNC,
++};
++
++typedef struct esp_sdio_ctrl {
++	struct sdio_func *func;
++	struct esp_pub *epub;
++
++
++	struct list_head free_req;
++
++	u8 *dma_buffer;
++
++	spinlock_t scat_lock;
++	struct list_head scat_req;
++
++	bool off;
++	atomic_t irq_handling;
++	const struct sdio_device_id *id;
++	u32 slc_blk_sz;
++	u32 target_id;
++	u32 slc_window_end_addr;
++
++	struct slc_host_regs slc_regs;
++	atomic_t irq_installed;
++
++} esp_sdio_ctrl_t;
++
++#define SIF_TO_DEVICE                    0x1
++#define SIF_FROM_DEVICE                    0x2
++
++#define SIF_SYNC             0x00000010
++#define SIF_ASYNC           0x00000020
++
++#define SIF_BYTE_BASIS              0x00000040
++#define SIF_BLOCK_BASIS             0x00000080
++
++#define SIF_FIXED_ADDR           0x00000100
++#define SIF_INC_ADDR     0x00000200
++
++#define EPUB_CTRL_CHECK(_epub, _go_err) do{\
++	if (_epub == NULL) {\
++		ESSERT(0);\
++		goto _go_err;\
++	}\
++	if ((_epub)->sif == NULL) {\
++		ESSERT(0);\
++		goto _go_err;\
++	}\
++}while(0)
++
++#define EPUB_FUNC_CHECK(_epub, _go_err) do{\
++	if (_epub == NULL) {\
++		ESSERT(0);\
++		goto _go_err;\
++	}\
++	if ((_epub)->sif == NULL) {\
++		ESSERT(0);\
++		goto _go_err;\
++	}\
++	if (((struct esp_sdio_ctrl *)(_epub)->sif)->func == NULL) {\
++		ESSERT(0);\
++		goto _go_err;\
++	}\
++}while(0)
++
++#define EPUB_TO_CTRL(_epub) (((struct esp_sdio_ctrl *)(_epub)->sif))
++
++#define EPUB_TO_FUNC(_epub) (((struct esp_sdio_ctrl *)(_epub)->sif)->func)
++
++void sdio_io_writeb(struct esp_pub *epub, u8 value, int addr, int *res);
++u8 sdio_io_readb(struct esp_pub *epub, int addr, int *res);
++
++
++void sif_enable_irq(struct esp_pub *epub);
++void sif_disable_irq(struct esp_pub *epub);
++void sif_disable_target_interrupt(struct esp_pub *epub);
++
++u32 sif_get_blksz(struct esp_pub *epub);
++u32 sif_get_target_id(struct esp_pub *epub);
++
++void sif_dsr(struct sdio_func *func);
++int sif_io_raw(struct esp_pub *epub, u32 addr, u8 * buf, u32 len,
++	       u32 flag);
++int sif_io_sync(struct esp_pub *epub, u32 addr, u8 * buf, u32 len,
++		u32 flag);
++int sif_io_async(struct esp_pub *epub, u32 addr, u8 * buf, u32 len,
++		 u32 flag, void *context);
++int sif_lldesc_read_sync(struct esp_pub *epub, u8 * buf, u32 len);
++int sif_lldesc_write_sync(struct esp_pub *epub, u8 * buf, u32 len);
++int sif_lldesc_read_raw(struct esp_pub *epub, u8 * buf, u32 len,
++			bool noround);
++int sif_lldesc_write_raw(struct esp_pub *epub, u8 * buf, u32 len);
++
++int sif_platform_get_irq_no(void);
++int sif_platform_is_irq_occur(void);
++void sif_platform_irq_clear(void);
++void sif_platform_irq_mask(int enable_mask);
++int sif_platform_irq_init(void);
++void sif_platform_irq_deinit(void);
++
++int esp_common_read(struct esp_pub *epub, u8 * buf, u32 len, int sync,
++		    bool noround);
++int esp_common_write(struct esp_pub *epub, u8 * buf, u32 len, int sync);
++int esp_common_read_with_addr(struct esp_pub *epub, u32 addr, u8 * buf,
++			      u32 len, int sync);
++int esp_common_write_with_addr(struct esp_pub *epub, u32 addr, u8 * buf,
++			       u32 len, int sync);
++
++int esp_common_readbyte_with_addr(struct esp_pub *epub, u32 addr, u8 * buf,
++				  int sync);
++int esp_common_writebyte_with_addr(struct esp_pub *epub, u32 addr, u8 buf,
++				   int sync);
++
++int sif_read_reg_window(struct esp_pub *epub, unsigned int reg_addr,
++			unsigned char *value);
++int sif_write_reg_window(struct esp_pub *epub, unsigned int reg_addr,
++			 unsigned char *value);
++int sif_ack_target_read_err(struct esp_pub *epub);
++int sif_had_io_enable(struct esp_pub *epub);
++
++struct slc_host_regs *sif_get_regs(struct esp_pub *epub);
++
++void sif_lock_bus(struct esp_pub *epub);
++void sif_unlock_bus(struct esp_pub *epub);
++
++int sif_interrupt_target(struct esp_pub *epub, u8 index);
++#ifdef USE_EXT_GPIO
++int sif_config_gpio_mode(struct esp_pub *epub, u8 gpio_num, u8 gpio_mode);
++int sif_set_gpio_output(struct esp_pub *epub, u16 mask, u16 value);
++int sif_get_gpio_intr(struct esp_pub *epub, u16 intr_mask, u16 * value);
++int sif_get_gpio_input(struct esp_pub *epub, u16 * mask, u16 * value);
++#endif
++
++void check_target_id(struct esp_pub *epub);
++
++void sif_record_bt_config(int value);
++int sif_get_bt_config(void);
++void sif_record_rst_config(int value);
++int sif_get_rst_config(void);
++void sif_record_ate_config(int value);
++int sif_get_ate_config(void);
++void sif_record_retry_config(void);
++int sif_get_retry_config(void);
++void sif_record_wakeup_gpio_config(int value);
++int sif_get_wakeup_gpio_config(void);
++
++#define sif_reg_read_sync(epub, addr, buf, len) sif_io_sync((epub), (addr), (buf), (len), SIF_FROM_DEVICE | SIF_BYTE_BASIS | SIF_INC_ADDR)
++
++#define sif_reg_write_sync(epub, addr, buf, len) sif_io_sync((epub), (addr), (buf), (len), SIF_TO_DEVICE | SIF_BYTE_BASIS | SIF_INC_ADDR)
++
++#endif				/* _ESP_SIF_H_ */
+diff --git a/drivers/net/wireless/esp8089/esp_sip.c b/drivers/net/wireless/esp8089/esp_sip.c
+new file mode 100644
+index 000000000000..6602a1e22ab1
+--- /dev/null
++++ b/drivers/net/wireless/esp8089/esp_sip.c
+@@ -0,0 +1,2420 @@
++/*
++ * Copyright (c) 2009 - 2014 Espressif System.
++ *
++ * Serial Interconnctor Protocol
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++
++#include <linux/ieee80211.h>
++#include <net/mac80211.h>
++#include <net/cfg80211.h>
++#include <linux/skbuff.h>
++#include <linux/bitops.h>
++#include <linux/version.h>
++#include <linux/mmc/card.h>
++#include <linux/mmc/mmc.h>
++#include <linux/mmc/host.h>
++#include <linux/mmc/sdio_func.h>
++#include <linux/mmc/sdio_ids.h>
++#include <linux/mmc/sdio.h>
++#include <linux/mmc/sd.h>
++#include <linux/completion.h>
++#include <linux/timer.h>
++
++#include "esp_mac80211.h"
++#include "esp_pub.h"
++#include "esp_sip.h"
++#include "esp_ctrl.h"
++#include "esp_sif.h"
++#include "esp_debug.h"
++#include "slc_host_register.h"
++#include "esp_wmac.h"
++#include "esp_utils.h"
++
++#ifdef USE_EXT_GPIO
++#include "esp_ext.h"
++#endif				/* USE_EXT_GPIO */
++
++extern struct completion *gl_bootup_cplx;
++
++static int old_signal = -35;
++static int avg_signal = 0;
++static int signal_loop = 0;
++
++struct esp_mac_prefix esp_mac_prefix_table[] = {
++	{0, {0x18, 0xfe, 0x34}},
++	{1, {0xac, 0xd0, 0x74}},
++	{255, {0x18, 0xfe, 0x34}},
++};
++
++#define SIGNAL_COUNT  300
++
++#define TID_TO_AC(_tid) ((_tid)== 0||((_tid)==3)?WME_AC_BE:((_tid)<3)?WME_AC_BK:((_tid)<6)?WME_AC_VI:WME_AC_VO)
++
++#ifdef SIP_DEBUG
++#define esp_sip_dbg esp_dbg
++struct sip_trace {
++	u32 tx_data;
++	u32 tx_cmd;
++	u32 rx_data;
++	u32 rx_evt;
++	u32 rx_tx_status;
++	u32 tx_out_of_credit;
++	u32 tx_one_shot_overflow;
++};
++static struct sip_trace str;
++#define STRACE_TX_DATA_INC() (str.tx_data++)
++#define STRACE_TX_CMD_INC()  (str.tx_cmd++)
++#define STRACE_RX_DATA_INC() (str.rx_data++)
++#define STRACE_RX_EVENT_INC() (str.rx_evt++)
++#define STRACE_RX_TXSTATUS_INC() (str.rx_tx_status++)
++#define STRACE_TX_OUT_OF_CREDIT_INC() (str.tx_out_of_credit++)
++#define STRACE_TX_ONE_SHOT_INC() (str.tx_one_shot_overflow++)
++#define STRACE_SHOW(sip)
++#else
++#define esp_sip_dbg(...)
++#define STRACE_TX_DATA_INC()
++#define STRACE_TX_CMD_INC()
++#define STRACE_RX_DATA_INC()
++#define STRACE_RX_EVENT_INC()
++#define STRACE_RX_TXSTATUS_INC()
++#define STRACE_TX_OUT_OF_CREDIT_INC()
++#define STRACE_TX_ONE_SHOT_INC()
++#define STRACE_SHOW(sip)
++#endif				/* SIP_DEBUG */
++
++#define SIP_STOP_QUEUE_THRESHOLD 48
++#define SIP_RESUME_QUEUE_THRESHOLD  12
++
++#define SIP_MIN_DATA_PKT_LEN    (sizeof(struct esp_mac_rx_ctrl) + 24)	//24 is min 80211hdr
++
++#ifdef ESP_PREALLOC
++extern struct sk_buff *esp_get_sip_skb(int size);
++extern void esp_put_sip_skb(struct sk_buff **skb);
++
++extern u8 *esp_get_tx_aggr_buf(void);
++extern void esp_put_tx_aggr_buf(u8 ** p);
++
++#endif
++
++static void sip_recalc_credit_init(struct esp_sip *sip);
++
++static int sip_recalc_credit_claim(struct esp_sip *sip, int force);
++
++static void sip_recalc_credit_release(struct esp_sip *sip);
++
++static struct sip_pkt *sip_get_ctrl_buf(struct esp_sip *sip,
++					SIP_BUF_TYPE bftype);
++
++static void sip_reclaim_ctrl_buf(struct esp_sip *sip, struct sip_pkt *pkt,
++				 SIP_BUF_TYPE bftype);
++
++static void sip_free_init_ctrl_buf(struct esp_sip *sip);
++
++static int sip_pack_pkt(struct esp_sip *sip, struct sk_buff *skb,
++			int *pm_state);
++
++static struct esp_mac_rx_ctrl *sip_parse_normal_mac_ctrl(struct sk_buff
++							 *skb,
++							 int *pkt_len_enc,
++							 int *buf_len,
++							 int *pulled_len);
++
++static struct sk_buff *sip_parse_data_rx_info(struct esp_sip *sip,
++					      struct sk_buff *skb,
++					      int pkt_len_enc, int buf_len,
++					      struct esp_mac_rx_ctrl
++					      *mac_ctrl, int *pulled_len);
++
++static inline void sip_rx_pkt_enqueue(struct esp_sip *sip,
++				      struct sk_buff *skb);
++
++static void sip_after_write_pkts(struct esp_sip *sip);
++
++static void sip_update_tx_credits(struct esp_sip *sip,
++				  u16 recycled_credits);
++
++//static void sip_trigger_txq_process(struct esp_sip *sip);
++
++static bool sip_rx_pkt_process(struct esp_sip *sip, struct sk_buff *skb);
++
++static void sip_tx_status_report(struct esp_sip *sip, struct sk_buff *skb,
++				 struct ieee80211_tx_info *tx_info,
++				 bool success);
++
++#ifdef FPGA_TXDATA
++int sip_send_tx_data(struct esp_sip *sip);
++#endif				/* FPGA_TXDATA */
++
++#ifdef FPGA_LOOPBACK
++int sip_send_loopback_cmd_mblk(struct esp_sip *sip);
++#endif				/* FPGA_LOOPBACK */
++
++static bool check_ac_tid(u8 * pkt, u8 ac, u8 tid)
++{
++	struct ieee80211_hdr *wh = (struct ieee80211_hdr *) pkt;
++#ifdef TID_DEBUG
++	u16 real_tid = 0;
++#endif				//TID_DEBUG
++
++	if (ieee80211_is_data_qos(wh->frame_control)) {
++#ifdef TID_DEBUG
++		real_tid =
++		    *ieee80211_get_qos_ctl(wh) &
++		    IEEE80211_QOS_CTL_TID_MASK;
++
++		esp_sip_dbg(ESP_SHOW, "ac:%u, tid:%u, tid in pkt:%u\n", ac,
++			    tid, real_tid);
++		if (tid != real_tid) {
++			esp_sip_dbg(ESP_DBG_ERROR,
++				    "111 ac:%u, tid:%u, tid in pkt:%u\n",
++				    ac, tid, real_tid);
++		}
++		if (TID_TO_AC(tid) != ac) {
++			esp_sip_dbg(ESP_DBG_ERROR,
++				    "222 ac:%u, tid:%u, tid in pkt:%u\n",
++				    ac, tid, real_tid);
++		}
++#endif				/* TID_DEBUG */
++	} else if (ieee80211_is_mgmt(wh->frame_control)) {
++#ifdef TID_DEBUG
++		esp_sip_dbg(ESP_SHOW, "ac:%u, tid:%u\n", ac, tid);
++		if (tid != 7 || ac != WME_AC_VO) {
++			esp_sip_dbg(ESP_DBG_ERROR, "333 ac:%u, tid:%u\n",
++				    ac, tid);
++		}
++#endif				/* TID_DEBUG */
++	} else {
++		if (ieee80211_is_ctl(wh->frame_control)) {
++#ifdef TID_DEBUG
++			esp_sip_dbg(ESP_SHOW,
++				    "%s is ctrl pkt fc 0x%04x ac:%u, tid:%u, tid in pkt:%u\n",
++				    __func__, wh->frame_control, ac, tid,
++				    real_tid);
++#endif				/* TID_DEBUG */
++		} else {
++			if (tid != 0 || ac != WME_AC_BE) {
++				//show_buf(pkt, 24);
++				esp_sip_dbg(ESP_DBG_LOG,
++					    "444 ac:%u, tid:%u \n", ac,
++					    tid);
++				if (tid == 7 && ac == WME_AC_VO)
++					return false;
++			}
++			return true;	//hack to modify non-qos null data.
++
++		}
++	}
++
++	return false;
++}
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0))
++static void sip_recalc_credit_timeout(struct timer_list *t)
++#else
++static void sip_recalc_credit_timeout(unsigned long data)
++#endif
++{
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0))
++	struct esp_sip *sip = from_timer(sip, t, credit_timer);
++#else
++	struct esp_sip *sip = (struct esp_sip *) data;
++#endif
++
++	esp_dbg(ESP_DBG_ERROR, "rct");
++
++	sip_recalc_credit_claim(sip, 1);	/* recalc again */
++}
++
++static void sip_recalc_credit_init(struct esp_sip *sip)
++{
++	atomic_set(&sip->credit_status, RECALC_CREDIT_DISABLE);	//set it disable
++
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0))
++	timer_setup(&sip->credit_timer, sip_recalc_credit_timeout, 0);
++#else
++	init_timer(&sip->credit_timer);
++	sip->credit_timer.data = (unsigned long) sip;
++	sip->credit_timer.function = sip_recalc_credit_timeout;
++#endif
++}
++
++static int sip_recalc_credit_claim(struct esp_sip *sip, int force)
++{
++	int ret;
++
++	if (atomic_read(&sip->credit_status) == RECALC_CREDIT_ENABLE
++	    && force == 0)
++		return 1;
++
++	atomic_set(&sip->credit_status, RECALC_CREDIT_ENABLE);
++	ret = sip_send_recalc_credit(sip->epub);
++	if (ret) {
++		esp_dbg(ESP_DBG_ERROR, "%s error %d", __func__, ret);
++		return ret;
++	}
++	/*setup a timer for handle the abs_credit not receive */
++	mod_timer(&sip->credit_timer, jiffies + msecs_to_jiffies(2000));
++
++	esp_dbg(ESP_SHOW, "rcc");
++
++	return ret;
++}
++
++static void sip_recalc_credit_release(struct esp_sip *sip)
++{
++	esp_dbg(ESP_SHOW, "rcr");
++
++	if (atomic_read(&sip->credit_status) == RECALC_CREDIT_ENABLE) {
++		atomic_set(&sip->credit_status, RECALC_CREDIT_DISABLE);
++		del_timer_sync(&sip->credit_timer);
++	} else
++		esp_dbg(ESP_SHOW, "maybe bogus credit");
++}
++
++static void sip_update_tx_credits(struct esp_sip *sip,
++				  u16 recycled_credits)
++{
++	esp_sip_dbg(ESP_DBG_TRACE, "%s:before add, credits is %d\n",
++		    __func__, atomic_read(&sip->tx_credits));
++
++	if (recycled_credits & 0x800) {
++		atomic_set(&sip->tx_credits, (recycled_credits & 0x7ff));
++		sip_recalc_credit_release(sip);
++	} else
++		atomic_add(recycled_credits, &sip->tx_credits);
++
++	esp_sip_dbg(ESP_DBG_TRACE, "%s:after add %d, credits is %d\n",
++		    __func__, recycled_credits,
++		    atomic_read(&sip->tx_credits));
++}
++
++void sip_trigger_txq_process(struct esp_sip *sip)
++{
++	if (atomic_read(&sip->tx_credits) <= sip->credit_to_reserve + SIP_CTRL_CREDIT_RESERVE	//no credits, do nothing
++	    || atomic_read(&sip->credit_status) == RECALC_CREDIT_ENABLE)
++		return;
++
++	if (sip_queue_may_resume(sip)) {
++		/* wakeup upper queue only if we have sufficient credits */
++		esp_sip_dbg(ESP_DBG_TRACE, "%s wakeup ieee80211 txq \n",
++			    __func__);
++		atomic_set(&sip->epub->txq_stopped, false);
++		ieee80211_wake_queues(sip->epub->hw);
++	} else if (atomic_read(&sip->epub->txq_stopped)) {
++		esp_sip_dbg(ESP_DBG_TRACE,
++			    "%s can't wake txq, credits: %d \n", __func__,
++			    atomic_read(&sip->tx_credits));
++	}
++
++	if (!skb_queue_empty(&sip->epub->txq)) {
++		/* try to send out pkt already in sip queue once we have credits */
++		esp_sip_dbg(ESP_DBG_TRACE, "%s resume sip txq \n",
++			    __func__);
++
++#if !defined(FPGA_TXDATA)
++		if (sif_get_ate_config() == 0) {
++			ieee80211_queue_work(sip->epub->hw,
++					     &sip->epub->tx_work);
++		} else {
++			queue_work(sip->epub->esp_wkq,
++				   &sip->epub->tx_work);
++		}
++#else
++		queue_work(sip->epub->esp_wkq, &sip->epub->tx_work);
++#endif
++	}
++}
++
++static bool sip_ampdu_occupy_buf(struct esp_sip *sip,
++				 struct esp_rx_ampdu_len *ampdu_len)
++{
++	return (ampdu_len->substate == 0
++		|| esp_wmac_rxsec_error(ampdu_len->substate)
++		|| (sip->dump_rpbm_err
++		    && ampdu_len->substate == RX_RPBM_ERR));
++}
++
++static bool sip_rx_pkt_process(struct esp_sip *sip, struct sk_buff *skb)
++{
++#define DO_NOT_COPY false
++#define DO_COPY true
++
++	struct sip_hdr *hdr = NULL;
++	struct sk_buff *rskb = NULL;
++	int remains_len = 0;
++	int first_pkt_len = 0;
++	u8 *bufptr = NULL;
++	int ret = 0;
++	bool trigger_rxq = false;
++
++	if (skb == NULL) {
++		esp_sip_dbg(ESP_DBG_ERROR, "%s NULL SKB!!!!!!!! \n",
++			    __func__);
++		return trigger_rxq;
++	}
++
++	hdr = (struct sip_hdr *) skb->data;
++	bufptr = skb->data;
++
++
++	esp_sip_dbg(ESP_DBG_TRACE, "%s Hcredits 0x%08x, realCredits %d\n",
++		    __func__, hdr->h_credits,
++		    hdr->h_credits & SIP_CREDITS_MASK);
++	if (hdr->h_credits & SIP_CREDITS_MASK) {
++		sip_update_tx_credits(sip,
++				      hdr->h_credits & SIP_CREDITS_MASK);
++	}
++
++	hdr->h_credits &= ~SIP_CREDITS_MASK;	/* clean credits in sip_hdr, prevent over-add */
++
++	esp_sip_dbg(ESP_DBG_TRACE, "%s credits %d\n", __func__,
++		    hdr->h_credits);
++
++	/*
++	 * first pkt's length is stored in  recycled_credits first 20 bits
++	 * config w3 [31:12]
++	 * repair hdr->len of first pkt
++	 */
++	remains_len = hdr->len;
++	first_pkt_len = hdr->h_credits >> 12;
++	hdr->len = first_pkt_len;
++
++	esp_dbg(ESP_DBG_TRACE, "%s first_pkt_len %d, whole pkt len %d \n",
++		__func__, first_pkt_len, remains_len);
++	if (first_pkt_len > remains_len) {
++		sip_recalc_credit_claim(sip, 0);
++		esp_dbg(ESP_DBG_ERROR,
++			"first_pkt_len %d, whole pkt len %d\n",
++			first_pkt_len, remains_len);
++		show_buf((u8 *) hdr, first_pkt_len);
++		ESSERT(0);
++		goto _exit;
++	}
++
++	/*
++	 * pkts handling, including the first pkt, should alloc new skb for each data pkt.
++	 * free the original whole skb after parsing is done.
++	 */
++	while (remains_len) {
++		if (remains_len < sizeof(struct sip_hdr)) {
++			sip_recalc_credit_claim(sip, 0);
++			ESSERT(0);
++			show_buf((u8 *) hdr, 512);
++			goto _exit;
++		}
++
++		hdr = (struct sip_hdr *) bufptr;
++		if (hdr->len <= 0) {
++			sip_recalc_credit_claim(sip, 0);
++			show_buf((u8 *) hdr, 512);
++			ESSERT(0);
++			goto _exit;
++		}
++
++		if ((hdr->len & 3) != 0) {
++			sip_recalc_credit_claim(sip, 0);
++			show_buf((u8 *) hdr, 512);
++			ESSERT(0);
++			goto _exit;
++		}
++		if (unlikely(hdr->seq != sip->rxseq++)) {
++			sip_recalc_credit_claim(sip, 0);
++			esp_dbg(ESP_DBG_ERROR,
++				"%s seq mismatch! got %u, expect %u\n",
++				__func__, hdr->seq, sip->rxseq - 1);
++			sip->rxseq = hdr->seq + 1;
++			show_buf(bufptr, 32);
++			ESSERT(0);
++		}
++
++		if (SIP_HDR_IS_CTRL(hdr)) {
++			STRACE_RX_EVENT_INC();
++			esp_sip_dbg(ESP_DBG_TRACE, "seq %u \n", hdr->seq);
++
++			ret = sip_parse_events(sip, bufptr);
++
++			skb_pull(skb, hdr->len);
++
++		} else if (SIP_HDR_IS_DATA(hdr)) {
++			struct esp_mac_rx_ctrl *mac_ctrl = NULL;
++			int pkt_len_enc = 0, buf_len = 0, pulled_len = 0;
++
++			STRACE_RX_DATA_INC();
++			esp_sip_dbg(ESP_DBG_TRACE, "seq %u \n", hdr->seq);
++			mac_ctrl =
++			    sip_parse_normal_mac_ctrl(skb, &pkt_len_enc,
++						      &buf_len,
++						      &pulled_len);
++			rskb =
++			    sip_parse_data_rx_info(sip, skb, pkt_len_enc,
++						   buf_len, mac_ctrl,
++						   &pulled_len);
++
++			if (rskb == NULL)
++				goto _move_on;
++
++			if (likely(atomic_read(&sip->epub->wl.off) == 0)) {
++#ifdef RX_CHECKSUM_TEST
++				esp_rx_checksum_test(rskb);
++#endif
++				local_bh_disable();
++				ieee80211_rx(sip->epub->hw, rskb);
++				local_bh_enable();
++			} else {
++				/* still need go thro parsing as skb_pull should invoke */
++				kfree_skb(rskb);
++			}
++		} else if (SIP_HDR_IS_AMPDU(hdr)) {
++			struct esp_mac_rx_ctrl *mac_ctrl = NULL;
++			struct esp_mac_rx_ctrl new_mac_ctrl;
++			struct esp_rx_ampdu_len *ampdu_len;
++			int pkt_num;
++			int pulled_len = 0;
++			static int pkt_dropped = 0;
++			static int pkt_total = 0;
++			bool have_rxabort = false;
++			bool have_goodpkt = false;
++			static u8 frame_head[16];
++			static u8 frame_buf_ttl = 0;
++
++			ampdu_len =
++			    (struct esp_rx_ampdu_len *) (skb->data +
++							 hdr->len /
++							 sip->rx_blksz *
++							 sip->rx_blksz);
++			esp_sip_dbg(ESP_DBG_TRACE,
++				    "%s rx ampdu total len %u\n", __func__,
++				    hdr->len);
++			if (skb->data != (u8 *) hdr) {
++				printk("%p %p\n", skb->data, hdr);
++				show_buf(skb->data, 512);
++				show_buf((u8 *) hdr, 512);
++				ESSERT(0);
++				goto _exit;
++			}
++			mac_ctrl =
++			    sip_parse_normal_mac_ctrl(skb, NULL, NULL,
++						      &pulled_len);
++			memcpy(&new_mac_ctrl, mac_ctrl,
++			       sizeof(struct esp_mac_rx_ctrl));
++			mac_ctrl = &new_mac_ctrl;
++			pkt_num = mac_ctrl->ampdu_cnt;
++			esp_sip_dbg(ESP_DBG_TRACE,
++				    "%s %d rx ampdu %u pkts, %d pkts dumped, first len %u\n",
++				    __func__, __LINE__,
++				    (unsigned
++				     int) ((hdr->len % sip->rx_blksz) /
++					   sizeof(struct
++						  esp_rx_ampdu_len)),
++				    pkt_num,
++				    (unsigned int) ampdu_len->sublen);
++
++			pkt_total += mac_ctrl->ampdu_cnt;
++			//esp_sip_dbg(ESP_DBG_ERROR, "%s ampdu dropped %d/%d\n", __func__, pkt_dropped, pkt_total);
++			while (pkt_num > 0) {
++				esp_sip_dbg(ESP_DBG_TRACE,
++					    "%s %d ampdu sub state %02x,\n",
++					    __func__, __LINE__,
++					    ampdu_len->substate);
++
++				if (sip_ampdu_occupy_buf(sip, ampdu_len)) {	//pkt is dumped
++
++					rskb =
++					    sip_parse_data_rx_info(sip,
++								   skb,
++								   ampdu_len->
++								   sublen -
++								   FCS_LEN,
++								   0,
++								   mac_ctrl,
++								   &pulled_len);
++					if (!rskb) {
++						ESSERT(0);
++						goto _exit;
++					}
++
++					if (likely
++					    (atomic_read
++					     (&sip->epub->wl.off) == 0)
++					    && (ampdu_len->substate == 0
++						|| ampdu_len->substate ==
++						RX_TKIPMIC_ERR
++						|| (sip->sendup_rpbm_pkt
++						    && ampdu_len->
++						    substate ==
++						    RX_RPBM_ERR))
++					    && (sip->rxabort_fixed
++						|| !have_rxabort)) {
++						if (!have_goodpkt) {
++							have_goodpkt =
++							    true;
++							memcpy(frame_head,
++							       rskb->data,
++							       16);
++							frame_head[1] &=
++							    ~0x80;
++							frame_buf_ttl = 3;
++						}
++#ifdef RX_CHECKSUM_TEST
++						esp_rx_checksum_test(rskb);
++#endif
++						local_bh_disable();
++						ieee80211_rx(sip->epub->hw,
++							     rskb);
++						local_bh_enable();
++
++					} else {
++						kfree_skb(rskb);
++					}
++				} else {
++					if (ampdu_len->substate ==
++					    RX_ABORT) {
++						u8 *a;
++						have_rxabort = true;
++						esp_sip_dbg(ESP_DBG_TRACE,
++							    "rx abort %d %d\n",
++							    frame_buf_ttl,
++							    pkt_num);
++						if (frame_buf_ttl
++						    && !sip->
++						    rxabort_fixed) {
++							struct
++							    esp_rx_ampdu_len
++							    *next_good_ampdu_len
++							    =
++							    ampdu_len + 1;
++							a = frame_head;
++							esp_sip_dbg
++							    (ESP_DBG_TRACE,
++							     "frame:%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
++							     a[0], a[1],
++							     a[2], a[3],
++							     a[4], a[5],
++							     a[6], a[7],
++							     a[8], a[9],
++							     a[10], a[11],
++							     a[12], a[13],
++							     a[14], a[15]);
++							while
++							    (!sip_ampdu_occupy_buf
++							     (sip,
++							      next_good_ampdu_len))
++							{
++								if (next_good_ampdu_len > ampdu_len + pkt_num - 1)
++									break;
++								next_good_ampdu_len++;
++
++							}
++							if (next_good_ampdu_len <= ampdu_len + pkt_num - 1) {
++								bool b0,
++								    b10,
++								    b11;
++								a = skb->
++								    data;
++								esp_sip_dbg
++								    (ESP_DBG_TRACE,
++								     "buf:%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
++								     a[0],
++								     a[1],
++								     a[2],
++								     a[3],
++								     a[4],
++								     a[5],
++								     a[6],
++								     a[7],
++								     a[8],
++								     a[9],
++								     a[10],
++								     a[11],
++								     a[12],
++								     a[13],
++								     a[14],
++								     a
++								     [15]);
++								b0 = memcmp
++								    (frame_head
++								     + 4,
++								     skb->
++								     data +
++								     4,
++								     12) ==
++								    0;
++								b10 =
++								    memcmp
++								    (frame_head
++								     + 10,
++								     skb->
++								     data,
++								     6) ==
++								    0;
++								b11 =
++								    memcpy
++								    (frame_head
++								     + 11,
++								     skb->
++								     data,
++								     5) ==
++								    0;
++								esp_sip_dbg
++								    (ESP_DBG_TRACE,
++								     "com %d %d %d\n",
++								     b0,
++								     b10,
++								     b11);
++								if (b0
++								    && !b10
++								    &&
++								    !b11) {
++									have_rxabort
++									    =
++									    false;
++									esp_sip_dbg
++									    (ESP_DBG_TRACE,
++									     "repair 0\n");
++								} else
++								    if (!b0
++									&&
++									b10
++									&&
++									!b11)
++								{
++									skb_push
++									    (skb,
++									     10);
++									memcpy
++									    (skb->
++									     data,
++									     frame_head,
++									     10);
++									have_rxabort
++									    =
++									    false;
++									pulled_len
++									    -=
++									    10;
++									esp_sip_dbg
++									    (ESP_DBG_TRACE,
++									     "repair 10\n");
++								} else
++								    if (!b0
++									&&
++									!b10
++									&&
++									b11)
++								{
++									skb_push
++									    (skb,
++									     11);
++									memcpy
++									    (skb->
++									     data,
++									     frame_head,
++									     11);
++									have_rxabort
++									    =
++									    false;
++									pulled_len
++									    -=
++									    11;
++									esp_sip_dbg
++									    (ESP_DBG_TRACE,
++									     "repair 11\n");
++								}
++							}
++						}
++					}
++					pkt_dropped++;
++					esp_sip_dbg(ESP_DBG_LOG,
++						    "%s ampdu dropped %d/%d\n",
++						    __func__, pkt_dropped,
++						    pkt_total);
++				}
++				pkt_num--;
++				ampdu_len++;
++			}
++			if (frame_buf_ttl)
++				frame_buf_ttl--;
++			skb_pull(skb, hdr->len - pulled_len);
++		} else {
++			esp_sip_dbg(ESP_DBG_ERROR, "%s %d unknown type\n",
++				    __func__, __LINE__);
++		}
++
++	      _move_on:
++		if (hdr->len < remains_len) {
++			remains_len -= hdr->len;
++		} else {
++			break;
++		}
++		bufptr += hdr->len;
++	}
++
++      _exit:
++#ifdef ESP_PREALLOC
++	esp_put_sip_skb(&skb);
++#else
++	kfree_skb(skb);
++#endif
++
++	return trigger_rxq;
++
++#undef DO_NOT_COPY
++#undef DO_COPY
++}
++
++static void _sip_rxq_process(struct esp_sip *sip)
++{
++	struct sk_buff *skb = NULL;
++	bool sendup = false;
++
++	while ((skb = skb_dequeue(&sip->rxq))) {
++		if (sip_rx_pkt_process(sip, skb))
++			sendup = true;
++	}
++	if (sendup) {
++		queue_work(sip->epub->esp_wkq, &sip->epub->sendup_work);
++	}
++
++	/* probably tx_credit is updated, try txq */
++	sip_trigger_txq_process(sip);
++}
++
++void sip_rxq_process(struct work_struct *work)
++{
++	struct esp_sip *sip =
++	    container_of(work, struct esp_sip, rx_process_work);
++	if (sip == NULL) {
++		ESSERT(0);
++		return;
++	}
++
++	if (unlikely(atomic_read(&sip->state) == SIP_SEND_INIT)) {
++		sip_send_chip_init(sip);
++		atomic_set(&sip->state, SIP_WAIT_BOOTUP);
++		return;
++	}
++
++	mutex_lock(&sip->rx_mtx);
++	_sip_rxq_process(sip);
++	mutex_unlock(&sip->rx_mtx);
++}
++
++static inline void sip_rx_pkt_enqueue(struct esp_sip *sip,
++				      struct sk_buff *skb)
++{
++	skb_queue_tail(&sip->rxq, skb);
++}
++
++static inline struct sk_buff *sip_rx_pkt_dequeue(struct esp_sip *sip)
++{
++	return skb_dequeue(&sip->rxq);
++}
++
++static u32 sip_rx_count = 0;
++void sip_debug_show(struct esp_sip *sip)
++{
++	esp_sip_dbg(ESP_DBG_ERROR, "txq left %d %d\n",
++		    skb_queue_len(&sip->epub->txq),
++		    atomic_read(&sip->tx_data_pkt_queued));
++	esp_sip_dbg(ESP_DBG_ERROR, "tx queues stop ? %d\n",
++		    atomic_read(&sip->epub->txq_stopped));
++	esp_sip_dbg(ESP_DBG_ERROR, "txq stop?  %d\n",
++		    test_bit(ESP_WL_FLAG_STOP_TXQ, &sip->epub->wl.flags));
++	esp_sip_dbg(ESP_DBG_ERROR, "tx credit %d\n",
++		    atomic_read(&sip->tx_credits));
++	esp_sip_dbg(ESP_DBG_ERROR, "rx collect %d\n", sip_rx_count);
++	sip_rx_count = 0;
++}
++
++int sip_rx(struct esp_pub *epub)
++{
++	struct sip_hdr *shdr = NULL;
++	struct esp_sip *sip = epub->sip;
++	int err = 0;
++	struct sk_buff *first_skb = NULL;
++	u8 *rx_buf = NULL;
++	u32 rx_blksz;
++	struct sk_buff *rx_skb = NULL;
++
++	u32 first_sz;
++
++	first_sz = sif_get_regs(epub)->config_w0;
++
++	if (likely(sif_get_ate_config() != 1)) {
++		do {
++			u8 raw_seq = sif_get_regs(epub)->intr_raw & 0xff;
++
++			if (raw_seq != sip->to_host_seq) {
++				if (raw_seq == sip->to_host_seq + 1) {	/* when last read pkt crc err, this situation may occur, but raw_seq mustn't < to_host_Seq */
++					sip->to_host_seq = raw_seq;
++					esp_dbg(ESP_DBG_TRACE,
++						"warn: to_host_seq reg 0x%02x, seq 0x%02x",
++						raw_seq, sip->to_host_seq);
++					break;
++				}
++				esp_dbg(ESP_DBG_ERROR,
++					"err: to_host_seq reg 0x%02x, seq 0x%02x",
++					raw_seq, sip->to_host_seq);
++				goto _err;
++			}
++		} while (0);
++	}
++	esp_sip_dbg(ESP_DBG_LOG, "%s enter\n", __func__);
++
++
++	/* first read one block out, if we luck enough, that's it
++	 *
++	 *  To make design as simple as possible, we allocate skb(s)
++	 *  separately for each sif read operation to avoid global
++	 *  read_buf_pointe access.  It coule be optimized late.
++	 */
++	rx_blksz = sif_get_blksz(epub);
++#ifdef ESP_PREALLOC
++	first_skb = esp_get_sip_skb(roundup(first_sz, rx_blksz));
++#else
++	first_skb =
++	    __dev_alloc_skb(roundup(first_sz, rx_blksz), GFP_KERNEL);
++#endif				/* ESP_PREALLOC */
++
++	if (first_skb == NULL) {
++		sif_unlock_bus(epub);
++		esp_sip_dbg(ESP_DBG_ERROR, "%s first no memory \n",
++			    __func__);
++		goto _err;
++	}
++
++	rx_buf = skb_put(first_skb, first_sz);
++	esp_sip_dbg(ESP_DBG_LOG, "%s rx_buf ptr %p, first_sz %d\n",
++		    __func__, rx_buf, first_sz);
++
++
++#ifdef USE_EXT_GPIO
++	do {
++		int err2 = 0;
++		u16 value = 0;
++		u16 intr_mask = ext_gpio_get_int_mask_reg();
++		if (!intr_mask)
++			break;
++		value = sif_get_regs(epub)->config_w3 & intr_mask;
++		if (value) {
++			err2 = sif_interrupt_target(epub, 6);
++			esp_sip_dbg(ESP_DBG, "write gpio\n");
++		}
++
++		if (!err2 && value) {
++			esp_sip_dbg(ESP_DBG_TRACE,
++				    "%s intr_mask[0x%04x] value[0x%04x]\n",
++				    __func__, intr_mask, value);
++			ext_gpio_int_process(value);
++		}
++	} while (0);
++#endif
++
++	err =
++	    esp_common_read(epub, rx_buf, first_sz, ESP_SIF_NOSYNC, false);
++	sip_rx_count++;
++	if (unlikely(err)) {
++		esp_dbg(ESP_DBG_ERROR, " %s first read err %d %d\n",
++			__func__, err, sif_get_regs(epub)->config_w0);
++#ifdef ESP_PREALLOC
++		esp_put_sip_skb(&first_skb);
++#else
++		kfree_skb(first_skb);
++#endif				/* ESP_PREALLOC */
++		sif_unlock_bus(epub);
++		goto _err;
++	}
++
++	shdr = (struct sip_hdr *) rx_buf;
++	if (SIP_HDR_IS_CTRL(shdr) && (shdr->c_evtid == SIP_EVT_SLEEP)) {
++		atomic_set(&sip->epub->ps.state, ESP_PM_ON);
++		esp_dbg(ESP_DBG_TRACE, "s\n");
++	}
++
++	if (likely(sif_get_ate_config() != 1)) {
++		sip->to_host_seq++;
++	}
++
++	if ((shdr->len & 3) != 0) {
++		esp_sip_dbg(ESP_DBG_ERROR, "%s shdr->len[%d] error\n",
++			    __func__, shdr->len);
++#ifdef ESP_PREALLOC
++		esp_put_sip_skb(&first_skb);
++#else
++		kfree_skb(first_skb);
++#endif				/* ESP_PREALLOC */
++		sif_unlock_bus(epub);
++		err = -EIO;
++		goto _err;
++	}
++	if (shdr->len != first_sz) {
++		esp_sip_dbg(ESP_DBG_ERROR,
++			    "%s shdr->len[%d]  first_size[%d] error\n",
++			    __func__, shdr->len, first_sz);
++#ifdef ESP_PREALLOC
++		esp_put_sip_skb(&first_skb);
++#else
++		kfree_skb(first_skb);
++#endif				/* ESP_PREALLOC */
++		sif_unlock_bus(epub);
++		err = -EIO;
++		goto _err;
++	} else {
++		sif_unlock_bus(epub);
++		skb_trim(first_skb, shdr->len);
++		esp_dbg(ESP_DBG_TRACE, " %s first_skb only\n", __func__);
++
++		rx_skb = first_skb;
++	}
++
++	if (atomic_read(&sip->state) == SIP_STOP) {
++#ifdef ESP_PREALLOC
++		esp_put_sip_skb(&rx_skb);
++#else
++		kfree_skb(rx_skb);
++#endif				/* ESP_PREALLOC */
++		esp_sip_dbg(ESP_DBG_ERROR, "%s when sip stopped\n",
++			    __func__);
++		return 0;
++	}
++
++	sip_rx_pkt_enqueue(sip, rx_skb);
++	queue_work(sip->epub->esp_wkq, &sip->rx_process_work);
++
++      _err:
++	return err;
++}
++
++int sip_post_init(struct esp_sip *sip, struct sip_evt_bootup2 *bevt)
++{
++	struct esp_pub *epub;
++
++	u8 mac_id = bevt->mac_addr[0];
++	int mac_index = 0;
++	int i = 0;
++
++	if (sip == NULL) {
++		ESSERT(0);
++		return -EINVAL;
++	}
++
++	epub = sip->epub;
++
++
++	sip->tx_aggr_write_ptr = sip->tx_aggr_buf;
++
++	sip->tx_blksz = bevt->tx_blksz;
++	sip->rx_blksz = bevt->rx_blksz;
++	sip->credit_to_reserve = bevt->credit_to_reserve;
++
++	sip->dump_rpbm_err = (bevt->options & SIP_DUMP_RPBM_ERR);
++	sip->rxabort_fixed = (bevt->options & SIP_RXABORT_FIXED);
++	sip->support_bgscan = (bevt->options & SIP_SUPPORT_BGSCAN);
++
++	sip->sendup_rpbm_pkt = sip->dump_rpbm_err && false;
++
++	/* print out MAC addr... */
++	memcpy(epub->mac_addr, bevt->mac_addr, ETH_ALEN);
++	for (i = 0;
++	     i <
++	     sizeof(esp_mac_prefix_table) / sizeof(struct esp_mac_prefix);
++	     i++) {
++		if (esp_mac_prefix_table[i].mac_index == mac_id) {
++			mac_index = i;
++			break;
++		}
++	}
++
++	epub->mac_addr[0] =
++	    esp_mac_prefix_table[mac_index].mac_addr_prefix[0];
++	epub->mac_addr[1] =
++	    esp_mac_prefix_table[mac_index].mac_addr_prefix[1];
++	epub->mac_addr[2] =
++	    esp_mac_prefix_table[mac_index].mac_addr_prefix[2];
++
++#ifdef SELF_MAC
++	epub->mac_addr[0] = 0xff;
++	epub->mac_addr[1] = 0xff;
++	epub->mac_addr[2] = 0xff;
++#endif
++	atomic_set(&sip->noise_floor, bevt->noise_floor);
++
++	sip_recalc_credit_init(sip);
++
++	esp_sip_dbg(ESP_DBG_TRACE,
++		    "%s tx_blksz %d rx_blksz %d mac addr %pM\n", __func__,
++		    sip->tx_blksz, sip->rx_blksz, epub->mac_addr);
++
++	return 0;
++}
++
++/* write pkts in aggr buf to target memory */
++static void sip_write_pkts(struct esp_sip *sip, int pm_state)
++{
++	int tx_aggr_len = 0;
++	struct sip_hdr *first_shdr = NULL;
++	int err = 0;
++
++	tx_aggr_len = sip->tx_aggr_write_ptr - sip->tx_aggr_buf;
++	if (tx_aggr_len < sizeof(struct sip_hdr)) {
++		printk("%s tx_aggr_len %d \n", __func__, tx_aggr_len);
++		ESSERT(0);
++		return;
++	}
++	if ((tx_aggr_len & 0x3) != 0) {
++		ESSERT(0);
++		return;
++	}
++
++	first_shdr = (struct sip_hdr *) sip->tx_aggr_buf;
++
++	if (atomic_read(&sip->tx_credits) <= SIP_CREDITS_LOW_THRESHOLD) {
++		first_shdr->fc[1] |= SIP_HDR_F_NEED_CRDT_RPT;
++	}
++
++	/* still use lock bus instead of sif_lldesc_write_sync since we want to protect several global varibles assignments */
++	sif_lock_bus(sip->epub);
++
++	err =
++	    esp_common_write(sip->epub, sip->tx_aggr_buf, tx_aggr_len,
++			     ESP_SIF_NOSYNC);
++
++	sip->tx_aggr_write_ptr = sip->tx_aggr_buf;
++	sip->tx_tot_len = 0;
++
++	sif_unlock_bus(sip->epub);
++
++	if (err)
++		esp_sip_dbg(ESP_DBG_ERROR, "func %s err!!!!!!!!!: %d\n",
++			    __func__, err);
++
++}
++
++/* setup sip header and tx info, copy pkt into aggr buf */
++static int sip_pack_pkt(struct esp_sip *sip, struct sk_buff *skb,
++			int *pm_state)
++{
++	struct ieee80211_tx_info *itx_info;
++	struct sip_hdr *shdr;
++	u32 tx_len = 0, offset = 0;
++	bool is_data = true;
++
++	itx_info = IEEE80211_SKB_CB(skb);
++
++	if (itx_info->flags == 0xffffffff) {
++		shdr = (struct sip_hdr *) skb->data;
++		is_data = false;
++		tx_len = skb->len;
++	} else {
++		struct ieee80211_hdr *wh =
++		    (struct ieee80211_hdr *) skb->data;
++		struct esp_vif *evif =
++		    (struct esp_vif *) itx_info->control.vif->drv_priv;
++		u8 sta_index;
++		struct esp_node *node;
++		/* update sip header */
++		shdr = (struct sip_hdr *) sip->tx_aggr_write_ptr;
++
++		shdr->fc[0] = 0;
++		shdr->fc[1] = 0;
++
++		if ((itx_info->flags & IEEE80211_TX_CTL_AMPDU)
++		    && (true || esp_is_ip_pkt(skb)))
++			SIP_HDR_SET_TYPE(shdr->fc[0], SIP_DATA_AMPDU);
++		else
++			SIP_HDR_SET_TYPE(shdr->fc[0], SIP_DATA);
++
++		if (evif->epub == NULL) {
++			sip_tx_status_report(sip, skb, itx_info, false);
++			atomic_dec(&sip->tx_data_pkt_queued);
++			return -EINVAL;
++		}
++
++		/* make room for encrypted pkt */
++		if (itx_info->control.hw_key) {
++			int alg =
++			    esp_cipher2alg(itx_info->control.hw_key->
++					   cipher);
++			if (unlikely(alg == -1)) {
++				sip_tx_status_report(sip, skb, itx_info,
++						     false);
++				atomic_dec(&sip->tx_data_pkt_queued);
++				return -1;
++			} else {
++				shdr->d_enc_flag = alg + 1;
++			}
++
++			shdr->d_hw_kid =
++			    itx_info->control.hw_key->hw_key_idx | (evif->
++								    index
++								    << 7);
++		} else {
++			shdr->d_enc_flag = 0;
++			shdr->d_hw_kid = (evif->index << 7 | evif->index);
++		}
++
++		/* update sip tx info */
++		node = esp_get_node_by_addr(sip->epub, wh->addr1);
++		if (node != NULL)
++			sta_index = node->index;
++		else
++			sta_index = ESP_PUB_MAX_STA + 1;
++		SIP_HDR_SET_IFIDX(shdr->fc[0],
++				  evif->index << 3 | sta_index);
++		shdr->d_p2p = itx_info->control.vif->p2p;
++		if (evif->index == 1)
++			shdr->d_p2p = 1;
++		shdr->d_ac = skb_get_queue_mapping(skb);
++		shdr->d_tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK;
++		wh = (struct ieee80211_hdr *) skb->data;
++		if (ieee80211_is_mgmt(wh->frame_control)) {
++			/* addba/delba/bar may use different tid/ac */
++			if (shdr->d_ac == WME_AC_VO) {
++				shdr->d_tid = 7;
++			}
++			if (ieee80211_is_beacon(wh->frame_control)) {
++				shdr->d_tid = 8;
++				shdr->d_ac = 4;
++			}
++		}
++		if (check_ac_tid(skb->data, shdr->d_ac, shdr->d_tid)) {
++			shdr->d_ac = WME_AC_BE;
++			shdr->d_tid = 0;
++		}
++
++
++		/* make sure data is start at 4 bytes aligned addr. */
++		offset = roundup(sizeof(struct sip_hdr), 4);
++
++#ifdef HOST_RC
++		esp_sip_dbg(ESP_DBG_TRACE, "%s offset0 %d \n", __func__,
++			    offset);
++		memcpy(sip->tx_aggr_write_ptr + offset,
++		       (void *) &itx_info->control,
++		       sizeof(struct sip_tx_rc));
++
++		offset += roundup(sizeof(struct sip_tx_rc), 4);
++		esp_show_tx_rates(&itx_info->control.rates[0]);
++
++#endif				/* HOST_RC */
++
++		if (SIP_HDR_IS_AMPDU(shdr)) {
++			memset(sip->tx_aggr_write_ptr + offset, 0,
++			       sizeof(struct esp_tx_ampdu_entry));
++			offset +=
++			    roundup(sizeof(struct esp_tx_ampdu_entry), 4);
++		}
++
++		tx_len = offset + skb->len;
++		shdr->len = tx_len;	/* actual len */
++
++		esp_sip_dbg(ESP_DBG_TRACE,
++			    "%s offset %d skblen %d txlen %d\n", __func__,
++			    offset, skb->len, tx_len);
++
++	}
++
++	shdr->seq = sip->txseq++;
++	//esp_sip_dbg(ESP_DBG_ERROR, "%s seq %u, %u %u\n", __func__, shdr->seq, SIP_HDR_GET_TYPE(shdr->fc[0]),shdr->c_cmdid);
++
++	/* copy skb to aggr buf */
++	memcpy(sip->tx_aggr_write_ptr + offset, skb->data, skb->len);
++
++	if (is_data) {
++		spin_lock_bh(&sip->epub->tx_lock);
++		sip->txdataseq = shdr->seq;
++		spin_unlock_bh(&sip->epub->tx_lock);
++		/* fake a tx_status and report to mac80211 stack to speed up tx, may affect
++		 *  1) rate control (now it's all in target, so should be OK)
++		 *  2) ps mode, mac80211 want to check ACK of ps/nulldata to see if AP is awake
++		 *  3) BAR, mac80211 do BAR by checking ACK
++		 */
++		/*
++		 *  XXX: need to adjust for 11n, e.g. report tx_status according to BA received in target
++		 *
++		 */
++		sip_tx_status_report(sip, skb, itx_info, true);
++		atomic_dec(&sip->tx_data_pkt_queued);
++
++		STRACE_TX_DATA_INC();
++	} else {
++		/* check pm state here */
++
++		/* no need to hold ctrl skb */
++		sip_free_ctrl_skbuff(sip, skb);
++		STRACE_TX_CMD_INC();
++	}
++
++	/* TBD: roundup here or whole aggr-buf */
++	tx_len = roundup(tx_len, sip->tx_blksz);
++
++	sip->tx_aggr_write_ptr += tx_len;
++	sip->tx_tot_len += tx_len;
++
++	return 0;
++}
++
++#ifdef HOST_RC
++static void sip_set_tx_rate_status(struct sip_rc_status *rcstatus,
++				   struct ieee80211_tx_rate *irates)
++{
++	int i;
++	u8 shift = 0;
++	u32 cnt = 0;
++
++	for (i = 0; i < IEEE80211_TX_MAX_RATES; i++) {
++		if (rcstatus->rc_map & BIT(i)) {
++			shift = i << 2;
++			cnt =
++			    (rcstatus->
++			     rc_cnt_store >> shift) & RC_CNT_MASK;
++			irates[i].idx = i;
++			irates[i].count = (u8) cnt;
++		} else {
++			irates[i].idx = -1;
++			irates[i].count = 0;
++		}
++	}
++
++	esp_show_rcstatus(rcstatus);
++	esp_show_tx_rates(irates);
++}
++#endif				/* HOST_RC */
++
++static void sip_tx_status_report(struct esp_sip *sip, struct sk_buff *skb,
++				 struct ieee80211_tx_info *tx_info,
++				 bool success)
++{
++	if (!(tx_info->flags & IEEE80211_TX_CTL_AMPDU)) {
++		if (likely(success))
++			tx_info->flags |= IEEE80211_TX_STAT_ACK;
++		else
++			tx_info->flags &= ~IEEE80211_TX_STAT_ACK;
++
++		/* manipulate rate status... */
++		tx_info->status.rates[0].idx = 11;
++		tx_info->status.rates[0].count = 1;
++		tx_info->status.rates[0].flags = 0;
++		tx_info->status.rates[1].idx = -1;
++
++	} else {
++		tx_info->flags |=
++		    IEEE80211_TX_STAT_AMPDU | IEEE80211_TX_STAT_ACK;
++		tx_info->status.ampdu_len = 1;
++		tx_info->status.ampdu_ack_len = 1;
++
++		/* manipulate rate status... */
++		tx_info->status.rates[0].idx = 7;
++		tx_info->status.rates[0].count = 1;
++		tx_info->status.rates[0].flags =
++		    IEEE80211_TX_RC_MCS | IEEE80211_TX_RC_SHORT_GI;
++		tx_info->status.rates[1].idx = -1;
++
++	}
++
++	if (tx_info->flags & IEEE80211_TX_STAT_AMPDU)
++		esp_sip_dbg(ESP_DBG_TRACE, "%s ampdu status! \n",
++			    __func__);
++
++	if (!mod_support_no_txampdu() &&
++	    cfg80211_get_chandef_type(&sip->epub->hw->conf.chandef) !=
++	    NL80211_CHAN_NO_HT) {
++		struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
++		struct ieee80211_hdr *wh =
++		    (struct ieee80211_hdr *) skb->data;
++		if (ieee80211_is_data_qos(wh->frame_control)) {
++			if (!(tx_info->flags & IEEE80211_TX_CTL_AMPDU)) {
++				u8 tidno =
++				    ieee80211_get_qos_ctl(wh)[0] &
++				    IEEE80211_QOS_CTL_TID_MASK;
++				struct esp_node *node;
++				struct esp_tx_tid *tid;
++				struct ieee80211_sta *sta;
++
++				node =
++				    esp_get_node_by_addr(sip->epub,
++							 wh->addr1);
++				if (node == NULL)
++					goto _exit;
++				if (node->sta == NULL)
++					goto _exit;
++				sta = node->sta;
++				tid = &node->tid[tidno];
++				spin_lock_bh(&sip->epub->tx_ampdu_lock);
++				//start session
++				if (tid == NULL) {
++					spin_unlock_bh(&sip->epub->
++						       tx_ampdu_lock);
++					ESSERT(0);
++					goto _exit;
++				}
++				if ((tid->state == ESP_TID_STATE_INIT) &&
++				    (TID_TO_AC(tidno) != WME_AC_VO)
++				    && tid->cnt >= 10) {
++					tid->state = ESP_TID_STATE_TRIGGER;
++					esp_sip_dbg(ESP_DBG_ERROR,
++						    "start tx ba session,addr:%pM,tid:%u\n",
++						    wh->addr1, tidno);
++					spin_unlock_bh(&sip->epub->
++						       tx_ampdu_lock);
++					ieee80211_start_tx_ba_session(sta,
++								      tidno,
++								      0);
++				} else {
++					if (tid->state ==
++					    ESP_TID_STATE_INIT)
++						tid->cnt++;
++					else
++						tid->cnt = 0;
++					spin_unlock_bh(&sip->epub->
++						       tx_ampdu_lock);
++				}
++			}
++		}
++	}
++      _exit:
++	ieee80211_tx_status_skb(sip->epub->hw, skb);
++}
++
++/*
++ *  NB: this routine should be locked when calling
++ */
++void sip_txq_process(struct esp_pub *epub)
++{
++	struct sk_buff *skb;
++	struct esp_sip *sip = epub->sip;
++	u32 pkt_len = 0, tx_len = 0;
++	int blknum = 0;
++	bool queued_back = false;
++	bool out_of_credits = false;
++	struct ieee80211_tx_info *itx_info;
++	int pm_state = 0;
++
++	while ((skb = skb_dequeue(&epub->txq))) {
++
++		/* cmd skb->len does not include sip_hdr too */
++		pkt_len = skb->len;
++		itx_info = IEEE80211_SKB_CB(skb);
++		if (itx_info->flags != 0xffffffff) {
++			pkt_len += roundup(sizeof(struct sip_hdr), 4);
++			if ((itx_info->flags & IEEE80211_TX_CTL_AMPDU)
++			    && (true || esp_is_ip_pkt(skb)))
++				pkt_len +=
++				    roundup(sizeof
++					    (struct esp_tx_ampdu_entry),
++					    4);
++		}
++
++		/* current design simply requires every sip_hdr must be at the begin of mblk, that definitely
++		 * need to be optimized, e.g. calulate remain length in the previous mblk, if it larger than
++		 * certain threshold (e.g, whole pkt or > 50% of pkt or 2 x sizeof(struct sip_hdr), append pkt
++		 * to the previous mblk.  This might be done in sip_pack_pkt()
++		 */
++		pkt_len = roundup(pkt_len, sip->tx_blksz);
++		blknum = pkt_len / sip->tx_blksz;
++		esp_dbg(ESP_DBG_TRACE,
++			"%s skb_len %d pkt_len %d blknum %d\n", __func__,
++			skb->len, pkt_len, blknum);
++
++		if (unlikely(atomic_read(&sip->credit_status) == RECALC_CREDIT_ENABLE)) {	/* need recalc credit */
++			struct sip_hdr *hdr = (struct sip_hdr *) skb->data;
++			itx_info = IEEE80211_SKB_CB(skb);
++			if (!(itx_info->flags == 0xffffffff && SIP_HDR_GET_TYPE(hdr->fc[0]) == SIP_CTRL && hdr->c_cmdid == SIP_CMD_RECALC_CREDIT && blknum <= atomic_read(&sip->tx_credits) - sip->credit_to_reserve)) {	/* except cmd recalc credit */
++				esp_dbg(ESP_DBG_ERROR,
++					"%s recalc credits!\n", __func__);
++				STRACE_TX_OUT_OF_CREDIT_INC();
++				queued_back = true;
++				out_of_credits = true;
++				break;
++			}
++		} else {	/* normal situation */
++			if (unlikely
++			    (blknum >
++			     (atomic_read(&sip->tx_credits) -
++			      sip->credit_to_reserve -
++			      SIP_CTRL_CREDIT_RESERVE))) {
++				itx_info = IEEE80211_SKB_CB(skb);
++				if (itx_info->flags == 0xffffffff) {	/* priv ctrl pkt */
++					if (blknum >
++					    atomic_read(&sip->tx_credits) -
++					    sip->credit_to_reserve) {
++						esp_dbg(ESP_DBG_TRACE,
++							"%s cmd pkt out of credits!\n",
++							__func__);
++						STRACE_TX_OUT_OF_CREDIT_INC
++						    ();
++						queued_back = true;
++						out_of_credits = true;
++						break;
++					}
++				} else {
++					esp_dbg(ESP_DBG_TRACE,
++						"%s out of credits!\n",
++						__func__);
++					STRACE_TX_OUT_OF_CREDIT_INC();
++					queued_back = true;
++					out_of_credits = true;
++					break;
++				}
++			}
++		}
++		tx_len += pkt_len;
++		if (tx_len >= SIP_TX_AGGR_BUF_SIZE) {
++			/* do we need to have limitation likemax 8 pkts in a row? */
++			esp_dbg(ESP_DBG_TRACE,
++				"%s too much pkts in one shot!\n",
++				__func__);
++			STRACE_TX_ONE_SHOT_INC();
++			tx_len -= pkt_len;
++			queued_back = true;
++			break;
++		}
++
++		if (sip_pack_pkt(sip, skb, &pm_state) != 0) {
++			/* wrong pkt, won't send to target */
++			tx_len -= pkt_len;
++			continue;
++		}
++
++		esp_sip_dbg(ESP_DBG_TRACE,
++			    "%s:before sub, credits is %d\n", __func__,
++			    atomic_read(&sip->tx_credits));
++		atomic_sub(blknum, &sip->tx_credits);
++		esp_sip_dbg(ESP_DBG_TRACE,
++			    "%s:after sub %d,credits remains %d\n",
++			    __func__, blknum,
++			    atomic_read(&sip->tx_credits));
++
++	}
++
++	if (queued_back) {
++		skb_queue_head(&epub->txq, skb);
++	}
++
++	if (atomic_read(&sip->state) == SIP_STOP
++#ifdef HOST_RESET_BUG
++	    || atomic_read(&epub->wl.off) == 1
++#endif
++	    ) {
++		queued_back = 1;
++		tx_len = 0;
++		sip_after_write_pkts(sip);
++	}
++
++	if (tx_len) {
++
++		sip_write_pkts(sip, pm_state);
++
++		sip_after_write_pkts(sip);
++	}
++
++	if (queued_back && !out_of_credits) {
++
++		/* skb pending, do async process again */
++		sip_trigger_txq_process(sip);
++	}
++}
++
++static void sip_after_write_pkts(struct esp_sip *sip)
++{
++
++}
++
++#ifndef NO_WMM_DUMMY
++static struct esp_80211_wmm_param_element esp_wmm_param = {
++	.oui = {0x00, 0x50, 0xf2},
++	.oui_type = 0x02,
++	.oui_subtype = 0x01,
++	.version = 0x01,
++	.qos_info = 0x00,
++	.reserved = 0x00,
++	.ac = {
++	       {
++		.aci_aifsn = 0x03,
++		.cw = 0xa4,
++		.txop_limit = 0x0000,
++		},
++	       {
++		.aci_aifsn = 0x27,
++		.cw = 0xa4,
++		.txop_limit = 0x0000,
++		},
++	       {
++		.aci_aifsn = 0x42,
++		.cw = 0x43,
++		.txop_limit = 0x005e,
++		},
++	       {
++		.aci_aifsn = 0x62,
++		.cw = 0x32,
++		.txop_limit = 0x002f,
++		},
++	       },
++};
++
++static int esp_add_wmm(struct sk_buff *skb)
++{
++	u8 *p;
++	int flag = 0;
++	int remain_len;
++	int base_len;
++	int len;
++	struct ieee80211_mgmt *mgmt;
++	struct ieee80211_hdr *wh;
++
++	if (!skb)
++		return -1;
++
++	wh = (struct ieee80211_hdr *) skb->data;
++	mgmt = (struct ieee80211_mgmt *) ((u8 *) skb->data);
++
++	if (ieee80211_is_assoc_resp(wh->frame_control)) {
++		p = mgmt->u.assoc_resp.variable;
++		base_len =
++		    (u8 *) mgmt->u.assoc_resp.variable - (u8 *) mgmt;
++	} else if (ieee80211_is_reassoc_resp(wh->frame_control)) {
++		p = mgmt->u.reassoc_resp.variable;
++		base_len =
++		    (u8 *) mgmt->u.reassoc_resp.variable - (u8 *) mgmt;
++	} else if (ieee80211_is_probe_resp(wh->frame_control)) {
++		p = mgmt->u.probe_resp.variable;
++		base_len =
++		    (u8 *) mgmt->u.probe_resp.variable - (u8 *) mgmt;
++	} else if (ieee80211_is_beacon(wh->frame_control)) {
++		p = mgmt->u.beacon.variable;
++		base_len = (u8 *) mgmt->u.beacon.variable - (u8 *) mgmt;
++	} else
++		return 1;
++
++
++	remain_len = skb->len - base_len;
++
++	while (remain_len > 0) {
++		if (*p == 0xdd && *(p + 5) == 0x02)	//wmm type
++			return 0;
++		else if (*p == 0x2d)	//has ht cap
++			flag = 1;
++
++		len = *(++p);
++		p += (len + 1);
++		remain_len -= (len + 2);
++	}
++
++	if (remain_len < 0) {
++		esp_dbg(ESP_DBG_TRACE,
++			"%s remain_len %d, skb->len %d, base_len %d, flag %d",
++			__func__, remain_len, skb->len, base_len, flag);
++		return -2;
++	}
++
++	if (flag == 1) {
++		skb_put(skb, 2 + sizeof(esp_wmm_param));
++
++		memset(p, 0xdd, sizeof(u8));
++		memset(p + 1, sizeof(esp_wmm_param), sizeof(u8));
++		memcpy(p + 2, &esp_wmm_param, sizeof(esp_wmm_param));
++
++		esp_dbg(ESP_DBG_TRACE, "esp_wmm_param");
++	}
++
++	return 0;
++}
++#endif				/* NO_WMM_DUMMY */
++
++/*  parse mac_rx_ctrl and return length */
++static int sip_parse_mac_rx_info(struct esp_sip *sip,
++				 struct esp_mac_rx_ctrl *mac_ctrl,
++				 struct sk_buff *skb)
++{
++	struct ieee80211_rx_status *rx_status = NULL;
++	struct ieee80211_hdr *hdr;
++
++	rx_status = IEEE80211_SKB_RXCB(skb);
++	rx_status->freq = esp_ieee2mhz(mac_ctrl->channel);
++
++	rx_status->signal = mac_ctrl->rssi + mac_ctrl->noise_floor;	/* snr actually, need to offset noise floor e.g. -85 */
++
++	hdr = (struct ieee80211_hdr *) skb->data;
++	if (mac_ctrl->damatch0 == 1 && mac_ctrl->bssidmatch0 == 1	/*match bssid and da, but beacon package contain other bssid */
++	    && strncmp(hdr->addr2, sip->epub->wl.bssid, ETH_ALEN) == 0) {	/* force match addr2 */
++		if (++signal_loop >= SIGNAL_COUNT) {
++			avg_signal += rx_status->signal;
++			avg_signal /= SIGNAL_COUNT;
++			old_signal = rx_status->signal = (avg_signal + 5);
++			signal_loop = 0;
++			avg_signal = 0;
++		} else {
++			avg_signal += rx_status->signal;
++			rx_status->signal = old_signal;
++		}
++	}
++
++	rx_status->antenna = 0;	/* one antenna for now */
++	rx_status->band = NL80211_BAND_2GHZ;
++	rx_status->flag = RX_FLAG_DECRYPTED | RX_FLAG_MMIC_STRIPPED;
++	if (mac_ctrl->sig_mode) {
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 12, 0))
++		rx_status->encoding = RX_ENC_HT;
++#else
++		rx_status->flag |= RX_FLAG_HT;
++#endif
++		rx_status->rate_idx = mac_ctrl->MCS;
++		if (mac_ctrl->SGI)
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 12, 0))
++			rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
++#else
++			rx_status->flag |= RX_FLAG_SHORT_GI;
++#endif
++	} else {
++		rx_status->rate_idx = esp_wmac_rate2idx(mac_ctrl->rate);
++	}
++	if (mac_ctrl->rxend_state == RX_FCS_ERR)
++		rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
++
++	/* Mic error frame flag */
++	if (mac_ctrl->rxend_state == RX_TKIPMIC_ERR
++	    || mac_ctrl->rxend_state == RX_CCMPMIC_ERR) {
++		if (atomic_read(&sip->epub->wl.tkip_key_set) == 1) {
++			rx_status->flag |= RX_FLAG_MMIC_ERROR;
++			atomic_set(&sip->epub->wl.tkip_key_set, 0);
++			printk("mic err\n");
++		} else {
++			printk("mic err discard\n");
++		}
++	}
++	//esp_dbg(ESP_DBG_LOG, "%s freq: %u; signal: %d;  rate_idx %d; flag: %d \n", __func__, rx_status->freq, rx_status->signal, rx_status->rate_idx, rx_status->flag);
++
++	do {
++		struct ieee80211_hdr *wh =
++		    (struct ieee80211_hdr *) ((u8 *) skb->data);
++
++#ifndef NO_WMM_DUMMY
++		if (ieee80211_is_mgmt(wh->frame_control))
++			esp_add_wmm(skb);
++#endif
++
++		/* some kernel e.g. 3.0.8 wrongly handles non-encrypted pkt like eapol */
++		if (ieee80211_is_data(wh->frame_control)) {
++			if (!ieee80211_has_protected(wh->frame_control)) {
++				esp_sip_dbg(ESP_DBG_TRACE,
++					    "%s kiv_war, add iv_stripped flag \n",
++					    __func__);
++				rx_status->flag |= RX_FLAG_IV_STRIPPED;
++			} else {
++				if ((atomic_read(&sip->epub->wl.ptk_cnt) ==
++				     0 && !(wh->addr1[0] & 0x1))
++				    || (atomic_read(&sip->epub->wl.gtk_cnt)
++					== 0 && (wh->addr1[0] & 0x1))) {
++					esp_dbg(ESP_DBG_TRACE,
++						"%s ==kiv_war, got bogus enc pkt==\n",
++						__func__);
++					rx_status->flag |=
++					    RX_FLAG_IV_STRIPPED;
++					//show_buf(skb->data, 32);
++				}
++
++				esp_sip_dbg(ESP_DBG_TRACE,
++					    "%s kiv_war, got enc pkt \n",
++					    __func__);
++			}
++		}
++	} while (0);
++
++	return 0;
++}
++
++static struct esp_mac_rx_ctrl *sip_parse_normal_mac_ctrl(struct sk_buff
++							 *skb,
++							 int *pkt_len_enc,
++							 int *buf_len,
++							 int *pulled_len)
++{
++	struct esp_mac_rx_ctrl *mac_ctrl = NULL;
++	struct sip_hdr *hdr = (struct sip_hdr *) skb->data;
++	int len_in_hdr = hdr->len;
++
++	ESSERT(skb != NULL);
++	ESSERT(skb->len > SIP_MIN_DATA_PKT_LEN);
++
++	skb_pull(skb, sizeof(struct sip_hdr));
++	*pulled_len += sizeof(struct sip_hdr);
++	mac_ctrl = (struct esp_mac_rx_ctrl *) skb->data;
++	if (!mac_ctrl->Aggregation) {
++		ESSERT(pkt_len_enc != NULL);
++		ESSERT(buf_len != NULL);
++		*pkt_len_enc =
++		    (mac_ctrl->sig_mode ? mac_ctrl->HT_length : mac_ctrl->
++		     legacy_length) - FCS_LEN;
++		*buf_len =
++		    len_in_hdr - sizeof(struct sip_hdr) -
++		    sizeof(struct esp_mac_rx_ctrl);
++	}
++	skb_pull(skb, sizeof(struct esp_mac_rx_ctrl));
++	*pulled_len += sizeof(struct esp_mac_rx_ctrl);
++
++	return mac_ctrl;
++}
++
++/*
++ * for one MPDU (including subframe in AMPDU)
++ *
++ */
++static struct sk_buff *sip_parse_data_rx_info(struct esp_sip *sip,
++					      struct sk_buff *skb,
++					      int pkt_len_enc, int buf_len,
++					      struct esp_mac_rx_ctrl
++					      *mac_ctrl, int *pulled_len)
++{
++	/*
++	 *   | mac_rx_ctrl | real_data_payload | ampdu_entries |
++	 */
++	//without enc
++	int pkt_len = 0;
++	struct sk_buff *rskb = NULL;
++	int ret;
++
++	if (mac_ctrl->Aggregation) {
++		struct ieee80211_hdr *wh =
++		    (struct ieee80211_hdr *) skb->data;
++		pkt_len = pkt_len_enc;
++		if (ieee80211_has_protected(wh->frame_control))	//ampdu, it is CCMP enc
++			pkt_len -= 8;
++		buf_len = roundup(pkt_len, 4);
++	} else
++		pkt_len = buf_len - 3 + ((pkt_len_enc - 1) & 0x3);
++	esp_dbg(ESP_DBG_TRACE,
++		"%s pkt_len %u, pkt_len_enc %u!, delta %d \n", __func__,
++		pkt_len, pkt_len_enc, pkt_len_enc - pkt_len);
++	do {
++#ifndef NO_WMM_DUMMY
++		rskb =
++		    __dev_alloc_skb(pkt_len_enc + sizeof(esp_wmm_param) +
++				    2, GFP_ATOMIC);
++#else
++		rskb = __dev_alloc_skb(pkt_len_enc, GFP_ATOMIC);
++#endif				/* NO_WMM_DUMMY */
++		if (unlikely(rskb == NULL)) {
++			esp_sip_dbg(ESP_DBG_ERROR, "%s no mem for rskb\n",
++				    __func__);
++			return NULL;
++		}
++		skb_put(rskb, pkt_len_enc);
++	} while (0);
++
++	do {
++		memcpy(rskb->data, skb->data, pkt_len);
++		if (pkt_len_enc > pkt_len) {
++			memset(rskb->data + pkt_len, 0,
++			       pkt_len_enc - pkt_len);
++		}
++		/* strip out current pkt, move to the next one */
++		skb_pull(skb, buf_len);
++		*pulled_len += buf_len;
++	} while (0);
++
++	ret = sip_parse_mac_rx_info(sip, mac_ctrl, rskb);
++	if (ret == -1 && !mac_ctrl->Aggregation) {
++		kfree_skb(rskb);
++		return NULL;
++	}
++
++	esp_dbg(ESP_DBG_LOG,
++		"%s after pull headers, skb->len %d rskb->len %d \n",
++		__func__, skb->len, rskb->len);
++
++	return rskb;
++}
++
++struct esp_sip *sip_attach(struct esp_pub *epub)
++{
++	struct esp_sip *sip = NULL;
++	struct sip_pkt *pkt = NULL;
++	int i;
++#ifndef ESP_PREALLOC
++	int po = 0;
++#endif
++
++	sip = kzalloc(sizeof(struct esp_sip), GFP_KERNEL);
++	if (sip == NULL) {
++		esp_dbg(ESP_DBG_ERROR, "no mem for sip! \n");
++		goto _err_sip;
++	}
++#ifdef ESP_PREALLOC
++	sip->tx_aggr_buf = (u8 *) esp_get_tx_aggr_buf();
++#else
++	po = get_order(SIP_TX_AGGR_BUF_SIZE);
++	sip->tx_aggr_buf = (u8 *) __get_free_pages(GFP_ATOMIC, po);
++#endif
++	if (sip->tx_aggr_buf == NULL) {
++		esp_dbg(ESP_DBG_ERROR, "no mem for tx_aggr_buf! \n");
++		goto _err_aggr;
++	}
++
++	spin_lock_init(&sip->lock);
++
++	INIT_LIST_HEAD(&sip->free_ctrl_txbuf);
++	INIT_LIST_HEAD(&sip->free_ctrl_rxbuf);
++
++	for (i = 0; i < SIP_CTRL_BUF_N; i++) {
++		pkt = kzalloc(sizeof(struct sip_pkt), GFP_KERNEL);
++
++		if (!pkt)
++			goto _err_pkt;
++
++		pkt->buf_begin = kzalloc(SIP_CTRL_BUF_SZ, GFP_KERNEL);
++
++		if (pkt->buf_begin == NULL) {
++			kfree(pkt);
++			pkt = NULL;
++			goto _err_pkt;
++		}
++
++		pkt->buf_len = SIP_CTRL_BUF_SZ;
++		pkt->buf = pkt->buf_begin;
++
++		if (i < SIP_CTRL_TXBUF_N) {
++			list_add_tail(&pkt->list, &sip->free_ctrl_txbuf);
++		} else {
++			list_add_tail(&pkt->list, &sip->free_ctrl_rxbuf);
++		}
++	}
++
++	mutex_init(&sip->rx_mtx);
++	skb_queue_head_init(&sip->rxq);
++	INIT_WORK(&sip->rx_process_work, sip_rxq_process);
++
++	sip->epub = epub;
++	atomic_set(&sip->noise_floor, -96);
++
++	atomic_set(&sip->state, SIP_INIT);
++	atomic_set(&sip->tx_credits, 0);
++
++	if (sip->rawbuf == NULL) {
++		sip->rawbuf = kzalloc(SIP_BOOT_BUF_SIZE, GFP_KERNEL);
++		if (sip->rawbuf == NULL) {
++			esp_dbg(ESP_DBG_ERROR, "no mem for rawbuf! \n");
++			goto _err_pkt;
++		}
++	}
++
++	atomic_set(&sip->state, SIP_PREPARE_BOOT);
++
++	return sip;
++
++      _err_pkt:
++	sip_free_init_ctrl_buf(sip);
++
++	if (sip->tx_aggr_buf) {
++#ifdef ESP_PREALLOC
++		esp_put_tx_aggr_buf(&sip->tx_aggr_buf);
++#else
++		po = get_order(SIP_TX_AGGR_BUF_SIZE);
++		free_pages((unsigned long) sip->tx_aggr_buf, po);
++		sip->tx_aggr_buf = NULL;
++#endif
++	}
++      _err_aggr:
++	if (sip) {
++		kfree(sip);
++		sip = NULL;
++	}
++      _err_sip:
++	return NULL;
++
++}
++
++static void sip_free_init_ctrl_buf(struct esp_sip *sip)
++{
++	struct sip_pkt *pkt, *tpkt;
++
++	list_for_each_entry_safe(pkt, tpkt, &sip->free_ctrl_txbuf, list) {
++		list_del(&pkt->list);
++		kfree(pkt->buf_begin);
++		kfree(pkt);
++	}
++
++	list_for_each_entry_safe(pkt, tpkt, &sip->free_ctrl_rxbuf, list) {
++		list_del(&pkt->list);
++		kfree(pkt->buf_begin);
++		kfree(pkt);
++	}
++}
++
++void sip_detach(struct esp_sip *sip)
++{
++#ifndef ESP_PREALLOC
++	int po;
++#endif
++	if (sip == NULL)
++		return;
++
++	esp_dbg(ESP_DBG_TRACE, "sip_detach: sip_free_init_ctrl_buf()");
++	sip_free_init_ctrl_buf(sip);
++
++	if (atomic_read(&sip->state) == SIP_RUN) {
++
++		sif_disable_target_interrupt(sip->epub);
++
++		atomic_set(&sip->state, SIP_STOP);
++
++		/* disable irq here */
++		sif_disable_irq(sip->epub);
++		cancel_work_sync(&sip->rx_process_work);
++
++		skb_queue_purge(&sip->rxq);
++		mutex_destroy(&sip->rx_mtx);
++		cancel_work(&sip->epub->sendup_work); // Must be non-sync
++		skb_queue_purge(&sip->epub->rxq);
++
++#ifdef ESP_NO_MAC80211
++		unregister_netdev(sip->epub->net_dev);
++		wiphy_unregister(sip->epub->wdev->wiphy);
++#else
++		if (test_and_clear_bit
++		    (ESP_WL_FLAG_HW_REGISTERED, &sip->epub->wl.flags)) {
++			ieee80211_unregister_hw(sip->epub->hw);
++		}
++#endif
++
++		/* cancel all worker/timer */
++		cancel_work_sync(&sip->epub->tx_work);
++		skb_queue_purge(&sip->epub->txq);
++		skb_queue_purge(&sip->epub->txdoneq);
++
++#ifdef ESP_PREALLOC
++		esp_put_tx_aggr_buf(&sip->tx_aggr_buf);
++#else
++		po = get_order(SIP_TX_AGGR_BUF_SIZE);
++		free_pages((unsigned long) sip->tx_aggr_buf, po);
++		sip->tx_aggr_buf = NULL;
++#endif
++
++		atomic_set(&sip->state, SIP_INIT);
++	} else if (atomic_read(&sip->state) >= SIP_BOOT
++		   && atomic_read(&sip->state) <= SIP_WAIT_BOOTUP) {
++
++		sif_disable_target_interrupt(sip->epub);
++		atomic_set(&sip->state, SIP_STOP);
++
++		sif_disable_irq(sip->epub);
++
++		if (sip->rawbuf)
++			kfree(sip->rawbuf);
++
++		if (atomic_read(&sip->state) == SIP_SEND_INIT) {
++			cancel_work_sync(&sip->rx_process_work);
++			skb_queue_purge(&sip->rxq);
++			mutex_destroy(&sip->rx_mtx);
++			cancel_work_sync(&sip->epub->sendup_work);
++			skb_queue_purge(&sip->epub->rxq);
++		}
++#ifdef ESP_NO_MAC80211
++		unregister_netdev(sip->epub->net_dev);
++		wiphy_unregister(sip->epub->wdev->wiphy);
++#else
++		if (test_and_clear_bit
++		    (ESP_WL_FLAG_HW_REGISTERED, &sip->epub->wl.flags)) {
++			ieee80211_unregister_hw(sip->epub->hw);
++		}
++#endif
++		atomic_set(&sip->state, SIP_INIT);
++	} else
++		esp_dbg(ESP_DBG_ERROR, "%s wrong state %d\n", __func__,
++			atomic_read(&sip->state));
++
++	kfree(sip);
++}
++
++int sip_write_memory(struct esp_sip *sip, u32 addr, u8 * buf, u16 len)
++{
++	struct sip_cmd_write_memory *cmd;
++	struct sip_hdr *chdr;
++	u16 remains, hdrs, bufsize;
++	u32 loadaddr;
++	u8 *src;
++	int err = 0;
++	u32 *t = NULL;
++
++	if (sip == NULL || sip->rawbuf == NULL) {
++		ESSERT(sip != NULL);
++		ESSERT(sip->rawbuf != NULL);
++		return -EINVAL;
++	}
++
++	memset(sip->rawbuf, 0, SIP_BOOT_BUF_SIZE);
++
++	chdr = (struct sip_hdr *) sip->rawbuf;
++	SIP_HDR_SET_TYPE(chdr->fc[0], SIP_CTRL);
++	chdr->c_cmdid = SIP_CMD_WRITE_MEMORY;
++
++	remains = len;
++	hdrs =
++	    sizeof(struct sip_hdr) + sizeof(struct sip_cmd_write_memory);
++
++	while (remains) {
++		src = &buf[len - remains];
++		loadaddr = addr + (len - remains);
++
++		if (remains < (SIP_BOOT_BUF_SIZE - hdrs)) {
++			/* aligned with 4 bytes */
++			bufsize = roundup(remains, 4);
++			memset(sip->rawbuf + hdrs, 0, bufsize);
++			remains = 0;
++		} else {
++			bufsize = SIP_BOOT_BUF_SIZE - hdrs;
++			remains -= bufsize;
++		}
++
++		chdr->len = bufsize + hdrs;
++		chdr->seq = sip->txseq++;
++		cmd =
++		    (struct sip_cmd_write_memory *) (sip->rawbuf +
++						     SIP_CTRL_HDR_LEN);
++		cmd->len = bufsize;
++		cmd->addr = loadaddr;
++		memcpy(sip->rawbuf + hdrs, src, bufsize);
++
++		t = (u32 *) sip->rawbuf;
++		esp_dbg(ESP_DBG_TRACE,
++			"%s t0: 0x%08x t1: 0x%08x t2:0x%08x loadaddr 0x%08x \n",
++			__func__, t[0], t[1], t[2], loadaddr);
++
++		err =
++		    esp_common_write(sip->epub, sip->rawbuf, chdr->len,
++				     ESP_SIF_SYNC);
++
++		if (err) {
++			esp_dbg(ESP_DBG_ERROR, "%s send buffer failed\n",
++				__func__);
++			return err;
++		}
++		// 1ms is enough, in fact on dell-d430, need not delay at all.
++		mdelay(1);
++
++	}
++
++	return err;
++}
++
++int sip_send_cmd(struct esp_sip *sip, int cid, u32 cmdlen, void *cmd)
++{
++	struct sip_hdr *chdr;
++	struct sip_pkt *pkt = NULL;
++	int ret = 0;
++
++	pkt = sip_get_ctrl_buf(sip, SIP_TX_CTRL_BUF);
++
++	if (pkt == NULL)
++		return -ENOMEM;
++
++	chdr = (struct sip_hdr *) pkt->buf_begin;
++	chdr->len = SIP_CTRL_HDR_LEN + cmdlen;
++	chdr->seq = sip->txseq++;
++	chdr->c_cmdid = cid;
++
++
++	if (cmd) {
++		memset(pkt->buf, 0, cmdlen);
++		memcpy(pkt->buf, (u8 *) cmd, cmdlen);
++	}
++
++	esp_dbg(ESP_DBG_TRACE, "cid %d, len %u, seq %u \n", chdr->c_cmdid,
++		chdr->len, chdr->seq);
++
++	esp_dbg(ESP_DBG_TRACE, "c1 0x%08x   c2 0x%08x\n",
++		*(u32 *) & pkt->buf[0], *(u32 *) & pkt->buf[4]);
++
++	ret =
++	    esp_common_write(sip->epub, pkt->buf_begin, chdr->len,
++			     ESP_SIF_SYNC);
++
++	if (ret)
++		esp_dbg(ESP_DBG_ERROR, "%s send cmd %d failed \n",
++			__func__, cid);
++
++	sip_reclaim_ctrl_buf(sip, pkt, SIP_TX_CTRL_BUF);
++
++	/*
++	 *  Hack here: reset tx/rx seq before target ram code is up...
++	 */
++	if (cid == SIP_CMD_BOOTUP) {
++		sip->rxseq = 0;
++		sip->txseq = 0;
++		sip->txdataseq = 0;
++	}
++
++	return ret;
++}
++
++struct sk_buff *sip_alloc_ctrl_skbuf(struct esp_sip *sip, u16 len, u32 cid)
++{
++	struct sip_hdr *si = NULL;
++	struct ieee80211_tx_info *ti = NULL;
++	struct sk_buff *skb = NULL;
++
++	ESSERT(len <= sip->tx_blksz);
++
++	/* no need to reserve space for net stack */
++	skb = __dev_alloc_skb(len, GFP_KERNEL);
++
++	if (skb == NULL) {
++		esp_dbg(ESP_DBG_ERROR, "no skb for ctrl !\n");
++		return NULL;
++	}
++
++	skb->len = len;
++
++	ti = IEEE80211_SKB_CB(skb);
++	/* set tx_info flags to 0xffffffff to indicate sip_ctrl pkt */
++	ti->flags = 0xffffffff;
++	si = (struct sip_hdr *) skb->data;
++	memset(si, 0, sizeof(struct sip_hdr));
++	SIP_HDR_SET_TYPE(si->fc[0], SIP_CTRL);
++	si->len = len;
++	si->c_cmdid = cid;
++
++	return skb;
++}
++
++void sip_free_ctrl_skbuff(struct esp_sip *sip, struct sk_buff *skb)
++{
++	memset(IEEE80211_SKB_CB(skb), 0, sizeof(struct ieee80211_tx_info));
++	kfree_skb(skb);
++}
++
++static struct sip_pkt *sip_get_ctrl_buf(struct esp_sip *sip,
++					SIP_BUF_TYPE bftype)
++{
++	struct sip_pkt *pkt = NULL;
++	struct list_head *bflist;
++	struct sip_hdr *chdr;
++
++	bflist =
++	    (bftype ==
++	     SIP_TX_CTRL_BUF) ? &sip->free_ctrl_txbuf : &sip->
++	    free_ctrl_rxbuf;
++
++	spin_lock_bh(&sip->lock);
++
++	if (list_empty(bflist)) {
++		spin_unlock_bh(&sip->lock);
++		return NULL;
++	}
++
++	pkt = list_first_entry(bflist, struct sip_pkt, list);
++	list_del(&pkt->list);
++	spin_unlock_bh(&sip->lock);
++
++	if (bftype == SIP_TX_CTRL_BUF) {
++		chdr = (struct sip_hdr *) pkt->buf_begin;
++		SIP_HDR_SET_TYPE(chdr->fc[0], SIP_CTRL);
++		pkt->buf = pkt->buf_begin + SIP_CTRL_HDR_LEN;
++	} else {
++		pkt->buf = pkt->buf_begin;
++	}
++
++	return pkt;
++}
++
++static void
++sip_reclaim_ctrl_buf(struct esp_sip *sip, struct sip_pkt *pkt,
++		     SIP_BUF_TYPE bftype)
++{
++	struct list_head *bflist = NULL;
++
++	if (bftype == SIP_TX_CTRL_BUF)
++		bflist = &sip->free_ctrl_txbuf;
++	else if (bftype == SIP_RX_CTRL_BUF)
++		bflist = &sip->free_ctrl_rxbuf;
++	else
++		return;
++
++	pkt->buf = pkt->buf_begin;
++
++	spin_lock_bh(&sip->lock);
++	list_add_tail(&pkt->list, bflist);
++	spin_unlock_bh(&sip->lock);
++}
++
++int sip_poll_bootup_event(struct esp_sip *sip)
++{
++	int ret = 0;
++
++	esp_dbg(ESP_DBG_TRACE, "polling bootup event... \n");
++
++	if (gl_bootup_cplx)
++		ret = wait_for_completion_timeout(gl_bootup_cplx, 2 * HZ);
++
++	esp_dbg(ESP_DBG_TRACE, "******time remain****** = [%d]\n", ret);
++	if (ret <= 0) {
++		esp_dbg(ESP_DBG_ERROR, "bootup event timeout\n");
++		return -ETIMEDOUT;
++	}
++
++	if (sif_get_ate_config() == 0) {
++		ret = esp_register_mac80211(sip->epub);
++	}
++#ifdef TEST_MODE
++	ret = test_init_netlink(sip);
++	if (ret < 0) {
++		esp_sip_dbg(ESP_DBG_TRACE,
++			    "esp_sdio: failed initializing netlink\n");
++		return ret;
++	}
++#endif
++
++	atomic_set(&sip->state, SIP_RUN);
++	esp_dbg(ESP_DBG_TRACE, "target booted up\n");
++
++	return ret;
++}
++
++int sip_poll_resetting_event(struct esp_sip *sip)
++{
++	int ret = 0;
++
++	esp_dbg(ESP_DBG_TRACE, "polling resetting event... \n");
++
++	if (gl_bootup_cplx)
++		ret = wait_for_completion_timeout(gl_bootup_cplx, 10 * HZ);
++
++	esp_dbg(ESP_DBG_TRACE, "******time remain****** = [%d]\n", ret);
++	if (ret <= 0) {
++		esp_dbg(ESP_DBG_ERROR, "resetting event timeout\n");
++		return -ETIMEDOUT;
++	}
++
++	esp_dbg(ESP_DBG_TRACE, "target resetting %d %p\n", ret,
++		gl_bootup_cplx);
++
++	return 0;
++}
++
++
++#ifdef FPGA_DEBUG
++
++/* bogus bootup cmd for FPGA debugging */
++int sip_send_bootup(struct esp_sip *sip)
++{
++	int ret;
++	struct sip_cmd_bootup bootcmd;
++
++	esp_dbg(ESP_DBG_LOG, "sending bootup\n");
++
++	bootcmd.boot_addr = 0;
++	ret =
++	    sip_send_cmd(sip, SIP_CMD_BOOTUP,
++			 sizeof(struct sip_cmd_bootup), &bootcmd);
++
++	return ret;
++}
++
++#endif				/* FPGA_DEBUG */
++
++bool sip_queue_need_stop(struct esp_sip * sip)
++{
++	return atomic_read(&sip->tx_data_pkt_queued) >=
++	    SIP_STOP_QUEUE_THRESHOLD || (atomic_read(&sip->tx_credits) < 8
++					 && atomic_read(&sip->
++							tx_data_pkt_queued)
++					 >=
++					 SIP_STOP_QUEUE_THRESHOLD / 4 * 3);
++}
++
++bool sip_queue_may_resume(struct esp_sip * sip)
++{
++	return atomic_read(&sip->epub->txq_stopped)
++	    && !test_bit(ESP_WL_FLAG_STOP_TXQ, &sip->epub->wl.flags)
++	    && ((atomic_read(&sip->tx_credits) >= 16
++		 && atomic_read(&sip->tx_data_pkt_queued) <
++		 SIP_RESUME_QUEUE_THRESHOLD * 2)
++		|| atomic_read(&sip->tx_data_pkt_queued) <
++		SIP_RESUME_QUEUE_THRESHOLD);
++}
++
++int sip_cmd_enqueue(struct esp_sip *sip, struct sk_buff *skb, int prior)
++{
++	if (!sip || !sip->epub) {
++		esp_dbg(ESP_DBG_ERROR, "func %s, sip->epub->txq is NULL\n",
++			__func__);
++		return -EINVAL;
++	}
++
++	if (!skb) {
++		esp_dbg(ESP_DBG_ERROR, "func %s, skb is NULL\n", __func__);
++		return -EINVAL;
++	}
++
++	if (prior == ENQUEUE_PRIOR_HEAD)
++		skb_queue_head(&sip->epub->txq, skb);
++	else
++		skb_queue_tail(&sip->epub->txq, skb);
++
++	if (sif_get_ate_config() == 0) {
++		ieee80211_queue_work(sip->epub->hw, &sip->epub->tx_work);
++	} else {
++		queue_work(sip->epub->esp_wkq, &sip->epub->tx_work);
++	}
++	return 0;
++}
++
++void sip_tx_data_pkt_enqueue(struct esp_pub *epub, struct sk_buff *skb)
++{
++	if (!epub || !epub->sip) {
++		if (!epub)
++			esp_dbg(ESP_DBG_ERROR, "func %s, epub is NULL\n",
++				__func__);
++		else
++			esp_dbg(ESP_DBG_ERROR,
++				"func %s, epub->sip is NULL\n", __func__);
++
++		return;
++	}
++	if (!skb) {
++		esp_dbg(ESP_DBG_ERROR, "func %s, skb is NULL\n", __func__);
++		return;
++	}
++	skb_queue_tail(&epub->txq, skb);
++	atomic_inc(&epub->sip->tx_data_pkt_queued);
++	if (sip_queue_need_stop(epub->sip)) {
++		if (epub->hw) {
++			ieee80211_stop_queues(epub->hw);
++			atomic_set(&epub->txq_stopped, true);
++		}
++
++	}
++}
++
++#ifdef FPGA_TXDATA
++int sip_send_tx_data(struct esp_sip *sip)
++{
++	struct sk_buff *skb = NULL;
++	struct sip_cmd_bss_info_update *bsscmd;
++
++	skb =
++	    sip_alloc_ctrl_skbuf(epub->sip,
++				 sizeof(struct sip_cmd_bss_info_update),
++				 SIP_CMD_BSS_INFO_UPDATE);
++	if (!skb)
++		return -EINVAL;
++
++	bsscmd =
++	    (struct sip_cmd_bss_info_update *) (skb->data +
++						sizeof(struct
++						       sip_tx_info));
++	bsscmd->isassoc = (assoc == true) ? 1 : 0;
++	memcpy(bsscmd->bssid, bssid, ETH_ALEN);
++	STRACE_SHOW(epub->sip);
++	return sip_cmd_enqueue(epub->sip, skb, ENQUEUE_PRIOR_TAIL);
++}
++#endif				/* FPGA_TXDATA */
+diff --git a/drivers/net/wireless/esp8089/esp_sip.h b/drivers/net/wireless/esp8089/esp_sip.h
+new file mode 100644
+index 000000000000..95cc42989b2c
+--- /dev/null
++++ b/drivers/net/wireless/esp8089/esp_sip.h
+@@ -0,0 +1,171 @@
++/*
++ *  Copyright (c) 2009- 2014 Espressif System.
++ *
++ *    Serial Interconnctor Protocol
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++
++#ifndef _ESP_SIP_H
++#define _ESP_SIP_H
++
++#include "sip2_common.h"
++
++#define SIP_CTRL_CREDIT_RESERVE      2
++
++#define SIP_PKT_MAX_LEN (1024*16)
++
++/* 16KB on normal X86 system, should check before porting to orhters */
++
++#define SIP_TX_AGGR_BUF_SIZE (4 * PAGE_SIZE)
++#define SIP_RX_AGGR_BUF_SIZE (4 * PAGE_SIZE)
++
++struct sk_buff;
++
++struct sip_pkt {
++	struct list_head list;
++
++	u8 *buf_begin;
++	u32 buf_len;
++	u8 *buf;
++};
++
++typedef enum RECALC_CREDIT_STATE {
++	RECALC_CREDIT_DISABLE = 0,
++	RECALC_CREDIT_ENABLE = 1,
++} RECALC_CREDIT_STATE;
++
++typedef enum ENQUEUE_PRIOR {
++	ENQUEUE_PRIOR_TAIL = 0,
++	ENQUEUE_PRIOR_HEAD,
++} ENQUEUE_PRIOR;
++
++typedef enum SIP_STATE {
++	SIP_INIT = 0,
++	SIP_PREPARE_BOOT,
++	SIP_BOOT,
++	SIP_SEND_INIT,
++	SIP_WAIT_BOOTUP,
++	SIP_RUN,
++	SIP_SUSPEND,
++	SIP_STOP
++} SIP_STATE;
++
++enum sip_notifier {
++	SIP_TX_DONE = 1,
++	SIP_RX_DONE = 2,
++};
++
++#define SIP_CREDITS_LOW_THRESHOLD  64	//i.e. 4k
++
++struct esp_sip {
++	struct list_head free_ctrl_txbuf;
++	struct list_head free_ctrl_rxbuf;
++
++	u32 rxseq;		/* sip pkt seq, should match target side */
++	u32 txseq;
++	u32 txdataseq;
++
++	u8 to_host_seq;
++
++	atomic_t state;
++	spinlock_t lock;
++	atomic_t tx_credits;
++
++	atomic_t tx_ask_credit_update;
++
++	u8 *rawbuf;		/* used in boot stage, free once chip is fully up */
++	u8 *tx_aggr_buf;
++	u8 *tx_aggr_write_ptr;	/* update after insertion of each pkt */
++	u8 *tx_aggr_lastpkt_ptr;
++
++	struct mutex rx_mtx;
++	struct sk_buff_head rxq;
++	struct work_struct rx_process_work;
++
++	u16 tx_blksz;
++	u16 rx_blksz;
++
++	bool dump_rpbm_err;
++	bool sendup_rpbm_pkt;
++	bool rxabort_fixed;
++	bool support_bgscan;
++	u8 credit_to_reserve;
++
++	atomic_t credit_status;
++	struct timer_list credit_timer;
++
++	atomic_t noise_floor;
++
++	u32 tx_tot_len;		/* total len for one transaction */
++	u32 rx_tot_len;
++
++	atomic_t rx_handling;
++	atomic_t tx_data_pkt_queued;
++
++	atomic_t data_tx_stopped;
++	atomic_t tx_stopped;
++
++	struct esp_pub *epub;
++};
++
++int sip_rx(struct esp_pub *epub);
++//int sip_download_fw(struct esp_sip *sip, u32 load_addr, u32 boot_addr);
++
++
++int sip_write_memory(struct esp_sip *, u32 addr, u8 * buf, u16 len);
++
++void sip_credit_process(struct esp_pub *, u8 credits);
++
++int sip_send_cmd(struct esp_sip *sip, int cid, u32 cmdlen, void *cmd);
++
++struct esp_sip *sip_attach(struct esp_pub *);
++
++int sip_post_init(struct esp_sip *sip, struct sip_evt_bootup2 *bevt);
++
++void sip_detach(struct esp_sip *sip);
++
++void sip_txq_process(struct esp_pub *epub);
++
++struct sk_buff *sip_alloc_ctrl_skbuf(struct esp_sip *sip, u16 len,
++				     u32 cid);
++
++void sip_free_ctrl_skbuff(struct esp_sip *sip, struct sk_buff *skb);
++
++bool sip_queue_need_stop(struct esp_sip *sip);
++bool sip_queue_may_resume(struct esp_sip *sip);
++bool sip_tx_data_need_stop(struct esp_sip *sip);
++bool sip_tx_data_may_resume(struct esp_sip *sip);
++
++void sip_tx_data_pkt_enqueue(struct esp_pub *epub, struct sk_buff *skb);
++void sip_rx_data_pkt_enqueue(struct esp_pub *epub, struct sk_buff *skb);
++
++int sip_cmd_enqueue(struct esp_sip *sip, struct sk_buff *skb, int prior);
++
++int sip_poll_bootup_event(struct esp_sip *sip);
++
++int sip_poll_resetting_event(struct esp_sip *sip);
++
++void sip_trigger_txq_process(struct esp_sip *sip);
++
++void sip_send_chip_init(struct esp_sip *sip);
++
++bool mod_support_no_txampdu(void);
++
++bool mod_support_no_rxampdu(void);
++
++void mod_support_no_txampdu_set(bool value);
++
++#ifdef FPGA_DEBUG
++int sip_send_bootup(struct esp_sip *sip);
++#endif				/* FPGA_DEBUG */
++void sip_debug_show(struct esp_sip *sip);
++#endif
+diff --git a/drivers/net/wireless/esp8089/esp_utils.c b/drivers/net/wireless/esp8089/esp_utils.c
+new file mode 100644
+index 000000000000..8b188de79b2c
+--- /dev/null
++++ b/drivers/net/wireless/esp8089/esp_utils.c
+@@ -0,0 +1,262 @@
++/*
++ * Copyright (c) 2009 - 2014 Espressif System.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++
++#include "linux/types.h"
++#include "linux/kernel.h"
++#include <linux/ieee80211.h>
++#include <net/mac80211.h>
++#include <linux/skbuff.h>
++
++#include <net/tcp.h>
++#include <linux/ip.h>
++#include <asm/checksum.h>
++
++#include "esp_pub.h"
++#include "esp_utils.h"
++#include "esp_wmac.h"
++#include "esp_debug.h"
++
++/*
++ * Convert IEEE channel number to MHz frequency.
++ */
++u32 esp_ieee2mhz(u8 chan)
++{
++	if (chan == 14)
++		return 2484;
++
++	if (chan < 14)
++		return 2407 + chan * 5;
++	else
++		return 2512 + ((chan - 15) * 20);
++	//TODO, add 5GHz
++}
++
++enum {
++	ESP_RATE_1_LONG = 0x0,
++	ESP_RATE_2_LONG = 0x1,
++	ESP_RATE_2_SHORT = 0x5,
++	ESP_RATE_5_SHORT = 0x6,
++	ESP_RATE_5_LONG = 0x2,
++	ESP_RATE_11_SHORT = 0x7,
++	ESP_RATE_11_LONG = 0x3,
++	ESP_RATE_6 = 0xb,
++	ESP_RATE_9 = 0xf,
++	ESP_RATE_12 = 0xa,
++	ESP_RATE_18 = 0xe,
++	ESP_RATE_24 = 0x9,
++	ESP_RATE_36 = 0xd,
++	ESP_RATE_48 = 0x8,
++	ESP_RATE_54 = 0xc,
++	/*        ESP_RATE_MCS0 =0x10,
++	   ESP_RATE_MCS1 =0x11,
++	   ESP_RATE_MCS2 =0x12,
++	   ESP_RATE_MCS3 =0x13,
++	   ESP_RATE_MCS4 =0x14,
++	   ESP_RATE_MCS5 =0x15,
++	   ESP_RATE_MCS6 =0x16,
++	   ESP_RATE_MCS7 =0x17,
++	 */
++};
++
++static u8 esp_rate_table[20] = {
++	ESP_RATE_1_LONG,
++	ESP_RATE_2_SHORT,
++	ESP_RATE_5_SHORT,
++	ESP_RATE_11_SHORT,
++	ESP_RATE_6,
++	ESP_RATE_9,
++	ESP_RATE_12,
++	ESP_RATE_18,
++	ESP_RATE_24,
++	ESP_RATE_36,
++	ESP_RATE_48,
++	ESP_RATE_54,
++	/*      ESP_RATE_MCS0,
++	   ESP_RATE_MCS1,
++	   ESP_RATE_MCS2,
++	   ESP_RATE_MCS3,
++	   ESP_RATE_MCS4,
++	   ESP_RATE_MCS5,
++	   ESP_RATE_MCS6,
++	   ESP_RATE_MCS7,
++	 */
++};
++
++s8 esp_wmac_rate2idx(u8 rate)
++{
++	int i;
++
++	if (rate == ESP_RATE_2_LONG)
++		return 1;
++	if (rate == ESP_RATE_5_LONG)
++		return 2;
++	if (rate == ESP_RATE_11_LONG)
++		return 3;
++
++	for (i = 0; i < 20; i++) {
++		if (rate == esp_rate_table[i])
++			return i;
++	}
++
++	esp_dbg(ESP_DBG_ERROR, "%s unknown rate 0x%02x \n", __func__,
++		rate);
++
++	return 0;
++}
++
++bool esp_wmac_rxsec_error(u8 error)
++{
++	return (error >= RX_SECOV_ERR && error <= RX_SECFIFO_TIMEOUT)
++	    || (error >= RX_WEPICV_ERR && error <= RX_WAPIMIC_ERR);
++}
++
++int esp_cipher2alg(int cipher)
++{
++	if (cipher == WLAN_CIPHER_SUITE_TKIP)
++		return ALG_TKIP;
++
++	if (cipher == WLAN_CIPHER_SUITE_CCMP)
++		return ALG_CCMP;
++
++	if (cipher == WLAN_CIPHER_SUITE_WEP40
++	    || cipher == WLAN_CIPHER_SUITE_WEP104)
++		return ALG_WEP;
++
++	if (cipher == WLAN_CIPHER_SUITE_AES_CMAC)
++		return ALG_AES_CMAC;
++
++	//printk("%s wrong cipher 0x%x!\n",__func__,cipher);
++
++	return -1;
++}
++
++#ifdef RX_CHECKSUM_TEST
++atomic_t g_iv_len;
++void esp_rx_checksum_test(struct sk_buff *skb)
++{
++	static u32 ip_err = 0;
++	static u32 tcp_err = 0;
++	struct ieee80211_hdr *pwh = (struct ieee80211_hdr *) skb->data;
++	int hdrlen = ieee80211_hdrlen(pwh->frame_control);
++
++	if (ieee80211_has_protected(pwh->frame_control))
++		hdrlen += atomic_read(&g_iv_len);
++
++	if (ieee80211_is_data(pwh->frame_control)) {
++		struct llc_snap_hdr *llc =
++		    (struct llc_snap_hdr *) (skb->data + hdrlen);
++		if (ntohs(llc->eth_type) == ETH_P_IP) {
++			int llclen = sizeof(struct llc_snap_hdr);
++			struct iphdr *iph =
++			    (struct iphdr *) (skb->data + hdrlen + llclen);
++			__sum16 csum_bak = iph->check;
++
++			iph->check = 0;
++			iph->check = ip_fast_csum(iph, iph->ihl);
++			if (iph->check != csum_bak) {
++				esp_dbg(ESP_DBG_ERROR,
++					"total ip checksum error %d\n",
++					++ip_err);
++			}
++			iph->check = csum_bak;
++
++			if (iph->protocol == 0x06) {
++				struct tcphdr *tcph =
++				    (struct tcphdr *) (skb->data + hdrlen +
++						       llclen +
++						       iph->ihl * 4);
++				int datalen =
++				    skb->len - (hdrlen + llclen +
++						iph->ihl * 4);
++				csum_bak = tcph->check;
++
++				tcph->check = 0;
++				tcph->check =
++				    tcp_v4_check(datalen, iph->saddr,
++						 iph->daddr,
++						 csum_partial((char *)
++							      tcph,
++							      datalen, 0));
++				if (tcph->check != csum_bak) {
++					esp_dbg(ESP_DBG_ERROR,
++						"total tcp checksum error %d\n",
++						++tcp_err);
++				}
++				tcph->check = csum_bak;
++			}
++		}
++	}
++}
++
++#endif
++
++#ifdef GEN_ERR_CHECKSUM
++
++void esp_gen_err_checksum(struct sk_buff *skb)
++{
++	static u32 tx_seq = 0;
++	if ((tx_seq++ % 16) == 0) {
++		struct ieee80211_hdr *hdr =
++		    (struct ieee80211_hdr *) skb->data;
++		int hdrlen = ieee80211_hdrlen(hdr->frame_control);
++
++		if (ieee80211_has_protected(pwh->frame_control))
++			hdrlen +=
++			    IEEE80211_SKB_CB(skb)->control.hw_key->iv_len;
++
++		struct llc_snap_hdr *llc =
++		    (struct llc_snap_hdr *) (skb->data + hdrlen);
++		if (ntohs(llc->eth_type) == ETH_P_IP) {
++			int llclen = sizeof(struct llc_snap_hdr);
++			struct iphdr *iph =
++			    (struct iphdr *) (skb->data + hdrlen + llclen);
++
++			iph->check = ~iph->check;
++
++			if (iph->protocol == 0x06) {
++				struct tcphdr *tcph =
++				    (struct tcphdr *) (skb->data + hdrlen +
++						       llclen +
++						       iph->ihl * 4);
++				tcph->check = ~tcph->check;
++			}
++		}
++	}
++}
++#endif
++
++bool esp_is_ip_pkt(struct sk_buff *skb)
++{
++	struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
++	int hdrlen;
++	struct llc_snap_hdr *llc;
++
++	if (!ieee80211_is_data(hdr->frame_control))
++		return false;
++
++	hdrlen = ieee80211_hdrlen(hdr->frame_control);
++	if (ieee80211_has_protected(hdr->frame_control))
++		hdrlen += IEEE80211_SKB_CB(skb)->control.hw_key->iv_len;
++#ifdef RX_CHECKSUM_TEST
++	atomic_set(&g_iv_len,
++		   IEEE80211_SKB_CB(skb)->control.hw_key->iv_len);
++#endif
++	if (skb->len < hdrlen + sizeof(struct llc_snap_hdr))
++		return false;
++	llc = (struct llc_snap_hdr *) (skb->data + hdrlen);
++	if (ntohs(llc->eth_type) != ETH_P_IP)
++		return false;
++	else
++		return true;
++}
+diff --git a/drivers/net/wireless/esp8089/esp_utils.h b/drivers/net/wireless/esp8089/esp_utils.h
+new file mode 100644
+index 000000000000..ed16d9ca0a65
+--- /dev/null
++++ b/drivers/net/wireless/esp8089/esp_utils.h
+@@ -0,0 +1,41 @@
++/*
++ * Copyright (c) 2011-2012 Espressif System.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++
++#ifndef _ESP_UTILS_H_
++#define _ESP_UTILS_H_
++
++#include "linux/types.h"
++#include <linux/version.h>
++
++#ifndef BIT
++#define BIT(x) (0x1 << (x))
++#endif
++
++u32 esp_ieee2mhz(u8 chan);
++
++enum ieee80211_key_alg {
++	ALG_WEP,
++	ALG_TKIP,
++	ALG_CCMP,
++	ALG_AES_CMAC
++};
++
++int esp_cipher2alg(int cipher);
++
++void esp_rx_checksum_test(struct sk_buff *skb);
++void esp_gen_err_checksum(struct sk_buff *skb);
++
++bool esp_is_ip_pkt(struct sk_buff *skb);
++
++#endif
+diff --git a/drivers/net/wireless/esp8089/esp_version.h b/drivers/net/wireless/esp8089/esp_version.h
+new file mode 100644
+index 000000000000..481d98841fc2
+--- /dev/null
++++ b/drivers/net/wireless/esp8089/esp_version.h
+@@ -0,0 +1 @@
++#define DRIVER_VER 0xbdf5087c3debll
+diff --git a/drivers/net/wireless/esp8089/esp_wl.h b/drivers/net/wireless/esp8089/esp_wl.h
+new file mode 100644
+index 000000000000..e3e62a83d505
+--- /dev/null
++++ b/drivers/net/wireless/esp8089/esp_wl.h
+@@ -0,0 +1,63 @@
++#ifndef _ESP_WL_H_
++#define _ESP_WL_H_
++
++//#define MAX_PROBED_SSID_INDEX 9
++
++
++enum {
++	CONF_HW_BIT_RATE_1MBPS = BIT(0),
++	CONF_HW_BIT_RATE_2MBPS = BIT(1),
++	CONF_HW_BIT_RATE_5_5MBPS = BIT(2),
++	CONF_HW_BIT_RATE_11MBPS = BIT(3),
++	CONF_HW_BIT_RATE_6MBPS = BIT(4),
++	CONF_HW_BIT_RATE_9MBPS = BIT(5),
++	CONF_HW_BIT_RATE_12MBPS = BIT(6),
++	CONF_HW_BIT_RATE_18MBPS = BIT(7),
++	CONF_HW_BIT_RATE_22MBPS = BIT(8),
++	CONF_HW_BIT_RATE_24MBPS = BIT(9),
++	CONF_HW_BIT_RATE_36MBPS = BIT(10),
++	CONF_HW_BIT_RATE_48MBPS = BIT(11),
++	CONF_HW_BIT_RATE_54MBPS = BIT(12),
++	CONF_HW_BIT_RATE_11B_MASK =
++	    (CONF_HW_BIT_RATE_1MBPS | CONF_HW_BIT_RATE_2MBPS |
++	     CONF_HW_BIT_RATE_5_5MBPS | CONF_HW_BIT_RATE_11MBPS),
++};
++
++#if 0
++enum {
++	CONF_HW_RATE_INDEX_1MBPS = 0,
++	CONF_HW_RATE_INDEX_2MBPS = 1,
++	CONF_HW_RATE_INDEX_5_5MBPS = 2,
++	CONF_HW_RATE_INDEX_6MBPS = 3,
++	CONF_HW_RATE_INDEX_9MBPS = 4,
++	CONF_HW_RATE_INDEX_11MBPS = 5,
++	CONF_HW_RATE_INDEX_12MBPS = 6,
++	CONF_HW_RATE_INDEX_18MBPS = 7,
++	CONF_HW_RATE_INDEX_22MBPS = 8,
++	CONF_HW_RATE_INDEX_24MBPS = 9,
++	CONF_HW_RATE_INDEX_36MBPS = 10,
++	CONF_HW_RATE_INDEX_48MBPS = 11,
++	CONF_HW_RATE_INDEX_54MBPS = 12,
++	CONF_HW_RATE_INDEX_MAX,
++};
++
++enum {
++	CONF_HW_RXTX_RATE_54 = 0,
++	CONF_HW_RXTX_RATE_48,
++	CONF_HW_RXTX_RATE_36,
++	CONF_HW_RXTX_RATE_24,
++	CONF_HW_RXTX_RATE_22,
++	CONF_HW_RXTX_RATE_18,
++	CONF_HW_RXTX_RATE_12,
++	CONF_HW_RXTX_RATE_11,
++	CONF_HW_RXTX_RATE_9,
++	CONF_HW_RXTX_RATE_6,
++	CONF_HW_RXTX_RATE_5_5,
++	CONF_HW_RXTX_RATE_2,
++	CONF_HW_RXTX_RATE_1,
++	CONF_HW_RXTX_RATE_MAX,
++	CONF_HW_RXTX_RATE_UNSUPPORTED = 0xff
++};
++#endif
++
++#endif				/* _ESP_WL_H_ */
+diff --git a/drivers/net/wireless/esp8089/esp_wmac.h b/drivers/net/wireless/esp8089/esp_wmac.h
+new file mode 100644
+index 000000000000..72d13cbfc0e5
+--- /dev/null
++++ b/drivers/net/wireless/esp8089/esp_wmac.h
+@@ -0,0 +1,92 @@
++/*
++ * Copyright (c) 2011-2012 Espressif System.
++ *
++ *   MAC header
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++
++#ifndef _ESP_WMAC_H_
++#define _ESP_WMAC_H_
++
++struct esp_mac_rx_ctrl {
++	signed rssi:8;
++	unsigned rate:4;
++	unsigned is_group:1;
++	unsigned:1;
++	unsigned sig_mode:2;
++	unsigned legacy_length:12;
++	unsigned damatch0:1;
++	unsigned damatch1:1;
++	unsigned bssidmatch0:1;
++	unsigned bssidmatch1:1;
++	unsigned MCS:7;
++	unsigned CWB:1;
++	unsigned HT_length:16;
++	unsigned Smoothing:1;
++	unsigned Not_Sounding:1;
++	unsigned:1;
++	unsigned Aggregation:1;
++	unsigned STBC:2;
++	unsigned FEC_CODING:1;
++	unsigned SGI:1;
++	unsigned rxend_state:8;
++	unsigned ampdu_cnt:8;
++	unsigned channel:4;
++	unsigned:4;
++	signed noise_floor:8;
++};
++
++struct esp_rx_ampdu_len {
++	unsigned substate:8;
++	unsigned sublen:12;
++	unsigned:12;
++};
++
++struct esp_tx_ampdu_entry {
++	u32 sub_len:12, dili_num:7,:1, null_byte:2, data:1, enc:1, seq:8;
++};
++
++//rxend_state flags
++#define RX_PYH_ERR_MIN 0x42
++#define RX_AGC_ERR_MIN 0x42
++#define RX_AGC_ERR_MAX 0x47
++#define RX_OFDM_ERR_MIN 0x50
++#define RX_OFDM_ERR_MAX 0x58
++#define RX_CCK_ERR_MIN 0x59
++#define RX_CCK_ERR_MAX 0x5F
++#define RX_ABORT 0x80
++#define RX_SF_ERR 0x40
++#define RX_FCS_ERR 0x41
++#define RX_AHBOV_ERR 0xC0
++#define RX_BUFOV_ERR 0xC1
++#define RX_BUFINV_ERR 0xC2
++#define RX_AMPDUSF_ERR 0xC3
++#define RX_AMPDUBUFOV_ERR 0xC4
++#define RX_MACBBFIFOOV_ERR 0xC5
++#define RX_RPBM_ERR 0xC6
++#define RX_BTFORCE_ERR 0xC7
++#define RX_SECOV_ERR 0xE1
++#define RX_SECPROT_ERR0 0xE2
++#define RX_SECPROT_ERR1 0xE3
++#define RX_SECKEY_ERR 0xE4
++#define RX_SECCRLEN_ERR 0xE5
++#define RX_SECFIFO_TIMEOUT 0xE6
++#define RX_WEPICV_ERR 0xF0
++#define RX_TKIPICV_ERR 0xF4
++#define RX_TKIPMIC_ERR 0xF5
++#define RX_CCMPMIC_ERR 0xF8
++#define RX_WAPIMIC_ERR 0xFC
++
++s8 esp_wmac_rate2idx(u8 rate);
++bool esp_wmac_rxsec_error(u8 error);
++
++#endif				/* _ESP_WMAC_H_ */
+diff --git a/drivers/net/wireless/esp8089/firmware/LICENSE-2.0.txt b/drivers/net/wireless/esp8089/firmware/LICENSE-2.0.txt
+new file mode 100644
+index 000000000000..0dd35c82a001
+--- /dev/null
++++ b/drivers/net/wireless/esp8089/firmware/LICENSE-2.0.txt
+@@ -0,0 +1,203 @@
++The esp8089 firmware files are licensed under the Apache License, Version 2.0:
++
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++                           Version 2.0, January 2004
++                        http://www.apache.org/licenses/
++
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++   You may obtain a copy of the License at
++
++       http://www.apache.org/licenses/LICENSE-2.0
++
++   Unless required by applicable law or agreed to in writing, software
++   distributed under the License is distributed on an "AS IS" BASIS,
++   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
++   See the License for the specific language governing permissions and
++   limitations under the License.
+diff --git a/drivers/net/wireless/esp8089/sdio_sif_esp.c b/drivers/net/wireless/esp8089/sdio_sif_esp.c
+new file mode 100644
+index 000000000000..2bd2c63f5388
+--- /dev/null
++++ b/drivers/net/wireless/esp8089/sdio_sif_esp.c
+@@ -0,0 +1,824 @@
++/*
++ * Copyright (c) 2010 -2013 Espressif System.
++ *
++ *   sdio serial i/f driver
++ *    - sdio device control routines
++ *    - sync/async DMA/PIO read/write
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++#include <linux/mmc/card.h>
++#include <linux/mmc/mmc.h>
++#include <linux/mmc/core.h>
++#include <linux/mmc/host.h>
++#include <linux/mmc/sdio_func.h>
++#include <linux/mmc/sdio_ids.h>
++#include <linux/mmc/sdio.h>
++#include <linux/mmc/sd.h>
++#include <linux/module.h>
++#include <net/mac80211.h>
++#include <linux/time.h>
++#include <linux/pm.h>
++#include <linux/delay.h>
++
++#include "esp_pub.h"
++#include "esp_sif.h"
++#include "esp_sip.h"
++#include "esp_debug.h"
++#include "slc_host_register.h"
++#include "esp_version.h"
++#include "esp_ctrl.h"
++#include "esp_file.h"
++#ifdef USE_EXT_GPIO
++#include "esp_ext.h"
++#endif				/* USE_EXT_GPIO */
++
++#define MANUFACTURER_ID_EAGLE_BASE        0x1110
++#define MANUFACTURER_ID_EAGLE_BASE_MASK     0xFF00
++#define MANUFACTURER_CODE                  0x6666
++
++static const struct sdio_device_id esp_sdio_devices[] = {
++	{SDIO_DEVICE
++	 (MANUFACTURER_CODE, (MANUFACTURER_ID_EAGLE_BASE | 0x1))},
++	{},
++};
++
++static const struct of_device_id esp_of_match_table[] = {
++        { .compatible = "esp,esp8089", .data = NULL},
++        { }
++};
++
++static int /*__init*/ esp_sdio_init(void);
++static void /*__exit*/ esp_sdio_exit(void);
++
++
++#define ESP_DMA_IBUFSZ   2048
++
++//unsigned int esp_msg_level = 0;
++unsigned int esp_msg_level = ESP_DBG_ERROR | ESP_SHOW;
++
++struct esp_sdio_ctrl *sif_sctrl = NULL;
++
++#ifdef ESP_ANDROID_LOGGER
++bool log_off = false;
++#endif				/* ESP_ANDROID_LOGGER */
++
++static int esdio_power_off(struct esp_sdio_ctrl *sctrl);
++static int esdio_power_on(struct esp_sdio_ctrl *sctrl);
++
++void sif_set_clock(struct sdio_func *func, int clk);
++
++void sif_lock_bus(struct esp_pub *epub)
++{
++	EPUB_FUNC_CHECK(epub, _exit);
++
++	sdio_claim_host(EPUB_TO_FUNC(epub));
++      _exit:
++	return;
++}
++
++void sif_unlock_bus(struct esp_pub *epub)
++{
++	EPUB_FUNC_CHECK(epub, _exit);
++
++	sdio_release_host(EPUB_TO_FUNC(epub));
++      _exit:
++	return;
++}
++
++static inline bool bad_buf(u8 * buf)
++{
++	return ((unsigned long) buf & 0x3) || !virt_addr_valid(buf);
++}
++
++u8 sdio_io_readb(struct esp_pub *epub, int addr, int *res)
++{
++	struct esp_sdio_ctrl *sctrl = NULL;
++	struct sdio_func *func = NULL;
++	sctrl = (struct esp_sdio_ctrl *) epub->sif;
++	func = sctrl->func;
++
++	if (func->num == 0)
++		return sdio_f0_readb(func, addr, res);
++	else
++		return sdio_readb(func, addr, res);
++}
++
++void sdio_io_writeb(struct esp_pub *epub, u8 value, int addr, int *res)
++{
++	struct esp_sdio_ctrl *sctrl = NULL;
++	struct sdio_func *func = NULL;
++	sctrl = (struct esp_sdio_ctrl *) epub->sif;
++	func = sctrl->func;
++
++	if (func->num == 0)
++		sdio_f0_writeb(func, value, addr, res);
++	else
++		sdio_writeb(func, value, addr, res);
++}
++
++int sif_io_raw(struct esp_pub *epub, u32 addr, u8 * buf, u32 len, u32 flag)
++{
++	int err = 0;
++	u8 *ibuf = NULL;
++	bool need_ibuf = false;
++	struct esp_sdio_ctrl *sctrl = NULL;
++	struct sdio_func *func = NULL;
++
++	if (epub == NULL || buf == NULL) {
++		ESSERT(0);
++		err = -EINVAL;
++		goto _exit;
++	}
++
++	sctrl = (struct esp_sdio_ctrl *) epub->sif;
++	func = sctrl->func;
++	if (func == NULL) {
++		ESSERT(0);
++		err = -EINVAL;
++		goto _exit;
++	}
++
++	if (bad_buf(buf)) {
++		esp_dbg(ESP_DBG_TRACE, "%s dst 0x%08x, len %d badbuf\n",
++			__func__, addr, len);
++		need_ibuf = true;
++		ibuf = sctrl->dma_buffer;
++	} else {
++		ibuf = buf;
++	}
++
++	if (flag & SIF_BLOCK_BASIS) {
++		/* round up for block data transcation */
++	}
++
++	if (flag & SIF_TO_DEVICE) {
++
++		if (need_ibuf)
++			memcpy(ibuf, buf, len);
++
++		if (flag & SIF_FIXED_ADDR)
++			err = sdio_writesb(func, addr, ibuf, len);
++		else if (flag & SIF_INC_ADDR) {
++			err = sdio_memcpy_toio(func, addr, ibuf, len);
++		}
++	} else if (flag & SIF_FROM_DEVICE) {
++
++		if (flag & SIF_FIXED_ADDR)
++			err = sdio_readsb(func, ibuf, addr, len);
++		else if (flag & SIF_INC_ADDR) {
++			err = sdio_memcpy_fromio(func, ibuf, addr, len);
++		}
++
++
++		if (!err && need_ibuf)
++			memcpy(buf, ibuf, len);
++	}
++
++      _exit:
++	return err;
++}
++
++int sif_io_sync(struct esp_pub *epub, u32 addr, u8 * buf, u32 len,
++		u32 flag)
++{
++	int err = 0;
++	u8 *ibuf = NULL;
++	bool need_ibuf = false;
++	struct esp_sdio_ctrl *sctrl = NULL;
++	struct sdio_func *func = NULL;
++
++	if (epub == NULL || buf == NULL) {
++		ESSERT(0);
++		err = -EINVAL;
++		goto _exit;
++	}
++
++	sctrl = (struct esp_sdio_ctrl *) epub->sif;
++	func = sctrl->func;
++	if (func == NULL) {
++		ESSERT(0);
++		err = -EINVAL;
++		goto _exit;
++	}
++
++	if (bad_buf(buf)) {
++		esp_dbg(ESP_DBG_TRACE, "%s dst 0x%08x, len %d badbuf\n",
++			__func__, addr, len);
++		need_ibuf = true;
++		ibuf = sctrl->dma_buffer;
++	} else {
++		ibuf = buf;
++	}
++
++	if (flag & SIF_BLOCK_BASIS) {
++		/* round up for block data transcation */
++	}
++
++	if (flag & SIF_TO_DEVICE) {
++
++		esp_dbg(ESP_DBG_TRACE, "%s to addr 0x%08x, len %d \n",
++			__func__, addr, len);
++		if (need_ibuf)
++			memcpy(ibuf, buf, len);
++
++		sdio_claim_host(func);
++
++		if (flag & SIF_FIXED_ADDR)
++			err = sdio_writesb(func, addr, ibuf, len);
++		else if (flag & SIF_INC_ADDR) {
++			err = sdio_memcpy_toio(func, addr, ibuf, len);
++		}
++		sdio_release_host(func);
++	} else if (flag & SIF_FROM_DEVICE) {
++
++		esp_dbg(ESP_DBG_TRACE, "%s from addr 0x%08x, len %d \n",
++			__func__, addr, len);
++
++		sdio_claim_host(func);
++
++		if (flag & SIF_FIXED_ADDR)
++			err = sdio_readsb(func, ibuf, addr, len);
++		else if (flag & SIF_INC_ADDR) {
++			err = sdio_memcpy_fromio(func, ibuf, addr, len);
++		}
++
++		sdio_release_host(func);
++
++		if (!err && need_ibuf)
++			memcpy(buf, ibuf, len);
++	}
++
++      _exit:
++	return err;
++}
++
++int sif_lldesc_read_sync(struct esp_pub *epub, u8 * buf, u32 len)
++{
++	struct esp_sdio_ctrl *sctrl = NULL;
++	u32 read_len;
++
++	if (epub == NULL || buf == NULL) {
++		ESSERT(0);
++		return -EINVAL;
++	}
++
++	sctrl = (struct esp_sdio_ctrl *) epub->sif;
++
++	switch (sctrl->target_id) {
++	case 0x100:
++		read_len = len;
++		break;
++	case 0x600:
++		read_len = roundup(len, sctrl->slc_blk_sz);
++		break;
++	default:
++		read_len = len;
++		break;
++	}
++
++	return sif_io_sync((epub),
++			   (sctrl->slc_window_end_addr - 2 - (len)), (buf),
++			   (read_len),
++			   SIF_FROM_DEVICE | SIF_BYTE_BASIS |
++			   SIF_INC_ADDR);
++}
++
++int sif_lldesc_write_sync(struct esp_pub *epub, u8 * buf, u32 len)
++{
++	struct esp_sdio_ctrl *sctrl = NULL;
++	u32 write_len;
++
++	if (epub == NULL || buf == NULL) {
++		ESSERT(0);
++		return -EINVAL;
++	}
++
++	sctrl = (struct esp_sdio_ctrl *) epub->sif;
++
++	switch (sctrl->target_id) {
++	case 0x100:
++		write_len = len;
++		break;
++	case 0x600:
++		write_len = roundup(len, sctrl->slc_blk_sz);
++		break;
++	default:
++		write_len = len;
++		break;
++	}
++
++	return sif_io_sync((epub), (sctrl->slc_window_end_addr - (len)),
++			   (buf), (write_len),
++			   SIF_TO_DEVICE | SIF_BYTE_BASIS | SIF_INC_ADDR);
++}
++
++int sif_lldesc_read_raw(struct esp_pub *epub, u8 * buf, u32 len,
++			bool noround)
++{
++	struct esp_sdio_ctrl *sctrl = NULL;
++	u32 read_len;
++
++	if (epub == NULL || buf == NULL) {
++		ESSERT(0);
++		return -EINVAL;
++	}
++
++	sctrl = (struct esp_sdio_ctrl *) epub->sif;
++
++	switch (sctrl->target_id) {
++	case 0x100:
++		read_len = len;
++		break;
++	case 0x600:
++		if (!noround)
++			read_len = roundup(len, sctrl->slc_blk_sz);
++		else
++			read_len = len;
++		break;
++	default:
++		read_len = len;
++		break;
++	}
++
++	return sif_io_raw((epub), (sctrl->slc_window_end_addr - 2 - (len)),
++			  (buf), (read_len),
++			  SIF_FROM_DEVICE | SIF_BYTE_BASIS | SIF_INC_ADDR);
++}
++
++int sif_lldesc_write_raw(struct esp_pub *epub, u8 * buf, u32 len)
++{
++	struct esp_sdio_ctrl *sctrl = NULL;
++	u32 write_len;
++
++	if (epub == NULL || buf == NULL) {
++		ESSERT(0);
++		return -EINVAL;
++	}
++
++	sctrl = (struct esp_sdio_ctrl *) epub->sif;
++
++	switch (sctrl->target_id) {
++	case 0x100:
++		write_len = len;
++		break;
++	case 0x600:
++		write_len = roundup(len, sctrl->slc_blk_sz);
++		break;
++	default:
++		write_len = len;
++		break;
++	}
++	return sif_io_raw((epub), (sctrl->slc_window_end_addr - (len)),
++			  (buf), (write_len),
++			  SIF_TO_DEVICE | SIF_BYTE_BASIS | SIF_INC_ADDR);
++
++}
++
++static int esdio_power_on(struct esp_sdio_ctrl *sctrl)
++{
++	int err = 0;
++
++	if (sctrl->off == false)
++		return err;
++
++	sdio_claim_host(sctrl->func);
++	err = sdio_enable_func(sctrl->func);
++
++	if (err) {
++		esp_dbg(ESP_DBG_ERROR, "Unable to enable sdio func: %d\n",
++			err);
++		sdio_release_host(sctrl->func);
++		return err;
++	}
++
++	sdio_release_host(sctrl->func);
++
++	/* ensure device is up */
++	msleep(5);
++
++	sctrl->off = false;
++
++	return err;
++}
++
++static int esdio_power_off(struct esp_sdio_ctrl *sctrl)
++{
++	int err;
++
++	if (sctrl->off)
++		return 0;
++
++	sdio_claim_host(sctrl->func);
++	err = sdio_disable_func(sctrl->func);
++	sdio_release_host(sctrl->func);
++
++	if (err)
++		return err;
++
++	sctrl->off = true;
++
++	return err;
++}
++
++void sif_enable_irq(struct esp_pub *epub)
++{
++	int err;
++	struct esp_sdio_ctrl *sctrl = NULL;
++
++	sctrl = (struct esp_sdio_ctrl *) epub->sif;
++
++	sdio_claim_host(sctrl->func);
++
++	err = sdio_claim_irq(sctrl->func, sif_dsr);
++
++	if (err)
++		esp_dbg(ESP_DBG_ERROR, "sif %s failed\n", __func__);
++
++	atomic_set(&epub->sip->state, SIP_BOOT);
++
++	atomic_set(&sctrl->irq_installed, 1);
++
++	sdio_release_host(sctrl->func);
++}
++
++void sif_disable_irq(struct esp_pub *epub)
++{
++	struct esp_sdio_ctrl *sctrl = (struct esp_sdio_ctrl *) epub->sif;
++	int i = 0;
++
++	if (atomic_read(&sctrl->irq_installed) == 0)
++		return;
++
++	sdio_claim_host(sctrl->func);
++
++	while (atomic_read(&sctrl->irq_handling)) {
++		sdio_release_host(sctrl->func);
++		schedule_timeout(HZ / 100);
++		sdio_claim_host(sctrl->func);
++		if (i++ >= 400) {
++			esp_dbg(ESP_DBG_ERROR, "%s force to stop irq\n",
++				__func__);
++			break;
++		}
++	}
++
++	/* Ignore errors, we don't always use an irq. */
++	sdio_release_irq(sctrl->func);
++
++	atomic_set(&sctrl->irq_installed, 0);
++
++	sdio_release_host(sctrl->func);
++
++}
++
++void sif_set_clock(struct sdio_func *func, int clk)
++{
++	struct mmc_host *host = NULL;
++	struct mmc_card *card = NULL;
++
++	card = func->card;
++	host = card->host;
++
++	sdio_claim_host(func);
++
++	//currently only set clock
++	host->ios.clock = clk * 1000000;
++
++	esp_dbg(ESP_SHOW, "%s clock is %u\n", __func__, host->ios.clock);
++	if (host->ios.clock > host->f_max) {
++		host->ios.clock = host->f_max;
++	}
++	host->ops->set_ios(host, &host->ios);
++
++	mdelay(2);
++
++	sdio_release_host(func);
++}
++
++static int esp_sdio_probe(struct sdio_func *func,
++			  const struct sdio_device_id *id);
++static void esp_sdio_remove(struct sdio_func *func);
++
++static int esp_sdio_probe(struct sdio_func *func,
++			  const struct sdio_device_id *id)
++{
++	int err = 0;
++	struct esp_pub *epub = NULL;
++	struct esp_sdio_ctrl *sctrl;
++
++	esp_dbg(ESP_DBG_TRACE,
++		"sdio_func_num: 0x%X, vendor id: 0x%X, dev id: 0x%X, block size: 0x%X/0x%X\n",
++		func->num, func->vendor, func->device, func->max_blksize,
++		func->cur_blksize);
++
++	if (sif_sctrl == NULL) {
++
++		esp_conf_init(&func->dev);
++
++		esp_conf_upload_first();
++
++		sctrl = kzalloc(sizeof(struct esp_sdio_ctrl), GFP_KERNEL);
++
++		if (sctrl == NULL) {
++			return -ENOMEM;
++		}
++
++		/* temp buffer reserved for un-dma-able request */
++		sctrl->dma_buffer = kzalloc(ESP_DMA_IBUFSZ, GFP_KERNEL);
++
++		if (sctrl->dma_buffer == NULL) {
++			err = -ENOMEM;
++			goto _err_last;
++		}
++		sif_sctrl = sctrl;
++		sctrl->slc_blk_sz = SIF_SLC_BLOCK_SIZE;
++
++		epub = esp_pub_alloc_mac80211(&func->dev);
++
++		if (epub == NULL) {
++			esp_dbg(ESP_DBG_ERROR, "no mem for epub \n");
++			err = -ENOMEM;
++			goto _err_dma;
++		}
++		epub->sif = (void *) sctrl;
++		epub->sdio_state = ESP_SDIO_STATE_FIRST_INIT;
++		sctrl->epub = epub;
++
++#ifdef USE_EXT_GPIO
++		if (sif_get_ate_config() == 0) {
++			err = ext_gpio_init(epub);
++			if (err) {
++				esp_dbg(ESP_DBG_ERROR,
++					"ext_irq_work_init failed %d\n",
++					err);
++				goto _err_epub;
++			}
++		}
++#endif
++
++	} else {
++		sctrl = sif_sctrl;
++		sif_sctrl = NULL;
++		epub = sctrl->epub;
++		epub->sdio_state = ESP_SDIO_STATE_SECOND_INIT;
++		SET_IEEE80211_DEV(epub->hw, &func->dev);
++		epub->dev = &func->dev;
++	}
++
++	sctrl->func = func;
++	sdio_set_drvdata(func, sctrl);
++
++	sctrl->id = id;
++	sctrl->off = true;
++
++	/* give us some time to enable, in ms */
++	func->enable_timeout = 100;
++
++	err = esdio_power_on(sctrl);
++	esp_dbg(ESP_DBG_TRACE, " %s >> power_on err %d \n", __func__, err);
++
++	if (err) {
++		if (epub->sdio_state == ESP_SDIO_STATE_FIRST_INIT)
++			goto _err_ext_gpio;
++		else
++			goto _err_second_init;
++	}
++	check_target_id(epub);
++
++	sdio_claim_host(func);
++
++	err = sdio_set_block_size(func, sctrl->slc_blk_sz);
++
++	if (err) {
++		esp_dbg(ESP_DBG_ERROR,
++			"Set sdio block size %d failed: %d)\n",
++			sctrl->slc_blk_sz, err);
++		sdio_release_host(func);
++		if (epub->sdio_state == ESP_SDIO_STATE_FIRST_INIT)
++			goto _err_off;
++		else
++			goto _err_second_init;
++	}
++
++	sdio_release_host(func);
++
++#ifdef LOWER_CLK
++	/* fix clock for dongle */
++	sif_set_clock(func, 23);
++#endif				//LOWER_CLK
++
++	err = esp_pub_init_all(epub);
++
++	if (err) {
++		esp_dbg(ESP_DBG_ERROR, "esp_init_all failed: %d\n", err);
++		if (epub->sdio_state == ESP_SDIO_STATE_FIRST_INIT) {
++			err = 0;
++			goto _err_first_init;
++		}
++		if (epub->sdio_state == ESP_SDIO_STATE_SECOND_INIT)
++			goto _err_second_init;
++	}
++
++	esp_dbg(ESP_DBG_TRACE, " %s return  %d\n", __func__, err);
++	if (epub->sdio_state == ESP_SDIO_STATE_FIRST_INIT) {
++		esp_dbg(ESP_DBG_TRACE, "first normal exit\n");
++		epub->sdio_state = ESP_SDIO_STATE_FIRST_NORMAL_EXIT;
++		/* Rescan the esp8089 after loading the initial firmware */
++		sdio_claim_host(func);
++		mmc_sw_reset(func->card);
++		sdio_release_host(func);
++		msleep(10);
++	}
++
++	return err;
++
++      _err_off:
++	esdio_power_off(sctrl);
++      _err_ext_gpio:
++#ifdef USE_EXT_GPIO
++	if (sif_get_ate_config() == 0)
++		ext_gpio_deinit();
++      _err_epub:
++#endif
++	esp_pub_dealloc_mac80211(epub);
++      _err_dma:
++	kfree(sctrl->dma_buffer);
++      _err_last:
++	kfree(sctrl);
++      _err_first_init:
++	if (epub && epub->sdio_state == ESP_SDIO_STATE_FIRST_INIT) {
++		esp_dbg(ESP_DBG_ERROR, "first error exit\n");
++		epub->sdio_state = ESP_SDIO_STATE_FIRST_ERROR_EXIT;
++	}
++	return err;
++      _err_second_init:
++	epub->sdio_state = ESP_SDIO_STATE_SECOND_ERROR_EXIT;
++	esp_sdio_remove(func);
++	return err;
++}
++
++static void esp_sdio_remove(struct sdio_func *func)
++{
++	struct esp_sdio_ctrl *sctrl = NULL;
++	struct esp_pub *epub = NULL;
++
++	esp_dbg(ESP_DBG_TRACE, "%s enter\n", __func__);
++
++	sctrl = sdio_get_drvdata(func);
++
++	if (sctrl == NULL) {
++		esp_dbg(ESP_DBG_ERROR, "%s no sctrl\n", __func__);
++		return;
++	}
++
++	do {
++		epub = sctrl->epub;
++		if (epub == NULL) {
++			esp_dbg(ESP_DBG_ERROR, "%s epub null\n", __func__);
++			break;
++		}
++		if (epub->sdio_state != ESP_SDIO_STATE_FIRST_NORMAL_EXIT) {
++			if (epub->sip) {
++				sip_detach(epub->sip);
++				epub->sip = NULL;
++				esp_dbg(ESP_DBG_TRACE,
++					"%s sip detached \n", __func__);
++			}
++#ifdef USE_EXT_GPIO
++			if (sif_get_ate_config() == 0)
++				ext_gpio_deinit();
++#endif
++		} else {
++			//sif_disable_target_interrupt(epub);
++			atomic_set(&epub->sip->state, SIP_STOP);
++			sif_disable_irq(epub);
++		}
++
++		if (epub->sdio_state != ESP_SDIO_STATE_FIRST_NORMAL_EXIT) {
++			esp_pub_dealloc_mac80211(epub);
++			esp_dbg(ESP_DBG_TRACE, "%s dealloc mac80211 \n",
++				__func__);
++
++			if (sctrl->dma_buffer) {
++				kfree(sctrl->dma_buffer);
++				sctrl->dma_buffer = NULL;
++				esp_dbg(ESP_DBG_TRACE,
++					"%s free dma_buffer \n", __func__);
++			}
++
++			kfree(sctrl);
++		}
++
++	} while (0);
++
++	sdio_set_drvdata(func, NULL);
++
++	/*
++	 * Reset on sdio remove to leave the hardware in cold state,
++	 * so a new module insertion will be possible
++	 */
++	if (epub->sdio_state == ESP_SDIO_STATE_SECOND_INIT) {
++		sdio_claim_host(func);
++		mmc_hw_reset(func->card);
++		sdio_release_host(func);
++		mdelay(10);
++	}
++
++	esp_dbg(ESP_DBG_TRACE, "eagle sdio remove complete\n");
++}
++
++static int esp_sdio_suspend(struct device *dev)
++{
++	struct sdio_func *func = dev_to_sdio_func(dev);
++	struct esp_sdio_ctrl *sctrl = sdio_get_drvdata(func);
++	struct esp_pub *epub = sctrl->epub;
++
++	printk("%s", __func__);
++	atomic_set(&epub->ps.state, ESP_PM_ON);
++
++	do {
++		u32 sdio_flags = 0;
++		int ret = 0;
++		sdio_flags = sdio_get_host_pm_caps(func);
++
++		if (!(sdio_flags & MMC_PM_KEEP_POWER)) {
++			printk
++			    ("%s can't keep power while host is suspended\n",
++			     __func__);
++		}
++
++		/* keep power while host suspended */
++		ret = sdio_set_host_pm_flags(func, MMC_PM_KEEP_POWER);
++		if (ret) {
++			printk("%s error while trying to keep power\n",
++			       __func__);
++		}
++	} while (0);
++
++
++	return 0;
++
++}
++
++static int esp_sdio_resume(struct device *dev)
++{
++	esp_dbg(ESP_DBG_ERROR, "%s", __func__);
++
++	return 0;
++}
++
++static const struct dev_pm_ops esp_sdio_pm_ops = {
++	.suspend = esp_sdio_suspend,
++	.resume = esp_sdio_resume,
++};
++
++static struct sdio_driver esp_sdio_driver = {
++	.name = "eagle_sdio",
++	.id_table = esp_sdio_devices,
++	.probe = esp_sdio_probe,
++	.remove = esp_sdio_remove,
++	.drv = {
++		.pm = &esp_sdio_pm_ops,
++		.of_match_table = esp_of_match_table,
++	},
++};
++
++static int /*__init*/ esp_sdio_init(void)
++{
++
++	esp_debugfs_init();
++	sdio_register_driver(&esp_sdio_driver);
++
++	msleep(1000);
++
++	sdio_unregister_driver(&esp_sdio_driver);
++	msleep(100);
++	sdio_register_driver(&esp_sdio_driver);
++
++	return 0;
++}
++
++static void /*__exit*/ esp_sdio_exit(void)
++{
++	sdio_unregister_driver(&esp_sdio_driver);
++	esp_debugfs_exit();
++}
++
++MODULE_DEVICE_TABLE(sdio, esp_sdio_devices);
++MODULE_DEVICE_TABLE(of, esp_of_match_table);
++MODULE_AUTHOR("Espressif System");
++MODULE_DESCRIPTION
++    ("Driver for SDIO interconnected eagle low-power WLAN devices");
++MODULE_LICENSE("GPL");
++
++module_init(esp_sdio_init);
++module_exit(esp_sdio_exit);
+diff --git a/drivers/net/wireless/esp8089/sip2_common.h b/drivers/net/wireless/esp8089/sip2_common.h
+new file mode 100644
+index 000000000000..d46e87589b0b
+--- /dev/null
++++ b/drivers/net/wireless/esp8089/sip2_common.h
+@@ -0,0 +1,475 @@
++/*
++ *  Copyright (c) 2010 - 2014 Espressif System.
++ *
++ *   Common definitions of Serial Interconnctor Protocol
++ *
++ *   little endian
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++
++#ifndef _SIP2_COMMON_H
++#define _SIP2_COMMON_H
++
++#ifdef __ets__
++#include "utils.h"
++#endif /*__ets__*/
++
++/* max 16 types */
++typedef enum {
++	SIP_CTRL = 0,
++	SIP_DATA,
++	SIP_DATA_AMPDU
++} SIP_TYPE;
++
++typedef enum {
++	SIP_TX_CTRL_BUF = 0,	/* from host */
++	SIP_RX_CTRL_BUF,	/* to host */
++	SIP_TX_DATA_BUF,	/* from host */
++	SIP_RX_DATA_BUF		/* to host */
++} SIP_BUF_TYPE;
++
++enum sip_cmd_id {
++	SIP_CMD_GET_VER = 0,
++	SIP_CMD_WRITE_MEMORY,	//1 ROM code
++	SIP_CMD_READ_MEMORY,	//2
++	SIP_CMD_WRITE_REG,	//3 ROM code
++	SIP_CMD_READ_REG,	//4
++	SIP_CMD_BOOTUP,		//5 ROM code
++	SIP_CMD_COPYBACK,	//6
++	SIP_CMD_INIT,		//7
++	SIP_CMD_SCAN,		//8
++	SIP_CMD_SETKEY,		//9
++	SIP_CMD_CONFIG,		//10
++	SIP_CMD_BSS_INFO_UPDATE,	//11
++	SIP_CMD_LOOPBACK,	//12  ROM code
++	//do not add cmd before this line
++	SIP_CMD_SET_WMM_PARAM,
++	SIP_CMD_AMPDU_ACTION,
++	SIP_CMD_HB_REQ,		//15
++	SIP_CMD_RESET_MAC,	//16
++	SIP_CMD_PRE_DOWN,	//17
++	SIP_CMD_SLEEP,		/* for sleep testing */
++	SIP_CMD_WAKEUP,		/* for sleep testing */
++	SIP_CMD_DEBUG,		/* for general testing */
++	SIP_CMD_GET_FW_VER,	/* get fw rev. */
++	SIP_CMD_SETVIF,
++	SIP_CMD_SETSTA,
++	SIP_CMD_PS,
++	SIP_CMD_ATE,
++	SIP_CMD_SUSPEND,
++	SIP_CMD_RECALC_CREDIT,
++	SIP_CMD_MAX,
++};
++
++enum {
++	SIP_EVT_TARGET_ON = 0,	//
++	SIP_EVT_BOOTUP,		//1 in ROM code
++	SIP_EVT_COPYBACK,	//2
++	SIP_EVT_SCAN_RESULT,	//3
++	SIP_EVT_TX_STATUS,	//4
++	SIP_EVT_CREDIT_RPT,	//5, in ROM code
++	SIP_EVT_ERROR,		//6
++	SIP_EVT_LOOPBACK,	//7, in ROM code
++	SIP_EVT_SNPRINTF_TO_HOST,	//8  in ROM code
++	//do not add evt before this line
++	SIP_EVT_HB_ACK,		//9
++	SIP_EVT_RESET_MAC_ACK,	//10
++	SIP_EVT_WAKEUP,		//11        /* for sleep testing */
++	SIP_EVT_DEBUG,		//12          /* for general testing */
++	SIP_EVT_PRINT_TO_HOST,	//13
++	SIP_EVT_TRC_AMPDU,	//14
++	SIP_EVT_ROC,		//15
++	SIP_EVT_RESETTING,
++	SIP_EVT_ATE,
++	SIP_EVT_EP,
++	SIP_EVT_INIT_EP,
++	SIP_EVT_SLEEP,
++	SIP_EVT_TXIDLE,
++	SIP_EVT_NOISEFLOOR,
++	SIP_EVT_MAX
++};
++
++#define SIP_IFIDX_MASK 0xf0
++#define SIP_IFIDX_S 4
++#define SIP_TYPE_MASK 0x0f
++#define SIP_TYPE_S 0
++
++#define SIP_HDR_GET_IFIDX(fc0) (((fc0) & SIP_IFIDX_MASK) >> SIP_IFIDX_S)
++#define SIP_HDR_SET_IFIDX(fc0, ifidx) ( (fc0) = ((fc0) & ~SIP_IFIDX_MASK) | ((ifidx) << SIP_IFIDX_S & SIP_IFIDX_MASK) )
++#define SIP_HDR_GET_TYPE(fc0) ((fc0) & SIP_TYPE_MASK )
++/* assume type field is cleared */
++#define SIP_HDR_SET_TYPE(fc0, type) ((fc0) = ((fc0) & ~ SIP_TYPE_MASK) | ((type) & SIP_TYPE_MASK))
++
++/* sip 2.0, not hybrid header so far */
++#define SIP_HDR_IS_CTRL(hdr) (SIP_HDR_GET_TYPE((hdr)->fc[0]) == SIP_CTRL)
++#define SIP_HDR_IS_DATA(hdr) (SIP_HDR_GET_TYPE((hdr)->fc[0]) == SIP_DATA)
++#define SIP_HDR_IS_AMPDU(hdr) (SIP_HDR_GET_TYPE((hdr)->fc[0]) == SIP_DATA_AMPDU)
++
++/* fc[1] flags, only for data pkt. Ctrl pkts use fc[1] as eventID */
++#define SIP_HDR_SET_FLAGS(hdr, flags) ((hdr)->fc[1] |= (flags))
++#define SIP_HDR_F_MORE_PKT 0x1
++#define SIP_HDR_F_NEED_CRDT_RPT 0x2
++#define SIP_HDR_F_SYNC 0x4
++#define SIP_HDR_F_SYNC_RESET 0x8
++#define SIP_HDR_F_PM_TURNING_ON 0x10
++#define SIP_HDR_F_PM_TURNING_OFF 0x20
++
++#define SIP_HDR_NEED_CREDIT_UPDATE(hdr) ((hdr)->fc[1] & SIP_HDR_F_NEED_CRDT_RPT)
++#define SIP_HDR_IS_MORE_PKT(hdr) ((hdr)->fc[1] & SIP_HDR_F_MORE_PKT)
++#define SIP_HDR_IS_CRDT_RPT(hdr) ((hdr)->fc[1] & SIP_HDR_F_CRDT_RPT)
++#define SIP_HDR_IS_SYNC(hdr) ((hdr)->fc[1] & SIP_HDR_F_SYNC)
++#define SIP_HDR_IS_SYNC_RESET(hdr) ((hdr)->fc[1] & SIP_HDR_F_SYNC_RESET)
++#define SIP_HDR_IS_SYNC_PKT(hdr) (SIP_HDR_IS_SYNC(hdr) | SIP_HDR_IS_SYNC_RESET(hdr))
++#define SIP_HDR_SET_SYNC(hdr) SIP_HDR_SET_FLAGS((hdr), SIP_HDR_F_SYNC)
++#define SIP_HDR_SET_SYNC_RESET(hdr) SIP_HDR_SET_FLAGS((hdr), SIP_HDR_F_SYNC_RESET)
++#define SIP_HDR_SET_MORE_PKT(hdr) SIP_HDR_SET_FLAGS((hdr), SIP_HDR_F_MORE_PKT)
++#define SIP_HDR_SET_PM_TURNING_ON(hdr) SIP_HDR_SET_FLAGS((hdr), SIP_HDR_F_PM_TURNING_ON)
++#define SIP_HDR_IS_PM_TURNING_ON(hdr) ((hdr)->fc[1] & SIP_HDR_F_PM_TURNING_ON)
++#define SIP_HDR_SET_PM_TURNING_OFF(hdr) SIP_HDR_SET_FLAGS((hdr), SIP_HDR_F_PM_TURNING_OFF)
++#define SIP_HDR_IS_PM_TURNING_OFF(hdr) ((hdr)->fc[1] & SIP_HDR_F_PM_TURNING_OFF)
++
++/*
++ * fc[0]: first 4bit: ifidx; last 4bit: type
++ * fc[1]: flags
++ *
++ *   Don't touch the header definitons
++ */
++struct sip_hdr_min {
++	u8 fc[2];
++	__le16 len;
++} __packed;
++
++/* not more than 4byte long */
++struct sip_tx_data_info {
++	u8 tid;
++	u8 ac;
++	u8 p2p:1, enc_flag:7;
++	u8 hw_kid;
++} __packed;
++
++/* NB: this structure should be not more than 4byte !! */
++struct sip_tx_info {
++	union {
++		u32 cmdid;
++		struct sip_tx_data_info dinfo;
++	} u;
++} __packed;
++
++struct sip_hdr {
++	u8 fc[2];		//fc[0]: type and ifidx ; fc[1] is eventID if the first ctrl pkt in the chain. data pkt still can use fc[1] to set flag
++	__le16 len;
++	union {
++		volatile u32 recycled_credits;	/* last 12bits is credits, first 20 bits is actual length of the first pkt in the chain */
++		struct sip_tx_info tx_info;
++	} u;
++	u32 seq;
++} __packed;
++
++#define h_credits u.recycled_credits
++#define c_evtid fc[1]
++#define c_cmdid u.tx_info.u.cmdid
++#define d_ac u.tx_info.u.dinfo.ac
++#define d_tid  u.tx_info.u.dinfo.tid
++#define d_p2p   u.tx_info.u.dinfo.p2p
++#define d_enc_flag u.tx_info.u.dinfo.enc_flag
++#define d_hw_kid   u.tx_info.u.dinfo.hw_kid
++
++#define SIP_CREDITS_MASK  0xfff	/* last 12 bits */
++
++#ifdef HOST_RC
++
++#define RC_CNT_MASK 0xf
++
++struct sip_rc_status {
++	u32 rc_map;
++	union {
++		u32 rc_cnt1:4, rc_cnt2:4, rc_cnt3:4, rc_cnt4:4, rc_cnt5:4;
++
++		u32 rc_cnt_store;
++	};
++};
++
++/* copy from mac80211.h */
++struct sip_tx_rc {
++	struct ieee80211_tx_rate rates[IEEE80211_TX_MAX_RATES];
++	s8 rts_cts_rate_idx;
++};
++#endif				/* HOST_RC */
++
++#define SIP_HDR_MIN_LEN 4
++#define SIP_HDR_LEN		sizeof(struct sip_hdr)
++#define SIP_CTRL_HDR_LEN 	SIP_HDR_LEN	/* same as sip_hdr in sip2 design */
++#define SIP_BOOT_BUF_SIZE 256
++#define SIP_CTRL_BUF_SZ 256	/* too much?? */
++#define SIP_CTRL_BUF_N 6
++#define SIP_CTRL_TXBUF_N 2
++#define SIP_CTRL_RXBUF_N 4
++
++/* WAR for mblk */
++#define SIP_RX_ADDR_PREFIX_MASK 0xfc000000
++#define SIP_RX_ADDR_SHIFT 6	/* [31:5],  shift 6 bits */
++
++struct sip_cmd_write_memory {
++	u32 addr;
++	u32 len;
++} __packed;
++
++struct sip_cmd_read_memory {
++	u32 addr;
++	u32 len;
++} __packed;
++
++struct sip_cmd_write_reg {
++	u32 addr;
++	u32 val;
++} __packed;
++
++struct sip_cmd_bootup {
++	u32 boot_addr;
++} __packed;
++
++struct sip_cmd_loopback {
++	u32 txlen;		//host to target packet len, 0 means no txpacket
++	u32 rxlen;		//target to host packet len, 0 means no rxpacket
++	u32 pack_id;		//sequence of packet
++} __packed;
++
++struct sip_evt_loopback {
++	u32 txlen;		//host to target packet len, 0 means no txpacket
++	u32 rxlen;		//target to host packet len, 0 means no rxpacket
++	u32 pack_id;		//sequence of packet
++} __packed;
++
++struct sip_cmd_copyback {
++	u32 addr;
++	u32 len;
++} __packed;
++
++struct sip_cmd_scan {
++//        u8  ssid[32];
++	u8 ssid_len;
++//        u8 hw_channel[14];
++	u8 n_channels;
++	u8 ie_len;
++	u8 aborted;
++} __packed;			// ie[] append at the end
++
++
++#ifndef ETH_ALEN
++#define ETH_ALEN 6
++#endif				/* ETH_ALEN */
++
++struct sip_cmd_setkey {
++	u8 bssid_no;
++	u8 addr[ETH_ALEN];
++	u8 alg;
++	u8 keyidx;
++	u8 hw_key_idx;
++	u8 flags;
++	u8 keylen;
++	u8 key[32];
++} __packed;
++
++struct sip_cmd_config {
++	u16 center_freq;
++	u16 duration;
++} __packed;
++
++struct sip_cmd_bss_info_update {
++	u8 bssid[ETH_ALEN];
++	u16 isassoc;
++	u32 beacon_int;
++	u8 bssid_no;
++} __packed;
++
++struct sip_evt_bootup {
++	u16 tx_blksz;
++	u8 mac_addr[ETH_ALEN];
++	/* anything else ? */
++} __packed;
++
++struct sip_cmd_setvif {
++	u8 index;
++	u8 mac[ETH_ALEN];
++	u8 set;
++	u8 op_mode;
++	u8 is_p2p;
++} __packed;
++
++enum esp_ieee80211_phytype {
++	ESP_IEEE80211_T_CCK = 0,
++	ESP_IEEE80211_T_OFDM = 1,
++	ESP_IEEE80211_T_HT20_L = 2,
++	ESP_IEEE80211_T_HT20_S = 3,
++};
++
++struct sip_cmd_setsta {
++	u8 ifidx;
++	u8 index;
++	u8 set;
++	u8 phymode;
++	u8 mac[ETH_ALEN];
++	u16 aid;
++	u8 ampdu_factor;
++	u8 ampdu_density;
++	u16 resv;
++} __packed;
++
++struct sip_cmd_ps {
++	u8 dtim_period;
++	u8 max_sleep_period;
++	u8 on;
++	u8 resv;
++} __packed;
++
++struct sip_cmd_suspend {
++	u8 suspend;
++	u8 resv[3];
++} __packed;
++
++#define SIP_DUMP_RPBM_ERR	BIT(0)
++#define SIP_RXABORT_FIXED	BIT(1)
++#define SIP_SUPPORT_BGSCAN	BIT(2)
++struct sip_evt_bootup2 {
++	u16 tx_blksz;
++	u8 mac_addr[ETH_ALEN];
++	u16 rx_blksz;
++	u8 credit_to_reserve;
++	u8 options;
++	s16 noise_floor;
++	u8 resv[2];
++	/* anything else ? */
++} __packed;
++
++typedef enum {
++	TRC_TX_AMPDU_STOPPED = 1,
++	TRC_TX_AMPDU_OPERATIONAL,
++	TRC_TX_AMPDU_WAIT_STOP,
++	TRC_TX_AMPDU_WAIT_OPERATIONAL,
++	TRC_TX_AMPDU_START,
++} trc_ampdu_state_t;
++
++struct sip_evt_trc_ampdu {
++	u8 state;
++	u8 tid;
++	u8 addr[ETH_ALEN];
++} __packed;
++
++struct sip_cmd_set_wmm_params {
++	u8 aci;
++	u8 aifs;
++	u8 ecw_min;
++	u8 ecw_max;
++	u16 txop_us;
++} __packed;
++
++#define SIP_AMPDU_RX_START 0
++#define SIP_AMPDU_RX_STOP 1
++#define SIP_AMPDU_TX_OPERATIONAL 2
++#define SIP_AMPDU_TX_STOP 3
++struct sip_cmd_ampdu_action {
++	u8 action;
++	u8 index;
++	u8 tid;
++	u8 win_size;
++	u16 ssn;
++	u8 addr[ETH_ALEN];
++} __packed;
++
++#define SIP_TX_ST_OK 0
++#define SIP_TX_ST_NOEB 1
++#define SIP_TX_ST_ACKTO 2
++#define SIP_TX_ST_ENCERR 3
++
++//NB: sip_tx_status must be 4 bytes aligned
++struct sip_tx_status {
++	u32 sip_seq;
++#ifdef HOST_RC
++	struct sip_rc_status rcstatus;
++#endif				/* HOST_RC */
++	u8 errno;		/* success or failure code */
++	u8 rate_index;
++	char ack_signal;
++	u8 pad;
++} __packed;
++
++struct sip_evt_tx_report {
++	u32 pkts;
++	struct sip_tx_status status[0];
++} __packed;
++
++struct sip_evt_tx_mblk {
++	u32 mblk_map;
++} __packed;
++
++struct sip_evt_scan_report {
++	u16 scan_id;
++	u16 aborted;
++} __packed;
++
++struct sip_evt_roc {
++	u16 state;		//start:1, end :0
++	u16 is_ok;
++} __packed;
++
++struct sip_evt_txidle {
++	u32 last_seq;
++} __packed;
++
++struct sip_evt_noisefloor {
++	s16 noise_floor;
++	u16 pad;
++} __packed;
++/*
++ *  for mblk direct memory access, no need for sip_hdr. tx: first 2k for contrl msg,
++ *  rest of 14k for data.  rx, same.
++ */
++#ifdef TEST_MODE
++
++struct sip_cmd_sleep {
++	u32 sleep_mode;
++	u32 sleep_tm_ms;
++	u32 wakeup_tm_ms;	//zero: after receive bcn, then sleep, nozero: delay nozero ms to sleep
++	u32 sleep_times;	//zero: always sleep, nozero: after nozero number sleep/wakeup, then end up sleep
++} __packed;
++
++struct sip_cmd_wakeup {
++	u32 check_data;		//0:copy to event
++} __packed;
++
++struct sip_evt_wakeup {
++	u32 check_data;
++} __packed;
++
++//general debug command
++struct sip_cmd_debug {
++	u32 cmd_type;
++	u32 para_num;
++	u32 para[10];
++} __packed;
++
++struct sip_evt_debug {
++	u16 len;
++	u32 results[12];
++	u16 pad;
++} __packed;
++
++struct sip_cmd_ate {
++	//u8  len;
++	u8 cmdstr[0];
++} __packed;
++
++
++
++#endif				//ifdef TEST_MODE
++
++#endif				/* _SIP_COMMON_H_ */
+diff --git a/drivers/net/wireless/esp8089/slc_host_register.h b/drivers/net/wireless/esp8089/slc_host_register.h
+new file mode 100644
+index 000000000000..2cdb2c856d15
+--- /dev/null
++++ b/drivers/net/wireless/esp8089/slc_host_register.h
+@@ -0,0 +1,271 @@
++//Generated at 2012-10-23 20:11:08
++/*
++ *  Copyright (c) 2011 Espressif System
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++
++#ifndef SLC_HOST_REGISTER_H_INCLUDED
++#define SLC_HOST_REGISTER_H_INCLUDED
++
++/* #define REG_SLC_HOST_BASE  0x00000000 */
++/* skip the token1, since reading it will clean the credit */
++#define REG_SLC_HOST_BASE  0x00000000
++#define REG_SLC_BASE  0x00000000
++
++
++#define SLC_HOST_PF                          (REG_SLC_HOST_BASE + 0x0)
++#define SLC_HOST_TOKEN_RDATA                 (REG_SLC_HOST_BASE + 0x4)
++#define SLC_HOST_RX_PF_EOF 0x0000000F
++#define SLC_HOST_RX_PF_EOF_S                 28
++#define SLC_HOST_TOKEN1 0x00000FFF
++#define SLC_HOST_TOKEN1_S 16
++#define SLC_HOST_RX_PF_VALID (BIT(15))
++#define SLC_HOST_TOKEN0               0x00000FFF
++#define SLC_HOST_TOKEN0_S 0
++
++#define SLC_HOST_TOKEN0_MASK SLC_HOST_TOKEN0
++
++#define SLC_HOST_INT_RAW                     (REG_SLC_HOST_BASE + 0x8)
++#define SLC_HOST_EXT_BIT3_INT_RAW (BIT(22))
++#define SLC_HOST_EXT_BIT2_INT_RAW (BIT(21))
++#define SLC_HOST_EXT_BIT1_INT_RAW (BIT(20))
++#define SLC_HOST_RXFIFO_NOT_EMPTY_INT_RAW (BIT(19))
++#define SLC_HOST_RX_PF_VALID_INT_RAW (BIT(18))
++#define SLC_HOST_TX_OVF_INT_RAW (BIT(17))
++#define SLC_HOST_RX_UDF_INT_RAW (BIT(16))
++#define SLC_HOST_TX_START_INT_RAW (BIT(15))
++#define SLC_HOST_RX_START_INT_RAW (BIT(14))
++#define SLC_HOST_RX_EOF_INT_RAW (BIT(13))
++#define SLC_HOST_RX_SOF_INT_RAW (BIT(12))
++#define SLC_HOST_TOKEN1_0TO1_INT_RAW (BIT(11))
++#define SLC_HOST_TOKEN0_0TO1_INT_RAW (BIT(10))
++#define SLC_HOST_TOKEN1_1TO0_INT_RAW (BIT(9))
++#define SLC_HOST_TOKEN0_1TO0_INT_RAW (BIT(8))
++#define SLC_HOST_TOHOST_BIT7_INT_RAW (BIT(7))
++#define SLC_HOST_TOHOST_BIT6_INT_RAW (BIT(6))
++#define SLC_HOST_TOHOST_BIT5_INT_RAW (BIT(5))
++#define SLC_HOST_TOHOST_BIT4_INT_RAW (BIT(4))
++#define SLC_HOST_TOHOST_BIT3_INT_RAW (BIT(3))
++#define SLC_HOST_TOHOST_BIT2_INT_RAW (BIT(2))
++#define SLC_HOST_TOHOST_BIT1_INT_RAW (BIT(1))
++#define SLC_HOST_TOHOST_BIT0_INT_RAW (BIT(0))
++
++#define SLC_HOST_STATE_W0                    (REG_SLC_HOST_BASE + 0xC)
++#define SLC_HOST_STATE3 0x000000FF
++#define SLC_HOST_STATE3_S 24
++#define SLC_HOST_STATE2 0x000000FF
++#define SLC_HOST_STATE2_S 16
++#define SLC_HOST_STATE1 0x000000FF
++#define SLC_HOST_STATE1_S 8
++#define SLC_HOST_STATE0 0x000000FF
++#define SLC_HOST_STATE0_S 0
++
++#define SLC_HOST_STATE_W1                    (REG_SLC_HOST_BASE + 0x10)
++#define SLC_HOST_STATE7 0x000000FF
++#define SLC_HOST_STATE7_S 24
++#define SLC_HOST_STATE6 0x000000FF
++#define SLC_HOST_STATE6_S 16
++#define SLC_HOST_STATE5 0x000000FF
++#define SLC_HOST_STATE5_S 8
++#define SLC_HOST_STATE4 0x000000FF
++#define SLC_HOST_STATE4_S 0
++
++#define SLC_HOST_CONF_W0                     (REG_SLC_HOST_BASE + 0x14)
++#define SLC_HOST_CONF3 0x000000FF
++#define SLC_HOST_CONF3_S 24
++#define SLC_HOST_CONF2 0x000000FF
++#define SLC_HOST_CONF2_S 16
++#define SLC_HOST_CONF1 0x000000FF
++#define SLC_HOST_CONF1_S 8
++#define SLC_HOST_CONF0 0x000000FF
++#define SLC_HOST_CONF0_S 0
++
++#define SLC_HOST_CONF_W1                     (REG_SLC_HOST_BASE + 0x18)
++#define SLC_HOST_CONF7 0x000000FF
++#define SLC_HOST_CONF7_S 24
++#define SLC_HOST_CONF6 0x000000FF
++#define SLC_HOST_CONF6_S 16
++#define SLC_HOST_CONF5 0x000000FF
++#define SLC_HOST_CONF5_S 8
++#define SLC_HOST_CONF4 0x000000FF
++#define SLC_HOST_CONF4_S 0
++
++#define SLC_HOST_INT_ST                      (REG_SLC_HOST_BASE + 0x1C)
++#define SLC_HOST_RX_ST (BIT(23))
++#define SLC_HOST_EXT_BIT3_INT_ST (BIT(22))
++#define SLC_HOST_EXT_BIT2_INT_ST (BIT(21))
++#define SLC_HOST_EXT_BIT1_INT_ST (BIT(20))
++#define SLC_HOST_RXFIFO_NOT_EMPTY_INT_ST (BIT(19))
++#define SLC_HOST_RX_PF_VALID_INT_ST (BIT(18))
++#define SLC_HOST_TX_OVF_INT_ST (BIT(17))
++#define SLC_HOST_RX_UDF_INT_ST (BIT(16))
++#define SLC_HOST_TX_START_INT_ST (BIT(15))
++#define SLC_HOST_RX_START_INT_ST (BIT(14))
++#define SLC_HOST_RX_EOF_INT_ST (BIT(13))
++#define SLC_HOST_RX_SOF_INT_ST (BIT(12))
++#define SLC_HOST_TOKEN1_0TO1_INT_ST (BIT(11))
++#define SLC_HOST_TOKEN0_0TO1_INT_ST (BIT(10))
++#define SLC_HOST_TOKEN1_1TO0_INT_ST (BIT(9))
++#define SLC_HOST_TOKEN0_1TO0_INT_ST (BIT(8))
++#define SLC_HOST_TOHOST_BIT7_INT_ST (BIT(7))
++#define SLC_HOST_TOHOST_BIT6_INT_ST (BIT(6))
++#define SLC_HOST_TOHOST_BIT5_INT_ST (BIT(5))
++#define SLC_HOST_TOHOST_BIT4_INT_ST (BIT(4))
++#define SLC_HOST_TOHOST_BIT3_INT_ST (BIT(3))
++#define SLC_HOST_TOHOST_BIT2_INT_ST (BIT(2))
++#define SLC_HOST_TOHOST_BIT1_INT_ST (BIT(1))
++#define SLC_HOST_TOHOST_BIT0_INT_ST (BIT(0))
++
++#define SLC_HOST_CONF_W2                     (REG_SLC_HOST_BASE + 0x20)
++#define SLC_HOST_CONF11 0x000000FF
++#define SLC_HOST_CONF11_S 24
++#define SLC_HOST_CONF10 0x000000FF
++#define SLC_HOST_CONF10_S 16
++#define SLC_HOST_CONF9 0x000000FF
++#define SLC_HOST_CONF9_S 8
++#define SLC_HOST_CONF8 0x000000FF
++#define SLC_HOST_CONF8_S 0
++
++#define SLC_HOST_CONF_W3                     (REG_SLC_HOST_BASE + 0x24)
++#define SLC_HOST_CONF15 0x000000FF
++#define SLC_HOST_CONF15_S 24
++#define SLC_HOST_CONF14 0x000000FF
++#define SLC_HOST_CONF14_S 16
++#define SLC_HOST_CONF13 0x000000FF
++#define SLC_HOST_CONF13_S 8
++#define SLC_HOST_CONF12 0x000000FF
++#define SLC_HOST_CONF12_S 0
++
++#define SLC_HOST_GEN_TXDONE_INT  BIT(16)
++#define SLC_HOST_GEN_RXDONE_INT  BIT(17)
++
++#define SLC_HOST_CONF_W4                     (REG_SLC_HOST_BASE + 0x28)
++#define SLC_HOST_CONF19 0x000000FF
++#define SLC_HOST_CONF19_S 24
++#define SLC_HOST_CONF18 0x000000FF
++#define SLC_HOST_CONF18_S 16
++#define SLC_HOST_CONF17 0x000000FF
++#define SLC_HOST_CONF17_S 8
++#define SLC_HOST_CONF16 0x000000FF
++#define SLC_HOST_CONF16_S 0
++
++#define SLC_HOST_TOKEN_WDATA                 (REG_SLC_HOST_BASE + 0x2C)
++#define SLC_HOST_TOKEN1_WD 0x00000FFF
++#define SLC_HOST_TOKEN1_WD_S 16
++#define SLC_HOST_TOKEN0_WD 0x00000FFF
++#define SLC_HOST_TOKEN0_WD_S 0
++
++#define SLC_HOST_INT_CLR                     (REG_SLC_HOST_BASE + 0x30)
++#define SLC_HOST_TOKEN1_WR (BIT(31))
++#define SLC_HOST_TOKEN0_WR (BIT(30))
++#define SLC_HOST_TOKEN1_DEC (BIT(29))
++#define SLC_HOST_TOKEN0_DEC (BIT(28))
++#define SLC_HOST_EXT_BIT3_INT_CLR (BIT(22))
++#define SLC_HOST_EXT_BIT2_INT_CLR (BIT(21))
++#define SLC_HOST_EXT_BIT1_INT_CLR (BIT(20))
++#define SLC_HOST_EXT_BIT0_INT_CLR (BIT(19))
++#define SLC_HOST_RX_PF_VALID_INT_CLR (BIT(18))
++#define SLC_HOST_TX_OVF_INT_CLR (BIT(17))
++#define SLC_HOST_RX_UDF_INT_CLR (BIT(16))
++#define SLC_HOST_TX_START_INT_CLR (BIT(15))
++#define SLC_HOST_RX_START_INT_CLR (BIT(14))
++#define SLC_HOST_RX_EOF_INT_CLR (BIT(13))
++#define SLC_HOST_RX_SOF_INT_CLR (BIT(12))
++#define SLC_HOST_TOKEN1_0TO1_INT_CLR (BIT(11))
++#define SLC_HOST_TOKEN0_0TO1_INT_CLR (BIT(10))
++#define SLC_HOST_TOKEN1_1TO0_INT_CLR (BIT(9))
++#define SLC_HOST_TOKEN0_1TO0_INT_CLR (BIT(8))
++#define SLC_HOST_TOHOST_BIT7_INT_CLR (BIT(7))
++#define SLC_HOST_TOHOST_BIT6_INT_CLR (BIT(6))
++#define SLC_HOST_TOHOST_BIT5_INT_CLR (BIT(5))
++#define SLC_HOST_TOHOST_BIT4_INT_CLR (BIT(4))
++#define SLC_HOST_TOHOST_BIT3_INT_CLR (BIT(3))
++#define SLC_HOST_TOHOST_BIT2_INT_CLR (BIT(2))
++#define SLC_HOST_TOHOST_BIT1_INT_CLR (BIT(1))
++#define SLC_HOST_TOHOST_BIT0_INT_CLR (BIT(0))
++
++#define SLC_HOST_INT_ENA                     (REG_SLC_HOST_BASE + 0x34)
++#define SLC_HOST_EXT_BIT3_INT_ENA (BIT(22))
++#define SLC_HOST_EXT_BIT2_INT_ENA (BIT(21))
++#define SLC_HOST_EXT_BIT1_INT_ENA (BIT(20))
++#define SLC_HOST_EXT_BIT0_INT_ENA (BIT(19))
++#define SLC_HOST_RX_PF_VALID_INT_ENA (BIT(18))
++#define SLC_HOST_TX_OVF_INT_ENA (BIT(17))
++#define SLC_HOST_RX_UDF_INT_ENA (BIT(16))
++#define SLC_HOST_TX_START_INT_ENA (BIT(15))
++#define SLC_HOST_RX_START_INT_ENA (BIT(14))
++#define SLC_HOST_RX_EOF_INT_ENA (BIT(13))
++#define SLC_HOST_RX_SOF_INT_ENA (BIT(12))
++#define SLC_HOST_TOKEN1_0TO1_INT_ENA (BIT(11))
++#define SLC_HOST_TOKEN0_0TO1_INT_ENA (BIT(10))
++#define SLC_HOST_TOKEN1_1TO0_INT_ENA (BIT(9))
++#define SLC_HOST_TOKEN0_1TO0_INT_ENA (BIT(8))
++#define SLC_HOST_TOHOST_BIT7_INT_ENA (BIT(7))
++#define SLC_HOST_TOHOST_BIT6_INT_ENA (BIT(6))
++#define SLC_HOST_TOHOST_BIT5_INT_ENA (BIT(5))
++#define SLC_HOST_TOHOST_BIT4_INT_ENA (BIT(4))
++#define SLC_HOST_TOHOST_BIT3_INT_ENA (BIT(3))
++#define SLC_HOST_TOHOST_BIT2_INT_ENA (BIT(2))
++#define SLC_HOST_TOHOST_BIT1_INT_ENA (BIT(1))
++#define SLC_HOST_TOHOST_BIT0_INT_ENA (BIT(0))
++
++#define SLC_HOST_CONF_W5                     (REG_SLC_HOST_BASE + 0x3C)
++#define SLC_HOST_CONF23 0x000000FF
++#define SLC_HOST_CONF23_S 24
++#define SLC_HOST_CONF22 0x000000FF
++#define SLC_HOST_CONF22_S 16
++#define SLC_HOST_CONF21 0x000000FF
++#define SLC_HOST_CONF21_S 8
++#define SLC_HOST_CONF20 0x000000FF
++#define SLC_HOST_CONF20_S 0
++
++#define SLC_HOST_WIN_CMD                     (REG_SLC_HOST_BASE + 0x40)
++
++
++#define SLC_HOST_DATE                         (REG_SLC_HOST_BASE + 0x78)
++#define SLC_HOST_ID                           (REG_SLC_HOST_BASE + 0x7C)
++
++#define SLC_ADDR_WINDOW_CLEAR_MASK   (~(0xf<<12))
++#define SLC_FROM_HOST_ADDR_WINDOW  (0x1<<12)
++#define SLC_TO_HOST_ADDR_WINDOW    (0x3<<12)
++
++#define SLC_SET_FROM_HOST_ADDR_WINDOW(v)   do { \
++        (v) &= 0xffff;    \
++	(v) &= SLC_ADDR_WINDOW_CLEAR_MASK; \
++	(v) |= SLC_FROM_HOST_ADDR_WINDOW; \
++} while (0);
++
++#define SLC_SET_TO_HOST_ADDR_WINDOW(v)   do { \
++        (v) &= 0xffff;    \
++	(v) &= SLC_ADDR_WINDOW_CLEAR_MASK; \
++	(v) |= SLC_TO_HOST_ADDR_WINDOW; \
++} while (0);
++
++#define SLC_INT_ENA                     	(REG_SLC_BASE + 0xC)
++#define SLC_RX_EOF_INT_ENA BIT(17)
++#define SLC_FRHOST_BIT2_INT_ENA BIT(2)
++
++#define SLC_RX_LINK                     	(REG_SLC_BASE + 0x24)
++#define SLC_RXLINK_START BIT(29)
++
++#define SLC_BRIDGE_CONF                     	(REG_SLC_BASE + 0x44)
++#define SLC_TX_PUSH_IDLE_NUM 0xFFFF
++#define SLC_TX_PUSH_IDLE_NUM_S 16
++#define SLC_HDA_MAP_128K BIT(13)
++#define SLC_TX_DUMMY_MODE BIT(12)
++#define SLC_FIFO_MAP_ENA 0x0000000F
++#define SLC_FIFO_MAP_ENA_S 8
++#define SLC_TXEOF_ENA 0x0000003F
++#define SLC_TXEOF_ENA_S
++
++
++#endif				// SLC_HOST_REGISTER_H_INCLUDED
+--
+2.34.1
diff --git a/projects/Rockchip/devices/RK322X/patches/linux/default/linux-4009-rk322x-composite-mmc-clk.patch b/projects/Rockchip/devices/RK322X/patches/linux/default/linux-4009-rk322x-composite-mmc-clk.patch
new file mode 100644
index 0000000000..5e4ecb6e81
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/patches/linux/default/linux-4009-rk322x-composite-mmc-clk.patch
@@ -0,0 +1,37 @@
+From 9e105544fcb63f8f79b199d1b194a36a354519b3 Mon Sep 17 00:00:00 2001
+From: Paolo Sabatino <paolo.sabatino@gmail.com>
+Date: Sun, 2 Apr 2023 10:53:07 +0000
+Subject: [PATCH 2/2] rk322x: better handle mmc/sdio clocks
+
+---
+ drivers/clk/rockchip/clk-rk3228.c | 10 ++++------
+ 1 file changed, 4 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c
+index 996f8bfee..0f690dd84 100644
+--- a/drivers/clk/rockchip/clk-rk3228.c
++++ b/drivers/clk/rockchip/clk-rk3228.c
+@@ -371,17 +371,15 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
+			RK2928_CLKSEL_CON(11), 8, 2, MFLAGS, 0, 8, DFLAGS,
+			RK2928_CLKGATE_CON(2), 11, GFLAGS),
+
+-	COMPOSITE_NODIV(SCLK_SDIO_SRC, "sclk_sdio_src", mux_mmc_src_p, 0,
++	COMPOSITE_DIV_OFFSET(SCLK_SDIO, "sclk_sdio", mux_mmc_src_p, 0,
+			RK2928_CLKSEL_CON(11), 10, 2, MFLAGS,
++			RK2928_CLKSEL_CON(12), 0, 8, DFLAGS,
+			RK2928_CLKGATE_CON(2), 13, GFLAGS),
+-	DIV(SCLK_SDIO, "sclk_sdio", "sclk_sdio_src", 0,
+-			RK2928_CLKSEL_CON(12), 0, 8, DFLAGS),
+
+-	COMPOSITE_NODIV(0, "sclk_emmc_src", mux_mmc_src_p, 0,
++	COMPOSITE_DIV_OFFSET(SCLK_EMMC, "sclk_emmc", mux_mmc_src_p, 0,
+			RK2928_CLKSEL_CON(11), 12, 2, MFLAGS,
++			RK2928_CLKSEL_CON(12), 8, 8, DFLAGS,
+			RK2928_CLKGATE_CON(2), 14, GFLAGS),
+-	DIV(SCLK_EMMC, "sclk_emmc", "sclk_emmc_src", 0,
+-			RK2928_CLKSEL_CON(12), 8, 8, DFLAGS),
+
+	/*
+	 * Clock-Architecture Diagram 2
+--
+2.34.1
diff --git a/projects/Rockchip/devices/RK322X/patches/linux/default/linux-4010-rk322x-gpio-ir-driver.patch b/projects/Rockchip/devices/RK322X/patches/linux/default/linux-4010-rk322x-gpio-ir-driver.patch
new file mode 100644
index 0000000000..848a8c4833
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/patches/linux/default/linux-4010-rk322x-gpio-ir-driver.patch
@@ -0,0 +1,785 @@
+From 13498feb91614d59ebece61d0c278e31529bb8c8 Mon Sep 17 00:00:00 2001
+From: Paolo Sabatino <paolo.sabatino@gmail.com>
+Date: Tue, 10 Oct 2023 21:54:51 +0200
+Subject: [PATCH] rockchip gpio IR driver
+
+---
+ drivers/media/rc/Kconfig       |  11 +
+ drivers/media/rc/Makefile      |   1 +
+ drivers/media/rc/rockchip-ir.c | 723 +++++++++++++++++++++++++++++++++
+ 3 files changed, 735 insertions(+)
+ create mode 100644 drivers/media/rc/rockchip-ir.c
+
+diff --git a/drivers/media/rc/Kconfig b/drivers/media/rc/Kconfig
+index f560fc38895f..b77fa83e90e8 100644
+--- a/drivers/media/rc/Kconfig
++++ b/drivers/media/rc/Kconfig
+@@ -333,6 +333,17 @@ config IR_REDRAT3
+	   To compile this driver as a module, choose M here: the
+	   module will be called redrat3.
+
++config IR_ROCKCHIP_CIR
++	tristate "Rockchip GPIO IR receiver"
++	depends on (OF && GPIOLIB) || COMPILE_TEST
++	help
++	   Say Y here if you want to use the Rockchip IR receiver with
++	   virtual poweroff features provided by rockchip Trust OS
++
++	   To compile this driver as a module, choose M here: the
++	   module will be called rockchip-ir
++
++
+ config IR_SERIAL
+	tristate "Homebrew Serial Port Receiver"
+	depends on HAS_IOPORT
+diff --git a/drivers/media/rc/Makefile b/drivers/media/rc/Makefile
+index a9285266e944..057d5b64c121 100644
+--- a/drivers/media/rc/Makefile
++++ b/drivers/media/rc/Makefile
+@@ -43,6 +43,7 @@ obj-$(CONFIG_IR_MTK) += mtk-cir.o
+ obj-$(CONFIG_IR_NUVOTON) += nuvoton-cir.o
+ obj-$(CONFIG_IR_PWM_TX) += pwm-ir-tx.o
+ obj-$(CONFIG_IR_REDRAT3) += redrat3.o
++obj-$(CONFIG_IR_ROCKCHIP_CIR) += rockchip-ir.o
+ obj-$(CONFIG_IR_SERIAL) += serial_ir.o
+ obj-$(CONFIG_IR_SPI) += ir-spi.o
+ obj-$(CONFIG_IR_STREAMZAP) += streamzap.o
+diff --git a/drivers/media/rc/rockchip-ir.c b/drivers/media/rc/rockchip-ir.c
+new file mode 100644
+index 000000000000..43ade8c4adce
+--- /dev/null
++++ b/drivers/media/rc/rockchip-ir.c
+@@ -0,0 +1,733 @@
++// SPDX-License-Identifier: GPL-2.0-only
++/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
++*/
++
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/interrupt.h>
++#include <linux/gpio/consumer.h>
++#include <linux/slab.h>
++#include <linux/of.h>
++#include <linux/of_gpio.h>
++#include <linux/platform_device.h>
++#include <linux/pinctrl/consumer.h>
++#include <linux/pm_runtime.h>
++#include <linux/pm_qos.h>
++#include <linux/irq.h>
++#include <linux/arm-smccc.h>
++#include <linux/clk.h>
++#include <linux/reboot.h>
++#include <uapi/linux/psci.h>
++#include <media/rc-core.h>
++#include <soc/rockchip/rockchip_sip.h>
++
++#define ROCKCHIP_IR_DEVICE_NAME	"rockchip_ir_recv"
++
++#ifdef CONFIG_64BIT
++#define PSCI_FN_NATIVE(version, name)	PSCI_##version##_FN64_##name
++#else
++#define PSCI_FN_NATIVE(version, name)	PSCI_##version##_FN_##name
++#endif
++
++/*
++* SIP/TEE constants for remote calls
++*/
++#define SIP_REMOTECTL_CFG				0x8200000b
++#define SIP_SUSPEND_MODE		0x82000003
++#define SIP_REMOTECTL_CFG		0x8200000b
++#define SUSPEND_MODE_CONFIG	0x01
++#define WKUP_SOURCE_CONFIG		0x02
++#define PWM_REGULATOR_CONFIG	0x03
++#define GPIO_POWER_CONFIG		0x04
++#define SUSPEND_DEBUG_ENABLE	0x05
++#define APIOS_SUSPEND_CONFIG	0x06
++#define VIRTUAL_POWEROFF		0x07
++
++#define REMOTECTL_SET_IRQ				0xf0
++#define REMOTECTL_SET_PWM_CH			0xf1
++#define REMOTECTL_SET_PWRKEY			0xf2
++#define REMOTECTL_GET_WAKEUP_STATE		0xf3
++#define REMOTECTL_ENABLE				0xf4
++#define REMOTECTL_PWRKEY_WAKEUP			0xdeadbeaf /* wakeup state */
++
++/*
++* PWM Registers
++* Each PWM has its own control registers
++*/
++#define PWM_REG_CNTR	0x00  /* Counter Register */
++#define PWM_REG_HPR		0x04  /* Period Register */
++#define PWM_REG_LPR		0x08  /* Duty Cycle Register */
++#define PWM_REG_CTRL	0x0c  /* Control Register */
++
++/*
++* PWM General registers
++* Registers shared among PWMs
++*/
++#define PWM_REG_INT_EN  0x44
++
++/*REG_CTRL bits definitions*/
++#define PWM_ENABLE		(1 << 0)
++#define PWM_DISABLE		(0 << 0)
++
++/*operation mode*/
++#define PWM_MODE_ONESHOT		(0x00 << 1)
++#define PWM_MODE_CONTINUMOUS	(0x01 << 1)
++#define PWM_MODE_CAPTURE		(0x02 << 1)
++
++/* Channel interrupt enable bit */
++#define PWM_CH_INT_ENABLE(n)		BIT(n)
++
++enum pwm_div {
++	PWM_DIV1	= (0x0 << 12),
++	PWM_DIV2	= (0x1 << 12),
++	PWM_DIV4	= (0x2 << 12),
++	PWM_DIV8	= (0x3 << 12),
++	PWM_DIV16	= (0x4 << 12),
++	PWM_DIV32	= (0x5 << 12),
++	PWM_DIV64	= (0x6 << 12),
++	PWM_DIV128	= (0x7 << 12),
++};
++
++#define PWM_INT_ENABLE		1
++#define PWM_INT_DISABLE		0
++
++struct rockchip_rc_dev {
++	struct rc_dev *rcdev;
++	struct gpio_desc *gpiod;
++	int irq;
++	struct device *pmdev;
++	struct pm_qos_request qos;
++	void __iomem *pwm_base;
++	int pwm_wake_irq;
++	int pwm_id;
++	bool use_shutdown_handler; // if true, installs a shutdown handler and triggers virtual poweroff
++	bool use_suspend_handler; // if true, virtual poweroff is used as suspend mode otherwise use as regular suspend
++	struct pinctrl *pinctrl;
++	struct pinctrl_state *pinctrl_state_default;
++	struct pinctrl_state *pinctrl_state_suspend;
++};
++
++static struct arm_smccc_res __invoke_sip_fn_smc(unsigned long function_id,
++												unsigned long arg0,
++												unsigned long arg1,
++												unsigned long arg2)
++{
++	struct arm_smccc_res res;
++
++	arm_smccc_smc(function_id, arg0, arg1, arg2, 0, 0, 0, 0, &res);
++
++	return res;
++}
++
++int sip_smc_remotectl_config(u32 func, u32 data)
++{
++	struct arm_smccc_res res;
++
++	res = __invoke_sip_fn_smc(SIP_REMOTECTL_CFG, func, data, 0);
++
++	return res.a0;
++}
++
++int sip_smc_set_suspend_mode(u32 ctrl, u32 config1, u32 config2)
++{
++	struct arm_smccc_res res;
++
++	res = __invoke_sip_fn_smc(SIP_SUSPEND_MODE, ctrl, config1, config2);
++	return res.a0;
++}
++
++int sip_smc_virtual_poweroff(void)
++{
++	struct arm_smccc_res res;
++
++	res = __invoke_sip_fn_smc(PSCI_FN_NATIVE(1_0, SYSTEM_SUSPEND), 0, 0, 0);
++	return res.a0;
++}
++
++static irqreturn_t rockchip_ir_recv_irq(int irq, void *dev_id)
++{
++	int val;
++	struct rockchip_rc_dev *gpio_dev = dev_id;
++	struct device *pmdev = gpio_dev->pmdev;
++
++	/*
++	* For some cpuidle systems, not all:
++	* Respond to interrupt taking more latency when cpu in idle.
++	* Invoke asynchronous pm runtime get from interrupt context,
++	* this may introduce a millisecond delay to call resume callback,
++	* where to disable cpuilde.
++	*
++	* Two issues lead to fail to decode first frame, one is latency to
++	* respond to interrupt, another is delay introduced by async api.
++	*/
++	if (pmdev)
++		pm_runtime_get(pmdev);
++
++	val = gpiod_get_value(gpio_dev->gpiod);
++	if (val >= 0)
++		ir_raw_event_store_edge(gpio_dev->rcdev, val == 1);
++
++	if (pmdev) {
++		pm_runtime_mark_last_busy(pmdev);
++		pm_runtime_put_autosuspend(pmdev);
++	}
++
++	return IRQ_HANDLED;
++}
++
++static void rockchip_pwm_int_ctrl(struct rockchip_rc_dev *gpio_dev, bool enable)
++{
++
++	void __iomem *pwm_base = gpio_dev->pwm_base;
++	struct device *dev = &gpio_dev->rcdev->dev;
++	int pwm_id = gpio_dev->pwm_id;
++
++	void __iomem *reg_int_ctrl;
++	int val;
++
++	reg_int_ctrl= pwm_base - (0x10 * pwm_id) + PWM_REG_INT_EN;
++
++	val = readl_relaxed(reg_int_ctrl);
++
++	if (enable) {
++		val |= PWM_CH_INT_ENABLE(pwm_id);
++		dev_info(dev, "PWM interrupt enabled, register value %x\n", val);
++	} else {
++		val &= ~PWM_CH_INT_ENABLE(pwm_id);
++		dev_info(dev, "PWM interrupt disabled, register value %x\n", val);
++	}
++
++	writel_relaxed(val, reg_int_ctrl);
++
++}
++
++static int rockchip_pwm_hw_init(struct rockchip_rc_dev *gpio_dev)
++{
++
++	void __iomem *pwm_base = gpio_dev->pwm_base;
++	int val;
++
++	//1. disabled pwm
++	val = readl_relaxed(pwm_base + PWM_REG_CTRL);
++	val = (val & 0xFFFFFFFE) | PWM_DISABLE;
++	writel_relaxed(val, pwm_base + PWM_REG_CTRL);
++
++	//2. capture mode
++	val = readl_relaxed(pwm_base + PWM_REG_CTRL);
++	val = (val & 0xFFFFFFF9) | PWM_MODE_CAPTURE;
++	writel_relaxed(val, pwm_base + PWM_REG_CTRL);
++
++	//set clk div, clk div to 64
++	val = readl_relaxed(pwm_base + PWM_REG_CTRL);
++	val = (val & 0xFF0001FF) | PWM_DIV64;
++	writel_relaxed(val, pwm_base + PWM_REG_CTRL);
++
++	//4. enabled pwm int
++	rockchip_pwm_int_ctrl(gpio_dev, true);
++
++	//5. enabled pwm
++	val = readl_relaxed(pwm_base + PWM_REG_CTRL);
++	val = (val & 0xFFFFFFFE) | PWM_ENABLE;
++	writel_relaxed(val, pwm_base + PWM_REG_CTRL);
++
++	return 0;
++
++}
++
++static int rockchip_pwm_hw_stop(struct rockchip_rc_dev *gpio_dev)
++{
++
++	void __iomem *pwm_base = gpio_dev->pwm_base;
++	int val;
++
++	//disable pwm interrupt
++	rockchip_pwm_int_ctrl(gpio_dev, false);
++
++	//disable pwm
++	val = readl_relaxed(pwm_base + PWM_REG_CTRL);
++	val = (val & 0xFFFFFFFE) | PWM_DISABLE;
++	writel_relaxed(val, pwm_base + PWM_REG_CTRL);
++
++	return 0;
++
++}
++
++static int rockchip_pwm_sip_wakeup_init(struct rockchip_rc_dev *gpio_dev)
++{
++
++	struct device *dev = &gpio_dev->rcdev->dev;
++
++	struct irq_data *irq_data;
++	long hwirq;
++	int ret;
++
++	irq_data = irq_get_irq_data(gpio_dev->pwm_wake_irq);
++	if (!irq_data) {
++		dev_err(dev, "could not get irq data\n");
++		return -1;
++	}
++
++	hwirq = irq_data->hwirq;
++	dev_info(dev, "use hwirq %ld, pwm chip id %d for PWM SIP wakeup\n", hwirq, gpio_dev->pwm_id);
++
++	ret = 0;
++
++	ret |= sip_smc_remotectl_config(REMOTECTL_SET_IRQ, (int)hwirq);
++	ret |= sip_smc_remotectl_config(REMOTECTL_SET_PWM_CH, gpio_dev->pwm_id);
++	ret |= sip_smc_remotectl_config(REMOTECTL_ENABLE, 1);
++
++	if (ret) {
++		dev_err(dev, "SIP remote controller mode, TEE does not support feature\n");
++		return ret;
++	}
++
++	sip_smc_set_suspend_mode(SUSPEND_MODE_CONFIG, 0x10042, 0);
++	sip_smc_set_suspend_mode(WKUP_SOURCE_CONFIG, 0x0, 0);
++	sip_smc_set_suspend_mode(PWM_REGULATOR_CONFIG, 0x0, 0);
++	//sip_smc_set_suspend_mode(GPIO_POWER_CONFIG, i, gpio_temp[i]);
++	sip_smc_set_suspend_mode(SUSPEND_DEBUG_ENABLE, 0x1, 0);
++	sip_smc_set_suspend_mode(APIOS_SUSPEND_CONFIG, 0x0, 0);
++	sip_smc_set_suspend_mode(VIRTUAL_POWEROFF, 0, 1);
++
++	dev_info(dev, "TEE remote controller wakeup installed\n");
++
++	return 0;
++
++}
++
++static void rockchip_ir_recv_remove(struct platform_device *pdev)
++{
++	struct rockchip_rc_dev *gpio_dev = platform_get_drvdata(pdev);
++	struct device *pmdev = gpio_dev->pmdev;
++
++	if (pmdev) {
++		pm_runtime_get_sync(pmdev);
++		cpu_latency_qos_remove_request(&gpio_dev->qos);
++
++		pm_runtime_disable(pmdev);
++		pm_runtime_put_noidle(pmdev);
++		pm_runtime_set_suspended(pmdev);
++	}
++
++	// Disable the remote controller handling of the Trust OS
++	sip_smc_remotectl_config(REMOTECTL_ENABLE, 0);
++
++	// Disable the virtual poweroff of the Trust OS
++	sip_smc_set_suspend_mode(VIRTUAL_POWEROFF, 0, 0);
++
++	//return 0;
++}
++
++static int rockchip_ir_register_power_key(struct device *dev)
++{
++
++	struct rockchip_rc_dev *gpio_dev = dev_get_drvdata(dev);
++
++	struct rc_map *key_map;
++	struct rc_map_table *key;
++	int idx, key_scancode, rev_scancode;
++	int tee_scancode;
++
++	key_map = &gpio_dev->rcdev->rc_map;
++
++	dev_info(dev, "remote key table %s, key map of %d items\n", key_map->name, key_map->len);
++
++	for (idx = 0; idx < key_map->len; idx++) {
++
++		key = &key_map->scan[idx];
++
++		if (key->keycode != KEY_POWER)
++			continue;
++
++		key_scancode = key->scancode;
++		rev_scancode = ~key_scancode;
++
++		// If key_scancode has higher 16 bits set to 0, then the scancode is NEC protocol, otherwise it is NECX/NEC32
++		if ((key_scancode & 0xffff) == key_scancode)
++			tee_scancode = (key_scancode & 0xff00) | ((rev_scancode & 0xff00) << 8); // NEC protocol
++		else
++			tee_scancode = ((key_scancode & 0xff0000) >> 8) | ((key_scancode & 0xff00) << 8); // NECX/NEC32 protocol
++
++		tee_scancode |= rev_scancode & 0xff;
++		tee_scancode <<= 8;
++
++		sip_smc_remotectl_config(REMOTECTL_SET_PWRKEY, tee_scancode);
++
++		dev_info(dev, "registered scancode %08x (SIP: %8x)\n", key_scancode, tee_scancode);
++
++	}
++
++	return 0;
++
++}
++
++static int rockchip_ir_recv_suspend_prepare(struct device *dev)
++{
++	struct rockchip_rc_dev *gpio_dev = dev_get_drvdata(dev);
++	int ret;
++
++	dev_info(dev, "initialize rockchip SIP virtual poweroff\n");
++	ret = rockchip_pwm_sip_wakeup_init(gpio_dev);
++
++	if (ret)
++		return ret;
++
++	rockchip_ir_register_power_key(dev);
++
++	disable_irq(gpio_dev->irq);
++	dev_info(dev, "GPIO IRQ disabled\n");
++
++	ret = pinctrl_select_state(gpio_dev->pinctrl, gpio_dev->pinctrl_state_suspend);
++	if (ret) {
++		dev_err(dev, "unable to set pin in PWM mode\n");
++		return ret;
++	}
++
++	dev_info(dev, "set pin configuration to PWM mode\n");
++
++	rockchip_pwm_hw_init(gpio_dev);
++	dev_info(dev, "started pin PWM mode\n");
++
++	return 0;
++
++}
++
++#ifdef CONFIG_PM
++static int rockchip_ir_recv_suspend(struct device *dev)
++{
++	struct rockchip_rc_dev *gpio_dev = dev_get_drvdata(dev);
++
++	/*
++	 * if property suspend-is-virtual-poweroff is set, we can disable
++	 * the regular gpio wakeup and enable the PWM mode for the Trust OS
++	 * to take control and react to remote control.
++	 * If the property is not set, we instead enable the wake up for the
++	 * regular gpio.
++	 */
++	if (gpio_dev->use_suspend_handler) {
++
++		rockchip_ir_recv_suspend_prepare(dev);
++
++	} else {
++
++		if (device_may_wakeup(dev))
++			enable_irq_wake(gpio_dev->irq);
++		else
++			disable_irq(gpio_dev->irq);
++
++	}
++
++	return 0;
++}
++
++static int rockchip_ir_recv_resume(struct device *dev)
++{
++	struct rockchip_rc_dev *gpio_dev = dev_get_drvdata(dev);
++	int ret;
++
++	/*
++	 * In case suspend-is-virtual-poweroff property is set,
++	 * restore the pin from PWM mode to regular GPIO configuration
++	 * and stop the PWM function.
++	 * Otherwise, just enable the regular GPIO irq
++	 */
++	if (gpio_dev->use_suspend_handler) {
++
++		rockchip_pwm_hw_stop(gpio_dev);
++		dev_info(dev, "stopped pin PWM mode\n");
++
++		ret = pinctrl_select_state(gpio_dev->pinctrl, gpio_dev->pinctrl_state_default);
++		if (ret) {
++			dev_err(dev, "unable to restore pin in GPIO mode\n");
++			return ret;
++		}
++		dev_info(dev, "restored pin configuration di GPIO\n");
++
++		enable_irq(gpio_dev->irq);
++		dev_info(dev, "restored GPIO IRQ\n");
++
++	} else {
++
++		if (device_may_wakeup(dev))
++			disable_irq_wake(gpio_dev->irq);
++		else
++			enable_irq(gpio_dev->irq);
++
++	}
++
++	return 0;
++}
++
++static void rockchip_ir_recv_shutdown(struct platform_device *pdev)
++{
++
++	struct device *dev = &pdev->dev;
++	struct rockchip_rc_dev *gpio_dev = dev_get_drvdata(dev);
++
++	if (gpio_dev->use_shutdown_handler)
++		rockchip_ir_recv_suspend_prepare(dev);
++
++	return;
++
++}
++
++static int rockchip_ir_recv_sys_off(struct sys_off_data *data)
++{
++
++	sip_smc_virtual_poweroff();
++
++	return 0;
++
++}
++
++static int rockchip_ir_recv_init_sip(void)
++{
++	struct arm_smccc_res res;
++
++	arm_smccc_smc(ROCKCHIP_SIP_SIP_VERSION, ROCKCHIP_SIP_IMPLEMENT_V2, SECURE_REG_WR, 0, 0, 0, 0, 0, &res);
++
++	if (res.a0)
++		return 0;
++
++	return res.a1;
++
++}
++
++static int rockchip_ir_recv_probe(struct platform_device *pdev)
++{
++	struct device *dev = &pdev->dev;
++	struct device_node *np = dev->of_node;
++	struct rockchip_rc_dev *gpio_dev;
++	struct rc_dev *rcdev;
++	struct clk *clk;
++	struct clk *p_clk;
++	struct resource *res;
++	u32 period = 0;
++	int rc;
++	int ret;
++	int pwm_wake_irq;
++	int clocks;
++
++	if (!np)
++		return -ENODEV;
++
++	gpio_dev = devm_kzalloc(dev, sizeof(*gpio_dev), GFP_KERNEL);
++	if (!gpio_dev)
++		return -ENOMEM;
++
++	gpio_dev->gpiod = devm_gpiod_get(dev, NULL, GPIOD_IN);
++	if (IS_ERR(gpio_dev->gpiod)) {
++		rc = PTR_ERR(gpio_dev->gpiod);
++		/* Just try again if this happens */
++		if (rc != -EPROBE_DEFER)
++			dev_err(dev, "error getting gpio (%d)\n", rc);
++		return rc;
++	}
++	gpio_dev->irq = gpiod_to_irq(gpio_dev->gpiod);
++	if (gpio_dev->irq < 0)
++		return gpio_dev->irq;
++
++	rcdev = devm_rc_allocate_device(dev, RC_DRIVER_IR_RAW);
++	if (!rcdev)
++		return -ENOMEM;
++
++	rcdev->priv = gpio_dev;
++	rcdev->device_name = ROCKCHIP_IR_DEVICE_NAME;
++	rcdev->input_phys = ROCKCHIP_IR_DEVICE_NAME "/input0";
++	rcdev->input_id.bustype = BUS_HOST;
++	rcdev->input_id.vendor = 0x0001;
++	rcdev->input_id.product = 0x0001;
++	rcdev->input_id.version = 0x0100;
++	rcdev->dev.parent = dev;
++	rcdev->driver_name = KBUILD_MODNAME;
++	rcdev->min_timeout = 1;
++	rcdev->timeout = IR_DEFAULT_TIMEOUT;
++	rcdev->max_timeout = 10 * IR_DEFAULT_TIMEOUT;
++	rcdev->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER;
++	rcdev->map_name = of_get_property(np, "linux,rc-map-name", NULL);
++	if (!rcdev->map_name)
++		rcdev->map_name = RC_MAP_EMPTY;
++
++	gpio_dev->rcdev = rcdev;
++	if (of_property_read_bool(np, "wakeup-source")) {
++
++		ret = device_init_wakeup(dev, true);
++
++		if (ret)
++			dev_err(dev, "could not init wakeup device\n");
++
++	}
++
++	rc = devm_rc_register_device(dev, rcdev);
++	if (rc < 0) {
++		dev_err(dev, "failed to register rc device (%d)\n", rc);
++		return rc;
++	}
++
++	of_property_read_u32(np, "linux,autosuspend-period", &period);
++	if (period) {
++		gpio_dev->pmdev = dev;
++		pm_runtime_set_autosuspend_delay(dev, period);
++		pm_runtime_use_autosuspend(dev);
++		pm_runtime_set_suspended(dev);
++		pm_runtime_enable(dev);
++	}
++
++	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	if (!res) {
++		dev_err(dev, "no memory resources defined\n");
++		return -ENODEV;
++	}
++
++	gpio_dev->pwm_base = devm_ioremap_resource(dev, res);
++	if (IS_ERR(gpio_dev->pwm_base))
++		return PTR_ERR(gpio_dev->pwm_base);
++
++	clocks = of_property_count_strings(np, "clock-names");
++	if (clocks == 2) {
++		clk = devm_clk_get(dev, "pwm");
++		p_clk = devm_clk_get(dev, "pclk");
++	} else {
++		clk = devm_clk_get(dev, NULL);
++		p_clk = clk;
++	}
++
++	if (IS_ERR(clk)) {
++		ret = PTR_ERR(clk);
++		if (ret != -EPROBE_DEFER)
++			dev_err(dev, "Can't get bus clock: %d\n", ret);
++		return ret;
++	}
++
++	if (IS_ERR(p_clk)) {
++		ret = PTR_ERR(p_clk);
++		if (ret != -EPROBE_DEFER)
++			dev_err(dev, "Can't get peripheral clock: %d\n", ret);
++		return ret;
++	}
++
++	ret = clk_prepare_enable(clk);
++	if (ret) {
++		dev_err(dev, "Can't enable bus clk: %d\n", ret);
++		return ret;
++	}
++
++	ret = clk_prepare_enable(p_clk);
++	if (ret) {
++		dev_err(dev, "Can't enable peripheral clk: %d\n", ret);
++		goto error_clk;
++	}
++
++	pwm_wake_irq = platform_get_irq(pdev, 0);
++	if (pwm_wake_irq < 0) {
++		dev_err(&pdev->dev, "cannot find PWM wake interrupt\n");
++		goto error_pclk;
++	}
++
++	gpio_dev->pwm_wake_irq = pwm_wake_irq;
++	ret = enable_irq_wake(pwm_wake_irq);
++	if (ret) {
++		dev_err(dev, "could not enable IRQ wakeup\n");
++	}
++
++	ret = of_property_read_u32(np, "pwm-id", &gpio_dev->pwm_id);
++	if (ret) {
++		dev_err(dev, "missing pwm-id property\n");
++		goto error_pclk;
++	}
++
++	if (gpio_dev->pwm_id > 3) {
++		dev_err(dev, "invalid pwm-id property\n");
++		goto error_pclk;
++	}
++
++	gpio_dev->use_shutdown_handler = of_property_read_bool(np, "shutdown-is-virtual-poweroff");
++	gpio_dev->use_suspend_handler = of_property_read_bool(np, "suspend-is-virtual-poweroff");
++
++	gpio_dev->pinctrl = devm_pinctrl_get(dev);
++	if (IS_ERR(gpio_dev->pinctrl)) {
++		dev_err(dev, "Unable to get pinctrl\n");
++		goto error_pclk;
++	}
++
++	gpio_dev->pinctrl_state_default = pinctrl_lookup_state(gpio_dev->pinctrl, "default");
++	if (IS_ERR(gpio_dev->pinctrl_state_default)) {
++		dev_err(dev, "Unable to get default pinctrl state\n");
++		goto error_pclk;
++	}
++
++	gpio_dev->pinctrl_state_suspend = pinctrl_lookup_state(gpio_dev->pinctrl, "suspend");
++	if (IS_ERR(gpio_dev->pinctrl_state_suspend)) {
++		dev_err(dev, "Unable to get suspend pinctrl state\n");
++		goto error_pclk;
++	}
++
++	platform_set_drvdata(pdev, gpio_dev);
++
++	ret = devm_request_irq(dev, gpio_dev->irq, rockchip_ir_recv_irq,
++				IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
++				"gpio-ir-recv-irq", gpio_dev);
++	if (ret) {
++		dev_err(dev, "Can't request GPIO interrupt\n");
++		goto error_pclk;
++	}
++
++	if (gpio_dev->use_shutdown_handler) {
++
++		ret = devm_register_sys_off_handler(dev, SYS_OFF_MODE_POWER_OFF,
++			SYS_OFF_PRIO_FIRMWARE, rockchip_ir_recv_sys_off, NULL);
++
++		if (ret)
++			dev_err(dev, "could not register sys_off handler\n");
++
++	}
++
++	ret = rockchip_ir_recv_init_sip();
++	if (!ret) {
++		dev_err(dev, "Unable to initialize Rockchip SIP v2, virtual poweroff unavailable\n");
++		gpio_dev->use_shutdown_handler = false;
++		gpio_dev->use_suspend_handler = false;
++	} else {
++		dev_info(dev, "rockchip SIP initialized, version 0x%x\n", ret);
++	}
++
++	return 0;
++
++error_pclk:
++	clk_unprepare(p_clk);
++error_clk:
++	clk_unprepare(clk);
++
++	return -ENODEV;
++
++}
++
++static const struct dev_pm_ops rockchip_ir_recv_pm_ops = {
++	.suspend        = rockchip_ir_recv_suspend,
++	.resume         = rockchip_ir_recv_resume,
++};
++#endif
++
++static const struct of_device_id rockchip_ir_recv_of_match[] = {
++	{ .compatible = "rockchip-ir-receiver", },
++	{ },
++};
++MODULE_DEVICE_TABLE(of, rockchip_ir_recv_of_match);
++
++static struct platform_driver rockchip_ir_recv_driver = {
++	.probe  = rockchip_ir_recv_probe,
++	.remove = rockchip_ir_recv_remove,
++	.shutdown = rockchip_ir_recv_shutdown,
++	.driver = {
++		.name   = KBUILD_MODNAME,
++		.of_match_table = of_match_ptr(rockchip_ir_recv_of_match),
++#ifdef CONFIG_PM
++		.pm	= &rockchip_ir_recv_pm_ops,
++#endif
++	},
++};
++module_platform_driver(rockchip_ir_recv_driver);
++
++MODULE_DESCRIPTION("Rockchip IR Receiver driver");
++MODULE_LICENSE("GPL v2");
diff --git a/projects/Rockchip/devices/RK322X/patches/linux/default/linux-9000-rk322x-dts.patch b/projects/Rockchip/devices/RK322X/patches/linux/default/linux-9000-rk322x-dts.patch
new file mode 100644
index 0000000000..d610fdb77f
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/patches/linux/default/linux-9000-rk322x-dts.patch
@@ -0,0 +1,1139 @@
+diff -ruPN linux/arch/arm/boot/dts/rockchip/rk322x-box-mxq4k.dts linux-new/arch/arm/boot/dts/rockchip/rk322x-box-mxq4k.dts
+--- linux/arch/arm/boot/dts/rockchip/rk322x-box-mxq4k.dts	1970-01-01 01:00:00.000000000 +0100
++++ linux-new/arch/arm/boot/dts/rockchip/rk322x-box-mxq4k.dts	2024-06-09 07:53:01.569912570 +0200
+@@ -0,0 +1,64 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++
++/dts-v1/;
++#include "rk322x-box.dtsi"
++#include "rk322x-opp.dtsi"
++#include "rk322x-legacy.dtsi"
++
++/ {
++	model = "RK3228 MXQ4K";
++	compatible = "rockchip,rk322x-box-mxq4k", "rockchip,rk3229";
++
++	leds {
++		compatible = "gpio-leds";
++
++		blue_led {
++			gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>;
++			default-state = "on";
++		};
++
++		red_led {
++			gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>;
++			default-state = "off";
++                        enable-state-shutdown;
++                        linux,default-trigger = "rc-feedback";
++		};
++	};
++};
++
++&cpu0_opp_table {
++
++	opp-1104000000 {
++		status = "okay";
++	};
++
++	opp-1200000000 {
++		status = "okay";
++	};
++
++};
++
++&dmc {
++	status = "okay";
++};
++
++&dmc_opp_table {
++	opp-666000000 {
++		status = "okay";
++	};
++
++	opp-728000000 {
++		status = "disabled";
++	};
++};
++
++&i2s1_bus {
++	rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>,
++			<0 RK_PB1 1 &pcfg_pull_none>,
++			<0 RK_PB3 1 &pcfg_pull_none>,
++			<0 RK_PB4 1 &pcfg_pull_none>,
++			<0 RK_PB5 1 &pcfg_pull_none>,
++			<0 RK_PB6 1 &pcfg_pull_none>,
++			<1 RK_PA4 2 &pcfg_pull_none>,
++			<1 RK_PA5 2 &pcfg_pull_none>;
++};
+diff -ruPN linux/arch/arm/boot/dts/rockchip/rk322x-box-mxq4k_r29.dts linux-new/arch/arm/boot/dts/rockchip/rk322x-box-mxq4k_r29.dts
+--- linux/arch/arm/boot/dts/rockchip/rk322x-box-mxq4k_r29.dts	1970-01-01 01:00:00.000000000 +0100
++++ linux-new/arch/arm/boot/dts/rockchip/rk322x-box-mxq4k_r29.dts	2024-05-15 19:17:00.274011021 +0200
+@@ -0,0 +1,36 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++
++/dts-v1/;
++
++#include "rk322x-box.dtsi"
++#include "rk322x-opp.dtsi"
++#include "rk322x-legacy.dtsi"
++
++/ {
++	model = "RK3228 mxq4k box r29 variant";
++	compatible = "rockchip,rk322x-box-mxq4k_r29", "rockchip,rk3228";
++
++	leds {
++		compatible = "gpio-leds";
++
++		blue_led {
++			gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>;
++			default-state = "on";
++		};
++
++		red_led {
++			gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
++			default-state = "off";
++			enable-state-shutdown;
++			linux,default-trigger = "rc-feedback";
++		};
++	};
++};
++
++&dmc {
++	status = "okay";
++};
++
++&emmc {
++	max-frequency = <50000000>;
++};
+\ Manca newline alla fine del file
+diff -ruPN linux/arch/arm/boot/dts/rockchip/rk322x-box-mxq4kpro.dts linux-new/arch/arm/boot/dts/rockchip/rk322x-box-mxq4kpro.dts
+--- linux/arch/arm/boot/dts/rockchip/rk322x-box-mxq4kpro.dts	1970-01-01 01:00:00.000000000 +0100
++++ linux-new/arch/arm/boot/dts/rockchip/rk322x-box-mxq4kpro.dts	2023-12-02 07:39:23.903336405 +0100
+@@ -0,0 +1,49 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++
++/dts-v1/;
++#include "rk322x-box.dtsi"
++#include "rk322x-opp.dtsi"
++#include "rk322x-legacy.dtsi"
++
++/ {
++	model = "RK3228 MXQ4kpro box";
++	compatible = "rockchip,rk322x-box-mxq4kpro", "rockchip,rk3228";
++
++	leds {
++		compatible = "gpio-leds";
++
++		blue_led {
++			gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_LOW>;
++			default-state = "on";
++		};
++
++		red_led {
++			gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_LOW>;
++			default-state = "off";
++			enable-state-shutdown;
++			linux,default-trigger = "rc-feedback";
++		};
++	};
++};
++
++&cpu0_opp_table {
++
++	opp-1104000000 {
++		status = "okay";
++	};
++
++	opp-1200000000 {
++		status = "okay";
++	};
++
++};
++
++&dmc {
++	status = "okay";
++};
++
++&dmc_opp_table {
++	opp-656000000 {
++		status = "okay";
++	};
++};
+\ Manca newline alla fine del file
+diff -ruPN linux/arch/arm/boot/dts/rockchip/rk322x-box-mxq4kpro_r329q.dts linux-new/arch/arm/boot/dts/rockchip/rk322x-box-mxq4kpro_r329q.dts
+--- linux/arch/arm/boot/dts/rockchip/rk322x-box-mxq4kpro_r329q.dts	1970-01-01 01:00:00.000000000 +0100
++++ linux-new/arch/arm/boot/dts/rockchip/rk322x-box-mxq4kpro_r329q.dts	2023-12-02 07:39:38.178337003 +0100
+@@ -0,0 +1,49 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++
++/dts-v1/;
++#include "rk322x-box.dtsi"
++#include "rk322x-opp.dtsi"
++#include "rk322x-legacy.dtsi"
++
++/ {
++	model = "RK3228 MXQ4K with R329q board";
++	compatible = "rockchip,rk322x-box-mxq4k_r329q", "rockchip,rk3228";
++
++	leds {
++		compatible = "gpio-leds";
++
++		blue_led {
++			gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_LOW>;
++			default-state = "on";
++		};
++
++		red_led {
++			gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_LOW>;
++			default-state = "off";
++			linux,default-trigger = "rc-feedback";
++                        enable-state-shutdown;
++		};
++	};
++};
++
++&cpu0_opp_table {
++
++	opp-1104000000 {
++		status = "okay";
++	};
++
++	opp-1200000000 {
++		status = "okay";
++	};
++
++};
++
++&dmc {
++	status = "okay";
++};
++
++&dmc_opp_table {
++	opp-666000000 {
++		status = "okay";
++	};
++};
+diff -ruPN linux/arch/arm/boot/dts/rockchip/rk322x-box-onetv-lite.dts linux-new/arch/arm/boot/dts/rockchip/rk322x-box-onetv-lite.dts
+--- linux/arch/arm/boot/dts/rockchip/rk322x-box-onetv-lite.dts	1970-01-01 01:00:00.000000000 +0100
++++ linux-new/arch/arm/boot/dts/rockchip/rk322x-box-onetv-lite.dts	2023-12-02 07:39:50.921337536 +0100
+@@ -0,0 +1,45 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++
++/dts-v1/;
++
++#include "rk322x-box.dtsi"
++#include "rk322x-opp.dtsi"
++#include "rk322x-legacy.dtsi"
++
++/ {
++	model = "RK3228 OneTv Lite";
++	compatible = "rockchip,rk322x-box-onetv-lite", "rockchip,rk3228";
++
++	leds {
++		compatible = "gpio-leds";
++
++		blue_led {
++			gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_LOW>;
++			default-state = "on";
++		};
++
++		red_led {
++                        gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_LOW>;
++                        default-state = "off";
++                        enable-state-shutdown;
++                        linux,default-trigger = "rc-feedback";
++                };
++	};
++};
++
++&dmc {
++	status = "okay";
++};
++
++&dmc_opp_table {
++        opp-666000000 {
++                status = "okay";
++        };
++};
++
++&dram_timing {
++	ddr3_drv = <DDR3_DS_34ohm>;
++	phy_ddr3_clk_drv = <PHY_DDR3_RON_RTT_22ohm>;
++	phy_ddr3_cmd_drv = <PHY_DDR3_RON_RTT_22ohm>;
++	phy_ddr3_dqs_drv = <PHY_DDR3_RON_RTT_22ohm>;
++};
+diff -ruPN linux/arch/arm/boot/dts/rockchip/rk322x-box-t95d.dts linux-new/arch/arm/boot/dts/rockchip/rk322x-box-t95d.dts
+--- linux/arch/arm/boot/dts/rockchip/rk322x-box-t95d.dts	1970-01-01 01:00:00.000000000 +0100
++++ linux-new/arch/arm/boot/dts/rockchip/rk322x-box-t95d.dts	2023-12-02 07:40:03.176338049 +0100
+@@ -0,0 +1,55 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++
++/dts-v1/;
++
++#include "rk322x-box.dtsi"
++#include "rk322x-opp.dtsi"
++#include "rk322x-legacy.dtsi"
++
++/ {
++	model = "RK3228 T95D box";
++	compatible = "rockchip,rk322x-box-t95d", "rockchip,rk3228";
++
++	leds {
++		compatible = "gpio-leds";
++
++		blue_led {
++			gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
++			default-state = "on";
++		};
++
++		red_led {
++			gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>;
++			default-state = "off";
++			enable-state-shutdown;
++			linux,default-trigger = "rc-feedback";
++		};
++	};
++
++	openvfd {
++		compatible = "open,vfd";
++		dev_name = "openvfd";
++		status = "okay";
++	};
++};
++
++&dmc {
++	status = "okay";
++};
++
++&dram_timing {
++	sr_idle = <24>;
++	pd_idle = <32>;
++	ddr3_drv = <DDR3_DS_34ohm>;
++	ddr3_odt = <DDR3_ODT_120ohm>;
++	phy_ddr3_clk_drv = <PHY_DDR3_RON_RTT_34ohm>;
++	phy_ddr3_cmd_drv = <PHY_DDR3_RON_RTT_34ohm>;
++	phy_ddr3_dqs_drv = <PHY_DDR3_RON_RTT_34ohm>;
++	phy_ddr3_odt = <PHY_DDR3_RON_RTT_225ohm>;
++};
++
++&uart1 {
++	bluetooth {
++		compatible = "brcm,bcm4345c5";
++	};
++};
+\ Manca newline alla fine del file
+diff -ruPN linux/arch/arm/boot/dts/rockchip/rk322x-box-v884k.dts linux-new/arch/arm/boot/dts/rockchip/rk322x-box-v884k.dts
+--- linux/arch/arm/boot/dts/rockchip/rk322x-box-v884k.dts	1970-01-01 01:00:00.000000000 +0100
++++ linux-new/arch/arm/boot/dts/rockchip/rk322x-box-v884k.dts	2023-12-02 07:40:25.720338993 +0100
+@@ -0,0 +1,42 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++
++/dts-v1/;
++#include "rk322x-box.dtsi"
++#include "rk322x-opp.dtsi"
++#include "rk322x-legacy.dtsi"
++
++/ {
++	model = "RK3228 V884K";
++	compatible = "rockchip,rk322x-box-v884k", "rockchip,rk3229";
++
++	leds {
++		compatible = "gpio-leds";
++
++		blue_led {
++			gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
++			default-state = "on";
++		};
++	};
++};
++
++&cpu0_opp_table {
++
++	opp-1104000000 {
++		status = "okay";
++	};
++
++	opp-1200000000 {
++		status = "okay";
++	};
++
++};
++
++&dmc {
++	status = "okay";
++};
++
++&dmc_opp_table {
++	opp-666000000 {
++		status = "okay";
++	};
++};
+\ Manca newline alla fine del file
+diff -ruPN linux/arch/arm/boot/dts/rockchip/rk322x-box-v88mars.dts linux-new/arch/arm/boot/dts/rockchip/rk322x-box-v88mars.dts
+--- linux/arch/arm/boot/dts/rockchip/rk322x-box-v88mars.dts	1970-01-01 01:00:00.000000000 +0100
++++ linux-new/arch/arm/boot/dts/rockchip/rk322x-box-v88mars.dts	2024-07-07 09:34:00.865380098 +0200
+@@ -0,0 +1,45 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++
++/dts-v1/;
++#include "rk322x-box.dtsi"
++#include "rk322x-opp.dtsi"
++#include "rk322x-legacy.dtsi"
++
++/ {
++	model = "RK3228 V88Mars";
++	compatible = "rockchip,rk322x-box-v88mars", "rockchip,rk3228";
++
++	leds {
++		compatible = "gpio-leds";
++
++		blue_led {
++			gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
++			default-state = "on";
++		};
++
++		red_led {
++			gpios = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>;
++			default-state = "off";
++			enable-state-shutdown;
++			linux,default-trigger = "rc-feedback";
++		};
++	};
++};
++
++&cpu0_opp_table {
++	opp-1104000000 {
++		status = "okay";
++	};
++
++	opp-1200000000 {
++		status = "okay";
++	};
++
++	opp-1296000000 {
++		status = "okay";
++	};
++
++	opp-1392000000 {
++		status = "disabled";
++	};
++};
+diff -ruPN linux/arch/arm/boot/dts/rockchip/rk322x-box.dts linux-new/arch/arm/boot/dts/rockchip/rk322x-box.dts
+--- linux/arch/arm/boot/dts/rockchip/rk322x-box.dts	1970-01-01 01:00:00.000000000 +0100
++++ linux-new/arch/arm/boot/dts/rockchip/rk322x-box.dts	2024-05-15 19:16:05.179008715 +0200
+@@ -0,0 +1,32 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++
++/dts-v1/;
++
++#include "rk322x-box.dtsi"
++#include "rk322x-opp.dtsi"
++#include "rk322x-legacy.dtsi"
++
++/ {
++        model = "Generic rk322x tv box";
++        compatible = "rockchip,rk3228", "rockchip,rk322x-box";
++/*
++	leds {
++		compatible = "gpio-leds";
++
++		blue_led {
++			gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
++			default-state = "on";
++		};
++
++		red_led {
++                        gpios = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>;
++                        default-state = "off";
++                        enable-state-shutdown;
++                };
++	};
++*/
++};
++
++&emmc {
++	max-frequency = <50000000>;
++};
+\ Manca newline alla fine del file
+diff -ruPN linux/arch/arm/boot/dts/rockchip/rk322x-box.dtsi linux-new/arch/arm/boot/dts/rockchip/rk322x-box.dtsi
+--- linux/arch/arm/boot/dts/rockchip/rk322x-box.dtsi	1970-01-01 01:00:00.000000000 +0100
++++ linux-new/arch/arm/boot/dts/rockchip/rk322x-box.dtsi	2024-05-15 19:14:46.332005414 +0200
+@@ -0,0 +1,465 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++
++#include <dt-bindings/input/input.h>
++#include "rk322x.dtsi"
++
++/ {
++
++	aliases {
++		mmc0 = &sdmmc;
++		mmc2 = &sdio;
++		mmc1 = &emmc;
++	};
++
++	dc_12v: dc-12v-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "dc_12v";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <12000000>;
++		regulator-max-microvolt = <12000000>;
++	};
++
++	ext_gmac: ext_gmac {
++		compatible = "fixed-clock";
++		clock-frequency = <125000000>;
++		clock-output-names = "ext_gmac";
++		#clock-cells = <0>;
++	};
++
++	ir_receiver: ir-receiver {
++		compatible = "rockchip-ir-receiver";
++		reg = <0x110b0030 0x10>;
++		gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_LOW>;
++		clocks = <&cru PCLK_PWM>;
++		interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
++		pinctrl-names = "default", "suspend";
++		pinctrl-0 = <&ir_int>;
++		pinctrl-1 = <&pwm3_pin>;
++		pwm-id = <3>;
++		shutdown-is-virtual-poweroff;
++		status = "okay";
++	};
++
++	memory@60000000 {
++		device_type = "memory";
++		reg = <0x60000000 0x40000000>;
++	};
++
++	sdio_pwrseq: sdio-pwrseq {
++		compatible = "mmc-pwrseq-simple";
++		/*pinctrl-names = "default";
++		pinctrl-0 = <&wifi_enable_h>;*/
++		post-power-on-delay-ms = <100>;
++		power-off-delay-us = <100000>;
++		reset-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_LOW>,
++			      <&gpio2 RK_PD5 GPIO_ACTIVE_LOW>,
++			      <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
++	};
++
++	spdif_out: spdif-out {
++		status = "okay";
++		compatible = "linux,spdif-dit";
++		#sound-dai-cells = <0>;
++	};
++
++	spdif-sound {
++		status = "okay";
++		compatible = "simple-audio-card";
++		simple-audio-card,name = "SPDIF";
++
++		simple-audio-card,cpu {
++			sound-dai = <&spdif>;
++		};
++
++		simple-audio-card,codec {
++			sound-dai = <&spdif_out>;
++		};
++	};
++
++	vcc_sys: vcc-sys-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc_sys";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++	};
++
++	vcc_host: vcc-host-regulator {
++		compatible = "regulator-fixed";
++		enable-active-high;
++		gpio = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&host_vbus_drv>;
++		regulator-name = "vcc_host";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		regulator-always-on;
++		regulator-boot-on;
++		vin-supply = <&vcc_sys>;
++	};
++
++	vccio_1v8: vccio-1v8-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vccio_1v8";
++		regulator-min-microvolt = <1800000>;
++		regulator-max-microvolt = <1800000>;
++		regulator-always-on;
++		vin-supply = <&vcc_sys>;
++	};
++
++	vccio_0v9: vccio-0v9-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vccio_0v9";
++		regulator-min-microvolt = <900000>;
++		regulator-max-microvolt = <900000>;
++		regulator-always-on;
++		vin-supply = <&vcc_sys>;
++	};
++
++	vcc_phy: vcc-phy-regulator {
++		compatible = "regulator-fixed";
++		enable-active-high;
++		regulator-name = "vcc_phy";
++		regulator-min-microvolt = <1800000>;
++		regulator-max-microvolt = <1800000>;
++		regulator-always-on;
++		regulator-boot-on;
++		vin-supply = <&vccio_1v8>;
++	};
++
++	vccio_3v3: vccio-3v3-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vccio_3v3";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		regulator-always-on;
++		vin-supply = <&vcc_sys>;
++	};
++
++	vdd_arm: vdd-arm-regulator {
++		compatible = "pwm-regulator";
++		pwms = <&pwm1 0 25000 1>;
++		pwm-supply = <&vcc_sys>;
++		regulator-name = "vdd_arm";
++		regulator-min-microvolt = <950000>;
++		regulator-max-microvolt = <1400000>;
++		regulator-ramp-delay = <4000>;
++		regulator-always-on;
++		regulator-boot-on;
++	};
++
++	vdd_hdmi_phy: vdd-hdmi-phy-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "hack_to_enable_some_hdmi_connector";
++		gpio = <&gpio2 RK_PB3 GPIO_ACTIVE_LOW>;
++		pinctrl-0 = <&hdmi_phy_enable>;
++		pinctrl-names = "default";
++		regulator-always-on;
++		regulator-boot-on;
++		vin-supply = <&vcc_sys>;
++	};
++
++	vdd_log: vdd-log-regulator {
++		compatible = "pwm-regulator";
++		pwms = <&pwm2 0 25000 1>;
++		pwm-supply = <&vcc_sys>;
++		regulator-name = "vdd_log";
++		regulator-min-microvolt = <1000000>;
++		regulator-max-microvolt = <1300000>;
++		regulator-always-on;
++		regulator-boot-on;
++	};
++
++};
++
++&cpu0 {
++	cpu-supply = <&vdd_arm>;
++	clock-frequency = <1200000000>;
++};
++
++&cpu1 {
++	cpu-supply = <&vdd_arm>;
++	clock-frequency = <1200000000>;
++};
++
++&cpu2 {
++	cpu-supply = <&vdd_arm>;
++	clock-frequency = <1200000000>;
++};
++
++&cpu3 {
++	cpu-supply = <&vdd_arm>;
++	clock-frequency = <1200000000>;
++};
++
++&cpu_alert0 {
++	temperature = <85000>;
++};
++
++&cpu_alert1 {
++	temperature = <95000>;
++};
++
++&cpu_crit {
++	temperature = <105000>;
++};
++
++&cru {
++    assigned-clocks = <&cru PLL_GPLL>, <&cru ARMCLK>,
++		<&cru PLL_CPLL>, <&cru ACLK_PERI>,
++		<&cru HCLK_PERI>, <&cru PCLK_PERI>,
++		<&cru ACLK_CPU>, <&cru HCLK_CPU>,
++		<&cru PCLK_CPU>, <&cru ACLK_VOP>;
++
++    assigned-clock-rates = <1200000000>, <816000000>,
++			    <500000000>, <150000000>,
++			    <150000000>, <75000000>,
++			    <150000000>, <150000000>,
++			    <75000000>, <400000000>;
++};
++
++&crypto {
++	assigned-clocks = <&cru HCLK_M_CRYPTO>;
++	assigned-clock-rates = <200000000>;
++};
++
++&emmc {
++	/delete-property/ pinctrl-names;
++	/delete-property/ pinctrl-0;
++	/delete-property/ rockchip,default-sample-phase;
++
++	cap-mmc-highspeed;
++	non-removable;
++	status = "okay";
++};
++
++&gmac {
++	assigned-clocks = <&cru SCLK_MAC_SRC>;
++	assigned-clock-rates = <50000000>;
++	clock_in_out = "output";
++	phy-handle = <&phy>;
++	phy-mode = "rmii";
++	phy-supply = <&vcc_phy>;
++	status = "okay";
++
++	mdio {
++		compatible = "snps,dwmac-mdio";
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		phy: ethernet-phy@0 {
++			compatible = "ethernet-phy-id1234.d400",
++			             "ethernet-phy-ieee802.3-c22";
++			reg = <0>;
++			clocks = <&cru SCLK_MAC_PHY>;
++			phy-is-integrated;
++			resets = <&cru SRST_MACPHY>;
++		};
++	};
++};
++
++&gpu {
++	mali-supply = <&vdd_log>;
++	status = "okay";
++};
++
++&hdmi {
++	avdd-0v9-supply = <&vccio_0v9>;
++	avdd-1v8-supply = <&vccio_1v8>;
++	status = "okay";
++};
++
++&hdmi_sound {
++	status = "okay";
++};
++
++&hdmi_phy {
++	status = "okay";
++};
++
++&i2s0 {
++	status = "okay";
++};
++
++&iep {
++	status = "okay";
++};
++
++&iep_mmu {
++	status = "okay";
++};
++
++&io_domains {
++	status = "okay";
++
++	vccio1-supply = <&vccio_3v3>;
++	vccio2-supply = <&vccio_1v8>;
++	vccio4-supply = <&vccio_3v3>;
++};
++
++&pinctrl {
++
++	hdmi-phy {
++		hdmi_phy_enable: hdmi-phy-enable {
++			rockchip,pins = <2 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	ir {
++		ir_int: ir-int {
++			rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	usb {
++		host_vbus_drv: host-vbus-drv {
++			rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	sdio-pwrseq {
++		wifi_enable_h: wifi-enable-h {
++			rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++};
++
++&pwm1 {
++	status = "okay";
++};
++
++&pwm2 {
++	status = "okay";
++};
++
++&sdio {
++	cap-sd-highspeed;
++	cap-sdio-irq;
++	mmc-pwrseq = <&sdio_pwrseq>;
++	non-removable;
++	keep-power-in-suspend;
++	no-sd;
++	no-mmc;
++	status = "okay";
++};
++
++&sdmmc {
++	cap-sd-highspeed;
++	status = "okay";
++	cd-gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_LOW>;
++	cd-debounce-delay-ms = <500>;
++};
++
++&spdif {
++	status = "okay";
++};
++
++&tsadc {
++	rockchip,hw-tshut-mode = <0>;
++	rockchip,grf = <&grf>;
++	rockchip,hw-tshut-polarity = <1>;
++	rockchip,hw-tshut-temp = <105000>;
++
++	/* delete the pinctrl-* properties because, on mainline kernel, they (in particular "default")
++	   change the GPIO configuration of the associated PIN. On most boards that pin is not connected
++	   so it does not do anything, but some other boards (X96-Mini) have that pin connected to
++	   a reset pin of the soc or whatever, thus changing the configuration of the pin at boot
++	   causes them to bootloop.
++	   We don't really need these ones though, because since hw-tshut-mode is set to 0, the CRU
++	   unit of the SoC does the reboot*/
++
++	/delete-property/ pinctrl-names;
++	/delete-property/ pinctrl-0;
++	/delete-property/ pinctrl-1;
++	/delete-property/ pinctrl-2;
++
++	status = "okay";
++};
++
++&u2phy0 {
++	status = "okay";
++
++	u2phy0_host: host-port {
++		phy-supply = <&vcc_host>;
++		status = "okay";
++	};
++
++	u2phy0_otg: otg-port {
++		phy-supply = <&vcc_host>;
++		status = "okay";
++	};
++};
++
++&u2phy1 {
++	status = "okay";
++
++	u2phy1_host: host-port {
++		phy-supply = <&vcc_host>;
++		status = "okay";
++	};
++
++	u2phy1_otg: otg-port {
++		phy-supply = <&vcc_host>;
++		status = "okay";
++	};
++};
++
++&uart1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart11_xfer &uart11_rts &uart11_cts>;
++	uart-has-rtscts;
++	status = "okay";
++	bluetooth {
++		enable-gpios = <&gpio2 RK_PD5 GPIO_ACTIVE_HIGH>;
++		device-wake-gpios = <&gpio3 RK_PD3 GPIO_ACTIVE_HIGH>;
++		host-wake-gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_HIGH>;
++	};
++};
++
++&uart2 {
++	status = "okay";
++};
++
++&usb_host0_ehci {
++	status = "okay";
++};
++
++&usb_host0_ohci {
++	status = "okay";
++};
++
++&usb_host1_ehci {
++	status = "okay";
++};
++
++&usb_host1_ohci {
++	status = "okay";
++};
++
++&usb_host2_ehci {
++	status = "okay";
++};
++
++&usb_host2_ohci {
++	status = "okay";
++};
++
++&usb_otg {
++	dr_mode = "host";
++	status = "okay";
++};
++
++&vdec {
++	/*assigned-clocks = <&cru ACLK_RKVDEC>, <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>;
++	assigned-clock-rates = <300000000>, <300000000>, <300000000>;*/
++};
++
++&vop {
++	status = "okay";
++};
++
++&vop_mmu {
++	status = "okay";
++};
+diff -ruPN linux/arch/arm/boot/dts/rockchip/rk322x-legacy.dtsi linux-new/arch/arm/boot/dts/rockchip/rk322x-legacy.dtsi
+--- linux/arch/arm/boot/dts/rockchip/rk322x-legacy.dtsi	1970-01-01 01:00:00.000000000 +0100
++++ linux-new/arch/arm/boot/dts/rockchip/rk322x-legacy.dtsi	2023-10-15 08:08:18.495034516 +0200
+@@ -0,0 +1,47 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++
++/ {
++
++	analog_sound: analog-sound {
++		compatible = "simple-audio-card";
++		simple-audio-card,format = "i2s";
++		simple-audio-card,mclk-fs = <256>;
++		simple-audio-card,name = "Analog";
++
++		simple-audio-card,cpu {
++			sound-dai = <&i2s1>;
++		};
++
++		simple-audio-card,codec {
++			sound-dai = <&analog_codec>;
++		};
++	};
++
++	nandc: nandc@30030000 {
++		compatible = "rockchip,rk-nandc";
++		reg = <0x30030000 0x4000>;
++		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
++		nandc_id = <0>;
++		clocks = <&cru SCLK_NANDC>, <&cru HCLK_NANDC>;
++		clock-names = "clk_nandc", "hclk_nandc";
++		status = "disabled";
++	};
++
++};
++
++&analog_codec {
++	status = "okay";
++};
++
++&dmc {
++	logic-supply = <&vdd_log>;
++	status = "disabled";
++};
++
++&i2s1 {
++	status = "okay";
++};
++
++/*&nandc {
++	status = "okay";
++};*/
+diff -ruPN linux/arch/arm/boot/dts/rockchip/rk322x-opp.dtsi linux-new/arch/arm/boot/dts/rockchip/rk322x-opp.dtsi
+--- linux/arch/arm/boot/dts/rockchip/rk322x-opp.dtsi	1970-01-01 01:00:00.000000000 +0100
++++ linux-new/arch/arm/boot/dts/rockchip/rk322x-opp.dtsi	2024-07-10 16:39:49.606789179 +0200
+@@ -0,0 +1,157 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++
++/ {
++	/delete-node/ opp-table-0;
++
++	cpu0_opp_table: opp-table-0 {
++		compatible = "operating-points-v2";
++		opp-shared;
++		nvmem-cells = <&cpu_leakage>;
++		nvmem-cell-names = "cpu-leakage";
++
++		opp-408000000 {
++			opp-hz = /bits/ 64 <408000000>;
++			opp-microvolt = <975000 975000 1275000>;
++			opp-microvolt-L0 = <975000 975000 1275000>;
++			opp-microvolt-L1 = <975000 975000 1275000>;
++			opp-suspend;
++		};
++		opp-600000000 {
++			opp-hz = /bits/ 64 <600000000>;
++			opp-microvolt = <1000000 1000000 1275000>;
++			opp-microvolt-L0 = <1000000 1000000 1275000>;
++			opp-microvolt-L1 = <975000 975000 1275000>;
++		};
++		opp-696000000 {
++			opp-hz = /bits/ 64 <696000000>;
++			opp-microvolt = <1000000 1000000 1275000>;
++			opp-microvolt-L0 = <1025000 1025000 1275000>;
++			opp-microvolt-L1 = <1000000 1000000 1275000>;
++		};
++		opp-816000000 {
++			opp-hz = /bits/ 64 <816000000>;
++			opp-microvolt = <1025000 1025000 1275000>;
++			opp-microvolt-L0 = <1025000 1025000 1275000>;
++			opp-microvolt-L1 = <1000000 1000000 1275000>;
++		};
++		opp-1008000000 {
++			opp-hz = /bits/ 64 <1008000000>;
++			opp-microvolt = <1075000 1075000 1275000>;
++			opp-microvolt-L0 = <1075000 1075000 1275000>;
++			opp-microvolt-L1 = <1025000 1025000 1275000>;
++		};
++		opp-1104000000 {
++			opp-hz = /bits/ 64 <1104000000>;
++			opp-microvolt = <1125000 1125000 1275000>;
++			opp-microvolt-L0 = <1125000 1125000 1275000>;
++			opp-microvolt-L1 = <1075000 1075000 1275000>;
++			status = "disabled";
++		};
++		opp-1200000000 {
++			opp-hz = /bits/ 64 <1200000000>;
++			opp-microvolt = <1175000 1175000 1275000>;
++			opp-microvolt-L0 = <1175000 1175000 1275000>;
++			opp-microvolt-L1 = <1125000 1125000 1275000>;
++			status = "disabled";
++		};
++		opp-1296000000 {
++			opp-hz = /bits/ 64 <1296000000>;
++			opp-microvolt = <1225000 1225000 1275000>;
++			opp-microvolt-L0 = <1225000 1225000 1275000>;
++			opp-microvolt-L1 = <1175000 1175000 1275000>;
++			status = "disabled";
++		};
++		opp-1392000000 {
++			opp-hz = /bits/ 64 <1392000000>;
++			opp-microvolt = <1275000 1275000 1275000>;
++			opp-microvolt-L0 = <1275000 1275000 1275000>;
++			opp-microvolt-L1 = <1225000 1225000 1275000>;
++			status = "disabled";
++		};
++	};
++
++	/delete-node/ dmc-opp-table;
++
++	dmc_opp_table: dmc-opp-table {
++		compatible = "operating-points-v2";
++
++		opp-330000000 {
++			opp-hz = /bits/ 64 <330000000>;
++			opp-microvolt = <1050000 1050000 1200000>;
++		};
++		opp-400000000 {
++			opp-hz = /bits/ 64 <400000000>;
++			opp-microvolt = <1050000 1050000 1200000>;
++		};
++		opp-666000000 {
++			opp-hz = /bits/ 64 <666000000>;
++			opp-microvolt = <1075000 1075000 1200000>;
++			status = "disabled";
++		};
++		opp-728000000 {
++			opp-hz = /bits/ 64 <728000000>;
++			opp-microvolt = <1125000 1125000 1200000>;
++			status = "disabled";
++		};
++
++	};
++
++	/delete-node/ opp-table2;
++
++	gpu_opp_table: opp-table2 {
++		compatible = "operating-points-v2";
++
++		opp-200000000 {
++			opp-hz = /bits/ 64 <200000000>;
++			opp-microvolt = <1050000 1050000 1200000>;
++		};
++
++		opp-300000000 {
++			opp-hz = /bits/ 64 <300000000>;
++			opp-microvolt = <1050000 1050000 1200000>;
++		};
++
++		opp-400000000 {
++			opp-hz = /bits/ 64 <400000000>;
++			opp-microvolt = <1075000 1075000 1200000>;
++		};
++
++		opp-500000000 {
++			opp-hz = /bits/ 64 <500000000>;
++			opp-microvolt = <1125000 1125000 1200000>;
++			status = "disabled";
++		};
++	};
++};
++
++&cpu_thermal {
++	cooling-maps {
++		map0 {
++			trip = <&cpu_alert0>;
++			cooling-device = <&cpu0 THERMAL_NO_LIMIT 2>,
++				<&cpu1 THERMAL_NO_LIMIT 2>,
++				<&cpu2 THERMAL_NO_LIMIT 2>,
++				<&cpu3 THERMAL_NO_LIMIT 2>;
++		};
++
++		map1 {
++			trip = <&cpu_alert1>;
++			cooling-device = <&cpu0 THERMAL_NO_LIMIT 4>,
++				<&cpu1 THERMAL_NO_LIMIT 4>,
++				<&cpu2 THERMAL_NO_LIMIT 4>,
++				<&cpu3 THERMAL_NO_LIMIT 4>;
++		};
++
++		map2 {
++			trip = <&cpu_alert1>;
++			cooling-device =
++			<&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
++		};
++
++		map3 {
++			trip = <&cpu_alert1>;
++			cooling-device =
++			<&dmc THERMAL_NO_LIMIT 1>;
++		};
++	};
++};
diff --git a/projects/Rockchip/devices/RK322X/patches/linux/default/linux-9001-a95xr1-dts.patch b/projects/Rockchip/devices/RK322X/patches/linux/default/linux-9001-a95xr1-dts.patch
new file mode 100644
index 0000000000..45ef6dbe25
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/patches/linux/default/linux-9001-a95xr1-dts.patch
@@ -0,0 +1,58 @@
+diff -ruPN linux-old/arch/arm/boot/dts/rockchip/rk322x-box-a95xr1.dts linux/arch/arm/boot/dts/rockchip/rk322x-box-a95xr1.dts
+--- /dev/null	2025-01-06 10:17:07.467999996 +0100
++++ linux/arch/arm/boot/dts/rockchip/rk322x-box-a95xr1.dts	2025-01-06 23:46:00.126768116 +0100
+@@ -0,0 +1,53 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++
++/dts-v1/;
++#include "rk322x-box.dtsi"
++#include "rk322x-opp.dtsi"
++#include "rk322x-legacy.dtsi"
++
++/ {
++	model = "RK3229 A95X-R1";
++	compatible = "rockchip,rk322x-box-a95xr1", "rockchip,rk3229";
++
++	leds {
++		compatible = "gpio-leds";
++
++		blue_led {
++			gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
++			default-state = "on";
++		};
++
++		red_led {
++			gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>;
++			default-state = "off";
++			enable-state-shutdown;
++			linux,default-trigger = "rc-feedback";
++		};
++	};
++};
++
++&cpu0_opp_table {
++
++	opp-1104000000 {
++		status = "okay";
++	};
++
++	opp-1200000000 {
++		status = "okay";
++	};
++
++};
++
++&dmc {
++	status = "okay";
++};
++
++&dmc_opp_table {
++	opp-666000000 {
++		status = "okay";
++	};
++};
++
++&emmc {
++	status = "okay";
++};
++
diff --git a/projects/Rockchip/devices/RK322X/patches/linux/default/linux-9003-fix-dmc-suspend-ddr2.patch b/projects/Rockchip/devices/RK322X/patches/linux/default/linux-9003-fix-dmc-suspend-ddr2.patch
new file mode 100644
index 0000000000..4015ca6f8d
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/patches/linux/default/linux-9003-fix-dmc-suspend-ddr2.patch
@@ -0,0 +1,73 @@
+diff -ruPN linux-5.10.76/drivers/devfreq/rk3228_dmc.c linux-new/drivers/devfreq/rk3228_dmc.c
+--- linux-5.10.76/drivers/devfreq/rk3228_dmc.c	2022-02-17 11:10:14.196295398 +0100
++++ linux-new/drivers/devfreq/rk3228_dmc.c	2022-02-17 11:13:37.163303895 +0100
+@@ -442,17 +442,23 @@
+	struct rk3228_dmc *rdev = dev_get_drvdata(dev);
+	int ret = 0;
+
+-	ret = devfreq_event_disable_edev(rdev->edev);
+-	if (ret < 0) {
+-		dev_err(dev, "failed to disable the devfreq-event devices\n");
+-		return ret;
+-	}
+-
+-	ret = devfreq_suspend_device(rdev->devfreq.devfreq);
+-	if (ret < 0) {
+-		dev_err(dev, "failed to suspend the devfreq devices\n");
+-		return ret;
+-	}
++    if (rdev->dram_type == DDR3 ||
++		rdev->dram_type == LPDDR3 ||
++		rdev->dram_type == DDR4 ||
++		rdev->dram_type == LPDDR4) {
++
++        ret = devfreq_event_disable_edev(rdev->edev);
++        if (ret < 0) {
++            dev_err(dev, "failed to disable the devfreq-event devices\n");
++            return ret;
++        }
++
++        ret = devfreq_suspend_device(rdev->devfreq.devfreq);
++        if (ret < 0) {
++            dev_err(dev, "failed to suspend the devfreq devices\n");
++            return ret;
++        }
++    }
+
+	return 0;
+ }
+@@ -462,17 +468,24 @@
+	struct rk3228_dmc *rdev = dev_get_drvdata(dev);
+	int ret = 0;
+
+-	ret = devfreq_event_enable_edev(rdev->edev);
+-	if (ret < 0) {
+-		dev_err(dev, "failed to enable the devfreq-event devices\n");
+-		return ret;
+-	}
+-
+-	ret = devfreq_resume_device(rdev->devfreq.devfreq);
+-	if (ret < 0) {
+-		dev_err(dev, "failed to resume the devfreq devices\n");
+-		return ret;
+-	}
++    if (rdev->dram_type == DDR3 ||
++		rdev->dram_type == LPDDR3 ||
++		rdev->dram_type == DDR4 ||
++		rdev->dram_type == LPDDR4) {
++
++        ret = devfreq_event_enable_edev(rdev->edev);
++        if (ret < 0) {
++            dev_err(dev, "failed to enable the devfreq-event devices\n");
++            return ret;
++        }
++
++        ret = devfreq_resume_device(rdev->devfreq.devfreq);
++        if (ret < 0) {
++            dev_err(dev, "failed to resume the devfreq devices\n");
++            return ret;
++        }
++    }
++
+	return ret;
+ }
diff --git a/projects/Rockchip/devices/RK322X/patches/linux/default/linux-9004-wip-audio-passtrough.patch b/projects/Rockchip/devices/RK322X/patches/linux/default/linux-9004-wip-audio-passtrough.patch
new file mode 100644
index 0000000000..4eaa88ab4d
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/patches/linux/default/linux-9004-wip-audio-passtrough.patch
@@ -0,0 +1,109 @@
+diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c
+index d7e65c869415..2ea9f69d312b 100644
+--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c
++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c
+@@ -40,8 +40,11 @@ static int dw_hdmi_i2s_hw_params(struct device *dev, void *data,
+ {
+	struct dw_hdmi_i2s_audio_data *audio = data;
+	struct dw_hdmi *hdmi = audio->hdmi;
++	int sample_width = hparms->sample_width;
++	int ca = hparms->cea.channel_allocation;
+	u8 conf0 = 0;
+	u8 conf1 = 0;
++	u8 conf2 = 0;
+	u8 inputclkfs = 0;
+
+	/* it cares I2S only */
+@@ -57,6 +60,17 @@ static int dw_hdmi_i2s_hw_params(struct device *dev, void *data,
+	inputclkfs	= HDMI_AUD_INPUTCLKFS_64FS;
+	conf0		= (HDMI_AUD_CONF0_I2S_SELECT | HDMI_AUD_CONF0_I2S_EN0);
+
++	if (fmt->bit_fmt == SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE) {
++		conf2 |= HDMI_AUD_CONF2_NLPCM;
++		if (hparms->channels == 8)
++			conf2 |= HDMI_AUD_CONF2_HBR;
++
++		sample_width = 21;
++		ca = 0;
++	}
++
++	hdmi_write(audio, conf2, HDMI_AUD_CONF2);
++
+	/* Enable the required i2s lanes */
+	switch (hparms->channels) {
+	case 7 ... 8:
+@@ -70,10 +84,13 @@ static int dw_hdmi_i2s_hw_params(struct device *dev, void *data,
+		/* Fall-thru */
+	}
+
+-	switch (hparms->sample_width) {
++	switch (sample_width) {
+	case 16:
+		conf1 = HDMI_AUD_CONF1_WIDTH_16;
+		break;
++	case 21:
++		conf1 = HDMI_AUD_CONF1_WIDTH_21;
++		break;
+	case 24:
+	case 32:
+		conf1 = HDMI_AUD_CONF1_WIDTH_24;
+@@ -104,7 +121,7 @@ static int dw_hdmi_i2s_hw_params(struct device *dev, void *data,
+	dw_hdmi_set_sample_rate(hdmi, hparms->sample_rate);
+	dw_hdmi_set_channel_status(hdmi, hparms->iec.status);
+	dw_hdmi_set_channel_count(hdmi, hparms->channels);
+-	dw_hdmi_set_channel_allocation(hdmi, hparms->cea.channel_allocation);
++	dw_hdmi_set_channel_allocation(hdmi, ca);
+
+	hdmi_write(audio, inputclkfs, HDMI_AUD_INPUTCLKFS);
+	hdmi_write(audio, conf0, HDMI_AUD_CONF0);
+diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h
+index 1999db05bc3b..bff849a336f7 100644
+--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h
++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h
+@@ -917,8 +917,13 @@ enum {
+	HDMI_AUD_CONF1_MODE_BURST_1 = 0x60,
+	HDMI_AUD_CONF1_MODE_BURST_2 = 0x80,
+	HDMI_AUD_CONF1_WIDTH_16 = 0x10,
++	HDMI_AUD_CONF1_WIDTH_21 = 0x15,
+	HDMI_AUD_CONF1_WIDTH_24 = 0x18,
+
++/* AUD_CONF1 field values */
++	HDMI_AUD_CONF2_NLPCM = 0x02,
++	HDMI_AUD_CONF2_HBR = 0x01,
++
+ /* AUD_CTS3 field values */
+	HDMI_AUD_CTS3_N_SHIFT_OFFSET = 5,
+	HDMI_AUD_CTS3_N_SHIFT_MASK = 0xe0,
+diff -ruPN linux/sound/soc/rockchip/rockchip_i2s.c linux-new/sound/soc/rockchip/rockchip_i2s.c
+--- linux/sound/soc/rockchip/rockchip_i2s.c	2023-08-11 12:08:27.000000000 +0200
++++ linux-new/sound/soc/rockchip/rockchip_i2s.c	2023-08-16 16:15:37.839774276 +0200
+@@ -391,6 +391,9 @@
+	case SNDRV_PCM_FORMAT_S32_LE:
+		val |= I2S_TXCR_VDW(32);
+		break;
++        case SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE:
++                val |= I2S_TXCR_VDW(21);
++                break;
+	default:
+		return -EINVAL;
+	}
+@@ -693,7 +696,8 @@
+					SNDRV_PCM_FMTBIT_S16_LE |
+					SNDRV_PCM_FMTBIT_S20_3LE |
+					SNDRV_PCM_FMTBIT_S24_LE |
+-					SNDRV_PCM_FMTBIT_S32_LE;
++					SNDRV_PCM_FMTBIT_S32_LE |
++					SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE;
+
+		i2s->playback_dma_data.addr = res->start + I2S_TXDR;
+		i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
+@@ -714,7 +718,8 @@
+				       SNDRV_PCM_FMTBIT_S16_LE |
+				       SNDRV_PCM_FMTBIT_S20_3LE |
+				       SNDRV_PCM_FMTBIT_S24_LE |
+-				       SNDRV_PCM_FMTBIT_S32_LE;
++				       SNDRV_PCM_FMTBIT_S32_LE |
++				       SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE;
+
+		i2s->capture_dma_data.addr = res->start + I2S_RXDR;
+		i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
diff --git a/projects/Rockchip/devices/RK322X/patches/linux/default/linux-9006-led-enable-at-shutdown.patch b/projects/Rockchip/devices/RK322X/patches/linux/default/linux-9006-led-enable-at-shutdown.patch
new file mode 100644
index 0000000000..1ca8e4cc35
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/patches/linux/default/linux-9006-led-enable-at-shutdown.patch
@@ -0,0 +1,37 @@
+diff -ruPN linux/drivers/leds/led-class.c linux-new/drivers/leds/led-class.c
+--- linux/drivers/leds/led-class.c	2023-08-11 12:08:27.000000000 +0200
++++ linux-new/drivers/leds/led-class.c	2023-09-28 18:56:46.822821117 +0200
+@@ -362,6 +362,9 @@
+			if (fwnode_property_present(init_data->fwnode,
+						    "retain-state-shutdown"))
+				led_cdev->flags |= LED_RETAIN_AT_SHUTDOWN;
++			if (fwnode_property_present(init_data->fwnode,
++						    "enable-state-shutdown"))
++				led_cdev->flags |= LED_ENABLE_AT_SHUTDOWN;
+
+	    fwnode_property_read_u32(init_data->fwnode,
+		"max-brightness",
+diff -ruPN linux/drivers/leds/leds-gpio.c linux-new/drivers/leds/leds-gpio.c
+--- linux/drivers/leds/leds-gpio.c	2023-08-11 12:08:27.000000000 +0200
++++ linux-new/drivers/leds/leds-gpio.c	2023-09-28 18:58:09.997824599 +0200
+@@ -293,6 +293,9 @@
+
+		if (!(led->cdev.flags & LED_RETAIN_AT_SHUTDOWN))
+			gpio_led_set(&led->cdev, LED_OFF);
++		if ((led->cdev.flags & LED_ENABLE_AT_SHUTDOWN))
++			gpio_led_set(&led->cdev, LED_FULL);
++
+	}
+ }
+
+diff -ruPN linux/include/linux/leds.h linux-new/include/linux/leds.h
+--- linux/include/linux/leds.h	2023-08-11 12:08:27.000000000 +0200
++++ linux-new/include/linux/leds.h	2023-09-28 18:18:54.678725996 +0200
+@@ -112,6 +112,7 @@
+ #define LED_INIT_DEFAULT_TRIGGER BIT(23)
+ #define LED_REJECT_NAME_CONFLICT BIT(24)
+ #define LED_MULTI_COLOR		BIT(25)
++#define LED_ENABLE_AT_SHUTDOWN BIT(26)
+
+	/* set_brightness_work / blink_timer flags, atomic, private. */
+	unsigned long		work_flags;
diff --git a/projects/Rockchip/devices/RK322X/patches/linux/default/linux-9007-lima-fix-null-pointer-dereference.patch b/projects/Rockchip/devices/RK322X/patches/linux/default/linux-9007-lima-fix-null-pointer-dereference.patch
new file mode 100644
index 0000000000..8602dddd51
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/patches/linux/default/linux-9007-lima-fix-null-pointer-dereference.patch
@@ -0,0 +1,47 @@
+diff -ruPN linux-6.1.19/drivers/gpu/drm/lima/lima_gem.c linux-new/drivers/gpu/drm/lima/lima_gem.c
+--- linux-6.1.19/drivers/gpu/drm/lima/lima_gem.c	2023-03-13 10:21:32.000000000 +0100
++++ linux-new/drivers/gpu/drm/lima/lima_gem.c	2023-03-23 14:13:46.303639522 +0100
+@@ -105,6 +105,16 @@
+	return ret;
+ }
+
++static void lima_gem_free_object(struct drm_gem_object *obj)
++{
++	struct lima_bo *bo = to_lima_bo(obj);
++
++	if (!list_empty(&bo->va))
++		dev_err(obj->dev->dev, "lima gem free bo still has va\n");
++
++	drm_gem_shmem_free(&bo->base);
++}
++
+ int lima_gem_create_handle(struct drm_device *dev, struct drm_file *file,
+			   u32 size, u32 flags, u32 *handle)
+ {
+@@ -145,21 +155,15 @@
+
+ out:
+	/* drop reference from allocate - handle holds it now */
+-	drm_gem_object_put(obj);
++	if (!err) {
++		drm_gem_object_put(obj);
++	} else {
++		lima_gem_free_object(obj);
++	}
+
+	return err;
+ }
+
+-static void lima_gem_free_object(struct drm_gem_object *obj)
+-{
+-	struct lima_bo *bo = to_lima_bo(obj);
+-
+-	if (!list_empty(&bo->va))
+-		dev_err(obj->dev->dev, "lima gem free bo still has va\n");
+-
+-	drm_gem_shmem_free(&bo->base);
+-}
+-
+ static int lima_gem_object_open(struct drm_gem_object *obj, struct drm_file *file)
+ {
+	struct lima_bo *bo = to_lima_bo(obj);
diff --git a/projects/Rockchip/devices/RK322X/patches/linux/default/linux-9008-dw-mmc-set-name-of-irq.patch b/projects/Rockchip/devices/RK322X/patches/linux/default/linux-9008-dw-mmc-set-name-of-irq.patch
new file mode 100644
index 0000000000..367cac631c
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/patches/linux/default/linux-9008-dw-mmc-set-name-of-irq.patch
@@ -0,0 +1,11 @@
+diff -ruPN linux/drivers/mmc/host/dw_mmc.c linux-new/drivers/mmc/host/dw_mmc.c
+--- linux/drivers/mmc/host/dw_mmc.c	2023-11-20 11:52:19.000000000 +0100
++++ linux-new/drivers/mmc/host/dw_mmc.c	2023-12-05 18:56:42.971038136 +0100
+@@ -3540,7 +3540,7 @@
+
+	INIT_WORK(&host->bh_work, dw_mci_work_func);
+	ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt,
+-			       host->irq_flags, "dw-mci", host);
++			       host->irq_flags, dev_name(host->dev), host);
+	if (ret)
+		goto err_dmaunmap;
diff --git a/projects/Rockchip/devices/RK322X/patches/parted/parted-0001-fix-do_version-declaration.patch b/projects/Rockchip/devices/RK322X/patches/parted/parted-0001-fix-do_version-declaration.patch
new file mode 100644
index 0000000000..be65377b52
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/patches/parted/parted-0001-fix-do_version-declaration.patch
@@ -0,0 +1,39 @@
+From 7dae5d837562a494e14f69702601bcc2240cab3e Mon Sep 17 00:00:00 2001
+From: Rudi Heitbaum <rudi@heitbaum.com>
+Date: Wed, 20 Nov 2024 12:17:07 +0000
+Subject: [PATCH] parted: fix do_version declaration
+
+With gcc 15-20241117 compile fails with the below error, update the
+do_version declaration to match the header in command.h
+
+../../parted/parted.c: In function '_init_commands':
+../../parted/parted.c:2469:9: error: passing argument 2 of 'command_create' from incompatible pointer type [-Wincompatible-pointer-types]
+ 2469 |         do_version,
+      |         ^~~~~~~~~~
+      |         |
+      |         int (*)(void)
+In file included from ../../parted/parted.c:28:
+../../parted/command.h:35:39: note: expected 'int (*)(PedDevice **, PedDisk **)' {aka 'int (*)(struct _PedDevice **, struct _PedDisk **)'} but argument is of type 'int (*)(void)'
+   35 |                                 int (*method) (PedDevice** dev, PedDisk** diskp),
+      |                                 ~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Signed-off-by: Rudi Heitbaum <rudi@heitbaum.com>
+---
+ parted/parted.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/parted/parted.c b/parted/parted.c
+index 3abb52f..fc2aeba 100644
+--- a/parted/parted.c
++++ b/parted/parted.c
+@@ -2172,7 +2172,7 @@ do_unit (PedDevice** dev, PedDisk** diskp)
+ }
+
+ static int
+-do_version ()
++do_version (PedDevice** dev, PedDisk** diskp)
+ {
+     printf ("\n%s\n%s",
+             prog_name,
+--
+2.43.0
diff --git a/projects/Rockchip/devices/RK322X/patches/pkg-config/0002-Do-not-use-bool-as-a-field-name.patch b/projects/Rockchip/devices/RK322X/patches/pkg-config/0002-Do-not-use-bool-as-a-field-name.patch
new file mode 100644
index 0000000000..bcb7e94d69
--- /dev/null
+++ b/projects/Rockchip/devices/RK322X/patches/pkg-config/0002-Do-not-use-bool-as-a-field-name.patch
@@ -0,0 +1,36 @@
+From b3b26a7e125e5e4f5b69975cc17eb6d33198ebaa Mon Sep 17 00:00:00 2001
+From: Emmanuele Bassi <ebassi@gnome.org>
+Date: Thu, 11 Apr 2024 14:40:21 +0100
+Subject: [PATCH] Do not use bool as a field name
+
+C99 aliases `bool` to `_Bool`, and C23 introduces `bool` as a reserved
+keyword. Let's avoid using `bool` as a field name.
+
+Upstream-Status: Backport [Backport from glib to bunlded version in pkg-config https://github.com/GNOME/glib/commit/9e320e1c43a4770ed1532248fe5416eb0c618120]
+Signed-off-by: Martin Jansa <martin.jansa@gmail.com>
+---
+ glib/glib/goption.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/glib/glib/goption.c b/glib/glib/goption.c
+index 0a22f6f..f439fd4 100644
+--- a/glib/glib/goption.c
++++ b/glib/glib/goption.c
+@@ -166,7 +166,7 @@ typedef struct
+   gpointer arg_data;
+   union
+   {
+-    gboolean bool;
++    gboolean boolean;
+     gint integer;
+     gchar *str;
+     gchar **array;
+@@ -1600,7 +1600,7 @@ free_changes_list (GOptionContext *context,
+           switch (change->arg_type)
+             {
+             case G_OPTION_ARG_NONE:
+-              *(gboolean *)change->arg_data = change->prev.bool;
++              *(gboolean *)change->arg_data = change->prev.boolean;
+               break;
+             case G_OPTION_ARG_INT:
+               *(gint *)change->arg_data = change->prev.integer;
diff --git a/projects/Rockchip/kodi/appliance.xml b/projects/Rockchip/kodi/appliance.xml
index e07e5708a0..c83b640487 100644
--- a/projects/Rockchip/kodi/appliance.xml
+++ b/projects/Rockchip/kodi/appliance.xml
@@ -11,7 +11,7 @@
           <visible>true</visible>
         </setting>
       </group>
-      <group id="4">
+      <group id="3">
         <setting id="videoscreen.noofbuffers">
           <default>2</default>
           <visible>false</visible>
diff --git a/projects/Rockchip/patches/linux/default/linux-1000-drm-rockchip.patch b/projects/Rockchip/patches/linux/default/linux-1000-drm-rockchip.patch
new file mode 100644
index 0000000000..df44845fd6
--- /dev/null
+++ b/projects/Rockchip/patches/linux/default/linux-1000-drm-rockchip.patch
@@ -0,0 +1,232 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Sun, 3 May 2020 16:51:31 +0000
+Subject: [PATCH] drm/rockchip: vop: filter modes outside 0.5% pixel clock
+ tolerance
+
+Filter modes that require a pixel clock that differ more then 0.5%
+from the requested pixel clock.
+
+This filter is only applied to tmds only connector and/or encoders.
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+Signed-off-by: Alex Bee <knaerzche@gmail.com>
+---
+ drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 54 +++++++++++++++++++++
+ 1 file changed, 54 insertions(+)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+index dbe4d411b30f..fac23d370ee0 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
++++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+@@ -1206,6 +1206,59 @@ static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
+	spin_unlock_irqrestore(&vop->irq_lock, flags);
+ }
+
++static bool vop_crtc_is_tmds(struct drm_crtc *crtc)
++{
++	struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
++	struct drm_encoder *encoder;
++
++	switch (s->output_type) {
++	case DRM_MODE_CONNECTOR_LVDS:
++	case DRM_MODE_CONNECTOR_DSI:
++		return false;
++	case DRM_MODE_CONNECTOR_eDP:
++	case DRM_MODE_CONNECTOR_HDMIA:
++	case DRM_MODE_CONNECTOR_DisplayPort:
++		return true;
++	}
++
++	drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask)
++		if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS)
++			return true;
++
++	return false;
++}
++
++/*
++ * The VESA DMT standard specifies a 0.5% pixel clock frequency tolerance.
++ * The CVT spec reuses that tolerance in its examples.
++ */
++#define	CLOCK_TOLERANCE_PER_MILLE	5
++
++static enum drm_mode_status vop_crtc_mode_valid5(struct drm_crtc *crtc,
++					const struct drm_display_mode *mode)
++{
++	struct vop *vop = to_vop(crtc);
++	long rounded_rate;
++	long lowest, highest;
++
++	if (!vop_crtc_is_tmds(crtc))
++		return MODE_OK;
++
++	rounded_rate = clk_round_rate(vop->dclk, mode->clock * 1000 + 999);
++	if (rounded_rate < 0)
++		return MODE_NOCLOCK;
++
++	lowest = mode->clock * (1000 - CLOCK_TOLERANCE_PER_MILLE);
++	if (rounded_rate < lowest)
++		return MODE_CLOCK_LOW;
++
++	highest = mode->clock * (1000 + CLOCK_TOLERANCE_PER_MILLE);
++	if (rounded_rate > highest)
++		return MODE_CLOCK_HIGH;
++
++	return MODE_OK;
++}
++
+ static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
+				const struct drm_display_mode *mode,
+				struct drm_display_mode *adjusted_mode)
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Mon, 20 Jul 2020 15:15:50 +0000
+Subject: [PATCH] drm/rockchip: vop: filter interlaced modes
+
+The current version of the driver does not support interlaced modes,
+lets filter any interlaced mode.
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+---
+ drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+index fac23d370ee0..9f7326c5b1f5 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
++++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+@@ -1244,6 +1244,9 @@ static enum drm_mode_status vop_crtc_mode_valid(struct drm_crtc *crtc,
+	if (!vop_crtc_is_tmds(crtc))
+		return MODE_OK;
+
++	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
++		return MODE_NO_INTERLACE;
++
+	rounded_rate = clk_round_rate(vop->dclk, mode->clock * 1000 + 999);
+	if (rounded_rate < 0)
+		return MODE_NOCLOCK;
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Mon, 20 Jul 2020 11:46:16 +0000
+Subject: [PATCH] drm/rockchip: vop: filter modes above max output supported
+
+Filter any mode with a resolution not supported by the VOP.
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+Signed-off-by: Alex Bee <knaerzche@gmail.com>
+---
+ drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 48 +++++++++++++++------
+ 1 file changed, 34 insertions(+), 14 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+index 9f7326c5b1f5..30e252ba7184 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
++++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+@@ -1228,6 +1228,24 @@ static bool vop_crtc_is_tmds(struct drm_crtc *crtc)
+	return false;
+ }
+
++static enum drm_mode_status vop_crtc_size_valid(struct drm_crtc *crtc,
++					const struct drm_display_mode *mode)
++{
++	struct vop *vop = to_vop(crtc);
++	const struct vop_rect *max_output = &vop->data->max_output;
++
++	if (max_output->width && max_output->height) {
++		/* only the size of the resulting rect matters */
++		if(drm_mode_validate_size(mode, max_output->width,
++					  max_output->height) != MODE_OK) {
++			return drm_mode_validate_size(mode, max_output->height,
++						      max_output->width);
++		}
++	}
++
++	return MODE_OK;
++}
++
+ /*
+  * The VESA DMT standard specifies a 0.5% pixel clock frequency tolerance.
+  * The CVT spec reuses that tolerance in its examples.
+@@ -1241,25 +1259,24 @@ static enum drm_mode_status vop_crtc_mode_valid(struct drm_crtc *crtc,
+	long rounded_rate;
+	long lowest, highest;
+
+-	if (!vop_crtc_is_tmds(crtc))
+-		return MODE_OK;
+-
+	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
+-		return MODE_NO_INTERLACE;
++			return MODE_NO_INTERLACE;
+
+-	rounded_rate = clk_round_rate(vop->dclk, mode->clock * 1000 + 999);
+-	if (rounded_rate < 0)
+-		return MODE_NOCLOCK;
++	if (vop_crtc_is_tmds(crtc)) {
++		rounded_rate = clk_round_rate(vop->dclk, mode->clock * 1000 + 999);
++		if (rounded_rate < 0)
++			return MODE_NOCLOCK;
+
+-	lowest = mode->clock * (1000 - CLOCK_TOLERANCE_PER_MILLE);
+-	if (rounded_rate < lowest)
+-		return MODE_CLOCK_LOW;
++		lowest = mode->clock * (1000 - CLOCK_TOLERANCE_PER_MILLE);
++		if (rounded_rate < lowest)
++			return MODE_CLOCK_LOW;
+
+-	highest = mode->clock * (1000 + CLOCK_TOLERANCE_PER_MILLE);
+-	if (rounded_rate > highest)
+-		return MODE_CLOCK_HIGH;
++		highest = mode->clock * (1000 + CLOCK_TOLERANCE_PER_MILLE);
++		if (rounded_rate > highest)
++			return MODE_CLOCK_HIGH;
++	}
+
+-	return MODE_OK;
++	return vop_crtc_size_valid(crtc, mode);
+ }
+
+ static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
+@@ -1269,6 +1286,9 @@ static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
+	struct vop *vop = to_vop(crtc);
+	unsigned long rate;
+
++	if (vop_crtc_size_valid(crtc, adjusted_mode) != MODE_OK)
++		return false;
++
+	/*
+	 * Clock craziness.
+	 *
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Alex Bee <knaerzche@gmail.com>
+Date: Sat, 15 Aug 2020 23:20:34 +0200
+Subject: [PATCH] drm/rockchip: enable ycbcr_420_allowed and ycbcr_444_allowed
+ for RK3228
+
+---
+ drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+index cb201612199f..8627f6826bfe 100644
+--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
++++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+@@ -616,6 +616,7 @@ static const struct dw_hdmi_phy_ops rk3228_hdmi_phy_ops = {
+ static struct rockchip_hdmi_chip_data rk3228_chip_data = {
+	.lcdsel_grf_reg = -1,
+	.max_tmds_clock = 594000,
++	.ycbcr_444_allowed = true,
+ };
+
+ static const struct dw_hdmi_plat_data rk3228_hdmi_drv_data = {
+@@ -624,6 +625,7 @@ static const struct dw_hdmi_plat_data rk3228_hdmi_drv_data = {
+	.phy_ops = &rk3228_hdmi_phy_ops,
+	.phy_name = "inno_dw_hdmi_phy2",
+	.phy_force_vendor = true,
++	.ycbcr_420_allowed = true,
+ };
+
+ static struct rockchip_hdmi_chip_data rk3288_chip_data = {
diff --git a/projects/Rockchip/patches/u-boot/0006-rockchip-roc-3328-cc-use-1600-ddr4-timing.patch b/projects/Rockchip/patches/u-boot/0006-rockchip-roc-3328-cc-use-1600-ddr4-timing.patch
deleted file mode 100644
index 6699ad2a0b..0000000000
--- a/projects/Rockchip/patches/u-boot/0006-rockchip-roc-3328-cc-use-1600-ddr4-timing.patch
+++ /dev/null
@@ -1,26 +0,0 @@
-From 2e54840fd3de7a791669bf20fc7b576b806167b8 Mon Sep 17 00:00:00 2001
-From: Da Xue <da@libre.computer>
-Date: Sun, 19 May 2024 18:48:57 -0400
-Subject: [PATCH] arm64: dts: rockchip: roc-3328-cc: use 1600 ddr4 timing
-
-Swap the ROC-3328-CC from DDR4 666 to 1600 timing to boost performance.
-
-Signed-off-by: Da Xue <da@libre.computer>
-Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
----
- arch/arm/dts/rk3328-roc-cc-u-boot.dtsi | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi b/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi
-index 582d6ba49b4e..c47d29c59de9 100644
---- a/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi
-+++ b/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi
-@@ -4,7 +4,7 @@
-  */
- 
- #include "rk3328-u-boot.dtsi"
--#include "rk3328-sdram-ddr4-666.dtsi"
-+#include "rk3328-sdram-ddr4-1600.dtsi"
- 
- / {
- 	smbios {
diff --git a/projects/Rockchip/patches/u-boot/0007-rockchip-rk3328-add-ddr4-1600-sdram-timing.patch b/projects/Rockchip/patches/u-boot/0007-rockchip-rk3328-add-ddr4-1600-sdram-timing.patch
deleted file mode 100644
index 4235f87ebe..0000000000
--- a/projects/Rockchip/patches/u-boot/0007-rockchip-rk3328-add-ddr4-1600-sdram-timing.patch
+++ /dev/null
@@ -1,247 +0,0 @@
-From 825863d08ce323ebcefc03af20fb1e37cdac0eaa Mon Sep 17 00:00:00 2001
-From: Da Xue <da@libre.computer>
-Date: Mon, 19 Sep 2022 13:40:01 -0400
-Subject: [PATCH] ram: rk3328: add ddr4-1600 sdram timing
-
-Add DDR4 1600MHz SDRAM timing data from LibreComputer u-boot sources
-for the ROC-3328-CC board.
-
-Signed-off-by: Da Xue <da@libre.computer>
-Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
----
- arch/arm/dts/rk3328-sdram-ddr4-1600.dtsi | 226 +++++++++++++++++++++++
- 1 file changed, 226 insertions(+)
- create mode 100644 arch/arm/dts/rk3328-sdram-ddr4-1600.dtsi
-
-diff --git a/arch/arm/dts/rk3328-sdram-ddr4-1600.dtsi b/arch/arm/dts/rk3328-sdram-ddr4-1600.dtsi
-new file mode 100644
-index 000000000000..9594bb428399
---- /dev/null
-+++ b/arch/arm/dts/rk3328-sdram-ddr4-1600.dtsi
-@@ -0,0 +1,226 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+// Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd.
-+
-+&dmc {
-+	rockchip,sdram-params = <
-+		0x1
-+		0xA
-+		0x2
-+		0x1
-+		0x0
-+		0x0
-+		0x11
-+		0x0
-+		0x11
-+		0x0
-+		0
-+
-+		0x94496354
-+		0x00000000
-+		0x0000002a
-+		0x000004e2
-+		0x00000015
-+		0x0000034a
-+		0x000000ff
-+
-+		800
-+		0
-+		1
-+		0
-+		0
-+
-+		0x00000000
-+		0x43041010
-+		0x00000064
-+		0x0061008c
-+		0x000000d0
-+		0x000200c5
-+		0x000000d4
-+		0x00500000
-+		0x000000d8
-+		0x00000100
-+		0x000000dc
-+		0x03140401
-+		0x000000e0
-+		0x00000000
-+		0x000000e4
-+		0x00110000
-+		0x000000e8
-+		0x00000420
-+		0x000000ec
-+		0x00000400
-+		0x000000f4
-+		0x000f011f
-+		0x00000100
-+		0x0c0e1b0e
-+		0x00000104
-+		0x00030314
-+		0x00000108
-+		0x0506050b
-+		0x0000010c
-+		0x0040400c
-+		0x00000110
-+		0x06030307
-+		0x00000114
-+		0x04040302
-+		0x00000120
-+		0x06060b06
-+		0x00000124
-+		0x00020308
-+		0x00000180
-+		0x01000040
-+		0x00000184
-+		0x00000000
-+		0x00000190
-+		0x07040003
-+		0x00000198
-+		0x05001100
-+		0x000001a0
-+		0xc0400003
-+		0x00000240
-+		0x0600060c
-+		0x00000244
-+		0x00000201
-+		0x00000250
-+		0x00000f00
-+		0x00000490
-+		0x00000001
-+		0xffffffff
-+		0xffffffff
-+		0xffffffff
-+		0xffffffff
-+		0xffffffff
-+		0xffffffff
-+		0xffffffff
-+		0xffffffff
-+		0xffffffff
-+		0xffffffff
-+		0xffffffff
-+		0xffffffff
-+		0xffffffff
-+		0xffffffff
-+
-+		0x00000004
-+		0x0000000c
-+		0x00000028
-+		0x0000000c
-+		0x0000002c
-+		0x00000000
-+		0x00000030
-+		0x00000009
-+		0xffffffff
-+		0xffffffff
-+
-+		0x77
-+		0x88
-+		0x79
-+		0x79
-+		0x87
-+		0x97
-+		0x87
-+		0x78
-+		0x77
-+		0x78
-+		0x87
-+		0x88
-+		0x87
-+		0x87
-+		0x77
-+
-+		0x78
-+		0x78
-+		0x78
-+		0x78
-+		0x78
-+		0x78
-+		0x78
-+		0x78
-+		0x78
-+		0x69
-+		0x9
-+
-+		0x77
-+		0x78
-+		0x77
-+		0x78
-+		0x77
-+		0x78
-+		0x77
-+		0x78
-+		0x77
-+		0x79
-+		0x9
-+
-+		0x78
-+		0x78
-+		0x78
-+		0x78
-+		0x78
-+		0x78
-+		0x78
-+		0x78
-+		0x78
-+		0x69
-+		0x9
-+
-+		0x77
-+		0x78
-+		0x77
-+		0x77
-+		0x77
-+		0x77
-+		0x77
-+		0x77
-+		0x77
-+		0x79
-+		0x9
-+
-+		0x78
-+		0x78
-+		0x78
-+		0x78
-+		0x78
-+		0x78
-+		0x78
-+		0x78
-+		0x78
-+		0x69
-+		0x9
-+
-+		0x77
-+		0x78
-+		0x77
-+		0x78
-+		0x77
-+		0x78
-+		0x77
-+		0x78
-+		0x77
-+		0x79
-+		0x9
-+
-+		0x78
-+		0x78
-+		0x78
-+		0x78
-+		0x78
-+		0x78
-+		0x78
-+		0x78
-+		0x78
-+		0x69
-+		0x9
-+
-+		0x77
-+		0x78
-+		0x77
-+		0x77
-+		0x77
-+		0x77
-+		0x77
-+		0x77
-+		0x77
-+		0x79
-+		0x9
-+	>;
-+};
diff --git a/projects/Rockchip/patches/u-boot/default/0001-rockchip-rk3328-BACKPORT-Set-efuse-auto-mode-and-timing-control.patch b/projects/Rockchip/patches/u-boot/default/0001-rockchip-rk3328-BACKPORT-Set-efuse-auto-mode-and-timing-control.patch
new file mode 100644
index 0000000000..d42e07d4d4
--- /dev/null
+++ b/projects/Rockchip/patches/u-boot/default/0001-rockchip-rk3328-BACKPORT-Set-efuse-auto-mode-and-timing-control.patch
@@ -0,0 +1,102 @@
+From 5708e8eeae53ad8ce605afdf61e5a83162dc5131 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Sun, 7 Jan 2024 18:18:33 +0000
+Subject: [PATCH] rockchip: rk3328: Set efuse auto mode and timing control
+
+Reading from efuse return zero when mainline TF-A is used.
+
+  => dump_efuse
+  00000000: 00 00 00 00  ....
+  00000004: 00 00 00 00  ....
+  00000008: 00 00 00 00  ....
+  0000000c: 00 00 00 00  ....
+  00000010: 00 00 00 00  ....
+  00000014: 00 00 00 00  ....
+  00000018: 00 00 00 00  ....
+  0000001c: 00 00 00 00  ....
+
+However, when vendor TF-A blobs is used reading from efuse works.
+
+Change to use auto mode, enable finish and auto access err interrupts
+and set timing control using same values that vendor TF-A blob use to
+fix this.
+
+With this efuse can be read when either of mainline TF-A or vendor blob
+is used.
+
+  => dump_efuse
+  00000000: 52 4b 33 82  RK3.
+  00000004: 00 fe 21 55  ..!U
+  00000008: 52 4b 57 34  RKW4
+  0000000c: 35 30 32 39  5029
+  00000010: 00 00 00 00  ....
+  00000014: 08 25 0c 0f  .%..
+  00000018: 02 0d 08 00  ....
+  0000001c: 00 00 f0 00  ....
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
+---
+ arch/arm/mach-rockchip/rk3328/rk3328.c | 38 ++++++++++++++++++++++++++
+ 1 file changed, 38 insertions(+)
+
+diff --git a/arch/arm/mach-rockchip/rk3328/rk3328.c b/arch/arm/mach-rockchip/rk3328/rk3328.c
+index de17b886827..ca623c0d3d0 100644
+--- a/arch/arm/mach-rockchip/rk3328/rk3328.c
++++ b/arch/arm/mach-rockchip/rk3328/rk3328.c
+@@ -19,6 +19,23 @@ DECLARE_GLOBAL_DATA_PTR;
+ #define GRF_BASE		0xFF100000
+ #define UART2_BASE		0xFF130000
+ #define FW_DDR_CON_REG		0xFF7C0040
++#define EFUSE_NS_BASE		0xFF260000
++
++#define EFUSE_MOD		0x0000
++#define EFUSE_INT_CON		0x0014
++#define EFUSE_T_CSB_P		0x0028
++#define EFUSE_T_PGENB_P		0x002C
++#define EFUSE_T_LOAD_P		0x0030
++#define EFUSE_T_ADDR_P		0x0034
++#define EFUSE_T_STROBE_P	0x0038
++#define EFUSE_T_CSB_R		0x003C
++#define EFUSE_T_PGENB_R		0x0040
++#define EFUSE_T_LOAD_R		0x0044
++#define EFUSE_T_ADDR_R		0x0048
++#define EFUSE_T_STROBE_R	0x004C
++
++#define EFUSE_USER_MODE		0x1
++#define EFUSE_TIMING(s, l)	(((s) << 16) | (l))
+
+ const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
+	[BROM_BOOTSOURCE_EMMC] = "/mmc@ff520000",
+@@ -50,10 +67,31 @@ struct mm_region *mem_map = rk3328_mem_map;
+ int arch_cpu_init(void)
+ {
+ #ifdef CONFIG_SPL_BUILD
++	u32 reg;
++
+	/* We do some SoC one time setting here. */
+
+	/* Disable the ddr secure region setting to make it non-secure */
+	rk_setreg(FW_DDR_CON_REG, 0x200);
++
++	/* Use efuse auto mode */
++	reg = readl(EFUSE_NS_BASE + EFUSE_MOD);
++	writel(reg & ~EFUSE_USER_MODE, EFUSE_NS_BASE + EFUSE_MOD);
++
++	/* Enable efuse finish and auto access err interrupt */
++	writel(0x07, EFUSE_NS_BASE + EFUSE_INT_CON);
++
++	/* Set efuse timing control */
++	writel(EFUSE_TIMING(1, 241), EFUSE_NS_BASE + EFUSE_T_CSB_P);
++	writel(EFUSE_TIMING(1, 241), EFUSE_NS_BASE + EFUSE_T_PGENB_P);
++	writel(EFUSE_TIMING(1, 241), EFUSE_NS_BASE + EFUSE_T_LOAD_P);
++	writel(EFUSE_TIMING(1, 241), EFUSE_NS_BASE + EFUSE_T_ADDR_P);
++	writel(EFUSE_TIMING(2, 240), EFUSE_NS_BASE + EFUSE_T_STROBE_P);
++	writel(EFUSE_TIMING(1, 4), EFUSE_NS_BASE + EFUSE_T_CSB_R);
++	writel(EFUSE_TIMING(1, 4), EFUSE_NS_BASE + EFUSE_T_PGENB_R);
++	writel(EFUSE_TIMING(1, 4), EFUSE_NS_BASE + EFUSE_T_LOAD_R);
++	writel(EFUSE_TIMING(1, 4), EFUSE_NS_BASE + EFUSE_T_ADDR_R);
++	writel(EFUSE_TIMING(2, 3), EFUSE_NS_BASE + EFUSE_T_STROBE_R);
+ #endif
+	return 0;
+ }
diff --git a/projects/Rockchip/patches/u-boot/default/0002-rockchip-backport-rk3328-added-DDR4-1600MT-1800MT-timings.patch b/projects/Rockchip/patches/u-boot/default/0002-rockchip-backport-rk3328-added-DDR4-1600MT-1800MT-timings.patch
new file mode 100644
index 0000000000..4092f761ff
--- /dev/null
+++ b/projects/Rockchip/patches/u-boot/default/0002-rockchip-backport-rk3328-added-DDR4-1600MT-1800MT-timings.patch
@@ -0,0 +1,500 @@
+From e01e0c3362eef660606630d4d42d89b94fd0f6d4 Mon Sep 17 00:00:00 2001
+From: Da Xue <da@lessconfused.com>
+Date: Mon, 19 Sep 2022 13:40:01 -0400
+Subject: [PATCH] rk3328: dt: add 1600mt and 1866mt timings
+
+Signed-off-by: Luke Lu <luke.lu@libretech.co>
+---
+ arch/arm/dts/rk3328-sdram-ddr4-1600.dtsi | 226 +++++++++++++++++++++++
+ arch/arm/dts/rk3328-sdram-ddr4-1866.dtsi | 226 +++++++++++++++++++++++
+ 2 files changed, 452 insertions(+)
+ create mode 100644 arch/arm/dts/rk3328-sdram-ddr4-1600.dtsi
+ create mode 100644 arch/arm/dts/rk3328-sdram-ddr4-1866.dtsi
+
+diff --git a/arch/arm/dts/rk3328-sdram-ddr4-1600.dtsi b/arch/arm/dts/rk3328-sdram-ddr4-1600.dtsi
+new file mode 100644
+index 00000000000..9594bb42839
+--- /dev/null
++++ b/arch/arm/dts/rk3328-sdram-ddr4-1600.dtsi
+@@ -0,0 +1,226 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++// Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd.
++
++&dmc {
++	rockchip,sdram-params = <
++		0x1
++		0xA
++		0x2
++		0x1
++		0x0
++		0x0
++		0x11
++		0x0
++		0x11
++		0x0
++		0
++
++		0x94496354
++		0x00000000
++		0x0000002a
++		0x000004e2
++		0x00000015
++		0x0000034a
++		0x000000ff
++
++		800
++		0
++		1
++		0
++		0
++
++		0x00000000
++		0x43041010
++		0x00000064
++		0x0061008c
++		0x000000d0
++		0x000200c5
++		0x000000d4
++		0x00500000
++		0x000000d8
++		0x00000100
++		0x000000dc
++		0x03140401
++		0x000000e0
++		0x00000000
++		0x000000e4
++		0x00110000
++		0x000000e8
++		0x00000420
++		0x000000ec
++		0x00000400
++		0x000000f4
++		0x000f011f
++		0x00000100
++		0x0c0e1b0e
++		0x00000104
++		0x00030314
++		0x00000108
++		0x0506050b
++		0x0000010c
++		0x0040400c
++		0x00000110
++		0x06030307
++		0x00000114
++		0x04040302
++		0x00000120
++		0x06060b06
++		0x00000124
++		0x00020308
++		0x00000180
++		0x01000040
++		0x00000184
++		0x00000000
++		0x00000190
++		0x07040003
++		0x00000198
++		0x05001100
++		0x000001a0
++		0xc0400003
++		0x00000240
++		0x0600060c
++		0x00000244
++		0x00000201
++		0x00000250
++		0x00000f00
++		0x00000490
++		0x00000001
++		0xffffffff
++		0xffffffff
++		0xffffffff
++		0xffffffff
++		0xffffffff
++		0xffffffff
++		0xffffffff
++		0xffffffff
++		0xffffffff
++		0xffffffff
++		0xffffffff
++		0xffffffff
++		0xffffffff
++		0xffffffff
++
++		0x00000004
++		0x0000000c
++		0x00000028
++		0x0000000c
++		0x0000002c
++		0x00000000
++		0x00000030
++		0x00000009
++		0xffffffff
++		0xffffffff
++
++		0x77
++		0x88
++		0x79
++		0x79
++		0x87
++		0x97
++		0x87
++		0x78
++		0x77
++		0x78
++		0x87
++		0x88
++		0x87
++		0x87
++		0x77
++
++		0x78
++		0x78
++		0x78
++		0x78
++		0x78
++		0x78
++		0x78
++		0x78
++		0x78
++		0x69
++		0x9
++
++		0x77
++		0x78
++		0x77
++		0x78
++		0x77
++		0x78
++		0x77
++		0x78
++		0x77
++		0x79
++		0x9
++
++		0x78
++		0x78
++		0x78
++		0x78
++		0x78
++		0x78
++		0x78
++		0x78
++		0x78
++		0x69
++		0x9
++
++		0x77
++		0x78
++		0x77
++		0x77
++		0x77
++		0x77
++		0x77
++		0x77
++		0x77
++		0x79
++		0x9
++
++		0x78
++		0x78
++		0x78
++		0x78
++		0x78
++		0x78
++		0x78
++		0x78
++		0x78
++		0x69
++		0x9
++
++		0x77
++		0x78
++		0x77
++		0x78
++		0x77
++		0x78
++		0x77
++		0x78
++		0x77
++		0x79
++		0x9
++
++		0x78
++		0x78
++		0x78
++		0x78
++		0x78
++		0x78
++		0x78
++		0x78
++		0x78
++		0x69
++		0x9
++
++		0x77
++		0x78
++		0x77
++		0x77
++		0x77
++		0x77
++		0x77
++		0x77
++		0x77
++		0x79
++		0x9
++	>;
++};
+diff --git a/arch/arm/dts/rk3328-sdram-ddr4-1866.dtsi b/arch/arm/dts/rk3328-sdram-ddr4-1866.dtsi
+new file mode 100644
+index 00000000000..db1e1e74ce3
+--- /dev/null
++++ b/arch/arm/dts/rk3328-sdram-ddr4-1866.dtsi
+@@ -0,0 +1,226 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++// Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd.
++
++&dmc {
++	rockchip,sdram-params = <
++		0x1
++		0xA
++		0x2
++		0x1
++		0x0
++		0x0
++		0x11
++		0x0
++		0x11
++		0x0
++		0
++
++		0x9869a3d7
++		0x00000000
++		0x0000002d
++		0x000004e2
++		0x00000015
++		0x00000352
++		0x000000ff
++
++		933
++		0
++		1
++		0
++		0
++
++		0x00000000
++		0x43041010
++		0x00000064
++		0x007100a4
++		0x000000d0
++		0x000200e5
++		0x000000d4
++		0x005d0000
++		0x000000d8
++		0x00000100
++		0x000000dc
++		0x05240401
++		0x000000e0
++		0x00080000
++		0x000000e4
++		0x00110000
++		0x000000e8
++		0x00000420
++		0x000000ec
++		0x00000400
++		0x000000f4
++		0x000f011f
++		0x00000100
++		0x0e0e1f10
++		0x00000104
++		0x00030317
++		0x00000108
++		0x0507050c
++		0x0000010c
++		0x0040400c
++		0x00000110
++		0x07030308
++		0x00000114
++		0x05050303
++		0x00000120
++		0x07070b07
++		0x00000124
++		0x00020309
++		0x00000180
++		0x01000040
++		0x00000184
++		0x00000000
++		0x00000190
++		0x07050003
++		0x00000198
++		0x05001100
++		0x000001a0
++		0xc0400003
++		0x00000240
++		0x06000610
++		0x00000244
++		0x00000201
++		0x00000250
++		0x00000f00
++		0x00000490
++		0x00000001
++		0xffffffff
++		0xffffffff
++		0xffffffff
++		0xffffffff
++		0xffffffff
++		0xffffffff
++		0xffffffff
++		0xffffffff
++		0xffffffff
++		0xffffffff
++		0xffffffff
++		0xffffffff
++		0xffffffff
++		0xffffffff
++
++		0x00000004
++		0x0000000c
++		0x00000028
++		0x0000000e
++		0x0000002c
++		0x00000000
++		0x00000030
++		0x0000000a
++		0xffffffff
++		0xffffffff
++
++		0x77
++		0x88
++		0x79
++		0x79
++		0x87
++		0x97
++		0x87
++		0x78
++		0x77
++		0x78
++		0x87
++		0x88
++		0x87
++		0x87
++		0x77
++
++		0x78
++		0x78
++		0x78
++		0x78
++		0x78
++		0x78
++		0x78
++		0x78
++		0x78
++		0x69
++		0x9
++
++		0x77
++		0x78
++		0x77
++		0x78
++		0x77
++		0x78
++		0x77
++		0x78
++		0x77
++		0x79
++		0x9
++
++		0x78
++		0x78
++		0x78
++		0x78
++		0x78
++		0x78
++		0x78
++		0x78
++		0x78
++		0x69
++		0x9
++
++		0x77
++		0x78
++		0x77
++		0x77
++		0x77
++		0x77
++		0x77
++		0x77
++		0x77
++		0x79
++		0x9
++
++		0x78
++		0x78
++		0x78
++		0x78
++		0x78
++		0x78
++		0x78
++		0x78
++		0x78
++		0x69
++		0x9
++
++		0x77
++		0x78
++		0x77
++		0x78
++		0x77
++		0x78
++		0x77
++		0x78
++		0x77
++		0x79
++		0x9
++
++		0x78
++		0x78
++		0x78
++		0x78
++		0x78
++		0x78
++		0x78
++		0x78
++		0x78
++		0x69
++		0x9
++
++		0x77
++		0x78
++		0x77
++		0x77
++		0x77
++		0x77
++		0x77
++		0x77
++		0x77
++		0x79
++		0x9
++	>;
++};
+
+From ed697b520da904136a555d49170461dbd8defc0e Mon Sep 17 00:00:00 2001
+From: Da Xue <da.xue@libretech.co>
+Date: Mon, 31 Jul 2023 02:48:16 -0400
+Subject: [PATCH] dt: roc-rk3328-cc: use 1600 ddr timings
+
+---
+ arch/arm/dts/rk3328-roc-cc-u-boot.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi b/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi
+index caae5297505..3c551621f2d 100644
+--- a/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi
++++ b/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi
+@@ -4,7 +4,7 @@
+  */
+
+ #include "rk3328-u-boot.dtsi"
+-#include "rk3328-sdram-ddr4-666.dtsi"
++#include "rk3328-sdram-ddr4-1600.dtsi"
+ / {
+	chosen {
+		u-boot,spl-boot-order = "same-as-spl", &spi0, &emmc, &sdmmc;
diff --git a/projects/Rockchip/patches/u-boot/0004-rockchip-rk3328-Set-VOP-QoS-to-high-priority.patch b/projects/Rockchip/patches/u-boot/default/0004-rockchip-rk3328-Set-VOP-QoS-to-high-priority.patch
similarity index 100%
rename from projects/Rockchip/patches/u-boot/0004-rockchip-rk3328-Set-VOP-QoS-to-high-priority.patch
rename to projects/Rockchip/patches/u-boot/default/0004-rockchip-rk3328-Set-VOP-QoS-to-high-priority.patch
diff --git a/projects/Rockchip/patches/u-boot/0005-rockchip-rk3288-Pick-SD-card-as-first-boot-device.patch b/projects/Rockchip/patches/u-boot/default/0005-rockchip-rk3288-Pick-SD-card-as-first-boot-device.patch
similarity index 100%
rename from projects/Rockchip/patches/u-boot/0005-rockchip-rk3288-Pick-SD-card-as-first-boot-device.patch
rename to projects/Rockchip/patches/u-boot/default/0005-rockchip-rk3288-Pick-SD-card-as-first-boot-device.patch
diff --git a/projects/Rockchip/patches/u-boot/default/0006-Rockchip-rk3399-evb-Don-t-initalize-i2c-bus-in-SPL.patch b/projects/Rockchip/patches/u-boot/default/0006-Rockchip-rk3399-evb-Don-t-initalize-i2c-bus-in-SPL.patch
new file mode 100644
index 0000000000..6eb8c2dde8
--- /dev/null
+++ b/projects/Rockchip/patches/u-boot/default/0006-Rockchip-rk3399-evb-Don-t-initalize-i2c-bus-in-SPL.patch
@@ -0,0 +1,37 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Alex Bee <knaerzche@gmail.com>
+Date: Mon, 31 Oct 2022 17:16:07 +0100
+Subject: [PATCH 6/6] Rockchip: rk3399-evb: Don't initalize i2c bus in SPL
+
+Since we are using this device as fallback for boards which are not supported
+by mainline u-boot in combination with vendor TPL/SPL, we need to make sure
+that i2c is initalized in BL33 because vendor bootchain doesn't do that in
+an earlier level.
+---
+ arch/arm/dts/rk3399-evb-u-boot.dtsi | 10 +---------
+ 1 file changed, 1 insertion(+), 9 deletions(-)
+
+diff --git a/arch/arm/dts/rk3399-evb-u-boot.dtsi b/arch/arm/dts/rk3399-evb-u-boot.dtsi
+index 5e39b1493d..18733da7f9 100644
+--- a/arch/arm/dts/rk3399-evb-u-boot.dtsi
++++ b/arch/arm/dts/rk3399-evb-u-boot.dtsi
+@@ -9,18 +9,10 @@
+ / {
+	chosen {
+		stdout-path = "serial2:1500000n8";
+-		u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc;
++		u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci;
+	};
+ };
+
+-&i2c0 {
+-	bootph-all;
+-};
+-
+-&rk808 {
+-	bootph-all;
+-};
+-
+ &tcphy1 {
+	status = "okay";
+ };
diff --git a/projects/Rockchip/patches/u-boot/default/patch.patch.disabled b/projects/Rockchip/patches/u-boot/default/patch.patch.disabled
new file mode 100644
index 0000000000..09a36d79d2
--- /dev/null
+++ b/projects/Rockchip/patches/u-boot/default/patch.patch.disabled
@@ -0,0 +1,12 @@
+diff -ruPN u-boot/arch/arm/dts/rk3328-roc-cc.dts u-boot-new/arch/arm/dts/rk3328-roc-cc.dts
+--- u-boot/arch/arm/dts/rk3328-roc-cc.dts	2024-01-08 16:37:48.000000000 +0100
++++ u-boot-new/arch/arm/dts/rk3328-roc-cc.dts	2024-04-29 18:30:42.982000132 +0200
+@@ -231,6 +231,8 @@
+				regulator-name = "vcc_ddr";
+				regulator-always-on;
+				regulator-boot-on;
++				regulator-min-microvolt = <1200000>;
++				regulator-max-microvolt = <1200000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
diff --git a/projects/Rockchip/patches/u-boot/default/xms6-rk3229_defconfig.patch b/projects/Rockchip/patches/u-boot/default/xms6-rk3229_defconfig.patch
new file mode 100644
index 0000000000..565531a16e
--- /dev/null
+++ b/projects/Rockchip/patches/u-boot/default/xms6-rk3229_defconfig.patch
@@ -0,0 +1,89 @@
+--- /dev/null	2019-06-24 09:31:44.666373967 +0000
++++ b/configs/xms6-rk3229_defconfig	2020-03-29 21:47:00.735897000 +0000
+@@ -0,0 +1,86 @@
++CONFIG_ARM=y
++CONFIG_ARCH_ROCKCHIP=y
++CONFIG_SYS_TEXT_BASE=0x61000000
++CONFIG_ROCKCHIP_RK322X=y
++CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0
++CONFIG_TPL_LDSCRIPT="arch/arm/mach-rockchip/u-boot-tpl.lds"
++CONFIG_TARGET_EVB_RK3229=y
++CONFIG_ENV_OFFSET=0x3F8000
++CONFIG_SPL_STACK_R_ADDR=0x60600000
++CONFIG_NR_DRAM_BANKS=2
++CONFIG_DEBUG_UART_BASE=0x11030000
++CONFIG_DEBUG_UART_CLOCK=24000000
++CONFIG_DEBUG_UART=y
++CONFIG_SPL_TEXT_BASE=0x60000000
++CONFIG_FIT=y
++CONFIG_FIT_VERBOSE=y
++CONFIG_SPL_LOAD_FIT=y
++CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/fit_spl_optee.sh"
++CONFIG_USE_PREBOOT=y
++CONFIG_DEFAULT_FDT_FILE="rk3229-evb.dtb"
++# CONFIG_DISPLAY_CPUINFO is not set
++CONFIG_DISPLAY_BOARDINFO_LATE=y
++# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
++CONFIG_SPL_STACK_R=y
++CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
++CONFIG_SPL_OPTEE=y
++CONFIG_CMD_GPT=y
++CONFIG_CMD_MMC=y
++CONFIG_CMD_USB_MASS_STORAGE=y
++# CONFIG_CMD_SETEXPR is not set
++CONFIG_CMD_TIME=y
++CONFIG_SPL_OF_CONTROL=y
++CONFIG_TPL_OF_CONTROL=y
++CONFIG_DEFAULT_DEVICE_TREE="rk3229-evb"
++CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
++CONFIG_ENV_IS_IN_MMC=y
++CONFIG_SYS_RELOC_GD_ENV_ADDR=y
++CONFIG_NET_RANDOM_ETHADDR=y
++CONFIG_REGMAP=y
++CONFIG_SPL_REGMAP=y
++CONFIG_TPL_REGMAP=y
++CONFIG_SYSCON=y
++CONFIG_SPL_SYSCON=y
++CONFIG_TPL_SYSCON=y
++CONFIG_CLK=y
++CONFIG_SPL_CLK=y
++CONFIG_TPL_CLK=y
++CONFIG_FASTBOOT_BUF_SIZE=0x04000000
++CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
++CONFIG_ROCKCHIP_GPIO=y
++CONFIG_SYS_I2C_ROCKCHIP=y
++CONFIG_MMC_DW=y
++CONFIG_MMC_DW_ROCKCHIP=y
++CONFIG_MTD=y
++CONFIG_DM_ETH=y
++CONFIG_ETH_DESIGNWARE=y
++CONFIG_GMAC_ROCKCHIP=y
++CONFIG_PHY=y
++CONFIG_PINCTRL=y
++CONFIG_RAM=y
++CONFIG_SPL_RAM=y
++CONFIG_TPL_RAM=y
++CONFIG_BAUDRATE=1500000
++CONFIG_DEBUG_UART_SHIFT=2
++CONFIG_SYSRESET=y
++CONFIG_USB=y
++CONFIG_USB_GADGET=y
++CONFIG_USB_GADGET_DWC2_OTG=y
++CONFIG_TPL_TINY_MEMSET=y
++CONFIG_ERRNO_STR=y
++
++CONFIG_ARM_SMCCC=y
++CONFIG_TEE=y
++CONFIG_OPTEE=y
++CONFIG_OPTEE_LOAD_ADDR=0x68400000
++CONFIG_OPTEE_TZDRAM_BASE=0x68400000
++CONFIG_OPTEE_TZDRAM_SIZE=0x00200000
++CONFIG_BOOTM_OPTEE=y
++CONFIG_SD_BOOT=y
++CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x61100000
++CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
++CONFIG_TEXT_BASE=0x61000000
++CONFIG_SYS_ARCH_TIMER=y
++CONFIG_SYS_BOOTM_LEN=0x4000000
++CONFIG_SYS_LOAD_ADDR=0x61800800
++CONFIG_SPL_NO_BSS_LIMIT=y
diff --git a/projects/Samsung/linux/linux.arm.conf b/projects/Samsung/linux/linux.arm.conf
index e77be073c4..8bfc3027cd 100644
--- a/projects/Samsung/linux/linux.arm.conf
+++ b/projects/Samsung/linux/linux.arm.conf
@@ -6861,6 +6861,7 @@ CONFIG_DEBUG_ATOMIC_SLEEP=y
 # CONFIG_SCF_TORTURE_TEST is not set
 # end of Lock Debugging (spinlocks, mutexes, etc...)
 
+# CONFIG_TRACE_IRQFLAGS is not set
 # CONFIG_DEBUG_IRQFLAGS is not set
 CONFIG_STACKTRACE=y
 # CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set
@@ -6879,6 +6880,7 @@ CONFIG_STACKTRACE=y
 #
 # RCU Debugging
 #
+# CONFIG_PROVE_RCU is not set
 # CONFIG_RCU_SCALE_TEST is not set
 # CONFIG_RCU_TORTURE_TEST is not set
 # CONFIG_RCU_REF_SCALE_TEST is not set
@@ -6905,6 +6907,7 @@ CONFIG_TRACE_CLOCK=y
 CONFIG_RING_BUFFER=y
 CONFIG_EVENT_TRACING=y
 CONFIG_CONTEXT_SWITCH_TRACER=y
+# CONFIG_PREEMPTIRQ_TRACEPOINTS is not set
 CONFIG_TRACING=y
 CONFIG_TRACING_SUPPORT=y
 CONFIG_FTRACE=y
diff --git a/projects/Samsung/patches/u-boot/u-boot-0001-add-odroid-xu4_defconfig-and-tweak-odroid-xu3_defcon.patch b/projects/Samsung/patches/u-boot/u-boot-0001-add-odroid-xu4_defconfig-and-tweak-odroid-xu3_defcon.patch
index d007100c83..bd9c91c10c 100644
--- a/projects/Samsung/patches/u-boot/u-boot-0001-add-odroid-xu4_defconfig-and-tweak-odroid-xu3_defcon.patch
+++ b/projects/Samsung/patches/u-boot/u-boot-0001-add-odroid-xu4_defconfig-and-tweak-odroid-xu3_defcon.patch
@@ -1,43 +1,43 @@
-From 0fa059a03304da39883f4e8df64edfcf4b93cef9 Mon Sep 17 00:00:00 2001
+From 802c90563efe1c04b401ad27fd63c628eb647d8d Mon Sep 17 00:00:00 2001
 From: Christian Hewitt <christianshewitt@gmail.com>
-Date: Wed, 30 Apr 2025 12:45:16 +0000
+Date: Wed, 30 Apr 2025 13:30:27 +0000
 Subject: [PATCH] add odroid-xu4_defconfig and tweak odroid-xu3_defconfig
 
 Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
 ---
  configs/odroid-xu3_defconfig |  4 +-
- configs/odroid-xu4_defconfig | 74 ++++++++++++++++++++++++++++++++++++
- 2 files changed, 76 insertions(+), 2 deletions(-)
+ configs/odroid-xu4_defconfig | 75 ++++++++++++++++++++++++++++++++++++
+ 2 files changed, 77 insertions(+), 2 deletions(-)
  create mode 100644 configs/odroid-xu4_defconfig
 
 diff --git a/configs/odroid-xu3_defconfig b/configs/odroid-xu3_defconfig
-index 6431f59568c..1cadf0f943f 100644
+index 718ec96cfbb..086fdbe3976 100644
 --- a/configs/odroid-xu3_defconfig
 +++ b/configs/odroid-xu3_defconfig
-@@ -14,7 +14,7 @@ CONFIG_ENV_SIZE=0x4000
+@@ -13,7 +13,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x42e00000
+ CONFIG_ENV_SIZE=0x4000
  CONFIG_ENV_OFFSET=0x310000
  CONFIG_DEFAULT_DEVICE_TREE="exynos5422-odroidxu3"
- CONFIG_SYS_LOAD_ADDR=0x43e00000
 -CONFIG_IDENT_STRING=" for ODROID-XU3/XU4/HC1/HC2"
 +CONFIG_IDENT_STRING=" for ODROID-XU3"
  CONFIG_SYS_MEM_TOP_HIDE=0x01600000
+ CONFIG_SYS_LOAD_ADDR=0x43e00000
  # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
- CONFIG_FIT=y
-@@ -28,7 +28,7 @@ CONFIG_BOARD_TYPES=y
+@@ -27,7 +27,7 @@ CONFIG_BOARD_TYPES=y
  CONFIG_DISPLAY_BOARDINFO_LATE=y
  CONFIG_BOARD_LATE_INIT=y
  CONFIG_MISC_INIT_R=y
 -CONFIG_SYS_PROMPT="ODROID-XU3 # "
-+CONFIG_SYS_PROMPT="XU3# "
++CONFIG_SYS_PROMPT="XU3 # "
+ CONFIG_SYS_PBSIZE=1024
  CONFIG_CMD_THOR_DOWNLOAD=y
  CONFIG_CMD_DFU=y
- CONFIG_CMD_GPIO=y
 diff --git a/configs/odroid-xu4_defconfig b/configs/odroid-xu4_defconfig
 new file mode 100644
-index 00000000000..1da725e9118
+index 00000000000..029a41bb87f
 --- /dev/null
 +++ b/configs/odroid-xu4_defconfig
-@@ -0,0 +1,74 @@
+@@ -0,0 +1,75 @@
 +CONFIG_ARM=y
 +CONFIG_SKIP_LOWLEVEL_INIT=y
 +CONFIG_ARCH_CPU_INIT=y
@@ -53,14 +53,13 @@ index 00000000000..1da725e9118
 +CONFIG_ENV_SIZE=0x4000
 +CONFIG_ENV_OFFSET=0x310000
 +CONFIG_DEFAULT_DEVICE_TREE="exynos5422-odroidxu3"
-+CONFIG_SYS_LOAD_ADDR=0x43e00000
 +CONFIG_IDENT_STRING=" for ODROID-XU4"
 +CONFIG_SYS_MEM_TOP_HIDE=0x01600000
++CONFIG_SYS_LOAD_ADDR=0x43e00000
 +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 +CONFIG_FIT=y
 +CONFIG_FIT_BEST_MATCH=y
 +CONFIG_DISTRO_DEFAULTS=y
-+CONFIG_SYS_PBSIZE=1024
 +CONFIG_SILENT_CONSOLE=y
 +CONFIG_CONSOLE_MUX=y
 +CONFIG_BOARD_TYPES=y
@@ -68,7 +67,8 @@ index 00000000000..1da725e9118
 +CONFIG_DISPLAY_BOARDINFO_LATE=y
 +CONFIG_BOARD_LATE_INIT=y
 +CONFIG_MISC_INIT_R=y
-+CONFIG_SYS_PROMPT="XU4# "
++CONFIG_SYS_PROMPT="XU4 # "
++CONFIG_SYS_PBSIZE=1024
 +CONFIG_CMD_THOR_DOWNLOAD=y
 +CONFIG_CMD_DFU=y
 +CONFIG_CMD_GPIO=y
diff --git a/scripts/uboot_helper b/scripts/uboot_helper
index 469374170e..fa12167759 100755
--- a/scripts/uboot_helper
+++ b/scripts/uboot_helper
@@ -285,6 +285,12 @@ devices = \
     },
   },
   'Rockchip': {
+      'RK322X': {
+      'rk322x': {
+        'dtb': 'rk322x-box.dtb',
+        'config': 'rk322x-box_defconfig'
+      },
+    },
     'RK3288': {
       'miqi': {
         'dtb': 'rk3288-miqi.dtb',
