Trying to boot from MMC1
Trying fit image at 0x4000 sector
## Verified-boot: 0
## Checking atf-1 0x00040000 ... sha256(d2f9701da5...) + OK
## Checking u-boot 0x00a00000 ... sha256(59dccb9b87...) + OK
## Checking fdt-1 0x00ab2ad0 ... sha256(fe6f55aa12...) + OK
## Checking atf-2 0x000f0000 ... sha256(b2af21b504...) + OK
## Checking atf-3 0xff100000 ... sha256(8899b10150...) + OK
Jumping to U-Boot(0x00a00000) via ARM Trusted Firmware(0x00040000)
Total: 818.385 ms

DDR 9fffbe1e78 cym 24/02/04-10:09:20,fwver: v1.16
LPDDR5, 2400MHz
channel[0] BW=16 Col=10 Bk=16 CS0 Row=16 CS=1 Die BW=16 Size=2048MB
channel[1] BW=16 Col=10 Bk=16 CS0 Row=16 CS=1 Die BW=16 Size=2048MB
channel[2] BW=16 Col=10 Bk=16 CS0 Row=16 CS=1 Die BW=16 Size=2048MB
channel[3] BW=16 Col=10 Bk=16 CS0 Row=16 CS=1 Die BW=16 Size=2048MB
Manufacturer ID:0xff
CH0 RX Vref:27.5%, TX Vref:19.0%,0.0%
CH1 RX Vref:28.3%, TX Vref:20.0%,0.0%
CH2 RX Vref:25.4%, TX Vref:19.0%,0.0%
CH3 RX Vref:28.5%, TX Vref:18.0%,0.0%
change to F1: 534MHz
change to F2: 1320MHz
change to F3: 1968MHz
change to F0: 2400MHz
out
U-Boot SPL board init
U-Boot SPL 2017.09-orangepi (Aug 30 2024 - 22:09:16)
Trying to boot from MMC1
Trying fit image at 0x4000 sector
## Verified-boot: 0
## Checking atf-1 0x00040000 ... sha256(d2f9701da5...) + OK
## Checking u-boot 0x00a00000 ... sha256(59dccb9b87...) + OK
## Checking fdt-1 0x00ab2ad0 ... sha256(fe6f55aa12...) + OK
## Checking atf-2 0x000f0000 ... sha256(b2af21b504...) + OK
## Checking atf-3 0xff100000 ... sha256(8899b10150...) + OK
Jumping to U-Boot(0x00a00000) via ARM Trusted Firmware(0x00040000)
Total: 586.347 ms

DDR 9fffbe1e78 cym 24/02/04-10:09:20,fwver: v1.16
LPDDR5, 2400MHz
channel[0] BW=16 Col=10 Bk=16 CS0 Row=16 CS=1 Die BW=16 Size=2048MB
channel[1] BW=16 Col=10 Bk=16 CS0 Row=16 CS=1 Die BW=16 Size=2048MB
channel[2] BW=16 Col=10 Bk=16 CS0 Row=16 CS=1 Die BW=16 Size=2048MB
channel[3] BW=16 Col=10 Bk=16 CS0 Row=16 CS=1 Die BW=16 Size=2048MB
Manufacturer ID:0xff
CH0 RX Vref:27.9%, TX Vref:19.0%,0.0%
CH1 RX Vref:28.3%, TX Vref:20.0%,0.0%
CH2 RX Vref:25.4%, TX Vref:20.0%,0.0%
CH3 RX Vref:28.5%, TX Vref:19.0%,0.0%
change to F1: 534MHz
change to F2: 1320MHz
change to F3: 1968MHz
change to F0: 2400MHz
out
U-Boot SPL board init
U-Boot SPL 2017.09-orangepi (Aug 30 2024 - 22:09:16)
Trying to boot from MMC1
Trying fit image at 0x4000 sector
## Verified-boot: 0
## Checking atf-1 0x00040000 ... sha256(d2f9701da5...) + OK
## Checking u-boot 0x00a00000 ... sha256(59dccb9b87...) + OK
## Checking fdt-1 0x00ab2ad0 ... sha256(fe6f55aa12...) + OK
## Checking atf-2 0x000f0000 ... sha256(b2af21b504...) + OK
## Checking atf-3 0xff100000 ... sha256(8899b10150...) + OK
Jumping to U-Boot(0x00a00000) via ARM Trusted Firmware(0x00040000)
Total: 585.600 ms

DDR 9fffbe1e78 cym 24/02/04-10:09:20,fwver: v1.16
LPDDR5, 2400MHz
channel[0] BW=16 Col=10 Bk=16 CS0 Row=16 CS=1 Die BW=16 Size=2048MB
channel[1] BW=16 Col=10 Bk=16 CS0 Row=16 CS=1 Die BW=16 Size=2048MB
channel[2] BW=16 Col=10 Bk=16 CS0 Row=16 CS=1 Die BW=16 Size=2048MB
channel[3] BW=16 Col=10 Bk=16 CS0 Row=16 CS=1 Die BW=16 Size=2048MB
Manufacturer ID:0xff
CH0 RX Vref:27.5%, TX Vref:18.0%,0.0%
CH1 RX Vref:28.3%, TX Vref:20.0%,0.0%
CH2 RX Vref:25.8%, TX Vref:18.0%,0.0%
CH3 RX Vref:28.5%, TX Vref:18.0%,0.0%
change to F1: 534MHz
change to F2: 1320MHz
change to F3: 1968MHz
change to F0: 2400MHz
out
U-Boot SPL board init
U-Boot SPL 2017.09-orangepi (Aug 30 2024 - 22:09:16)
Trying to boot from MMC1
Trying fit image at 0x4000 sector
## Verified-boot: 0
## Checking atf-1 0x00040000 ... sha256(d2f9701da5...) + OK
## Checking u-boot 0x00a00000 ... sha256(59dccb9b87...) + OK
## Checking fdt-1 0x00ab2ad0 ... sha256(fe6f55aa12...) + OK
## Checking atf-2 0x000f0000 ... sha256(b2af21b504...) + OK
## Checking atf-3 0xff100000 ... sha256(8899b10150...) + OK
Jumping to U-Boot(0x00a00000) via ARM Trusted Firmware(0x00040000)
Total: 585.681 ms

DDR 9fffbe1e78 cym 24/02/04-10:09:20,fwver: v1.16
LPDDR5, 2400MHz
channel[0] BW=16 Col=10 Bk=16 CS0 Row=16 CS=1 Die BW=16 Size=2048MB
channel[1] BW=16 Col=10 Bk=16 CS0 Row=16 CS=1 Die BW=16 Size=2048MB
channel[2] BW=16 Col=10 Bk=16 CS0 Row=16 CS=1 Die BW=16 Size=2048MB
channel[3] BW=16 Col=10 Bk=16 CS0 Row=16 CS=1 Die BW=16 Size=2048MB
Manufacturer ID:0xff
CH0 RX Vref:27.9%, TX Vref:19.0%,0.0%
CH1 RX Vref:28.3%, TX Vref:20.0%,0.0%
CH2 RX Vref:25.4%, TX Vref:19.0%,0.0%
CH3 RX Vref:29.3%, TX Vref:18.0%,0.0%
change to F1: 534MHz
change to F2: 1320MHz
change to F3: 1968MHz
change to F0: 2400MHz
out
U-Boot SPL board init
U-Boot SPL 2017.09-orangepi (Aug 30 2024 - 22:09:16)
Trying to boot from MMC1
Trying fit image at 0x4000 sector
## Verified-boot: 0
## Checking atf-1 0x00040000 ... sha256(d2f9701da5...) + OK
## Checking u-boot 0x00a00000 ... sha256(59dccb9b87...) + OK
## Checking fdt-1 0x00ab2ad0 ... sha256(fe6f55aa12...) + OK
## Checking atf-2 0x000f0000 ... sha256(b2af21b504...) + OK
## Checking atf-3 0xff100000 ... sha256(8899b10150...) + OK
Jumping to U-Boot(0x00a00000) via ARM Trusted Firmware(0x00040000)
Total: 585.621 ms

DDR 9fffbe1e78 cym 24/02/04-10:09:20,fwver: v1.16
LPDDR5, 2400MHz
channel[0] BW=16 Col=10 Bk=16 CS0 Row=16 CS=1 Die BW=16 Size=2048MB
channel[1] BW=16 Col=10 Bk=16 CS0 Row=16 CS=1 Die BW=16 Size=2048MB
channel[2] BW=16 Col=10 Bk=16 CS0 Row=16 CS=1 Die BW=16 Size=2048MB
channel[3] BW=16 Col=10 Bk=16 CS0 Row=16 CS=1 Die BW=16 Size=2048MB
Manufacturer ID:0xff
CH0 RX Vref:27.9%, TX Vref:19.0%,0.0%
CH1 RX Vref:28.3%, TX Vref:20.0%,0.0%
CH2 RX Vref:25.4%, TX Vref:19.0%,0.0%
CH3 RX Vref:28.5%, TX Vref:18.0%,0.0%
change to F1: 534MHz
change to F2: 1320MHz
change to F3: 1968MHz
change to F0: 2400MHz
out
U-Boot SPL board init
U-Boot SPL 2017.09-orangepi (Aug 30 2024 - 22:09:16)
Trying to boot from MMC1
Trying fit image at 0x4000 sector
## Verified-boot: 0
## Checking atf-1 0x00040000 ... sha256(d2f9701da5...) + OK
## Checking u-boot 0x00a00000 ... sha256(59dccb9b87...) + OK
## Checking fdt-1 0x00ab2ad0 ... sha256(fe6f55aa12...) + OK
## Checking atf-2 0x000f0000 ... sha256(b2af21b504...) + OK
## Checking atf-3 0xff100000 ... sha256(8899b10150...) + OK
Jumping to U-Boot(0x00a00000) via ARM Trusted Firmware(0x00040000)
Total: 585.85 ms

DDR 9fffbe1e78 cym 24/02/04-10:09:20,fwver: v1.16
LPDDR5, 2400MHz
channel[0] BW=16 Col=10 Bk=16 CS0 Row=16 CS=1 Die BW=16 Size=2048MB
channel[1] BW=16 Col=10 Bk=16 CS0 Row=16 CS=1 Die BW=16 Size=2048MB
channel[2] BW=16 Col=10 Bk=16 CS0 Row=16 CS=1 Die BW=16 Size=2048MB
channel[3] BW=16 Col=10 Bk=16 CS0 Row=16 CS=1 Die BW=16 Size=2048MB
Manufacturer ID:0xff
CH0 RX Vref:27.9%, TX Vref:18.0%,0.0%
CH1 RX Vref:28.3%, TX Vref:20.0%,0.0%
CH2 RX Vref:25.4%, TX Vref:19.0%,0.0%
CH3 RX Vref:28.5%, TX Vref:18.0%,0.0%
change to F1: 534MHz
change to F2: 1320MHz
change to F3: 1968MHz
change to F0: 2400MHz
out
U-Boot SPL board init
U-Boot SPL 2017.09-orangepi (Aug 30 2024 - 22:09:16)