DDR Version 1.24 20191016
In
channel 0
CS = 0
MR0=0x19
MR4=0x3
MR5=0x6
MR8=0x0
MR12=0x72
MR14=0x72
MR18=0x0
MR19=0x0
MR24=0x8
MR25=0xFF
channel 1
CS = 0
MR0=0x19
MR4=0x3
MR5=0x6
MR8=0x0
MR12=0x72
MR14=0x72
MR18=0x0
MR19=0x0
MR24=0x8
MR25=0xFF
channel 0 training pass!
channel 1 training pass!
change freq to 416MHz 0,1
Channel 0: LPDDR4,416MHz
Bus Width=32 Col=10 Bank=8 Row=14 CS=1 Die Bus-Width=16 Size=512MB
Channel 1: LPDDR4,416MHz
Bus Width=32 Col=10 Bank=8 Row=14 CS=1 Die Bus-Width=16 Size=512MB
256B stride
channel 0
CS = 0
MR0=0x19
MR4=0x3
MR5=0x6
MR8=0x0
MR12=0x72
MR14=0x72
MR18=0x0
MR19=0x0
MR24=0x8
MR25=0xFF
channel 1
CS = 0
MR0=0x19
MR4=0x3
MR5=0x6
MR8=0x0
MR12=0x72
MR14=0x72
MR18=0x0
MR19=0x0
MR24=0x8
MR25=0xFF
channel 0 training pass!
channel 1 training pass!
channel 0, cs 0, advanced training done