DDR Version 1.17 20190115 In channel 0 CS = 0 MR0=0x18 MR4=0x1 MR5=0x6 MR8=0x8 MR12=0x72 MR14=0x72 MR18=0x0 MR19=0x0MR24=0x8 MR25=0xFF CS = 1 MR0=0x18 MR4=0x1 MR5=0x6 MR8=0x8 MR12=0x72 MR14=0x72 MR18=0x0 MR19=0x0 MR24=0x8 MR25=0xFF channel 1 CS = 0 MR0=0x18 MR4=0x1 MR5=0x6 MR8=0x8 MR12=0x72 MR14=0x72 MR18=0x0 MR19=0x0 MR24=0x8 MR25=0xFF CS = 1 MR4=0x1 MR5=0x6 MR8=0x8 MR12=0x72 MR14=0x72 MR18=0x0 MR19=0x0 MR24=0x8 MR25=0xFF channel 0 training pass! channel 1 training pass! change freq to 400channel 0 CS = 0 MR0=0x18 MR4=0x1 MR5=0x6 MR8=0x8 MR12=0x72 MR14=0x72 MR18=0x0 MR19=0x0 MR24=0x8 MR25=0xFF CS = 1 MR0=0x18 MR4=0x1 MR5=0x6 MR8=0=0x72 MR14=0x72 MR18=0x0 MR19=0x0 MR24=0x8 MR25=0xFF channel 1 CS = 0 MR0=0x18 MR4=0x1 MR5=0x6 MR8=0x8 MR12=0x72 MR14=0x72 MR18=0x0 MR19=0x0 MR24=0x8 MR25=0xFF CS = 1 MR0=0x=0x1 MR5=0x6 MR8=0x8 MR12=0x72 MR14=0x72 MR18=0x0 MR19=0x0 MR24=0x8 MR25=0xFF channel 0 training pass! channel 1 training pass! change freq to 800MHzDR4,800MHz Bus Width=32 Col=10 Bank=8 Row=15/15 CS=2 Die Bus-WiChannel 1: LPDDR4,800MHz Bus Width=32 Col=10 Bank=8 Row=15/15 Ce=2048MB 256B stride nfig = 0x101, ddrsize = 0x2020e = 0x2020 pmugrf_os_reg[2] = 0x3AA1FAA1, stride = 0xD OUT Boot1 Release Time: Dec 24 2019 18:00:26, version: 1.24 CPUId =pe = 0x10, 312 mmc: ERROR: SDHCI ERR:cmd:0x102,stat:0x18000 mmc: ERROR: Card did not respond to voltage selectmmc: ERROR: SDHCI ERR:cmd:0x10 mmc: ERROR: Card dlect! emmc reinit mmc: ERROR: SDHCI ERR:cmd:0x102,stat:0x18000 not respond to voltage select! SdmmcInit=2 1 mmc0:cmd5,20 SdmmcInit=0 0 BootCapSize=0 UserCapSize=15193MB FwPartOffset=2000 , 0 StorageInit ok = 56287 SecureMode = 0 SecureInit rea: 0x4 SecureInit read PBA: 0x404 SecureInit read PBA: 0x804 SecureInit read PBA: 0xc04 SecureInit read PBA: 0x1004 SecureInit read PBA: 0x1404 SecureInit read PBA: 0x1804 SecureInit read PBA: 0x1c04 SecureInit ret = 0, SecureMode = 0 GPT 0x3380ea0 signature is wrong recovery gpGPT 0x3380ea0 signature is wrongNo find bl30.bin No find bl32.bin Load uboot, ReadLba = 2000 Load OK, addr=0x200000, size=0xc999c RunBL31 0x40000 @ 166734 us NOTICE: BL31: v1.3(debug):734d84297 NOTICE: BL31: Built : 15: Dec 12 2019 NOTICE: BL31: Rockchip release version: v1.1 INFO: GICv3 with legacy support detected. ARM GICV3 driver initialized in EL3 INFO: Using opteed sec cpu_context! INFO: boot cpu mask: 0 INFO: If lpddr4 need support ulti frequency, INFO: please update loader! INFO: Current ctl index[0] freq=400MHz INFOt ctl index[1] freq=800MHz INFO: plat_rockchip_pmu_init(1190L31: Initializing runtime services WARNING: No OPTEE provided by BL2 boot loader, Booting devication. SMC`s destinK ERROR: Error initializing runtime service: Preparing for EL3 exit to normal wd INFO: Entry point address = 0x200000 INFO: SPSR U-Boot 2021.01 (Apr 01 2021 - 09:35:39 +0300) SoC: Rockch9 Reset cause: POR Model: Firefly ROC-RK3399-PC Mezzanine Board DRAM: 3.9 GiB PMIC: RK808 MMC: mmc@fe310000: 2, mmc@fe320000: 1, sdhci@fe330000: 0 Loading Environment from SPIFlash... Invalid bus 0 (err=-19) **g - spi_flash_probe_bus_cs() failed, using default environment In: serial Out: serial Err: serial Model: Firefly ROC-RK3399-PC Mezzanine Board Net: Error: ethernet@fe300000 address not set. Hit any key to stop autoboot: 0 starting USB... Bus usb@fe380000: USB EHCI 1.00 Bus usb@fe3c0000: USB EHCI 1.00 Bus dwc3: usb maximum-speed not found Register 2000140 NbrPorts 2 Starting the controller USB XHCI 1380000 for devices... 1 USB Device(s) found scanning bus usb@fe3c0000 for devices... 3 USB Device(s) found scanning bus dwc3 for devices... 1 USB Device(s) found scanning usb for storage devices.. Device 0: unknown device switch to partitions #0, OK mmc1 is current device Scanning mmc 1:1... Found /extlinux/extlinux.conf Retrieving file: /extlinux/extlin209 bytes read in 9 ms (22.5 KiB/s) 1: LibreELEC Retrieving file: /KERNEL 30920712 bytes read in 1947 ms (15.1 MiB/s) append: boot=LABEL=LIBREELEC disk=LABEL=STORAGE quiet console=uart8250,mmio32,02 Retrieving file: /dtb/rockchip/rk3399-roc-pc-mezzanine.dtb 77110 bytes read in 16 ms (4.6 MiB/s) Moving Image from 0x2080000 to 0x2200000, end=4080000 ## Flattened Device Tree blob at 01f00000 Booting using the dt blob at 0x1f00000 Loading Device Tree to 00000000f1f09000, end 00000000f1f1ed35OK Starting kernel ... [ 1.586105] rk_gmac-dwmac fe300000.ethernet: phy regulator is not available g [ 2.036115] no UART detected at 0x1 [ 2.138574] mmc1: tuning execution failed: -5 [ 2.138971]tialising SD card [ 2.616079] rockchip-pcie f8000000.pcie: PCIe link training g[ 2.882309] ) [ 2.886632] rk_gmac-dwmac fe300000.ethernet: cannot get clock clk_mac_speed [ 3.383856] dwmmc_rockchip fe320000.mmc: Busy; trying anyway LibreELEC:/ #