G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:800;NAND:81;SD?:0;SD:0;READ:0;0 . bl2_stage_init 0x01 bl2_stage_init 0x81 hw id: 0x0000 - pwm id 0x01 bl2_stage_init 0xc1 bl2_stage_init 0x02 no sdio debug board detected L0:00000000 L1:00000703 L2:0000c067 L3:14000020 B2:00402000 B1:e0f83180 TE: 242265 BL2 Built : 10:47:19, Jan 14 2019. g12b g152d217 - guotai.shen@droid11-sz Board ID = 5 Set A53 clk to 24M Set A73 clk to 24M Set clk81 to 24M A53 clk: 1200 MHz A73 clk: 1200 MHz CLK81: 166.6M smccc: 0003fae5 DDR driver_vesion: LPDDR4_PHY_V_0_1_11 build time: Jan 14 2019 10:47:15 board id: 5 Load FIP HDR from SD, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0 fw parse done Load ddrfw from SD, src: 0x00060200, des: 0xfffd0000, size: 0x0000c000, part: 0 Load ddrfw from SD, src: 0x00038200, des: 0xfffd0000, size: 0x00004000, part: 0 PIEI prepare done Cfg max: 2, cur: 1. Board id: 255. Force loop cfg DDR4 probe ddr clk to 1320MHz Load ddrfw from SD, src: 0x00014200, des: 0xfffd0000, size: 0x0000c000, part: 0 Check phy result INFO : End of initialization INFO : End of read enable training INFO : End of fine write leveling INFO : End of read dq deskew training INFO : End of MPR read delay center optimization INFO : End of Write leveling coarse delay INFO : End of write delay center optimization INFO : End of read delay center optimization INFO : End of max read latency training INFO : Training has run successfully! 1D training succeed Load ddrfw from SD, src: 0x00020200, des: 0xfffd0000, size: 0x0000c000, part: 0 Check phy result INFO : End of initialization INFO : End of 2D read delay Voltage center optimization INFO : End of 2D write delay Voltage center optimization INFO : Training has run successfully! R0_RxClkDly_Margin==70 ps 6 R0_TxDqDly_Margi==106 ps 9 R1_RxClkDly_Margin==0 ps 0 R1_TxDqDly_Margi==0 ps 0 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0001 ddr scramble enable 2D training succeed auto size-- 65535DDR cs0 size: 2048MB DDR cs1 size: 2048MB DMC_DDR_CTRL: 00600024DDR size: 3928MB cs0 DataBus test pass cs1 DataBus test pass cs0 AddrBus test pass cs1 AddrBus test pass pre test bdlr_100_average==416 bdlr_100_min==416 bdlr_100_max==416 bdlr_100_cur==416 aft test bdlr_100_average==416 bdlr_100_min==416 bdlr_100_max==416 bdlr_100_cur==416 100bdlr_step_size ps== 420 result report boot times 0Enable ddr reg access Load FIP HDR from SD, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0 Load BL3X from SD, src: 0x0006c200, des: 0x0175c000, size: 0x00094000, part: 0 Never should be here! reset... 0.0;M3 CHK:0;cm4_sp_mode 0 E30HDR MVN_1=0x00000000 MVN_2=0x00000000 [ImageG12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:800;NAND:81;SD?:0;SD:0;RE AD:0;0.ý!,KýýEýý}ýýýA0x01 bl2_stage_init 0x81 hw id: 0x0000 - pwm id 0x01 bl2_stage_init 0xc1 bl2_stage_init 0x02 no sdio debug board detected L0:00000000 L1:00000703 L2:0000c067 L3:14000020 B2:00402000 B1:e0f83180 TE: 130957 BL2 Built : 10:47:19, Jan 14 2019. g12b g152d217 - guotai.shen@droid11-sz Board ID = 5 Set A53 clk to 24M Set A73 clk to 24M Set clk81 to 24M A53 clk: 1200 MHz A73 clk: 1200 MHz CLK81: 166.6M smccc: 0002481a DDR driver_vesion: LPDDR4_PHY_V_0_1_11 build time: Jan 14 2019 10:47:15 board id: 5 Load FIP HDR from SD, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0 fw parse done Load ddrfw from SD, src: 0x00060200, des: 0xfffd0000, size: 0x0000c000, part: 0 Load ddrfw from SD, src: 0x00038200, des: 0xfffd0000, size: 0x00004000, part: 0 PIEI prepare done Cfg max: 2, cur: 1. Board id: 255. Force loop cfg DDR4 probe ddr clk to 1320MHz Load ddrfw from SD, src: 0x00014200, des: 0xfffd0000, size: 0x0000c000, part: 0 Check phy result INFO : End of initialization INFO : End of read enable training INFO : End of fine write leveling INFO : End of read dq deskew training INFO : End of MPR read delay center optimization INFO : End of Write leveling coarse delay INFO : End of write delay center optimization INFO : End of read delay center optimization INFO : End of max read latency training INFO : Training has run successfully! 1D training succeed Load ddrfw from SD, src: 0x00020200, des: 0xfffd0000, size: 0x0000c000, part: 0 Check phy result INFO : End of initialization INFO : End of 2D read delay Voltage center optimization INFO : End of 2D write delay Voltage center optimization INFO : Training has run successfully! R0_RxClkDly_Margin==82 ps 7 R0_TxDqDly_Margi==118 ps 10 R1_RxClkDly_Margin==0 ps 0 R1_TxDqDly_Margi==0 ps 0 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0001 ddr scramble enable 2D training succeed auto size-- 65535DDR cs0 size: 2048MB DDR cs1 size: 2048MB DMC_DDR_CTRL: 00600024DDR size: 3928MB cs0 DataBus test pass cs1 DataBus test pass cs0 AddrBus test pass cs1 AddrBus test pass pre test bdlr_100_average==416 bdlr_100_min==416 bdlr_100_max==416 bdlr_100_cur==416 aft test bdlr_100_average==416 bdlr_100_min==416 bdlr_100_max==416 bdlr_100_cur==416 100bdlr_step_size ps== 411 result report boot times 1Enable ddr reg access Load FIP HDR from SD, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0 Load BL3X from SD, src: 0x0006c200, des: 0x0175c000, size: 0x00094000, part: 0 Never should be here! reset... 0.0;M3 CHK:0;cm4_sp_mode 0 E30HDR MVN_1=0x00000000 MVN_2=0x00000000 [ImageG12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:800;NAND:81;SD?:0;SD:0;RE AD:0;0. bl2_stage_init 0x01 bl2_stage_init 0x81 hw id: 0x0000 - pwm id 0x01 bl2_stage_init 0xc1 bl2_stage_init 0x02 no sdio debug board detected L0:00000000 L1:00000703 L2:0000c067 L3:14000020 B2:00402000 B1:e0f83180 TE: 130966 BL2 Built : 10:47:19, Jan 14 2019. g12b g152d217 - guotai.shen@droid11-sz Board ID = 5 Set A53 clk to 24M Set A73 clk to 24M Set clk81 to 24M A53 clk: 1200 MHz A73 clk: 1200 MHz CLK81: 166.6M smccc: 00024823 DDR driver_vesion: LPDDR4_PHY_V_0_1_11 build time: Jan 14 2019 10:47:15 board id: 5 Load FIP HDR from SD, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0 fw parse done Load ddrfw from SD, src: 0x00060200, des: 0xfffd0000, size: 0x0000c000, part: 0 Load ddrfw from SD, src: 0x00038200, des: 0xfffd0000, size: 0x00004000, part: 0 PIEI prepare done Cfg max: 2, cur: 1. Board id: 255. Force loop cfg DDR4 probe ddr clk to 1320MHz Load ddrfw from SD, src: 0x00014200, des: 0xfffd0000, size: 0x0000c000, part: 0 Check phy result INFO : End of initialization INFO : End of read enable training INFO : End of fine write leveling INFO : End of read dq deskew training INFO : End of MPR read delay center optimization INFO : End of Write leveling coarse delay INFO : End of write delay center optimization INFO : End of read delay center optimization INFO : End of max read latency training INFO : Training has run successfully! 1D training succeed Load ddrfw from SD, src: 0x00020200, des: 0xfffd0000, size: 0x0000c000, part: 0 Check phy result INFO : End of initialization INFO : End of 2D read delay Voltage center optimization INFO : End of 2D write delay Voltage center optimization INFO : Training has run successfully! R0_RxClkDly_Margin==82 ps 7 R0_TxDqDly_Margi==106 ps 9 R1_RxClkDly_Margin==0 ps 0 R1_TxDqDly_Margi==0 ps 0 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0001 ddr scramble enable 2D training succeed auto size-- 65535DDR cs0 size: 2048MB DDR cs1 size: 2048MB DMC_DDR_CTRL: 00600024DDR size: 3928MB cs0 DataBus test pass cs1 DataBus test pass cs0 AddrBus test pass cs1 AddrBus test pass pre test bdlr_100_average==420 bdlr_100_min==420 bdlr_100_max==420 bdlr_100_cur==420 aft test bdlr_100_average==420 bdlr_100_min==420 bdlr_100_max==420 bdlr_100_cur==420 100bdlr_step_size ps== 416 result report boot times 2Enable ddr reg access Load FIP HDR from SD, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0 Load BL3X from SD, src: 0x0006c200, des: 0x0175c000, size: 0x00094000, part: 0 Never should be here! reset... 0.0;M3 CHK:0;cm4_sp_mode 0 E30HDR MVN_1=0x00000000 MVN_2=0x00000000 [ImagýG12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:800;NAND:81;SD?:0;SD:0;RE AD:0;0. bl2_stage_init 0x01 bl2_stage_init 0x81 hw id: 0x0000 - pwm id 0x01 bl2_stage_init 0xc1 bl2_stage_init 0x02 no sdio debug board detected L0:00000000 L1:00000703 L2:0000c067 L3:14000020 B2:00402000 B1:e0f83180 TE: 130992 BL2 Built : 10:47:19, Jan 14 2019. g12b g152d217 - guotai.shen@droid11-sz Board ID = 5 Set A53 clk to 24M Set A73 clk to 24M Set clk81 to 24M A53 clk: 1200 MHz A73 clk: 1200 MHz CLK81: 166.6M smccc: 0002483d DDR driver_vesion: LPDDR4_PHY_V_0_1_11 build time: Jan 14 2019 10:47:15 board id: 5 Load FIP HDR from SD, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0 fw parse done Load ddrfw from SD, src: 0x00060200, des: 0xfffd0000, size: 0x0000c000, part: 0 Load ddrfw from SD, src: 0x00038200, des: 0xfffd0000, size: 0x00004000, part: 0 PIEI prepare done Cfg max: 2, cur: 1. Board id: 255. Force loop cfg DDR4 probe ddr clk to 1320MHz Load ddrfw from SD, src: 0x00014200, des: 0xfffd0000, size: 0x0000c000, part: 0 Check phy result INFO : End of initialization INFO : End of read enable training INFO : End of fine write leveling INFO : End of read dq deskew training INFO : End of MPR read delay center optimization INFO : End of Write leveling coarse delay INFO : End of write delay center optimization INFO : End of read delay center optimization INFO : End of max read latency training INFO : Training has run successfully! 1D training succeed Load ddrfw from SD, src: 0x00020200, des: 0xfffd0000, size: 0x0000c000, part: 0 Check phy result INFO : End of initialization INFO : End of 2D read delay Voltage center optimization INFO : End of 2D write delay Voltage center optimization INFO : Training has run successfully! R0_RxClkDly_Margin==94 ps 8 R0_TxDqDly_Margi==106 ps 9 R1_RxClkDly_Margin==0 ps 0 R1_TxDqDly_Margi==0 ps 0 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0001 ddr scramble enable 2D training succeed auto size-- 65535DDR cs0 size: 2048MB DDR cs1 size: 2048MB DMC_DDR_CTRL: 00600024DDR size: 3928MB cs0 DataBus test pass cs1 DataBus test pass cs0 AddrBus test pass cs1 AddrBus test pass pre test bdlr_100_average==416 bdlr_100_min==416 bdlr_100_max==416 bdlr_100_cur==416 aft test bdlr_100_average==416 bdlr_100_min==416 bdlr_100_max==416 bdlr_100_cur==416 100bdlr_step_size ps== 420 result report boot times 3Enable ddr reg access Load FIP HDR from SD, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0 Load BL3X from SD, src: 0x0006c200, des: 0x0175c000, size: 0x00094000, part: 0 Never should be here! reset... 0.0;M3 CHK:0;cm4_sp_mode 0 E30HDR MVN_1=0x00000000 MVN_2=0x00000000 [ImageG12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:800;NAND:81;SD?:0;SD:0;RE AD:0;0. bl2_stage_init 0x01 bl2_stage_init 0x81 hw id: 0x0000 - pwm id 0x01 bl2_stage_init 0xc1 bl2_stage_init 0x02 no sdio debug board detected L0:00000000 L1:00000703 L2:0000c067 L3:14000020 B2:00402000 B1:e0f83180 TE: 131010 BL2 Built : 10:47:19, Jan 14 2019. g12b g152d217 - guotai.shen@droid11-sz Board ID = 5 Set A53 clk to 24M Set A73 clk to 24M Set clk81 to 24M A53 clk: 1200 MHz A73 clk: 1200 MHz CLK81: 166.6M smccc: 0002484f DDR driver_vesion: LPDDR4_PHY_V_0_1_11 build time: Jan 14 2019 10:47:15 board id: 5 Load FIP HDR from SD, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0 fw parse done Load ddrfw from SD, src: 0x00060200, des: 0xfffd0000, size: 0x0000c000, part: 0 Load ddrfw from SD, src: 0x00038200, des: 0xfffd0000, size: 0x00004000, part: 0 PIEI prepare done Cfg max: 2, cur: 1. Board id: 255. Force loop cfg DDR4 probe ddr clk to 1320MHz Load ddrfw from SD, src: 0x00014200, des: 0xfffd0000, size: 0x0000c000, part: 0 Check phy result INFO : End of initialization INFO : End of read enable training INFO : End of fine write leveling INFO : End of read dq deskew training INFO : End of MPR read delay center optimization INFO : End of Write leveling coarse delay INFO : End of write delay center optimization INFO : End of read delay center optimization INFO : End of max read latency training INFO : Training has run successfully! 1D training succeed Load ddrfw from SD, src: 0x00020200, des: 0xfffd0000, size: 0x0000c000, part: 0 Check phy result INFO : End of initialization INFO : End of 2D read delay Voltage center optimization INFO : End of 2D write delay Voltage center optimization INFO : Training has run successfully! R0_RxClkDly_Margin==94 ps 8 R0_TxDqDly_Margi==106 ps 9 R1_RxClkDly_Margin==0 ps 0 R1_TxDqDly_Margi==0 ps 0 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0001 ddr scramble enable 2D training succeed auto size-- 65535DDR cs0 size: 2048MB DDR cs1 size: 2048MB DMC_DDR_CTRL: 00600024DDR size: 3928MB cs0 DataBus test pass cs1 DataBus test pass cs0 AddrBus test pass cs1 AddrBus test pass pre test bdlr_100_average==416 bdlr_100_min==416 bdlr_100_max==416 bdlr_100_cur==416 aft test bdlr_100_average==416 bdlr_100_min==416 bdlr_100_max==416 bdlr_100_cur==416 100bdlr_step_size ps== 411 result report boot times 4Enable ddr reg access Load FIP HDR from SD, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0 Load BL3X from SD, src: 0x0006c200, des: 0x0175c000, size: 0x00094000, part: 0 Never should be here! reset... 0.0;M3 CHK:0;cm4_sp_mode 0 E30HDR MVN_1=0x00000000 MVN_2=0x00000000 [ImageG12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:800;NAND:81;SD?:0;SD:0;RE AD:0;0. bl2_stage_init 0x01 bl2_stage_init 0x81 hw id: 0x0000 - pwm id 0x01 bl2_stage_init 0xc1 bl2_stage_init 0x02 no sdio debug board detected L0:00000000 L1:00000703 L2:0000c067 L3:14000020 B2:00402000 B1:e0f83180 TE: 130966 BL2 Built : 10:47:19, Jan 14 2019. g12b g152d217 - guotai.shen@droid11-sz Board ID = 5 Set A53 clk to 24M Set A73 clk to 24M Set clk81 to 24M A53 clk: 1200 MHz A73 clk: 1200 MHz CLK81: 166.6M smccc: 00024823 DDR driver_vesion: LPDDR4_PHY_V_0_1_11 build time: Jan 14 2019 10:47:15 board id: 5 Load FIP HDR from SD, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0 fw parse done Load ddrfw from SD, src: 0x00060200, des: 0xfffd0000, size: 0x0000c000, part: 0 Load ddrfw from SD, src: 0x00038200, des: 0xfffd0000, size: 0x00004000, part: 0 PIEI prepare done Cfg max: 2, cur: 1. Board id: 255. Force loop cfg DDR4 probe ddr clk to 1320MHz Load ddrfw from SD, src: 0x00014200, des: 0xfffd0000, size: 0x0000c000, part: 0 Check phy result INFO : End of initialization INFO : End of read enable training INFO : End of fine write leveling INFO : End of read dq deskew training INFO : End of MPR read delay center optimization INFO : End of Write leveling coarse delay INFO : End of write delay center optimization INFO : End of read delay center optimization INFO : End of max read latency training INFO : Training has run successfully! 1D training succeed Load ddrfw from SD, src: 0x00020200, des: 0xfffd0000, size: 0x0000c000, part: 0 Check phy result INFO : End of initialization INFO : End of 2D read delay Voltage center optimization INFO : End of 2D write delay Voltage center optimization INFO : Training has run successfully! R0_RxClkDly_Margin==94 ps 8 R0_TxDqDly_Margi==106 ps 9 R1_RxClkDly_Margin==0 ps 0 R1_TxDqDly_Margi==0 ps 0 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0001 ddr scramble enable 2D training succeed auto size-- 65535DDR cs0 size: 2048MB DDR cs1 size: 2048MB DMC_DDR_CTRL: 00600024DDR size: 3928MB cs0 DataBus test pass cs1 DataBus test pass cs0 AddrBus test pass cs1 AddrBus test pass pre test bdlr_100_average==416 bdlr_100_min==416 bdlr_100_max==416 bdlr_100_cur==416 aft test bdlr_100_average==416 bdlr_100_min==416 bdlr_100_max==416 bdlr_100_cur==416 100bdlr_step_size ps== 420 result report boot times 5Enable ddr reg access Load FIP HDR from SD, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0 Load BL3X from SD, src: 0x0006c200, des: 0x0175c000, size: 0x00094000, part: 0 Never should be here! reset... 0.0;M3 CHK:0;cm4_sp_mode 0 E30HDR MVN_1=0x00000000 MVN_2=0x00000000 [ImagýG12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:800;NAND:81;SD?:0;SD:0;RE AD:0;0. bl2_stage_init 0x01 bl2_stage_init 0x81 hw id: 0x0000 - pwm id 0x01 bl2_stage_init 0xc1 bl2_stage_init 0x02 no sdio debug board detected L0:00000000 L1:00000703 L2:0000c067 L3:14000020 B2:00402000 B1:e0f83180 TE: 130984 BL2 Built : 10:47:19, Jan 14 2019. g12b g152d217 - guotai.shen@droid11-sz Board ID = 5 Set A53 clk to 24M Set A73 clk to 24M Set clk81 to 24M A53 clk: 1200 MHz A73 clk: 1200 MHz CLK81: 166.6M smccc: 00024834 DDR driver_vesion: LPDDR4_PHY_V_0_1_11 build time: Jan 14 2019 10:47:15 board id: 5 Load FIP HDR from SD, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0 fw parse done Load ddrfw from SD, src: 0x00060200, des: 0xfffd0000, size: 0x0000c000, part: 0 Load ddrfw from SD, src: 0x00038200, des: 0xfffd0000, size: 0x00004000, part: 0 PIEI prepare done Cfg max: 2, cur: 1. Board id: 255. Force loop cfg DDR4 probe ddr clk to 1320MHz Load ddrfw from SD, src: 0x00014200, des: 0xfffd0000, size: 0x0000c000, part: 0 Check phy result INFO : End of initialization INFO : End of read enable training INFO : End of fine write leveling INFO : End of read dq deskew training INFO : End of MPR read delay center optimization INFO : End of Write leveling coarse delay INFO : End of write delay center optimization INFO : End of read delay center optimization INFO : End of max read latency training INFO : Training has run successfully! 1D training succeed Load ddrfw from SD, src: 0x00020200, des: 0xfffd0000, size: 0x0000c000, part: 0 Check phy result INFO : End of initialization INFO : End of 2D read delay Voltage center optimization INFO : End of 2D write delay Voltage center optimization INFO : Training has run successfully! R0_RxClkDly_Margin==82 ps 7 R0_TxDqDly_Margi==118 ps 10 R1_RxClkDly_Margin==0 ps 0 R1_TxDqDly_Margi==0 ps 0 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0001 ddr scramble enable 2D training succeed auto size-- 65535DDR cs0 size: 2048MB DDR cs1 size: 2048MB DMC_DDR_CTRL: 00600024DDR size: 3928MB cs0 DataBus test pass cs1 DataBus test pass cs0 AddrBus test pass cs1 AddrBus test pass pre test bdlr_100_average==416 bdlr_100_min==416 bdlr_100_max==416 bdlr_100_cur==416 aft test bdlr_100_average==416 bdlr_100_min==416 bdlr_100_max==416 bdlr_100_cur==416 100bdlr_step_size ps== 420 result report boot times 6Enable ddr reg access Load FIP HDR from SD, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0 Load BL3X from SD, src: 0x0006c200, des: 0x0175c000, size: 0x00094000, part: 0 Never should be here! reset... 0.0;M3 CHK:0;cm4_sp_mode 0 E30HDR MVN_1=0x00000000 MVN_2=0x00000000 [ImageG12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:800;NAND:81;SD?:0;SD:0;RE AD:0;0. bl2_stage_init 0x01 bl2_stage_init 0x81 hw id: 0x0000 - pwm id 0x01 bl2_stage_init 0xc1 bl2_stage_init 0x02 no sdio debug board detected L0:00000000 L1:00000703 L2:0000c067 L3:14000020 B2:00402000 B1:e0f83180 TE: 130992 BL2 Built : 10:47:19, Jan 14 2019. g12b g152d217 - guotai.shen@droid11-sz Board ID = 5 Set A53 clk to 24M Set A73 clk to 24M Set clk81 to 24M A53 clk: 1200 MHz A73 clk: 1200 MHz CLK81: 166.6M smccc: 0002483d DDR driver_vesion: LPDDR4_PHY_V_0_1_11 build time: Jan 14 2019 10:47:15 board id: 5 Load FIP HDR from SD, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0 fw parse done Load ddrfw from SD, src: 0x00060200, des: 0xfffd0000, size: 0x0000c000, part: 0 Load ddrfw from SD, src: 0x00038200, des: 0xfffd0000, size: 0x00004000, part: 0 PIEI prepare done Cfg max: 2, cur: 1. Board id: 255. Force loop cfg DDR4 probe ddr clk to 1320MHz Load ddrfw from SD, src: 0x00014200, des: 0xfffd0000, size: 0x0000c000, part: 0 Check phy result INFO : End of initialization INFO : End of read enable training INFO : End of fine write leveling INFO : End of read dq deskew training INFO : End of MPR read delay center optimization INFO : End of Write leveling coarse delay INFO : End of write delay center optimization INFO : End of read delay center optimization INFO : End of max read latency training INFO : Training has run successfully! 1D training succeed Load ddrfw from SD, src: 0x00020200, des: 0xfffd0000, size: 0x0000c000, part: 0 Check phy result INFO : End of initialization INFO : End of 2D read delay Voltage center optimization INFO : End of 2D write delay Voltage center optimization INFO : Training has run successfully! R0_RxClkDly_Margin==94 ps 8 R0_TxDqDly_Margi==106 ps 9 R1_RxClkDly_Margin==0 ps 0 R1_TxDqDly_Margi==0 ps 0 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0001 ddr scramble enable 2D training succeed auto size-- 65535DDR cs0 size: 2048MB DDR cs1 size: 2048MB DMC_DDR_CTRL: 00600024DDR size: 3928MB cs0 DataBus test pass cs1 DataBus test pass cs0 AddrBus test pass cs1 AddrBus test pass pre test bdlr_100_average==416 bdlr_100_min==416 bdlr_100_max==416 bdlr_100_cur==416 aft test bdlr_100_average==416 bdlr_100_min==416 bdlr_100_max==416 bdlr_100_cur==416 100bdlr_step_size ps== 420 result report boot times 7Enable ddr reg access Load FIP HDR from SD, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0 Load BL3X from SD, src: 0x0006c200, des: 0x0175c000, size: 0x00094000, part: 0 Never should be here! reset... 0.0;M3 CHK:0;cm4_sp_mode 0 E30HDR MVN_1=0x00000000 MVN_2=0x00000000 [ImagýG12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:800;NAND:81;SD?:0;SD:0;RE AD:0;0. bl2_stage_init 0x01 bl2_stage_init 0x81 hw id: 0x0000 - pwm id 0x01 bl2_stage_init 0xc1 bl2_stage_init 0x02 no sdio debug board detected L0:00000000 L1:00000703 L2:0000c067 L3:14000020 B2:00402000 B1:e0f83180 TE: 130958 BL2 Built : 10:47:19, Jan 14 2019. g12b g152d217 - guotai.shen@droid11-sz Board ID = 5 Set A53 clk to 24M Set A73 clk to 24M Set clk81 to 24M A53 clk: 1200 MHz A73 clk: 1200 MHz CLK81: 166.6M smccc: 0002481a DDR driver_vesion: LPDDR4_PHY_V_0_1_11 build time: Jan 14 2019 10:47:15 board id: 5 Load FIP HDR from SD, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0 fw parse done Load ddrfw from SD, src: 0x00060200, des: 0xfffd0000, size: 0x0000c000, part: 0 Load ddrfw from SD, src: 0x00038200, des: 0xfffd0000, size: 0x00004000, part: 0 PIEI prepare done Cfg max: 2, cur: 1. Board id: 255. Force loop cfg DDR4 probe ddr clk to 1320MHz Load ddrfw from SD, src: 0x00014200, des: 0xfffd0000, size: 0x0000c000, part: 0 Check phy result INFO : End of initialization INFO : End of read enable training INFO : End of fine write leveling INFO : End of read dq deskew training INFO : End of MPR read delay center optimization INFO : End of Write leveling coarse delay INFO : End of write delay center optimization INFO : End of read delay center optimization INFO : End of max read latency training INFO : Training has run successfully! 1D training succeed Load ddrfw from SD, src: 0x00020200, des: 0xfffd0000, size: 0x0000c000, part: 0 Check phy result INFO : End of initialization INFO : End of 2D read delay Voltage center optimization INFO : End of 2D write delay Voltage center optimization INFO : Training has run successfully! R0_RxClkDly_Margin==82 ps 7 R0_TxDqDly_Margi==106 ps 9 R1_RxClkDly_Margin==0 ps 0 R1_TxDqDly_Margi==0 ps 0 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0001 ddr scramble enable 2D training succeed auto size-- 65535DDR cs0 size: 2048MB DDR cs1 size: 2048MB DMC_DDR_CTRL: 00600024DDR size: 3928MB cs0 DataBus test pass cs1 DataBus test pass cs0 AddrBus test pass cs1 AddrBus test pass pre test bdlr_100_average==416 bdlr_100_min==416 bdlr_100_max==416 bdlr_100_cur==416 aft test bdlr_100_average==416 bdlr_100_min==416 bdlr_100_max==416 bdlr_100_cur==416 100bdlr_step_size ps== 411 result report boot times 8Enable ddr reg access Load FIP HDR from SD, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0 Load BL3X from SD, src: 0x0006c200, des: 0x0175c000, size: 0x00094000, part: 0 Never should be here! reset... 0.0;M3 CHK:0;cm4_sp_mode 0 E30HDR MVN_1=0x00000000 MVN_2=0x00000000 [ImagýG12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:800;NAND:81;SD?:0;SD:0;RE AD:0;0. bl2_stage_init 0x01 bl2_stage_init 0x81 hw id: 0x0000 - pwm id 0x01 bl2_stage_init 0xc1 bl2_stage_init 0x02 no sdio debug board detected L0:00000000 L1:00000703 L2:0000c067 L3:14000020 B2:00402000 B1:e0f83180 TE: 131001 BL2 Built : 10:47:19, Jan 14 2019. g12b g152d217 - guotai.shen@droid11-sz Board ID = 5 Set A53 clk to 24M Set A73 clk to 24M Set clk81 to 24M A53 clk: 1200 MHz A73 clk: 1200 MHz CLK81: 166.6M smccc: 00024845 DDR driver_vesion: LPDDR4_PHY_V_0_1_11 build time: Jan 14 2019 10:47:15 board id: 5 Load FIP HDR from SD, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0 fw parse done Load ddrfw from SD, src: 0x00060200, des: 0xfffd0000, size: 0x0000c000, part: 0 Load ddrfw from SD, src: 0x00038200, des: 0xfffd0000, size: 0x00004000, part: 0 PIEI prepare done Cfg max: 2, cur: 1. Board id: 255. Force loop cfg DDR4 probe ddr clk to 1320MHz Load ddrfw from SD, src: 0x00014200, des: 0xfffd0000, size: 0x0000c000, part: 0 Check phy result INFO : End of initialization INFO : End of read enable training INFO : End of fine write leveling INFO : End of read dq deskew training INFO : End of MPR read delay center optimization INFO : End of Write leveling coarse delay INFO : End of write delay center optimization INFO : End of read delay center optimization INFO : End of max read latency training INFO : Training has run successfully! 1D training succeed Load ddrfw from SD, src: 0x00020200, des: 0xfffd0000, size: 0x0000c000, part: 0 Check phy result INFO : End of initialization INFO : End of 2D read delay Voltage center optimization INFO : End of 2D write delay Voltage center optimization INFO : Training has run successfully! R0_RxClkDly_Margin==94 ps 8 R0_TxDqDly_Margi==106 ps 9 R1_RxClkDly_Margin==0 ps 0 R1_TxDqDly_Margi==0 ps 0 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0001 ddr scramble enable 2D training succeed auto size-- 65535DDR cs0 size: 2048MB DDR cs1 size: 2048MB DMC_DDR_CTRL: 00600024DDR size: 3928MB cs0 DataBus test pass cs1 DataBus test pass cs0 AddrBus test pass cs1 AddrBus test pass pre test bdlr_100_average==420 bdlr_100_min==420 bdlr_100_max==420 bdlr_100_cur==420 aft test bdlr_100_average==420 bdlr_100_min==420 bdlr_100_max==420 bdlr_100_cur==420 100bdlr_step_size ps== 416 result report boot times 9Enable ddr reg access Load FIP HDR from SD, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0 Load BL3X from SD, src: 0x0006c200, des: 0x0175c000, size: 0x00094000, part: 0 Never should be here! reset... 0.0;M3 CHK:0;cm4_sp_mode 0 E30HDR MVN_1=0x00000000 MVN_2=0x00000000 [ImagýG12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:800;NAND:81;SD?:0;SD:0;RE AD:0;0. bl2_stage_init 0x01 bl2_stage_init 0x81 hw id: 0x0000 - pwm id 0x01 bl2_stage_init 0xc1 bl2_stage_init 0x02 no sdio debug board detected L0:00000000 L1:00000703 L2:0000c067 L3:14000020 B2:00402000 B1:e0f83180 TE: 130984 BL2 Built : 10:47:19, Jan 14 2019. g12b g152d217 - guotai.shen@droid11-sz Board ID = 5 Set A53 clk to 24M Set A73 clk to 24M Set clk81 to 24M A53 clk: 1200 MHz A73 clk: 1200 MHz CLK81: 166.6M smccc: 00024835 DDR driver_vesion: LPDDR4_PHY_V_0_1_11 build time: Jan 14 2019 10:47:15 board id: 5 Load FIP HDR from SD, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0 fw parse done Load ddrfw from SD, src: 0x00060200, des: 0xfffd0000, size: 0x0000c000, part: 0 Load ddrfw from SD, src: 0x00038200, des: 0xfffd0000, size: 0x00004000, part: 0 PIEI prepare done Cfg max: 2, cur: 1. Board id: 255. Force loop cfg DDR4 probe ddr clk to 1320MHz Load ddrfw from SD, src: 0x00014200, des: 0xfffd0000, size: 0x0000c000, part: 0 Check phy result INFO : End of initialization INFO : End of read enable training INFO : End of fine write leveling INFO : End of read dq deskew training INFO : End of MPR read delay center optimization INFO : End of Write leveling coarse delay INFO : End of write delay center optimization INFO : End of read delay center optimization INFO : End of max read latency training INFO : Training has run successfully! 1D training succeed Load ddrfw from SD, src: 0x00020200, des: 0xfffd0000, size: 0x0000c000, part: 0 Check phy result INFO : End of initialization INFO : End of 2D read delay Voltage center optimization INFO : End of 2D write delay Voltage center optimization INFO : Training has run successfully! R0_RxClkDly_Margin==94 ps 8 R0_TxDqDly_Margi==106 ps 9 R1_RxClkDly_Margin==0 ps 0 R1_TxDqDly_Margi==0 ps 0 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0001 ddr scramble enable 2D training succeed auto size-- 65535DDR cs0 size: 2048MB DDR cs1 size: 2048MB DMC_DDR_CTRL: 00600024DDR size: 3928MB cs0 DataBus test pass cs1 DataBus test pass cs0 AddrBus test pass cs1 AddrBus test pass pre test bdlr_100_average==411 bdlr_100_min==411 bdlr_100_max==411 bdlr_100_cur==411 aft test bdlr_100_average==411 bdlr_100_min==411 bdlr_100_max==411 bdlr_100_cur==411 100bdlr_step_size ps== 416 result report boot times 10Enable ddr reg access Load FIP HDR from SD, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0 Load BL3X from SD, src: 0x0006c200, des: 0x0175c000, size: 0x00094000, part: 0 Never should be here! reset... 0.0;M3 CHK:0;cm4_sp_mode 0 E30HDR MVN_1=0x00000000 MVN_2=0x00000000 [ImagýG12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:800;NAND:81;SD?:0;SD:0;RE AD:0;0. bl2_stage_init 0x01 bl2_stage_init 0x81 hw id: 0x0000 - pwm id 0x01 bl2_stage_init 0xc1 bl2_stage_init 0x02 no sdio debug board detected L0:00000000 L1:00000703 L2:0000c067 L3:14000020 B2:00402000 B1:e0f83180 TE: 130966 BL2 Built : 10:47:19, Jan 14 2019. g12b g152d217 - guotai.shen@droid11-sz Board ID = 5 Set A53 clk to 24M Set A73 clk to 24M Set clk81 to 24M A53 clk: 1200 MHz A73 clk: 1200 MHz CLK81: 166.6M smccc: 00024823 DDR driver_vesion: LPDDR4_PHY_V_0_1_11 build time: Jan 14 2019 10:47:15 board id: 5 Load FIP HDR from SD, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0 fw parse done Load ddrfw from SD, src: 0x00060200, des: 0xfffd0000, size: 0x0000c000, part: 0 Load ddrfw from SD, src: 0x00038200, des: 0xfffd0000, size: 0x00004000, part: 0 PIEI prepare done Cfg max: 2, cur: 1. Board id: 255. Force loop cfg DDR4 probe ddr clk to 1320MHz Load ddrfw from SD, src: 0x00014200, des: 0xfffd0000, size: 0x0000c000, part: 0 Check phy result INFO : End of initialization INFO : End of read enable training INFO : End of fine write leveling INFO : End of read dq deskew training INFO : End of MPR read delay center optimization INFO : End of Write leveling coarse delay INFO : End of write delay center optimization INFO : End of read delay center optimization INFO : End of max read latency training INFO : Training has run successfully! 1D training succeed Load ddrfw from SD, src: 0x00020200, des: 0xfffd0000, size: 0x0000c000, part: 0 Check phy result INFO : End of initialization INFO : End of 2D read delay Voltage center optimization INFO : End of 2D write delay Voltage center optimization INFO : Training has run successfully! R0_RxClkDly_Margin==82 ps 7 R0_TxDqDly_Margi==118 ps 10 R1_RxClkDly_Margin==0 ps 0 R1_TxDqDly_Margi==0 ps 0 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0001 ddr scramble enable 2D training succeed auto size-- 65535DDR cs0 size: 2048MB DDR cs1 size: 2048MB DMC_DDR_CTRL: 00600024DDR size: 3928MB cs0 DataBus test pass cs1 DataBus test pass cs0 AddrBus test pass cs1 AddrBus test pass pre test bdlr_100_average==416 bdlr_100_min==416 bdlr_100_max==416 bdlr_100_cur==416 aft test bdlr_100_average==416 bdlr_100_min==416 bdlr_100_max==416 bdlr_100_cur==416 100bdlr_step_size ps== 411 result report boot times 11Enable ddr reg access Load FIP HDR from SD, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0 Load BL3X from SD, src: 0x0006c200, des: 0x0175c000, size: 0x00094000, part: 0 Never should be here! reset... 0.0;M3 CHK:0;cm4_sp_mode 0 E30HDR MVN_1=0x00000000 MVN_2=0x00000000 [ImageG12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:800;NAND:81;SD?:0;SD:0;RE AD:0;0. bl2_stage_init 0x01 bl2_stage_init 0x81 hw id: 0x0000 - pwm id 0x01 bl2_stage_init 0xc1 bl2_stage_init 0x02 no sdio debug board detected L0:00000000 L1:00000703 L2:0000c067 L3:14000020 B2:00402000 B1:e0f83180 TE: 130992 BL2 Built : 10:47:19, Jan 14 2019. g12b g152d217 - guotai.shen@droid11-sz Board ID = 5 Set A53 clk to 24M Set A73 clk to 24M Set clk81 to 24M A53 clk: 1200 MHz A73 clk: 1200 MHz CLK81: 166.6M smccc: 0002483d DDR driver_vesion: LPDDR4_PHY_V_0_1_11 build time: Jan 14 2019 10:47:15 board id: 5 Load FIP HDR from SD, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0 fw parse done Load ddrfw from SD, src: 0x00060200, des: 0xfffd0000, size: 0x0000c000, part: 0 Load ddrfw from SD, src: 0x00038200, des: 0xfffd0000, size: 0x00004000, part: 0 PIEI prepare done Cfg max: 2, cur: 1. Board id: 255. Force loop cfg DDR4 probe ddr clk to 1320MHz Load ddrfw from SD, src: 0x00014200, des: 0xfffd0000, size: 0x0000c000, part: 0 Check phy result INFO : End of initialization INFO : End of read enable training INFO : End of fine write leveling INFO : End of read dq deskew training INFO : End of MPR read delay center optimization INFO : End of Write leveling coarse delay INFO : End of write delay center optimization INFO : End of read delay center optimization INFO : End of max read latency training INFO : Training has run successfully! 1D training succeed Load ddrfw from SD, src: 0x00020200, des: 0xfffd0000, size: 0x0000c000, part: 0 Check phy result INFO : End of initialization INFO : End of 2D read delay Voltage center optimization INFO : End of 2D write delay Voltage center optimization INFO : Training has run successfully! R0_RxClkDly_Margin==94 ps 8 R0_TxDqDly_Margi==106 ps 9 R1_RxClkDly_Margin==0 ps 0 R1_TxDqDly_Margi==0 ps 0 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0001 ddr scramble enable 2D training succeed auto size-- 65535DDR cs0 size: 2048MB DDR cs1 size: 2048MB DMC_DDR_CTRL: 00600024DDR size: 3928MB cs0 DataBus test pass cs1 DataBus test pass cs0 AddrBus test pass cs1 AddrBus test pass pre test bdlr_100_average==420 bdlr_100_min==420 bdlr_100_max==420 bdlr_100_cur==420 aft test bdlr_100_average==420 bdlr_100_min==420 bdlr_100_max==420 bdlr_100_cur==420 100bdlr_step_size ps== 416 result report boot times 12Enable ddr reg access Load FIP HDR from SD, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0 Load BL3X from SD, src: 0x0006c200, des: 0x0175c000, size: 0x00094000, part: 0 Never should be here! reset... 0.0;M3 CHK:0;cm4_sp_mode 0 E30HDR MVN_1=0x00000000 MVN_2=0x00000000 [ImageG12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:800;NAND:81;SD?:0;SD:0;RE AD:0;0. bl2_stage_init 0x01 bl2_stage_init 0x81 hw id: 0x0000 - pwm id 0x01 bl2_stage_init 0xc1 bl2_stage_init 0x02 no sdio debug board detected L0:00000000 L1:00000703 L2:0000c067 L3:14000020 B2:00402000 B1:e0f83180 TE: 130992 BL2 Built : 10:47:19, Jan 14 2019. g12b g152d217 - guotai.shen@droid11-sz Board ID = 5 Set A53 clk to 24M Set A73 clk to 24M Set clk81 to 24M A53 clk: 1200 MHz A73 clk: 1200 MHz CLK81: 166.6M smccc: 0002483d DDR driver_vesion: LPDDR4_PHY_V_0_1_11 build time: Jan 14 2019 10:47:15 board id: 5 Load FIP HDR from SD, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0 fw parse done Load ddrfw from SD, src: 0x00060200, des: 0xfffd0000, size: 0x0000c000, part: 0 Load ddrfw from SD, src: 0x00038200, des: 0xfffd0000, size: 0x00004000, part: 0 PIEI prepare done Cfg max: 2, cur: 1. Board id: 255. Force loop cfg DDR4 probe ddr clk to 1320MHz Load ddrfw from SD, src: 0x00014200, des: 0xfffd0000, size: 0x0000c000, part: 0 Check phy result INFO : End of initialization INFO : End of read enable training INFO : End of fine write leveling INFO : End of read dq deskew training INFO : End of MPR read delay center optimization INFO : End of Write leveling coarse delay INFO : End of write delay center optimization INFO : End of read delay center optimization INFO : End of max read latency training INFO : Training has run successfully! 1D training succeed Load ddrfw from SD, src: 0x00020200, des: 0xfffd0000, size: 0x0000c000, part: 0 Check phy result INFO : End of initialization INFO : End of 2D read delay Voltage center optimization INFO : End of 2D write delay Voltage center optimization INFO : Training has run successfully! R0_RxClkDly_Margin==82 ps 7 R0_TxDqDly_Margi==106 ps 9 R1_RxClkDly_Margin==0 ps 0 R1_TxDqDly_Margi==0 ps 0 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0001 ddr scramble enable 2D training succeed auto size-- 65535DDR cs0 size: 2048MB DDR cs1 size: 2048MB DMC_DDR_CTRL: 00600024DDR size: 3928MB cs0 DataBus test pass cs1 DataBus test pass cs0 AddrBus test pass cs1 AddrBus test pass pre test bdlr_100_average==416 bdlr_100_min==416 bdlr_100_max==416 bdlr_100_cur==416 aft test bdlr_100_average==416 bdlr_100_min==416 bdlr_100_max==416 bdlr_100_cur==416 100bdlr_step_size ps== 420 result report boot times 13Enable ddr reg access Load FIP HDR from SD, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0 Load BL3X from SD, src: 0x0006c200, des: 0x0175c000, size: 0x00094000, part: 0 Never should be here! reset... 0.0;M3 CHK:0;cm4_sp_mode 0 E30HDR MVN_1=0x00000000 MVN_2=0x00000000 [ImagýG12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:800;NAND:81;SD?:0;SD:0;RE AD:0;0. bl2_stage_init 0x01 bl2_stage_init 0x81 hw id: 0x0000 - pwm id 0x01 bl2_stage_init 0xc1 bl2_stage_init 0x02 no sdio debug board detected L0:00000000 L1:00000703 L2:0000c067 L3:14000020 B2:00402000 B1:e0f83180 TE: 130975 BL2 Built : 10:47:19, Jan 14 2019. g12b g152d217 - guotai.shen@droid11-sz Board ID = 5 Set A53 clk to 24M Set A73 clk to 24M Set clk81 to 24M A53 clk: 1200 MHz A73 clk: 1200 MHz CLK81: 166.6M smccc: 0002482b DDR driver_vesion: LPDDR4_PHY_V_0_1_11 build time: Jan 14 2019 10:47:15 board id: 5 Load FIP HDR from SD, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0 fw parse done Load ddrfw from SD, src: 0x00060200, des: 0xfffd0000, size: 0x0000c000, part: 0 Load ddrfw from SD, src: 0x00038200, des: 0xfffd0000, size: 0x00004000, part: 0 PIEI prepare done Cfg max: 2, cur: 1. Board id: 255. Force loop cfg DDR4 probe ddr clk to 1320MHz Load ddrfw from SD, src: 0x00014200, des: 0xfffd0000, size: 0x0000c000, part: 0 Check phy result INFO : End of initialization INFO : End of read enable training INFO : End of fine write leveling INFO : End of read dq deskew training INFO : End of MPR read delay center optimization INFO : End of Write leveling coarse delay INFO : End of write delay center optimization INFO : End of read delay center optimization INFO : End of max read latency training INFO : Training has run successfully! 1D training succeed Load ddrfw from SD, src: 0x00020200, des: 0xfffd0000, size: 0x0000c000, part: 0 Check phy result INFO : End of initialization INFO : End of 2D read delay Voltage center optimization INFO : End of 2D write delay Voltage center optimization INFO : Training has run successfully! R0_RxClkDly_Margin==94 ps 8 R0_TxDqDly_Margi==106 ps 9 R1_RxClkDly_Margin==0 ps 0 R1_TxDqDly_Margi==0 ps 0 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0001 ddr scramble enable 2D training succeed auto size-- 65535DDR cs0 size: 2048MB DDR cs1 size: 2048MB DMC_DDR_CTRL: 00600024DDR size: 3928MB cs0 DataBus test pass cs1 DataBus test pass cs0 AddrBus test pass cs1 AddrBus test pass pre test bdlr_100_average==411 bdlr_100_min==411 bdlr_100_max==411 bdlr_100_cur==411 aft test bdlr_100_average==411 bdlr_100_min==411 bdlr_100_max==411 bdlr_100_cur==411 100bdlr_step_size ps== 425 result report boot times 14Enable ddr reg access Load FIP HDR from SD, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0 Load BL3X from SD, src: 0x0006c200, des: 0x0175c000, size: 0x00094000, part: 0 Never should be here! reset... 0.0;M3 CHK:0;cm4_sp_mode 0 E30HDR MVN_1=0x00000000 MVN_2=0x00000000 [ImageG12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:800;NAND:81;SD?:0;SD:0;RE AD:0;0. bl2_stage_init 0x01 bl2_stage_init 0x81 hw id: 0x0000 - pwm id 0x01 bl2_stage_init 0xc1 bl2_stage_init 0x02 no sdio debug board detected L0:00000000 L1:00000703 L2:0000c067 L3:14000020 B2:00402000 B1:e0f83180 TE: 130992 BL2 Built : 10:47:19, Jan 14 2019. g12b g152d217 - guotai.shen@droid11-sz Board ID = 5 Set A53 clk to 24M Set A73 clk to 24M Set clk81 to 24M A53 clk: 1200 MHz A73 clk: 1200 MHz CLK81: 166.6M smccc: 0002483d DDR driver_vesion: LPDDR4_PHY_V_0_1_11 build time: Jan 14 2019 10:47:15 board id: 5 Load FIP HDR from SD, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0 fw parse done Load ddrfw from SD, src: 0x00060200, des: 0xfffd0000, size: 0x0000c000, part: 0 Load ddrfw from SD, src: 0x00038200, des: 0xfffd0000, size: 0x00004000, part: 0 PIEI prepare done Cfg max: 2, cur: 1. Board id: 255. Force loop cfg DDR4 probe ddr clk to 1320MHz Load ddrfw from SD, src: 0x00014200, des: 0xfffd0000, size: 0x0000c000, part: 0 Check phy result INFO : End of initialization INFO : End of read enable training INFO : End of fine write leveling INFO : End of read dq deskew training INFO : End of MPR read delay center optimization INFO : End of Write leveling coarse delay INFO : End of write delay center optimization INFO : End of read delay center optimization INFO : End of max read latency training INFO : Training has run successfully! 1D training succeed Load ddrfw from SD, src: 0x00020200, des: 0xfffd0000, size: 0x0000c000, part: 0 Check phy result INFO : End of initialization INFO : End of 2D read delay Voltage center optimization INFO : End of 2D write delay Voltage center optimization INFO : Training has run successfully! R0_RxClkDly_Margin==94 ps 8 R0_TxDqDly_Margi==118 ps 10 R1_RxClkDly_Margin==0 ps 0 R1_TxDqDly_Margi==0 ps 0 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0001 ddr scramble enable 2D training succeed auto size-- 65535DDR cs0 size: 2048MB DDR cs1 size: 2048MB DMC_DDR_CTRL: 00600024DDR size: 3928MB cs0 DataBus test pass cs1 DataBus test pass cs0 AddrBus test pass cs1 AddrBus test pass pre test bdlr_100_average==420 bdlr_100_min==420 bdlr_100_max==420 bdlr_100_cur==420 aft test bdlr_100_average==420 bdlr_100_min==420 bdlr_100_max==420 bdlr_100_cur==420 100bdlr_step_size ps== 425 result report boot times 15Enable ddr reg access Load FIP HDR from SD, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0 Load BL3X from SD, src: 0x0006c200, des: 0x0175c000, size: 0x00094000, part: 0 Never should be here! reset... 0.0;M3 CHK:0;cm4_sp_mode 0 E30HDR MVN_1=0x00000000 MVN_2=0x00000000 [ImageG12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:800;NAND:81;SD?:0;SD:0;RE AD:0;0. bl2_stage_init 0x01 bl2_stage_init 0x81 hw id: 0x0000 - pwm id 0x01 bl2_stage_init 0xc1 bl2_stage_init 0x02 no sdio debug board detected L0:00000000 L1:00000703 L2:0000c067 L3:14000020 B2:00402000 B1:e0f83180 TE: 131001 BL2 Built : 10:47:19, Jan 14 2019. g12b g152d217 - guotai.shen@droid11-sz Board ID = 5 Set A53 clk to 24M Set A73 clk to 24M Set clk81 to 24M A53 clk: 1200 MHz A73 clk: 1200 MHz CLK81: 166.6M smccc: 00024845 DDR driver_vesion: LPDDR4_PHY_V_0_1_11 build time: Jan 14 2019 10:47:15 board id: 5 Load FIP HDR from SD, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0 fw parse done Load ddrfw from SD, src: 0x00060200, des: 0xfffd0000, size: 0x0000c000, part: 0 Load ddrfw from SD, src: 0x00038200, des: 0xfffd0000, size: 0x00004000, part: 0 PIEI prepare done Cfg max: 2, cur: 1. Board id: 255. Force loop cfg DDR4 probe ddr clk to 1320MHz Load ddrfw from SD, src: 0x00014200, des: 0xfffd0000, size: 0x0000c000, part: 0 Check phy result INFO : End of initialization INFO : End of read enable training INFO : End of fine write leveling INFO : End of read dq deskew training INFO : End of MPR read delay center optimization INFO : End of Write leveling coarse delay INFO : End of write delay center optimization INFO : End of read delay center optimization INFO : End of max read latency training INFO : Training has run successfully! 1D training succeed Load ddrfw from SD, src: 0x00020200, des: 0xfffd0000, size: 0x0000c000, part: 0 Check phy result INFO : End of initialization ý